drivers/net/fm10k/fm10k_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2013-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <rte_ethdev.h>
  35 #include <rte_malloc.h>
  36 #include <rte_memzone.h>
  37 #include <rte_string_fns.h>
  38 #include <rte_dev.h>
  39 #include <rte_spinlock.h>
  40 #include <rte_kvargs.h>
  41
  42 #include "fm10k.h"
  43 #include "base/fm10k_api.h"
  44
  45 /* Default delay to acquire mailbox lock */
  46 #define FM10K_MBXLOCK_DELAY_US 20
  47 #define UINT64_LOWER_32BITS_MASK 0x00000000ffffffffULL
  48
  49 #define MAIN_VSI_POOL_NUMBER 0
  50
  51 /* Max try times to acquire switch status */
  52 #define MAX_QUERY_SWITCH_STATE_TIMES 10
  53 /* Wait interval to get switch status */
  54 #define WAIT_SWITCH_MSG_US    100000
  55 /* A period of quiescence for switch */
  56 #define FM10K_SWITCH_QUIESCE_US 10000
  57 /* Number of chars per uint32 type */
  58 #define CHARS_PER_UINT32 (sizeof(uint32_t))
  59 #define BIT_MASK_PER_UINT32 ((1 << CHARS_PER_UINT32) - 1)
  60
  61 /* default 1:1 map from queue ID to interrupt vector ID */
  62 #define Q2V(pci_dev, queue_id) ((pci_dev)->intr_handle.intr_vec[queue_id])
  63
  64 /* First 64 Logical ports for PF/VMDQ, second 64 for Flow director */
  65 #define MAX_LPORT_NUM    128
  66 #define GLORT_FD_Q_BASE  0x40
  67 #define GLORT_PF_MASK    0xFFC0
  68 #define GLORT_FD_MASK    GLORT_PF_MASK
  69 #define GLORT_FD_INDEX   GLORT_FD_Q_BASE
  70
  71 static void fm10k_close_mbx_service(struct fm10k_hw *hw);
  72 static void fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev);
  73 static void fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev);
  74 static void fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev);
  75 static void fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev);
  76 static inline int fm10k_glort_valid(struct fm10k_hw *hw);
  77 static int
  78 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
  79 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
  80         const u8 *mac, bool add, uint32_t pool);
  81 static void fm10k_tx_queue_release(void *queue);
  82 static void fm10k_rx_queue_release(void *queue);
  83 static void fm10k_set_rx_function(struct rte_eth_dev *dev);
  84 static void fm10k_set_tx_function(struct rte_eth_dev *dev);
  85 static int fm10k_check_ftag(struct rte_devargs *devargs);
  86
  87 struct fm10k_xstats_name_off {
  88         char name[RTE_ETH_XSTATS_NAME_SIZE];
  89         unsigned offset;
  90 };
  91
  92 struct fm10k_xstats_name_off fm10k_hw_stats_strings[] = {
  93         {"completion_timeout_count", offsetof(struct fm10k_hw_stats, timeout)},
  94         {"unsupported_requests_count", offsetof(struct fm10k_hw_stats, ur)},
  95         {"completer_abort_count", offsetof(struct fm10k_hw_stats, ca)},
  96         {"unsupported_message_count", offsetof(struct fm10k_hw_stats, um)},
  97         {"checksum_error_count", offsetof(struct fm10k_hw_stats, xec)},
  98         {"vlan_dropped", offsetof(struct fm10k_hw_stats, vlan_drop)},
  99         {"loopback_dropped", offsetof(struct fm10k_hw_stats, loopback_drop)},
 100         {"rx_mbuf_allocation_errors", offsetof(struct fm10k_hw_stats,
 101                 nodesc_drop)},
 102 };
 103
 104 #define FM10K_NB_HW_XSTATS (sizeof(fm10k_hw_stats_strings) / \
 105                 sizeof(fm10k_hw_stats_strings[0]))
 106
 107 struct fm10k_xstats_name_off fm10k_hw_stats_rx_q_strings[] = {
 108         {"packets", offsetof(struct fm10k_hw_stats_q, rx_packets)},
 109         {"bytes", offsetof(struct fm10k_hw_stats_q, rx_bytes)},
 110         {"dropped", offsetof(struct fm10k_hw_stats_q, rx_drops)},
 111 };
 112
 113 #define FM10K_NB_RX_Q_XSTATS (sizeof(fm10k_hw_stats_rx_q_strings) / \
 114                 sizeof(fm10k_hw_stats_rx_q_strings[0]))
 115
 116 struct fm10k_xstats_name_off fm10k_hw_stats_tx_q_strings[] = {
 117         {"packets", offsetof(struct fm10k_hw_stats_q, tx_packets)},
 118         {"bytes", offsetof(struct fm10k_hw_stats_q, tx_bytes)},
 119 };
 120
 121 #define FM10K_NB_TX_Q_XSTATS (sizeof(fm10k_hw_stats_tx_q_strings) / \
 122                 sizeof(fm10k_hw_stats_tx_q_strings[0]))
 123
 124 #define FM10K_NB_XSTATS (FM10K_NB_HW_XSTATS + FM10K_MAX_QUEUES_PF * \
 125                 (FM10K_NB_RX_Q_XSTATS + FM10K_NB_TX_Q_XSTATS))
 126 static int
 127 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 128
 129 static void
 130 fm10k_mbx_initlock(struct fm10k_hw *hw)
 131 {
 132         rte_spinlock_init(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
 133 }
 134
 135 static void
 136 fm10k_mbx_lock(struct fm10k_hw *hw)
 137 {
 138         while (!rte_spinlock_trylock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back)))
 139                 rte_delay_us(FM10K_MBXLOCK_DELAY_US);
 140 }
 141
 142 static void
 143 fm10k_mbx_unlock(struct fm10k_hw *hw)
 144 {
 145         rte_spinlock_unlock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
 146 }
 147
 148 /* Stubs needed for linkage when vPMD is disabled */
 149 int __attribute__((weak))
 150 fm10k_rx_vec_condition_check(__rte_unused struct rte_eth_dev *dev)
 151 {
 152         return -1;
 153 }
 154
 155 uint16_t __attribute__((weak))
 156 fm10k_recv_pkts_vec(
 157         __rte_unused void *rx_queue,
 158         __rte_unused struct rte_mbuf **rx_pkts,
 159         __rte_unused uint16_t nb_pkts)
 160 {
 161         return 0;
 162 }
 163
 164 uint16_t __attribute__((weak))
 165 fm10k_recv_scattered_pkts_vec(
 166                 __rte_unused void *rx_queue,
 167                 __rte_unused struct rte_mbuf **rx_pkts,
 168                 __rte_unused uint16_t nb_pkts)
 169 {
 170         return 0;
 171 }
 172
 173 int __attribute__((weak))
 174 fm10k_rxq_vec_setup(__rte_unused struct fm10k_rx_queue *rxq)
 175
 176 {
 177         return -1;
 178 }
 179
 180 void __attribute__((weak))
 181 fm10k_rx_queue_release_mbufs_vec(
 182                 __rte_unused struct fm10k_rx_queue *rxq)
 183 {
 184         return;
 185 }
 186
 187 void __attribute__((weak))
 188 fm10k_txq_vec_setup(__rte_unused struct fm10k_tx_queue *txq)
 189 {
 190         return;
 191 }
 192
 193 int __attribute__((weak))
 194 fm10k_tx_vec_condition_check(__rte_unused struct fm10k_tx_queue *txq)
 195 {
 196         return -1;
 197 }
 198
 199 uint16_t __attribute__((weak))
 200 fm10k_xmit_pkts_vec(__rte_unused void *tx_queue,
 201                 __rte_unused struct rte_mbuf **tx_pkts,
 202                 __rte_unused uint16_t nb_pkts)
 203 {
 204         return 0;
 205 }
 206
 207 /*
 208  * reset queue to initial state, allocate software buffers used when starting
 209  * device.
 210  * return 0 on success
 211  * return -ENOMEM if buffers cannot be allocated
 212  * return -EINVAL if buffers do not satisfy alignment condition
 213  */
 214 static inline int
 215 rx_queue_reset(struct fm10k_rx_queue *q)
 216 {
 217         static const union fm10k_rx_desc zero = {{0} };
 218         uint64_t dma_addr;
 219         int i, diag;
 220         PMD_INIT_FUNC_TRACE();
 221
 222         diag = rte_mempool_get_bulk(q->mp, (void **)q->sw_ring, q->nb_desc);
 223         if (diag != 0)
 224                 return -ENOMEM;
 225
 226         for (i = 0; i < q->nb_desc; ++i) {
 227                 fm10k_pktmbuf_reset(q->sw_ring[i], q->port_id);
 228                 if (!fm10k_addr_alignment_valid(q->sw_ring[i])) {
 229                         rte_mempool_put_bulk(q->mp, (void **)q->sw_ring,
 230                                                 q->nb_desc);
 231                         return -EINVAL;
 232                 }
 233                 dma_addr = MBUF_DMA_ADDR_DEFAULT(q->sw_ring[i]);
 234                 q->hw_ring[i].q.pkt_addr = dma_addr;
 235                 q->hw_ring[i].q.hdr_addr = dma_addr;
 236         }
 237
 238         /* initialize extra software ring entries. Space for these extra
 239          * entries is always allocated.
 240          */
 241         memset(&q->fake_mbuf, 0x0, sizeof(q->fake_mbuf));
 242         for (i = 0; i < q->nb_fake_desc; ++i) {
 243                 q->sw_ring[q->nb_desc + i] = &q->fake_mbuf;
 244                 q->hw_ring[q->nb_desc + i] = zero;
 245         }
 246
 247         q->next_dd = 0;
 248         q->next_alloc = 0;
 249         q->next_trigger = q->alloc_thresh - 1;
 250         FM10K_PCI_REG_WRITE(q->tail_ptr, q->nb_desc - 1);
 251         q->rxrearm_start = 0;
 252         q->rxrearm_nb = 0;
 253
 254         return 0;
 255 }
 256
 257 /*
 258  * clean queue, descriptor rings, free software buffers used when stopping
 259  * device.
 260  */
 261 static inline void
 262 rx_queue_clean(struct fm10k_rx_queue *q)
 263 {
 264         union fm10k_rx_desc zero = {.q = {0, 0, 0, 0} };
 265         uint32_t i;
 266         PMD_INIT_FUNC_TRACE();
 267
 268         /* zero descriptor rings */
 269         for (i = 0; i < q->nb_desc; ++i)
 270                 q->hw_ring[i] = zero;
 271
 272         /* zero faked descriptors */
 273         for (i = 0; i < q->nb_fake_desc; ++i)
 274                 q->hw_ring[q->nb_desc + i] = zero;
 275
 276         /* vPMD driver has a different way of releasing mbufs. */
 277         if (q->rx_using_sse) {
 278                 fm10k_rx_queue_release_mbufs_vec(q);
 279                 return;
 280         }
 281
 282         /* free software buffers */
 283         for (i = 0; i < q->nb_desc; ++i) {
 284                 if (q->sw_ring[i]) {
 285                         rte_pktmbuf_free_seg(q->sw_ring[i]);
 286                         q->sw_ring[i] = NULL;
 287                 }
 288         }
 289 }
 290
 291 /*
 292  * free all queue memory used when releasing the queue (i.e. configure)
 293  */
 294 static inline void
 295 rx_queue_free(struct fm10k_rx_queue *q)
 296 {
 297         PMD_INIT_FUNC_TRACE();
 298         if (q) {
 299                 PMD_INIT_LOG(DEBUG, "Freeing rx queue %p", q);
 300                 rx_queue_clean(q);
 301                 if (q->sw_ring) {
 302                         rte_free(q->sw_ring);
 303                         q->sw_ring = NULL;
 304                 }
 305                 rte_free(q);
 306                 q = NULL;
 307         }
 308 }
 309
 310 /*
 311  * disable RX queue, wait unitl HW finished necessary flush operation
 312  */
 313 static inline int
 314 rx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
 315 {
 316         uint32_t reg, i;
 317
 318         reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
 319         FM10K_WRITE_REG(hw, FM10K_RXQCTL(qnum),
 320                         reg & ~FM10K_RXQCTL_ENABLE);
 321
 322         /* Wait 100us at most */
 323         for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
 324                 rte_delay_us(1);
 325                 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
 326                 if (!(reg & FM10K_RXQCTL_ENABLE))
 327                         break;
 328         }
 329
 330         if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
 331                 return -1;
 332
 333         return 0;
 334 }
 335
 336 /*
 337  * reset queue to initial state, allocate software buffers used when starting
 338  * device
 339  */
 340 static inline void
 341 tx_queue_reset(struct fm10k_tx_queue *q)
 342 {
 343         PMD_INIT_FUNC_TRACE();
 344         q->last_free = 0;
 345         q->next_free = 0;
 346         q->nb_used = 0;
 347         q->nb_free = q->nb_desc - 1;
 348         fifo_reset(&q->rs_tracker, (q->nb_desc + 1) / q->rs_thresh);
 349         FM10K_PCI_REG_WRITE(q->tail_ptr, 0);
 350 }
 351
 352 /*
 353  * clean queue, descriptor rings, free software buffers used when stopping
 354  * device
 355  */
 356 static inline void
 357 tx_queue_clean(struct fm10k_tx_queue *q)
 358 {
 359         struct fm10k_tx_desc zero = {0, 0, 0, 0, 0, 0};
 360         uint32_t i;
 361         PMD_INIT_FUNC_TRACE();
 362
 363         /* zero descriptor rings */
 364         for (i = 0; i < q->nb_desc; ++i)
 365                 q->hw_ring[i] = zero;
 366
 367         /* free software buffers */
 368         for (i = 0; i < q->nb_desc; ++i) {
 369                 if (q->sw_ring[i]) {
 370                         rte_pktmbuf_free_seg(q->sw_ring[i]);
 371                         q->sw_ring[i] = NULL;
 372                 }
 373         }
 374 }
 375
 376 /*
 377  * free all queue memory used when releasing the queue (i.e. configure)
 378  */
 379 static inline void
 380 tx_queue_free(struct fm10k_tx_queue *q)
 381 {
 382         PMD_INIT_FUNC_TRACE();
 383         if (q) {
 384                 PMD_INIT_LOG(DEBUG, "Freeing tx queue %p", q);
 385                 tx_queue_clean(q);
 386                 if (q->rs_tracker.list) {
 387                         rte_free(q->rs_tracker.list);
 388                         q->rs_tracker.list = NULL;
 389                 }
 390                 if (q->sw_ring) {
 391                         rte_free(q->sw_ring);
 392                         q->sw_ring = NULL;
 393                 }
 394                 rte_free(q);
 395                 q = NULL;
 396         }
 397 }
 398
 399 /*
 400  * disable TX queue, wait unitl HW finished necessary flush operation
 401  */
 402 static inline int
 403 tx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
 404 {
 405         uint32_t reg, i;
 406
 407         reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
 408         FM10K_WRITE_REG(hw, FM10K_TXDCTL(qnum),
 409                         reg & ~FM10K_TXDCTL_ENABLE);
 410
 411         /* Wait 100us at most */
 412         for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
 413                 rte_delay_us(1);
 414                 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
 415                 if (!(reg & FM10K_TXDCTL_ENABLE))
 416                         break;
 417         }
 418
 419         if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
 420                 return -1;
 421
 422         return 0;
 423 }
 424
 425 static int
 426 fm10k_check_mq_mode(struct rte_eth_dev *dev)
 427 {
 428         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 429         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 430         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 431         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 432
 433         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 434
 435         if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
 436                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
 437                 return -EINVAL;
 438         }
 439
 440         if (!(rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG))
 441                 return 0;
 442
 443         if (hw->mac.type == fm10k_mac_vf) {
 444                 PMD_INIT_LOG(ERR, "VMDQ mode is not supported in VF.");
 445                 return -EINVAL;
 446         }
 447
 448         /* Check VMDQ queue pool number */
 449         if (vmdq_conf->nb_queue_pools >
 450                         sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT ||
 451                         vmdq_conf->nb_queue_pools > nb_rx_q) {
 452                 PMD_INIT_LOG(ERR, "Too many of queue pools: %d",
 453                         vmdq_conf->nb_queue_pools);
 454                 return -EINVAL;
 455         }
 456
 457         return 0;
 458 }
 459
 460 static const struct fm10k_txq_ops def_txq_ops = {
 461         .reset = tx_queue_reset,
 462 };
 463
 464 static int
 465 fm10k_dev_configure(struct rte_eth_dev *dev)
 466 {
 467         int ret;
 468
 469         PMD_INIT_FUNC_TRACE();
 470
 471         if (dev->data->dev_conf.rxmode.hw_strip_crc == 0)
 472                 PMD_INIT_LOG(WARNING, "fm10k always strip CRC");
 473         /* multipe queue mode checking */
 474         ret  = fm10k_check_mq_mode(dev);
 475         if (ret != 0) {
 476                 PMD_DRV_LOG(ERR, "fm10k_check_mq_mode fails with %d.",
 477                             ret);
 478                 return ret;
 479         }
 480
 481         return 0;
 482 }
 483
 484 /* fls = find last set bit = 32 minus the number of leading zeros */
 485 #ifndef fls
 486 #define fls(x) (((x) == 0) ? 0 : (32 - __builtin_clz((x))))
 487 #endif
 488
 489 static void
 490 fm10k_dev_vmdq_rx_configure(struct rte_eth_dev *dev)
 491 {
 492         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 493         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 494         uint32_t i;
 495
 496         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 497
 498         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
 499                 if (!vmdq_conf->pool_map[i].pools)
 500                         continue;
 501                 fm10k_mbx_lock(hw);
 502                 fm10k_update_vlan(hw, vmdq_conf->pool_map[i].vlan_id, 0, true);
 503                 fm10k_mbx_unlock(hw);
 504         }
 505 }
 506
 507 static void
 508 fm10k_dev_pf_main_vsi_reset(struct rte_eth_dev *dev)
 509 {
 510         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 511
 512         /* Add default mac address */
 513         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
 514                 MAIN_VSI_POOL_NUMBER);
 515 }
 516
 517 static void
 518 fm10k_dev_rss_configure(struct rte_eth_dev *dev)
 519 {
 520         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 521         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 522         uint32_t mrqc, *key, i, reta, j;
 523         uint64_t hf;
 524
 525 #define RSS_KEY_SIZE 40
 526         static uint8_t rss_intel_key[RSS_KEY_SIZE] = {
 527                 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
 528                 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
 529                 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
 530                 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
 531                 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
 532         };
 533
 534         if (dev->data->nb_rx_queues == 1 ||
 535             dev_conf->rxmode.mq_mode != ETH_MQ_RX_RSS ||
 536             dev_conf->rx_adv_conf.rss_conf.rss_hf == 0) {
 537                 FM10K_WRITE_REG(hw, FM10K_MRQC(0), 0);
 538                 return;
 539         }
 540
 541         /* random key is rss_intel_key (default) or user provided (rss_key) */
 542         if (dev_conf->rx_adv_conf.rss_conf.rss_key == NULL)
 543                 key = (uint32_t *)rss_intel_key;
 544         else
 545                 key = (uint32_t *)dev_conf->rx_adv_conf.rss_conf.rss_key;
 546
 547         /* Now fill our hash function seeds, 4 bytes at a time */
 548         for (i = 0; i < RSS_KEY_SIZE / sizeof(*key); ++i)
 549                 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
 550
 551         /*
 552          * Fill in redirection table
 553          * The byte-swap is needed because NIC registers are in
 554          * little-endian order.
 555          */
 556         reta = 0;
 557         for (i = 0, j = 0; i < FM10K_MAX_RSS_INDICES; i++, j++) {
 558                 if (j == dev->data->nb_rx_queues)
 559                         j = 0;
 560                 reta = (reta << CHAR_BIT) | j;
 561                 if ((i & 3) == 3)
 562                         FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2),
 563                                         rte_bswap32(reta));
 564         }
 565
 566         /*
 567          * Generate RSS hash based on packet types, TCP/UDP
 568          * port numbers and/or IPv4/v6 src and dst addresses
 569          */
 570         hf = dev_conf->rx_adv_conf.rss_conf.rss_hf;
 571         mrqc = 0;
 572         mrqc |= (hf & ETH_RSS_IPV4)              ? FM10K_MRQC_IPV4     : 0;
 573         mrqc |= (hf & ETH_RSS_IPV6)              ? FM10K_MRQC_IPV6     : 0;
 574         mrqc |= (hf & ETH_RSS_IPV6_EX)           ? FM10K_MRQC_IPV6     : 0;
 575         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? FM10K_MRQC_TCP_IPV4 : 0;
 576         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? FM10K_MRQC_TCP_IPV6 : 0;
 577         mrqc |= (hf & ETH_RSS_IPV6_TCP_EX)       ? FM10K_MRQC_TCP_IPV6 : 0;
 578         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? FM10K_MRQC_UDP_IPV4 : 0;
 579         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? FM10K_MRQC_UDP_IPV6 : 0;
 580         mrqc |= (hf & ETH_RSS_IPV6_UDP_EX)       ? FM10K_MRQC_UDP_IPV6 : 0;
 581
 582         if (mrqc == 0) {
 583                 PMD_INIT_LOG(ERR, "Specified RSS mode 0x%"PRIx64"is not"
 584                         "supported", hf);
 585                 return;
 586         }
 587
 588         FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
 589 }
 590
 591 static void
 592 fm10k_dev_logic_port_update(struct rte_eth_dev *dev, uint16_t nb_lport_new)
 593 {
 594         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 595         uint32_t i;
 596
 597         for (i = 0; i < nb_lport_new; i++) {
 598                 /* Set unicast mode by default. App can change
 599                  * to other mode in other API func.
 600                  */
 601                 fm10k_mbx_lock(hw);
 602                 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map + i,
 603                         FM10K_XCAST_MODE_NONE);
 604                 fm10k_mbx_unlock(hw);
 605         }
 606 }
 607
 608 static void
 609 fm10k_dev_mq_rx_configure(struct rte_eth_dev *dev)
 610 {
 611         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 612         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 613         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 614         struct fm10k_macvlan_filter_info *macvlan;
 615         uint16_t nb_queue_pools = 0; /* pool number in configuration */
 616         uint16_t nb_lport_new;
 617
 618         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
 619         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 620
 621         fm10k_dev_rss_configure(dev);
 622
 623         /* only PF supports VMDQ */
 624         if (hw->mac.type != fm10k_mac_pf)
 625                 return;
 626
 627         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
 628                 nb_queue_pools = vmdq_conf->nb_queue_pools;
 629
 630         /* no pool number change, no need to update logic port and VLAN/MAC */
 631         if (macvlan->nb_queue_pools == nb_queue_pools)
 632                 return;
 633
 634         nb_lport_new = nb_queue_pools ? nb_queue_pools : 1;
 635         fm10k_dev_logic_port_update(dev, nb_lport_new);
 636
 637         /* reset MAC/VLAN as it's based on VMDQ or PF main VSI */
 638         memset(dev->data->mac_addrs, 0,
 639                 ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM);
 640         ether_addr_copy((const struct ether_addr *)hw->mac.addr,
 641                 &dev->data->mac_addrs[0]);
 642         memset(macvlan, 0, sizeof(*macvlan));
 643         macvlan->nb_queue_pools = nb_queue_pools;
 644
 645         if (nb_queue_pools)
 646                 fm10k_dev_vmdq_rx_configure(dev);
 647         else
 648                 fm10k_dev_pf_main_vsi_reset(dev);
 649 }
 650
 651 static int
 652 fm10k_dev_tx_init(struct rte_eth_dev *dev)
 653 {
 654         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 655         int i, ret;
 656         struct fm10k_tx_queue *txq;
 657         uint64_t base_addr;
 658         uint32_t size;
 659
 660         /* Disable TXINT to avoid possible interrupt */
 661         for (i = 0; i < hw->mac.max_queues; i++)
 662                 FM10K_WRITE_REG(hw, FM10K_TXINT(i),
 663                                 3 << FM10K_TXINT_TIMER_SHIFT);
 664
 665         /* Setup TX queue */
 666         for (i = 0; i < dev->data->nb_tx_queues; ++i) {
 667                 txq = dev->data->tx_queues[i];
 668                 base_addr = txq->hw_ring_phys_addr;
 669                 size = txq->nb_desc * sizeof(struct fm10k_tx_desc);
 670
 671                 /* disable queue to avoid issues while updating state */
 672                 ret = tx_queue_disable(hw, i);
 673                 if (ret) {
 674                         PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
 675                         return -1;
 676                 }
 677                 /* Enable use of FTAG bit in TX descriptor, PFVTCTL
 678                  * register is read-only for VF.
 679                  */
 680                 if (fm10k_check_ftag(dev->pci_dev->device.devargs)) {
 681                         if (hw->mac.type == fm10k_mac_pf) {
 682                                 FM10K_WRITE_REG(hw, FM10K_PFVTCTL(i),
 683                                                 FM10K_PFVTCTL_FTAG_DESC_ENABLE);
 684                                 PMD_INIT_LOG(DEBUG, "FTAG mode is enabled");
 685                         } else {
 686                                 PMD_INIT_LOG(ERR, "VF FTAG is not supported.");
 687                                 return -ENOTSUP;
 688                         }
 689                 }
 690
 691                 /* set location and size for descriptor ring */
 692                 FM10K_WRITE_REG(hw, FM10K_TDBAL(i),
 693                                 base_addr & UINT64_LOWER_32BITS_MASK);
 694                 FM10K_WRITE_REG(hw, FM10K_TDBAH(i),
 695                                 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
 696                 FM10K_WRITE_REG(hw, FM10K_TDLEN(i), size);
 697
 698                 /* assign default SGLORT for each TX queue by PF */
 699                 if (hw->mac.type == fm10k_mac_pf)
 700                         FM10K_WRITE_REG(hw, FM10K_TX_SGLORT(i), hw->mac.dglort_map);
 701         }
 702
 703         /* set up vector or scalar TX function as appropriate */
 704         fm10k_set_tx_function(dev);
 705
 706         return 0;
 707 }
 708
 709 static int
 710 fm10k_dev_rx_init(struct rte_eth_dev *dev)
 711 {
 712         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 713         struct fm10k_macvlan_filter_info *macvlan;
 714         struct rte_pci_device *pdev = dev->pci_dev;
 715         struct rte_intr_handle *intr_handle = &pdev->intr_handle;
 716         int i, ret;
 717         struct fm10k_rx_queue *rxq;
 718         uint64_t base_addr;
 719         uint32_t size;
 720         uint32_t rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
 721         uint32_t logic_port = hw->mac.dglort_map;
 722         uint16_t buf_size;
 723         uint16_t queue_stride = 0;
 724
 725         /* enable RXINT for interrupt mode */
 726         i = 0;
 727         if (rte_intr_dp_is_en(intr_handle)) {
 728                 for (; i < dev->data->nb_rx_queues; i++) {
 729                         FM10K_WRITE_REG(hw, FM10K_RXINT(i), Q2V(pdev, i));
 730                         if (hw->mac.type == fm10k_mac_pf)
 731                                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, i)),
 732                                         FM10K_ITR_AUTOMASK |
 733                                         FM10K_ITR_MASK_CLEAR);
 734                         else
 735                                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, i)),
 736                                         FM10K_ITR_AUTOMASK |
 737                                         FM10K_ITR_MASK_CLEAR);
 738                 }
 739         }
 740         /* Disable other RXINT to avoid possible interrupt */
 741         for (; i < hw->mac.max_queues; i++)
 742                 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
 743                         3 << FM10K_RXINT_TIMER_SHIFT);
 744
 745         /* Setup RX queues */
 746         for (i = 0; i < dev->data->nb_rx_queues; ++i) {
 747                 rxq = dev->data->rx_queues[i];
 748                 base_addr = rxq->hw_ring_phys_addr;
 749                 size = rxq->nb_desc * sizeof(union fm10k_rx_desc);
 750
 751                 /* disable queue to avoid issues while updating state */
 752                 ret = rx_queue_disable(hw, i);
 753                 if (ret) {
 754                         PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
 755                         return -1;
 756                 }
 757
 758                 /* Setup the Base and Length of the Rx Descriptor Ring */
 759                 FM10K_WRITE_REG(hw, FM10K_RDBAL(i),
 760                                 base_addr & UINT64_LOWER_32BITS_MASK);
 761                 FM10K_WRITE_REG(hw, FM10K_RDBAH(i),
 762                                 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
 763                 FM10K_WRITE_REG(hw, FM10K_RDLEN(i), size);
 764
 765                 /* Configure the Rx buffer size for one buff without split */
 766                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 767                         RTE_PKTMBUF_HEADROOM);
 768                 /* As RX buffer is aligned to 512B within mbuf, some bytes are
 769                  * reserved for this purpose, and the worst case could be 511B.
 770                  * But SRR reg assumes all buffers have the same size. In order
 771                  * to fill the gap, we'll have to consider the worst case and
 772                  * assume 512B is reserved. If we don't do so, it's possible
 773                  * for HW to overwrite data to next mbuf.
 774                  */
 775                 buf_size -= FM10K_RX_DATABUF_ALIGN;
 776
 777                 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i),
 778                                 (buf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT) |
 779                                 FM10K_SRRCTL_LOOPBACK_SUPPRESS);
 780
 781                 /* It adds dual VLAN length for supporting dual VLAN */
 782                 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
 783                                 2 * FM10K_VLAN_TAG_SIZE) > buf_size ||
 784                         dev->data->dev_conf.rxmode.enable_scatter) {
 785                         uint32_t reg;
 786                         dev->data->scattered_rx = 1;
 787                         reg = FM10K_READ_REG(hw, FM10K_SRRCTL(i));
 788                         reg |= FM10K_SRRCTL_BUFFER_CHAINING_EN;
 789                         FM10K_WRITE_REG(hw, FM10K_SRRCTL(i), reg);
 790                 }
 791
 792                 /* Enable drop on empty, it's RO for VF */
 793                 if (hw->mac.type == fm10k_mac_pf && rxq->drop_en)
 794                         rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
 795
 796                 FM10K_WRITE_REG(hw, FM10K_RXDCTL(i), rxdctl);
 797                 FM10K_WRITE_FLUSH(hw);
 798         }
 799
 800         /* Configure VMDQ/RSS if applicable */
 801         fm10k_dev_mq_rx_configure(dev);
 802
 803         /* Decide the best RX function */
 804         fm10k_set_rx_function(dev);
 805
 806         /* update RX_SGLORT for loopback suppress*/
 807         if (hw->mac.type != fm10k_mac_pf)
 808                 return 0;
 809         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
 810         if (macvlan->nb_queue_pools)
 811                 queue_stride = dev->data->nb_rx_queues / macvlan->nb_queue_pools;
 812         for (i = 0; i < dev->data->nb_rx_queues; ++i) {
 813                 if (i && queue_stride && !(i % queue_stride))
 814                         logic_port++;
 815                 FM10K_WRITE_REG(hw, FM10K_RX_SGLORT(i), logic_port);
 816         }
 817
 818         return 0;
 819 }
 820
 821 static int
 822 fm10k_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 823 {
 824         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 825         int err = -1;
 826         uint32_t reg;
 827         struct fm10k_rx_queue *rxq;
 828
 829         PMD_INIT_FUNC_TRACE();
 830
 831         if (rx_queue_id < dev->data->nb_rx_queues) {
 832                 rxq = dev->data->rx_queues[rx_queue_id];
 833                 err = rx_queue_reset(rxq);
 834                 if (err == -ENOMEM) {
 835                         PMD_INIT_LOG(ERR, "Failed to alloc memory : %d", err);
 836                         return err;
 837                 } else if (err == -EINVAL) {
 838                         PMD_INIT_LOG(ERR, "Invalid buffer address alignment :"
 839                                 " %d", err);
 840                         return err;
 841                 }
 842
 843                 /* Setup the HW Rx Head and Tail Descriptor Pointers
 844                  * Note: this must be done AFTER the queue is enabled on real
 845                  * hardware, but BEFORE the queue is enabled when using the
 846                  * emulation platform. Do it in both places for now and remove
 847                  * this comment and the following two register writes when the
 848                  * emulation platform is no longer being used.
 849                  */
 850                 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
 851                 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
 852
 853                 /* Set PF ownership flag for PF devices */
 854                 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(rx_queue_id));
 855                 if (hw->mac.type == fm10k_mac_pf)
 856                         reg |= FM10K_RXQCTL_PF;
 857                 reg |= FM10K_RXQCTL_ENABLE;
 858                 /* enable RX queue */
 859                 FM10K_WRITE_REG(hw, FM10K_RXQCTL(rx_queue_id), reg);
 860                 FM10K_WRITE_FLUSH(hw);
 861
 862                 /* Setup the HW Rx Head and Tail Descriptor Pointers
 863                  * Note: this must be done AFTER the queue is enabled
 864                  */
 865                 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
 866                 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
 867                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 868         }
 869
 870         return err;
 871 }
 872
 873 static int
 874 fm10k_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 875 {
 876         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 877
 878         PMD_INIT_FUNC_TRACE();
 879
 880         if (rx_queue_id < dev->data->nb_rx_queues) {
 881                 /* Disable RX queue */
 882                 rx_queue_disable(hw, rx_queue_id);
 883
 884                 /* Free mbuf and clean HW ring */
 885                 rx_queue_clean(dev->data->rx_queues[rx_queue_id]);
 886                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 887         }
 888
 889         return 0;
 890 }
 891
 892 static int
 893 fm10k_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 894 {
 895         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 896         /** @todo - this should be defined in the shared code */
 897 #define FM10K_TXDCTL_WRITE_BACK_MIN_DELAY       0x00010000
 898         uint32_t txdctl = FM10K_TXDCTL_WRITE_BACK_MIN_DELAY;
 899         int err = 0;
 900
 901         PMD_INIT_FUNC_TRACE();
 902
 903         if (tx_queue_id < dev->data->nb_tx_queues) {
 904                 struct fm10k_tx_queue *q = dev->data->tx_queues[tx_queue_id];
 905
 906                 q->ops->reset(q);
 907
 908                 /* reset head and tail pointers */
 909                 FM10K_WRITE_REG(hw, FM10K_TDH(tx_queue_id), 0);
 910                 FM10K_WRITE_REG(hw, FM10K_TDT(tx_queue_id), 0);
 911
 912                 /* enable TX queue */
 913                 FM10K_WRITE_REG(hw, FM10K_TXDCTL(tx_queue_id),
 914                                         FM10K_TXDCTL_ENABLE | txdctl);
 915                 FM10K_WRITE_FLUSH(hw);
 916                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 917         } else
 918                 err = -1;
 919
 920         return err;
 921 }
 922
 923 static int
 924 fm10k_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 925 {
 926         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 927
 928         PMD_INIT_FUNC_TRACE();
 929
 930         if (tx_queue_id < dev->data->nb_tx_queues) {
 931                 tx_queue_disable(hw, tx_queue_id);
 932                 tx_queue_clean(dev->data->tx_queues[tx_queue_id]);
 933                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 934         }
 935
 936         return 0;
 937 }
 938
 939 static inline int fm10k_glort_valid(struct fm10k_hw *hw)
 940 {
 941         return ((hw->mac.dglort_map & FM10K_DGLORTMAP_NONE)
 942                 != FM10K_DGLORTMAP_NONE);
 943 }
 944
 945 static void
 946 fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev)
 947 {
 948         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 949         int status;
 950
 951         PMD_INIT_FUNC_TRACE();
 952
 953         /* Return if it didn't acquire valid glort range */
 954         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
 955                 return;
 956
 957         fm10k_mbx_lock(hw);
 958         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 959                                 FM10K_XCAST_MODE_PROMISC);
 960         fm10k_mbx_unlock(hw);
 961
 962         if (status != FM10K_SUCCESS)
 963                 PMD_INIT_LOG(ERR, "Failed to enable promiscuous mode");
 964 }
 965
 966 static void
 967 fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev)
 968 {
 969         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 970         uint8_t mode;
 971         int status;
 972
 973         PMD_INIT_FUNC_TRACE();
 974
 975         /* Return if it didn't acquire valid glort range */
 976         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
 977                 return;
 978
 979         if (dev->data->all_multicast == 1)
 980                 mode = FM10K_XCAST_MODE_ALLMULTI;
 981         else
 982                 mode = FM10K_XCAST_MODE_NONE;
 983
 984         fm10k_mbx_lock(hw);
 985         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 986                                 mode);
 987         fm10k_mbx_unlock(hw);
 988
 989         if (status != FM10K_SUCCESS)
 990                 PMD_INIT_LOG(ERR, "Failed to disable promiscuous mode");
 991 }
 992
 993 static void
 994 fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev)
 995 {
 996         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 997         int status;
 998
 999         PMD_INIT_FUNC_TRACE();
1000
1001         /* Return if it didn't acquire valid glort range */
1002         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1003                 return;
1004
1005         /* If promiscuous mode is enabled, it doesn't make sense to enable
1006          * allmulticast and disable promiscuous since fm10k only can select
1007          * one of the modes.
1008          */
1009         if (dev->data->promiscuous) {
1010                 PMD_INIT_LOG(INFO, "Promiscuous mode is enabled, "\
1011                         "needn't enable allmulticast");
1012                 return;
1013         }
1014
1015         fm10k_mbx_lock(hw);
1016         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1017                                 FM10K_XCAST_MODE_ALLMULTI);
1018         fm10k_mbx_unlock(hw);
1019
1020         if (status != FM10K_SUCCESS)
1021                 PMD_INIT_LOG(ERR, "Failed to enable allmulticast mode");
1022 }
1023
1024 static void
1025 fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev)
1026 {
1027         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1028         int status;
1029
1030         PMD_INIT_FUNC_TRACE();
1031
1032         /* Return if it didn't acquire valid glort range */
1033         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1034                 return;
1035
1036         if (dev->data->promiscuous) {
1037                 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode "\
1038                         "since promisc mode is enabled");
1039                 return;
1040         }
1041
1042         fm10k_mbx_lock(hw);
1043         /* Change mode to unicast mode */
1044         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1045                                 FM10K_XCAST_MODE_NONE);
1046         fm10k_mbx_unlock(hw);
1047
1048         if (status != FM10K_SUCCESS)
1049                 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode");
1050 }
1051
1052 static void
1053 fm10k_dev_dglort_map_configure(struct rte_eth_dev *dev)
1054 {
1055         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1056         uint32_t dglortdec, pool_len, rss_len, i, dglortmask;
1057         uint16_t nb_queue_pools;
1058         struct fm10k_macvlan_filter_info *macvlan;
1059
1060         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1061         nb_queue_pools = macvlan->nb_queue_pools;
1062         pool_len = nb_queue_pools ? fls(nb_queue_pools - 1) : 0;
1063         rss_len = fls(dev->data->nb_rx_queues - 1) - pool_len;
1064
1065         /* GLORT 0x0-0x3F are used by PF and VMDQ,  0x40-0x7F used by FD */
1066         dglortdec = (rss_len << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | pool_len;
1067         dglortmask = (GLORT_PF_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1068                         hw->mac.dglort_map;
1069         FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(0), dglortmask);
1070         /* Configure VMDQ/RSS DGlort Decoder */
1071         FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(0), dglortdec);
1072
1073         /* Flow Director configurations, only queue number is valid. */
1074         dglortdec = fls(dev->data->nb_rx_queues - 1);
1075         dglortmask = (GLORT_FD_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1076                         (hw->mac.dglort_map + GLORT_FD_Q_BASE);
1077         FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(1), dglortmask);
1078         FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(1), dglortdec);
1079
1080         /* Invalidate all other GLORT entries */
1081         for (i = 2; i < FM10K_DGLORT_COUNT; i++)
1082                 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(i),
1083                                 FM10K_DGLORTMAP_NONE);
1084 }
1085
1086 #define BSIZEPKT_ROUNDUP ((1 << FM10K_SRRCTL_BSIZEPKT_SHIFT) - 1)
1087 static int
1088 fm10k_dev_start(struct rte_eth_dev *dev)
1089 {
1090         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1091         int i, diag;
1092
1093         PMD_INIT_FUNC_TRACE();
1094
1095         /* stop, init, then start the hw */
1096         diag = fm10k_stop_hw(hw);
1097         if (diag != FM10K_SUCCESS) {
1098                 PMD_INIT_LOG(ERR, "Hardware stop failed: %d", diag);
1099                 return -EIO;
1100         }
1101
1102         diag = fm10k_init_hw(hw);
1103         if (diag != FM10K_SUCCESS) {
1104                 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
1105                 return -EIO;
1106         }
1107
1108         diag = fm10k_start_hw(hw);
1109         if (diag != FM10K_SUCCESS) {
1110                 PMD_INIT_LOG(ERR, "Hardware start failed: %d", diag);
1111                 return -EIO;
1112         }
1113
1114         diag = fm10k_dev_tx_init(dev);
1115         if (diag) {
1116                 PMD_INIT_LOG(ERR, "TX init failed: %d", diag);
1117                 return diag;
1118         }
1119
1120         if (fm10k_dev_rxq_interrupt_setup(dev))
1121                 return -EIO;
1122
1123         diag = fm10k_dev_rx_init(dev);
1124         if (diag) {
1125                 PMD_INIT_LOG(ERR, "RX init failed: %d", diag);
1126                 return diag;
1127         }
1128
1129         if (hw->mac.type == fm10k_mac_pf)
1130                 fm10k_dev_dglort_map_configure(dev);
1131
1132         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1133                 struct fm10k_rx_queue *rxq;
1134                 rxq = dev->data->rx_queues[i];
1135
1136                 if (rxq->rx_deferred_start)
1137                         continue;
1138                 diag = fm10k_dev_rx_queue_start(dev, i);
1139                 if (diag != 0) {
1140                         int j;
1141                         for (j = 0; j < i; ++j)
1142                                 rx_queue_clean(dev->data->rx_queues[j]);
1143                         return diag;
1144                 }
1145         }
1146
1147         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1148                 struct fm10k_tx_queue *txq;
1149                 txq = dev->data->tx_queues[i];
1150
1151                 if (txq->tx_deferred_start)
1152                         continue;
1153                 diag = fm10k_dev_tx_queue_start(dev, i);
1154                 if (diag != 0) {
1155                         int j;
1156                         for (j = 0; j < i; ++j)
1157                                 tx_queue_clean(dev->data->tx_queues[j]);
1158                         for (j = 0; j < dev->data->nb_rx_queues; ++j)
1159                                 rx_queue_clean(dev->data->rx_queues[j]);
1160                         return diag;
1161                 }
1162         }
1163
1164         /* Update default vlan when not in VMDQ mode */
1165         if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
1166                 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
1167
1168         return 0;
1169 }
1170
1171 static void
1172 fm10k_dev_stop(struct rte_eth_dev *dev)
1173 {
1174         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1175         struct rte_pci_device *pdev = dev->pci_dev;
1176         struct rte_intr_handle *intr_handle = &pdev->intr_handle;
1177         int i;
1178
1179         PMD_INIT_FUNC_TRACE();
1180
1181         if (dev->data->tx_queues)
1182                 for (i = 0; i < dev->data->nb_tx_queues; i++)
1183                         fm10k_dev_tx_queue_stop(dev, i);
1184
1185         if (dev->data->rx_queues)
1186                 for (i = 0; i < dev->data->nb_rx_queues; i++)
1187                         fm10k_dev_rx_queue_stop(dev, i);
1188
1189         /* Disable datapath event */
1190         if (rte_intr_dp_is_en(intr_handle)) {
1191                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1192                         FM10K_WRITE_REG(hw, FM10K_RXINT(i),
1193                                 3 << FM10K_RXINT_TIMER_SHIFT);
1194                         if (hw->mac.type == fm10k_mac_pf)
1195                                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, i)),
1196                                         FM10K_ITR_MASK_SET);
1197                         else
1198                                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, i)),
1199                                         FM10K_ITR_MASK_SET);
1200                 }
1201         }
1202         /* Clean datapath event and queue/vec mapping */
1203         rte_intr_efd_disable(intr_handle);
1204         rte_free(intr_handle->intr_vec);
1205         intr_handle->intr_vec = NULL;
1206 }
1207
1208 static void
1209 fm10k_dev_queue_release(struct rte_eth_dev *dev)
1210 {
1211         int i;
1212
1213         PMD_INIT_FUNC_TRACE();
1214
1215         if (dev->data->tx_queues) {
1216                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1217                         struct fm10k_tx_queue *txq = dev->data->tx_queues[i];
1218
1219                         tx_queue_free(txq);
1220                 }
1221         }
1222
1223         if (dev->data->rx_queues) {
1224                 for (i = 0; i < dev->data->nb_rx_queues; i++)
1225                         fm10k_rx_queue_release(dev->data->rx_queues[i]);
1226         }
1227 }
1228
1229 static void
1230 fm10k_dev_close(struct rte_eth_dev *dev)
1231 {
1232         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1233
1234         PMD_INIT_FUNC_TRACE();
1235
1236         fm10k_mbx_lock(hw);
1237         hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
1238                 MAX_LPORT_NUM, false);
1239         fm10k_mbx_unlock(hw);
1240
1241         /* allow 10ms for device to quiesce */
1242         rte_delay_us(FM10K_SWITCH_QUIESCE_US);
1243
1244         /* Stop mailbox service first */
1245         fm10k_close_mbx_service(hw);
1246         fm10k_dev_stop(dev);
1247         fm10k_dev_queue_release(dev);
1248         fm10k_stop_hw(hw);
1249 }
1250
1251 static int
1252 fm10k_link_update(struct rte_eth_dev *dev,
1253         __rte_unused int wait_to_complete)
1254 {
1255         PMD_INIT_FUNC_TRACE();
1256
1257         /* The host-interface link is always up.  The speed is ~50Gbps per Gen3
1258          * x8 PCIe interface. For now, we leave the speed undefined since there
1259          * is no 50Gbps Ethernet. */
1260         dev->data->dev_link.link_speed  = 0;
1261         dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
1262         dev->data->dev_link.link_status = ETH_LINK_UP;
1263
1264         return 0;
1265 }
1266
1267 static int fm10k_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1268         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
1269 {
1270         unsigned i, q;
1271         unsigned count = 0;
1272
1273         if (xstats_names != NULL) {
1274                 /* Note: limit checked in rte_eth_xstats_names() */
1275
1276                 /* Global stats */
1277                 for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1278                         snprintf(xstats_names[count].name,
1279                                 sizeof(xstats_names[count].name),
1280                                 "%s", fm10k_hw_stats_strings[count].name);
1281                         count++;
1282                 }
1283
1284                 /* PF queue stats */
1285                 for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1286                         for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1287                                 snprintf(xstats_names[count].name,
1288                                         sizeof(xstats_names[count].name),
1289                                         "rx_q%u_%s", q,
1290                                         fm10k_hw_stats_rx_q_strings[i].name);
1291                                 count++;
1292                         }
1293                         for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1294                                 snprintf(xstats_names[count].name,
1295                                         sizeof(xstats_names[count].name),
1296                                         "tx_q%u_%s", q,
1297                                         fm10k_hw_stats_tx_q_strings[i].name);
1298                                 count++;
1299                         }
1300                 }
1301         }
1302         return FM10K_NB_XSTATS;
1303 }
1304
1305 static int
1306 fm10k_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1307                  unsigned n)
1308 {
1309         struct fm10k_hw_stats *hw_stats =
1310                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1311         unsigned i, q, count = 0;
1312
1313         if (n < FM10K_NB_XSTATS)
1314                 return FM10K_NB_XSTATS;
1315
1316         /* Global stats */
1317         for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1318                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1319                         fm10k_hw_stats_strings[count].offset);
1320                 count++;
1321         }
1322
1323         /* PF queue stats */
1324         for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1325                 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1326                         xstats[count].value =
1327                                 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1328                                 fm10k_hw_stats_rx_q_strings[i].offset);
1329                         count++;
1330                 }
1331                 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1332                         xstats[count].value =
1333                                 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1334                                 fm10k_hw_stats_tx_q_strings[i].offset);
1335                         count++;
1336                 }
1337         }
1338
1339         return FM10K_NB_XSTATS;
1340 }
1341
1342 static void
1343 fm10k_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1344 {
1345         uint64_t ipackets, opackets, ibytes, obytes;
1346         struct fm10k_hw *hw =
1347                 FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1348         struct fm10k_hw_stats *hw_stats =
1349                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1350         int i;
1351
1352         PMD_INIT_FUNC_TRACE();
1353
1354         fm10k_update_hw_stats(hw, hw_stats);
1355
1356         ipackets = opackets = ibytes = obytes = 0;
1357         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1358                 (i < hw->mac.max_queues); ++i) {
1359                 stats->q_ipackets[i] = hw_stats->q[i].rx_packets.count;
1360                 stats->q_opackets[i] = hw_stats->q[i].tx_packets.count;
1361                 stats->q_ibytes[i]   = hw_stats->q[i].rx_bytes.count;
1362                 stats->q_obytes[i]   = hw_stats->q[i].tx_bytes.count;
1363                 ipackets += stats->q_ipackets[i];
1364                 opackets += stats->q_opackets[i];
1365                 ibytes   += stats->q_ibytes[i];
1366                 obytes   += stats->q_obytes[i];
1367         }
1368         stats->ipackets = ipackets;
1369         stats->opackets = opackets;
1370         stats->ibytes = ibytes;
1371         stats->obytes = obytes;
1372 }
1373
1374 static void
1375 fm10k_stats_reset(struct rte_eth_dev *dev)
1376 {
1377         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1378         struct fm10k_hw_stats *hw_stats =
1379                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1380
1381         PMD_INIT_FUNC_TRACE();
1382
1383         memset(hw_stats, 0, sizeof(*hw_stats));
1384         fm10k_rebind_hw_stats(hw, hw_stats);
1385 }
1386
1387 static void
1388 fm10k_dev_infos_get(struct rte_eth_dev *dev,
1389         struct rte_eth_dev_info *dev_info)
1390 {
1391         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1392         struct rte_pci_device *pdev = dev->pci_dev;
1393
1394         PMD_INIT_FUNC_TRACE();
1395
1396         dev_info->min_rx_bufsize     = FM10K_MIN_RX_BUF_SIZE;
1397         dev_info->max_rx_pktlen      = FM10K_MAX_PKT_SIZE;
1398         dev_info->max_rx_queues      = hw->mac.max_queues;
1399         dev_info->max_tx_queues      = hw->mac.max_queues;
1400         dev_info->max_mac_addrs      = FM10K_MAX_MACADDR_NUM;
1401         dev_info->max_hash_mac_addrs = 0;
1402         dev_info->max_vfs            = pdev->max_vfs;
1403         dev_info->vmdq_pool_base     = 0;
1404         dev_info->vmdq_queue_base    = 0;
1405         dev_info->max_vmdq_pools     = ETH_32_POOLS;
1406         dev_info->vmdq_queue_num     = FM10K_MAX_QUEUES_PF;
1407         dev_info->rx_offload_capa =
1408                 DEV_RX_OFFLOAD_VLAN_STRIP |
1409                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1410                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1411                 DEV_RX_OFFLOAD_TCP_CKSUM;
1412         dev_info->tx_offload_capa =
1413                 DEV_TX_OFFLOAD_VLAN_INSERT |
1414                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1415                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1416                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1417                 DEV_TX_OFFLOAD_TCP_TSO;
1418
1419         dev_info->hash_key_size = FM10K_RSSRK_SIZE * sizeof(uint32_t);
1420         dev_info->reta_size = FM10K_MAX_RSS_INDICES;
1421
1422         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1423                 .rx_thresh = {
1424                         .pthresh = FM10K_DEFAULT_RX_PTHRESH,
1425                         .hthresh = FM10K_DEFAULT_RX_HTHRESH,
1426                         .wthresh = FM10K_DEFAULT_RX_WTHRESH,
1427                 },
1428                 .rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(0),
1429                 .rx_drop_en = 0,
1430         };
1431
1432         dev_info->default_txconf = (struct rte_eth_txconf) {
1433                 .tx_thresh = {
1434                         .pthresh = FM10K_DEFAULT_TX_PTHRESH,
1435                         .hthresh = FM10K_DEFAULT_TX_HTHRESH,
1436                         .wthresh = FM10K_DEFAULT_TX_WTHRESH,
1437                 },
1438                 .tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(0),
1439                 .tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(0),
1440                 .txq_flags = FM10K_SIMPLE_TX_FLAG,
1441         };
1442
1443         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1444                 .nb_max = FM10K_MAX_RX_DESC,
1445                 .nb_min = FM10K_MIN_RX_DESC,
1446                 .nb_align = FM10K_MULT_RX_DESC,
1447         };
1448
1449         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1450                 .nb_max = FM10K_MAX_TX_DESC,
1451                 .nb_min = FM10K_MIN_TX_DESC,
1452                 .nb_align = FM10K_MULT_TX_DESC,
1453         };
1454
1455         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G |
1456                         ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
1457                         ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G;
1458 }
1459
1460 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
1461 static const uint32_t *
1462 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1463 {
1464         if (dev->rx_pkt_burst == fm10k_recv_pkts ||
1465             dev->rx_pkt_burst == fm10k_recv_scattered_pkts) {
1466                 static uint32_t ptypes[] = {
1467                         /* refers to rx_desc_to_ol_flags() */
1468                         RTE_PTYPE_L2_ETHER,
1469                         RTE_PTYPE_L3_IPV4,
1470                         RTE_PTYPE_L3_IPV4_EXT,
1471                         RTE_PTYPE_L3_IPV6,
1472                         RTE_PTYPE_L3_IPV6_EXT,
1473                         RTE_PTYPE_L4_TCP,
1474                         RTE_PTYPE_L4_UDP,
1475                         RTE_PTYPE_UNKNOWN
1476                 };
1477
1478                 return ptypes;
1479         } else if (dev->rx_pkt_burst == fm10k_recv_pkts_vec ||
1480                    dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec) {
1481                 static uint32_t ptypes_vec[] = {
1482                         /* refers to fm10k_desc_to_pktype_v() */
1483                         RTE_PTYPE_L3_IPV4,
1484                         RTE_PTYPE_L3_IPV4_EXT,
1485                         RTE_PTYPE_L3_IPV6,
1486                         RTE_PTYPE_L3_IPV6_EXT,
1487                         RTE_PTYPE_L4_TCP,
1488                         RTE_PTYPE_L4_UDP,
1489                         RTE_PTYPE_TUNNEL_GENEVE,
1490                         RTE_PTYPE_TUNNEL_NVGRE,
1491                         RTE_PTYPE_TUNNEL_VXLAN,
1492                         RTE_PTYPE_TUNNEL_GRE,
1493                         RTE_PTYPE_UNKNOWN
1494                 };
1495
1496                 return ptypes_vec;
1497         }
1498
1499         return NULL;
1500 }
1501 #else
1502 static const uint32_t *
1503 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1504 {
1505         return NULL;
1506 }
1507 #endif
1508
1509 static int
1510 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1511 {
1512         s32 result;
1513         uint16_t mac_num = 0;
1514         uint32_t vid_idx, vid_bit, mac_index;
1515         struct fm10k_hw *hw;
1516         struct fm10k_macvlan_filter_info *macvlan;
1517         struct rte_eth_dev_data *data = dev->data;
1518
1519         hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1520         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1521
1522         if (macvlan->nb_queue_pools > 0) { /* VMDQ mode */
1523                 PMD_INIT_LOG(ERR, "Cannot change VLAN filter in VMDQ mode");
1524                 return -EINVAL;
1525         }
1526
1527         if (vlan_id > ETH_VLAN_ID_MAX) {
1528                 PMD_INIT_LOG(ERR, "Invalid vlan_id: must be < 4096");
1529                 return -EINVAL;
1530         }
1531
1532         vid_idx = FM10K_VFTA_IDX(vlan_id);
1533         vid_bit = FM10K_VFTA_BIT(vlan_id);
1534         /* this VLAN ID is already in the VLAN filter table, return SUCCESS */
1535         if (on && (macvlan->vfta[vid_idx] & vid_bit))
1536                 return 0;
1537         /* this VLAN ID is NOT in the VLAN filter table, cannot remove */
1538         if (!on && !(macvlan->vfta[vid_idx] & vid_bit)) {
1539                 PMD_INIT_LOG(ERR, "Invalid vlan_id: not existing "
1540                         "in the VLAN filter table");
1541                 return -EINVAL;
1542         }
1543
1544         fm10k_mbx_lock(hw);
1545         result = fm10k_update_vlan(hw, vlan_id, 0, on);
1546         fm10k_mbx_unlock(hw);
1547         if (result != FM10K_SUCCESS) {
1548                 PMD_INIT_LOG(ERR, "VLAN update failed: %d", result);
1549                 return -EIO;
1550         }
1551
1552         for (mac_index = 0; (mac_index < FM10K_MAX_MACADDR_NUM) &&
1553                         (result == FM10K_SUCCESS); mac_index++) {
1554                 if (is_zero_ether_addr(&data->mac_addrs[mac_index]))
1555                         continue;
1556                 if (mac_num > macvlan->mac_num - 1) {
1557                         PMD_INIT_LOG(ERR, "MAC address number "
1558                                         "not match");
1559                         break;
1560                 }
1561                 fm10k_mbx_lock(hw);
1562                 result = fm10k_update_uc_addr(hw, hw->mac.dglort_map,
1563                         data->mac_addrs[mac_index].addr_bytes,
1564                         vlan_id, on, 0);
1565                 fm10k_mbx_unlock(hw);
1566                 mac_num++;
1567         }
1568         if (result != FM10K_SUCCESS) {
1569                 PMD_INIT_LOG(ERR, "MAC address update failed: %d", result);
1570                 return -EIO;
1571         }
1572
1573         if (on) {
1574                 macvlan->vlan_num++;
1575                 macvlan->vfta[vid_idx] |= vid_bit;
1576         } else {
1577                 macvlan->vlan_num--;
1578                 macvlan->vfta[vid_idx] &= ~vid_bit;
1579         }
1580         return 0;
1581 }
1582
1583 static void
1584 fm10k_vlan_offload_set(__rte_unused struct rte_eth_dev *dev, int mask)
1585 {
1586         if (mask & ETH_VLAN_STRIP_MASK) {
1587                 if (!dev->data->dev_conf.rxmode.hw_vlan_strip)
1588                         PMD_INIT_LOG(ERR, "VLAN stripping is "
1589                                         "always on in fm10k");
1590         }
1591
1592         if (mask & ETH_VLAN_EXTEND_MASK) {
1593                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1594                         PMD_INIT_LOG(ERR, "VLAN QinQ is not "
1595                                         "supported in fm10k");
1596         }
1597
1598         if (mask & ETH_VLAN_FILTER_MASK) {
1599                 if (!dev->data->dev_conf.rxmode.hw_vlan_filter)
1600                         PMD_INIT_LOG(ERR, "VLAN filter is always on in fm10k");
1601         }
1602 }
1603
1604 /* Add/Remove a MAC address, and update filters to main VSI */
1605 static void fm10k_MAC_filter_set_main_vsi(struct rte_eth_dev *dev,
1606                 const u8 *mac, bool add, uint32_t pool)
1607 {
1608         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1609         struct fm10k_macvlan_filter_info *macvlan;
1610         uint32_t i, j, k;
1611
1612         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1613
1614         if (pool != MAIN_VSI_POOL_NUMBER) {
1615                 PMD_DRV_LOG(ERR, "VMDQ not enabled, can't set "
1616                         "mac to pool %u", pool);
1617                 return;
1618         }
1619         for (i = 0, j = 0; j < FM10K_VFTA_SIZE; j++) {
1620                 if (!macvlan->vfta[j])
1621                         continue;
1622                 for (k = 0; k < FM10K_UINT32_BIT_SIZE; k++) {
1623                         if (!(macvlan->vfta[j] & (1 << k)))
1624                                 continue;
1625                         if (i + 1 > macvlan->vlan_num) {
1626                                 PMD_INIT_LOG(ERR, "vlan number not match");
1627                                 return;
1628                         }
1629                         fm10k_mbx_lock(hw);
1630                         fm10k_update_uc_addr(hw, hw->mac.dglort_map, mac,
1631                                 j * FM10K_UINT32_BIT_SIZE + k, add, 0);
1632                         fm10k_mbx_unlock(hw);
1633                         i++;
1634                 }
1635         }
1636 }
1637
1638 /* Add/Remove a MAC address, and update filters to VMDQ */
1639 static void fm10k_MAC_filter_set_vmdq(struct rte_eth_dev *dev,
1640                 const u8 *mac, bool add, uint32_t pool)
1641 {
1642         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1643         struct fm10k_macvlan_filter_info *macvlan;
1644         struct rte_eth_vmdq_rx_conf *vmdq_conf;
1645         uint32_t i;
1646
1647         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1648         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1649
1650         if (pool > macvlan->nb_queue_pools) {
1651                 PMD_DRV_LOG(ERR, "Pool number %u invalid."
1652                         " Max pool is %u",
1653                         pool, macvlan->nb_queue_pools);
1654                 return;
1655         }
1656         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
1657                 if (!(vmdq_conf->pool_map[i].pools & (1UL << pool)))
1658                         continue;
1659                 fm10k_mbx_lock(hw);
1660                 fm10k_update_uc_addr(hw, hw->mac.dglort_map + pool, mac,
1661                         vmdq_conf->pool_map[i].vlan_id, add, 0);
1662                 fm10k_mbx_unlock(hw);
1663         }
1664 }
1665
1666 /* Add/Remove a MAC address, and update filters */
1667 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
1668                 const u8 *mac, bool add, uint32_t pool)
1669 {
1670         struct fm10k_macvlan_filter_info *macvlan;
1671
1672         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1673
1674         if (macvlan->nb_queue_pools > 0) /* VMDQ mode */
1675                 fm10k_MAC_filter_set_vmdq(dev, mac, add, pool);
1676         else
1677                 fm10k_MAC_filter_set_main_vsi(dev, mac, add, pool);
1678
1679         if (add)
1680                 macvlan->mac_num++;
1681         else
1682                 macvlan->mac_num--;
1683 }
1684
1685 /* Add a MAC address, and update filters */
1686 static void
1687 fm10k_macaddr_add(struct rte_eth_dev *dev,
1688                 struct ether_addr *mac_addr,
1689                 uint32_t index,
1690                 uint32_t pool)
1691 {
1692         struct fm10k_macvlan_filter_info *macvlan;
1693
1694         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1695         fm10k_MAC_filter_set(dev, mac_addr->addr_bytes, TRUE, pool);
1696         macvlan->mac_vmdq_id[index] = pool;
1697 }
1698
1699 /* Remove a MAC address, and update filters */
1700 static void
1701 fm10k_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1702 {
1703         struct rte_eth_dev_data *data = dev->data;
1704         struct fm10k_macvlan_filter_info *macvlan;
1705
1706         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1707         fm10k_MAC_filter_set(dev, data->mac_addrs[index].addr_bytes,
1708                         FALSE, macvlan->mac_vmdq_id[index]);
1709         macvlan->mac_vmdq_id[index] = 0;
1710 }
1711
1712 static inline int
1713 check_nb_desc(uint16_t min, uint16_t max, uint16_t mult, uint16_t request)
1714 {
1715         if ((request < min) || (request > max) || ((request % mult) != 0))
1716                 return -1;
1717         else
1718                 return 0;
1719 }
1720
1721
1722 static inline int
1723 check_thresh(uint16_t min, uint16_t max, uint16_t div, uint16_t request)
1724 {
1725         if ((request < min) || (request > max) || ((div % request) != 0))
1726                 return -1;
1727         else
1728                 return 0;
1729 }
1730
1731 static inline int
1732 handle_rxconf(struct fm10k_rx_queue *q, const struct rte_eth_rxconf *conf)
1733 {
1734         uint16_t rx_free_thresh;
1735
1736         if (conf->rx_free_thresh == 0)
1737                 rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(q);
1738         else
1739                 rx_free_thresh = conf->rx_free_thresh;
1740
1741         /* make sure the requested threshold satisfies the constraints */
1742         if (check_thresh(FM10K_RX_FREE_THRESH_MIN(q),
1743                         FM10K_RX_FREE_THRESH_MAX(q),
1744                         FM10K_RX_FREE_THRESH_DIV(q),
1745                         rx_free_thresh)) {
1746                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be "
1747                         "less than or equal to %u, "
1748                         "greater than or equal to %u, "
1749                         "and a divisor of %u",
1750                         rx_free_thresh, FM10K_RX_FREE_THRESH_MAX(q),
1751                         FM10K_RX_FREE_THRESH_MIN(q),
1752                         FM10K_RX_FREE_THRESH_DIV(q));
1753                 return -EINVAL;
1754         }
1755
1756         q->alloc_thresh = rx_free_thresh;
1757         q->drop_en = conf->rx_drop_en;
1758         q->rx_deferred_start = conf->rx_deferred_start;
1759
1760         return 0;
1761 }
1762
1763 /*
1764  * Hardware requires specific alignment for Rx packet buffers. At
1765  * least one of the following two conditions must be satisfied.
1766  *  1. Address is 512B aligned
1767  *  2. Address is 8B aligned and buffer does not cross 4K boundary.
1768  *
1769  * As such, the driver may need to adjust the DMA address within the
1770  * buffer by up to 512B.
1771  *
1772  * return 1 if the element size is valid, otherwise return 0.
1773  */
1774 static int
1775 mempool_element_size_valid(struct rte_mempool *mp)
1776 {
1777         uint32_t min_size;
1778
1779         /* elt_size includes mbuf header and headroom */
1780         min_size = mp->elt_size - sizeof(struct rte_mbuf) -
1781                         RTE_PKTMBUF_HEADROOM;
1782
1783         /* account for up to 512B of alignment */
1784         min_size -= FM10K_RX_DATABUF_ALIGN;
1785
1786         /* sanity check for overflow */
1787         if (min_size > mp->elt_size)
1788                 return 0;
1789
1790         /* size is valid */
1791         return 1;
1792 }
1793
1794 static int
1795 fm10k_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1796         uint16_t nb_desc, unsigned int socket_id,
1797         const struct rte_eth_rxconf *conf, struct rte_mempool *mp)
1798 {
1799         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1800         struct fm10k_dev_info *dev_info = FM10K_DEV_PRIVATE_TO_INFO(dev);
1801         struct fm10k_rx_queue *q;
1802         const struct rte_memzone *mz;
1803
1804         PMD_INIT_FUNC_TRACE();
1805
1806         /* make sure the mempool element size can account for alignment. */
1807         if (!mempool_element_size_valid(mp)) {
1808                 PMD_INIT_LOG(ERR, "Error : Mempool element size is too small");
1809                 return -EINVAL;
1810         }
1811
1812         /* make sure a valid number of descriptors have been requested */
1813         if (check_nb_desc(FM10K_MIN_RX_DESC, FM10K_MAX_RX_DESC,
1814                                 FM10K_MULT_RX_DESC, nb_desc)) {
1815                 PMD_INIT_LOG(ERR, "Number of Rx descriptors (%u) must be "
1816                         "less than or equal to %"PRIu32", "
1817                         "greater than or equal to %u, "
1818                         "and a multiple of %u",
1819                         nb_desc, (uint32_t)FM10K_MAX_RX_DESC, FM10K_MIN_RX_DESC,
1820                         FM10K_MULT_RX_DESC);
1821                 return -EINVAL;
1822         }
1823
1824         /*
1825          * if this queue existed already, free the associated memory. The
1826          * queue cannot be reused in case we need to allocate memory on
1827          * different socket than was previously used.
1828          */
1829         if (dev->data->rx_queues[queue_id] != NULL) {
1830                 rx_queue_free(dev->data->rx_queues[queue_id]);
1831                 dev->data->rx_queues[queue_id] = NULL;
1832         }
1833
1834         /* allocate memory for the queue structure */
1835         q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1836                                 socket_id);
1837         if (q == NULL) {
1838                 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1839                 return -ENOMEM;
1840         }
1841
1842         /* setup queue */
1843         q->mp = mp;
1844         q->nb_desc = nb_desc;
1845         q->nb_fake_desc = FM10K_MULT_RX_DESC;
1846         q->port_id = dev->data->port_id;
1847         q->queue_id = queue_id;
1848         q->tail_ptr = (volatile uint32_t *)
1849                 &((uint32_t *)hw->hw_addr)[FM10K_RDT(queue_id)];
1850         if (handle_rxconf(q, conf))
1851                 return -EINVAL;
1852
1853         /* allocate memory for the software ring */
1854         q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
1855                         (nb_desc + q->nb_fake_desc) * sizeof(struct rte_mbuf *),
1856                         RTE_CACHE_LINE_SIZE, socket_id);
1857         if (q->sw_ring == NULL) {
1858                 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
1859                 rte_free(q);
1860                 return -ENOMEM;
1861         }
1862
1863         /*
1864          * allocate memory for the hardware descriptor ring. A memzone large
1865          * enough to hold the maximum ring size is requested to allow for
1866          * resizing in later calls to the queue setup function.
1867          */
1868         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_id,
1869                                       FM10K_MAX_RX_RING_SZ, FM10K_ALIGN_RX_DESC,
1870                                       socket_id);
1871         if (mz == NULL) {
1872                 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
1873                 rte_free(q->sw_ring);
1874                 rte_free(q);
1875                 return -ENOMEM;
1876         }
1877         q->hw_ring = mz->addr;
1878         q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1879
1880         /* Check if number of descs satisfied Vector requirement */
1881         if (!rte_is_power_of_2(nb_desc)) {
1882                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
1883                                     "preconditions - canceling the feature for "
1884                                     "the whole port[%d]",
1885                              q->queue_id, q->port_id);
1886                 dev_info->rx_vec_allowed = false;
1887         } else
1888                 fm10k_rxq_vec_setup(q);
1889
1890         dev->data->rx_queues[queue_id] = q;
1891         return 0;
1892 }
1893
1894 static void
1895 fm10k_rx_queue_release(void *queue)
1896 {
1897         PMD_INIT_FUNC_TRACE();
1898
1899         rx_queue_free(queue);
1900 }
1901
1902 static inline int
1903 handle_txconf(struct fm10k_tx_queue *q, const struct rte_eth_txconf *conf)
1904 {
1905         uint16_t tx_free_thresh;
1906         uint16_t tx_rs_thresh;
1907
1908         /* constraint MACROs require that tx_free_thresh is configured
1909          * before tx_rs_thresh */
1910         if (conf->tx_free_thresh == 0)
1911                 tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(q);
1912         else
1913                 tx_free_thresh = conf->tx_free_thresh;
1914
1915         /* make sure the requested threshold satisfies the constraints */
1916         if (check_thresh(FM10K_TX_FREE_THRESH_MIN(q),
1917                         FM10K_TX_FREE_THRESH_MAX(q),
1918                         FM10K_TX_FREE_THRESH_DIV(q),
1919                         tx_free_thresh)) {
1920                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be "
1921                         "less than or equal to %u, "
1922                         "greater than or equal to %u, "
1923                         "and a divisor of %u",
1924                         tx_free_thresh, FM10K_TX_FREE_THRESH_MAX(q),
1925                         FM10K_TX_FREE_THRESH_MIN(q),
1926                         FM10K_TX_FREE_THRESH_DIV(q));
1927                 return -EINVAL;
1928         }
1929
1930         q->free_thresh = tx_free_thresh;
1931
1932         if (conf->tx_rs_thresh == 0)
1933                 tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(q);
1934         else
1935                 tx_rs_thresh = conf->tx_rs_thresh;
1936
1937         q->tx_deferred_start = conf->tx_deferred_start;
1938
1939         /* make sure the requested threshold satisfies the constraints */
1940         if (check_thresh(FM10K_TX_RS_THRESH_MIN(q),
1941                         FM10K_TX_RS_THRESH_MAX(q),
1942                         FM10K_TX_RS_THRESH_DIV(q),
1943                         tx_rs_thresh)) {
1944                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be "
1945                         "less than or equal to %u, "
1946                         "greater than or equal to %u, "
1947                         "and a divisor of %u",
1948                         tx_rs_thresh, FM10K_TX_RS_THRESH_MAX(q),
1949                         FM10K_TX_RS_THRESH_MIN(q),
1950                         FM10K_TX_RS_THRESH_DIV(q));
1951                 return -EINVAL;
1952         }
1953
1954         q->rs_thresh = tx_rs_thresh;
1955
1956         return 0;
1957 }
1958
1959 static int
1960 fm10k_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1961         uint16_t nb_desc, unsigned int socket_id,
1962         const struct rte_eth_txconf *conf)
1963 {
1964         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1965         struct fm10k_tx_queue *q;
1966         const struct rte_memzone *mz;
1967
1968         PMD_INIT_FUNC_TRACE();
1969
1970         /* make sure a valid number of descriptors have been requested */
1971         if (check_nb_desc(FM10K_MIN_TX_DESC, FM10K_MAX_TX_DESC,
1972                                 FM10K_MULT_TX_DESC, nb_desc)) {
1973                 PMD_INIT_LOG(ERR, "Number of Tx descriptors (%u) must be "
1974                         "less than or equal to %"PRIu32", "
1975                         "greater than or equal to %u, "
1976                         "and a multiple of %u",
1977                         nb_desc, (uint32_t)FM10K_MAX_TX_DESC, FM10K_MIN_TX_DESC,
1978                         FM10K_MULT_TX_DESC);
1979                 return -EINVAL;
1980         }
1981
1982         /*
1983          * if this queue existed already, free the associated memory. The
1984          * queue cannot be reused in case we need to allocate memory on
1985          * different socket than was previously used.
1986          */
1987         if (dev->data->tx_queues[queue_id] != NULL) {
1988                 struct fm10k_tx_queue *txq = dev->data->tx_queues[queue_id];
1989
1990                 tx_queue_free(txq);
1991                 dev->data->tx_queues[queue_id] = NULL;
1992         }
1993
1994         /* allocate memory for the queue structure */
1995         q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1996                                 socket_id);
1997         if (q == NULL) {
1998                 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1999                 return -ENOMEM;
2000         }
2001
2002         /* setup queue */
2003         q->nb_desc = nb_desc;
2004         q->port_id = dev->data->port_id;
2005         q->queue_id = queue_id;
2006         q->txq_flags = conf->txq_flags;
2007         q->ops = &def_txq_ops;
2008         q->tail_ptr = (volatile uint32_t *)
2009                 &((uint32_t *)hw->hw_addr)[FM10K_TDT(queue_id)];
2010         if (handle_txconf(q, conf))
2011                 return -EINVAL;
2012
2013         /* allocate memory for the software ring */
2014         q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
2015                                         nb_desc * sizeof(struct rte_mbuf *),
2016                                         RTE_CACHE_LINE_SIZE, socket_id);
2017         if (q->sw_ring == NULL) {
2018                 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
2019                 rte_free(q);
2020                 return -ENOMEM;
2021         }
2022
2023         /*
2024          * allocate memory for the hardware descriptor ring. A memzone large
2025          * enough to hold the maximum ring size is requested to allow for
2026          * resizing in later calls to the queue setup function.
2027          */
2028         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_id,
2029                                       FM10K_MAX_TX_RING_SZ, FM10K_ALIGN_TX_DESC,
2030                                       socket_id);
2031         if (mz == NULL) {
2032                 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
2033                 rte_free(q->sw_ring);
2034                 rte_free(q);
2035                 return -ENOMEM;
2036         }
2037         q->hw_ring = mz->addr;
2038         q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2039
2040         /*
2041          * allocate memory for the RS bit tracker. Enough slots to hold the
2042          * descriptor index for each RS bit needing to be set are required.
2043          */
2044         q->rs_tracker.list = rte_zmalloc_socket("fm10k rs tracker",
2045                                 ((nb_desc + 1) / q->rs_thresh) *
2046                                 sizeof(uint16_t),
2047                                 RTE_CACHE_LINE_SIZE, socket_id);
2048         if (q->rs_tracker.list == NULL) {
2049                 PMD_INIT_LOG(ERR, "Cannot allocate RS bit tracker");
2050                 rte_free(q->sw_ring);
2051                 rte_free(q);
2052                 return -ENOMEM;
2053         }
2054
2055         dev->data->tx_queues[queue_id] = q;
2056         return 0;
2057 }
2058
2059 static void
2060 fm10k_tx_queue_release(void *queue)
2061 {
2062         struct fm10k_tx_queue *q = queue;
2063         PMD_INIT_FUNC_TRACE();
2064
2065         tx_queue_free(q);
2066 }
2067
2068 static int
2069 fm10k_reta_update(struct rte_eth_dev *dev,
2070                         struct rte_eth_rss_reta_entry64 *reta_conf,
2071                         uint16_t reta_size)
2072 {
2073         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2074         uint16_t i, j, idx, shift;
2075         uint8_t mask;
2076         uint32_t reta;
2077
2078         PMD_INIT_FUNC_TRACE();
2079
2080         if (reta_size > FM10K_MAX_RSS_INDICES) {
2081                 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2082                         "(%d) doesn't match the number hardware can supported "
2083                         "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2084                 return -EINVAL;
2085         }
2086
2087         /*
2088          * Update Redirection Table RETA[n], n=0..31. The redirection table has
2089          * 128-entries in 32 registers
2090          */
2091         for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2092                 idx = i / RTE_RETA_GROUP_SIZE;
2093                 shift = i % RTE_RETA_GROUP_SIZE;
2094                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2095                                 BIT_MASK_PER_UINT32);
2096                 if (mask == 0)
2097                         continue;
2098
2099                 reta = 0;
2100                 if (mask != BIT_MASK_PER_UINT32)
2101                         reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2102
2103                 for (j = 0; j < CHARS_PER_UINT32; j++) {
2104                         if (mask & (0x1 << j)) {
2105                                 if (mask != 0xF)
2106                                         reta &= ~(UINT8_MAX << CHAR_BIT * j);
2107                                 reta |= reta_conf[idx].reta[shift + j] <<
2108                                                 (CHAR_BIT * j);
2109                         }
2110                 }
2111                 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2), reta);
2112         }
2113
2114         return 0;
2115 }
2116
2117 static int
2118 fm10k_reta_query(struct rte_eth_dev *dev,
2119                         struct rte_eth_rss_reta_entry64 *reta_conf,
2120                         uint16_t reta_size)
2121 {
2122         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2123         uint16_t i, j, idx, shift;
2124         uint8_t mask;
2125         uint32_t reta;
2126
2127         PMD_INIT_FUNC_TRACE();
2128
2129         if (reta_size < FM10K_MAX_RSS_INDICES) {
2130                 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2131                         "(%d) doesn't match the number hardware can supported "
2132                         "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2133                 return -EINVAL;
2134         }
2135
2136         /*
2137          * Read Redirection Table RETA[n], n=0..31. The redirection table has
2138          * 128-entries in 32 registers
2139          */
2140         for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2141                 idx = i / RTE_RETA_GROUP_SIZE;
2142                 shift = i % RTE_RETA_GROUP_SIZE;
2143                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2144                                 BIT_MASK_PER_UINT32);
2145                 if (mask == 0)
2146                         continue;
2147
2148                 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2149                 for (j = 0; j < CHARS_PER_UINT32; j++) {
2150                         if (mask & (0x1 << j))
2151                                 reta_conf[idx].reta[shift + j] = ((reta >>
2152                                         CHAR_BIT * j) & UINT8_MAX);
2153                 }
2154         }
2155
2156         return 0;
2157 }
2158
2159 static int
2160 fm10k_rss_hash_update(struct rte_eth_dev *dev,
2161         struct rte_eth_rss_conf *rss_conf)
2162 {
2163         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2165         uint32_t mrqc;
2166         uint64_t hf = rss_conf->rss_hf;
2167         int i;
2168
2169         PMD_INIT_FUNC_TRACE();
2170
2171         if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2172                                 FM10K_RSSRK_ENTRIES_PER_REG))
2173                 return -EINVAL;
2174
2175         if (hf == 0)
2176                 return -EINVAL;
2177
2178         mrqc = 0;
2179         mrqc |= (hf & ETH_RSS_IPV4)              ? FM10K_MRQC_IPV4     : 0;
2180         mrqc |= (hf & ETH_RSS_IPV6)              ? FM10K_MRQC_IPV6     : 0;
2181         mrqc |= (hf & ETH_RSS_IPV6_EX)           ? FM10K_MRQC_IPV6     : 0;
2182         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? FM10K_MRQC_TCP_IPV4 : 0;
2183         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? FM10K_MRQC_TCP_IPV6 : 0;
2184         mrqc |= (hf & ETH_RSS_IPV6_TCP_EX)       ? FM10K_MRQC_TCP_IPV6 : 0;
2185         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? FM10K_MRQC_UDP_IPV4 : 0;
2186         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? FM10K_MRQC_UDP_IPV6 : 0;
2187         mrqc |= (hf & ETH_RSS_IPV6_UDP_EX)       ? FM10K_MRQC_UDP_IPV6 : 0;
2188
2189         /* If the mapping doesn't fit any supported, return */
2190         if (mrqc == 0)
2191                 return -EINVAL;
2192
2193         if (key != NULL)
2194                 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2195                         FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
2196
2197         FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
2198
2199         return 0;
2200 }
2201
2202 static int
2203 fm10k_rss_hash_conf_get(struct rte_eth_dev *dev,
2204         struct rte_eth_rss_conf *rss_conf)
2205 {
2206         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2207         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2208         uint32_t mrqc;
2209         uint64_t hf;
2210         int i;
2211
2212         PMD_INIT_FUNC_TRACE();
2213
2214         if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2215                                 FM10K_RSSRK_ENTRIES_PER_REG))
2216                 return -EINVAL;
2217
2218         if (key != NULL)
2219                 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2220                         key[i] = FM10K_READ_REG(hw, FM10K_RSSRK(0, i));
2221
2222         mrqc = FM10K_READ_REG(hw, FM10K_MRQC(0));
2223         hf = 0;
2224         hf |= (mrqc & FM10K_MRQC_IPV4)     ? ETH_RSS_IPV4              : 0;
2225         hf |= (mrqc & FM10K_MRQC_IPV6)     ? ETH_RSS_IPV6              : 0;
2226         hf |= (mrqc & FM10K_MRQC_IPV6)     ? ETH_RSS_IPV6_EX           : 0;
2227         hf |= (mrqc & FM10K_MRQC_TCP_IPV4) ? ETH_RSS_NONFRAG_IPV4_TCP  : 0;
2228         hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_NONFRAG_IPV6_TCP  : 0;
2229         hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_IPV6_TCP_EX       : 0;
2230         hf |= (mrqc & FM10K_MRQC_UDP_IPV4) ? ETH_RSS_NONFRAG_IPV4_UDP  : 0;
2231         hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_NONFRAG_IPV6_UDP  : 0;
2232         hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_IPV6_UDP_EX       : 0;
2233
2234         rss_conf->rss_hf = hf;
2235
2236         return 0;
2237 }
2238
2239 static void
2240 fm10k_dev_enable_intr_pf(struct rte_eth_dev *dev)
2241 {
2242         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2243         uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2244
2245         /* Bind all local non-queue interrupt to vector 0 */
2246         int_map |= FM10K_MISC_VEC_ID;
2247
2248         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2249         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2250         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2251         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2252         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2253         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2254
2255         /* Enable misc causes */
2256         FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |
2257                                 FM10K_EIMR_ENABLE(THI_FAULT) |
2258                                 FM10K_EIMR_ENABLE(FUM_FAULT) |
2259                                 FM10K_EIMR_ENABLE(MAILBOX) |
2260                                 FM10K_EIMR_ENABLE(SWITCHREADY) |
2261                                 FM10K_EIMR_ENABLE(SWITCHNOTREADY) |
2262                                 FM10K_EIMR_ENABLE(SRAMERROR) |
2263                                 FM10K_EIMR_ENABLE(VFLR));
2264
2265         /* Enable ITR 0 */
2266         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2267                                         FM10K_ITR_MASK_CLEAR);
2268         FM10K_WRITE_FLUSH(hw);
2269 }
2270
2271 static void
2272 fm10k_dev_disable_intr_pf(struct rte_eth_dev *dev)
2273 {
2274         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2275         uint32_t int_map = FM10K_INT_MAP_DISABLE;
2276
2277         int_map |= FM10K_MISC_VEC_ID;
2278
2279         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2280         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2281         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2282         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2283         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2284         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2285
2286         /* Disable misc causes */
2287         FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(PCA_FAULT) |
2288                                 FM10K_EIMR_DISABLE(THI_FAULT) |
2289                                 FM10K_EIMR_DISABLE(FUM_FAULT) |
2290                                 FM10K_EIMR_DISABLE(MAILBOX) |
2291                                 FM10K_EIMR_DISABLE(SWITCHREADY) |
2292                                 FM10K_EIMR_DISABLE(SWITCHNOTREADY) |
2293                                 FM10K_EIMR_DISABLE(SRAMERROR) |
2294                                 FM10K_EIMR_DISABLE(VFLR));
2295
2296         /* Disable ITR 0 */
2297         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_MASK_SET);
2298         FM10K_WRITE_FLUSH(hw);
2299 }
2300
2301 static void
2302 fm10k_dev_enable_intr_vf(struct rte_eth_dev *dev)
2303 {
2304         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2305         uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2306
2307         /* Bind all local non-queue interrupt to vector 0 */
2308         int_map |= FM10K_MISC_VEC_ID;
2309
2310         /* Only INT 0 available, other 15 are reserved. */
2311         FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2312
2313         /* Enable ITR 0 */
2314         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2315                                         FM10K_ITR_MASK_CLEAR);
2316         FM10K_WRITE_FLUSH(hw);
2317 }
2318
2319 static void
2320 fm10k_dev_disable_intr_vf(struct rte_eth_dev *dev)
2321 {
2322         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2323         uint32_t int_map = FM10K_INT_MAP_DISABLE;
2324
2325         int_map |= FM10K_MISC_VEC_ID;
2326
2327         /* Only INT 0 available, other 15 are reserved. */
2328         FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2329
2330         /* Disable ITR 0 */
2331         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_MASK_SET);
2332         FM10K_WRITE_FLUSH(hw);
2333 }
2334
2335 static int
2336 fm10k_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
2337 {
2338         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2339         struct rte_pci_device *pdev = dev->pci_dev;
2340
2341         /* Enable ITR */
2342         if (hw->mac.type == fm10k_mac_pf)
2343                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, queue_id)),
2344                         FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2345         else
2346                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, queue_id)),
2347                         FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2348         rte_intr_enable(&pdev->intr_handle);
2349         return 0;
2350 }
2351
2352 static int
2353 fm10k_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2354 {
2355         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2356         struct rte_pci_device *pdev = dev->pci_dev;
2357
2358         /* Disable ITR */
2359         if (hw->mac.type == fm10k_mac_pf)
2360                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, queue_id)),
2361                         FM10K_ITR_MASK_SET);
2362         else
2363                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, queue_id)),
2364                         FM10K_ITR_MASK_SET);
2365         return 0;
2366 }
2367
2368 static int
2369 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2370 {
2371         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2372         struct rte_pci_device *pdev = dev->pci_dev;
2373         struct rte_intr_handle *intr_handle = &pdev->intr_handle;
2374         uint32_t intr_vector, vec;
2375         uint16_t queue_id;
2376         int result = 0;
2377
2378         /* fm10k needs one separate interrupt for mailbox,
2379          * so only drivers which support multiple interrupt vectors
2380          * e.g. vfio-pci can work for fm10k interrupt mode
2381          */
2382         if (!rte_intr_cap_multiple(intr_handle) ||
2383                         dev->data->dev_conf.intr_conf.rxq == 0)
2384                 return result;
2385
2386         intr_vector = dev->data->nb_rx_queues;
2387
2388         /* disable interrupt first */
2389         rte_intr_disable(intr_handle);
2390         if (hw->mac.type == fm10k_mac_pf)
2391                 fm10k_dev_disable_intr_pf(dev);
2392         else
2393                 fm10k_dev_disable_intr_vf(dev);
2394
2395         if (rte_intr_efd_enable(intr_handle, intr_vector)) {
2396                 PMD_INIT_LOG(ERR, "Failed to init event fd");
2397                 result = -EIO;
2398         }
2399
2400         if (rte_intr_dp_is_en(intr_handle) && !result) {
2401                 intr_handle->intr_vec = rte_zmalloc("intr_vec",
2402                         dev->data->nb_rx_queues * sizeof(int), 0);
2403                 if (intr_handle->intr_vec) {
2404                         for (queue_id = 0, vec = FM10K_RX_VEC_START;
2405                                         queue_id < dev->data->nb_rx_queues;
2406                                         queue_id++) {
2407                                 intr_handle->intr_vec[queue_id] = vec;
2408                                 if (vec < intr_handle->nb_efd - 1
2409                                                 + FM10K_RX_VEC_START)
2410                                         vec++;
2411                         }
2412                 } else {
2413                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2414                                 " intr_vec", dev->data->nb_rx_queues);
2415                         rte_intr_efd_disable(intr_handle);
2416                         result = -ENOMEM;
2417                 }
2418         }
2419
2420         if (hw->mac.type == fm10k_mac_pf)
2421                 fm10k_dev_enable_intr_pf(dev);
2422         else
2423                 fm10k_dev_enable_intr_vf(dev);
2424         rte_intr_enable(intr_handle);
2425         hw->mac.ops.update_int_moderator(hw);
2426         return result;
2427 }
2428
2429 static int
2430 fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr)
2431 {
2432         struct fm10k_fault fault;
2433         int err;
2434         const char *estr = "Unknown error";
2435
2436         /* Process PCA fault */
2437         if (eicr & FM10K_EICR_PCA_FAULT) {
2438                 err = fm10k_get_fault(hw, FM10K_PCA_FAULT, &fault);
2439                 if (err)
2440                         goto error;
2441                 switch (fault.type) {
2442                 case PCA_NO_FAULT:
2443                         estr = "PCA_NO_FAULT"; break;
2444                 case PCA_UNMAPPED_ADDR:
2445                         estr = "PCA_UNMAPPED_ADDR"; break;
2446                 case PCA_BAD_QACCESS_PF:
2447                         estr = "PCA_BAD_QACCESS_PF"; break;
2448                 case PCA_BAD_QACCESS_VF:
2449                         estr = "PCA_BAD_QACCESS_VF"; break;
2450                 case PCA_MALICIOUS_REQ:
2451                         estr = "PCA_MALICIOUS_REQ"; break;
2452                 case PCA_POISONED_TLP:
2453                         estr = "PCA_POISONED_TLP"; break;
2454                 case PCA_TLP_ABORT:
2455                         estr = "PCA_TLP_ABORT"; break;
2456                 default:
2457                         goto error;
2458                 }
2459                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2460                         estr, fault.func ? "VF" : "PF", fault.func,
2461                         fault.address, fault.specinfo);
2462         }
2463
2464         /* Process THI fault */
2465         if (eicr & FM10K_EICR_THI_FAULT) {
2466                 err = fm10k_get_fault(hw, FM10K_THI_FAULT, &fault);
2467                 if (err)
2468                         goto error;
2469                 switch (fault.type) {
2470                 case THI_NO_FAULT:
2471                         estr = "THI_NO_FAULT"; break;
2472                 case THI_MAL_DIS_Q_FAULT:
2473                         estr = "THI_MAL_DIS_Q_FAULT"; break;
2474                 default:
2475                         goto error;
2476                 }
2477                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2478                         estr, fault.func ? "VF" : "PF", fault.func,
2479                         fault.address, fault.specinfo);
2480         }
2481
2482         /* Process FUM fault */
2483         if (eicr & FM10K_EICR_FUM_FAULT) {
2484                 err = fm10k_get_fault(hw, FM10K_FUM_FAULT, &fault);
2485                 if (err)
2486                         goto error;
2487                 switch (fault.type) {
2488                 case FUM_NO_FAULT:
2489                         estr = "FUM_NO_FAULT"; break;
2490                 case FUM_UNMAPPED_ADDR:
2491                         estr = "FUM_UNMAPPED_ADDR"; break;
2492                 case FUM_POISONED_TLP:
2493                         estr = "FUM_POISONED_TLP"; break;
2494                 case FUM_BAD_VF_QACCESS:
2495                         estr = "FUM_BAD_VF_QACCESS"; break;
2496                 case FUM_ADD_DECODE_ERR:
2497                         estr = "FUM_ADD_DECODE_ERR"; break;
2498                 case FUM_RO_ERROR:
2499                         estr = "FUM_RO_ERROR"; break;
2500                 case FUM_QPRC_CRC_ERROR:
2501                         estr = "FUM_QPRC_CRC_ERROR"; break;
2502                 case FUM_CSR_TIMEOUT:
2503                         estr = "FUM_CSR_TIMEOUT"; break;
2504                 case FUM_INVALID_TYPE:
2505                         estr = "FUM_INVALID_TYPE"; break;
2506                 case FUM_INVALID_LENGTH:
2507                         estr = "FUM_INVALID_LENGTH"; break;
2508                 case FUM_INVALID_BE:
2509                         estr = "FUM_INVALID_BE"; break;
2510                 case FUM_INVALID_ALIGN:
2511                         estr = "FUM_INVALID_ALIGN"; break;
2512                 default:
2513                         goto error;
2514                 }
2515                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2516                         estr, fault.func ? "VF" : "PF", fault.func,
2517                         fault.address, fault.specinfo);
2518         }
2519
2520         return 0;
2521 error:
2522         PMD_INIT_LOG(ERR, "Failed to handle fault event.");
2523         return err;
2524 }
2525
2526 /**
2527  * PF interrupt handler triggered by NIC for handling specific interrupt.
2528  *
2529  * @param handle
2530  *  Pointer to interrupt handle.
2531  * @param param
2532  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2533  *
2534  * @return
2535  *  void
2536  */
2537 static void
2538 fm10k_dev_interrupt_handler_pf(
2539                         struct rte_intr_handle *handle,
2540                         void *param)
2541 {
2542         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2543         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2544         uint32_t cause, status;
2545
2546         if (hw->mac.type != fm10k_mac_pf)
2547                 return;
2548
2549         cause = FM10K_READ_REG(hw, FM10K_EICR);
2550
2551         /* Handle PCI fault cases */
2552         if (cause & FM10K_EICR_FAULT_MASK) {
2553                 PMD_INIT_LOG(ERR, "INT: find fault!");
2554                 fm10k_dev_handle_fault(hw, cause);
2555         }
2556
2557         /* Handle switch up/down */
2558         if (cause & FM10K_EICR_SWITCHNOTREADY)
2559                 PMD_INIT_LOG(ERR, "INT: Switch is not ready");
2560
2561         if (cause & FM10K_EICR_SWITCHREADY)
2562                 PMD_INIT_LOG(INFO, "INT: Switch is ready");
2563
2564         /* Handle mailbox message */
2565         fm10k_mbx_lock(hw);
2566         hw->mbx.ops.process(hw, &hw->mbx);
2567         fm10k_mbx_unlock(hw);
2568
2569         /* Handle SRAM error */
2570         if (cause & FM10K_EICR_SRAMERROR) {
2571                 PMD_INIT_LOG(ERR, "INT: SRAM error on PEP");
2572
2573                 status = FM10K_READ_REG(hw, FM10K_SRAM_IP);
2574                 /* Write to clear pending bits */
2575                 FM10K_WRITE_REG(hw, FM10K_SRAM_IP, status);
2576
2577                 /* Todo: print out error message after shared code  updates */
2578         }
2579
2580         /* Clear these 3 events if having any */
2581         cause &= FM10K_EICR_SWITCHNOTREADY | FM10K_EICR_MAILBOX |
2582                  FM10K_EICR_SWITCHREADY;
2583         if (cause)
2584                 FM10K_WRITE_REG(hw, FM10K_EICR, cause);
2585
2586         /* Re-enable interrupt from device side */
2587         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2588                                         FM10K_ITR_MASK_CLEAR);
2589         /* Re-enable interrupt from host side */
2590         rte_intr_enable(handle);
2591 }
2592
2593 /**
2594  * VF interrupt handler triggered by NIC for handling specific interrupt.
2595  *
2596  * @param handle
2597  *  Pointer to interrupt handle.
2598  * @param param
2599  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2600  *
2601  * @return
2602  *  void
2603  */
2604 static void
2605 fm10k_dev_interrupt_handler_vf(
2606                         struct rte_intr_handle *handle,
2607                         void *param)
2608 {
2609         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2610         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2611
2612         if (hw->mac.type != fm10k_mac_vf)
2613                 return;
2614
2615         /* Handle mailbox message if lock is acquired */
2616         fm10k_mbx_lock(hw);
2617         hw->mbx.ops.process(hw, &hw->mbx);
2618         fm10k_mbx_unlock(hw);
2619
2620         /* Re-enable interrupt from device side */
2621         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2622                                         FM10K_ITR_MASK_CLEAR);
2623         /* Re-enable interrupt from host side */
2624         rte_intr_enable(handle);
2625 }
2626
2627 /* Mailbox message handler in VF */
2628 static const struct fm10k_msg_data fm10k_msgdata_vf[] = {
2629         FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
2630         FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),
2631         FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
2632         FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
2633 };
2634
2635 static int
2636 fm10k_setup_mbx_service(struct fm10k_hw *hw)
2637 {
2638         int err = 0;
2639
2640         /* Initialize mailbox lock */
2641         fm10k_mbx_initlock(hw);
2642
2643         /* Replace default message handler with new ones */
2644         if (hw->mac.type == fm10k_mac_vf)
2645                 err = hw->mbx.ops.register_handlers(&hw->mbx, fm10k_msgdata_vf);
2646
2647         if (err) {
2648                 PMD_INIT_LOG(ERR, "Failed to register mailbox handler.err:%d",
2649                                 err);
2650                 return err;
2651         }
2652         /* Connect to SM for PF device or PF for VF device */
2653         return hw->mbx.ops.connect(hw, &hw->mbx);
2654 }
2655
2656 static void
2657 fm10k_close_mbx_service(struct fm10k_hw *hw)
2658 {
2659         /* Disconnect from SM for PF device or PF for VF device */
2660         hw->mbx.ops.disconnect(hw, &hw->mbx);
2661 }
2662
2663 static const struct eth_dev_ops fm10k_eth_dev_ops = {
2664         .dev_configure          = fm10k_dev_configure,
2665         .dev_start              = fm10k_dev_start,
2666         .dev_stop               = fm10k_dev_stop,
2667         .dev_close              = fm10k_dev_close,
2668         .promiscuous_enable     = fm10k_dev_promiscuous_enable,
2669         .promiscuous_disable    = fm10k_dev_promiscuous_disable,
2670         .allmulticast_enable    = fm10k_dev_allmulticast_enable,
2671         .allmulticast_disable   = fm10k_dev_allmulticast_disable,
2672         .stats_get              = fm10k_stats_get,
2673         .xstats_get             = fm10k_xstats_get,
2674         .xstats_get_names       = fm10k_xstats_get_names,
2675         .stats_reset            = fm10k_stats_reset,
2676         .xstats_reset           = fm10k_stats_reset,
2677         .link_update            = fm10k_link_update,
2678         .dev_infos_get          = fm10k_dev_infos_get,
2679         .dev_supported_ptypes_get = fm10k_dev_supported_ptypes_get,
2680         .vlan_filter_set        = fm10k_vlan_filter_set,
2681         .vlan_offload_set       = fm10k_vlan_offload_set,
2682         .mac_addr_add           = fm10k_macaddr_add,
2683         .mac_addr_remove        = fm10k_macaddr_remove,
2684         .rx_queue_start         = fm10k_dev_rx_queue_start,
2685         .rx_queue_stop          = fm10k_dev_rx_queue_stop,
2686         .tx_queue_start         = fm10k_dev_tx_queue_start,
2687         .tx_queue_stop          = fm10k_dev_tx_queue_stop,
2688         .rx_queue_setup         = fm10k_rx_queue_setup,
2689         .rx_queue_release       = fm10k_rx_queue_release,
2690         .tx_queue_setup         = fm10k_tx_queue_setup,
2691         .tx_queue_release       = fm10k_tx_queue_release,
2692         .rx_descriptor_done     = fm10k_dev_rx_descriptor_done,
2693         .rx_queue_intr_enable   = fm10k_dev_rx_queue_intr_enable,
2694         .rx_queue_intr_disable  = fm10k_dev_rx_queue_intr_disable,
2695         .reta_update            = fm10k_reta_update,
2696         .reta_query             = fm10k_reta_query,
2697         .rss_hash_update        = fm10k_rss_hash_update,
2698         .rss_hash_conf_get      = fm10k_rss_hash_conf_get,
2699 };
2700
2701 static int ftag_check_handler(__rte_unused const char *key,
2702                 const char *value, __rte_unused void *opaque)
2703 {
2704         if (strcmp(value, "1"))
2705                 return -1;
2706
2707         return 0;
2708 }
2709
2710 static int
2711 fm10k_check_ftag(struct rte_devargs *devargs)
2712 {
2713         struct rte_kvargs *kvlist;
2714         const char *ftag_key = "enable_ftag";
2715
2716         if (devargs == NULL)
2717                 return 0;
2718
2719         kvlist = rte_kvargs_parse(devargs->args, NULL);
2720         if (kvlist == NULL)
2721                 return 0;
2722
2723         if (!rte_kvargs_count(kvlist, ftag_key)) {
2724                 rte_kvargs_free(kvlist);
2725                 return 0;
2726         }
2727         /* FTAG is enabled when there's key-value pair: enable_ftag=1 */
2728         if (rte_kvargs_process(kvlist, ftag_key,
2729                                 ftag_check_handler, NULL) < 0) {
2730                 rte_kvargs_free(kvlist);
2731                 return 0;
2732         }
2733         rte_kvargs_free(kvlist);
2734
2735         return 1;
2736 }
2737
2738 static void __attribute__((cold))
2739 fm10k_set_tx_function(struct rte_eth_dev *dev)
2740 {
2741         struct fm10k_tx_queue *txq;
2742         int i;
2743         int use_sse = 1;
2744         uint16_t tx_ftag_en = 0;
2745
2746         if (fm10k_check_ftag(dev->pci_dev->device.devargs))
2747                 tx_ftag_en = 1;
2748
2749         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2750                 txq = dev->data->tx_queues[i];
2751                 txq->tx_ftag_en = tx_ftag_en;
2752                 /* Check if Vector Tx is satisfied */
2753                 if (fm10k_tx_vec_condition_check(txq))
2754                         use_sse = 0;
2755         }
2756
2757         if (use_sse) {
2758                 PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2759                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2760                         txq = dev->data->tx_queues[i];
2761                         fm10k_txq_vec_setup(txq);
2762                 }
2763                 dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2764         } else {
2765                 dev->tx_pkt_burst = fm10k_xmit_pkts;
2766                 PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2767         }
2768 }
2769
2770 static void __attribute__((cold))
2771 fm10k_set_rx_function(struct rte_eth_dev *dev)
2772 {
2773         struct fm10k_dev_info *dev_info = FM10K_DEV_PRIVATE_TO_INFO(dev);
2774         uint16_t i, rx_using_sse;
2775         uint16_t rx_ftag_en = 0;
2776
2777         if (fm10k_check_ftag(dev->pci_dev->device.devargs))
2778                 rx_ftag_en = 1;
2779
2780         /* In order to allow Vector Rx there are a few configuration
2781          * conditions to be met.
2782          */
2783         if (!fm10k_rx_vec_condition_check(dev) &&
2784                         dev_info->rx_vec_allowed && !rx_ftag_en) {
2785                 if (dev->data->scattered_rx)
2786                         dev->rx_pkt_burst = fm10k_recv_scattered_pkts_vec;
2787                 else
2788                         dev->rx_pkt_burst = fm10k_recv_pkts_vec;
2789         } else if (dev->data->scattered_rx)
2790                 dev->rx_pkt_burst = fm10k_recv_scattered_pkts;
2791         else
2792                 dev->rx_pkt_burst = fm10k_recv_pkts;
2793
2794         rx_using_sse =
2795                 (dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec ||
2796                 dev->rx_pkt_burst == fm10k_recv_pkts_vec);
2797
2798         if (rx_using_sse)
2799                 PMD_INIT_LOG(DEBUG, "Use vector Rx func");
2800         else
2801                 PMD_INIT_LOG(DEBUG, "Use regular Rx func");
2802
2803         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2804                 struct fm10k_rx_queue *rxq = dev->data->rx_queues[i];
2805
2806                 rxq->rx_using_sse = rx_using_sse;
2807                 rxq->rx_ftag_en = rx_ftag_en;
2808         }
2809 }
2810
2811 static void
2812 fm10k_params_init(struct rte_eth_dev *dev)
2813 {
2814         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2815         struct fm10k_dev_info *info = FM10K_DEV_PRIVATE_TO_INFO(dev);
2816
2817         /* Inialize bus info. Normally we would call fm10k_get_bus_info(), but
2818          * there is no way to get link status without reading BAR4.  Until this
2819          * works, assume we have maximum bandwidth.
2820          * @todo - fix bus info
2821          */
2822         hw->bus_caps.speed = fm10k_bus_speed_8000;
2823         hw->bus_caps.width = fm10k_bus_width_pcie_x8;
2824         hw->bus_caps.payload = fm10k_bus_payload_512;
2825         hw->bus.speed = fm10k_bus_speed_8000;
2826         hw->bus.width = fm10k_bus_width_pcie_x8;
2827         hw->bus.payload = fm10k_bus_payload_256;
2828
2829         info->rx_vec_allowed = true;
2830 }
2831
2832 static int
2833 eth_fm10k_dev_init(struct rte_eth_dev *dev)
2834 {
2835         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2836         struct rte_pci_device *pdev = dev->pci_dev;
2837         struct rte_intr_handle *intr_handle = &pdev->intr_handle;
2838         int diag, i;
2839         struct fm10k_macvlan_filter_info *macvlan;
2840
2841         PMD_INIT_FUNC_TRACE();
2842
2843         dev->dev_ops = &fm10k_eth_dev_ops;
2844         dev->rx_pkt_burst = &fm10k_recv_pkts;
2845         dev->tx_pkt_burst = &fm10k_xmit_pkts;
2846
2847         /* only initialize in the primary process */
2848         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2849                 return 0;
2850
2851         rte_eth_copy_pci_info(dev, pdev);
2852
2853         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
2854         memset(macvlan, 0, sizeof(*macvlan));
2855         /* Vendor and Device ID need to be set before init of shared code */
2856         memset(hw, 0, sizeof(*hw));
2857         hw->device_id = pdev->id.device_id;
2858         hw->vendor_id = pdev->id.vendor_id;
2859         hw->subsystem_device_id = pdev->id.subsystem_device_id;
2860         hw->subsystem_vendor_id = pdev->id.subsystem_vendor_id;
2861         hw->revision_id = 0;
2862         hw->hw_addr = (void *)pdev->mem_resource[0].addr;
2863         if (hw->hw_addr == NULL) {
2864                 PMD_INIT_LOG(ERR, "Bad mem resource."
2865                         " Try to blacklist unused devices.");
2866                 return -EIO;
2867         }
2868
2869         /* Store fm10k_adapter pointer */
2870         hw->back = dev->data->dev_private;
2871
2872         /* Initialize the shared code */
2873         diag = fm10k_init_shared_code(hw);
2874         if (diag != FM10K_SUCCESS) {
2875                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
2876                 return -EIO;
2877         }
2878
2879         /* Initialize parameters */
2880         fm10k_params_init(dev);
2881
2882         /* Initialize the hw */
2883         diag = fm10k_init_hw(hw);
2884         if (diag != FM10K_SUCCESS) {
2885                 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
2886                 return -EIO;
2887         }
2888
2889         /* Initialize MAC address(es) */
2890         dev->data->mac_addrs = rte_zmalloc("fm10k",
2891                         ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM, 0);
2892         if (dev->data->mac_addrs == NULL) {
2893                 PMD_INIT_LOG(ERR, "Cannot allocate memory for MAC addresses");
2894                 return -ENOMEM;
2895         }
2896
2897         diag = fm10k_read_mac_addr(hw);
2898
2899         ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2900                         &dev->data->mac_addrs[0]);
2901
2902         if (diag != FM10K_SUCCESS ||
2903                 !is_valid_assigned_ether_addr(dev->data->mac_addrs)) {
2904
2905                 /* Generate a random addr */
2906                 eth_random_addr(hw->mac.addr);
2907                 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
2908                 ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2909                 &dev->data->mac_addrs[0]);
2910         }
2911
2912         /* Reset the hw statistics */
2913         fm10k_stats_reset(dev);
2914
2915         /* Reset the hw */
2916         diag = fm10k_reset_hw(hw);
2917         if (diag != FM10K_SUCCESS) {
2918                 PMD_INIT_LOG(ERR, "Hardware reset failed: %d", diag);
2919                 return -EIO;
2920         }
2921
2922         /* Setup mailbox service */
2923         diag = fm10k_setup_mbx_service(hw);
2924         if (diag != FM10K_SUCCESS) {
2925                 PMD_INIT_LOG(ERR, "Failed to setup mailbox: %d", diag);
2926                 return -EIO;
2927         }
2928
2929         /*PF/VF has different interrupt handling mechanism */
2930         if (hw->mac.type == fm10k_mac_pf) {
2931                 /* register callback func to eal lib */
2932                 rte_intr_callback_register(intr_handle,
2933                         fm10k_dev_interrupt_handler_pf, (void *)dev);
2934
2935                 /* enable MISC interrupt */
2936                 fm10k_dev_enable_intr_pf(dev);
2937         } else { /* VF */
2938                 rte_intr_callback_register(intr_handle,
2939                         fm10k_dev_interrupt_handler_vf, (void *)dev);
2940
2941                 fm10k_dev_enable_intr_vf(dev);
2942         }
2943
2944         /* Enable intr after callback registered */
2945         rte_intr_enable(intr_handle);
2946
2947         hw->mac.ops.update_int_moderator(hw);
2948
2949         /* Make sure Switch Manager is ready before going forward. */
2950         if (hw->mac.type == fm10k_mac_pf) {
2951                 int switch_ready = 0;
2952
2953                 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
2954                         fm10k_mbx_lock(hw);
2955                         hw->mac.ops.get_host_state(hw, &switch_ready);
2956                         fm10k_mbx_unlock(hw);
2957                         if (switch_ready)
2958                                 break;
2959                         /* Delay some time to acquire async LPORT_MAP info. */
2960                         rte_delay_us(WAIT_SWITCH_MSG_US);
2961                 }
2962
2963                 if (switch_ready == 0) {
2964                         PMD_INIT_LOG(ERR, "switch is not ready");
2965                         return -1;
2966                 }
2967         }
2968
2969         /*
2970          * Below function will trigger operations on mailbox, acquire lock to
2971          * avoid race condition from interrupt handler. Operations on mailbox
2972          * FIFO will trigger interrupt to PF/SM, in which interrupt handler
2973          * will handle and generate an interrupt to our side. Then,  FIFO in
2974          * mailbox will be touched.
2975          */
2976         fm10k_mbx_lock(hw);
2977         /* Enable port first */
2978         hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
2979                                         MAX_LPORT_NUM, 1);
2980
2981         /* Set unicast mode by default. App can change to other mode in other
2982          * API func.
2983          */
2984         hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
2985                                         FM10K_XCAST_MODE_NONE);
2986
2987         fm10k_mbx_unlock(hw);
2988
2989         /* Make sure default VID is ready before going forward. */
2990         if (hw->mac.type == fm10k_mac_pf) {
2991                 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
2992                         if (hw->mac.default_vid)
2993                                 break;
2994                         /* Delay some time to acquire async port VLAN info. */
2995                         rte_delay_us(WAIT_SWITCH_MSG_US);
2996                 }
2997
2998                 if (!hw->mac.default_vid) {
2999                         PMD_INIT_LOG(ERR, "default VID is not ready");
3000                         return -1;
3001                 }
3002         }
3003
3004         /* Add default mac address */
3005         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
3006                 MAIN_VSI_POOL_NUMBER);
3007
3008         return 0;
3009 }
3010
3011 static int
3012 eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
3013 {
3014         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3015         struct rte_pci_device *pdev = dev->pci_dev;
3016         struct rte_intr_handle *intr_handle = &pdev->intr_handle;
3017         PMD_INIT_FUNC_TRACE();
3018
3019         /* only uninitialize in the primary process */
3020         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3021                 return 0;
3022
3023         /* safe to close dev here */
3024         fm10k_dev_close(dev);
3025
3026         dev->dev_ops = NULL;
3027         dev->rx_pkt_burst = NULL;
3028         dev->tx_pkt_burst = NULL;
3029
3030         /* disable uio/vfio intr */
3031         rte_intr_disable(intr_handle);
3032
3033         /*PF/VF has different interrupt handling mechanism */
3034         if (hw->mac.type == fm10k_mac_pf) {
3035                 /* disable interrupt */
3036                 fm10k_dev_disable_intr_pf(dev);
3037
3038                 /* unregister callback func to eal lib */
3039                 rte_intr_callback_unregister(intr_handle,
3040                         fm10k_dev_interrupt_handler_pf, (void *)dev);
3041         } else {
3042                 /* disable interrupt */
3043                 fm10k_dev_disable_intr_vf(dev);
3044
3045                 rte_intr_callback_unregister(intr_handle,
3046                         fm10k_dev_interrupt_handler_vf, (void *)dev);
3047         }
3048
3049         /* free mac memory */
3050         if (dev->data->mac_addrs) {
3051                 rte_free(dev->data->mac_addrs);
3052                 dev->data->mac_addrs = NULL;
3053         }
3054
3055         memset(hw, 0, sizeof(*hw));
3056
3057         return 0;
3058 }
3059
3060 /*
3061  * The set of PCI devices this driver supports. This driver will enable both PF
3062  * and SRIOV-VF devices.
3063  */
3064 static const struct rte_pci_id pci_id_fm10k_map[] = {
3065         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_PF) },
3066         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_SDI_FM10420_QDA2) },
3067         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_VF) },
3068         { .vendor_id = 0, /* sentinel */ },
3069 };
3070
3071 static struct eth_driver rte_pmd_fm10k = {
3072         .pci_drv = {
3073                 .id_table = pci_id_fm10k_map,
3074                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3075                         RTE_PCI_DRV_DETACHABLE,
3076                 .probe = rte_eth_dev_pci_probe,
3077                 .remove = rte_eth_dev_pci_remove,
3078         },
3079         .eth_dev_init = eth_fm10k_dev_init,
3080         .eth_dev_uninit = eth_fm10k_dev_uninit,
3081         .dev_private_size = sizeof(struct fm10k_adapter),
3082 };
3083
3084 RTE_PMD_REGISTER_PCI(net_fm10k, rte_pmd_fm10k.pci_drv);
3085 RTE_PMD_REGISTER_PCI_TABLE(net_fm10k, pci_id_fm10k_map);
3086 RTE_PMD_REGISTER_KMOD_DEP(net_fm10k, "* igb_uio | uio_pci_generic | vfio");