drivers/net/fm10k/fm10k_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <rte_ethdev.h>
  35 #include <rte_malloc.h>
  36 #include <rte_memzone.h>
  37 #include <rte_string_fns.h>
  38 #include <rte_dev.h>
  39 #include <rte_spinlock.h>
  40 #include <rte_kvargs.h>
  41
  42 #include "fm10k.h"
  43 #include "base/fm10k_api.h"
  44
  45 /* Default delay to acquire mailbox lock */
  46 #define FM10K_MBXLOCK_DELAY_US 20
  47 #define UINT64_LOWER_32BITS_MASK 0x00000000ffffffffULL
  48
  49 #define MAIN_VSI_POOL_NUMBER 0
  50
  51 /* Max try times to acquire switch status */
  52 #define MAX_QUERY_SWITCH_STATE_TIMES 10
  53 /* Wait interval to get switch status */
  54 #define WAIT_SWITCH_MSG_US    100000
  55 /* Number of chars per uint32 type */
  56 #define CHARS_PER_UINT32 (sizeof(uint32_t))
  57 #define BIT_MASK_PER_UINT32 ((1 << CHARS_PER_UINT32) - 1)
  58
  59 /* default 1:1 map from queue ID to interrupt vector ID */
  60 #define Q2V(dev, queue_id) (dev->pci_dev->intr_handle.intr_vec[queue_id])
  61
  62 /* First 64 Logical ports for PF/VMDQ, second 64 for Flow director */
  63 #define MAX_LPORT_NUM    128
  64 #define GLORT_FD_Q_BASE  0x40
  65 #define GLORT_PF_MASK    0xFFC0
  66 #define GLORT_FD_MASK    GLORT_PF_MASK
  67 #define GLORT_FD_INDEX   GLORT_FD_Q_BASE
  68
  69 static void fm10k_close_mbx_service(struct fm10k_hw *hw);
  70 static void fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev);
  71 static void fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev);
  72 static void fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev);
  73 static void fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev);
  74 static inline int fm10k_glort_valid(struct fm10k_hw *hw);
  75 static int
  76 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
  77 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
  78         const u8 *mac, bool add, uint32_t pool);
  79 static void fm10k_tx_queue_release(void *queue);
  80 static void fm10k_rx_queue_release(void *queue);
  81 static void fm10k_set_rx_function(struct rte_eth_dev *dev);
  82 static void fm10k_set_tx_function(struct rte_eth_dev *dev);
  83 static int fm10k_check_ftag(struct rte_devargs *devargs);
  84
  85 struct fm10k_xstats_name_off {
  86         char name[RTE_ETH_XSTATS_NAME_SIZE];
  87         unsigned offset;
  88 };
  89
  90 struct fm10k_xstats_name_off fm10k_hw_stats_strings[] = {
  91         {"completion_timeout_count", offsetof(struct fm10k_hw_stats, timeout)},
  92         {"unsupported_requests_count", offsetof(struct fm10k_hw_stats, ur)},
  93         {"completer_abort_count", offsetof(struct fm10k_hw_stats, ca)},
  94         {"unsupported_message_count", offsetof(struct fm10k_hw_stats, um)},
  95         {"checksum_error_count", offsetof(struct fm10k_hw_stats, xec)},
  96         {"vlan_dropped", offsetof(struct fm10k_hw_stats, vlan_drop)},
  97         {"loopback_dropped", offsetof(struct fm10k_hw_stats, loopback_drop)},
  98         {"rx_mbuf_allocation_errors", offsetof(struct fm10k_hw_stats,
  99                 nodesc_drop)},
 100 };
 101
 102 #define FM10K_NB_HW_XSTATS (sizeof(fm10k_hw_stats_strings) / \
 103                 sizeof(fm10k_hw_stats_strings[0]))
 104
 105 struct fm10k_xstats_name_off fm10k_hw_stats_rx_q_strings[] = {
 106         {"packets", offsetof(struct fm10k_hw_stats_q, rx_packets)},
 107         {"bytes", offsetof(struct fm10k_hw_stats_q, rx_bytes)},
 108         {"dropped", offsetof(struct fm10k_hw_stats_q, rx_drops)},
 109 };
 110
 111 #define FM10K_NB_RX_Q_XSTATS (sizeof(fm10k_hw_stats_rx_q_strings) / \
 112                 sizeof(fm10k_hw_stats_rx_q_strings[0]))
 113
 114 struct fm10k_xstats_name_off fm10k_hw_stats_tx_q_strings[] = {
 115         {"packets", offsetof(struct fm10k_hw_stats_q, tx_packets)},
 116         {"bytes", offsetof(struct fm10k_hw_stats_q, tx_bytes)},
 117 };
 118
 119 #define FM10K_NB_TX_Q_XSTATS (sizeof(fm10k_hw_stats_tx_q_strings) / \
 120                 sizeof(fm10k_hw_stats_tx_q_strings[0]))
 121
 122 #define FM10K_NB_XSTATS (FM10K_NB_HW_XSTATS + FM10K_MAX_QUEUES_PF * \
 123                 (FM10K_NB_RX_Q_XSTATS + FM10K_NB_TX_Q_XSTATS))
 124 static int
 125 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 126
 127 static void
 128 fm10k_mbx_initlock(struct fm10k_hw *hw)
 129 {
 130         rte_spinlock_init(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
 131 }
 132
 133 static void
 134 fm10k_mbx_lock(struct fm10k_hw *hw)
 135 {
 136         while (!rte_spinlock_trylock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back)))
 137                 rte_delay_us(FM10K_MBXLOCK_DELAY_US);
 138 }
 139
 140 static void
 141 fm10k_mbx_unlock(struct fm10k_hw *hw)
 142 {
 143         rte_spinlock_unlock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
 144 }
 145
 146 /* Stubs needed for linkage when vPMD is disabled */
 147 int __attribute__((weak))
 148 fm10k_rx_vec_condition_check(__rte_unused struct rte_eth_dev *dev)
 149 {
 150         return -1;
 151 }
 152
 153 uint16_t __attribute__((weak))
 154 fm10k_recv_pkts_vec(
 155         __rte_unused void *rx_queue,
 156         __rte_unused struct rte_mbuf **rx_pkts,
 157         __rte_unused uint16_t nb_pkts)
 158 {
 159         return 0;
 160 }
 161
 162 uint16_t __attribute__((weak))
 163 fm10k_recv_scattered_pkts_vec(
 164                 __rte_unused void *rx_queue,
 165                 __rte_unused struct rte_mbuf **rx_pkts,
 166                 __rte_unused uint16_t nb_pkts)
 167 {
 168         return 0;
 169 }
 170
 171 int __attribute__((weak))
 172 fm10k_rxq_vec_setup(__rte_unused struct fm10k_rx_queue *rxq)
 173
 174 {
 175         return -1;
 176 }
 177
 178 void __attribute__((weak))
 179 fm10k_rx_queue_release_mbufs_vec(
 180                 __rte_unused struct fm10k_rx_queue *rxq)
 181 {
 182         return;
 183 }
 184
 185 void __attribute__((weak))
 186 fm10k_txq_vec_setup(__rte_unused struct fm10k_tx_queue *txq)
 187 {
 188         return;
 189 }
 190
 191 int __attribute__((weak))
 192 fm10k_tx_vec_condition_check(__rte_unused struct fm10k_tx_queue *txq)
 193 {
 194         return -1;
 195 }
 196
 197 uint16_t __attribute__((weak))
 198 fm10k_xmit_pkts_vec(__rte_unused void *tx_queue,
 199                 __rte_unused struct rte_mbuf **tx_pkts,
 200                 __rte_unused uint16_t nb_pkts)
 201 {
 202         return 0;
 203 }
 204
 205 /*
 206  * reset queue to initial state, allocate software buffers used when starting
 207  * device.
 208  * return 0 on success
 209  * return -ENOMEM if buffers cannot be allocated
 210  * return -EINVAL if buffers do not satisfy alignment condition
 211  */
 212 static inline int
 213 rx_queue_reset(struct fm10k_rx_queue *q)
 214 {
 215         static const union fm10k_rx_desc zero = {{0} };
 216         uint64_t dma_addr;
 217         int i, diag;
 218         PMD_INIT_FUNC_TRACE();
 219
 220         diag = rte_mempool_get_bulk(q->mp, (void **)q->sw_ring, q->nb_desc);
 221         if (diag != 0)
 222                 return -ENOMEM;
 223
 224         for (i = 0; i < q->nb_desc; ++i) {
 225                 fm10k_pktmbuf_reset(q->sw_ring[i], q->port_id);
 226                 if (!fm10k_addr_alignment_valid(q->sw_ring[i])) {
 227                         rte_mempool_put_bulk(q->mp, (void **)q->sw_ring,
 228                                                 q->nb_desc);
 229                         return -EINVAL;
 230                 }
 231                 dma_addr = MBUF_DMA_ADDR_DEFAULT(q->sw_ring[i]);
 232                 q->hw_ring[i].q.pkt_addr = dma_addr;
 233                 q->hw_ring[i].q.hdr_addr = dma_addr;
 234         }
 235
 236         /* initialize extra software ring entries. Space for these extra
 237          * entries is always allocated.
 238          */
 239         memset(&q->fake_mbuf, 0x0, sizeof(q->fake_mbuf));
 240         for (i = 0; i < q->nb_fake_desc; ++i) {
 241                 q->sw_ring[q->nb_desc + i] = &q->fake_mbuf;
 242                 q->hw_ring[q->nb_desc + i] = zero;
 243         }
 244
 245         q->next_dd = 0;
 246         q->next_alloc = 0;
 247         q->next_trigger = q->alloc_thresh - 1;
 248         FM10K_PCI_REG_WRITE(q->tail_ptr, q->nb_desc - 1);
 249         q->rxrearm_start = 0;
 250         q->rxrearm_nb = 0;
 251
 252         return 0;
 253 }
 254
 255 /*
 256  * clean queue, descriptor rings, free software buffers used when stopping
 257  * device.
 258  */
 259 static inline void
 260 rx_queue_clean(struct fm10k_rx_queue *q)
 261 {
 262         union fm10k_rx_desc zero = {.q = {0, 0, 0, 0} };
 263         uint32_t i;
 264         PMD_INIT_FUNC_TRACE();
 265
 266         /* zero descriptor rings */
 267         for (i = 0; i < q->nb_desc; ++i)
 268                 q->hw_ring[i] = zero;
 269
 270         /* zero faked descriptors */
 271         for (i = 0; i < q->nb_fake_desc; ++i)
 272                 q->hw_ring[q->nb_desc + i] = zero;
 273
 274         /* vPMD driver has a different way of releasing mbufs. */
 275         if (q->rx_using_sse) {
 276                 fm10k_rx_queue_release_mbufs_vec(q);
 277                 return;
 278         }
 279
 280         /* free software buffers */
 281         for (i = 0; i < q->nb_desc; ++i) {
 282                 if (q->sw_ring[i]) {
 283                         rte_pktmbuf_free_seg(q->sw_ring[i]);
 284                         q->sw_ring[i] = NULL;
 285                 }
 286         }
 287 }
 288
 289 /*
 290  * free all queue memory used when releasing the queue (i.e. configure)
 291  */
 292 static inline void
 293 rx_queue_free(struct fm10k_rx_queue *q)
 294 {
 295         PMD_INIT_FUNC_TRACE();
 296         if (q) {
 297                 PMD_INIT_LOG(DEBUG, "Freeing rx queue %p", q);
 298                 rx_queue_clean(q);
 299                 if (q->sw_ring) {
 300                         rte_free(q->sw_ring);
 301                         q->sw_ring = NULL;
 302                 }
 303                 rte_free(q);
 304                 q = NULL;
 305         }
 306 }
 307
 308 /*
 309  * disable RX queue, wait unitl HW finished necessary flush operation
 310  */
 311 static inline int
 312 rx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
 313 {
 314         uint32_t reg, i;
 315
 316         reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
 317         FM10K_WRITE_REG(hw, FM10K_RXQCTL(qnum),
 318                         reg & ~FM10K_RXQCTL_ENABLE);
 319
 320         /* Wait 100us at most */
 321         for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
 322                 rte_delay_us(1);
 323                 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
 324                 if (!(reg & FM10K_RXQCTL_ENABLE))
 325                         break;
 326         }
 327
 328         if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
 329                 return -1;
 330
 331         return 0;
 332 }
 333
 334 /*
 335  * reset queue to initial state, allocate software buffers used when starting
 336  * device
 337  */
 338 static inline void
 339 tx_queue_reset(struct fm10k_tx_queue *q)
 340 {
 341         PMD_INIT_FUNC_TRACE();
 342         q->last_free = 0;
 343         q->next_free = 0;
 344         q->nb_used = 0;
 345         q->nb_free = q->nb_desc - 1;
 346         fifo_reset(&q->rs_tracker, (q->nb_desc + 1) / q->rs_thresh);
 347         FM10K_PCI_REG_WRITE(q->tail_ptr, 0);
 348 }
 349
 350 /*
 351  * clean queue, descriptor rings, free software buffers used when stopping
 352  * device
 353  */
 354 static inline void
 355 tx_queue_clean(struct fm10k_tx_queue *q)
 356 {
 357         struct fm10k_tx_desc zero = {0, 0, 0, 0, 0, 0};
 358         uint32_t i;
 359         PMD_INIT_FUNC_TRACE();
 360
 361         /* zero descriptor rings */
 362         for (i = 0; i < q->nb_desc; ++i)
 363                 q->hw_ring[i] = zero;
 364
 365         /* free software buffers */
 366         for (i = 0; i < q->nb_desc; ++i) {
 367                 if (q->sw_ring[i]) {
 368                         rte_pktmbuf_free_seg(q->sw_ring[i]);
 369                         q->sw_ring[i] = NULL;
 370                 }
 371         }
 372 }
 373
 374 /*
 375  * free all queue memory used when releasing the queue (i.e. configure)
 376  */
 377 static inline void
 378 tx_queue_free(struct fm10k_tx_queue *q)
 379 {
 380         PMD_INIT_FUNC_TRACE();
 381         if (q) {
 382                 PMD_INIT_LOG(DEBUG, "Freeing tx queue %p", q);
 383                 tx_queue_clean(q);
 384                 if (q->rs_tracker.list) {
 385                         rte_free(q->rs_tracker.list);
 386                         q->rs_tracker.list = NULL;
 387                 }
 388                 if (q->sw_ring) {
 389                         rte_free(q->sw_ring);
 390                         q->sw_ring = NULL;
 391                 }
 392                 rte_free(q);
 393                 q = NULL;
 394         }
 395 }
 396
 397 /*
 398  * disable TX queue, wait unitl HW finished necessary flush operation
 399  */
 400 static inline int
 401 tx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
 402 {
 403         uint32_t reg, i;
 404
 405         reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
 406         FM10K_WRITE_REG(hw, FM10K_TXDCTL(qnum),
 407                         reg & ~FM10K_TXDCTL_ENABLE);
 408
 409         /* Wait 100us at most */
 410         for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
 411                 rte_delay_us(1);
 412                 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
 413                 if (!(reg & FM10K_TXDCTL_ENABLE))
 414                         break;
 415         }
 416
 417         if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
 418                 return -1;
 419
 420         return 0;
 421 }
 422
 423 static int
 424 fm10k_check_mq_mode(struct rte_eth_dev *dev)
 425 {
 426         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 427         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 428         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 429         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 430
 431         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 432
 433         if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
 434                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
 435                 return -EINVAL;
 436         }
 437
 438         if (!(rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG))
 439                 return 0;
 440
 441         if (hw->mac.type == fm10k_mac_vf) {
 442                 PMD_INIT_LOG(ERR, "VMDQ mode is not supported in VF.");
 443                 return -EINVAL;
 444         }
 445
 446         /* Check VMDQ queue pool number */
 447         if (vmdq_conf->nb_queue_pools >
 448                         sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT ||
 449                         vmdq_conf->nb_queue_pools > nb_rx_q) {
 450                 PMD_INIT_LOG(ERR, "Too many of queue pools: %d",
 451                         vmdq_conf->nb_queue_pools);
 452                 return -EINVAL;
 453         }
 454
 455         return 0;
 456 }
 457
 458 static const struct fm10k_txq_ops def_txq_ops = {
 459         .reset = tx_queue_reset,
 460 };
 461
 462 static int
 463 fm10k_dev_configure(struct rte_eth_dev *dev)
 464 {
 465         int ret;
 466
 467         PMD_INIT_FUNC_TRACE();
 468
 469         if (dev->data->dev_conf.rxmode.hw_strip_crc == 0)
 470                 PMD_INIT_LOG(WARNING, "fm10k always strip CRC");
 471         /* multipe queue mode checking */
 472         ret  = fm10k_check_mq_mode(dev);
 473         if (ret != 0) {
 474                 PMD_DRV_LOG(ERR, "fm10k_check_mq_mode fails with %d.",
 475                             ret);
 476                 return ret;
 477         }
 478
 479         return 0;
 480 }
 481
 482 /* fls = find last set bit = 32 minus the number of leading zeros */
 483 #ifndef fls
 484 #define fls(x) (((x) == 0) ? 0 : (32 - __builtin_clz((x))))
 485 #endif
 486
 487 static void
 488 fm10k_dev_vmdq_rx_configure(struct rte_eth_dev *dev)
 489 {
 490         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 491         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 492         uint32_t i;
 493
 494         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 495
 496         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
 497                 if (!vmdq_conf->pool_map[i].pools)
 498                         continue;
 499                 fm10k_mbx_lock(hw);
 500                 fm10k_update_vlan(hw, vmdq_conf->pool_map[i].vlan_id, 0, true);
 501                 fm10k_mbx_unlock(hw);
 502         }
 503 }
 504
 505 static void
 506 fm10k_dev_pf_main_vsi_reset(struct rte_eth_dev *dev)
 507 {
 508         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 509
 510         /* Add default mac address */
 511         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
 512                 MAIN_VSI_POOL_NUMBER);
 513 }
 514
 515 static void
 516 fm10k_dev_rss_configure(struct rte_eth_dev *dev)
 517 {
 518         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 519         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 520         uint32_t mrqc, *key, i, reta, j;
 521         uint64_t hf;
 522
 523 #define RSS_KEY_SIZE 40
 524         static uint8_t rss_intel_key[RSS_KEY_SIZE] = {
 525                 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
 526                 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
 527                 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
 528                 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
 529                 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
 530         };
 531
 532         if (dev->data->nb_rx_queues == 1 ||
 533             dev_conf->rxmode.mq_mode != ETH_MQ_RX_RSS ||
 534             dev_conf->rx_adv_conf.rss_conf.rss_hf == 0) {
 535                 FM10K_WRITE_REG(hw, FM10K_MRQC(0), 0);
 536                 return;
 537         }
 538
 539         /* random key is rss_intel_key (default) or user provided (rss_key) */
 540         if (dev_conf->rx_adv_conf.rss_conf.rss_key == NULL)
 541                 key = (uint32_t *)rss_intel_key;
 542         else
 543                 key = (uint32_t *)dev_conf->rx_adv_conf.rss_conf.rss_key;
 544
 545         /* Now fill our hash function seeds, 4 bytes at a time */
 546         for (i = 0; i < RSS_KEY_SIZE / sizeof(*key); ++i)
 547                 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
 548
 549         /*
 550          * Fill in redirection table
 551          * The byte-swap is needed because NIC registers are in
 552          * little-endian order.
 553          */
 554         reta = 0;
 555         for (i = 0, j = 0; i < FM10K_MAX_RSS_INDICES; i++, j++) {
 556                 if (j == dev->data->nb_rx_queues)
 557                         j = 0;
 558                 reta = (reta << CHAR_BIT) | j;
 559                 if ((i & 3) == 3)
 560                         FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2),
 561                                         rte_bswap32(reta));
 562         }
 563
 564         /*
 565          * Generate RSS hash based on packet types, TCP/UDP
 566          * port numbers and/or IPv4/v6 src and dst addresses
 567          */
 568         hf = dev_conf->rx_adv_conf.rss_conf.rss_hf;
 569         mrqc = 0;
 570         mrqc |= (hf & ETH_RSS_IPV4)              ? FM10K_MRQC_IPV4     : 0;
 571         mrqc |= (hf & ETH_RSS_IPV6)              ? FM10K_MRQC_IPV6     : 0;
 572         mrqc |= (hf & ETH_RSS_IPV6_EX)           ? FM10K_MRQC_IPV6     : 0;
 573         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? FM10K_MRQC_TCP_IPV4 : 0;
 574         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? FM10K_MRQC_TCP_IPV6 : 0;
 575         mrqc |= (hf & ETH_RSS_IPV6_TCP_EX)       ? FM10K_MRQC_TCP_IPV6 : 0;
 576         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? FM10K_MRQC_UDP_IPV4 : 0;
 577         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? FM10K_MRQC_UDP_IPV6 : 0;
 578         mrqc |= (hf & ETH_RSS_IPV6_UDP_EX)       ? FM10K_MRQC_UDP_IPV6 : 0;
 579
 580         if (mrqc == 0) {
 581                 PMD_INIT_LOG(ERR, "Specified RSS mode 0x%"PRIx64"is not"
 582                         "supported", hf);
 583                 return;
 584         }
 585
 586         FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
 587 }
 588
 589 static void
 590 fm10k_dev_logic_port_update(struct rte_eth_dev *dev, uint16_t nb_lport_new)
 591 {
 592         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 593         uint32_t i;
 594
 595         for (i = 0; i < nb_lport_new; i++) {
 596                 /* Set unicast mode by default. App can change
 597                  * to other mode in other API func.
 598                  */
 599                 fm10k_mbx_lock(hw);
 600                 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map + i,
 601                         FM10K_XCAST_MODE_NONE);
 602                 fm10k_mbx_unlock(hw);
 603         }
 604 }
 605
 606 static void
 607 fm10k_dev_mq_rx_configure(struct rte_eth_dev *dev)
 608 {
 609         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 610         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 611         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 612         struct fm10k_macvlan_filter_info *macvlan;
 613         uint16_t nb_queue_pools = 0; /* pool number in configuration */
 614         uint16_t nb_lport_new;
 615
 616         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
 617         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 618
 619         fm10k_dev_rss_configure(dev);
 620
 621         /* only PF supports VMDQ */
 622         if (hw->mac.type != fm10k_mac_pf)
 623                 return;
 624
 625         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
 626                 nb_queue_pools = vmdq_conf->nb_queue_pools;
 627
 628         /* no pool number change, no need to update logic port and VLAN/MAC */
 629         if (macvlan->nb_queue_pools == nb_queue_pools)
 630                 return;
 631
 632         nb_lport_new = nb_queue_pools ? nb_queue_pools : 1;
 633         fm10k_dev_logic_port_update(dev, nb_lport_new);
 634
 635         /* reset MAC/VLAN as it's based on VMDQ or PF main VSI */
 636         memset(dev->data->mac_addrs, 0,
 637                 ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM);
 638         ether_addr_copy((const struct ether_addr *)hw->mac.addr,
 639                 &dev->data->mac_addrs[0]);
 640         memset(macvlan, 0, sizeof(*macvlan));
 641         macvlan->nb_queue_pools = nb_queue_pools;
 642
 643         if (nb_queue_pools)
 644                 fm10k_dev_vmdq_rx_configure(dev);
 645         else
 646                 fm10k_dev_pf_main_vsi_reset(dev);
 647 }
 648
 649 static int
 650 fm10k_dev_tx_init(struct rte_eth_dev *dev)
 651 {
 652         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 653         int i, ret;
 654         struct fm10k_tx_queue *txq;
 655         uint64_t base_addr;
 656         uint32_t size;
 657
 658         /* Disable TXINT to avoid possible interrupt */
 659         for (i = 0; i < hw->mac.max_queues; i++)
 660                 FM10K_WRITE_REG(hw, FM10K_TXINT(i),
 661                                 3 << FM10K_TXINT_TIMER_SHIFT);
 662
 663         /* Setup TX queue */
 664         for (i = 0; i < dev->data->nb_tx_queues; ++i) {
 665                 txq = dev->data->tx_queues[i];
 666                 base_addr = txq->hw_ring_phys_addr;
 667                 size = txq->nb_desc * sizeof(struct fm10k_tx_desc);
 668
 669                 /* disable queue to avoid issues while updating state */
 670                 ret = tx_queue_disable(hw, i);
 671                 if (ret) {
 672                         PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
 673                         return -1;
 674                 }
 675                 /* Enable use of FTAG bit in TX descriptor, PFVTCTL
 676                  * register is read-only for VF.
 677                  */
 678                 if (fm10k_check_ftag(dev->pci_dev->devargs)) {
 679                         if (hw->mac.type == fm10k_mac_pf) {
 680                                 FM10K_WRITE_REG(hw, FM10K_PFVTCTL(i),
 681                                                 FM10K_PFVTCTL_FTAG_DESC_ENABLE);
 682                                 PMD_INIT_LOG(DEBUG, "FTAG mode is enabled");
 683                         } else {
 684                                 PMD_INIT_LOG(ERR, "VF FTAG is not supported.");
 685                                 return -ENOTSUP;
 686                         }
 687                 }
 688
 689                 /* set location and size for descriptor ring */
 690                 FM10K_WRITE_REG(hw, FM10K_TDBAL(i),
 691                                 base_addr & UINT64_LOWER_32BITS_MASK);
 692                 FM10K_WRITE_REG(hw, FM10K_TDBAH(i),
 693                                 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
 694                 FM10K_WRITE_REG(hw, FM10K_TDLEN(i), size);
 695
 696                 /* assign default SGLORT for each TX queue */
 697                 FM10K_WRITE_REG(hw, FM10K_TX_SGLORT(i), hw->mac.dglort_map);
 698         }
 699
 700         /* set up vector or scalar TX function as appropriate */
 701         fm10k_set_tx_function(dev);
 702
 703         return 0;
 704 }
 705
 706 static int
 707 fm10k_dev_rx_init(struct rte_eth_dev *dev)
 708 {
 709         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 710         struct fm10k_macvlan_filter_info *macvlan;
 711         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
 712         int i, ret;
 713         struct fm10k_rx_queue *rxq;
 714         uint64_t base_addr;
 715         uint32_t size;
 716         uint32_t rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
 717         uint32_t logic_port = hw->mac.dglort_map;
 718         uint16_t buf_size;
 719         uint16_t queue_stride = 0;
 720
 721         /* enable RXINT for interrupt mode */
 722         i = 0;
 723         if (rte_intr_dp_is_en(intr_handle)) {
 724                 for (; i < dev->data->nb_rx_queues; i++) {
 725                         FM10K_WRITE_REG(hw, FM10K_RXINT(i), Q2V(dev, i));
 726                         if (hw->mac.type == fm10k_mac_pf)
 727                                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, i)),
 728                                         FM10K_ITR_AUTOMASK |
 729                                         FM10K_ITR_MASK_CLEAR);
 730                         else
 731                                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, i)),
 732                                         FM10K_ITR_AUTOMASK |
 733                                         FM10K_ITR_MASK_CLEAR);
 734                 }
 735         }
 736         /* Disable other RXINT to avoid possible interrupt */
 737         for (; i < hw->mac.max_queues; i++)
 738                 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
 739                         3 << FM10K_RXINT_TIMER_SHIFT);
 740
 741         /* Setup RX queues */
 742         for (i = 0; i < dev->data->nb_rx_queues; ++i) {
 743                 rxq = dev->data->rx_queues[i];
 744                 base_addr = rxq->hw_ring_phys_addr;
 745                 size = rxq->nb_desc * sizeof(union fm10k_rx_desc);
 746
 747                 /* disable queue to avoid issues while updating state */
 748                 ret = rx_queue_disable(hw, i);
 749                 if (ret) {
 750                         PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
 751                         return -1;
 752                 }
 753
 754                 /* Setup the Base and Length of the Rx Descriptor Ring */
 755                 FM10K_WRITE_REG(hw, FM10K_RDBAL(i),
 756                                 base_addr & UINT64_LOWER_32BITS_MASK);
 757                 FM10K_WRITE_REG(hw, FM10K_RDBAH(i),
 758                                 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
 759                 FM10K_WRITE_REG(hw, FM10K_RDLEN(i), size);
 760
 761                 /* Configure the Rx buffer size for one buff without split */
 762                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 763                         RTE_PKTMBUF_HEADROOM);
 764                 /* As RX buffer is aligned to 512B within mbuf, some bytes are
 765                  * reserved for this purpose, and the worst case could be 511B.
 766                  * But SRR reg assumes all buffers have the same size. In order
 767                  * to fill the gap, we'll have to consider the worst case and
 768                  * assume 512B is reserved. If we don't do so, it's possible
 769                  * for HW to overwrite data to next mbuf.
 770                  */
 771                 buf_size -= FM10K_RX_DATABUF_ALIGN;
 772
 773                 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i),
 774                                 (buf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT) |
 775                                 FM10K_SRRCTL_LOOPBACK_SUPPRESS);
 776
 777                 /* It adds dual VLAN length for supporting dual VLAN */
 778                 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
 779                                 2 * FM10K_VLAN_TAG_SIZE) > buf_size ||
 780                         dev->data->dev_conf.rxmode.enable_scatter) {
 781                         uint32_t reg;
 782                         dev->data->scattered_rx = 1;
 783                         reg = FM10K_READ_REG(hw, FM10K_SRRCTL(i));
 784                         reg |= FM10K_SRRCTL_BUFFER_CHAINING_EN;
 785                         FM10K_WRITE_REG(hw, FM10K_SRRCTL(i), reg);
 786                 }
 787
 788                 /* Enable drop on empty, it's RO for VF */
 789                 if (hw->mac.type == fm10k_mac_pf && rxq->drop_en)
 790                         rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
 791
 792                 FM10K_WRITE_REG(hw, FM10K_RXDCTL(i), rxdctl);
 793                 FM10K_WRITE_FLUSH(hw);
 794         }
 795
 796         /* Configure VMDQ/RSS if applicable */
 797         fm10k_dev_mq_rx_configure(dev);
 798
 799         /* Decide the best RX function */
 800         fm10k_set_rx_function(dev);
 801
 802         /* update RX_SGLORT for loopback suppress*/
 803         if (hw->mac.type != fm10k_mac_pf)
 804                 return 0;
 805         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
 806         if (macvlan->nb_queue_pools)
 807                 queue_stride = dev->data->nb_rx_queues / macvlan->nb_queue_pools;
 808         for (i = 0; i < dev->data->nb_rx_queues; ++i) {
 809                 if (i && queue_stride && !(i % queue_stride))
 810                         logic_port++;
 811                 FM10K_WRITE_REG(hw, FM10K_RX_SGLORT(i), logic_port);
 812         }
 813
 814         return 0;
 815 }
 816
 817 static int
 818 fm10k_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 819 {
 820         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 821         int err = -1;
 822         uint32_t reg;
 823         struct fm10k_rx_queue *rxq;
 824
 825         PMD_INIT_FUNC_TRACE();
 826
 827         if (rx_queue_id < dev->data->nb_rx_queues) {
 828                 rxq = dev->data->rx_queues[rx_queue_id];
 829                 err = rx_queue_reset(rxq);
 830                 if (err == -ENOMEM) {
 831                         PMD_INIT_LOG(ERR, "Failed to alloc memory : %d", err);
 832                         return err;
 833                 } else if (err == -EINVAL) {
 834                         PMD_INIT_LOG(ERR, "Invalid buffer address alignment :"
 835                                 " %d", err);
 836                         return err;
 837                 }
 838
 839                 /* Setup the HW Rx Head and Tail Descriptor Pointers
 840                  * Note: this must be done AFTER the queue is enabled on real
 841                  * hardware, but BEFORE the queue is enabled when using the
 842                  * emulation platform. Do it in both places for now and remove
 843                  * this comment and the following two register writes when the
 844                  * emulation platform is no longer being used.
 845                  */
 846                 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
 847                 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
 848
 849                 /* Set PF ownership flag for PF devices */
 850                 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(rx_queue_id));
 851                 if (hw->mac.type == fm10k_mac_pf)
 852                         reg |= FM10K_RXQCTL_PF;
 853                 reg |= FM10K_RXQCTL_ENABLE;
 854                 /* enable RX queue */
 855                 FM10K_WRITE_REG(hw, FM10K_RXQCTL(rx_queue_id), reg);
 856                 FM10K_WRITE_FLUSH(hw);
 857
 858                 /* Setup the HW Rx Head and Tail Descriptor Pointers
 859                  * Note: this must be done AFTER the queue is enabled
 860                  */
 861                 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
 862                 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
 863                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 864         }
 865
 866         return err;
 867 }
 868
 869 static int
 870 fm10k_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 871 {
 872         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 873
 874         PMD_INIT_FUNC_TRACE();
 875
 876         if (rx_queue_id < dev->data->nb_rx_queues) {
 877                 /* Disable RX queue */
 878                 rx_queue_disable(hw, rx_queue_id);
 879
 880                 /* Free mbuf and clean HW ring */
 881                 rx_queue_clean(dev->data->rx_queues[rx_queue_id]);
 882                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 883         }
 884
 885         return 0;
 886 }
 887
 888 static int
 889 fm10k_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 890 {
 891         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 892         /** @todo - this should be defined in the shared code */
 893 #define FM10K_TXDCTL_WRITE_BACK_MIN_DELAY       0x00010000
 894         uint32_t txdctl = FM10K_TXDCTL_WRITE_BACK_MIN_DELAY;
 895         int err = 0;
 896
 897         PMD_INIT_FUNC_TRACE();
 898
 899         if (tx_queue_id < dev->data->nb_tx_queues) {
 900                 struct fm10k_tx_queue *q = dev->data->tx_queues[tx_queue_id];
 901
 902                 q->ops->reset(q);
 903
 904                 /* reset head and tail pointers */
 905                 FM10K_WRITE_REG(hw, FM10K_TDH(tx_queue_id), 0);
 906                 FM10K_WRITE_REG(hw, FM10K_TDT(tx_queue_id), 0);
 907
 908                 /* enable TX queue */
 909                 FM10K_WRITE_REG(hw, FM10K_TXDCTL(tx_queue_id),
 910                                         FM10K_TXDCTL_ENABLE | txdctl);
 911                 FM10K_WRITE_FLUSH(hw);
 912                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 913         } else
 914                 err = -1;
 915
 916         return err;
 917 }
 918
 919 static int
 920 fm10k_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 921 {
 922         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 923
 924         PMD_INIT_FUNC_TRACE();
 925
 926         if (tx_queue_id < dev->data->nb_tx_queues) {
 927                 tx_queue_disable(hw, tx_queue_id);
 928                 tx_queue_clean(dev->data->tx_queues[tx_queue_id]);
 929                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 930         }
 931
 932         return 0;
 933 }
 934
 935 static inline int fm10k_glort_valid(struct fm10k_hw *hw)
 936 {
 937         return ((hw->mac.dglort_map & FM10K_DGLORTMAP_NONE)
 938                 != FM10K_DGLORTMAP_NONE);
 939 }
 940
 941 static void
 942 fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev)
 943 {
 944         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 945         int status;
 946
 947         PMD_INIT_FUNC_TRACE();
 948
 949         /* Return if it didn't acquire valid glort range */
 950         if (!fm10k_glort_valid(hw))
 951                 return;
 952
 953         fm10k_mbx_lock(hw);
 954         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 955                                 FM10K_XCAST_MODE_PROMISC);
 956         fm10k_mbx_unlock(hw);
 957
 958         if (status != FM10K_SUCCESS)
 959                 PMD_INIT_LOG(ERR, "Failed to enable promiscuous mode");
 960 }
 961
 962 static void
 963 fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev)
 964 {
 965         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 966         uint8_t mode;
 967         int status;
 968
 969         PMD_INIT_FUNC_TRACE();
 970
 971         /* Return if it didn't acquire valid glort range */
 972         if (!fm10k_glort_valid(hw))
 973                 return;
 974
 975         if (dev->data->all_multicast == 1)
 976                 mode = FM10K_XCAST_MODE_ALLMULTI;
 977         else
 978                 mode = FM10K_XCAST_MODE_NONE;
 979
 980         fm10k_mbx_lock(hw);
 981         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 982                                 mode);
 983         fm10k_mbx_unlock(hw);
 984
 985         if (status != FM10K_SUCCESS)
 986                 PMD_INIT_LOG(ERR, "Failed to disable promiscuous mode");
 987 }
 988
 989 static void
 990 fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev)
 991 {
 992         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 993         int status;
 994
 995         PMD_INIT_FUNC_TRACE();
 996
 997         /* Return if it didn't acquire valid glort range */
 998         if (!fm10k_glort_valid(hw))
 999                 return;
1000
1001         /* If promiscuous mode is enabled, it doesn't make sense to enable
1002          * allmulticast and disable promiscuous since fm10k only can select
1003          * one of the modes.
1004          */
1005         if (dev->data->promiscuous) {
1006                 PMD_INIT_LOG(INFO, "Promiscuous mode is enabled, "\
1007                         "needn't enable allmulticast");
1008                 return;
1009         }
1010
1011         fm10k_mbx_lock(hw);
1012         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1013                                 FM10K_XCAST_MODE_ALLMULTI);
1014         fm10k_mbx_unlock(hw);
1015
1016         if (status != FM10K_SUCCESS)
1017                 PMD_INIT_LOG(ERR, "Failed to enable allmulticast mode");
1018 }
1019
1020 static void
1021 fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev)
1022 {
1023         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1024         int status;
1025
1026         PMD_INIT_FUNC_TRACE();
1027
1028         /* Return if it didn't acquire valid glort range */
1029         if (!fm10k_glort_valid(hw))
1030                 return;
1031
1032         if (dev->data->promiscuous) {
1033                 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode "\
1034                         "since promisc mode is enabled");
1035                 return;
1036         }
1037
1038         fm10k_mbx_lock(hw);
1039         /* Change mode to unicast mode */
1040         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1041                                 FM10K_XCAST_MODE_NONE);
1042         fm10k_mbx_unlock(hw);
1043
1044         if (status != FM10K_SUCCESS)
1045                 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode");
1046 }
1047
1048 static void
1049 fm10k_dev_dglort_map_configure(struct rte_eth_dev *dev)
1050 {
1051         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1052         uint32_t dglortdec, pool_len, rss_len, i, dglortmask;
1053         uint16_t nb_queue_pools;
1054         struct fm10k_macvlan_filter_info *macvlan;
1055
1056         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1057         nb_queue_pools = macvlan->nb_queue_pools;
1058         pool_len = nb_queue_pools ? fls(nb_queue_pools - 1) : 0;
1059         rss_len = fls(dev->data->nb_rx_queues - 1) - pool_len;
1060
1061         /* GLORT 0x0-0x3F are used by PF and VMDQ,  0x40-0x7F used by FD */
1062         dglortdec = (rss_len << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | pool_len;
1063         dglortmask = (GLORT_PF_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1064                         hw->mac.dglort_map;
1065         FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(0), dglortmask);
1066         /* Configure VMDQ/RSS DGlort Decoder */
1067         FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(0), dglortdec);
1068
1069         /* Flow Director configurations, only queue number is valid. */
1070         dglortdec = fls(dev->data->nb_rx_queues - 1);
1071         dglortmask = (GLORT_FD_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1072                         (hw->mac.dglort_map + GLORT_FD_Q_BASE);
1073         FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(1), dglortmask);
1074         FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(1), dglortdec);
1075
1076         /* Invalidate all other GLORT entries */
1077         for (i = 2; i < FM10K_DGLORT_COUNT; i++)
1078                 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(i),
1079                                 FM10K_DGLORTMAP_NONE);
1080 }
1081
1082 #define BSIZEPKT_ROUNDUP ((1 << FM10K_SRRCTL_BSIZEPKT_SHIFT) - 1)
1083 static int
1084 fm10k_dev_start(struct rte_eth_dev *dev)
1085 {
1086         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1087         int i, diag;
1088
1089         PMD_INIT_FUNC_TRACE();
1090
1091         /* stop, init, then start the hw */
1092         diag = fm10k_stop_hw(hw);
1093         if (diag != FM10K_SUCCESS) {
1094                 PMD_INIT_LOG(ERR, "Hardware stop failed: %d", diag);
1095                 return -EIO;
1096         }
1097
1098         diag = fm10k_init_hw(hw);
1099         if (diag != FM10K_SUCCESS) {
1100                 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
1101                 return -EIO;
1102         }
1103
1104         diag = fm10k_start_hw(hw);
1105         if (diag != FM10K_SUCCESS) {
1106                 PMD_INIT_LOG(ERR, "Hardware start failed: %d", diag);
1107                 return -EIO;
1108         }
1109
1110         diag = fm10k_dev_tx_init(dev);
1111         if (diag) {
1112                 PMD_INIT_LOG(ERR, "TX init failed: %d", diag);
1113                 return diag;
1114         }
1115
1116         if (fm10k_dev_rxq_interrupt_setup(dev))
1117                 return -EIO;
1118
1119         diag = fm10k_dev_rx_init(dev);
1120         if (diag) {
1121                 PMD_INIT_LOG(ERR, "RX init failed: %d", diag);
1122                 return diag;
1123         }
1124
1125         if (hw->mac.type == fm10k_mac_pf)
1126                 fm10k_dev_dglort_map_configure(dev);
1127
1128         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1129                 struct fm10k_rx_queue *rxq;
1130                 rxq = dev->data->rx_queues[i];
1131
1132                 if (rxq->rx_deferred_start)
1133                         continue;
1134                 diag = fm10k_dev_rx_queue_start(dev, i);
1135                 if (diag != 0) {
1136                         int j;
1137                         for (j = 0; j < i; ++j)
1138                                 rx_queue_clean(dev->data->rx_queues[j]);
1139                         return diag;
1140                 }
1141         }
1142
1143         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1144                 struct fm10k_tx_queue *txq;
1145                 txq = dev->data->tx_queues[i];
1146
1147                 if (txq->tx_deferred_start)
1148                         continue;
1149                 diag = fm10k_dev_tx_queue_start(dev, i);
1150                 if (diag != 0) {
1151                         int j;
1152                         for (j = 0; j < i; ++j)
1153                                 tx_queue_clean(dev->data->tx_queues[j]);
1154                         for (j = 0; j < dev->data->nb_rx_queues; ++j)
1155                                 rx_queue_clean(dev->data->rx_queues[j]);
1156                         return diag;
1157                 }
1158         }
1159
1160         /* Update default vlan when not in VMDQ mode */
1161         if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
1162                 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
1163
1164         return 0;
1165 }
1166
1167 static void
1168 fm10k_dev_stop(struct rte_eth_dev *dev)
1169 {
1170         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1171         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1172         int i;
1173
1174         PMD_INIT_FUNC_TRACE();
1175
1176         if (dev->data->tx_queues)
1177                 for (i = 0; i < dev->data->nb_tx_queues; i++)
1178                         fm10k_dev_tx_queue_stop(dev, i);
1179
1180         if (dev->data->rx_queues)
1181                 for (i = 0; i < dev->data->nb_rx_queues; i++)
1182                         fm10k_dev_rx_queue_stop(dev, i);
1183
1184         /* Disable datapath event */
1185         if (rte_intr_dp_is_en(intr_handle)) {
1186                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1187                         FM10K_WRITE_REG(hw, FM10K_RXINT(i),
1188                                 3 << FM10K_RXINT_TIMER_SHIFT);
1189                         if (hw->mac.type == fm10k_mac_pf)
1190                                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, i)),
1191                                         FM10K_ITR_MASK_SET);
1192                         else
1193                                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, i)),
1194                                         FM10K_ITR_MASK_SET);
1195                 }
1196         }
1197         /* Clean datapath event and queue/vec mapping */
1198         rte_intr_efd_disable(intr_handle);
1199         rte_free(intr_handle->intr_vec);
1200         intr_handle->intr_vec = NULL;
1201 }
1202
1203 static void
1204 fm10k_dev_queue_release(struct rte_eth_dev *dev)
1205 {
1206         int i;
1207
1208         PMD_INIT_FUNC_TRACE();
1209
1210         if (dev->data->tx_queues) {
1211                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1212                         struct fm10k_tx_queue *txq = dev->data->tx_queues[i];
1213
1214                         tx_queue_free(txq);
1215                 }
1216         }
1217
1218         if (dev->data->rx_queues) {
1219                 for (i = 0; i < dev->data->nb_rx_queues; i++)
1220                         fm10k_rx_queue_release(dev->data->rx_queues[i]);
1221         }
1222 }
1223
1224 static void
1225 fm10k_dev_close(struct rte_eth_dev *dev)
1226 {
1227         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1228
1229         PMD_INIT_FUNC_TRACE();
1230
1231         fm10k_mbx_lock(hw);
1232         hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
1233                 MAX_LPORT_NUM, false);
1234         fm10k_mbx_unlock(hw);
1235
1236         /* Stop mailbox service first */
1237         fm10k_close_mbx_service(hw);
1238         fm10k_dev_stop(dev);
1239         fm10k_dev_queue_release(dev);
1240         fm10k_stop_hw(hw);
1241 }
1242
1243 static int
1244 fm10k_link_update(struct rte_eth_dev *dev,
1245         __rte_unused int wait_to_complete)
1246 {
1247         PMD_INIT_FUNC_TRACE();
1248
1249         /* The host-interface link is always up.  The speed is ~50Gbps per Gen3
1250          * x8 PCIe interface. For now, we leave the speed undefined since there
1251          * is no 50Gbps Ethernet. */
1252         dev->data->dev_link.link_speed  = 0;
1253         dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
1254         dev->data->dev_link.link_status = 1;
1255
1256         return 0;
1257 }
1258
1259 static int
1260 fm10k_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1261                  unsigned n)
1262 {
1263         struct fm10k_hw_stats *hw_stats =
1264                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1265         unsigned i, q, count = 0;
1266
1267         if (n < FM10K_NB_XSTATS)
1268                 return FM10K_NB_XSTATS;
1269
1270         /* Global stats */
1271         for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1272                 snprintf(xstats[count].name, sizeof(xstats[count].name),
1273                          "%s", fm10k_hw_stats_strings[count].name);
1274                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1275                         fm10k_hw_stats_strings[count].offset);
1276                 count++;
1277         }
1278
1279         /* PF queue stats */
1280         for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1281                 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1282                         snprintf(xstats[count].name, sizeof(xstats[count].name),
1283                                  "rx_q%u_%s", q,
1284                                  fm10k_hw_stats_rx_q_strings[i].name);
1285                         xstats[count].value =
1286                                 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1287                                 fm10k_hw_stats_rx_q_strings[i].offset);
1288                         count++;
1289                 }
1290                 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1291                         snprintf(xstats[count].name, sizeof(xstats[count].name),
1292                                  "tx_q%u_%s", q,
1293                                  fm10k_hw_stats_tx_q_strings[i].name);
1294                         xstats[count].value =
1295                                 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1296                                 fm10k_hw_stats_tx_q_strings[i].offset);
1297                         count++;
1298                 }
1299         }
1300
1301         return FM10K_NB_XSTATS;
1302 }
1303
1304 static void
1305 fm10k_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1306 {
1307         uint64_t ipackets, opackets, ibytes, obytes;
1308         struct fm10k_hw *hw =
1309                 FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1310         struct fm10k_hw_stats *hw_stats =
1311                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1312         int i;
1313
1314         PMD_INIT_FUNC_TRACE();
1315
1316         fm10k_update_hw_stats(hw, hw_stats);
1317
1318         ipackets = opackets = ibytes = obytes = 0;
1319         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1320                 (i < hw->mac.max_queues); ++i) {
1321                 stats->q_ipackets[i] = hw_stats->q[i].rx_packets.count;
1322                 stats->q_opackets[i] = hw_stats->q[i].tx_packets.count;
1323                 stats->q_ibytes[i]   = hw_stats->q[i].rx_bytes.count;
1324                 stats->q_obytes[i]   = hw_stats->q[i].tx_bytes.count;
1325                 ipackets += stats->q_ipackets[i];
1326                 opackets += stats->q_opackets[i];
1327                 ibytes   += stats->q_ibytes[i];
1328                 obytes   += stats->q_obytes[i];
1329         }
1330         stats->ipackets = ipackets;
1331         stats->opackets = opackets;
1332         stats->ibytes = ibytes;
1333         stats->obytes = obytes;
1334 }
1335
1336 static void
1337 fm10k_stats_reset(struct rte_eth_dev *dev)
1338 {
1339         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1340         struct fm10k_hw_stats *hw_stats =
1341                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1342
1343         PMD_INIT_FUNC_TRACE();
1344
1345         memset(hw_stats, 0, sizeof(*hw_stats));
1346         fm10k_rebind_hw_stats(hw, hw_stats);
1347 }
1348
1349 static void
1350 fm10k_dev_infos_get(struct rte_eth_dev *dev,
1351         struct rte_eth_dev_info *dev_info)
1352 {
1353         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1354
1355         PMD_INIT_FUNC_TRACE();
1356
1357         dev_info->min_rx_bufsize     = FM10K_MIN_RX_BUF_SIZE;
1358         dev_info->max_rx_pktlen      = FM10K_MAX_PKT_SIZE;
1359         dev_info->max_rx_queues      = hw->mac.max_queues;
1360         dev_info->max_tx_queues      = hw->mac.max_queues;
1361         dev_info->max_mac_addrs      = FM10K_MAX_MACADDR_NUM;
1362         dev_info->max_hash_mac_addrs = 0;
1363         dev_info->max_vfs            = dev->pci_dev->max_vfs;
1364         dev_info->vmdq_pool_base     = 0;
1365         dev_info->vmdq_queue_base    = 0;
1366         dev_info->max_vmdq_pools     = ETH_32_POOLS;
1367         dev_info->vmdq_queue_num     = FM10K_MAX_QUEUES_PF;
1368         dev_info->rx_offload_capa =
1369                 DEV_RX_OFFLOAD_VLAN_STRIP |
1370                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1371                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1372                 DEV_RX_OFFLOAD_TCP_CKSUM;
1373         dev_info->tx_offload_capa =
1374                 DEV_TX_OFFLOAD_VLAN_INSERT |
1375                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1376                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1377                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1378                 DEV_TX_OFFLOAD_TCP_TSO;
1379
1380         dev_info->hash_key_size = FM10K_RSSRK_SIZE * sizeof(uint32_t);
1381         dev_info->reta_size = FM10K_MAX_RSS_INDICES;
1382
1383         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1384                 .rx_thresh = {
1385                         .pthresh = FM10K_DEFAULT_RX_PTHRESH,
1386                         .hthresh = FM10K_DEFAULT_RX_HTHRESH,
1387                         .wthresh = FM10K_DEFAULT_RX_WTHRESH,
1388                 },
1389                 .rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(0),
1390                 .rx_drop_en = 0,
1391         };
1392
1393         dev_info->default_txconf = (struct rte_eth_txconf) {
1394                 .tx_thresh = {
1395                         .pthresh = FM10K_DEFAULT_TX_PTHRESH,
1396                         .hthresh = FM10K_DEFAULT_TX_HTHRESH,
1397                         .wthresh = FM10K_DEFAULT_TX_WTHRESH,
1398                 },
1399                 .tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(0),
1400                 .tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(0),
1401                 .txq_flags = FM10K_SIMPLE_TX_FLAG,
1402         };
1403
1404         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1405                 .nb_max = FM10K_MAX_RX_DESC,
1406                 .nb_min = FM10K_MIN_RX_DESC,
1407                 .nb_align = FM10K_MULT_RX_DESC,
1408         };
1409
1410         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1411                 .nb_max = FM10K_MAX_TX_DESC,
1412                 .nb_min = FM10K_MIN_TX_DESC,
1413                 .nb_align = FM10K_MULT_TX_DESC,
1414         };
1415 }
1416
1417 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
1418 static const uint32_t *
1419 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1420 {
1421         if (dev->rx_pkt_burst == fm10k_recv_pkts ||
1422             dev->rx_pkt_burst == fm10k_recv_scattered_pkts) {
1423                 static uint32_t ptypes[] = {
1424                         /* refers to rx_desc_to_ol_flags() */
1425                         RTE_PTYPE_L2_ETHER,
1426                         RTE_PTYPE_L3_IPV4,
1427                         RTE_PTYPE_L3_IPV4_EXT,
1428                         RTE_PTYPE_L3_IPV6,
1429                         RTE_PTYPE_L3_IPV6_EXT,
1430                         RTE_PTYPE_L4_TCP,
1431                         RTE_PTYPE_L4_UDP,
1432                         RTE_PTYPE_UNKNOWN
1433                 };
1434
1435                 return ptypes;
1436         } else if (dev->rx_pkt_burst == fm10k_recv_pkts_vec ||
1437                    dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec) {
1438                 static uint32_t ptypes_vec[] = {
1439                         /* refers to fm10k_desc_to_pktype_v() */
1440                         RTE_PTYPE_L3_IPV4,
1441                         RTE_PTYPE_L3_IPV4_EXT,
1442                         RTE_PTYPE_L3_IPV6,
1443                         RTE_PTYPE_L3_IPV6_EXT,
1444                         RTE_PTYPE_L4_TCP,
1445                         RTE_PTYPE_L4_UDP,
1446                         RTE_PTYPE_TUNNEL_GENEVE,
1447                         RTE_PTYPE_TUNNEL_NVGRE,
1448                         RTE_PTYPE_TUNNEL_VXLAN,
1449                         RTE_PTYPE_TUNNEL_GRE,
1450                         RTE_PTYPE_UNKNOWN
1451                 };
1452
1453                 return ptypes_vec;
1454         }
1455
1456         return NULL;
1457 }
1458 #else
1459 static const uint32_t *
1460 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1461 {
1462         return NULL;
1463 }
1464 #endif
1465
1466 static int
1467 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1468 {
1469         s32 result;
1470         uint16_t mac_num = 0;
1471         uint32_t vid_idx, vid_bit, mac_index;
1472         struct fm10k_hw *hw;
1473         struct fm10k_macvlan_filter_info *macvlan;
1474         struct rte_eth_dev_data *data = dev->data;
1475
1476         hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1477         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1478
1479         if (macvlan->nb_queue_pools > 0) { /* VMDQ mode */
1480                 PMD_INIT_LOG(ERR, "Cannot change VLAN filter in VMDQ mode");
1481                 return -EINVAL;
1482         }
1483
1484         if (vlan_id > ETH_VLAN_ID_MAX) {
1485                 PMD_INIT_LOG(ERR, "Invalid vlan_id: must be < 4096");
1486                 return -EINVAL;
1487         }
1488
1489         vid_idx = FM10K_VFTA_IDX(vlan_id);
1490         vid_bit = FM10K_VFTA_BIT(vlan_id);
1491         /* this VLAN ID is already in the VLAN filter table, return SUCCESS */
1492         if (on && (macvlan->vfta[vid_idx] & vid_bit))
1493                 return 0;
1494         /* this VLAN ID is NOT in the VLAN filter table, cannot remove */
1495         if (!on && !(macvlan->vfta[vid_idx] & vid_bit)) {
1496                 PMD_INIT_LOG(ERR, "Invalid vlan_id: not existing "
1497                         "in the VLAN filter table");
1498                 return -EINVAL;
1499         }
1500
1501         fm10k_mbx_lock(hw);
1502         result = fm10k_update_vlan(hw, vlan_id, 0, on);
1503         fm10k_mbx_unlock(hw);
1504         if (result != FM10K_SUCCESS) {
1505                 PMD_INIT_LOG(ERR, "VLAN update failed: %d", result);
1506                 return -EIO;
1507         }
1508
1509         for (mac_index = 0; (mac_index < FM10K_MAX_MACADDR_NUM) &&
1510                         (result == FM10K_SUCCESS); mac_index++) {
1511                 if (is_zero_ether_addr(&data->mac_addrs[mac_index]))
1512                         continue;
1513                 if (mac_num > macvlan->mac_num - 1) {
1514                         PMD_INIT_LOG(ERR, "MAC address number "
1515                                         "not match");
1516                         break;
1517                 }
1518                 fm10k_mbx_lock(hw);
1519                 result = fm10k_update_uc_addr(hw, hw->mac.dglort_map,
1520                         data->mac_addrs[mac_index].addr_bytes,
1521                         vlan_id, on, 0);
1522                 fm10k_mbx_unlock(hw);
1523                 mac_num++;
1524         }
1525         if (result != FM10K_SUCCESS) {
1526                 PMD_INIT_LOG(ERR, "MAC address update failed: %d", result);
1527                 return -EIO;
1528         }
1529
1530         if (on) {
1531                 macvlan->vlan_num++;
1532                 macvlan->vfta[vid_idx] |= vid_bit;
1533         } else {
1534                 macvlan->vlan_num--;
1535                 macvlan->vfta[vid_idx] &= ~vid_bit;
1536         }
1537         return 0;
1538 }
1539
1540 static void
1541 fm10k_vlan_offload_set(__rte_unused struct rte_eth_dev *dev, int mask)
1542 {
1543         if (mask & ETH_VLAN_STRIP_MASK) {
1544                 if (!dev->data->dev_conf.rxmode.hw_vlan_strip)
1545                         PMD_INIT_LOG(ERR, "VLAN stripping is "
1546                                         "always on in fm10k");
1547         }
1548
1549         if (mask & ETH_VLAN_EXTEND_MASK) {
1550                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1551                         PMD_INIT_LOG(ERR, "VLAN QinQ is not "
1552                                         "supported in fm10k");
1553         }
1554
1555         if (mask & ETH_VLAN_FILTER_MASK) {
1556                 if (!dev->data->dev_conf.rxmode.hw_vlan_filter)
1557                         PMD_INIT_LOG(ERR, "VLAN filter is always on in fm10k");
1558         }
1559 }
1560
1561 /* Add/Remove a MAC address, and update filters to main VSI */
1562 static void fm10k_MAC_filter_set_main_vsi(struct rte_eth_dev *dev,
1563                 const u8 *mac, bool add, uint32_t pool)
1564 {
1565         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1566         struct fm10k_macvlan_filter_info *macvlan;
1567         uint32_t i, j, k;
1568
1569         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1570
1571         if (pool != MAIN_VSI_POOL_NUMBER) {
1572                 PMD_DRV_LOG(ERR, "VMDQ not enabled, can't set "
1573                         "mac to pool %u", pool);
1574                 return;
1575         }
1576         for (i = 0, j = 0; j < FM10K_VFTA_SIZE; j++) {
1577                 if (!macvlan->vfta[j])
1578                         continue;
1579                 for (k = 0; k < FM10K_UINT32_BIT_SIZE; k++) {
1580                         if (!(macvlan->vfta[j] & (1 << k)))
1581                                 continue;
1582                         if (i + 1 > macvlan->vlan_num) {
1583                                 PMD_INIT_LOG(ERR, "vlan number not match");
1584                                 return;
1585                         }
1586                         fm10k_mbx_lock(hw);
1587                         fm10k_update_uc_addr(hw, hw->mac.dglort_map, mac,
1588                                 j * FM10K_UINT32_BIT_SIZE + k, add, 0);
1589                         fm10k_mbx_unlock(hw);
1590                         i++;
1591                 }
1592         }
1593 }
1594
1595 /* Add/Remove a MAC address, and update filters to VMDQ */
1596 static void fm10k_MAC_filter_set_vmdq(struct rte_eth_dev *dev,
1597                 const u8 *mac, bool add, uint32_t pool)
1598 {
1599         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1600         struct fm10k_macvlan_filter_info *macvlan;
1601         struct rte_eth_vmdq_rx_conf *vmdq_conf;
1602         uint32_t i;
1603
1604         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1605         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1606
1607         if (pool > macvlan->nb_queue_pools) {
1608                 PMD_DRV_LOG(ERR, "Pool number %u invalid."
1609                         " Max pool is %u",
1610                         pool, macvlan->nb_queue_pools);
1611                 return;
1612         }
1613         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
1614                 if (!(vmdq_conf->pool_map[i].pools & (1UL << pool)))
1615                         continue;
1616                 fm10k_mbx_lock(hw);
1617                 fm10k_update_uc_addr(hw, hw->mac.dglort_map + pool, mac,
1618                         vmdq_conf->pool_map[i].vlan_id, add, 0);
1619                 fm10k_mbx_unlock(hw);
1620         }
1621 }
1622
1623 /* Add/Remove a MAC address, and update filters */
1624 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
1625                 const u8 *mac, bool add, uint32_t pool)
1626 {
1627         struct fm10k_macvlan_filter_info *macvlan;
1628
1629         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1630
1631         if (macvlan->nb_queue_pools > 0) /* VMDQ mode */
1632                 fm10k_MAC_filter_set_vmdq(dev, mac, add, pool);
1633         else
1634                 fm10k_MAC_filter_set_main_vsi(dev, mac, add, pool);
1635
1636         if (add)
1637                 macvlan->mac_num++;
1638         else
1639                 macvlan->mac_num--;
1640 }
1641
1642 /* Add a MAC address, and update filters */
1643 static void
1644 fm10k_macaddr_add(struct rte_eth_dev *dev,
1645                 struct ether_addr *mac_addr,
1646                 uint32_t index,
1647                 uint32_t pool)
1648 {
1649         struct fm10k_macvlan_filter_info *macvlan;
1650
1651         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1652         fm10k_MAC_filter_set(dev, mac_addr->addr_bytes, TRUE, pool);
1653         macvlan->mac_vmdq_id[index] = pool;
1654 }
1655
1656 /* Remove a MAC address, and update filters */
1657 static void
1658 fm10k_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1659 {
1660         struct rte_eth_dev_data *data = dev->data;
1661         struct fm10k_macvlan_filter_info *macvlan;
1662
1663         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1664         fm10k_MAC_filter_set(dev, data->mac_addrs[index].addr_bytes,
1665                         FALSE, macvlan->mac_vmdq_id[index]);
1666         macvlan->mac_vmdq_id[index] = 0;
1667 }
1668
1669 static inline int
1670 check_nb_desc(uint16_t min, uint16_t max, uint16_t mult, uint16_t request)
1671 {
1672         if ((request < min) || (request > max) || ((request % mult) != 0))
1673                 return -1;
1674         else
1675                 return 0;
1676 }
1677
1678
1679 static inline int
1680 check_thresh(uint16_t min, uint16_t max, uint16_t div, uint16_t request)
1681 {
1682         if ((request < min) || (request > max) || ((div % request) != 0))
1683                 return -1;
1684         else
1685                 return 0;
1686 }
1687
1688 static inline int
1689 handle_rxconf(struct fm10k_rx_queue *q, const struct rte_eth_rxconf *conf)
1690 {
1691         uint16_t rx_free_thresh;
1692
1693         if (conf->rx_free_thresh == 0)
1694                 rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(q);
1695         else
1696                 rx_free_thresh = conf->rx_free_thresh;
1697
1698         /* make sure the requested threshold satisfies the constraints */
1699         if (check_thresh(FM10K_RX_FREE_THRESH_MIN(q),
1700                         FM10K_RX_FREE_THRESH_MAX(q),
1701                         FM10K_RX_FREE_THRESH_DIV(q),
1702                         rx_free_thresh)) {
1703                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be "
1704                         "less than or equal to %u, "
1705                         "greater than or equal to %u, "
1706                         "and a divisor of %u",
1707                         rx_free_thresh, FM10K_RX_FREE_THRESH_MAX(q),
1708                         FM10K_RX_FREE_THRESH_MIN(q),
1709                         FM10K_RX_FREE_THRESH_DIV(q));
1710                 return -EINVAL;
1711         }
1712
1713         q->alloc_thresh = rx_free_thresh;
1714         q->drop_en = conf->rx_drop_en;
1715         q->rx_deferred_start = conf->rx_deferred_start;
1716
1717         return 0;
1718 }
1719
1720 /*
1721  * Hardware requires specific alignment for Rx packet buffers. At
1722  * least one of the following two conditions must be satisfied.
1723  *  1. Address is 512B aligned
1724  *  2. Address is 8B aligned and buffer does not cross 4K boundary.
1725  *
1726  * As such, the driver may need to adjust the DMA address within the
1727  * buffer by up to 512B.
1728  *
1729  * return 1 if the element size is valid, otherwise return 0.
1730  */
1731 static int
1732 mempool_element_size_valid(struct rte_mempool *mp)
1733 {
1734         uint32_t min_size;
1735
1736         /* elt_size includes mbuf header and headroom */
1737         min_size = mp->elt_size - sizeof(struct rte_mbuf) -
1738                         RTE_PKTMBUF_HEADROOM;
1739
1740         /* account for up to 512B of alignment */
1741         min_size -= FM10K_RX_DATABUF_ALIGN;
1742
1743         /* sanity check for overflow */
1744         if (min_size > mp->elt_size)
1745                 return 0;
1746
1747         /* size is valid */
1748         return 1;
1749 }
1750
1751 static int
1752 fm10k_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1753         uint16_t nb_desc, unsigned int socket_id,
1754         const struct rte_eth_rxconf *conf, struct rte_mempool *mp)
1755 {
1756         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1757         struct fm10k_dev_info *dev_info = FM10K_DEV_PRIVATE_TO_INFO(dev);
1758         struct fm10k_rx_queue *q;
1759         const struct rte_memzone *mz;
1760
1761         PMD_INIT_FUNC_TRACE();
1762
1763         /* make sure the mempool element size can account for alignment. */
1764         if (!mempool_element_size_valid(mp)) {
1765                 PMD_INIT_LOG(ERR, "Error : Mempool element size is too small");
1766                 return -EINVAL;
1767         }
1768
1769         /* make sure a valid number of descriptors have been requested */
1770         if (check_nb_desc(FM10K_MIN_RX_DESC, FM10K_MAX_RX_DESC,
1771                                 FM10K_MULT_RX_DESC, nb_desc)) {
1772                 PMD_INIT_LOG(ERR, "Number of Rx descriptors (%u) must be "
1773                         "less than or equal to %"PRIu32", "
1774                         "greater than or equal to %u, "
1775                         "and a multiple of %u",
1776                         nb_desc, (uint32_t)FM10K_MAX_RX_DESC, FM10K_MIN_RX_DESC,
1777                         FM10K_MULT_RX_DESC);
1778                 return -EINVAL;
1779         }
1780
1781         /*
1782          * if this queue existed already, free the associated memory. The
1783          * queue cannot be reused in case we need to allocate memory on
1784          * different socket than was previously used.
1785          */
1786         if (dev->data->rx_queues[queue_id] != NULL) {
1787                 rx_queue_free(dev->data->rx_queues[queue_id]);
1788                 dev->data->rx_queues[queue_id] = NULL;
1789         }
1790
1791         /* allocate memory for the queue structure */
1792         q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1793                                 socket_id);
1794         if (q == NULL) {
1795                 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1796                 return -ENOMEM;
1797         }
1798
1799         /* setup queue */
1800         q->mp = mp;
1801         q->nb_desc = nb_desc;
1802         q->nb_fake_desc = FM10K_MULT_RX_DESC;
1803         q->port_id = dev->data->port_id;
1804         q->queue_id = queue_id;
1805         q->tail_ptr = (volatile uint32_t *)
1806                 &((uint32_t *)hw->hw_addr)[FM10K_RDT(queue_id)];
1807         if (handle_rxconf(q, conf))
1808                 return -EINVAL;
1809
1810         /* allocate memory for the software ring */
1811         q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
1812                         (nb_desc + q->nb_fake_desc) * sizeof(struct rte_mbuf *),
1813                         RTE_CACHE_LINE_SIZE, socket_id);
1814         if (q->sw_ring == NULL) {
1815                 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
1816                 rte_free(q);
1817                 return -ENOMEM;
1818         }
1819
1820         /*
1821          * allocate memory for the hardware descriptor ring. A memzone large
1822          * enough to hold the maximum ring size is requested to allow for
1823          * resizing in later calls to the queue setup function.
1824          */
1825         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_id,
1826                                       FM10K_MAX_RX_RING_SZ, FM10K_ALIGN_RX_DESC,
1827                                       socket_id);
1828         if (mz == NULL) {
1829                 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
1830                 rte_free(q->sw_ring);
1831                 rte_free(q);
1832                 return -ENOMEM;
1833         }
1834         q->hw_ring = mz->addr;
1835         q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1836
1837         /* Check if number of descs satisfied Vector requirement */
1838         if (!rte_is_power_of_2(nb_desc)) {
1839                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
1840                                     "preconditions - canceling the feature for "
1841                                     "the whole port[%d]",
1842                              q->queue_id, q->port_id);
1843                 dev_info->rx_vec_allowed = false;
1844         } else
1845                 fm10k_rxq_vec_setup(q);
1846
1847         dev->data->rx_queues[queue_id] = q;
1848         return 0;
1849 }
1850
1851 static void
1852 fm10k_rx_queue_release(void *queue)
1853 {
1854         PMD_INIT_FUNC_TRACE();
1855
1856         rx_queue_free(queue);
1857 }
1858
1859 static inline int
1860 handle_txconf(struct fm10k_tx_queue *q, const struct rte_eth_txconf *conf)
1861 {
1862         uint16_t tx_free_thresh;
1863         uint16_t tx_rs_thresh;
1864
1865         /* constraint MACROs require that tx_free_thresh is configured
1866          * before tx_rs_thresh */
1867         if (conf->tx_free_thresh == 0)
1868                 tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(q);
1869         else
1870                 tx_free_thresh = conf->tx_free_thresh;
1871
1872         /* make sure the requested threshold satisfies the constraints */
1873         if (check_thresh(FM10K_TX_FREE_THRESH_MIN(q),
1874                         FM10K_TX_FREE_THRESH_MAX(q),
1875                         FM10K_TX_FREE_THRESH_DIV(q),
1876                         tx_free_thresh)) {
1877                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be "
1878                         "less than or equal to %u, "
1879                         "greater than or equal to %u, "
1880                         "and a divisor of %u",
1881                         tx_free_thresh, FM10K_TX_FREE_THRESH_MAX(q),
1882                         FM10K_TX_FREE_THRESH_MIN(q),
1883                         FM10K_TX_FREE_THRESH_DIV(q));
1884                 return -EINVAL;
1885         }
1886
1887         q->free_thresh = tx_free_thresh;
1888
1889         if (conf->tx_rs_thresh == 0)
1890                 tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(q);
1891         else
1892                 tx_rs_thresh = conf->tx_rs_thresh;
1893
1894         q->tx_deferred_start = conf->tx_deferred_start;
1895
1896         /* make sure the requested threshold satisfies the constraints */
1897         if (check_thresh(FM10K_TX_RS_THRESH_MIN(q),
1898                         FM10K_TX_RS_THRESH_MAX(q),
1899                         FM10K_TX_RS_THRESH_DIV(q),
1900                         tx_rs_thresh)) {
1901                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be "
1902                         "less than or equal to %u, "
1903                         "greater than or equal to %u, "
1904                         "and a divisor of %u",
1905                         tx_rs_thresh, FM10K_TX_RS_THRESH_MAX(q),
1906                         FM10K_TX_RS_THRESH_MIN(q),
1907                         FM10K_TX_RS_THRESH_DIV(q));
1908                 return -EINVAL;
1909         }
1910
1911         q->rs_thresh = tx_rs_thresh;
1912
1913         return 0;
1914 }
1915
1916 static int
1917 fm10k_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1918         uint16_t nb_desc, unsigned int socket_id,
1919         const struct rte_eth_txconf *conf)
1920 {
1921         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         struct fm10k_tx_queue *q;
1923         const struct rte_memzone *mz;
1924
1925         PMD_INIT_FUNC_TRACE();
1926
1927         /* make sure a valid number of descriptors have been requested */
1928         if (check_nb_desc(FM10K_MIN_TX_DESC, FM10K_MAX_TX_DESC,
1929                                 FM10K_MULT_TX_DESC, nb_desc)) {
1930                 PMD_INIT_LOG(ERR, "Number of Tx descriptors (%u) must be "
1931                         "less than or equal to %"PRIu32", "
1932                         "greater than or equal to %u, "
1933                         "and a multiple of %u",
1934                         nb_desc, (uint32_t)FM10K_MAX_TX_DESC, FM10K_MIN_TX_DESC,
1935                         FM10K_MULT_TX_DESC);
1936                 return -EINVAL;
1937         }
1938
1939         /*
1940          * if this queue existed already, free the associated memory. The
1941          * queue cannot be reused in case we need to allocate memory on
1942          * different socket than was previously used.
1943          */
1944         if (dev->data->tx_queues[queue_id] != NULL) {
1945                 struct fm10k_tx_queue *txq = dev->data->tx_queues[queue_id];
1946
1947                 tx_queue_free(txq);
1948                 dev->data->tx_queues[queue_id] = NULL;
1949         }
1950
1951         /* allocate memory for the queue structure */
1952         q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1953                                 socket_id);
1954         if (q == NULL) {
1955                 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1956                 return -ENOMEM;
1957         }
1958
1959         /* setup queue */
1960         q->nb_desc = nb_desc;
1961         q->port_id = dev->data->port_id;
1962         q->queue_id = queue_id;
1963         q->txq_flags = conf->txq_flags;
1964         q->ops = &def_txq_ops;
1965         q->tail_ptr = (volatile uint32_t *)
1966                 &((uint32_t *)hw->hw_addr)[FM10K_TDT(queue_id)];
1967         if (handle_txconf(q, conf))
1968                 return -EINVAL;
1969
1970         /* allocate memory for the software ring */
1971         q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
1972                                         nb_desc * sizeof(struct rte_mbuf *),
1973                                         RTE_CACHE_LINE_SIZE, socket_id);
1974         if (q->sw_ring == NULL) {
1975                 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
1976                 rte_free(q);
1977                 return -ENOMEM;
1978         }
1979
1980         /*
1981          * allocate memory for the hardware descriptor ring. A memzone large
1982          * enough to hold the maximum ring size is requested to allow for
1983          * resizing in later calls to the queue setup function.
1984          */
1985         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_id,
1986                                       FM10K_MAX_TX_RING_SZ, FM10K_ALIGN_TX_DESC,
1987                                       socket_id);
1988         if (mz == NULL) {
1989                 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
1990                 rte_free(q->sw_ring);
1991                 rte_free(q);
1992                 return -ENOMEM;
1993         }
1994         q->hw_ring = mz->addr;
1995         q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1996
1997         /*
1998          * allocate memory for the RS bit tracker. Enough slots to hold the
1999          * descriptor index for each RS bit needing to be set are required.
2000          */
2001         q->rs_tracker.list = rte_zmalloc_socket("fm10k rs tracker",
2002                                 ((nb_desc + 1) / q->rs_thresh) *
2003                                 sizeof(uint16_t),
2004                                 RTE_CACHE_LINE_SIZE, socket_id);
2005         if (q->rs_tracker.list == NULL) {
2006                 PMD_INIT_LOG(ERR, "Cannot allocate RS bit tracker");
2007                 rte_free(q->sw_ring);
2008                 rte_free(q);
2009                 return -ENOMEM;
2010         }
2011
2012         dev->data->tx_queues[queue_id] = q;
2013         return 0;
2014 }
2015
2016 static void
2017 fm10k_tx_queue_release(void *queue)
2018 {
2019         struct fm10k_tx_queue *q = queue;
2020         PMD_INIT_FUNC_TRACE();
2021
2022         tx_queue_free(q);
2023 }
2024
2025 static int
2026 fm10k_reta_update(struct rte_eth_dev *dev,
2027                         struct rte_eth_rss_reta_entry64 *reta_conf,
2028                         uint16_t reta_size)
2029 {
2030         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2031         uint16_t i, j, idx, shift;
2032         uint8_t mask;
2033         uint32_t reta;
2034
2035         PMD_INIT_FUNC_TRACE();
2036
2037         if (reta_size > FM10K_MAX_RSS_INDICES) {
2038                 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2039                         "(%d) doesn't match the number hardware can supported "
2040                         "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2041                 return -EINVAL;
2042         }
2043
2044         /*
2045          * Update Redirection Table RETA[n], n=0..31. The redirection table has
2046          * 128-entries in 32 registers
2047          */
2048         for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2049                 idx = i / RTE_RETA_GROUP_SIZE;
2050                 shift = i % RTE_RETA_GROUP_SIZE;
2051                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2052                                 BIT_MASK_PER_UINT32);
2053                 if (mask == 0)
2054                         continue;
2055
2056                 reta = 0;
2057                 if (mask != BIT_MASK_PER_UINT32)
2058                         reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2059
2060                 for (j = 0; j < CHARS_PER_UINT32; j++) {
2061                         if (mask & (0x1 << j)) {
2062                                 if (mask != 0xF)
2063                                         reta &= ~(UINT8_MAX << CHAR_BIT * j);
2064                                 reta |= reta_conf[idx].reta[shift + j] <<
2065                                                 (CHAR_BIT * j);
2066                         }
2067                 }
2068                 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2), reta);
2069         }
2070
2071         return 0;
2072 }
2073
2074 static int
2075 fm10k_reta_query(struct rte_eth_dev *dev,
2076                         struct rte_eth_rss_reta_entry64 *reta_conf,
2077                         uint16_t reta_size)
2078 {
2079         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2080         uint16_t i, j, idx, shift;
2081         uint8_t mask;
2082         uint32_t reta;
2083
2084         PMD_INIT_FUNC_TRACE();
2085
2086         if (reta_size < FM10K_MAX_RSS_INDICES) {
2087                 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2088                         "(%d) doesn't match the number hardware can supported "
2089                         "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2090                 return -EINVAL;
2091         }
2092
2093         /*
2094          * Read Redirection Table RETA[n], n=0..31. The redirection table has
2095          * 128-entries in 32 registers
2096          */
2097         for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2098                 idx = i / RTE_RETA_GROUP_SIZE;
2099                 shift = i % RTE_RETA_GROUP_SIZE;
2100                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2101                                 BIT_MASK_PER_UINT32);
2102                 if (mask == 0)
2103                         continue;
2104
2105                 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2106                 for (j = 0; j < CHARS_PER_UINT32; j++) {
2107                         if (mask & (0x1 << j))
2108                                 reta_conf[idx].reta[shift + j] = ((reta >>
2109                                         CHAR_BIT * j) & UINT8_MAX);
2110                 }
2111         }
2112
2113         return 0;
2114 }
2115
2116 static int
2117 fm10k_rss_hash_update(struct rte_eth_dev *dev,
2118         struct rte_eth_rss_conf *rss_conf)
2119 {
2120         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2121         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2122         uint32_t mrqc;
2123         uint64_t hf = rss_conf->rss_hf;
2124         int i;
2125
2126         PMD_INIT_FUNC_TRACE();
2127
2128         if (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2129                 FM10K_RSSRK_ENTRIES_PER_REG)
2130                 return -EINVAL;
2131
2132         if (hf == 0)
2133                 return -EINVAL;
2134
2135         mrqc = 0;
2136         mrqc |= (hf & ETH_RSS_IPV4)              ? FM10K_MRQC_IPV4     : 0;
2137         mrqc |= (hf & ETH_RSS_IPV6)              ? FM10K_MRQC_IPV6     : 0;
2138         mrqc |= (hf & ETH_RSS_IPV6_EX)           ? FM10K_MRQC_IPV6     : 0;
2139         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? FM10K_MRQC_TCP_IPV4 : 0;
2140         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? FM10K_MRQC_TCP_IPV6 : 0;
2141         mrqc |= (hf & ETH_RSS_IPV6_TCP_EX)       ? FM10K_MRQC_TCP_IPV6 : 0;
2142         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? FM10K_MRQC_UDP_IPV4 : 0;
2143         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? FM10K_MRQC_UDP_IPV6 : 0;
2144         mrqc |= (hf & ETH_RSS_IPV6_UDP_EX)       ? FM10K_MRQC_UDP_IPV6 : 0;
2145
2146         /* If the mapping doesn't fit any supported, return */
2147         if (mrqc == 0)
2148                 return -EINVAL;
2149
2150         if (key != NULL)
2151                 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2152                         FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
2153
2154         FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
2155
2156         return 0;
2157 }
2158
2159 static int
2160 fm10k_rss_hash_conf_get(struct rte_eth_dev *dev,
2161         struct rte_eth_rss_conf *rss_conf)
2162 {
2163         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2165         uint32_t mrqc;
2166         uint64_t hf;
2167         int i;
2168
2169         PMD_INIT_FUNC_TRACE();
2170
2171         if (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2172                                 FM10K_RSSRK_ENTRIES_PER_REG)
2173                 return -EINVAL;
2174
2175         if (key != NULL)
2176                 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2177                         key[i] = FM10K_READ_REG(hw, FM10K_RSSRK(0, i));
2178
2179         mrqc = FM10K_READ_REG(hw, FM10K_MRQC(0));
2180         hf = 0;
2181         hf |= (mrqc & FM10K_MRQC_IPV4)     ? ETH_RSS_IPV4              : 0;
2182         hf |= (mrqc & FM10K_MRQC_IPV6)     ? ETH_RSS_IPV6              : 0;
2183         hf |= (mrqc & FM10K_MRQC_IPV6)     ? ETH_RSS_IPV6_EX           : 0;
2184         hf |= (mrqc & FM10K_MRQC_TCP_IPV4) ? ETH_RSS_NONFRAG_IPV4_TCP  : 0;
2185         hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_NONFRAG_IPV6_TCP  : 0;
2186         hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_IPV6_TCP_EX       : 0;
2187         hf |= (mrqc & FM10K_MRQC_UDP_IPV4) ? ETH_RSS_NONFRAG_IPV4_UDP  : 0;
2188         hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_NONFRAG_IPV6_UDP  : 0;
2189         hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_IPV6_UDP_EX       : 0;
2190
2191         rss_conf->rss_hf = hf;
2192
2193         return 0;
2194 }
2195
2196 static void
2197 fm10k_dev_enable_intr_pf(struct rte_eth_dev *dev)
2198 {
2199         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200         uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2201
2202         /* Bind all local non-queue interrupt to vector 0 */
2203         int_map |= FM10K_MISC_VEC_ID;
2204
2205         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2206         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2207         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2208         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2209         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2210         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2211
2212         /* Enable misc causes */
2213         FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |
2214                                 FM10K_EIMR_ENABLE(THI_FAULT) |
2215                                 FM10K_EIMR_ENABLE(FUM_FAULT) |
2216                                 FM10K_EIMR_ENABLE(MAILBOX) |
2217                                 FM10K_EIMR_ENABLE(SWITCHREADY) |
2218                                 FM10K_EIMR_ENABLE(SWITCHNOTREADY) |
2219                                 FM10K_EIMR_ENABLE(SRAMERROR) |
2220                                 FM10K_EIMR_ENABLE(VFLR));
2221
2222         /* Enable ITR 0 */
2223         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2224                                         FM10K_ITR_MASK_CLEAR);
2225         FM10K_WRITE_FLUSH(hw);
2226 }
2227
2228 static void
2229 fm10k_dev_disable_intr_pf(struct rte_eth_dev *dev)
2230 {
2231         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2232         uint32_t int_map = FM10K_INT_MAP_DISABLE;
2233
2234         int_map |= FM10K_MISC_VEC_ID;
2235
2236         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2237         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2238         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2239         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2240         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2241         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2242
2243         /* Disable misc causes */
2244         FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(PCA_FAULT) |
2245                                 FM10K_EIMR_DISABLE(THI_FAULT) |
2246                                 FM10K_EIMR_DISABLE(FUM_FAULT) |
2247                                 FM10K_EIMR_DISABLE(MAILBOX) |
2248                                 FM10K_EIMR_DISABLE(SWITCHREADY) |
2249                                 FM10K_EIMR_DISABLE(SWITCHNOTREADY) |
2250                                 FM10K_EIMR_DISABLE(SRAMERROR) |
2251                                 FM10K_EIMR_DISABLE(VFLR));
2252
2253         /* Disable ITR 0 */
2254         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_MASK_SET);
2255         FM10K_WRITE_FLUSH(hw);
2256 }
2257
2258 static void
2259 fm10k_dev_enable_intr_vf(struct rte_eth_dev *dev)
2260 {
2261         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2262         uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2263
2264         /* Bind all local non-queue interrupt to vector 0 */
2265         int_map |= FM10K_MISC_VEC_ID;
2266
2267         /* Only INT 0 available, other 15 are reserved. */
2268         FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2269
2270         /* Enable ITR 0 */
2271         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2272                                         FM10K_ITR_MASK_CLEAR);
2273         FM10K_WRITE_FLUSH(hw);
2274 }
2275
2276 static void
2277 fm10k_dev_disable_intr_vf(struct rte_eth_dev *dev)
2278 {
2279         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2280         uint32_t int_map = FM10K_INT_MAP_DISABLE;
2281
2282         int_map |= FM10K_MISC_VEC_ID;
2283
2284         /* Only INT 0 available, other 15 are reserved. */
2285         FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2286
2287         /* Disable ITR 0 */
2288         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_MASK_SET);
2289         FM10K_WRITE_FLUSH(hw);
2290 }
2291
2292 static int
2293 fm10k_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
2294 {
2295         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2296
2297         /* Enable ITR */
2298         if (hw->mac.type == fm10k_mac_pf)
2299                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, queue_id)),
2300                         FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2301         else
2302                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, queue_id)),
2303                         FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2304         rte_intr_enable(&dev->pci_dev->intr_handle);
2305         return 0;
2306 }
2307
2308 static int
2309 fm10k_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2310 {
2311         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2312
2313         /* Disable ITR */
2314         if (hw->mac.type == fm10k_mac_pf)
2315                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, queue_id)),
2316                         FM10K_ITR_MASK_SET);
2317         else
2318                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, queue_id)),
2319                         FM10K_ITR_MASK_SET);
2320         return 0;
2321 }
2322
2323 static int
2324 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2325 {
2326         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2327         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2328         uint32_t intr_vector, vec;
2329         uint16_t queue_id;
2330         int result = 0;
2331
2332         /* fm10k needs one separate interrupt for mailbox,
2333          * so only drivers which support multiple interrupt vectors
2334          * e.g. vfio-pci can work for fm10k interrupt mode
2335          */
2336         if (!rte_intr_cap_multiple(intr_handle) ||
2337                         dev->data->dev_conf.intr_conf.rxq == 0)
2338                 return result;
2339
2340         intr_vector = dev->data->nb_rx_queues;
2341
2342         /* disable interrupt first */
2343         rte_intr_disable(&dev->pci_dev->intr_handle);
2344         if (hw->mac.type == fm10k_mac_pf)
2345                 fm10k_dev_disable_intr_pf(dev);
2346         else
2347                 fm10k_dev_disable_intr_vf(dev);
2348
2349         if (rte_intr_efd_enable(intr_handle, intr_vector)) {
2350                 PMD_INIT_LOG(ERR, "Failed to init event fd");
2351                 result = -EIO;
2352         }
2353
2354         if (rte_intr_dp_is_en(intr_handle) && !result) {
2355                 intr_handle->intr_vec = rte_zmalloc("intr_vec",
2356                         dev->data->nb_rx_queues * sizeof(int), 0);
2357                 if (intr_handle->intr_vec) {
2358                         for (queue_id = 0, vec = FM10K_RX_VEC_START;
2359                                         queue_id < dev->data->nb_rx_queues;
2360                                         queue_id++) {
2361                                 intr_handle->intr_vec[queue_id] = vec;
2362                                 if (vec < intr_handle->nb_efd - 1
2363                                                 + FM10K_RX_VEC_START)
2364                                         vec++;
2365                         }
2366                 } else {
2367                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2368                                 " intr_vec", dev->data->nb_rx_queues);
2369                         rte_intr_efd_disable(intr_handle);
2370                         result = -ENOMEM;
2371                 }
2372         }
2373
2374         if (hw->mac.type == fm10k_mac_pf)
2375                 fm10k_dev_enable_intr_pf(dev);
2376         else
2377                 fm10k_dev_enable_intr_vf(dev);
2378         rte_intr_enable(&dev->pci_dev->intr_handle);
2379         hw->mac.ops.update_int_moderator(hw);
2380         return result;
2381 }
2382
2383 static int
2384 fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr)
2385 {
2386         struct fm10k_fault fault;
2387         int err;
2388         const char *estr = "Unknown error";
2389
2390         /* Process PCA fault */
2391         if (eicr & FM10K_EICR_PCA_FAULT) {
2392                 err = fm10k_get_fault(hw, FM10K_PCA_FAULT, &fault);
2393                 if (err)
2394                         goto error;
2395                 switch (fault.type) {
2396                 case PCA_NO_FAULT:
2397                         estr = "PCA_NO_FAULT"; break;
2398                 case PCA_UNMAPPED_ADDR:
2399                         estr = "PCA_UNMAPPED_ADDR"; break;
2400                 case PCA_BAD_QACCESS_PF:
2401                         estr = "PCA_BAD_QACCESS_PF"; break;
2402                 case PCA_BAD_QACCESS_VF:
2403                         estr = "PCA_BAD_QACCESS_VF"; break;
2404                 case PCA_MALICIOUS_REQ:
2405                         estr = "PCA_MALICIOUS_REQ"; break;
2406                 case PCA_POISONED_TLP:
2407                         estr = "PCA_POISONED_TLP"; break;
2408                 case PCA_TLP_ABORT:
2409                         estr = "PCA_TLP_ABORT"; break;
2410                 default:
2411                         goto error;
2412                 }
2413                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2414                         estr, fault.func ? "VF" : "PF", fault.func,
2415                         fault.address, fault.specinfo);
2416         }
2417
2418         /* Process THI fault */
2419         if (eicr & FM10K_EICR_THI_FAULT) {
2420                 err = fm10k_get_fault(hw, FM10K_THI_FAULT, &fault);
2421                 if (err)
2422                         goto error;
2423                 switch (fault.type) {
2424                 case THI_NO_FAULT:
2425                         estr = "THI_NO_FAULT"; break;
2426                 case THI_MAL_DIS_Q_FAULT:
2427                         estr = "THI_MAL_DIS_Q_FAULT"; break;
2428                 default:
2429                         goto error;
2430                 }
2431                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2432                         estr, fault.func ? "VF" : "PF", fault.func,
2433                         fault.address, fault.specinfo);
2434         }
2435
2436         /* Process FUM fault */
2437         if (eicr & FM10K_EICR_FUM_FAULT) {
2438                 err = fm10k_get_fault(hw, FM10K_FUM_FAULT, &fault);
2439                 if (err)
2440                         goto error;
2441                 switch (fault.type) {
2442                 case FUM_NO_FAULT:
2443                         estr = "FUM_NO_FAULT"; break;
2444                 case FUM_UNMAPPED_ADDR:
2445                         estr = "FUM_UNMAPPED_ADDR"; break;
2446                 case FUM_POISONED_TLP:
2447                         estr = "FUM_POISONED_TLP"; break;
2448                 case FUM_BAD_VF_QACCESS:
2449                         estr = "FUM_BAD_VF_QACCESS"; break;
2450                 case FUM_ADD_DECODE_ERR:
2451                         estr = "FUM_ADD_DECODE_ERR"; break;
2452                 case FUM_RO_ERROR:
2453                         estr = "FUM_RO_ERROR"; break;
2454                 case FUM_QPRC_CRC_ERROR:
2455                         estr = "FUM_QPRC_CRC_ERROR"; break;
2456                 case FUM_CSR_TIMEOUT:
2457                         estr = "FUM_CSR_TIMEOUT"; break;
2458                 case FUM_INVALID_TYPE:
2459                         estr = "FUM_INVALID_TYPE"; break;
2460                 case FUM_INVALID_LENGTH:
2461                         estr = "FUM_INVALID_LENGTH"; break;
2462                 case FUM_INVALID_BE:
2463                         estr = "FUM_INVALID_BE"; break;
2464                 case FUM_INVALID_ALIGN:
2465                         estr = "FUM_INVALID_ALIGN"; break;
2466                 default:
2467                         goto error;
2468                 }
2469                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2470                         estr, fault.func ? "VF" : "PF", fault.func,
2471                         fault.address, fault.specinfo);
2472         }
2473
2474         return 0;
2475 error:
2476         PMD_INIT_LOG(ERR, "Failed to handle fault event.");
2477         return err;
2478 }
2479
2480 /**
2481  * PF interrupt handler triggered by NIC for handling specific interrupt.
2482  *
2483  * @param handle
2484  *  Pointer to interrupt handle.
2485  * @param param
2486  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2487  *
2488  * @return
2489  *  void
2490  */
2491 static void
2492 fm10k_dev_interrupt_handler_pf(
2493                         __rte_unused struct rte_intr_handle *handle,
2494                         void *param)
2495 {
2496         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2497         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2498         uint32_t cause, status;
2499
2500         if (hw->mac.type != fm10k_mac_pf)
2501                 return;
2502
2503         cause = FM10K_READ_REG(hw, FM10K_EICR);
2504
2505         /* Handle PCI fault cases */
2506         if (cause & FM10K_EICR_FAULT_MASK) {
2507                 PMD_INIT_LOG(ERR, "INT: find fault!");
2508                 fm10k_dev_handle_fault(hw, cause);
2509         }
2510
2511         /* Handle switch up/down */
2512         if (cause & FM10K_EICR_SWITCHNOTREADY)
2513                 PMD_INIT_LOG(ERR, "INT: Switch is not ready");
2514
2515         if (cause & FM10K_EICR_SWITCHREADY)
2516                 PMD_INIT_LOG(INFO, "INT: Switch is ready");
2517
2518         /* Handle mailbox message */
2519         fm10k_mbx_lock(hw);
2520         hw->mbx.ops.process(hw, &hw->mbx);
2521         fm10k_mbx_unlock(hw);
2522
2523         /* Handle SRAM error */
2524         if (cause & FM10K_EICR_SRAMERROR) {
2525                 PMD_INIT_LOG(ERR, "INT: SRAM error on PEP");
2526
2527                 status = FM10K_READ_REG(hw, FM10K_SRAM_IP);
2528                 /* Write to clear pending bits */
2529                 FM10K_WRITE_REG(hw, FM10K_SRAM_IP, status);
2530
2531                 /* Todo: print out error message after shared code  updates */
2532         }
2533
2534         /* Clear these 3 events if having any */
2535         cause &= FM10K_EICR_SWITCHNOTREADY | FM10K_EICR_MAILBOX |
2536                  FM10K_EICR_SWITCHREADY;
2537         if (cause)
2538                 FM10K_WRITE_REG(hw, FM10K_EICR, cause);
2539
2540         /* Re-enable interrupt from device side */
2541         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2542                                         FM10K_ITR_MASK_CLEAR);
2543         /* Re-enable interrupt from host side */
2544         rte_intr_enable(&(dev->pci_dev->intr_handle));
2545 }
2546
2547 /**
2548  * VF interrupt handler triggered by NIC for handling specific interrupt.
2549  *
2550  * @param handle
2551  *  Pointer to interrupt handle.
2552  * @param param
2553  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2554  *
2555  * @return
2556  *  void
2557  */
2558 static void
2559 fm10k_dev_interrupt_handler_vf(
2560                         __rte_unused struct rte_intr_handle *handle,
2561                         void *param)
2562 {
2563         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2564         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2565
2566         if (hw->mac.type != fm10k_mac_vf)
2567                 return;
2568
2569         /* Handle mailbox message if lock is acquired */
2570         fm10k_mbx_lock(hw);
2571         hw->mbx.ops.process(hw, &hw->mbx);
2572         fm10k_mbx_unlock(hw);
2573
2574         /* Re-enable interrupt from device side */
2575         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2576                                         FM10K_ITR_MASK_CLEAR);
2577         /* Re-enable interrupt from host side */
2578         rte_intr_enable(&(dev->pci_dev->intr_handle));
2579 }
2580
2581 /* Mailbox message handler in VF */
2582 static const struct fm10k_msg_data fm10k_msgdata_vf[] = {
2583         FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
2584         FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),
2585         FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
2586         FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
2587 };
2588
2589 static int
2590 fm10k_setup_mbx_service(struct fm10k_hw *hw)
2591 {
2592         int err = 0;
2593
2594         /* Initialize mailbox lock */
2595         fm10k_mbx_initlock(hw);
2596
2597         /* Replace default message handler with new ones */
2598         if (hw->mac.type == fm10k_mac_vf)
2599                 err = hw->mbx.ops.register_handlers(&hw->mbx, fm10k_msgdata_vf);
2600
2601         if (err) {
2602                 PMD_INIT_LOG(ERR, "Failed to register mailbox handler.err:%d",
2603                                 err);
2604                 return err;
2605         }
2606         /* Connect to SM for PF device or PF for VF device */
2607         return hw->mbx.ops.connect(hw, &hw->mbx);
2608 }
2609
2610 static void
2611 fm10k_close_mbx_service(struct fm10k_hw *hw)
2612 {
2613         /* Disconnect from SM for PF device or PF for VF device */
2614         hw->mbx.ops.disconnect(hw, &hw->mbx);
2615 }
2616
2617 static const struct eth_dev_ops fm10k_eth_dev_ops = {
2618         .dev_configure          = fm10k_dev_configure,
2619         .dev_start              = fm10k_dev_start,
2620         .dev_stop               = fm10k_dev_stop,
2621         .dev_close              = fm10k_dev_close,
2622         .promiscuous_enable     = fm10k_dev_promiscuous_enable,
2623         .promiscuous_disable    = fm10k_dev_promiscuous_disable,
2624         .allmulticast_enable    = fm10k_dev_allmulticast_enable,
2625         .allmulticast_disable   = fm10k_dev_allmulticast_disable,
2626         .stats_get              = fm10k_stats_get,
2627         .xstats_get             = fm10k_xstats_get,
2628         .stats_reset            = fm10k_stats_reset,
2629         .xstats_reset           = fm10k_stats_reset,
2630         .link_update            = fm10k_link_update,
2631         .dev_infos_get          = fm10k_dev_infos_get,
2632         .dev_supported_ptypes_get = fm10k_dev_supported_ptypes_get,
2633         .vlan_filter_set        = fm10k_vlan_filter_set,
2634         .vlan_offload_set       = fm10k_vlan_offload_set,
2635         .mac_addr_add           = fm10k_macaddr_add,
2636         .mac_addr_remove        = fm10k_macaddr_remove,
2637         .rx_queue_start         = fm10k_dev_rx_queue_start,
2638         .rx_queue_stop          = fm10k_dev_rx_queue_stop,
2639         .tx_queue_start         = fm10k_dev_tx_queue_start,
2640         .tx_queue_stop          = fm10k_dev_tx_queue_stop,
2641         .rx_queue_setup         = fm10k_rx_queue_setup,
2642         .rx_queue_release       = fm10k_rx_queue_release,
2643         .tx_queue_setup         = fm10k_tx_queue_setup,
2644         .tx_queue_release       = fm10k_tx_queue_release,
2645         .rx_descriptor_done     = fm10k_dev_rx_descriptor_done,
2646         .rx_queue_intr_enable   = fm10k_dev_rx_queue_intr_enable,
2647         .rx_queue_intr_disable  = fm10k_dev_rx_queue_intr_disable,
2648         .reta_update            = fm10k_reta_update,
2649         .reta_query             = fm10k_reta_query,
2650         .rss_hash_update        = fm10k_rss_hash_update,
2651         .rss_hash_conf_get      = fm10k_rss_hash_conf_get,
2652 };
2653
2654 static int ftag_check_handler(__rte_unused const char *key,
2655                 const char *value, __rte_unused void *opaque)
2656 {
2657         if (strcmp(value, "1"))
2658                 return -1;
2659
2660         return 0;
2661 }
2662
2663 static int
2664 fm10k_check_ftag(struct rte_devargs *devargs)
2665 {
2666         struct rte_kvargs *kvlist;
2667         const char *ftag_key = "enable_ftag";
2668
2669         if (devargs == NULL)
2670                 return 0;
2671
2672         kvlist = rte_kvargs_parse(devargs->args, NULL);
2673         if (kvlist == NULL)
2674                 return 0;
2675
2676         if (!rte_kvargs_count(kvlist, ftag_key)) {
2677                 rte_kvargs_free(kvlist);
2678                 return 0;
2679         }
2680         /* FTAG is enabled when there's key-value pair: enable_ftag=1 */
2681         if (rte_kvargs_process(kvlist, ftag_key,
2682                                 ftag_check_handler, NULL) < 0) {
2683                 rte_kvargs_free(kvlist);
2684                 return 0;
2685         }
2686         rte_kvargs_free(kvlist);
2687
2688         return 1;
2689 }
2690
2691 static void __attribute__((cold))
2692 fm10k_set_tx_function(struct rte_eth_dev *dev)
2693 {
2694         struct fm10k_tx_queue *txq;
2695         int i;
2696         int use_sse = 1;
2697         uint16_t tx_ftag_en = 0;
2698
2699         if (fm10k_check_ftag(dev->pci_dev->devargs))
2700                 tx_ftag_en = 1;
2701
2702         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2703                 txq = dev->data->tx_queues[i];
2704                 txq->tx_ftag_en = tx_ftag_en;
2705                 /* Check if Vector Tx is satisfied */
2706                 if (fm10k_tx_vec_condition_check(txq)) {
2707                         use_sse = 0;
2708                         break;
2709                 }
2710         }
2711
2712         if (use_sse) {
2713                 PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2714                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2715                         txq = dev->data->tx_queues[i];
2716                         fm10k_txq_vec_setup(txq);
2717                 }
2718                 dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2719         } else {
2720                 dev->tx_pkt_burst = fm10k_xmit_pkts;
2721                 PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2722         }
2723 }
2724
2725 static void __attribute__((cold))
2726 fm10k_set_rx_function(struct rte_eth_dev *dev)
2727 {
2728         struct fm10k_dev_info *dev_info = FM10K_DEV_PRIVATE_TO_INFO(dev);
2729         uint16_t i, rx_using_sse;
2730         uint16_t rx_ftag_en = 0;
2731
2732         if (fm10k_check_ftag(dev->pci_dev->devargs))
2733                 rx_ftag_en = 1;
2734
2735         /* In order to allow Vector Rx there are a few configuration
2736          * conditions to be met.
2737          */
2738         if (!fm10k_rx_vec_condition_check(dev) &&
2739                         dev_info->rx_vec_allowed && !rx_ftag_en) {
2740                 if (dev->data->scattered_rx)
2741                         dev->rx_pkt_burst = fm10k_recv_scattered_pkts_vec;
2742                 else
2743                         dev->rx_pkt_burst = fm10k_recv_pkts_vec;
2744         } else if (dev->data->scattered_rx)
2745                 dev->rx_pkt_burst = fm10k_recv_scattered_pkts;
2746         else
2747                 dev->rx_pkt_burst = fm10k_recv_pkts;
2748
2749         rx_using_sse =
2750                 (dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec ||
2751                 dev->rx_pkt_burst == fm10k_recv_pkts_vec);
2752
2753         if (rx_using_sse)
2754                 PMD_INIT_LOG(DEBUG, "Use vector Rx func");
2755         else
2756                 PMD_INIT_LOG(DEBUG, "Use regular Rx func");
2757
2758         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2759                 struct fm10k_rx_queue *rxq = dev->data->rx_queues[i];
2760
2761                 rxq->rx_using_sse = rx_using_sse;
2762                 rxq->rx_ftag_en = rx_ftag_en;
2763         }
2764 }
2765
2766 static void
2767 fm10k_params_init(struct rte_eth_dev *dev)
2768 {
2769         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2770         struct fm10k_dev_info *info = FM10K_DEV_PRIVATE_TO_INFO(dev);
2771
2772         /* Inialize bus info. Normally we would call fm10k_get_bus_info(), but
2773          * there is no way to get link status without reading BAR4.  Until this
2774          * works, assume we have maximum bandwidth.
2775          * @todo - fix bus info
2776          */
2777         hw->bus_caps.speed = fm10k_bus_speed_8000;
2778         hw->bus_caps.width = fm10k_bus_width_pcie_x8;
2779         hw->bus_caps.payload = fm10k_bus_payload_512;
2780         hw->bus.speed = fm10k_bus_speed_8000;
2781         hw->bus.width = fm10k_bus_width_pcie_x8;
2782         hw->bus.payload = fm10k_bus_payload_256;
2783
2784         info->rx_vec_allowed = true;
2785 }
2786
2787 static int
2788 eth_fm10k_dev_init(struct rte_eth_dev *dev)
2789 {
2790         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2791         int diag, i;
2792         struct fm10k_macvlan_filter_info *macvlan;
2793
2794         PMD_INIT_FUNC_TRACE();
2795
2796         dev->dev_ops = &fm10k_eth_dev_ops;
2797         dev->rx_pkt_burst = &fm10k_recv_pkts;
2798         dev->tx_pkt_burst = &fm10k_xmit_pkts;
2799
2800         /* only initialize in the primary process */
2801         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2802                 return 0;
2803
2804         rte_eth_copy_pci_info(dev, dev->pci_dev);
2805
2806         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
2807         memset(macvlan, 0, sizeof(*macvlan));
2808         /* Vendor and Device ID need to be set before init of shared code */
2809         memset(hw, 0, sizeof(*hw));
2810         hw->device_id = dev->pci_dev->id.device_id;
2811         hw->vendor_id = dev->pci_dev->id.vendor_id;
2812         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
2813         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
2814         hw->revision_id = 0;
2815         hw->hw_addr = (void *)dev->pci_dev->mem_resource[0].addr;
2816         if (hw->hw_addr == NULL) {
2817                 PMD_INIT_LOG(ERR, "Bad mem resource."
2818                         " Try to blacklist unused devices.");
2819                 return -EIO;
2820         }
2821
2822         /* Store fm10k_adapter pointer */
2823         hw->back = dev->data->dev_private;
2824
2825         /* Initialize the shared code */
2826         diag = fm10k_init_shared_code(hw);
2827         if (diag != FM10K_SUCCESS) {
2828                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
2829                 return -EIO;
2830         }
2831
2832         /* Initialize parameters */
2833         fm10k_params_init(dev);
2834
2835         /* Initialize the hw */
2836         diag = fm10k_init_hw(hw);
2837         if (diag != FM10K_SUCCESS) {
2838                 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
2839                 return -EIO;
2840         }
2841
2842         /* Initialize MAC address(es) */
2843         dev->data->mac_addrs = rte_zmalloc("fm10k",
2844                         ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM, 0);
2845         if (dev->data->mac_addrs == NULL) {
2846                 PMD_INIT_LOG(ERR, "Cannot allocate memory for MAC addresses");
2847                 return -ENOMEM;
2848         }
2849
2850         diag = fm10k_read_mac_addr(hw);
2851
2852         ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2853                         &dev->data->mac_addrs[0]);
2854
2855         if (diag != FM10K_SUCCESS ||
2856                 !is_valid_assigned_ether_addr(dev->data->mac_addrs)) {
2857
2858                 /* Generate a random addr */
2859                 eth_random_addr(hw->mac.addr);
2860                 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
2861                 ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2862                 &dev->data->mac_addrs[0]);
2863         }
2864
2865         /* Reset the hw statistics */
2866         fm10k_stats_reset(dev);
2867
2868         /* Reset the hw */
2869         diag = fm10k_reset_hw(hw);
2870         if (diag != FM10K_SUCCESS) {
2871                 PMD_INIT_LOG(ERR, "Hardware reset failed: %d", diag);
2872                 return -EIO;
2873         }
2874
2875         /* Setup mailbox service */
2876         diag = fm10k_setup_mbx_service(hw);
2877         if (diag != FM10K_SUCCESS) {
2878                 PMD_INIT_LOG(ERR, "Failed to setup mailbox: %d", diag);
2879                 return -EIO;
2880         }
2881
2882         /*PF/VF has different interrupt handling mechanism */
2883         if (hw->mac.type == fm10k_mac_pf) {
2884                 /* register callback func to eal lib */
2885                 rte_intr_callback_register(&(dev->pci_dev->intr_handle),
2886                         fm10k_dev_interrupt_handler_pf, (void *)dev);
2887
2888                 /* enable MISC interrupt */
2889                 fm10k_dev_enable_intr_pf(dev);
2890         } else { /* VF */
2891                 rte_intr_callback_register(&(dev->pci_dev->intr_handle),
2892                         fm10k_dev_interrupt_handler_vf, (void *)dev);
2893
2894                 fm10k_dev_enable_intr_vf(dev);
2895         }
2896
2897         /* Enable intr after callback registered */
2898         rte_intr_enable(&(dev->pci_dev->intr_handle));
2899
2900         hw->mac.ops.update_int_moderator(hw);
2901
2902         /* Make sure Switch Manager is ready before going forward. */
2903         if (hw->mac.type == fm10k_mac_pf) {
2904                 int switch_ready = 0;
2905
2906                 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
2907                         fm10k_mbx_lock(hw);
2908                         hw->mac.ops.get_host_state(hw, &switch_ready);
2909                         fm10k_mbx_unlock(hw);
2910                         if (switch_ready)
2911                                 break;
2912                         /* Delay some time to acquire async LPORT_MAP info. */
2913                         rte_delay_us(WAIT_SWITCH_MSG_US);
2914                 }
2915
2916                 if (switch_ready == 0) {
2917                         PMD_INIT_LOG(ERR, "switch is not ready");
2918                         return -1;
2919                 }
2920         }
2921
2922         /*
2923          * Below function will trigger operations on mailbox, acquire lock to
2924          * avoid race condition from interrupt handler. Operations on mailbox
2925          * FIFO will trigger interrupt to PF/SM, in which interrupt handler
2926          * will handle and generate an interrupt to our side. Then,  FIFO in
2927          * mailbox will be touched.
2928          */
2929         fm10k_mbx_lock(hw);
2930         /* Enable port first */
2931         hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
2932                                         MAX_LPORT_NUM, 1);
2933
2934         /* Set unicast mode by default. App can change to other mode in other
2935          * API func.
2936          */
2937         hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
2938                                         FM10K_XCAST_MODE_NONE);
2939
2940         fm10k_mbx_unlock(hw);
2941
2942         /* Make sure default VID is ready before going forward. */
2943         if (hw->mac.type == fm10k_mac_pf) {
2944                 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
2945                         if (hw->mac.default_vid)
2946                                 break;
2947                         /* Delay some time to acquire async port VLAN info. */
2948                         rte_delay_us(WAIT_SWITCH_MSG_US);
2949                 }
2950
2951                 if (!hw->mac.default_vid) {
2952                         PMD_INIT_LOG(ERR, "default VID is not ready");
2953                         return -1;
2954                 }
2955         }
2956
2957         /* Add default mac address */
2958         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
2959                 MAIN_VSI_POOL_NUMBER);
2960
2961         return 0;
2962 }
2963
2964 static int
2965 eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
2966 {
2967         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2968
2969         PMD_INIT_FUNC_TRACE();
2970
2971         /* only uninitialize in the primary process */
2972         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2973                 return 0;
2974
2975         /* safe to close dev here */
2976         fm10k_dev_close(dev);
2977
2978         dev->dev_ops = NULL;
2979         dev->rx_pkt_burst = NULL;
2980         dev->tx_pkt_burst = NULL;
2981
2982         /* disable uio/vfio intr */
2983         rte_intr_disable(&(dev->pci_dev->intr_handle));
2984
2985         /*PF/VF has different interrupt handling mechanism */
2986         if (hw->mac.type == fm10k_mac_pf) {
2987                 /* disable interrupt */
2988                 fm10k_dev_disable_intr_pf(dev);
2989
2990                 /* unregister callback func to eal lib */
2991                 rte_intr_callback_unregister(&(dev->pci_dev->intr_handle),
2992                         fm10k_dev_interrupt_handler_pf, (void *)dev);
2993         } else {
2994                 /* disable interrupt */
2995                 fm10k_dev_disable_intr_vf(dev);
2996
2997                 rte_intr_callback_unregister(&(dev->pci_dev->intr_handle),
2998                         fm10k_dev_interrupt_handler_vf, (void *)dev);
2999         }
3000
3001         /* free mac memory */
3002         if (dev->data->mac_addrs) {
3003                 rte_free(dev->data->mac_addrs);
3004                 dev->data->mac_addrs = NULL;
3005         }
3006
3007         memset(hw, 0, sizeof(*hw));
3008
3009         return 0;
3010 }
3011
3012 /*
3013  * The set of PCI devices this driver supports. This driver will enable both PF
3014  * and SRIOV-VF devices.
3015  */
3016 static const struct rte_pci_id pci_id_fm10k_map[] = {
3017 #define RTE_PCI_DEV_ID_DECL_FM10K(vend, dev) { RTE_PCI_DEVICE(vend, dev) },
3018 #define RTE_PCI_DEV_ID_DECL_FM10KVF(vend, dev) { RTE_PCI_DEVICE(vend, dev) },
3019 #include "rte_pci_dev_ids.h"
3020         { .vendor_id = 0, /* sentinel */ },
3021 };
3022
3023 static struct eth_driver rte_pmd_fm10k = {
3024         .pci_drv = {
3025                 .name = "rte_pmd_fm10k",
3026                 .id_table = pci_id_fm10k_map,
3027                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3028                         RTE_PCI_DRV_DETACHABLE,
3029         },
3030         .eth_dev_init = eth_fm10k_dev_init,
3031         .eth_dev_uninit = eth_fm10k_dev_uninit,
3032         .dev_private_size = sizeof(struct fm10k_adapter),
3033 };
3034
3035 /*
3036  * Driver initialization routine.
3037  * Invoked once at EAL init time.
3038  * Register itself as the [Poll Mode] Driver of PCI FM10K devices.
3039  */
3040 static int
3041 rte_pmd_fm10k_init(__rte_unused const char *name,
3042         __rte_unused const char *params)
3043 {
3044         PMD_INIT_FUNC_TRACE();
3045         rte_eth_driver_register(&rte_pmd_fm10k);
3046         return 0;
3047 }
3048
3049 static struct rte_driver rte_fm10k_driver = {
3050         .type = PMD_PDEV,
3051         .init = rte_pmd_fm10k_init,
3052 };
3053
3054 PMD_REGISTER_DRIVER(rte_fm10k_driver);