drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 115
 116 #define I40E_FLOW_TYPES ( \
 117         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 122         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 127         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 128
 129 /* Additional timesync values. */
 130 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 131 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 132 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 133 #define I40E_PRTTSYN_TSYNENA     0x80000000
 134 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 135 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 136
 137 #define I40E_MAX_PERCENT            100
 138 #define I40E_DEFAULT_DCB_APP_NUM    1
 139 #define I40E_DEFAULT_DCB_APP_PRIO   3
 140
 141 #define I40E_INSET_NONE            0x00000000000000000ULL
 142
 143 /* bit0 ~ bit 7 */
 144 #define I40E_INSET_DMAC            0x0000000000000001ULL
 145 #define I40E_INSET_SMAC            0x0000000000000002ULL
 146 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 147 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 148 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 149
 150 /* bit 8 ~ bit 15 */
 151 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 152 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 153 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 154 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 155 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 156 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 157 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 158
 159 /* bit 16 ~ bit 31 */
 160 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 161 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 162 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 163 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 164 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 165 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 166 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 167 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 168
 169 /* bit 32 ~ bit 47, tunnel fields */
 170 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 171 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 172 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 173 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 174 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 175 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 176
 177 /* bit 48 ~ bit 55 */
 178 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 179
 180 /* bit 56 ~ bit 63, Flex Payload */
 181 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD \
 190         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 191         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 192         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 193         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 194
 195 /**
 196  * Below are values for writing un-exposed registers suggested
 197  * by silicon experts
 198  */
 199 /* Destination MAC address */
 200 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 201 /* Source MAC address */
 202 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 203 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 204 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 205 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 206 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 207 /* Single VLAN tag in the inner L2 header */
 208 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 209 /* Source IPv4 address */
 210 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 211 /* Destination IPv4 address */
 212 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 213 /* Source IPv4 address for X722 */
 214 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 215 /* Destination IPv4 address for X722 */
 216 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 217 /* IPv4 Protocol for X722 */
 218 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 219 /* IPv4 Time to Live for X722 */
 220 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 221 /* IPv4 Type of Service (TOS) */
 222 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 223 /* IPv4 Protocol */
 224 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 225 /* IPv4 Time to Live */
 226 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 227 /* Source IPv6 address */
 228 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 229 /* Destination IPv6 address */
 230 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 231 /* IPv6 Traffic Class (TC) */
 232 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 233 /* IPv6 Next Header */
 234 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 235 /* IPv6 Hop Limit */
 236 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 237 /* Source L4 port */
 238 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 239 /* Destination L4 port */
 240 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 241 /* SCTP verification tag */
 242 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 243 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 244 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 245 /* Source port of tunneling UDP */
 246 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 247 /* Destination port of tunneling UDP */
 248 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 249 /* UDP Tunneling ID, NVGRE/GRE key */
 250 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 251 /* Last ether type */
 252 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 253 /* Tunneling outer destination IPv4 address */
 254 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 255 /* Tunneling outer destination IPv6 address */
 256 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 257 /* 1st word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 259 /* 2nd word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 261 /* 3rd word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 263 /* 4th word of flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 265 /* 5th word of flex payload */
 266 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 267 /* 6th word of flex payload */
 268 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 269 /* 7th word of flex payload */
 270 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 271 /* 8th word of flex payload */
 272 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 273 /* all 8 words flex payload */
 274 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 275 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 276
 277 #define I40E_TRANSLATE_INSET 0
 278 #define I40E_TRANSLATE_REG   1
 279
 280 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 281 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 282 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 283 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 284 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 285 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 286
 287 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 288 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 290         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 291
 292 /* PCI offset for querying capability */
 293 #define PCI_DEV_CAP_REG            0xA4
 294 /* PCI offset for enabling/disabling Extended Tag */
 295 #define PCI_DEV_CTRL_REG           0xA8
 296 /* Bit mask of Extended Tag capability */
 297 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 298 /* Bit shift of Extended Tag enable/disable */
 299 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 300 /* Bit mask of Extended Tag enable/disable */
 301 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 302
 303 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 304 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 305 static int i40e_dev_configure(struct rte_eth_dev *dev);
 306 static int i40e_dev_start(struct rte_eth_dev *dev);
 307 static void i40e_dev_stop(struct rte_eth_dev *dev);
 308 static void i40e_dev_close(struct rte_eth_dev *dev);
 309 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 310 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 311 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 312 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 313 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 314 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 315 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 316                                struct rte_eth_stats *stats);
 317 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 318                                struct rte_eth_xstat *xstats, unsigned n);
 319 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 320                                      struct rte_eth_xstat_name *xstats_names,
 321                                      unsigned limit);
 322 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 323 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 324                                             uint16_t queue_id,
 325                                             uint8_t stat_idx,
 326                                             uint8_t is_rx);
 327 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 328                               struct rte_eth_dev_info *dev_info);
 329 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 330                                 uint16_t vlan_id,
 331                                 int on);
 332 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 333                               enum rte_vlan_type vlan_type,
 334                               uint16_t tpid);
 335 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 336 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 337                                       uint16_t queue,
 338                                       int on);
 339 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 340 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 341 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 342 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 343                               struct rte_eth_fc_conf *fc_conf);
 344 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 345                               struct rte_eth_fc_conf *fc_conf);
 346 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 347                                        struct rte_eth_pfc_conf *pfc_conf);
 348 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 349                           struct ether_addr *mac_addr,
 350                           uint32_t index,
 351                           uint32_t pool);
 352 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 353 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 354                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 355                                     uint16_t reta_size);
 356 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 357                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 358                                    uint16_t reta_size);
 359
 360 static int i40e_get_cap(struct i40e_hw *hw);
 361 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 362 static int i40e_pf_setup(struct i40e_pf *pf);
 363 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 364 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 365 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 366 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 367 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 368                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 369 static void i40e_stat_update_48(struct i40e_hw *hw,
 370                                uint32_t hireg,
 371                                uint32_t loreg,
 372                                bool offset_loaded,
 373                                uint64_t *offset,
 374                                uint64_t *stat);
 375 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 376 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 377                                        void *param);
 378 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 379                                 uint32_t base, uint32_t num);
 380 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 381 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 382                         uint32_t base);
 383 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 384                         uint16_t num);
 385 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 386 static int i40e_veb_release(struct i40e_veb *veb);
 387 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 388                                                 struct i40e_vsi *vsi);
 389 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 390 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 391 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 392                                              struct i40e_macvlan_filter *mv_f,
 393                                              int num,
 394                                              struct ether_addr *addr);
 395 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 396                                              struct i40e_macvlan_filter *mv_f,
 397                                              int num,
 398                                              uint16_t vlan);
 399 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 400 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 401                                     struct rte_eth_rss_conf *rss_conf);
 402 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 403                                       struct rte_eth_rss_conf *rss_conf);
 404 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 405                                         struct rte_eth_udp_tunnel *udp_tunnel);
 406 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 407                                         struct rte_eth_udp_tunnel *udp_tunnel);
 408 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 409 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 410                         struct rte_eth_ethertype_filter *filter,
 411                         bool add);
 412 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 413                                 enum rte_filter_op filter_op,
 414                                 void *arg);
 415 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 416                                 enum rte_filter_type filter_type,
 417                                 enum rte_filter_op filter_op,
 418                                 void *arg);
 419 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 420                                   struct rte_eth_dcb_info *dcb_info);
 421 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 422 static void i40e_configure_registers(struct i40e_hw *hw);
 423 static void i40e_hw_init(struct rte_eth_dev *dev);
 424 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 425 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 426                         struct rte_eth_mirror_conf *mirror_conf,
 427                         uint8_t sw_id, uint8_t on);
 428 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 429
 430 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 431 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 432 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 433                                            struct timespec *timestamp,
 434                                            uint32_t flags);
 435 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 436                                            struct timespec *timestamp);
 437 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 438
 439 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 440
 441 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 442                                    struct timespec *timestamp);
 443 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 444                                     const struct timespec *timestamp);
 445
 446 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 447                                          uint16_t queue_id);
 448 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 449                                           uint16_t queue_id);
 450
 451 static int i40e_get_regs(struct rte_eth_dev *dev,
 452                          struct rte_dev_reg_info *regs);
 453
 454 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 455
 456 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 457                            struct rte_dev_eeprom_info *eeprom);
 458
 459 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 460                                       struct ether_addr *mac_addr);
 461
 462 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 463
 464 static const struct rte_pci_id pci_id_i40e_map[] = {
 465         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 466         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 467         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 468         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 469         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 470         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 471         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 478         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 479         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 480         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 481         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 482         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 483         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 484         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 485         { .vendor_id = 0, /* sentinel */ },
 486 };
 487
 488 static const struct eth_dev_ops i40e_eth_dev_ops = {
 489         .dev_configure                = i40e_dev_configure,
 490         .dev_start                    = i40e_dev_start,
 491         .dev_stop                     = i40e_dev_stop,
 492         .dev_close                    = i40e_dev_close,
 493         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 494         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 495         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 496         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 497         .dev_set_link_up              = i40e_dev_set_link_up,
 498         .dev_set_link_down            = i40e_dev_set_link_down,
 499         .link_update                  = i40e_dev_link_update,
 500         .stats_get                    = i40e_dev_stats_get,
 501         .xstats_get                   = i40e_dev_xstats_get,
 502         .xstats_get_names             = i40e_dev_xstats_get_names,
 503         .stats_reset                  = i40e_dev_stats_reset,
 504         .xstats_reset                 = i40e_dev_stats_reset,
 505         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 506         .dev_infos_get                = i40e_dev_info_get,
 507         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 508         .vlan_filter_set              = i40e_vlan_filter_set,
 509         .vlan_tpid_set                = i40e_vlan_tpid_set,
 510         .vlan_offload_set             = i40e_vlan_offload_set,
 511         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 512         .vlan_pvid_set                = i40e_vlan_pvid_set,
 513         .rx_queue_start               = i40e_dev_rx_queue_start,
 514         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 515         .tx_queue_start               = i40e_dev_tx_queue_start,
 516         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 517         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 518         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 519         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 520         .rx_queue_release             = i40e_dev_rx_queue_release,
 521         .rx_queue_count               = i40e_dev_rx_queue_count,
 522         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 523         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 524         .tx_queue_release             = i40e_dev_tx_queue_release,
 525         .dev_led_on                   = i40e_dev_led_on,
 526         .dev_led_off                  = i40e_dev_led_off,
 527         .flow_ctrl_get                = i40e_flow_ctrl_get,
 528         .flow_ctrl_set                = i40e_flow_ctrl_set,
 529         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 530         .mac_addr_add                 = i40e_macaddr_add,
 531         .mac_addr_remove              = i40e_macaddr_remove,
 532         .reta_update                  = i40e_dev_rss_reta_update,
 533         .reta_query                   = i40e_dev_rss_reta_query,
 534         .rss_hash_update              = i40e_dev_rss_hash_update,
 535         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 536         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 537         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 538         .filter_ctrl                  = i40e_dev_filter_ctrl,
 539         .rxq_info_get                 = i40e_rxq_info_get,
 540         .txq_info_get                 = i40e_txq_info_get,
 541         .mirror_rule_set              = i40e_mirror_rule_set,
 542         .mirror_rule_reset            = i40e_mirror_rule_reset,
 543         .timesync_enable              = i40e_timesync_enable,
 544         .timesync_disable             = i40e_timesync_disable,
 545         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 546         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 547         .get_dcb_info                 = i40e_dev_get_dcb_info,
 548         .timesync_adjust_time         = i40e_timesync_adjust_time,
 549         .timesync_read_time           = i40e_timesync_read_time,
 550         .timesync_write_time          = i40e_timesync_write_time,
 551         .get_reg                      = i40e_get_regs,
 552         .get_eeprom_length            = i40e_get_eeprom_length,
 553         .get_eeprom                   = i40e_get_eeprom,
 554         .mac_addr_set                 = i40e_set_default_mac_addr,
 555         .mtu_set                      = i40e_dev_mtu_set,
 556 };
 557
 558 /* store statistics names and its offset in stats structure */
 559 struct rte_i40e_xstats_name_off {
 560         char name[RTE_ETH_XSTATS_NAME_SIZE];
 561         unsigned offset;
 562 };
 563
 564 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 565         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 566         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 567         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 568         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 569         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 570                 rx_unknown_protocol)},
 571         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 572         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 573         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 574         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 575 };
 576
 577 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 578                 sizeof(rte_i40e_stats_strings[0]))
 579
 580 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 581         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 582                 tx_dropped_link_down)},
 583         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 584         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 585                 illegal_bytes)},
 586         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 587         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 588                 mac_local_faults)},
 589         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 590                 mac_remote_faults)},
 591         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 592                 rx_length_errors)},
 593         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 594         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 595         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 596         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 597         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 598         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 599                 rx_size_127)},
 600         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 601                 rx_size_255)},
 602         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 603                 rx_size_511)},
 604         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 605                 rx_size_1023)},
 606         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 607                 rx_size_1522)},
 608         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 609                 rx_size_big)},
 610         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 611                 rx_undersize)},
 612         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 613                 rx_oversize)},
 614         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 615                 mac_short_packet_dropped)},
 616         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 617                 rx_fragments)},
 618         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 619         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 620         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 621                 tx_size_127)},
 622         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 623                 tx_size_255)},
 624         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 625                 tx_size_511)},
 626         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 627                 tx_size_1023)},
 628         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 629                 tx_size_1522)},
 630         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 631                 tx_size_big)},
 632         {"rx_flow_director_atr_match_packets",
 633                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 634         {"rx_flow_director_sb_match_packets",
 635                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 636         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 637                 tx_lpi_status)},
 638         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 639                 rx_lpi_status)},
 640         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 641                 tx_lpi_count)},
 642         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 643                 rx_lpi_count)},
 644 };
 645
 646 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 647                 sizeof(rte_i40e_hw_port_strings[0]))
 648
 649 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 650         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 651                 priority_xon_rx)},
 652         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 653                 priority_xoff_rx)},
 654 };
 655
 656 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 657                 sizeof(rte_i40e_rxq_prio_strings[0]))
 658
 659 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 660         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 661                 priority_xon_tx)},
 662         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 663                 priority_xoff_tx)},
 664         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 665                 priority_xon_2_xoff)},
 666 };
 667
 668 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 669                 sizeof(rte_i40e_txq_prio_strings[0]))
 670
 671 static struct eth_driver rte_i40e_pmd = {
 672         .pci_drv = {
 673                 .id_table = pci_id_i40e_map,
 674                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 675                         RTE_PCI_DRV_DETACHABLE,
 676                 .probe = rte_eth_dev_pci_probe,
 677                 .remove = rte_eth_dev_pci_remove,
 678         },
 679         .eth_dev_init = eth_i40e_dev_init,
 680         .eth_dev_uninit = eth_i40e_dev_uninit,
 681         .dev_private_size = sizeof(struct i40e_adapter),
 682 };
 683
 684 static inline int
 685 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 686                                      struct rte_eth_link *link)
 687 {
 688         struct rte_eth_link *dst = link;
 689         struct rte_eth_link *src = &(dev->data->dev_link);
 690
 691         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 692                                         *(uint64_t *)src) == 0)
 693                 return -1;
 694
 695         return 0;
 696 }
 697
 698 static inline int
 699 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 700                                       struct rte_eth_link *link)
 701 {
 702         struct rte_eth_link *dst = &(dev->data->dev_link);
 703         struct rte_eth_link *src = link;
 704
 705         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 706                                         *(uint64_t *)src) == 0)
 707                 return -1;
 708
 709         return 0;
 710 }
 711
 712 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 713 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 714 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 715
 716 #ifndef I40E_GLQF_ORT
 717 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 718 #endif
 719 #ifndef I40E_GLQF_PIT
 720 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 721 #endif
 722
 723 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 724 {
 725         /*
 726          * Initialize registers for flexible payload, which should be set by NVM.
 727          * This should be removed from code once it is fixed in NVM.
 728          */
 729         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 730         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 731         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 732         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 733         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 734         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 735         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 736         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 737         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 738         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 739         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 740         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 741
 742         /* Initialize registers for parsing packet type of QinQ */
 743         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 744         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 745 }
 746
 747 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 748
 749 /*
 750  * Add a ethertype filter to drop all flow control frames transmitted
 751  * from VSIs.
 752 */
 753 static void
 754 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 755 {
 756         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 757         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 758                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 759                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 760         int ret;
 761
 762         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 763                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 764                                 pf->main_vsi_seid, 0,
 765                                 TRUE, NULL, NULL);
 766         if (ret)
 767                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 768                                   " frames from VSIs.");
 769 }
 770
 771 static int
 772 floating_veb_list_handler(__rte_unused const char *key,
 773                           const char *floating_veb_value,
 774                           void *opaque)
 775 {
 776         int idx = 0;
 777         unsigned int count = 0;
 778         char *end = NULL;
 779         int min, max;
 780         bool *vf_floating_veb = opaque;
 781
 782         while (isblank(*floating_veb_value))
 783                 floating_veb_value++;
 784
 785         /* Reset floating VEB configuration for VFs */
 786         for (idx = 0; idx < I40E_MAX_VF; idx++)
 787                 vf_floating_veb[idx] = false;
 788
 789         min = I40E_MAX_VF;
 790         do {
 791                 while (isblank(*floating_veb_value))
 792                         floating_veb_value++;
 793                 if (*floating_veb_value == '\0')
 794                         return -1;
 795                 errno = 0;
 796                 idx = strtoul(floating_veb_value, &end, 10);
 797                 if (errno || end == NULL)
 798                         return -1;
 799                 while (isblank(*end))
 800                         end++;
 801                 if (*end == '-') {
 802                         min = idx;
 803                 } else if ((*end == ';') || (*end == '\0')) {
 804                         max = idx;
 805                         if (min == I40E_MAX_VF)
 806                                 min = idx;
 807                         if (max >= I40E_MAX_VF)
 808                                 max = I40E_MAX_VF - 1;
 809                         for (idx = min; idx <= max; idx++) {
 810                                 vf_floating_veb[idx] = true;
 811                                 count++;
 812                         }
 813                         min = I40E_MAX_VF;
 814                 } else {
 815                         return -1;
 816                 }
 817                 floating_veb_value = end + 1;
 818         } while (*end != '\0');
 819
 820         if (count == 0)
 821                 return -1;
 822
 823         return 0;
 824 }
 825
 826 static void
 827 config_vf_floating_veb(struct rte_devargs *devargs,
 828                        uint16_t floating_veb,
 829                        bool *vf_floating_veb)
 830 {
 831         struct rte_kvargs *kvlist;
 832         int i;
 833         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 834
 835         if (!floating_veb)
 836                 return;
 837         /* All the VFs attach to the floating VEB by default
 838          * when the floating VEB is enabled.
 839          */
 840         for (i = 0; i < I40E_MAX_VF; i++)
 841                 vf_floating_veb[i] = true;
 842
 843         if (devargs == NULL)
 844                 return;
 845
 846         kvlist = rte_kvargs_parse(devargs->args, NULL);
 847         if (kvlist == NULL)
 848                 return;
 849
 850         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 851                 rte_kvargs_free(kvlist);
 852                 return;
 853         }
 854         /* When the floating_veb_list parameter exists, all the VFs
 855          * will attach to the legacy VEB firstly, then configure VFs
 856          * to the floating VEB according to the floating_veb_list.
 857          */
 858         if (rte_kvargs_process(kvlist, floating_veb_list,
 859                                floating_veb_list_handler,
 860                                vf_floating_veb) < 0) {
 861                 rte_kvargs_free(kvlist);
 862                 return;
 863         }
 864         rte_kvargs_free(kvlist);
 865 }
 866
 867 static int
 868 i40e_check_floating_handler(__rte_unused const char *key,
 869                             const char *value,
 870                             __rte_unused void *opaque)
 871 {
 872         if (strcmp(value, "1"))
 873                 return -1;
 874
 875         return 0;
 876 }
 877
 878 static int
 879 is_floating_veb_supported(struct rte_devargs *devargs)
 880 {
 881         struct rte_kvargs *kvlist;
 882         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 883
 884         if (devargs == NULL)
 885                 return 0;
 886
 887         kvlist = rte_kvargs_parse(devargs->args, NULL);
 888         if (kvlist == NULL)
 889                 return 0;
 890
 891         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 892                 rte_kvargs_free(kvlist);
 893                 return 0;
 894         }
 895         /* Floating VEB is enabled when there's key-value:
 896          * enable_floating_veb=1
 897          */
 898         if (rte_kvargs_process(kvlist, floating_veb_key,
 899                                i40e_check_floating_handler, NULL) < 0) {
 900                 rte_kvargs_free(kvlist);
 901                 return 0;
 902         }
 903         rte_kvargs_free(kvlist);
 904
 905         return 1;
 906 }
 907
 908 static void
 909 config_floating_veb(struct rte_eth_dev *dev)
 910 {
 911         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 912         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 913         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 914
 915         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 916
 917         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 918                 pf->floating_veb =
 919                         is_floating_veb_supported(pci_dev->device.devargs);
 920                 config_vf_floating_veb(pci_dev->device.devargs,
 921                                        pf->floating_veb,
 922                                        pf->floating_veb_list);
 923         } else {
 924                 pf->floating_veb = false;
 925         }
 926 }
 927
 928 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 929 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 930
 931 static int
 932 eth_i40e_dev_init(struct rte_eth_dev *dev)
 933 {
 934         struct rte_pci_device *pci_dev;
 935         struct rte_intr_handle *intr_handle;
 936         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 937         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 938         struct i40e_vsi *vsi;
 939         int ret;
 940         uint32_t len;
 941         uint8_t aq_fail = 0;
 942
 943         PMD_INIT_FUNC_TRACE();
 944
 945         dev->dev_ops = &i40e_eth_dev_ops;
 946         dev->rx_pkt_burst = i40e_recv_pkts;
 947         dev->tx_pkt_burst = i40e_xmit_pkts;
 948
 949         /* for secondary processes, we don't initialise any further as primary
 950          * has already done this work. Only check we don't need a different
 951          * RX function */
 952         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 953                 i40e_set_rx_function(dev);
 954                 i40e_set_tx_function(dev);
 955                 return 0;
 956         }
 957         pci_dev = I40E_DEV_TO_PCI(dev);
 958         intr_handle = &pci_dev->intr_handle;
 959
 960         rte_eth_copy_pci_info(dev, pci_dev);
 961
 962         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 963         pf->adapter->eth_dev = dev;
 964         pf->dev_data = dev->data;
 965
 966         hw->back = I40E_PF_TO_ADAPTER(pf);
 967         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 968         if (!hw->hw_addr) {
 969                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 970                              "as address is NULL");
 971                 return -ENODEV;
 972         }
 973
 974         hw->vendor_id = pci_dev->id.vendor_id;
 975         hw->device_id = pci_dev->id.device_id;
 976         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 977         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 978         hw->bus.device = pci_dev->addr.devid;
 979         hw->bus.func = pci_dev->addr.function;
 980         hw->adapter_stopped = 0;
 981
 982         /* Make sure all is clean before doing PF reset */
 983         i40e_clear_hw(hw);
 984
 985         /* Initialize the hardware */
 986         i40e_hw_init(dev);
 987
 988         /* Reset here to make sure all is clean for each PF */
 989         ret = i40e_pf_reset(hw);
 990         if (ret) {
 991                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 992                 return ret;
 993         }
 994
 995         /* Initialize the shared code (base driver) */
 996         ret = i40e_init_shared_code(hw);
 997         if (ret) {
 998                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 999                 return ret;
1000         }
1001
1002         /*
1003          * To work around the NVM issue, initialize registers
1004          * for flexible payload and packet type of QinQ by
1005          * software. It should be removed once issues are fixed
1006          * in NVM.
1007          */
1008         i40e_GLQF_reg_init(hw);
1009
1010         /* Initialize the input set for filters (hash and fd) to default value */
1011         i40e_filter_input_set_init(pf);
1012
1013         /* Initialize the parameters for adminq */
1014         i40e_init_adminq_parameter(hw);
1015         ret = i40e_init_adminq(hw);
1016         if (ret != I40E_SUCCESS) {
1017                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1018                 return -EIO;
1019         }
1020         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1021                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1022                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1023                      ((hw->nvm.version >> 12) & 0xf),
1024                      ((hw->nvm.version >> 4) & 0xff),
1025                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1026
1027         /* Need the special FW version to support floating VEB */
1028         config_floating_veb(dev);
1029         /* Clear PXE mode */
1030         i40e_clear_pxe_mode(hw);
1031         ret = i40e_dev_sync_phy_type(hw);
1032         if (ret) {
1033                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1034                 goto err_sync_phy_type;
1035         }
1036         /*
1037          * On X710, performance number is far from the expectation on recent
1038          * firmware versions. The fix for this issue may not be integrated in
1039          * the following firmware version. So the workaround in software driver
1040          * is needed. It needs to modify the initial values of 3 internal only
1041          * registers. Note that the workaround can be removed when it is fixed
1042          * in firmware in the future.
1043          */
1044         i40e_configure_registers(hw);
1045
1046         /* Get hw capabilities */
1047         ret = i40e_get_cap(hw);
1048         if (ret != I40E_SUCCESS) {
1049                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1050                 goto err_get_capabilities;
1051         }
1052
1053         /* Initialize parameters for PF */
1054         ret = i40e_pf_parameter_init(dev);
1055         if (ret != 0) {
1056                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1057                 goto err_parameter_init;
1058         }
1059
1060         /* Initialize the queue management */
1061         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1062         if (ret < 0) {
1063                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1064                 goto err_qp_pool_init;
1065         }
1066         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1067                                 hw->func_caps.num_msix_vectors - 1);
1068         if (ret < 0) {
1069                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1070                 goto err_msix_pool_init;
1071         }
1072
1073         /* Initialize lan hmc */
1074         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1075                                 hw->func_caps.num_rx_qp, 0, 0);
1076         if (ret != I40E_SUCCESS) {
1077                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1078                 goto err_init_lan_hmc;
1079         }
1080
1081         /* Configure lan hmc */
1082         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1083         if (ret != I40E_SUCCESS) {
1084                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1085                 goto err_configure_lan_hmc;
1086         }
1087
1088         /* Get and check the mac address */
1089         i40e_get_mac_addr(hw, hw->mac.addr);
1090         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1091                 PMD_INIT_LOG(ERR, "mac address is not valid");
1092                 ret = -EIO;
1093                 goto err_get_mac_addr;
1094         }
1095         /* Copy the permanent MAC address */
1096         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1097                         (struct ether_addr *) hw->mac.perm_addr);
1098
1099         /* Disable flow control */
1100         hw->fc.requested_mode = I40E_FC_NONE;
1101         i40e_set_fc(hw, &aq_fail, TRUE);
1102
1103         /* Set the global registers with default ether type value */
1104         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1105         if (ret != I40E_SUCCESS) {
1106                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1107                              "VLAN ether type");
1108                 goto err_setup_pf_switch;
1109         }
1110
1111         /* PF setup, which includes VSI setup */
1112         ret = i40e_pf_setup(pf);
1113         if (ret) {
1114                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1115                 goto err_setup_pf_switch;
1116         }
1117
1118         /* reset all stats of the device, including pf and main vsi */
1119         i40e_dev_stats_reset(dev);
1120
1121         vsi = pf->main_vsi;
1122
1123         /* Disable double vlan by default */
1124         i40e_vsi_config_double_vlan(vsi, FALSE);
1125
1126         /* Disable S-TAG identification when floating_veb is disabled */
1127         if (!pf->floating_veb) {
1128                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1129                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1130                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1131                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1132                 }
1133         }
1134
1135         if (!vsi->max_macaddrs)
1136                 len = ETHER_ADDR_LEN;
1137         else
1138                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1139
1140         /* Should be after VSI initialized */
1141         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1142         if (!dev->data->mac_addrs) {
1143                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1144                                         "for storing mac address");
1145                 goto err_mac_alloc;
1146         }
1147         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1148                                         &dev->data->mac_addrs[0]);
1149
1150         /* initialize pf host driver to setup SRIOV resource if applicable */
1151         i40e_pf_host_init(dev);
1152
1153         /* register callback func to eal lib */
1154         rte_intr_callback_register(intr_handle,
1155                                    i40e_dev_interrupt_handler, dev);
1156
1157         /* configure and enable device interrupt */
1158         i40e_pf_config_irq0(hw, TRUE);
1159         i40e_pf_enable_irq0(hw);
1160
1161         /* enable uio intr after callback register */
1162         rte_intr_enable(intr_handle);
1163         /*
1164          * Add an ethertype filter to drop all flow control frames transmitted
1165          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1166          * frames to wire.
1167          */
1168         i40e_add_tx_flow_control_drop_filter(pf);
1169
1170         /* Set the max frame size to 0x2600 by default,
1171          * in case other drivers changed the default value.
1172          */
1173         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1174
1175         /* initialize mirror rule list */
1176         TAILQ_INIT(&pf->mirror_list);
1177
1178         /* Init dcb to sw mode by default */
1179         ret = i40e_dcb_init_configure(dev, TRUE);
1180         if (ret != I40E_SUCCESS) {
1181                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1182                 pf->flags &= ~I40E_FLAG_DCB;
1183         }
1184
1185         return 0;
1186
1187 err_mac_alloc:
1188         i40e_vsi_release(pf->main_vsi);
1189 err_setup_pf_switch:
1190 err_get_mac_addr:
1191 err_configure_lan_hmc:
1192         (void)i40e_shutdown_lan_hmc(hw);
1193 err_init_lan_hmc:
1194         i40e_res_pool_destroy(&pf->msix_pool);
1195 err_msix_pool_init:
1196         i40e_res_pool_destroy(&pf->qp_pool);
1197 err_qp_pool_init:
1198 err_parameter_init:
1199 err_get_capabilities:
1200 err_sync_phy_type:
1201         (void)i40e_shutdown_adminq(hw);
1202
1203         return ret;
1204 }
1205
1206 static int
1207 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1208 {
1209         struct rte_pci_device *pci_dev;
1210         struct rte_intr_handle *intr_handle;
1211         struct i40e_hw *hw;
1212         struct i40e_filter_control_settings settings;
1213         int ret;
1214         uint8_t aq_fail = 0;
1215
1216         PMD_INIT_FUNC_TRACE();
1217
1218         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1219                 return 0;
1220
1221         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1222         pci_dev = I40E_DEV_TO_PCI(dev);
1223         intr_handle = &pci_dev->intr_handle;
1224
1225         if (hw->adapter_stopped == 0)
1226                 i40e_dev_close(dev);
1227
1228         dev->dev_ops = NULL;
1229         dev->rx_pkt_burst = NULL;
1230         dev->tx_pkt_burst = NULL;
1231
1232         /* Clear PXE mode */
1233         i40e_clear_pxe_mode(hw);
1234
1235         /* Unconfigure filter control */
1236         memset(&settings, 0, sizeof(settings));
1237         ret = i40e_set_filter_control(hw, &settings);
1238         if (ret)
1239                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1240                                         ret);
1241
1242         /* Disable flow control */
1243         hw->fc.requested_mode = I40E_FC_NONE;
1244         i40e_set_fc(hw, &aq_fail, TRUE);
1245
1246         /* uninitialize pf host driver */
1247         i40e_pf_host_uninit(dev);
1248
1249         rte_free(dev->data->mac_addrs);
1250         dev->data->mac_addrs = NULL;
1251
1252         /* disable uio intr before callback unregister */
1253         rte_intr_disable(intr_handle);
1254
1255         /* register callback func to eal lib */
1256         rte_intr_callback_unregister(intr_handle,
1257                                      i40e_dev_interrupt_handler, dev);
1258
1259         return 0;
1260 }
1261
1262 static int
1263 i40e_dev_configure(struct rte_eth_dev *dev)
1264 {
1265         struct i40e_adapter *ad =
1266                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1267         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1268         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1269         int i, ret;
1270
1271         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1272          * bulk allocation or vector Rx preconditions we will reset it.
1273          */
1274         ad->rx_bulk_alloc_allowed = true;
1275         ad->rx_vec_allowed = true;
1276         ad->tx_simple_allowed = true;
1277         ad->tx_vec_allowed = true;
1278
1279         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1280                 ret = i40e_fdir_setup(pf);
1281                 if (ret != I40E_SUCCESS) {
1282                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1283                         return -ENOTSUP;
1284                 }
1285                 ret = i40e_fdir_configure(dev);
1286                 if (ret < 0) {
1287                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1288                         goto err;
1289                 }
1290         } else
1291                 i40e_fdir_teardown(pf);
1292
1293         ret = i40e_dev_init_vlan(dev);
1294         if (ret < 0)
1295                 goto err;
1296
1297         /* VMDQ setup.
1298          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1299          *  RSS setting have different requirements.
1300          *  General PMD driver call sequence are NIC init, configure,
1301          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1302          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1303          *  applicable. So, VMDQ setting has to be done before
1304          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1305          *  For RSS setting, it will try to calculate actual configured RX queue
1306          *  number, which will be available after rx_queue_setup(). dev_start()
1307          *  function is good to place RSS setup.
1308          */
1309         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1310                 ret = i40e_vmdq_setup(dev);
1311                 if (ret)
1312                         goto err;
1313         }
1314
1315         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1316                 ret = i40e_dcb_setup(dev);
1317                 if (ret) {
1318                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1319                         goto err_dcb;
1320                 }
1321         }
1322
1323         return 0;
1324
1325 err_dcb:
1326         /* need to release vmdq resource if exists */
1327         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1328                 i40e_vsi_release(pf->vmdq[i].vsi);
1329                 pf->vmdq[i].vsi = NULL;
1330         }
1331         rte_free(pf->vmdq);
1332         pf->vmdq = NULL;
1333 err:
1334         /* need to release fdir resource if exists */
1335         i40e_fdir_teardown(pf);
1336         return ret;
1337 }
1338
1339 void
1340 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1341 {
1342         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1343         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1344         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1345         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1346         uint16_t msix_vect = vsi->msix_intr;
1347         uint16_t i;
1348
1349         for (i = 0; i < vsi->nb_qps; i++) {
1350                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1351                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1352                 rte_wmb();
1353         }
1354
1355         if (vsi->type != I40E_VSI_SRIOV) {
1356                 if (!rte_intr_allow_others(intr_handle)) {
1357                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1358                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1359                         I40E_WRITE_REG(hw,
1360                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1361                                        0);
1362                 } else {
1363                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1364                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1365                         I40E_WRITE_REG(hw,
1366                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1367                                                        msix_vect - 1), 0);
1368                 }
1369         } else {
1370                 uint32_t reg;
1371                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1372                         vsi->user_param + (msix_vect - 1);
1373
1374                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1375                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1376         }
1377         I40E_WRITE_FLUSH(hw);
1378 }
1379
1380 static void
1381 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1382                        int base_queue, int nb_queue)
1383 {
1384         int i;
1385         uint32_t val;
1386         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1387
1388         /* Bind all RX queues to allocated MSIX interrupt */
1389         for (i = 0; i < nb_queue; i++) {
1390                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1391                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1392                         ((base_queue + i + 1) <<
1393                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1394                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1395                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1396
1397                 if (i == nb_queue - 1)
1398                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1399                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1400         }
1401
1402         /* Write first RX queue to Link list register as the head element */
1403         if (vsi->type != I40E_VSI_SRIOV) {
1404                 uint16_t interval =
1405                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1406
1407                 if (msix_vect == I40E_MISC_VEC_ID) {
1408                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1409                                        (base_queue <<
1410                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1411                                        (0x0 <<
1412                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1413                         I40E_WRITE_REG(hw,
1414                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1415                                        interval);
1416                 } else {
1417                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1418                                        (base_queue <<
1419                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1420                                        (0x0 <<
1421                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1422                         I40E_WRITE_REG(hw,
1423                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1424                                                        msix_vect - 1),
1425                                        interval);
1426                 }
1427         } else {
1428                 uint32_t reg;
1429
1430                 if (msix_vect == I40E_MISC_VEC_ID) {
1431                         I40E_WRITE_REG(hw,
1432                                        I40E_VPINT_LNKLST0(vsi->user_param),
1433                                        (base_queue <<
1434                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1435                                        (0x0 <<
1436                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1437                 } else {
1438                         /* num_msix_vectors_vf needs to minus irq0 */
1439                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1440                                 vsi->user_param + (msix_vect - 1);
1441
1442                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1443                                        (base_queue <<
1444                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1445                                        (0x0 <<
1446                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1447                 }
1448         }
1449
1450         I40E_WRITE_FLUSH(hw);
1451 }
1452
1453 void
1454 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1455 {
1456         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1457         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1458         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1459         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1460         uint16_t msix_vect = vsi->msix_intr;
1461         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1462         uint16_t queue_idx = 0;
1463         int record = 0;
1464         uint32_t val;
1465         int i;
1466
1467         for (i = 0; i < vsi->nb_qps; i++) {
1468                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1469                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1470         }
1471
1472         /* INTENA flag is not auto-cleared for interrupt */
1473         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1474         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1475                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1476                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1477         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1478
1479         /* VF bind interrupt */
1480         if (vsi->type == I40E_VSI_SRIOV) {
1481                 __vsi_queues_bind_intr(vsi, msix_vect,
1482                                        vsi->base_queue, vsi->nb_qps);
1483                 return;
1484         }
1485
1486         /* PF & VMDq bind interrupt */
1487         if (rte_intr_dp_is_en(intr_handle)) {
1488                 if (vsi->type == I40E_VSI_MAIN) {
1489                         queue_idx = 0;
1490                         record = 1;
1491                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1492                         struct i40e_vsi *main_vsi =
1493                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1494                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1495                         record = 1;
1496                 }
1497         }
1498
1499         for (i = 0; i < vsi->nb_used_qps; i++) {
1500                 if (nb_msix <= 1) {
1501                         if (!rte_intr_allow_others(intr_handle))
1502                                 /* allow to share MISC_VEC_ID */
1503                                 msix_vect = I40E_MISC_VEC_ID;
1504
1505                         /* no enough msix_vect, map all to one */
1506                         __vsi_queues_bind_intr(vsi, msix_vect,
1507                                                vsi->base_queue + i,
1508                                                vsi->nb_used_qps - i);
1509                         for (; !!record && i < vsi->nb_used_qps; i++)
1510                                 intr_handle->intr_vec[queue_idx + i] =
1511                                         msix_vect;
1512                         break;
1513                 }
1514                 /* 1:1 queue/msix_vect mapping */
1515                 __vsi_queues_bind_intr(vsi, msix_vect,
1516                                        vsi->base_queue + i, 1);
1517                 if (!!record)
1518                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1519
1520                 msix_vect++;
1521                 nb_msix--;
1522         }
1523 }
1524
1525 static void
1526 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1527 {
1528         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1529         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1530         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1531         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1532         uint16_t interval = i40e_calc_itr_interval(\
1533                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1534         uint16_t msix_intr, i;
1535
1536         if (rte_intr_allow_others(intr_handle))
1537                 for (i = 0; i < vsi->nb_msix; i++) {
1538                         msix_intr = vsi->msix_intr + i;
1539                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1540                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1541                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1542                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1543                                 (interval <<
1544                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1545                 }
1546         else
1547                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1548                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1549                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1550                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1551                                (interval <<
1552                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1553
1554         I40E_WRITE_FLUSH(hw);
1555 }
1556
1557 static void
1558 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1559 {
1560         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1561         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1562         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1563         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1564         uint16_t msix_intr, i;
1565
1566         if (rte_intr_allow_others(intr_handle))
1567                 for (i = 0; i < vsi->nb_msix; i++) {
1568                         msix_intr = vsi->msix_intr + i;
1569                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1570                                        0);
1571                 }
1572         else
1573                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1574
1575         I40E_WRITE_FLUSH(hw);
1576 }
1577
1578 static inline uint8_t
1579 i40e_parse_link_speeds(uint16_t link_speeds)
1580 {
1581         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1582
1583         if (link_speeds & ETH_LINK_SPEED_40G)
1584                 link_speed |= I40E_LINK_SPEED_40GB;
1585         if (link_speeds & ETH_LINK_SPEED_25G)
1586                 link_speed |= I40E_LINK_SPEED_25GB;
1587         if (link_speeds & ETH_LINK_SPEED_20G)
1588                 link_speed |= I40E_LINK_SPEED_20GB;
1589         if (link_speeds & ETH_LINK_SPEED_10G)
1590                 link_speed |= I40E_LINK_SPEED_10GB;
1591         if (link_speeds & ETH_LINK_SPEED_1G)
1592                 link_speed |= I40E_LINK_SPEED_1GB;
1593         if (link_speeds & ETH_LINK_SPEED_100M)
1594                 link_speed |= I40E_LINK_SPEED_100MB;
1595
1596         return link_speed;
1597 }
1598
1599 static int
1600 i40e_phy_conf_link(struct i40e_hw *hw,
1601                    uint8_t abilities,
1602                    uint8_t force_speed)
1603 {
1604         enum i40e_status_code status;
1605         struct i40e_aq_get_phy_abilities_resp phy_ab;
1606         struct i40e_aq_set_phy_config phy_conf;
1607         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1608                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1609                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1610                         I40E_AQ_PHY_FLAG_LOW_POWER;
1611         const uint8_t advt = I40E_LINK_SPEED_40GB |
1612                         I40E_LINK_SPEED_25GB |
1613                         I40E_LINK_SPEED_10GB |
1614                         I40E_LINK_SPEED_1GB |
1615                         I40E_LINK_SPEED_100MB;
1616         int ret = -ENOTSUP;
1617
1618
1619         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1620                                               NULL);
1621         if (status)
1622                 return ret;
1623
1624         memset(&phy_conf, 0, sizeof(phy_conf));
1625
1626         /* bits 0-2 use the values from get_phy_abilities_resp */
1627         abilities &= ~mask;
1628         abilities |= phy_ab.abilities & mask;
1629
1630         /* update ablities and speed */
1631         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1632                 phy_conf.link_speed = advt;
1633         else
1634                 phy_conf.link_speed = force_speed;
1635
1636         phy_conf.abilities = abilities;
1637
1638         /* use get_phy_abilities_resp value for the rest */
1639         phy_conf.phy_type = phy_ab.phy_type;
1640         phy_conf.eee_capability = phy_ab.eee_capability;
1641         phy_conf.eeer = phy_ab.eeer_val;
1642         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1643
1644         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1645                     phy_ab.abilities, phy_ab.link_speed);
1646         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1647                     phy_conf.abilities, phy_conf.link_speed);
1648
1649         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1650         if (status)
1651                 return ret;
1652
1653         return I40E_SUCCESS;
1654 }
1655
1656 static int
1657 i40e_apply_link_speed(struct rte_eth_dev *dev)
1658 {
1659         uint8_t speed;
1660         uint8_t abilities = 0;
1661         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1662         struct rte_eth_conf *conf = &dev->data->dev_conf;
1663
1664         speed = i40e_parse_link_speeds(conf->link_speeds);
1665         if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
1666                 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1667         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1668                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1669         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1670
1671         /* Skip changing speed on 40G interfaces, FW does not support */
1672         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1673                 speed =  I40E_LINK_SPEED_UNKNOWN;
1674                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1675         }
1676
1677         return i40e_phy_conf_link(hw, abilities, speed);
1678 }
1679
1680 static int
1681 i40e_dev_start(struct rte_eth_dev *dev)
1682 {
1683         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1684         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1685         struct i40e_vsi *main_vsi = pf->main_vsi;
1686         int ret, i;
1687         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1688         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1689         uint32_t intr_vector = 0;
1690
1691         hw->adapter_stopped = 0;
1692
1693         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1694                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1695                              dev->data->port_id);
1696                 return -EINVAL;
1697         }
1698
1699         rte_intr_disable(intr_handle);
1700
1701         if ((rte_intr_cap_multiple(intr_handle) ||
1702              !RTE_ETH_DEV_SRIOV(dev).active) &&
1703             dev->data->dev_conf.intr_conf.rxq != 0) {
1704                 intr_vector = dev->data->nb_rx_queues;
1705                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1706                         return -1;
1707         }
1708
1709         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1710                 intr_handle->intr_vec =
1711                         rte_zmalloc("intr_vec",
1712                                     dev->data->nb_rx_queues * sizeof(int),
1713                                     0);
1714                 if (!intr_handle->intr_vec) {
1715                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1716                                      " intr_vec\n", dev->data->nb_rx_queues);
1717                         return -ENOMEM;
1718                 }
1719         }
1720
1721         /* Initialize VSI */
1722         ret = i40e_dev_rxtx_init(pf);
1723         if (ret != I40E_SUCCESS) {
1724                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1725                 goto err_up;
1726         }
1727
1728         /* Map queues with MSIX interrupt */
1729         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1730                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1731         i40e_vsi_queues_bind_intr(main_vsi);
1732         i40e_vsi_enable_queues_intr(main_vsi);
1733
1734         /* Map VMDQ VSI queues with MSIX interrupt */
1735         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1736                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1737                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1738                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1739         }
1740
1741         /* enable FDIR MSIX interrupt */
1742         if (pf->fdir.fdir_vsi) {
1743                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1744                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1745         }
1746
1747         /* Enable all queues which have been configured */
1748         ret = i40e_dev_switch_queues(pf, TRUE);
1749         if (ret != I40E_SUCCESS) {
1750                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1751                 goto err_up;
1752         }
1753
1754         /* Enable receiving broadcast packets */
1755         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1756         if (ret != I40E_SUCCESS)
1757                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1758
1759         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1760                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1761                                                 true, NULL);
1762                 if (ret != I40E_SUCCESS)
1763                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1764         }
1765
1766         /* Apply link configure */
1767         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1768                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1769                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1770                                 ETH_LINK_SPEED_40G)) {
1771                 PMD_DRV_LOG(ERR, "Invalid link setting");
1772                 goto err_up;
1773         }
1774         ret = i40e_apply_link_speed(dev);
1775         if (I40E_SUCCESS != ret) {
1776                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1777                 goto err_up;
1778         }
1779
1780         if (!rte_intr_allow_others(intr_handle)) {
1781                 rte_intr_callback_unregister(intr_handle,
1782                                              i40e_dev_interrupt_handler,
1783                                              (void *)dev);
1784                 /* configure and enable device interrupt */
1785                 i40e_pf_config_irq0(hw, FALSE);
1786                 i40e_pf_enable_irq0(hw);
1787
1788                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1789                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1790                                      " no intr multiplex\n");
1791         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1792                 ret = i40e_aq_set_phy_int_mask(hw,
1793                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1794                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1795                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1796                 if (ret != I40E_SUCCESS)
1797                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1798
1799                 /* Call get_link_info aq commond to enable LSE */
1800                 i40e_dev_link_update(dev, 0);
1801         }
1802
1803         /* enable uio intr after callback register */
1804         rte_intr_enable(intr_handle);
1805
1806         return I40E_SUCCESS;
1807
1808 err_up:
1809         i40e_dev_switch_queues(pf, FALSE);
1810         i40e_dev_clear_queues(dev);
1811
1812         return ret;
1813 }
1814
1815 static void
1816 i40e_dev_stop(struct rte_eth_dev *dev)
1817 {
1818         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1819         struct i40e_vsi *main_vsi = pf->main_vsi;
1820         struct i40e_mirror_rule *p_mirror;
1821         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1822         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1823         int i;
1824
1825         /* Disable all queues */
1826         i40e_dev_switch_queues(pf, FALSE);
1827
1828         /* un-map queues with interrupt registers */
1829         i40e_vsi_disable_queues_intr(main_vsi);
1830         i40e_vsi_queues_unbind_intr(main_vsi);
1831
1832         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1833                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1834                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1835         }
1836
1837         if (pf->fdir.fdir_vsi) {
1838                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1839                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1840         }
1841         /* Clear all queues and release memory */
1842         i40e_dev_clear_queues(dev);
1843
1844         /* Set link down */
1845         i40e_dev_set_link_down(dev);
1846
1847         /* Remove all mirror rules */
1848         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1849                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1850                 rte_free(p_mirror);
1851         }
1852         pf->nb_mirror_rule = 0;
1853
1854         if (!rte_intr_allow_others(intr_handle))
1855                 /* resume to the default handler */
1856                 rte_intr_callback_register(intr_handle,
1857                                            i40e_dev_interrupt_handler,
1858                                            (void *)dev);
1859
1860         /* Clean datapath event and queue/vec mapping */
1861         rte_intr_efd_disable(intr_handle);
1862         if (intr_handle->intr_vec) {
1863                 rte_free(intr_handle->intr_vec);
1864                 intr_handle->intr_vec = NULL;
1865         }
1866 }
1867
1868 static void
1869 i40e_dev_close(struct rte_eth_dev *dev)
1870 {
1871         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1872         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1873         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1874         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1875         uint32_t reg;
1876         int i;
1877
1878         PMD_INIT_FUNC_TRACE();
1879
1880         i40e_dev_stop(dev);
1881         hw->adapter_stopped = 1;
1882         i40e_dev_free_queues(dev);
1883
1884         /* Disable interrupt */
1885         i40e_pf_disable_irq0(hw);
1886         rte_intr_disable(intr_handle);
1887
1888         /* shutdown and destroy the HMC */
1889         i40e_shutdown_lan_hmc(hw);
1890
1891         /* release all the existing VSIs and VEBs */
1892         i40e_fdir_teardown(pf);
1893         i40e_vsi_release(pf->main_vsi);
1894
1895         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1896                 i40e_vsi_release(pf->vmdq[i].vsi);
1897                 pf->vmdq[i].vsi = NULL;
1898         }
1899
1900         rte_free(pf->vmdq);
1901         pf->vmdq = NULL;
1902
1903         /* shutdown the adminq */
1904         i40e_aq_queue_shutdown(hw, true);
1905         i40e_shutdown_adminq(hw);
1906
1907         i40e_res_pool_destroy(&pf->qp_pool);
1908         i40e_res_pool_destroy(&pf->msix_pool);
1909
1910         /* force a PF reset to clean anything leftover */
1911         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1912         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1913                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1914         I40E_WRITE_FLUSH(hw);
1915 }
1916
1917 static void
1918 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1919 {
1920         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1921         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         struct i40e_vsi *vsi = pf->main_vsi;
1923         int status;
1924
1925         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1926                                                      true, NULL, true);
1927         if (status != I40E_SUCCESS)
1928                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1929
1930         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1931                                                         TRUE, NULL);
1932         if (status != I40E_SUCCESS)
1933                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1934
1935 }
1936
1937 static void
1938 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1939 {
1940         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1941         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942         struct i40e_vsi *vsi = pf->main_vsi;
1943         int status;
1944
1945         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1946                                                      false, NULL, true);
1947         if (status != I40E_SUCCESS)
1948                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1949
1950         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1951                                                         false, NULL);
1952         if (status != I40E_SUCCESS)
1953                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1954 }
1955
1956 static void
1957 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1958 {
1959         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1960         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1961         struct i40e_vsi *vsi = pf->main_vsi;
1962         int ret;
1963
1964         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1965         if (ret != I40E_SUCCESS)
1966                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1967 }
1968
1969 static void
1970 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1971 {
1972         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1973         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1974         struct i40e_vsi *vsi = pf->main_vsi;
1975         int ret;
1976
1977         if (dev->data->promiscuous == 1)
1978                 return; /* must remain in all_multicast mode */
1979
1980         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1981                                 vsi->seid, FALSE, NULL);
1982         if (ret != I40E_SUCCESS)
1983                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1984 }
1985
1986 /*
1987  * Set device link up.
1988  */
1989 static int
1990 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1991 {
1992         /* re-apply link speed setting */
1993         return i40e_apply_link_speed(dev);
1994 }
1995
1996 /*
1997  * Set device link down.
1998  */
1999 static int
2000 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2001 {
2002         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2003         uint8_t abilities = 0;
2004         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2005
2006         if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2007                 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2008         return i40e_phy_conf_link(hw, abilities, speed);
2009 }
2010
2011 int
2012 i40e_dev_link_update(struct rte_eth_dev *dev,
2013                      int wait_to_complete)
2014 {
2015 #define CHECK_INTERVAL 100  /* 100ms */
2016 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2017         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2018         struct i40e_link_status link_status;
2019         struct rte_eth_link link, old;
2020         int status;
2021         unsigned rep_cnt = MAX_REPEAT_TIME;
2022         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2023
2024         memset(&link, 0, sizeof(link));
2025         memset(&old, 0, sizeof(old));
2026         memset(&link_status, 0, sizeof(link_status));
2027         rte_i40e_dev_atomic_read_link_status(dev, &old);
2028
2029         do {
2030                 /* Get link status information from hardware */
2031                 status = i40e_aq_get_link_info(hw, enable_lse,
2032                                                 &link_status, NULL);
2033                 if (status != I40E_SUCCESS) {
2034                         link.link_speed = ETH_SPEED_NUM_100M;
2035                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2036                         PMD_DRV_LOG(ERR, "Failed to get link info");
2037                         goto out;
2038                 }
2039
2040                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2041                 if (!wait_to_complete)
2042                         break;
2043
2044                 rte_delay_ms(CHECK_INTERVAL);
2045         } while (!link.link_status && rep_cnt--);
2046
2047         if (!link.link_status)
2048                 goto out;
2049
2050         /* i40e uses full duplex only */
2051         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2052
2053         /* Parse the link status */
2054         switch (link_status.link_speed) {
2055         case I40E_LINK_SPEED_100MB:
2056                 link.link_speed = ETH_SPEED_NUM_100M;
2057                 break;
2058         case I40E_LINK_SPEED_1GB:
2059                 link.link_speed = ETH_SPEED_NUM_1G;
2060                 break;
2061         case I40E_LINK_SPEED_10GB:
2062                 link.link_speed = ETH_SPEED_NUM_10G;
2063                 break;
2064         case I40E_LINK_SPEED_20GB:
2065                 link.link_speed = ETH_SPEED_NUM_20G;
2066                 break;
2067         case I40E_LINK_SPEED_25GB:
2068                 link.link_speed = ETH_SPEED_NUM_25G;
2069                 break;
2070         case I40E_LINK_SPEED_40GB:
2071                 link.link_speed = ETH_SPEED_NUM_40G;
2072                 break;
2073         default:
2074                 link.link_speed = ETH_SPEED_NUM_100M;
2075                 break;
2076         }
2077
2078         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2079                         ETH_LINK_SPEED_FIXED);
2080
2081 out:
2082         rte_i40e_dev_atomic_write_link_status(dev, &link);
2083         if (link.link_status == old.link_status)
2084                 return -1;
2085
2086         return 0;
2087 }
2088
2089 /* Get all the statistics of a VSI */
2090 void
2091 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2092 {
2093         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2094         struct i40e_eth_stats *nes = &vsi->eth_stats;
2095         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2096         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2097
2098         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2099                             vsi->offset_loaded, &oes->rx_bytes,
2100                             &nes->rx_bytes);
2101         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2102                             vsi->offset_loaded, &oes->rx_unicast,
2103                             &nes->rx_unicast);
2104         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2105                             vsi->offset_loaded, &oes->rx_multicast,
2106                             &nes->rx_multicast);
2107         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2108                             vsi->offset_loaded, &oes->rx_broadcast,
2109                             &nes->rx_broadcast);
2110         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2111                             &oes->rx_discards, &nes->rx_discards);
2112         /* GLV_REPC not supported */
2113         /* GLV_RMPC not supported */
2114         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2115                             &oes->rx_unknown_protocol,
2116                             &nes->rx_unknown_protocol);
2117         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2118                             vsi->offset_loaded, &oes->tx_bytes,
2119                             &nes->tx_bytes);
2120         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2121                             vsi->offset_loaded, &oes->tx_unicast,
2122                             &nes->tx_unicast);
2123         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2124                             vsi->offset_loaded, &oes->tx_multicast,
2125                             &nes->tx_multicast);
2126         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2127                             vsi->offset_loaded,  &oes->tx_broadcast,
2128                             &nes->tx_broadcast);
2129         /* GLV_TDPC not supported */
2130         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2131                             &oes->tx_errors, &nes->tx_errors);
2132         vsi->offset_loaded = true;
2133
2134         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2135                     vsi->vsi_id);
2136         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2137         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2138         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2139         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2140         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2141         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2142                     nes->rx_unknown_protocol);
2143         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2144         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2145         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2146         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2147         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2148         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2149         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2150                     vsi->vsi_id);
2151 }
2152
2153 static void
2154 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2155 {
2156         unsigned int i;
2157         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2158         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2159
2160         /* Get statistics of struct i40e_eth_stats */
2161         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2162                             I40E_GLPRT_GORCL(hw->port),
2163                             pf->offset_loaded, &os->eth.rx_bytes,
2164                             &ns->eth.rx_bytes);
2165         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2166                             I40E_GLPRT_UPRCL(hw->port),
2167                             pf->offset_loaded, &os->eth.rx_unicast,
2168                             &ns->eth.rx_unicast);
2169         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2170                             I40E_GLPRT_MPRCL(hw->port),
2171                             pf->offset_loaded, &os->eth.rx_multicast,
2172                             &ns->eth.rx_multicast);
2173         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2174                             I40E_GLPRT_BPRCL(hw->port),
2175                             pf->offset_loaded, &os->eth.rx_broadcast,
2176                             &ns->eth.rx_broadcast);
2177         /* Workaround: CRC size should not be included in byte statistics,
2178          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2179          */
2180         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2181                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2182
2183         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2184                             pf->offset_loaded, &os->eth.rx_discards,
2185                             &ns->eth.rx_discards);
2186         /* GLPRT_REPC not supported */
2187         /* GLPRT_RMPC not supported */
2188         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2189                             pf->offset_loaded,
2190                             &os->eth.rx_unknown_protocol,
2191                             &ns->eth.rx_unknown_protocol);
2192         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2193                             I40E_GLPRT_GOTCL(hw->port),
2194                             pf->offset_loaded, &os->eth.tx_bytes,
2195                             &ns->eth.tx_bytes);
2196         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2197                             I40E_GLPRT_UPTCL(hw->port),
2198                             pf->offset_loaded, &os->eth.tx_unicast,
2199                             &ns->eth.tx_unicast);
2200         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2201                             I40E_GLPRT_MPTCL(hw->port),
2202                             pf->offset_loaded, &os->eth.tx_multicast,
2203                             &ns->eth.tx_multicast);
2204         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2205                             I40E_GLPRT_BPTCL(hw->port),
2206                             pf->offset_loaded, &os->eth.tx_broadcast,
2207                             &ns->eth.tx_broadcast);
2208         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2209                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2210         /* GLPRT_TEPC not supported */
2211
2212         /* additional port specific stats */
2213         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2214                             pf->offset_loaded, &os->tx_dropped_link_down,
2215                             &ns->tx_dropped_link_down);
2216         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2217                             pf->offset_loaded, &os->crc_errors,
2218                             &ns->crc_errors);
2219         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2220                             pf->offset_loaded, &os->illegal_bytes,
2221                             &ns->illegal_bytes);
2222         /* GLPRT_ERRBC not supported */
2223         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2224                             pf->offset_loaded, &os->mac_local_faults,
2225                             &ns->mac_local_faults);
2226         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2227                             pf->offset_loaded, &os->mac_remote_faults,
2228                             &ns->mac_remote_faults);
2229         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2230                             pf->offset_loaded, &os->rx_length_errors,
2231                             &ns->rx_length_errors);
2232         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2233                             pf->offset_loaded, &os->link_xon_rx,
2234                             &ns->link_xon_rx);
2235         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2236                             pf->offset_loaded, &os->link_xoff_rx,
2237                             &ns->link_xoff_rx);
2238         for (i = 0; i < 8; i++) {
2239                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2240                                     pf->offset_loaded,
2241                                     &os->priority_xon_rx[i],
2242                                     &ns->priority_xon_rx[i]);
2243                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2244                                     pf->offset_loaded,
2245                                     &os->priority_xoff_rx[i],
2246                                     &ns->priority_xoff_rx[i]);
2247         }
2248         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2249                             pf->offset_loaded, &os->link_xon_tx,
2250                             &ns->link_xon_tx);
2251         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2252                             pf->offset_loaded, &os->link_xoff_tx,
2253                             &ns->link_xoff_tx);
2254         for (i = 0; i < 8; i++) {
2255                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2256                                     pf->offset_loaded,
2257                                     &os->priority_xon_tx[i],
2258                                     &ns->priority_xon_tx[i]);
2259                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2260                                     pf->offset_loaded,
2261                                     &os->priority_xoff_tx[i],
2262                                     &ns->priority_xoff_tx[i]);
2263                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2264                                     pf->offset_loaded,
2265                                     &os->priority_xon_2_xoff[i],
2266                                     &ns->priority_xon_2_xoff[i]);
2267         }
2268         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2269                             I40E_GLPRT_PRC64L(hw->port),
2270                             pf->offset_loaded, &os->rx_size_64,
2271                             &ns->rx_size_64);
2272         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2273                             I40E_GLPRT_PRC127L(hw->port),
2274                             pf->offset_loaded, &os->rx_size_127,
2275                             &ns->rx_size_127);
2276         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2277                             I40E_GLPRT_PRC255L(hw->port),
2278                             pf->offset_loaded, &os->rx_size_255,
2279                             &ns->rx_size_255);
2280         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2281                             I40E_GLPRT_PRC511L(hw->port),
2282                             pf->offset_loaded, &os->rx_size_511,
2283                             &ns->rx_size_511);
2284         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2285                             I40E_GLPRT_PRC1023L(hw->port),
2286                             pf->offset_loaded, &os->rx_size_1023,
2287                             &ns->rx_size_1023);
2288         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2289                             I40E_GLPRT_PRC1522L(hw->port),
2290                             pf->offset_loaded, &os->rx_size_1522,
2291                             &ns->rx_size_1522);
2292         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2293                             I40E_GLPRT_PRC9522L(hw->port),
2294                             pf->offset_loaded, &os->rx_size_big,
2295                             &ns->rx_size_big);
2296         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2297                             pf->offset_loaded, &os->rx_undersize,
2298                             &ns->rx_undersize);
2299         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2300                             pf->offset_loaded, &os->rx_fragments,
2301                             &ns->rx_fragments);
2302         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2303                             pf->offset_loaded, &os->rx_oversize,
2304                             &ns->rx_oversize);
2305         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2306                             pf->offset_loaded, &os->rx_jabber,
2307                             &ns->rx_jabber);
2308         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2309                             I40E_GLPRT_PTC64L(hw->port),
2310                             pf->offset_loaded, &os->tx_size_64,
2311                             &ns->tx_size_64);
2312         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2313                             I40E_GLPRT_PTC127L(hw->port),
2314                             pf->offset_loaded, &os->tx_size_127,
2315                             &ns->tx_size_127);
2316         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2317                             I40E_GLPRT_PTC255L(hw->port),
2318                             pf->offset_loaded, &os->tx_size_255,
2319                             &ns->tx_size_255);
2320         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2321                             I40E_GLPRT_PTC511L(hw->port),
2322                             pf->offset_loaded, &os->tx_size_511,
2323                             &ns->tx_size_511);
2324         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2325                             I40E_GLPRT_PTC1023L(hw->port),
2326                             pf->offset_loaded, &os->tx_size_1023,
2327                             &ns->tx_size_1023);
2328         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2329                             I40E_GLPRT_PTC1522L(hw->port),
2330                             pf->offset_loaded, &os->tx_size_1522,
2331                             &ns->tx_size_1522);
2332         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2333                             I40E_GLPRT_PTC9522L(hw->port),
2334                             pf->offset_loaded, &os->tx_size_big,
2335                             &ns->tx_size_big);
2336         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2337                            pf->offset_loaded,
2338                            &os->fd_sb_match, &ns->fd_sb_match);
2339         /* GLPRT_MSPDC not supported */
2340         /* GLPRT_XEC not supported */
2341
2342         pf->offset_loaded = true;
2343
2344         if (pf->main_vsi)
2345                 i40e_update_vsi_stats(pf->main_vsi);
2346 }
2347
2348 /* Get all statistics of a port */
2349 static void
2350 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2351 {
2352         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2353         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2354         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2355         unsigned i;
2356
2357         /* call read registers - updates values, now write them to struct */
2358         i40e_read_stats_registers(pf, hw);
2359
2360         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2361                         pf->main_vsi->eth_stats.rx_multicast +
2362                         pf->main_vsi->eth_stats.rx_broadcast -
2363                         pf->main_vsi->eth_stats.rx_discards;
2364         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2365                         pf->main_vsi->eth_stats.tx_multicast +
2366                         pf->main_vsi->eth_stats.tx_broadcast;
2367         stats->ibytes   = ns->eth.rx_bytes;
2368         stats->obytes   = ns->eth.tx_bytes;
2369         stats->oerrors  = ns->eth.tx_errors +
2370                         pf->main_vsi->eth_stats.tx_errors;
2371
2372         /* Rx Errors */
2373         stats->imissed  = ns->eth.rx_discards +
2374                         pf->main_vsi->eth_stats.rx_discards;
2375         stats->ierrors  = ns->crc_errors +
2376                         ns->rx_length_errors + ns->rx_undersize +
2377                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2378
2379         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2380         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2381         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2382         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2383         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2384         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2385         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2386                     ns->eth.rx_unknown_protocol);
2387         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2388         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2389         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2390         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2391         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2392         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2393
2394         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2395                     ns->tx_dropped_link_down);
2396         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2397         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2398                     ns->illegal_bytes);
2399         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2400         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2401                     ns->mac_local_faults);
2402         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2403                     ns->mac_remote_faults);
2404         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2405                     ns->rx_length_errors);
2406         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2407         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2408         for (i = 0; i < 8; i++) {
2409                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2410                                 i, ns->priority_xon_rx[i]);
2411                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2412                                 i, ns->priority_xoff_rx[i]);
2413         }
2414         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2415         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2416         for (i = 0; i < 8; i++) {
2417                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2418                                 i, ns->priority_xon_tx[i]);
2419                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2420                                 i, ns->priority_xoff_tx[i]);
2421                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2422                                 i, ns->priority_xon_2_xoff[i]);
2423         }
2424         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2425         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2426         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2427         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2428         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2429         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2430         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2431         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2432         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2433         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2434         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2435         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2436         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2437         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2438         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2439         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2440         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2441         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2442         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2443                         ns->mac_short_packet_dropped);
2444         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2445                     ns->checksum_error);
2446         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2447         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2448 }
2449
2450 /* Reset the statistics */
2451 static void
2452 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2453 {
2454         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2455         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2456
2457         /* Mark PF and VSI stats to update the offset, aka "reset" */
2458         pf->offset_loaded = false;
2459         if (pf->main_vsi)
2460                 pf->main_vsi->offset_loaded = false;
2461
2462         /* read the stats, reading current register values into offset */
2463         i40e_read_stats_registers(pf, hw);
2464 }
2465
2466 static uint32_t
2467 i40e_xstats_calc_num(void)
2468 {
2469         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2470                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2471                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2472 }
2473
2474 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2475                                      struct rte_eth_xstat_name *xstats_names,
2476                                      __rte_unused unsigned limit)
2477 {
2478         unsigned count = 0;
2479         unsigned i, prio;
2480
2481         if (xstats_names == NULL)
2482                 return i40e_xstats_calc_num();
2483
2484         /* Note: limit checked in rte_eth_xstats_names() */
2485
2486         /* Get stats from i40e_eth_stats struct */
2487         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2488                 snprintf(xstats_names[count].name,
2489                          sizeof(xstats_names[count].name),
2490                          "%s", rte_i40e_stats_strings[i].name);
2491                 count++;
2492         }
2493
2494         /* Get individiual stats from i40e_hw_port struct */
2495         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2496                 snprintf(xstats_names[count].name,
2497                         sizeof(xstats_names[count].name),
2498                          "%s", rte_i40e_hw_port_strings[i].name);
2499                 count++;
2500         }
2501
2502         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2503                 for (prio = 0; prio < 8; prio++) {
2504                         snprintf(xstats_names[count].name,
2505                                  sizeof(xstats_names[count].name),
2506                                  "rx_priority%u_%s", prio,
2507                                  rte_i40e_rxq_prio_strings[i].name);
2508                         count++;
2509                 }
2510         }
2511
2512         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2513                 for (prio = 0; prio < 8; prio++) {
2514                         snprintf(xstats_names[count].name,
2515                                  sizeof(xstats_names[count].name),
2516                                  "tx_priority%u_%s", prio,
2517                                  rte_i40e_txq_prio_strings[i].name);
2518                         count++;
2519                 }
2520         }
2521         return count;
2522 }
2523
2524 static int
2525 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2526                     unsigned n)
2527 {
2528         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2529         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2530         unsigned i, count, prio;
2531         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2532
2533         count = i40e_xstats_calc_num();
2534         if (n < count)
2535                 return count;
2536
2537         i40e_read_stats_registers(pf, hw);
2538
2539         if (xstats == NULL)
2540                 return 0;
2541
2542         count = 0;
2543
2544         /* Get stats from i40e_eth_stats struct */
2545         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2546                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2547                         rte_i40e_stats_strings[i].offset);
2548                 count++;
2549         }
2550
2551         /* Get individiual stats from i40e_hw_port struct */
2552         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2553                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2554                         rte_i40e_hw_port_strings[i].offset);
2555                 count++;
2556         }
2557
2558         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2559                 for (prio = 0; prio < 8; prio++) {
2560                         xstats[count].value =
2561                                 *(uint64_t *)(((char *)hw_stats) +
2562                                 rte_i40e_rxq_prio_strings[i].offset +
2563                                 (sizeof(uint64_t) * prio));
2564                         count++;
2565                 }
2566         }
2567
2568         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2569                 for (prio = 0; prio < 8; prio++) {
2570                         xstats[count].value =
2571                                 *(uint64_t *)(((char *)hw_stats) +
2572                                 rte_i40e_txq_prio_strings[i].offset +
2573                                 (sizeof(uint64_t) * prio));
2574                         count++;
2575                 }
2576         }
2577
2578         return count;
2579 }
2580
2581 static int
2582 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2583                                  __rte_unused uint16_t queue_id,
2584                                  __rte_unused uint8_t stat_idx,
2585                                  __rte_unused uint8_t is_rx)
2586 {
2587         PMD_INIT_FUNC_TRACE();
2588
2589         return -ENOSYS;
2590 }
2591
2592 static void
2593 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2594 {
2595         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2596         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2597         struct i40e_vsi *vsi = pf->main_vsi;
2598         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2599
2600         dev_info->max_rx_queues = vsi->nb_qps;
2601         dev_info->max_tx_queues = vsi->nb_qps;
2602         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2603         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2604         dev_info->max_mac_addrs = vsi->max_macaddrs;
2605         dev_info->max_vfs = pci_dev->max_vfs;
2606         dev_info->rx_offload_capa =
2607                 DEV_RX_OFFLOAD_VLAN_STRIP |
2608                 DEV_RX_OFFLOAD_QINQ_STRIP |
2609                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2610                 DEV_RX_OFFLOAD_UDP_CKSUM |
2611                 DEV_RX_OFFLOAD_TCP_CKSUM;
2612         dev_info->tx_offload_capa =
2613                 DEV_TX_OFFLOAD_VLAN_INSERT |
2614                 DEV_TX_OFFLOAD_QINQ_INSERT |
2615                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2616                 DEV_TX_OFFLOAD_UDP_CKSUM |
2617                 DEV_TX_OFFLOAD_TCP_CKSUM |
2618                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2619                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2620                 DEV_TX_OFFLOAD_TCP_TSO |
2621                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2622                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2623                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2624                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2625         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2626                                                 sizeof(uint32_t);
2627         dev_info->reta_size = pf->hash_lut_size;
2628         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2629
2630         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2631                 .rx_thresh = {
2632                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2633                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2634                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2635                 },
2636                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2637                 .rx_drop_en = 0,
2638         };
2639
2640         dev_info->default_txconf = (struct rte_eth_txconf) {
2641                 .tx_thresh = {
2642                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2643                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2644                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2645                 },
2646                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2647                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2648                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2649                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2650         };
2651
2652         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2653                 .nb_max = I40E_MAX_RING_DESC,
2654                 .nb_min = I40E_MIN_RING_DESC,
2655                 .nb_align = I40E_ALIGN_RING_DESC,
2656         };
2657
2658         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2659                 .nb_max = I40E_MAX_RING_DESC,
2660                 .nb_min = I40E_MIN_RING_DESC,
2661                 .nb_align = I40E_ALIGN_RING_DESC,
2662         };
2663
2664         if (pf->flags & I40E_FLAG_VMDQ) {
2665                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2666                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2667                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2668                                                 pf->max_nb_vmdq_vsi;
2669                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2670                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2671                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2672         }
2673
2674         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2675                 /* For XL710 */
2676                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2677         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2678                 /* For XXV710 */
2679                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2680         else
2681                 /* For X710 */
2682                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2683 }
2684
2685 static int
2686 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2687 {
2688         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2689         struct i40e_vsi *vsi = pf->main_vsi;
2690         PMD_INIT_FUNC_TRACE();
2691
2692         if (on)
2693                 return i40e_vsi_add_vlan(vsi, vlan_id);
2694         else
2695                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2696 }
2697
2698 static int
2699 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2700                    enum rte_vlan_type vlan_type,
2701                    uint16_t tpid)
2702 {
2703         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2704         uint64_t reg_r = 0, reg_w = 0;
2705         uint16_t reg_id = 0;
2706         int ret = 0;
2707         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2708
2709         switch (vlan_type) {
2710         case ETH_VLAN_TYPE_OUTER:
2711                 if (qinq)
2712                         reg_id = 2;
2713                 else
2714                         reg_id = 3;
2715                 break;
2716         case ETH_VLAN_TYPE_INNER:
2717                 if (qinq)
2718                         reg_id = 3;
2719                 else {
2720                         ret = -EINVAL;
2721                         PMD_DRV_LOG(ERR,
2722                                 "Unsupported vlan type in single vlan.\n");
2723                         return ret;
2724                 }
2725                 break;
2726         default:
2727                 ret = -EINVAL;
2728                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2729                 return ret;
2730         }
2731         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2732                                           &reg_r, NULL);
2733         if (ret != I40E_SUCCESS) {
2734                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2735                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2736                 ret = -EIO;
2737                 return ret;
2738         }
2739         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2740                     "0x%08"PRIx64"", reg_id, reg_r);
2741
2742         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2743         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2744         if (reg_r == reg_w) {
2745                 ret = 0;
2746                 PMD_DRV_LOG(DEBUG, "No need to write");
2747                 return ret;
2748         }
2749
2750         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2751                                            reg_w, NULL);
2752         if (ret != I40E_SUCCESS) {
2753                 ret = -EIO;
2754                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2755                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2756                 return ret;
2757         }
2758         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2759                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2760
2761         return ret;
2762 }
2763
2764 static void
2765 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2766 {
2767         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2768         struct i40e_vsi *vsi = pf->main_vsi;
2769
2770         if (mask & ETH_VLAN_FILTER_MASK) {
2771                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2772                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2773                 else
2774                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2775         }
2776
2777         if (mask & ETH_VLAN_STRIP_MASK) {
2778                 /* Enable or disable VLAN stripping */
2779                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2780                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2781                 else
2782                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2783         }
2784
2785         if (mask & ETH_VLAN_EXTEND_MASK) {
2786                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2787                         i40e_vsi_config_double_vlan(vsi, TRUE);
2788                         /* Set global registers with default ether type value */
2789                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2790                                            ETHER_TYPE_VLAN);
2791                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2792                                            ETHER_TYPE_VLAN);
2793                 }
2794                 else
2795                         i40e_vsi_config_double_vlan(vsi, FALSE);
2796         }
2797 }
2798
2799 static void
2800 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2801                           __rte_unused uint16_t queue,
2802                           __rte_unused int on)
2803 {
2804         PMD_INIT_FUNC_TRACE();
2805 }
2806
2807 static int
2808 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2809 {
2810         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2811         struct i40e_vsi *vsi = pf->main_vsi;
2812         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2813         struct i40e_vsi_vlan_pvid_info info;
2814
2815         memset(&info, 0, sizeof(info));
2816         info.on = on;
2817         if (info.on)
2818                 info.config.pvid = pvid;
2819         else {
2820                 info.config.reject.tagged =
2821                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2822                 info.config.reject.untagged =
2823                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2824         }
2825
2826         return i40e_vsi_vlan_pvid_set(vsi, &info);
2827 }
2828
2829 static int
2830 i40e_dev_led_on(struct rte_eth_dev *dev)
2831 {
2832         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2833         uint32_t mode = i40e_led_get(hw);
2834
2835         if (mode == 0)
2836                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2837
2838         return 0;
2839 }
2840
2841 static int
2842 i40e_dev_led_off(struct rte_eth_dev *dev)
2843 {
2844         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2845         uint32_t mode = i40e_led_get(hw);
2846
2847         if (mode != 0)
2848                 i40e_led_set(hw, 0, false);
2849
2850         return 0;
2851 }
2852
2853 static int
2854 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2855 {
2856         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2857         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2858
2859         fc_conf->pause_time = pf->fc_conf.pause_time;
2860         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2861         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2862
2863          /* Return current mode according to actual setting*/
2864         switch (hw->fc.current_mode) {
2865         case I40E_FC_FULL:
2866                 fc_conf->mode = RTE_FC_FULL;
2867                 break;
2868         case I40E_FC_TX_PAUSE:
2869                 fc_conf->mode = RTE_FC_TX_PAUSE;
2870                 break;
2871         case I40E_FC_RX_PAUSE:
2872                 fc_conf->mode = RTE_FC_RX_PAUSE;
2873                 break;
2874         case I40E_FC_NONE:
2875         default:
2876                 fc_conf->mode = RTE_FC_NONE;
2877         };
2878
2879         return 0;
2880 }
2881
2882 static int
2883 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2884 {
2885         uint32_t mflcn_reg, fctrl_reg, reg;
2886         uint32_t max_high_water;
2887         uint8_t i, aq_failure;
2888         int err;
2889         struct i40e_hw *hw;
2890         struct i40e_pf *pf;
2891         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2892                 [RTE_FC_NONE] = I40E_FC_NONE,
2893                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2894                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2895                 [RTE_FC_FULL] = I40E_FC_FULL
2896         };
2897
2898         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2899
2900         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2901         if ((fc_conf->high_water > max_high_water) ||
2902                         (fc_conf->high_water < fc_conf->low_water)) {
2903                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2904                         "High_water must <= %d.", max_high_water);
2905                 return -EINVAL;
2906         }
2907
2908         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2909         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2910         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2911
2912         pf->fc_conf.pause_time = fc_conf->pause_time;
2913         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2914         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2915
2916         PMD_INIT_FUNC_TRACE();
2917
2918         /* All the link flow control related enable/disable register
2919          * configuration is handle by the F/W
2920          */
2921         err = i40e_set_fc(hw, &aq_failure, true);
2922         if (err < 0)
2923                 return -ENOSYS;
2924
2925         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
2926                 /* Configure flow control refresh threshold,
2927                  * the value for stat_tx_pause_refresh_timer[8]
2928                  * is used for global pause operation.
2929                  */
2930
2931                 I40E_WRITE_REG(hw,
2932                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2933                                pf->fc_conf.pause_time);
2934
2935                 /* configure the timer value included in transmitted pause
2936                  * frame,
2937                  * the value for stat_tx_pause_quanta[8] is used for global
2938                  * pause operation
2939                  */
2940                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2941                                pf->fc_conf.pause_time);
2942
2943                 fctrl_reg = I40E_READ_REG(hw,
2944                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2945
2946                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2947                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2948                 else
2949                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2950
2951                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2952                                fctrl_reg);
2953         } else {
2954                 /* Configure pause time (2 TCs per register) */
2955                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2956                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2957                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2958
2959                 /* Configure flow control refresh threshold value */
2960                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2961                                pf->fc_conf.pause_time / 2);
2962
2963                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2964
2965                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2966                  *depending on configuration
2967                  */
2968                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2969                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2970                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2971                 } else {
2972                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2973                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2974                 }
2975
2976                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2977         }
2978
2979         /* config the water marker both based on the packets and bytes */
2980         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2981                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2982                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2983         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2984                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2985                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2986         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2987                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2988                        << I40E_KILOSHIFT);
2989         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2990                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2991                        << I40E_KILOSHIFT);
2992
2993         I40E_WRITE_FLUSH(hw);
2994
2995         return 0;
2996 }
2997
2998 static int
2999 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3000                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3001 {
3002         PMD_INIT_FUNC_TRACE();
3003
3004         return -ENOSYS;
3005 }
3006
3007 /* Add a MAC address, and update filters */
3008 static void
3009 i40e_macaddr_add(struct rte_eth_dev *dev,
3010                  struct ether_addr *mac_addr,
3011                  __rte_unused uint32_t index,
3012                  uint32_t pool)
3013 {
3014         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3015         struct i40e_mac_filter_info mac_filter;
3016         struct i40e_vsi *vsi;
3017         int ret;
3018
3019         /* If VMDQ not enabled or configured, return */
3020         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3021                           !pf->nb_cfg_vmdq_vsi)) {
3022                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3023                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3024                         pool);
3025                 return;
3026         }
3027
3028         if (pool > pf->nb_cfg_vmdq_vsi) {
3029                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3030                                 pool, pf->nb_cfg_vmdq_vsi);
3031                 return;
3032         }
3033
3034         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3035         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3036                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3037         else
3038                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3039
3040         if (pool == 0)
3041                 vsi = pf->main_vsi;
3042         else
3043                 vsi = pf->vmdq[pool - 1].vsi;
3044
3045         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3046         if (ret != I40E_SUCCESS) {
3047                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3048                 return;
3049         }
3050 }
3051
3052 /* Remove a MAC address, and update filters */
3053 static void
3054 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3055 {
3056         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3057         struct i40e_vsi *vsi;
3058         struct rte_eth_dev_data *data = dev->data;
3059         struct ether_addr *macaddr;
3060         int ret;
3061         uint32_t i;
3062         uint64_t pool_sel;
3063
3064         macaddr = &(data->mac_addrs[index]);
3065
3066         pool_sel = dev->data->mac_pool_sel[index];
3067
3068         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3069                 if (pool_sel & (1ULL << i)) {
3070                         if (i == 0)
3071                                 vsi = pf->main_vsi;
3072                         else {
3073                                 /* No VMDQ pool enabled or configured */
3074                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3075                                         (i > pf->nb_cfg_vmdq_vsi)) {
3076                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3077                                                         "/configured");
3078                                         return;
3079                                 }
3080                                 vsi = pf->vmdq[i - 1].vsi;
3081                         }
3082                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3083
3084                         if (ret) {
3085                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3086                                 return;
3087                         }
3088                 }
3089         }
3090 }
3091
3092 /* Set perfect match or hash match of MAC and VLAN for a VF */
3093 static int
3094 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3095                  struct rte_eth_mac_filter *filter,
3096                  bool add)
3097 {
3098         struct i40e_hw *hw;
3099         struct i40e_mac_filter_info mac_filter;
3100         struct ether_addr old_mac;
3101         struct ether_addr *new_mac;
3102         struct i40e_pf_vf *vf = NULL;
3103         uint16_t vf_id;
3104         int ret;
3105
3106         if (pf == NULL) {
3107                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3108                 return -EINVAL;
3109         }
3110         hw = I40E_PF_TO_HW(pf);
3111
3112         if (filter == NULL) {
3113                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3114                 return -EINVAL;
3115         }
3116
3117         new_mac = &filter->mac_addr;
3118
3119         if (is_zero_ether_addr(new_mac)) {
3120                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3121                 return -EINVAL;
3122         }
3123
3124         vf_id = filter->dst_id;
3125
3126         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3127                 PMD_DRV_LOG(ERR, "Invalid argument.");
3128                 return -EINVAL;
3129         }
3130         vf = &pf->vfs[vf_id];
3131
3132         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3133                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3134                 return -EINVAL;
3135         }
3136
3137         if (add) {
3138                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3139                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3140                                 ETHER_ADDR_LEN);
3141                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3142                                  ETHER_ADDR_LEN);
3143
3144                 mac_filter.filter_type = filter->filter_type;
3145                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3146                 if (ret != I40E_SUCCESS) {
3147                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3148                         return -1;
3149                 }
3150                 ether_addr_copy(new_mac, &pf->dev_addr);
3151         } else {
3152                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3153                                 ETHER_ADDR_LEN);
3154                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3155                 if (ret != I40E_SUCCESS) {
3156                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3157                         return -1;
3158                 }
3159
3160                 /* Clear device address as it has been removed */
3161                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3162                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3163         }
3164
3165         return 0;
3166 }
3167
3168 /* MAC filter handle */
3169 static int
3170 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3171                 void *arg)
3172 {
3173         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3174         struct rte_eth_mac_filter *filter;
3175         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3176         int ret = I40E_NOT_SUPPORTED;
3177
3178         filter = (struct rte_eth_mac_filter *)(arg);
3179
3180         switch (filter_op) {
3181         case RTE_ETH_FILTER_NOP:
3182                 ret = I40E_SUCCESS;
3183                 break;
3184         case RTE_ETH_FILTER_ADD:
3185                 i40e_pf_disable_irq0(hw);
3186                 if (filter->is_vf)
3187                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3188                 i40e_pf_enable_irq0(hw);
3189                 break;
3190         case RTE_ETH_FILTER_DELETE:
3191                 i40e_pf_disable_irq0(hw);
3192                 if (filter->is_vf)
3193                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3194                 i40e_pf_enable_irq0(hw);
3195                 break;
3196         default:
3197                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3198                 ret = I40E_ERR_PARAM;
3199                 break;
3200         }
3201
3202         return ret;
3203 }
3204
3205 static int
3206 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3207 {
3208         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3209         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3210         int ret;
3211
3212         if (!lut)
3213                 return -EINVAL;
3214
3215         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3216                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3217                                           lut, lut_size);
3218                 if (ret) {
3219                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3220                         return ret;
3221                 }
3222         } else {
3223                 uint32_t *lut_dw = (uint32_t *)lut;
3224                 uint16_t i, lut_size_dw = lut_size / 4;
3225
3226                 for (i = 0; i < lut_size_dw; i++)
3227                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3228         }
3229
3230         return 0;
3231 }
3232
3233 static int
3234 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3235 {
3236         struct i40e_pf *pf;
3237         struct i40e_hw *hw;
3238         int ret;
3239
3240         if (!vsi || !lut)
3241                 return -EINVAL;
3242
3243         pf = I40E_VSI_TO_PF(vsi);
3244         hw = I40E_VSI_TO_HW(vsi);
3245
3246         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3247                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3248                                           lut, lut_size);
3249                 if (ret) {
3250                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3251                         return ret;
3252                 }
3253         } else {
3254                 uint32_t *lut_dw = (uint32_t *)lut;
3255                 uint16_t i, lut_size_dw = lut_size / 4;
3256
3257                 for (i = 0; i < lut_size_dw; i++)
3258                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3259                 I40E_WRITE_FLUSH(hw);
3260         }
3261
3262         return 0;
3263 }
3264
3265 static int
3266 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3267                          struct rte_eth_rss_reta_entry64 *reta_conf,
3268                          uint16_t reta_size)
3269 {
3270         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3271         uint16_t i, lut_size = pf->hash_lut_size;
3272         uint16_t idx, shift;
3273         uint8_t *lut;
3274         int ret;
3275
3276         if (reta_size != lut_size ||
3277                 reta_size > ETH_RSS_RETA_SIZE_512) {
3278                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3279                         "(%d) doesn't match the number hardware can supported "
3280                                         "(%d)\n", reta_size, lut_size);
3281                 return -EINVAL;
3282         }
3283
3284         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3285         if (!lut) {
3286                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3287                 return -ENOMEM;
3288         }
3289         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3290         if (ret)
3291                 goto out;
3292         for (i = 0; i < reta_size; i++) {
3293                 idx = i / RTE_RETA_GROUP_SIZE;
3294                 shift = i % RTE_RETA_GROUP_SIZE;
3295                 if (reta_conf[idx].mask & (1ULL << shift))
3296                         lut[i] = reta_conf[idx].reta[shift];
3297         }
3298         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3299
3300 out:
3301         rte_free(lut);
3302
3303         return ret;
3304 }
3305
3306 static int
3307 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3308                         struct rte_eth_rss_reta_entry64 *reta_conf,
3309                         uint16_t reta_size)
3310 {
3311         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3312         uint16_t i, lut_size = pf->hash_lut_size;
3313         uint16_t idx, shift;
3314         uint8_t *lut;
3315         int ret;
3316
3317         if (reta_size != lut_size ||
3318                 reta_size > ETH_RSS_RETA_SIZE_512) {
3319                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3320                         "(%d) doesn't match the number hardware can supported "
3321                                         "(%d)\n", reta_size, lut_size);
3322                 return -EINVAL;
3323         }
3324
3325         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3326         if (!lut) {
3327                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3328                 return -ENOMEM;
3329         }
3330
3331         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3332         if (ret)
3333                 goto out;
3334         for (i = 0; i < reta_size; i++) {
3335                 idx = i / RTE_RETA_GROUP_SIZE;
3336                 shift = i % RTE_RETA_GROUP_SIZE;
3337                 if (reta_conf[idx].mask & (1ULL << shift))
3338                         reta_conf[idx].reta[shift] = lut[i];
3339         }
3340
3341 out:
3342         rte_free(lut);
3343
3344         return ret;
3345 }
3346
3347 /**
3348  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3349  * @hw:   pointer to the HW structure
3350  * @mem:  pointer to mem struct to fill out
3351  * @size: size of memory requested
3352  * @alignment: what to align the allocation to
3353  **/
3354 enum i40e_status_code
3355 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3356                         struct i40e_dma_mem *mem,
3357                         u64 size,
3358                         u32 alignment)
3359 {
3360         const struct rte_memzone *mz = NULL;
3361         char z_name[RTE_MEMZONE_NAMESIZE];
3362
3363         if (!mem)
3364                 return I40E_ERR_PARAM;
3365
3366         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3367         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3368                                          alignment, RTE_PGSIZE_2M);
3369         if (!mz)
3370                 return I40E_ERR_NO_MEMORY;
3371
3372         mem->size = size;
3373         mem->va = mz->addr;
3374         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3375         mem->zone = (const void *)mz;
3376         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3377                     "%"PRIu64, mz->name, mem->pa);
3378
3379         return I40E_SUCCESS;
3380 }
3381
3382 /**
3383  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3384  * @hw:   pointer to the HW structure
3385  * @mem:  ptr to mem struct to free
3386  **/
3387 enum i40e_status_code
3388 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3389                     struct i40e_dma_mem *mem)
3390 {
3391         if (!mem)
3392                 return I40E_ERR_PARAM;
3393
3394         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3395                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3396                     mem->pa);
3397         rte_memzone_free((const struct rte_memzone *)mem->zone);
3398         mem->zone = NULL;
3399         mem->va = NULL;
3400         mem->pa = (u64)0;
3401
3402         return I40E_SUCCESS;
3403 }
3404
3405 /**
3406  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3407  * @hw:   pointer to the HW structure
3408  * @mem:  pointer to mem struct to fill out
3409  * @size: size of memory requested
3410  **/
3411 enum i40e_status_code
3412 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3413                          struct i40e_virt_mem *mem,
3414                          u32 size)
3415 {
3416         if (!mem)
3417                 return I40E_ERR_PARAM;
3418
3419         mem->size = size;
3420         mem->va = rte_zmalloc("i40e", size, 0);
3421
3422         if (mem->va)
3423                 return I40E_SUCCESS;
3424         else
3425                 return I40E_ERR_NO_MEMORY;
3426 }
3427
3428 /**
3429  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3430  * @hw:   pointer to the HW structure
3431  * @mem:  pointer to mem struct to free
3432  **/
3433 enum i40e_status_code
3434 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3435                      struct i40e_virt_mem *mem)
3436 {
3437         if (!mem)
3438                 return I40E_ERR_PARAM;
3439
3440         rte_free(mem->va);
3441         mem->va = NULL;
3442
3443         return I40E_SUCCESS;
3444 }
3445
3446 void
3447 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3448 {
3449         rte_spinlock_init(&sp->spinlock);
3450 }
3451
3452 void
3453 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3454 {
3455         rte_spinlock_lock(&sp->spinlock);
3456 }
3457
3458 void
3459 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3460 {
3461         rte_spinlock_unlock(&sp->spinlock);
3462 }
3463
3464 void
3465 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3466 {
3467         return;
3468 }
3469
3470 /**
3471  * Get the hardware capabilities, which will be parsed
3472  * and saved into struct i40e_hw.
3473  */
3474 static int
3475 i40e_get_cap(struct i40e_hw *hw)
3476 {
3477         struct i40e_aqc_list_capabilities_element_resp *buf;
3478         uint16_t len, size = 0;
3479         int ret;
3480
3481         /* Calculate a huge enough buff for saving response data temporarily */
3482         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3483                                                 I40E_MAX_CAP_ELE_NUM;
3484         buf = rte_zmalloc("i40e", len, 0);
3485         if (!buf) {
3486                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3487                 return I40E_ERR_NO_MEMORY;
3488         }
3489
3490         /* Get, parse the capabilities and save it to hw */
3491         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3492                         i40e_aqc_opc_list_func_capabilities, NULL);
3493         if (ret != I40E_SUCCESS)
3494                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3495
3496         /* Free the temporary buffer after being used */
3497         rte_free(buf);
3498
3499         return ret;
3500 }
3501
3502 static int
3503 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3504 {
3505         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3506         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3507         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3508         uint16_t qp_count = 0, vsi_count = 0;
3509
3510         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3511                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3512                 return -EINVAL;
3513         }
3514         /* Add the parameter init for LFC */
3515         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3516         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3517         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3518
3519         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3520         pf->max_num_vsi = hw->func_caps.num_vsis;
3521         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3522         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3523         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3524
3525         /* FDir queue/VSI allocation */
3526         pf->fdir_qp_offset = 0;
3527         if (hw->func_caps.fd) {
3528                 pf->flags |= I40E_FLAG_FDIR;
3529                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3530         } else {
3531                 pf->fdir_nb_qps = 0;
3532         }
3533         qp_count += pf->fdir_nb_qps;
3534         vsi_count += 1;
3535
3536         /* LAN queue/VSI allocation */
3537         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3538         if (!hw->func_caps.rss) {
3539                 pf->lan_nb_qps = 1;
3540         } else {
3541                 pf->flags |= I40E_FLAG_RSS;
3542                 if (hw->mac.type == I40E_MAC_X722)
3543                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3544                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3545         }
3546         qp_count += pf->lan_nb_qps;
3547         vsi_count += 1;
3548
3549         /* VF queue/VSI allocation */
3550         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3551         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3552                 pf->flags |= I40E_FLAG_SRIOV;
3553                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3554                 pf->vf_num = pci_dev->max_vfs;
3555                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3556                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3557                             pf->vf_nb_qps * pf->vf_num);
3558         } else {
3559                 pf->vf_nb_qps = 0;
3560                 pf->vf_num = 0;
3561         }
3562         qp_count += pf->vf_nb_qps * pf->vf_num;
3563         vsi_count += pf->vf_num;
3564
3565         /* VMDq queue/VSI allocation */
3566         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3567         pf->vmdq_nb_qps = 0;
3568         pf->max_nb_vmdq_vsi = 0;
3569         if (hw->func_caps.vmdq) {
3570                 if (qp_count < hw->func_caps.num_tx_qp &&
3571                         vsi_count < hw->func_caps.num_vsis) {
3572                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3573                                 qp_count) / pf->vmdq_nb_qp_max;
3574
3575                         /* Limit the maximum number of VMDq vsi to the maximum
3576                          * ethdev can support
3577                          */
3578                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3579                                 hw->func_caps.num_vsis - vsi_count);
3580                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3581                                 ETH_64_POOLS);
3582                         if (pf->max_nb_vmdq_vsi) {
3583                                 pf->flags |= I40E_FLAG_VMDQ;
3584                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3585                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3586                                             "per VMDQ VSI, in total %u queues",
3587                                             pf->max_nb_vmdq_vsi,
3588                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3589                                             pf->max_nb_vmdq_vsi);
3590                         } else {
3591                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3592                                             "VMDq");
3593                         }
3594                 } else {
3595                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3596                 }
3597         }
3598         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3599         vsi_count += pf->max_nb_vmdq_vsi;
3600
3601         if (hw->func_caps.dcb)
3602                 pf->flags |= I40E_FLAG_DCB;
3603
3604         if (qp_count > hw->func_caps.num_tx_qp) {
3605                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3606                             "the hardware maximum %u", qp_count,
3607                             hw->func_caps.num_tx_qp);
3608                 return -EINVAL;
3609         }
3610         if (vsi_count > hw->func_caps.num_vsis) {
3611                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3612                             "the hardware maximum %u", vsi_count,
3613                             hw->func_caps.num_vsis);
3614                 return -EINVAL;
3615         }
3616
3617         return 0;
3618 }
3619
3620 static int
3621 i40e_pf_get_switch_config(struct i40e_pf *pf)
3622 {
3623         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3624         struct i40e_aqc_get_switch_config_resp *switch_config;
3625         struct i40e_aqc_switch_config_element_resp *element;
3626         uint16_t start_seid = 0, num_reported;
3627         int ret;
3628
3629         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3630                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3631         if (!switch_config) {
3632                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3633                 return -ENOMEM;
3634         }
3635
3636         /* Get the switch configurations */
3637         ret = i40e_aq_get_switch_config(hw, switch_config,
3638                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3639         if (ret != I40E_SUCCESS) {
3640                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3641                 goto fail;
3642         }
3643         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3644         if (num_reported != 1) { /* The number should be 1 */
3645                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3646                 goto fail;
3647         }
3648
3649         /* Parse the switch configuration elements */
3650         element = &(switch_config->element[0]);
3651         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3652                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3653                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3654         } else
3655                 PMD_DRV_LOG(INFO, "Unknown element type");
3656
3657 fail:
3658         rte_free(switch_config);
3659
3660         return ret;
3661 }
3662
3663 static int
3664 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3665                         uint32_t num)
3666 {
3667         struct pool_entry *entry;
3668
3669         if (pool == NULL || num == 0)
3670                 return -EINVAL;
3671
3672         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3673         if (entry == NULL) {
3674                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3675                 return -ENOMEM;
3676         }
3677
3678         /* queue heap initialize */
3679         pool->num_free = num;
3680         pool->num_alloc = 0;
3681         pool->base = base;
3682         LIST_INIT(&pool->alloc_list);
3683         LIST_INIT(&pool->free_list);
3684
3685         /* Initialize element  */
3686         entry->base = 0;
3687         entry->len = num;
3688
3689         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3690         return 0;
3691 }
3692
3693 static void
3694 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3695 {
3696         struct pool_entry *entry, *next_entry;
3697
3698         if (pool == NULL)
3699                 return;
3700
3701         for (entry = LIST_FIRST(&pool->alloc_list);
3702                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3703                         entry = next_entry) {
3704                 LIST_REMOVE(entry, next);
3705                 rte_free(entry);
3706         }
3707
3708         for (entry = LIST_FIRST(&pool->free_list);
3709                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3710                         entry = next_entry) {
3711                 LIST_REMOVE(entry, next);
3712                 rte_free(entry);
3713         }
3714
3715         pool->num_free = 0;
3716         pool->num_alloc = 0;
3717         pool->base = 0;
3718         LIST_INIT(&pool->alloc_list);
3719         LIST_INIT(&pool->free_list);
3720 }
3721
3722 static int
3723 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3724                        uint32_t base)
3725 {
3726         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3727         uint32_t pool_offset;
3728         int insert;
3729
3730         if (pool == NULL) {
3731                 PMD_DRV_LOG(ERR, "Invalid parameter");
3732                 return -EINVAL;
3733         }
3734
3735         pool_offset = base - pool->base;
3736         /* Lookup in alloc list */
3737         LIST_FOREACH(entry, &pool->alloc_list, next) {
3738                 if (entry->base == pool_offset) {
3739                         valid_entry = entry;
3740                         LIST_REMOVE(entry, next);
3741                         break;
3742                 }
3743         }
3744
3745         /* Not find, return */
3746         if (valid_entry == NULL) {
3747                 PMD_DRV_LOG(ERR, "Failed to find entry");
3748                 return -EINVAL;
3749         }
3750
3751         /**
3752          * Found it, move it to free list  and try to merge.
3753          * In order to make merge easier, always sort it by qbase.
3754          * Find adjacent prev and last entries.
3755          */
3756         prev = next = NULL;
3757         LIST_FOREACH(entry, &pool->free_list, next) {
3758                 if (entry->base > valid_entry->base) {
3759                         next = entry;
3760                         break;
3761                 }
3762                 prev = entry;
3763         }
3764
3765         insert = 0;
3766         /* Try to merge with next one*/
3767         if (next != NULL) {
3768                 /* Merge with next one */
3769                 if (valid_entry->base + valid_entry->len == next->base) {
3770                         next->base = valid_entry->base;
3771                         next->len += valid_entry->len;
3772                         rte_free(valid_entry);
3773                         valid_entry = next;
3774                         insert = 1;
3775                 }
3776         }
3777
3778         if (prev != NULL) {
3779                 /* Merge with previous one */
3780                 if (prev->base + prev->len == valid_entry->base) {
3781                         prev->len += valid_entry->len;
3782                         /* If it merge with next one, remove next node */
3783                         if (insert == 1) {
3784                                 LIST_REMOVE(valid_entry, next);
3785                                 rte_free(valid_entry);
3786                         } else {
3787                                 rte_free(valid_entry);
3788                                 insert = 1;
3789                         }
3790                 }
3791         }
3792
3793         /* Not find any entry to merge, insert */
3794         if (insert == 0) {
3795                 if (prev != NULL)
3796                         LIST_INSERT_AFTER(prev, valid_entry, next);
3797                 else if (next != NULL)
3798                         LIST_INSERT_BEFORE(next, valid_entry, next);
3799                 else /* It's empty list, insert to head */
3800                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3801         }
3802
3803         pool->num_free += valid_entry->len;
3804         pool->num_alloc -= valid_entry->len;
3805
3806         return 0;
3807 }
3808
3809 static int
3810 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3811                        uint16_t num)
3812 {
3813         struct pool_entry *entry, *valid_entry;
3814
3815         if (pool == NULL || num == 0) {
3816                 PMD_DRV_LOG(ERR, "Invalid parameter");
3817                 return -EINVAL;
3818         }
3819
3820         if (pool->num_free < num) {
3821                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3822                             num, pool->num_free);
3823                 return -ENOMEM;
3824         }
3825
3826         valid_entry = NULL;
3827         /* Lookup  in free list and find most fit one */
3828         LIST_FOREACH(entry, &pool->free_list, next) {
3829                 if (entry->len >= num) {
3830                         /* Find best one */
3831                         if (entry->len == num) {
3832                                 valid_entry = entry;
3833                                 break;
3834                         }
3835                         if (valid_entry == NULL || valid_entry->len > entry->len)
3836                                 valid_entry = entry;
3837                 }
3838         }
3839
3840         /* Not find one to satisfy the request, return */
3841         if (valid_entry == NULL) {
3842                 PMD_DRV_LOG(ERR, "No valid entry found");
3843                 return -ENOMEM;
3844         }
3845         /**
3846          * The entry have equal queue number as requested,
3847          * remove it from alloc_list.
3848          */
3849         if (valid_entry->len == num) {
3850                 LIST_REMOVE(valid_entry, next);
3851         } else {
3852                 /**
3853                  * The entry have more numbers than requested,
3854                  * create a new entry for alloc_list and minus its
3855                  * queue base and number in free_list.
3856                  */
3857                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3858                 if (entry == NULL) {
3859                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3860                                     "resource pool");
3861                         return -ENOMEM;
3862                 }
3863                 entry->base = valid_entry->base;
3864                 entry->len = num;
3865                 valid_entry->base += num;
3866                 valid_entry->len -= num;
3867                 valid_entry = entry;
3868         }
3869
3870         /* Insert it into alloc list, not sorted */
3871         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3872
3873         pool->num_free -= valid_entry->len;
3874         pool->num_alloc += valid_entry->len;
3875
3876         return valid_entry->base + pool->base;
3877 }
3878
3879 /**
3880  * bitmap_is_subset - Check whether src2 is subset of src1
3881  **/
3882 static inline int
3883 bitmap_is_subset(uint8_t src1, uint8_t src2)
3884 {
3885         return !((src1 ^ src2) & src2);
3886 }
3887
3888 static enum i40e_status_code
3889 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3890 {
3891         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3892
3893         /* If DCB is not supported, only default TC is supported */
3894         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3895                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3896                 return I40E_NOT_SUPPORTED;
3897         }
3898
3899         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3900                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3901                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3902                             enabled_tcmap);
3903                 return I40E_NOT_SUPPORTED;
3904         }
3905         return I40E_SUCCESS;
3906 }
3907
3908 int
3909 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3910                                 struct i40e_vsi_vlan_pvid_info *info)
3911 {
3912         struct i40e_hw *hw;
3913         struct i40e_vsi_context ctxt;
3914         uint8_t vlan_flags = 0;
3915         int ret;
3916
3917         if (vsi == NULL || info == NULL) {
3918                 PMD_DRV_LOG(ERR, "invalid parameters");
3919                 return I40E_ERR_PARAM;
3920         }
3921
3922         if (info->on) {
3923                 vsi->info.pvid = info->config.pvid;
3924                 /**
3925                  * If insert pvid is enabled, only tagged pkts are
3926                  * allowed to be sent out.
3927                  */
3928                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3929                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3930         } else {
3931                 vsi->info.pvid = 0;
3932                 if (info->config.reject.tagged == 0)
3933                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3934
3935                 if (info->config.reject.untagged == 0)
3936                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3937         }
3938         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3939                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3940         vsi->info.port_vlan_flags |= vlan_flags;
3941         vsi->info.valid_sections =
3942                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3943         memset(&ctxt, 0, sizeof(ctxt));
3944         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3945         ctxt.seid = vsi->seid;
3946
3947         hw = I40E_VSI_TO_HW(vsi);
3948         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3949         if (ret != I40E_SUCCESS)
3950                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3951
3952         return ret;
3953 }
3954
3955 static int
3956 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3957 {
3958         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3959         int i, ret;
3960         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3961
3962         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3963         if (ret != I40E_SUCCESS)
3964                 return ret;
3965
3966         if (!vsi->seid) {
3967                 PMD_DRV_LOG(ERR, "seid not valid");
3968                 return -EINVAL;
3969         }
3970
3971         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3972         tc_bw_data.tc_valid_bits = enabled_tcmap;
3973         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3974                 tc_bw_data.tc_bw_credits[i] =
3975                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3976
3977         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3978         if (ret != I40E_SUCCESS) {
3979                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3980                 return ret;
3981         }
3982
3983         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3984                                         sizeof(vsi->info.qs_handle));
3985         return I40E_SUCCESS;
3986 }
3987
3988 static enum i40e_status_code
3989 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3990                                  struct i40e_aqc_vsi_properties_data *info,
3991                                  uint8_t enabled_tcmap)
3992 {
3993         enum i40e_status_code ret;
3994         int i, total_tc = 0;
3995         uint16_t qpnum_per_tc, bsf, qp_idx;
3996
3997         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3998         if (ret != I40E_SUCCESS)
3999                 return ret;
4000
4001         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4002                 if (enabled_tcmap & (1 << i))
4003                         total_tc++;
4004         vsi->enabled_tc = enabled_tcmap;
4005
4006         /* Number of queues per enabled TC */
4007         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4008         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4009         bsf = rte_bsf32(qpnum_per_tc);
4010
4011         /* Adjust the queue number to actual queues that can be applied */
4012         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4013                 vsi->nb_qps = qpnum_per_tc * total_tc;
4014
4015         /**
4016          * Configure TC and queue mapping parameters, for enabled TC,
4017          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4018          * default queue will serve it.
4019          */
4020         qp_idx = 0;
4021         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4022                 if (vsi->enabled_tc & (1 << i)) {
4023                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4024                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4025                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4026                         qp_idx += qpnum_per_tc;
4027                 } else
4028                         info->tc_mapping[i] = 0;
4029         }
4030
4031         /* Associate queue number with VSI */
4032         if (vsi->type == I40E_VSI_SRIOV) {
4033                 info->mapping_flags |=
4034                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4035                 for (i = 0; i < vsi->nb_qps; i++)
4036                         info->queue_mapping[i] =
4037                                 rte_cpu_to_le_16(vsi->base_queue + i);
4038         } else {
4039                 info->mapping_flags |=
4040                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4041                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4042         }
4043         info->valid_sections |=
4044                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4045
4046         return I40E_SUCCESS;
4047 }
4048
4049 static int
4050 i40e_veb_release(struct i40e_veb *veb)
4051 {
4052         struct i40e_vsi *vsi;
4053         struct i40e_hw *hw;
4054
4055         if (veb == NULL)
4056                 return -EINVAL;
4057
4058         if (!TAILQ_EMPTY(&veb->head)) {
4059                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4060                 return -EACCES;
4061         }
4062         /* associate_vsi field is NULL for floating VEB */
4063         if (veb->associate_vsi != NULL) {
4064                 vsi = veb->associate_vsi;
4065                 hw = I40E_VSI_TO_HW(vsi);
4066
4067                 vsi->uplink_seid = veb->uplink_seid;
4068                 vsi->veb = NULL;
4069         } else {
4070                 veb->associate_pf->main_vsi->floating_veb = NULL;
4071                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4072         }
4073
4074         i40e_aq_delete_element(hw, veb->seid, NULL);
4075         rte_free(veb);
4076         return I40E_SUCCESS;
4077 }
4078
4079 /* Setup a veb */
4080 static struct i40e_veb *
4081 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4082 {
4083         struct i40e_veb *veb;
4084         int ret;
4085         struct i40e_hw *hw;
4086
4087         if (pf == NULL) {
4088                 PMD_DRV_LOG(ERR,
4089                             "veb setup failed, associated PF shouldn't null");
4090                 return NULL;
4091         }
4092         hw = I40E_PF_TO_HW(pf);
4093
4094         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4095         if (!veb) {
4096                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4097                 goto fail;
4098         }
4099
4100         veb->associate_vsi = vsi;
4101         veb->associate_pf = pf;
4102         TAILQ_INIT(&veb->head);
4103         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4104
4105         /* create floating veb if vsi is NULL */
4106         if (vsi != NULL) {
4107                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4108                                       I40E_DEFAULT_TCMAP, false,
4109                                       &veb->seid, false, NULL);
4110         } else {
4111                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4112                                       true, &veb->seid, false, NULL);
4113         }
4114
4115         if (ret != I40E_SUCCESS) {
4116                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4117                             hw->aq.asq_last_status);
4118                 goto fail;
4119         }
4120
4121         /* get statistics index */
4122         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4123                                 &veb->stats_idx, NULL, NULL, NULL);
4124         if (ret != I40E_SUCCESS) {
4125                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4126                             hw->aq.asq_last_status);
4127                 goto fail;
4128         }
4129         /* Get VEB bandwidth, to be implemented */
4130         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4131         if (vsi)
4132                 vsi->uplink_seid = veb->seid;
4133
4134         return veb;
4135 fail:
4136         rte_free(veb);
4137         return NULL;
4138 }
4139
4140 int
4141 i40e_vsi_release(struct i40e_vsi *vsi)
4142 {
4143         struct i40e_pf *pf;
4144         struct i40e_hw *hw;
4145         struct i40e_vsi_list *vsi_list;
4146         void *temp;
4147         int ret;
4148         struct i40e_mac_filter *f;
4149         uint16_t user_param;
4150
4151         if (!vsi)
4152                 return I40E_SUCCESS;
4153
4154         user_param = vsi->user_param;
4155
4156         pf = I40E_VSI_TO_PF(vsi);
4157         hw = I40E_VSI_TO_HW(vsi);
4158
4159         /* VSI has child to attach, release child first */
4160         if (vsi->veb) {
4161                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4162                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4163                                 return -1;
4164                 }
4165                 i40e_veb_release(vsi->veb);
4166         }
4167
4168         if (vsi->floating_veb) {
4169                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4170                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4171                                 return -1;
4172                 }
4173         }
4174
4175         /* Remove all macvlan filters of the VSI */
4176         i40e_vsi_remove_all_macvlan_filter(vsi);
4177         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4178                 rte_free(f);
4179
4180         if (vsi->type != I40E_VSI_MAIN &&
4181             ((vsi->type != I40E_VSI_SRIOV) ||
4182             !pf->floating_veb_list[user_param])) {
4183                 /* Remove vsi from parent's sibling list */
4184                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4185                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4186                         return I40E_ERR_PARAM;
4187                 }
4188                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4189                                 &vsi->sib_vsi_list, list);
4190
4191                 /* Remove all switch element of the VSI */
4192                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4193                 if (ret != I40E_SUCCESS)
4194                         PMD_DRV_LOG(ERR, "Failed to delete element");
4195         }
4196
4197         if ((vsi->type == I40E_VSI_SRIOV) &&
4198             pf->floating_veb_list[user_param]) {
4199                 /* Remove vsi from parent's sibling list */
4200                 if (vsi->parent_vsi == NULL ||
4201                     vsi->parent_vsi->floating_veb == NULL) {
4202                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4203                         return I40E_ERR_PARAM;
4204                 }
4205                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4206                              &vsi->sib_vsi_list, list);
4207
4208                 /* Remove all switch element of the VSI */
4209                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4210                 if (ret != I40E_SUCCESS)
4211                         PMD_DRV_LOG(ERR, "Failed to delete element");
4212         }
4213
4214         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4215
4216         if (vsi->type != I40E_VSI_SRIOV)
4217                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4218         rte_free(vsi);
4219
4220         return I40E_SUCCESS;
4221 }
4222
4223 static int
4224 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4225 {
4226         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4227         struct i40e_aqc_remove_macvlan_element_data def_filter;
4228         struct i40e_mac_filter_info filter;
4229         int ret;
4230
4231         if (vsi->type != I40E_VSI_MAIN)
4232                 return I40E_ERR_CONFIG;
4233         memset(&def_filter, 0, sizeof(def_filter));
4234         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4235                                         ETH_ADDR_LEN);
4236         def_filter.vlan_tag = 0;
4237         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4238                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4239         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4240         if (ret != I40E_SUCCESS) {
4241                 struct i40e_mac_filter *f;
4242                 struct ether_addr *mac;
4243
4244                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4245                             "macvlan filter");
4246                 /* It needs to add the permanent mac into mac list */
4247                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4248                 if (f == NULL) {
4249                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4250                         return I40E_ERR_NO_MEMORY;
4251                 }
4252                 mac = &f->mac_info.mac_addr;
4253                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4254                                 ETH_ADDR_LEN);
4255                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4256                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4257                 vsi->mac_num++;
4258
4259                 return ret;
4260         }
4261         (void)rte_memcpy(&filter.mac_addr,
4262                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4263         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4264         return i40e_vsi_add_mac(vsi, &filter);
4265 }
4266
4267 /*
4268  * i40e_vsi_get_bw_config - Query VSI BW Information
4269  * @vsi: the VSI to be queried
4270  *
4271  * Returns 0 on success, negative value on failure
4272  */
4273 static enum i40e_status_code
4274 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4275 {
4276         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4277         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4278         struct i40e_hw *hw = &vsi->adapter->hw;
4279         i40e_status ret;
4280         int i;
4281         uint32_t bw_max;
4282
4283         memset(&bw_config, 0, sizeof(bw_config));
4284         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4285         if (ret != I40E_SUCCESS) {
4286                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4287                             hw->aq.asq_last_status);
4288                 return ret;
4289         }
4290
4291         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4292         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4293                                         &ets_sla_config, NULL);
4294         if (ret != I40E_SUCCESS) {
4295                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4296                             "configuration %u", hw->aq.asq_last_status);
4297                 return ret;
4298         }
4299
4300         /* store and print out BW info */
4301         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4302         vsi->bw_info.bw_max = bw_config.max_bw;
4303         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4304         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4305         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4306                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4307                      I40E_16_BIT_WIDTH);
4308         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4309                 vsi->bw_info.bw_ets_share_credits[i] =
4310                                 ets_sla_config.share_credits[i];
4311                 vsi->bw_info.bw_ets_credits[i] =
4312                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4313                 /* 4 bits per TC, 4th bit is reserved */
4314                 vsi->bw_info.bw_ets_max[i] =
4315                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4316                                   RTE_LEN2MASK(3, uint8_t));
4317                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4318                             vsi->bw_info.bw_ets_share_credits[i]);
4319                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4320                             vsi->bw_info.bw_ets_credits[i]);
4321                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4322                             vsi->bw_info.bw_ets_max[i]);
4323         }
4324
4325         return I40E_SUCCESS;
4326 }
4327
4328 /* i40e_enable_pf_lb
4329  * @pf: pointer to the pf structure
4330  *
4331  * allow loopback on pf
4332  */
4333 static inline void
4334 i40e_enable_pf_lb(struct i40e_pf *pf)
4335 {
4336         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4337         struct i40e_vsi_context ctxt;
4338         int ret;
4339
4340         /* Use the FW API if FW >= v5.0 */
4341         if (hw->aq.fw_maj_ver < 5) {
4342                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4343                 return;
4344         }
4345
4346         memset(&ctxt, 0, sizeof(ctxt));
4347         ctxt.seid = pf->main_vsi_seid;
4348         ctxt.pf_num = hw->pf_id;
4349         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4350         if (ret) {
4351                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4352                             ret, hw->aq.asq_last_status);
4353                 return;
4354         }
4355         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4356         ctxt.info.valid_sections =
4357                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4358         ctxt.info.switch_id |=
4359                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4360
4361         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4362         if (ret)
4363                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4364                             hw->aq.asq_last_status);
4365 }
4366
4367 /* Setup a VSI */
4368 struct i40e_vsi *
4369 i40e_vsi_setup(struct i40e_pf *pf,
4370                enum i40e_vsi_type type,
4371                struct i40e_vsi *uplink_vsi,
4372                uint16_t user_param)
4373 {
4374         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4375         struct i40e_vsi *vsi;
4376         struct i40e_mac_filter_info filter;
4377         int ret;
4378         struct i40e_vsi_context ctxt;
4379         struct ether_addr broadcast =
4380                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4381
4382         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4383             uplink_vsi == NULL) {
4384                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4385                             "VSI link shouldn't be NULL");
4386                 return NULL;
4387         }
4388
4389         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4390                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4391                             "uplink VSI should be NULL");
4392                 return NULL;
4393         }
4394
4395         /* two situations
4396          * 1.type is not MAIN and uplink vsi is not NULL
4397          * If uplink vsi didn't setup VEB, create one first under veb field
4398          * 2.type is SRIOV and the uplink is NULL
4399          * If floating VEB is NULL, create one veb under floating veb field
4400          */
4401
4402         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4403             uplink_vsi->veb == NULL) {
4404                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4405
4406                 if (uplink_vsi->veb == NULL) {
4407                         PMD_DRV_LOG(ERR, "VEB setup failed");
4408                         return NULL;
4409                 }
4410                 /* set ALLOWLOOPBACk on pf, when veb is created */
4411                 i40e_enable_pf_lb(pf);
4412         }
4413
4414         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4415             pf->main_vsi->floating_veb == NULL) {
4416                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4417
4418                 if (pf->main_vsi->floating_veb == NULL) {
4419                         PMD_DRV_LOG(ERR, "VEB setup failed");
4420                         return NULL;
4421                 }
4422         }
4423
4424         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4425         if (!vsi) {
4426                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4427                 return NULL;
4428         }
4429         TAILQ_INIT(&vsi->mac_list);
4430         vsi->type = type;
4431         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4432         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4433         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4434         vsi->user_param = user_param;
4435         /* Allocate queues */
4436         switch (vsi->type) {
4437         case I40E_VSI_MAIN  :
4438                 vsi->nb_qps = pf->lan_nb_qps;
4439                 break;
4440         case I40E_VSI_SRIOV :
4441                 vsi->nb_qps = pf->vf_nb_qps;
4442                 break;
4443         case I40E_VSI_VMDQ2:
4444                 vsi->nb_qps = pf->vmdq_nb_qps;
4445                 break;
4446         case I40E_VSI_FDIR:
4447                 vsi->nb_qps = pf->fdir_nb_qps;
4448                 break;
4449         default:
4450                 goto fail_mem;
4451         }
4452         /*
4453          * The filter status descriptor is reported in rx queue 0,
4454          * while the tx queue for fdir filter programming has no
4455          * such constraints, can be non-zero queues.
4456          * To simplify it, choose FDIR vsi use queue 0 pair.
4457          * To make sure it will use queue 0 pair, queue allocation
4458          * need be done before this function is called
4459          */
4460         if (type != I40E_VSI_FDIR) {
4461                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4462                         if (ret < 0) {
4463                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4464                                                 vsi->seid, ret);
4465                                 goto fail_mem;
4466                         }
4467                         vsi->base_queue = ret;
4468         } else
4469                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4470
4471         /* VF has MSIX interrupt in VF range, don't allocate here */
4472         if (type == I40E_VSI_MAIN) {
4473                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4474                                           RTE_MIN(vsi->nb_qps,
4475                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4476                 if (ret < 0) {
4477                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4478                                     vsi->seid, ret);
4479                         goto fail_queue_alloc;
4480                 }
4481                 vsi->msix_intr = ret;
4482                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4483         } else if (type != I40E_VSI_SRIOV) {
4484                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4485                 if (ret < 0) {
4486                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4487                         goto fail_queue_alloc;
4488                 }
4489                 vsi->msix_intr = ret;
4490                 vsi->nb_msix = 1;
4491         } else {
4492                 vsi->msix_intr = 0;
4493                 vsi->nb_msix = 0;
4494         }
4495
4496         /* Add VSI */
4497         if (type == I40E_VSI_MAIN) {
4498                 /* For main VSI, no need to add since it's default one */
4499                 vsi->uplink_seid = pf->mac_seid;
4500                 vsi->seid = pf->main_vsi_seid;
4501                 /* Bind queues with specific MSIX interrupt */
4502                 /**
4503                  * Needs 2 interrupt at least, one for misc cause which will
4504                  * enabled from OS side, Another for queues binding the
4505                  * interrupt from device side only.
4506                  */
4507
4508                 /* Get default VSI parameters from hardware */
4509                 memset(&ctxt, 0, sizeof(ctxt));
4510                 ctxt.seid = vsi->seid;
4511                 ctxt.pf_num = hw->pf_id;
4512                 ctxt.uplink_seid = vsi->uplink_seid;
4513                 ctxt.vf_num = 0;
4514                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4515                 if (ret != I40E_SUCCESS) {
4516                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4517                         goto fail_msix_alloc;
4518                 }
4519                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4520                         sizeof(struct i40e_aqc_vsi_properties_data));
4521                 vsi->vsi_id = ctxt.vsi_number;
4522                 vsi->info.valid_sections = 0;
4523
4524                 /* Configure tc, enabled TC0 only */
4525                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4526                         I40E_SUCCESS) {
4527                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4528                         goto fail_msix_alloc;
4529                 }
4530
4531                 /* TC, queue mapping */
4532                 memset(&ctxt, 0, sizeof(ctxt));
4533                 vsi->info.valid_sections |=
4534                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4535                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4536                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4537                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4538                         sizeof(struct i40e_aqc_vsi_properties_data));
4539                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4540                                                 I40E_DEFAULT_TCMAP);
4541                 if (ret != I40E_SUCCESS) {
4542                         PMD_DRV_LOG(ERR, "Failed to configure "
4543                                     "TC queue mapping");
4544                         goto fail_msix_alloc;
4545                 }
4546                 ctxt.seid = vsi->seid;
4547                 ctxt.pf_num = hw->pf_id;
4548                 ctxt.uplink_seid = vsi->uplink_seid;
4549                 ctxt.vf_num = 0;
4550
4551                 /* Update VSI parameters */
4552                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4553                 if (ret != I40E_SUCCESS) {
4554                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4555                         goto fail_msix_alloc;
4556                 }
4557
4558                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4559                                                 sizeof(vsi->info.tc_mapping));
4560                 (void)rte_memcpy(&vsi->info.queue_mapping,
4561                                 &ctxt.info.queue_mapping,
4562                         sizeof(vsi->info.queue_mapping));
4563                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4564                 vsi->info.valid_sections = 0;
4565
4566                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4567                                 ETH_ADDR_LEN);
4568
4569                 /**
4570                  * Updating default filter settings are necessary to prevent
4571                  * reception of tagged packets.
4572                  * Some old firmware configurations load a default macvlan
4573                  * filter which accepts both tagged and untagged packets.
4574                  * The updating is to use a normal filter instead if needed.
4575                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4576                  * The firmware with correct configurations load the default
4577                  * macvlan filter which is expected and cannot be removed.
4578                  */
4579                 i40e_update_default_filter_setting(vsi);
4580                 i40e_config_qinq(hw, vsi);
4581         } else if (type == I40E_VSI_SRIOV) {
4582                 memset(&ctxt, 0, sizeof(ctxt));
4583                 /**
4584                  * For other VSI, the uplink_seid equals to uplink VSI's
4585                  * uplink_seid since they share same VEB
4586                  */
4587                 if (uplink_vsi == NULL)
4588                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4589                 else
4590                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4591                 ctxt.pf_num = hw->pf_id;
4592                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4593                 ctxt.uplink_seid = vsi->uplink_seid;
4594                 ctxt.connection_type = 0x1;
4595                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4596
4597                 /* Use the VEB configuration if FW >= v5.0 */
4598                 if (hw->aq.fw_maj_ver >= 5) {
4599                         /* Configure switch ID */
4600                         ctxt.info.valid_sections |=
4601                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4602                         ctxt.info.switch_id =
4603                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4604                 }
4605
4606                 /* Configure port/vlan */
4607                 ctxt.info.valid_sections |=
4608                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4609                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4610                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4611                                                 I40E_DEFAULT_TCMAP);
4612                 if (ret != I40E_SUCCESS) {
4613                         PMD_DRV_LOG(ERR, "Failed to configure "
4614                                     "TC queue mapping");
4615                         goto fail_msix_alloc;
4616                 }
4617                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4618                 ctxt.info.valid_sections |=
4619                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4620                 /**
4621                  * Since VSI is not created yet, only configure parameter,
4622                  * will add vsi below.
4623                  */
4624
4625                 i40e_config_qinq(hw, vsi);
4626         } else if (type == I40E_VSI_VMDQ2) {
4627                 memset(&ctxt, 0, sizeof(ctxt));
4628                 /*
4629                  * For other VSI, the uplink_seid equals to uplink VSI's
4630                  * uplink_seid since they share same VEB
4631                  */
4632                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4633                 ctxt.pf_num = hw->pf_id;
4634                 ctxt.vf_num = 0;
4635                 ctxt.uplink_seid = vsi->uplink_seid;
4636                 ctxt.connection_type = 0x1;
4637                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4638
4639                 ctxt.info.valid_sections |=
4640                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4641                 /* user_param carries flag to enable loop back */
4642                 if (user_param) {
4643                         ctxt.info.switch_id =
4644                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4645                         ctxt.info.switch_id |=
4646                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4647                 }
4648
4649                 /* Configure port/vlan */
4650                 ctxt.info.valid_sections |=
4651                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4652                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4653                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4654                                                 I40E_DEFAULT_TCMAP);
4655                 if (ret != I40E_SUCCESS) {
4656                         PMD_DRV_LOG(ERR, "Failed to configure "
4657                                         "TC queue mapping");
4658                         goto fail_msix_alloc;
4659                 }
4660                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4661                 ctxt.info.valid_sections |=
4662                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4663         } else if (type == I40E_VSI_FDIR) {
4664                 memset(&ctxt, 0, sizeof(ctxt));
4665                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4666                 ctxt.pf_num = hw->pf_id;
4667                 ctxt.vf_num = 0;
4668                 ctxt.uplink_seid = vsi->uplink_seid;
4669                 ctxt.connection_type = 0x1;     /* regular data port */
4670                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4671                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4672                                                 I40E_DEFAULT_TCMAP);
4673                 if (ret != I40E_SUCCESS) {
4674                         PMD_DRV_LOG(ERR, "Failed to configure "
4675                                         "TC queue mapping.");
4676                         goto fail_msix_alloc;
4677                 }
4678                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4679                 ctxt.info.valid_sections |=
4680                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4681         } else {
4682                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4683                 goto fail_msix_alloc;
4684         }
4685
4686         if (vsi->type != I40E_VSI_MAIN) {
4687                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4688                 if (ret != I40E_SUCCESS) {
4689                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4690                                     hw->aq.asq_last_status);
4691                         goto fail_msix_alloc;
4692                 }
4693                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4694                 vsi->info.valid_sections = 0;
4695                 vsi->seid = ctxt.seid;
4696                 vsi->vsi_id = ctxt.vsi_number;
4697                 vsi->sib_vsi_list.vsi = vsi;
4698                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4699                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4700                                           &vsi->sib_vsi_list, list);
4701                 } else {
4702                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4703                                           &vsi->sib_vsi_list, list);
4704                 }
4705         }
4706
4707         /* MAC/VLAN configuration */
4708         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4709         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4710
4711         ret = i40e_vsi_add_mac(vsi, &filter);
4712         if (ret != I40E_SUCCESS) {
4713                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4714                 goto fail_msix_alloc;
4715         }
4716
4717         /* Get VSI BW information */
4718         i40e_vsi_get_bw_config(vsi);
4719         return vsi;
4720 fail_msix_alloc:
4721         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4722 fail_queue_alloc:
4723         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4724 fail_mem:
4725         rte_free(vsi);
4726         return NULL;
4727 }
4728
4729 /* Configure vlan filter on or off */
4730 int
4731 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4732 {
4733         int i, num;
4734         struct i40e_mac_filter *f;
4735         void *temp;
4736         struct i40e_mac_filter_info *mac_filter;
4737         enum rte_mac_filter_type desired_filter;
4738         int ret = I40E_SUCCESS;
4739
4740         if (on) {
4741                 /* Filter to match MAC and VLAN */
4742                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4743         } else {
4744                 /* Filter to match only MAC */
4745                 desired_filter = RTE_MAC_PERFECT_MATCH;
4746         }
4747
4748         num = vsi->mac_num;
4749
4750         mac_filter = rte_zmalloc("mac_filter_info_data",
4751                                  num * sizeof(*mac_filter), 0);
4752         if (mac_filter == NULL) {
4753                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4754                 return I40E_ERR_NO_MEMORY;
4755         }
4756
4757         i = 0;
4758
4759         /* Remove all existing mac */
4760         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4761                 mac_filter[i] = f->mac_info;
4762                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4763                 if (ret) {
4764                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4765                                     on ? "enable" : "disable");
4766                         goto DONE;
4767                 }
4768                 i++;
4769         }
4770
4771         /* Override with new filter */
4772         for (i = 0; i < num; i++) {
4773                 mac_filter[i].filter_type = desired_filter;
4774                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4775                 if (ret) {
4776                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4777                                     on ? "enable" : "disable");
4778                         goto DONE;
4779                 }
4780         }
4781
4782 DONE:
4783         rte_free(mac_filter);
4784         return ret;
4785 }
4786
4787 /* Configure vlan stripping on or off */
4788 int
4789 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4790 {
4791         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4792         struct i40e_vsi_context ctxt;
4793         uint8_t vlan_flags;
4794         int ret = I40E_SUCCESS;
4795
4796         /* Check if it has been already on or off */
4797         if (vsi->info.valid_sections &
4798                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4799                 if (on) {
4800                         if ((vsi->info.port_vlan_flags &
4801                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4802                                 return 0; /* already on */
4803                 } else {
4804                         if ((vsi->info.port_vlan_flags &
4805                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4806                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4807                                 return 0; /* already off */
4808                 }
4809         }
4810
4811         if (on)
4812                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4813         else
4814                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4815         vsi->info.valid_sections =
4816                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4817         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4818         vsi->info.port_vlan_flags |= vlan_flags;
4819         ctxt.seid = vsi->seid;
4820         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4821         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4822         if (ret)
4823                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4824                             on ? "enable" : "disable");
4825
4826         return ret;
4827 }
4828
4829 static int
4830 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4831 {
4832         struct rte_eth_dev_data *data = dev->data;
4833         int ret;
4834         int mask = 0;
4835
4836         /* Apply vlan offload setting */
4837         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4838         i40e_vlan_offload_set(dev, mask);
4839
4840         /* Apply double-vlan setting, not implemented yet */
4841
4842         /* Apply pvid setting */
4843         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4844                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4845         if (ret)
4846                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4847
4848         return ret;
4849 }
4850
4851 static int
4852 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4853 {
4854         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4855
4856         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4857 }
4858
4859 static int
4860 i40e_update_flow_control(struct i40e_hw *hw)
4861 {
4862 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4863         struct i40e_link_status link_status;
4864         uint32_t rxfc = 0, txfc = 0, reg;
4865         uint8_t an_info;
4866         int ret;
4867
4868         memset(&link_status, 0, sizeof(link_status));
4869         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4870         if (ret != I40E_SUCCESS) {
4871                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4872                 goto write_reg; /* Disable flow control */
4873         }
4874
4875         an_info = hw->phy.link_info.an_info;
4876         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4877                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4878                 ret = I40E_ERR_NOT_READY;
4879                 goto write_reg; /* Disable flow control */
4880         }
4881         /**
4882          * If link auto negotiation is enabled, flow control needs to
4883          * be configured according to it
4884          */
4885         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4886         case I40E_LINK_PAUSE_RXTX:
4887                 rxfc = 1;
4888                 txfc = 1;
4889                 hw->fc.current_mode = I40E_FC_FULL;
4890                 break;
4891         case I40E_AQ_LINK_PAUSE_RX:
4892                 rxfc = 1;
4893                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4894                 break;
4895         case I40E_AQ_LINK_PAUSE_TX:
4896                 txfc = 1;
4897                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4898                 break;
4899         default:
4900                 hw->fc.current_mode = I40E_FC_NONE;
4901                 break;
4902         }
4903
4904 write_reg:
4905         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4906                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4907         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4908         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4909         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4910         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4911
4912         return ret;
4913 }
4914
4915 /* PF setup */
4916 static int
4917 i40e_pf_setup(struct i40e_pf *pf)
4918 {
4919         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4920         struct i40e_filter_control_settings settings;
4921         struct i40e_vsi *vsi;
4922         int ret;
4923
4924         /* Clear all stats counters */
4925         pf->offset_loaded = FALSE;
4926         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4927         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4928
4929         ret = i40e_pf_get_switch_config(pf);
4930         if (ret != I40E_SUCCESS) {
4931                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4932                 return ret;
4933         }
4934         if (pf->flags & I40E_FLAG_FDIR) {
4935                 /* make queue allocated first, let FDIR use queue pair 0*/
4936                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4937                 if (ret != I40E_FDIR_QUEUE_ID) {
4938                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4939                                     " ret =%d", ret);
4940                         pf->flags &= ~I40E_FLAG_FDIR;
4941                 }
4942         }
4943         /*  main VSI setup */
4944         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4945         if (!vsi) {
4946                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4947                 return I40E_ERR_NOT_READY;
4948         }
4949         pf->main_vsi = vsi;
4950
4951         /* Configure filter control */
4952         memset(&settings, 0, sizeof(settings));
4953         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4954                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4955         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4956                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4957         else {
4958                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4959                                                 hw->func_caps.rss_table_size);
4960                 return I40E_ERR_PARAM;
4961         }
4962         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4963                         "size: %u\n", hw->func_caps.rss_table_size);
4964         pf->hash_lut_size = hw->func_caps.rss_table_size;
4965
4966         /* Enable ethtype and macvlan filters */
4967         settings.enable_ethtype = TRUE;
4968         settings.enable_macvlan = TRUE;
4969         ret = i40e_set_filter_control(hw, &settings);
4970         if (ret)
4971                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4972                                                                 ret);
4973
4974         /* Update flow control according to the auto negotiation */
4975         i40e_update_flow_control(hw);
4976
4977         return I40E_SUCCESS;
4978 }
4979
4980 int
4981 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4982 {
4983         uint32_t reg;
4984         uint16_t j;
4985
4986         /**
4987          * Set or clear TX Queue Disable flags,
4988          * which is required by hardware.
4989          */
4990         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4991         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4992
4993         /* Wait until the request is finished */
4994         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4995                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4996                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4997                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4998                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4999                                                         & 0x1))) {
5000                         break;
5001                 }
5002         }
5003         if (on) {
5004                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5005                         return I40E_SUCCESS; /* already on, skip next steps */
5006
5007                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5008                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5009         } else {
5010                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5011                         return I40E_SUCCESS; /* already off, skip next steps */
5012                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5013         }
5014         /* Write the register */
5015         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5016         /* Check the result */
5017         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5018                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5019                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5020                 if (on) {
5021                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5022                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5023                                 break;
5024                 } else {
5025                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5026                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5027                                 break;
5028                 }
5029         }
5030         /* Check if it is timeout */
5031         if (j >= I40E_CHK_Q_ENA_COUNT) {
5032                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5033                             (on ? "enable" : "disable"), q_idx);
5034                 return I40E_ERR_TIMEOUT;
5035         }
5036
5037         return I40E_SUCCESS;
5038 }
5039
5040 /* Swith on or off the tx queues */
5041 static int
5042 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5043 {
5044         struct rte_eth_dev_data *dev_data = pf->dev_data;
5045         struct i40e_tx_queue *txq;
5046         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5047         uint16_t i;
5048         int ret;
5049
5050         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5051                 txq = dev_data->tx_queues[i];
5052                 /* Don't operate the queue if not configured or
5053                  * if starting only per queue */
5054                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5055                         continue;
5056                 if (on)
5057                         ret = i40e_dev_tx_queue_start(dev, i);
5058                 else
5059                         ret = i40e_dev_tx_queue_stop(dev, i);
5060                 if ( ret != I40E_SUCCESS)
5061                         return ret;
5062         }
5063
5064         return I40E_SUCCESS;
5065 }
5066
5067 int
5068 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5069 {
5070         uint32_t reg;
5071         uint16_t j;
5072
5073         /* Wait until the request is finished */
5074         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5075                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5076                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5077                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5078                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5079                         break;
5080         }
5081
5082         if (on) {
5083                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5084                         return I40E_SUCCESS; /* Already on, skip next steps */
5085                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5086         } else {
5087                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5088                         return I40E_SUCCESS; /* Already off, skip next steps */
5089                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5090         }
5091
5092         /* Write the register */
5093         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5094         /* Check the result */
5095         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5096                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5097                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5098                 if (on) {
5099                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5100                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5101                                 break;
5102                 } else {
5103                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5104                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5105                                 break;
5106                 }
5107         }
5108
5109         /* Check if it is timeout */
5110         if (j >= I40E_CHK_Q_ENA_COUNT) {
5111                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5112                             (on ? "enable" : "disable"), q_idx);
5113                 return I40E_ERR_TIMEOUT;
5114         }
5115
5116         return I40E_SUCCESS;
5117 }
5118 /* Switch on or off the rx queues */
5119 static int
5120 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5121 {
5122         struct rte_eth_dev_data *dev_data = pf->dev_data;
5123         struct i40e_rx_queue *rxq;
5124         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5125         uint16_t i;
5126         int ret;
5127
5128         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5129                 rxq = dev_data->rx_queues[i];
5130                 /* Don't operate the queue if not configured or
5131                  * if starting only per queue */
5132                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5133                         continue;
5134                 if (on)
5135                         ret = i40e_dev_rx_queue_start(dev, i);
5136                 else
5137                         ret = i40e_dev_rx_queue_stop(dev, i);
5138                 if (ret != I40E_SUCCESS)
5139                         return ret;
5140         }
5141
5142         return I40E_SUCCESS;
5143 }
5144
5145 /* Switch on or off all the rx/tx queues */
5146 int
5147 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5148 {
5149         int ret;
5150
5151         if (on) {
5152                 /* enable rx queues before enabling tx queues */
5153                 ret = i40e_dev_switch_rx_queues(pf, on);
5154                 if (ret) {
5155                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5156                         return ret;
5157                 }
5158                 ret = i40e_dev_switch_tx_queues(pf, on);
5159         } else {
5160                 /* Stop tx queues before stopping rx queues */
5161                 ret = i40e_dev_switch_tx_queues(pf, on);
5162                 if (ret) {
5163                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5164                         return ret;
5165                 }
5166                 ret = i40e_dev_switch_rx_queues(pf, on);
5167         }
5168
5169         return ret;
5170 }
5171
5172 /* Initialize VSI for TX */
5173 static int
5174 i40e_dev_tx_init(struct i40e_pf *pf)
5175 {
5176         struct rte_eth_dev_data *data = pf->dev_data;
5177         uint16_t i;
5178         uint32_t ret = I40E_SUCCESS;
5179         struct i40e_tx_queue *txq;
5180
5181         for (i = 0; i < data->nb_tx_queues; i++) {
5182                 txq = data->tx_queues[i];
5183                 if (!txq || !txq->q_set)
5184                         continue;
5185                 ret = i40e_tx_queue_init(txq);
5186                 if (ret != I40E_SUCCESS)
5187                         break;
5188         }
5189         if (ret == I40E_SUCCESS)
5190                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5191                                      ->eth_dev);
5192
5193         return ret;
5194 }
5195
5196 /* Initialize VSI for RX */
5197 static int
5198 i40e_dev_rx_init(struct i40e_pf *pf)
5199 {
5200         struct rte_eth_dev_data *data = pf->dev_data;
5201         int ret = I40E_SUCCESS;
5202         uint16_t i;
5203         struct i40e_rx_queue *rxq;
5204
5205         i40e_pf_config_mq_rx(pf);
5206         for (i = 0; i < data->nb_rx_queues; i++) {
5207                 rxq = data->rx_queues[i];
5208                 if (!rxq || !rxq->q_set)
5209                         continue;
5210
5211                 ret = i40e_rx_queue_init(rxq);
5212                 if (ret != I40E_SUCCESS) {
5213                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5214                                     "initialization");
5215                         break;
5216                 }
5217         }
5218         if (ret == I40E_SUCCESS)
5219                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5220                                      ->eth_dev);
5221
5222         return ret;
5223 }
5224
5225 static int
5226 i40e_dev_rxtx_init(struct i40e_pf *pf)
5227 {
5228         int err;
5229
5230         err = i40e_dev_tx_init(pf);
5231         if (err) {
5232                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5233                 return err;
5234         }
5235         err = i40e_dev_rx_init(pf);
5236         if (err) {
5237                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5238                 return err;
5239         }
5240
5241         return err;
5242 }
5243
5244 static int
5245 i40e_vmdq_setup(struct rte_eth_dev *dev)
5246 {
5247         struct rte_eth_conf *conf = &dev->data->dev_conf;
5248         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5249         int i, err, conf_vsis, j, loop;
5250         struct i40e_vsi *vsi;
5251         struct i40e_vmdq_info *vmdq_info;
5252         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5253         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5254
5255         /*
5256          * Disable interrupt to avoid message from VF. Furthermore, it will
5257          * avoid race condition in VSI creation/destroy.
5258          */
5259         i40e_pf_disable_irq0(hw);
5260
5261         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5262                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5263                 return -ENOTSUP;
5264         }
5265
5266         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5267         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5268                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5269                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5270                         pf->max_nb_vmdq_vsi);
5271                 return -ENOTSUP;
5272         }
5273
5274         if (pf->vmdq != NULL) {
5275                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5276                 return 0;
5277         }
5278
5279         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5280                                 sizeof(*vmdq_info) * conf_vsis, 0);
5281
5282         if (pf->vmdq == NULL) {
5283                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5284                 return -ENOMEM;
5285         }
5286
5287         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5288
5289         /* Create VMDQ VSI */
5290         for (i = 0; i < conf_vsis; i++) {
5291                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5292                                 vmdq_conf->enable_loop_back);
5293                 if (vsi == NULL) {
5294                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5295                         err = -1;
5296                         goto err_vsi_setup;
5297                 }
5298                 vmdq_info = &pf->vmdq[i];
5299                 vmdq_info->pf = pf;
5300                 vmdq_info->vsi = vsi;
5301         }
5302         pf->nb_cfg_vmdq_vsi = conf_vsis;
5303
5304         /* Configure Vlan */
5305         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5306         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5307                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5308                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5309                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5310                                         vmdq_conf->pool_map[i].vlan_id, j);
5311
5312                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5313                                                 vmdq_conf->pool_map[i].vlan_id);
5314                                 if (err) {
5315                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5316                                         err = -1;
5317                                         goto err_vsi_setup;
5318                                 }
5319                         }
5320                 }
5321         }
5322
5323         i40e_pf_enable_irq0(hw);
5324
5325         return 0;
5326
5327 err_vsi_setup:
5328         for (i = 0; i < conf_vsis; i++)
5329                 if (pf->vmdq[i].vsi == NULL)
5330                         break;
5331                 else
5332                         i40e_vsi_release(pf->vmdq[i].vsi);
5333
5334         rte_free(pf->vmdq);
5335         pf->vmdq = NULL;
5336         i40e_pf_enable_irq0(hw);
5337         return err;
5338 }
5339
5340 static void
5341 i40e_stat_update_32(struct i40e_hw *hw,
5342                    uint32_t reg,
5343                    bool offset_loaded,
5344                    uint64_t *offset,
5345                    uint64_t *stat)
5346 {
5347         uint64_t new_data;
5348
5349         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5350         if (!offset_loaded)
5351                 *offset = new_data;
5352
5353         if (new_data >= *offset)
5354                 *stat = (uint64_t)(new_data - *offset);
5355         else
5356                 *stat = (uint64_t)((new_data +
5357                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5358 }
5359
5360 static void
5361 i40e_stat_update_48(struct i40e_hw *hw,
5362                    uint32_t hireg,
5363                    uint32_t loreg,
5364                    bool offset_loaded,
5365                    uint64_t *offset,
5366                    uint64_t *stat)
5367 {
5368         uint64_t new_data;
5369
5370         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5371         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5372                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5373
5374         if (!offset_loaded)
5375                 *offset = new_data;
5376
5377         if (new_data >= *offset)
5378                 *stat = new_data - *offset;
5379         else
5380                 *stat = (uint64_t)((new_data +
5381                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5382
5383         *stat &= I40E_48_BIT_MASK;
5384 }
5385
5386 /* Disable IRQ0 */
5387 void
5388 i40e_pf_disable_irq0(struct i40e_hw *hw)
5389 {
5390         /* Disable all interrupt types */
5391         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5392         I40E_WRITE_FLUSH(hw);
5393 }
5394
5395 /* Enable IRQ0 */
5396 void
5397 i40e_pf_enable_irq0(struct i40e_hw *hw)
5398 {
5399         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5400                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5401                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5402                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5403         I40E_WRITE_FLUSH(hw);
5404 }
5405
5406 static void
5407 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5408 {
5409         /* read pending request and disable first */
5410         i40e_pf_disable_irq0(hw);
5411         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5412         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5413                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5414
5415         if (no_queue)
5416                 /* Link no queues with irq0 */
5417                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5418                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5419 }
5420
5421 static void
5422 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5423 {
5424         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5425         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5426         int i;
5427         uint16_t abs_vf_id;
5428         uint32_t index, offset, val;
5429
5430         if (!pf->vfs)
5431                 return;
5432         /**
5433          * Try to find which VF trigger a reset, use absolute VF id to access
5434          * since the reg is global register.
5435          */
5436         for (i = 0; i < pf->vf_num; i++) {
5437                 abs_vf_id = hw->func_caps.vf_base_id + i;
5438                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5439                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5440                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5441                 /* VFR event occured */
5442                 if (val & (0x1 << offset)) {
5443                         int ret;
5444
5445                         /* Clear the event first */
5446                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5447                                                         (0x1 << offset));
5448                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5449                         /**
5450                          * Only notify a VF reset event occured,
5451                          * don't trigger another SW reset
5452                          */
5453                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5454                         if (ret != I40E_SUCCESS)
5455                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5456                 }
5457         }
5458 }
5459
5460 static void
5461 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5462 {
5463         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5464         struct i40e_virtchnl_pf_event event;
5465         int i;
5466
5467         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5468         event.event_data.link_event.link_status =
5469                 dev->data->dev_link.link_status;
5470         event.event_data.link_event.link_speed =
5471                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5472
5473         for (i = 0; i < pf->vf_num; i++)
5474                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5475                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5476 }
5477
5478 static void
5479 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5480 {
5481         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5482         struct i40e_arq_event_info info;
5483         uint16_t pending, opcode;
5484         int ret;
5485
5486         info.buf_len = I40E_AQ_BUF_SZ;
5487         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5488         if (!info.msg_buf) {
5489                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5490                 return;
5491         }
5492
5493         pending = 1;
5494         while (pending) {
5495                 ret = i40e_clean_arq_element(hw, &info, &pending);
5496
5497                 if (ret != I40E_SUCCESS) {
5498                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5499                                     "aq_err: %u", hw->aq.asq_last_status);
5500                         break;
5501                 }
5502                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5503
5504                 switch (opcode) {
5505                 case i40e_aqc_opc_send_msg_to_pf:
5506                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5507                         i40e_pf_host_handle_vf_msg(dev,
5508                                         rte_le_to_cpu_16(info.desc.retval),
5509                                         rte_le_to_cpu_32(info.desc.cookie_high),
5510                                         rte_le_to_cpu_32(info.desc.cookie_low),
5511                                         info.msg_buf,
5512                                         info.msg_len);
5513                         break;
5514                 case i40e_aqc_opc_get_link_status:
5515                         ret = i40e_dev_link_update(dev, 0);
5516                         if (!ret) {
5517                                 i40e_notify_all_vfs_link_status(dev);
5518                                 _rte_eth_dev_callback_process(dev,
5519                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5520                         }
5521                         break;
5522                 default:
5523                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5524                                     opcode);
5525                         break;
5526                 }
5527         }
5528         rte_free(info.msg_buf);
5529 }
5530
5531 /**
5532  * Interrupt handler triggered by NIC  for handling
5533  * specific interrupt.
5534  *
5535  * @param handle
5536  *  Pointer to interrupt handle.
5537  * @param param
5538  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5539  *
5540  * @return
5541  *  void
5542  */
5543 static void
5544 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5545                            void *param)
5546 {
5547         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5548         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5549         uint32_t icr0;
5550
5551         /* Disable interrupt */
5552         i40e_pf_disable_irq0(hw);
5553
5554         /* read out interrupt causes */
5555         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5556
5557         /* No interrupt event indicated */
5558         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5559                 PMD_DRV_LOG(INFO, "No interrupt event");
5560                 goto done;
5561         }
5562 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5563         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5564                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5565         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5566                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5567         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5568                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5569         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5570                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5571         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5572                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5573         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5574                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5575         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5576                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5577 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5578
5579         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5580                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5581                 i40e_dev_handle_vfr_event(dev);
5582         }
5583         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5584                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5585                 i40e_dev_handle_aq_msg(dev);
5586         }
5587
5588 done:
5589         /* Enable interrupt */
5590         i40e_pf_enable_irq0(hw);
5591         rte_intr_enable(intr_handle);
5592 }
5593
5594 static int
5595 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5596                          struct i40e_macvlan_filter *filter,
5597                          int total)
5598 {
5599         int ele_num, ele_buff_size;
5600         int num, actual_num, i;
5601         uint16_t flags;
5602         int ret = I40E_SUCCESS;
5603         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5604         struct i40e_aqc_add_macvlan_element_data *req_list;
5605
5606         if (filter == NULL  || total == 0)
5607                 return I40E_ERR_PARAM;
5608         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5609         ele_buff_size = hw->aq.asq_buf_size;
5610
5611         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5612         if (req_list == NULL) {
5613                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5614                 return I40E_ERR_NO_MEMORY;
5615         }
5616
5617         num = 0;
5618         do {
5619                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5620                 memset(req_list, 0, ele_buff_size);
5621
5622                 for (i = 0; i < actual_num; i++) {
5623                         (void)rte_memcpy(req_list[i].mac_addr,
5624                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5625                         req_list[i].vlan_tag =
5626                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5627
5628                         switch (filter[num + i].filter_type) {
5629                         case RTE_MAC_PERFECT_MATCH:
5630                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5631                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5632                                 break;
5633                         case RTE_MACVLAN_PERFECT_MATCH:
5634                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5635                                 break;
5636                         case RTE_MAC_HASH_MATCH:
5637                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5638                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5639                                 break;
5640                         case RTE_MACVLAN_HASH_MATCH:
5641                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5642                                 break;
5643                         default:
5644                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5645                                 ret = I40E_ERR_PARAM;
5646                                 goto DONE;
5647                         }
5648
5649                         req_list[i].queue_number = 0;
5650
5651                         req_list[i].flags = rte_cpu_to_le_16(flags);
5652                 }
5653
5654                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5655                                                 actual_num, NULL);
5656                 if (ret != I40E_SUCCESS) {
5657                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5658                         goto DONE;
5659                 }
5660                 num += actual_num;
5661         } while (num < total);
5662
5663 DONE:
5664         rte_free(req_list);
5665         return ret;
5666 }
5667
5668 static int
5669 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5670                             struct i40e_macvlan_filter *filter,
5671                             int total)
5672 {
5673         int ele_num, ele_buff_size;
5674         int num, actual_num, i;
5675         uint16_t flags;
5676         int ret = I40E_SUCCESS;
5677         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5678         struct i40e_aqc_remove_macvlan_element_data *req_list;
5679
5680         if (filter == NULL  || total == 0)
5681                 return I40E_ERR_PARAM;
5682
5683         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5684         ele_buff_size = hw->aq.asq_buf_size;
5685
5686         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5687         if (req_list == NULL) {
5688                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5689                 return I40E_ERR_NO_MEMORY;
5690         }
5691
5692         num = 0;
5693         do {
5694                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5695                 memset(req_list, 0, ele_buff_size);
5696
5697                 for (i = 0; i < actual_num; i++) {
5698                         (void)rte_memcpy(req_list[i].mac_addr,
5699                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5700                         req_list[i].vlan_tag =
5701                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5702
5703                         switch (filter[num + i].filter_type) {
5704                         case RTE_MAC_PERFECT_MATCH:
5705                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5706                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5707                                 break;
5708                         case RTE_MACVLAN_PERFECT_MATCH:
5709                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5710                                 break;
5711                         case RTE_MAC_HASH_MATCH:
5712                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5713                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5714                                 break;
5715                         case RTE_MACVLAN_HASH_MATCH:
5716                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5717                                 break;
5718                         default:
5719                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5720                                 ret = I40E_ERR_PARAM;
5721                                 goto DONE;
5722                         }
5723                         req_list[i].flags = rte_cpu_to_le_16(flags);
5724                 }
5725
5726                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5727                                                 actual_num, NULL);
5728                 if (ret != I40E_SUCCESS) {
5729                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5730                         goto DONE;
5731                 }
5732                 num += actual_num;
5733         } while (num < total);
5734
5735 DONE:
5736         rte_free(req_list);
5737         return ret;
5738 }
5739
5740 /* Find out specific MAC filter */
5741 static struct i40e_mac_filter *
5742 i40e_find_mac_filter(struct i40e_vsi *vsi,
5743                          struct ether_addr *macaddr)
5744 {
5745         struct i40e_mac_filter *f;
5746
5747         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5748                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5749                         return f;
5750         }
5751
5752         return NULL;
5753 }
5754
5755 static bool
5756 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5757                          uint16_t vlan_id)
5758 {
5759         uint32_t vid_idx, vid_bit;
5760
5761         if (vlan_id > ETH_VLAN_ID_MAX)
5762                 return 0;
5763
5764         vid_idx = I40E_VFTA_IDX(vlan_id);
5765         vid_bit = I40E_VFTA_BIT(vlan_id);
5766
5767         if (vsi->vfta[vid_idx] & vid_bit)
5768                 return 1;
5769         else
5770                 return 0;
5771 }
5772
5773 static void
5774 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5775                          uint16_t vlan_id, bool on)
5776 {
5777         uint32_t vid_idx, vid_bit;
5778
5779         if (vlan_id > ETH_VLAN_ID_MAX)
5780                 return;
5781
5782         vid_idx = I40E_VFTA_IDX(vlan_id);
5783         vid_bit = I40E_VFTA_BIT(vlan_id);
5784
5785         if (on)
5786                 vsi->vfta[vid_idx] |= vid_bit;
5787         else
5788                 vsi->vfta[vid_idx] &= ~vid_bit;
5789 }
5790
5791 /**
5792  * Find all vlan options for specific mac addr,
5793  * return with actual vlan found.
5794  */
5795 static inline int
5796 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5797                            struct i40e_macvlan_filter *mv_f,
5798                            int num, struct ether_addr *addr)
5799 {
5800         int i;
5801         uint32_t j, k;
5802
5803         /**
5804          * Not to use i40e_find_vlan_filter to decrease the loop time,
5805          * although the code looks complex.
5806           */
5807         if (num < vsi->vlan_num)
5808                 return I40E_ERR_PARAM;
5809
5810         i = 0;
5811         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5812                 if (vsi->vfta[j]) {
5813                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5814                                 if (vsi->vfta[j] & (1 << k)) {
5815                                         if (i > num - 1) {
5816                                                 PMD_DRV_LOG(ERR, "vlan number "
5817                                                             "not match");
5818                                                 return I40E_ERR_PARAM;
5819                                         }
5820                                         (void)rte_memcpy(&mv_f[i].macaddr,
5821                                                         addr, ETH_ADDR_LEN);
5822                                         mv_f[i].vlan_id =
5823                                                 j * I40E_UINT32_BIT_SIZE + k;
5824                                         i++;
5825                                 }
5826                         }
5827                 }
5828         }
5829         return I40E_SUCCESS;
5830 }
5831
5832 static inline int
5833 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5834                            struct i40e_macvlan_filter *mv_f,
5835                            int num,
5836                            uint16_t vlan)
5837 {
5838         int i = 0;
5839         struct i40e_mac_filter *f;
5840
5841         if (num < vsi->mac_num)
5842                 return I40E_ERR_PARAM;
5843
5844         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5845                 if (i > num - 1) {
5846                         PMD_DRV_LOG(ERR, "buffer number not match");
5847                         return I40E_ERR_PARAM;
5848                 }
5849                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5850                                 ETH_ADDR_LEN);
5851                 mv_f[i].vlan_id = vlan;
5852                 mv_f[i].filter_type = f->mac_info.filter_type;
5853                 i++;
5854         }
5855
5856         return I40E_SUCCESS;
5857 }
5858
5859 static int
5860 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5861 {
5862         int i, num;
5863         struct i40e_mac_filter *f;
5864         struct i40e_macvlan_filter *mv_f;
5865         int ret = I40E_SUCCESS;
5866
5867         if (vsi == NULL || vsi->mac_num == 0)
5868                 return I40E_ERR_PARAM;
5869
5870         /* Case that no vlan is set */
5871         if (vsi->vlan_num == 0)
5872                 num = vsi->mac_num;
5873         else
5874                 num = vsi->mac_num * vsi->vlan_num;
5875
5876         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5877         if (mv_f == NULL) {
5878                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5879                 return I40E_ERR_NO_MEMORY;
5880         }
5881
5882         i = 0;
5883         if (vsi->vlan_num == 0) {
5884                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5885                         (void)rte_memcpy(&mv_f[i].macaddr,
5886                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5887                         mv_f[i].vlan_id = 0;
5888                         i++;
5889                 }
5890         } else {
5891                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5892                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5893                                         vsi->vlan_num, &f->mac_info.mac_addr);
5894                         if (ret != I40E_SUCCESS)
5895                                 goto DONE;
5896                         i += vsi->vlan_num;
5897                 }
5898         }
5899
5900         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5901 DONE:
5902         rte_free(mv_f);
5903
5904         return ret;
5905 }
5906
5907 int
5908 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5909 {
5910         struct i40e_macvlan_filter *mv_f;
5911         int mac_num;
5912         int ret = I40E_SUCCESS;
5913
5914         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5915                 return I40E_ERR_PARAM;
5916
5917         /* If it's already set, just return */
5918         if (i40e_find_vlan_filter(vsi,vlan))
5919                 return I40E_SUCCESS;
5920
5921         mac_num = vsi->mac_num;
5922
5923         if (mac_num == 0) {
5924                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5925                 return I40E_ERR_PARAM;
5926         }
5927
5928         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5929
5930         if (mv_f == NULL) {
5931                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5932                 return I40E_ERR_NO_MEMORY;
5933         }
5934
5935         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5936
5937         if (ret != I40E_SUCCESS)
5938                 goto DONE;
5939
5940         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5941
5942         if (ret != I40E_SUCCESS)
5943                 goto DONE;
5944
5945         i40e_set_vlan_filter(vsi, vlan, 1);
5946
5947         vsi->vlan_num++;
5948         ret = I40E_SUCCESS;
5949 DONE:
5950         rte_free(mv_f);
5951         return ret;
5952 }
5953
5954 int
5955 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5956 {
5957         struct i40e_macvlan_filter *mv_f;
5958         int mac_num;
5959         int ret = I40E_SUCCESS;
5960
5961         /**
5962          * Vlan 0 is the generic filter for untagged packets
5963          * and can't be removed.
5964          */
5965         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5966                 return I40E_ERR_PARAM;
5967
5968         /* If can't find it, just return */
5969         if (!i40e_find_vlan_filter(vsi, vlan))
5970                 return I40E_ERR_PARAM;
5971
5972         mac_num = vsi->mac_num;
5973
5974         if (mac_num == 0) {
5975                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5976                 return I40E_ERR_PARAM;
5977         }
5978
5979         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5980
5981         if (mv_f == NULL) {
5982                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5983                 return I40E_ERR_NO_MEMORY;
5984         }
5985
5986         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5987
5988         if (ret != I40E_SUCCESS)
5989                 goto DONE;
5990
5991         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5992
5993         if (ret != I40E_SUCCESS)
5994                 goto DONE;
5995
5996         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5997         if (vsi->vlan_num == 1) {
5998                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5999                 if (ret != I40E_SUCCESS)
6000                         goto DONE;
6001
6002                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6003                 if (ret != I40E_SUCCESS)
6004                         goto DONE;
6005         }
6006
6007         i40e_set_vlan_filter(vsi, vlan, 0);
6008
6009         vsi->vlan_num--;
6010         ret = I40E_SUCCESS;
6011 DONE:
6012         rte_free(mv_f);
6013         return ret;
6014 }
6015
6016 int
6017 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6018 {
6019         struct i40e_mac_filter *f;
6020         struct i40e_macvlan_filter *mv_f;
6021         int i, vlan_num = 0;
6022         int ret = I40E_SUCCESS;
6023
6024         /* If it's add and we've config it, return */
6025         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6026         if (f != NULL)
6027                 return I40E_SUCCESS;
6028         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6029                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6030
6031                 /**
6032                  * If vlan_num is 0, that's the first time to add mac,
6033                  * set mask for vlan_id 0.
6034                  */
6035                 if (vsi->vlan_num == 0) {
6036                         i40e_set_vlan_filter(vsi, 0, 1);
6037                         vsi->vlan_num = 1;
6038                 }
6039                 vlan_num = vsi->vlan_num;
6040         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6041                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6042                 vlan_num = 1;
6043
6044         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6045         if (mv_f == NULL) {
6046                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6047                 return I40E_ERR_NO_MEMORY;
6048         }
6049
6050         for (i = 0; i < vlan_num; i++) {
6051                 mv_f[i].filter_type = mac_filter->filter_type;
6052                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6053                                 ETH_ADDR_LEN);
6054         }
6055
6056         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6057                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6058                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6059                                         &mac_filter->mac_addr);
6060                 if (ret != I40E_SUCCESS)
6061                         goto DONE;
6062         }
6063
6064         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6065         if (ret != I40E_SUCCESS)
6066                 goto DONE;
6067
6068         /* Add the mac addr into mac list */
6069         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6070         if (f == NULL) {
6071                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6072                 ret = I40E_ERR_NO_MEMORY;
6073                 goto DONE;
6074         }
6075         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6076                         ETH_ADDR_LEN);
6077         f->mac_info.filter_type = mac_filter->filter_type;
6078         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6079         vsi->mac_num++;
6080
6081         ret = I40E_SUCCESS;
6082 DONE:
6083         rte_free(mv_f);
6084
6085         return ret;
6086 }
6087
6088 int
6089 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6090 {
6091         struct i40e_mac_filter *f;
6092         struct i40e_macvlan_filter *mv_f;
6093         int i, vlan_num;
6094         enum rte_mac_filter_type filter_type;
6095         int ret = I40E_SUCCESS;
6096
6097         /* Can't find it, return an error */
6098         f = i40e_find_mac_filter(vsi, addr);
6099         if (f == NULL)
6100                 return I40E_ERR_PARAM;
6101
6102         vlan_num = vsi->vlan_num;
6103         filter_type = f->mac_info.filter_type;
6104         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6105                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6106                 if (vlan_num == 0) {
6107                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6108                         return I40E_ERR_PARAM;
6109                 }
6110         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6111                         filter_type == RTE_MAC_HASH_MATCH)
6112                 vlan_num = 1;
6113
6114         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6115         if (mv_f == NULL) {
6116                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6117                 return I40E_ERR_NO_MEMORY;
6118         }
6119
6120         for (i = 0; i < vlan_num; i++) {
6121                 mv_f[i].filter_type = filter_type;
6122                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6123                                 ETH_ADDR_LEN);
6124         }
6125         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6126                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6127                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6128                 if (ret != I40E_SUCCESS)
6129                         goto DONE;
6130         }
6131
6132         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6133         if (ret != I40E_SUCCESS)
6134                 goto DONE;
6135
6136         /* Remove the mac addr into mac list */
6137         TAILQ_REMOVE(&vsi->mac_list, f, next);
6138         rte_free(f);
6139         vsi->mac_num--;
6140
6141         ret = I40E_SUCCESS;
6142 DONE:
6143         rte_free(mv_f);
6144         return ret;
6145 }
6146
6147 /* Configure hash enable flags for RSS */
6148 uint64_t
6149 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6150 {
6151         uint64_t hena = 0;
6152
6153         if (!flags)
6154                 return hena;
6155
6156         if (flags & ETH_RSS_FRAG_IPV4)
6157                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6158         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6159                 if (type == I40E_MAC_X722) {
6160                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6161                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6162                 } else
6163                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6164         }
6165         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6166                 if (type == I40E_MAC_X722) {
6167                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6168                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6169                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6170                 } else
6171                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6172         }
6173         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6174                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6175         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6176                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6177         if (flags & ETH_RSS_FRAG_IPV6)
6178                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6179         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6180                 if (type == I40E_MAC_X722) {
6181                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6182                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6183                 } else
6184                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6185         }
6186         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6187                 if (type == I40E_MAC_X722) {
6188                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6189                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6190                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6191                 } else
6192                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6193         }
6194         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6195                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6196         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6197                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6198         if (flags & ETH_RSS_L2_PAYLOAD)
6199                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6200
6201         return hena;
6202 }
6203
6204 /* Parse the hash enable flags */
6205 uint64_t
6206 i40e_parse_hena(uint64_t flags)
6207 {
6208         uint64_t rss_hf = 0;
6209
6210         if (!flags)
6211                 return rss_hf;
6212         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6213                 rss_hf |= ETH_RSS_FRAG_IPV4;
6214         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6215                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6216 #ifdef X722_SUPPORT
6217         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6218                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6219 #endif
6220         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6221                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6222 #ifdef X722_SUPPORT
6223         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6224                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6225         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6226                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6227 #endif
6228         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6229                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6230         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6231                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6232         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6233                 rss_hf |= ETH_RSS_FRAG_IPV6;
6234         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6235                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6236 #ifdef X722_SUPPORT
6237         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6238                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6239 #endif
6240         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6241                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6242 #ifdef X722_SUPPORT
6243         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6244                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6245         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6246                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6247 #endif
6248         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6249                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6250         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6251                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6252         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6253                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6254
6255         return rss_hf;
6256 }
6257
6258 /* Disable RSS */
6259 static void
6260 i40e_pf_disable_rss(struct i40e_pf *pf)
6261 {
6262         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6263         uint64_t hena;
6264
6265         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6266         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6267         if (hw->mac.type == I40E_MAC_X722)
6268                 hena &= ~I40E_RSS_HENA_ALL_X722;
6269         else
6270                 hena &= ~I40E_RSS_HENA_ALL;
6271         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6272         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6273         I40E_WRITE_FLUSH(hw);
6274 }
6275
6276 static int
6277 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6278 {
6279         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6280         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6281         int ret = 0;
6282
6283         if (!key || key_len == 0) {
6284                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6285                 return 0;
6286         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6287                 sizeof(uint32_t)) {
6288                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6289                 return -EINVAL;
6290         }
6291
6292         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6293                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6294                         (struct i40e_aqc_get_set_rss_key_data *)key;
6295
6296                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6297                 if (ret)
6298                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6299                                      "via AQ");
6300         } else {
6301                 uint32_t *hash_key = (uint32_t *)key;
6302                 uint16_t i;
6303
6304                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6305                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6306                 I40E_WRITE_FLUSH(hw);
6307         }
6308
6309         return ret;
6310 }
6311
6312 static int
6313 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6314 {
6315         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6316         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6317         int ret;
6318
6319         if (!key || !key_len)
6320                 return -EINVAL;
6321
6322         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6323                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6324                         (struct i40e_aqc_get_set_rss_key_data *)key);
6325                 if (ret) {
6326                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6327                         return ret;
6328                 }
6329         } else {
6330                 uint32_t *key_dw = (uint32_t *)key;
6331                 uint16_t i;
6332
6333                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6334                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6335         }
6336         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6337
6338         return 0;
6339 }
6340
6341 static int
6342 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6343 {
6344         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6345         uint64_t rss_hf;
6346         uint64_t hena;
6347         int ret;
6348
6349         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6350                                rss_conf->rss_key_len);
6351         if (ret)
6352                 return ret;
6353
6354         rss_hf = rss_conf->rss_hf;
6355         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6356         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6357         if (hw->mac.type == I40E_MAC_X722)
6358                 hena &= ~I40E_RSS_HENA_ALL_X722;
6359         else
6360                 hena &= ~I40E_RSS_HENA_ALL;
6361         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6362         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6363         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6364         I40E_WRITE_FLUSH(hw);
6365
6366         return 0;
6367 }
6368
6369 static int
6370 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6371                          struct rte_eth_rss_conf *rss_conf)
6372 {
6373         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6374         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6375         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6376         uint64_t hena;
6377
6378         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6379         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6380         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6381                  ? I40E_RSS_HENA_ALL_X722
6382                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6383                 if (rss_hf != 0) /* Enable RSS */
6384                         return -EINVAL;
6385                 return 0; /* Nothing to do */
6386         }
6387         /* RSS enabled */
6388         if (rss_hf == 0) /* Disable RSS */
6389                 return -EINVAL;
6390
6391         return i40e_hw_rss_hash_set(pf, rss_conf);
6392 }
6393
6394 static int
6395 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6396                            struct rte_eth_rss_conf *rss_conf)
6397 {
6398         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6399         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6400         uint64_t hena;
6401
6402         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6403                          &rss_conf->rss_key_len);
6404
6405         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6406         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6407         rss_conf->rss_hf = i40e_parse_hena(hena);
6408
6409         return 0;
6410 }
6411
6412 static int
6413 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6414 {
6415         switch (filter_type) {
6416         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6417                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6418                 break;
6419         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6420                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6421                 break;
6422         case RTE_TUNNEL_FILTER_IMAC_TENID:
6423                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6424                 break;
6425         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6426                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6427                 break;
6428         case ETH_TUNNEL_FILTER_IMAC:
6429                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6430                 break;
6431         case ETH_TUNNEL_FILTER_OIP:
6432                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6433                 break;
6434         case ETH_TUNNEL_FILTER_IIP:
6435                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6436                 break;
6437         default:
6438                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6439                 return -EINVAL;
6440         }
6441
6442         return 0;
6443 }
6444
6445 static int
6446 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6447                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6448                         uint8_t add)
6449 {
6450         uint16_t ip_type;
6451         uint32_t ipv4_addr;
6452         uint8_t i, tun_type = 0;
6453         /* internal varialbe to convert ipv6 byte order */
6454         uint32_t convert_ipv6[4];
6455         int val, ret = 0;
6456         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6457         struct i40e_vsi *vsi = pf->main_vsi;
6458         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6459         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6460
6461         cld_filter = rte_zmalloc("tunnel_filter",
6462                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6463                 0);
6464
6465         if (NULL == cld_filter) {
6466                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6467                 return -EINVAL;
6468         }
6469         pfilter = cld_filter;
6470
6471         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6472         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6473
6474         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6475         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6476                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6477                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6478                 rte_memcpy(&pfilter->ipaddr.v4.data,
6479                                 &rte_cpu_to_le_32(ipv4_addr),
6480                                 sizeof(pfilter->ipaddr.v4.data));
6481         } else {
6482                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6483                 for (i = 0; i < 4; i++) {
6484                         convert_ipv6[i] =
6485                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6486                 }
6487                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6488                                 sizeof(pfilter->ipaddr.v6.data));
6489         }
6490
6491         /* check tunneled type */
6492         switch (tunnel_filter->tunnel_type) {
6493         case RTE_TUNNEL_TYPE_VXLAN:
6494                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6495                 break;
6496         case RTE_TUNNEL_TYPE_NVGRE:
6497                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6498                 break;
6499         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6500                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6501                 break;
6502         default:
6503                 /* Other tunnel types is not supported. */
6504                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6505                 rte_free(cld_filter);
6506                 return -EINVAL;
6507         }
6508
6509         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6510                                                 &pfilter->flags);
6511         if (val < 0) {
6512                 rte_free(cld_filter);
6513                 return -EINVAL;
6514         }
6515
6516         pfilter->flags |= rte_cpu_to_le_16(
6517                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6518                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6519         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6520         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6521
6522         if (add)
6523                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6524         else
6525                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6526                                                 cld_filter, 1);
6527
6528         rte_free(cld_filter);
6529         return ret;
6530 }
6531
6532 static int
6533 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6534 {
6535         uint8_t i;
6536
6537         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6538                 if (pf->vxlan_ports[i] == port)
6539                         return i;
6540         }
6541
6542         return -1;
6543 }
6544
6545 static int
6546 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6547 {
6548         int  idx, ret;
6549         uint8_t filter_idx;
6550         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6551
6552         idx = i40e_get_vxlan_port_idx(pf, port);
6553
6554         /* Check if port already exists */
6555         if (idx >= 0) {
6556                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6557                 return -EINVAL;
6558         }
6559
6560         /* Now check if there is space to add the new port */
6561         idx = i40e_get_vxlan_port_idx(pf, 0);
6562         if (idx < 0) {
6563                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6564                         "not adding port %d", port);
6565                 return -ENOSPC;
6566         }
6567
6568         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6569                                         &filter_idx, NULL);
6570         if (ret < 0) {
6571                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6572                 return -1;
6573         }
6574
6575         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6576                          port,  filter_idx);
6577
6578         /* New port: add it and mark its index in the bitmap */
6579         pf->vxlan_ports[idx] = port;
6580         pf->vxlan_bitmap |= (1 << idx);
6581
6582         if (!(pf->flags & I40E_FLAG_VXLAN))
6583                 pf->flags |= I40E_FLAG_VXLAN;
6584
6585         return 0;
6586 }
6587
6588 static int
6589 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6590 {
6591         int idx;
6592         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6593
6594         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6595                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6596                 return -EINVAL;
6597         }
6598
6599         idx = i40e_get_vxlan_port_idx(pf, port);
6600
6601         if (idx < 0) {
6602                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6603                 return -EINVAL;
6604         }
6605
6606         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6607                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6608                 return -1;
6609         }
6610
6611         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6612                         port, idx);
6613
6614         pf->vxlan_ports[idx] = 0;
6615         pf->vxlan_bitmap &= ~(1 << idx);
6616
6617         if (!pf->vxlan_bitmap)
6618                 pf->flags &= ~I40E_FLAG_VXLAN;
6619
6620         return 0;
6621 }
6622
6623 /* Add UDP tunneling port */
6624 static int
6625 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6626                              struct rte_eth_udp_tunnel *udp_tunnel)
6627 {
6628         int ret = 0;
6629         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6630
6631         if (udp_tunnel == NULL)
6632                 return -EINVAL;
6633
6634         switch (udp_tunnel->prot_type) {
6635         case RTE_TUNNEL_TYPE_VXLAN:
6636                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6637                 break;
6638
6639         case RTE_TUNNEL_TYPE_GENEVE:
6640         case RTE_TUNNEL_TYPE_TEREDO:
6641                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6642                 ret = -1;
6643                 break;
6644
6645         default:
6646                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6647                 ret = -1;
6648                 break;
6649         }
6650
6651         return ret;
6652 }
6653
6654 /* Remove UDP tunneling port */
6655 static int
6656 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6657                              struct rte_eth_udp_tunnel *udp_tunnel)
6658 {
6659         int ret = 0;
6660         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6661
6662         if (udp_tunnel == NULL)
6663                 return -EINVAL;
6664
6665         switch (udp_tunnel->prot_type) {
6666         case RTE_TUNNEL_TYPE_VXLAN:
6667                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6668                 break;
6669         case RTE_TUNNEL_TYPE_GENEVE:
6670         case RTE_TUNNEL_TYPE_TEREDO:
6671                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6672                 ret = -1;
6673                 break;
6674         default:
6675                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6676                 ret = -1;
6677                 break;
6678         }
6679
6680         return ret;
6681 }
6682
6683 /* Calculate the maximum number of contiguous PF queues that are configured */
6684 static int
6685 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6686 {
6687         struct rte_eth_dev_data *data = pf->dev_data;
6688         int i, num;
6689         struct i40e_rx_queue *rxq;
6690
6691         num = 0;
6692         for (i = 0; i < pf->lan_nb_qps; i++) {
6693                 rxq = data->rx_queues[i];
6694                 if (rxq && rxq->q_set)
6695                         num++;
6696                 else
6697                         break;
6698         }
6699
6700         return num;
6701 }
6702
6703 /* Configure RSS */
6704 static int
6705 i40e_pf_config_rss(struct i40e_pf *pf)
6706 {
6707         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6708         struct rte_eth_rss_conf rss_conf;
6709         uint32_t i, lut = 0;
6710         uint16_t j, num;
6711
6712         /*
6713          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6714          * It's necessary to calulate the actual PF queues that are configured.
6715          */
6716         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6717                 num = i40e_pf_calc_configured_queues_num(pf);
6718         else
6719                 num = pf->dev_data->nb_rx_queues;
6720
6721         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6722         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6723                         num);
6724
6725         if (num == 0) {
6726                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6727                 return -ENOTSUP;
6728         }
6729
6730         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6731                 if (j == num)
6732                         j = 0;
6733                 lut = (lut << 8) | (j & ((0x1 <<
6734                         hw->func_caps.rss_table_entry_width) - 1));
6735                 if ((i & 3) == 3)
6736                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6737         }
6738
6739         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6740         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6741                 i40e_pf_disable_rss(pf);
6742                 return 0;
6743         }
6744         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6745                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6746                 /* Random default keys */
6747                 static uint32_t rss_key_default[] = {0x6b793944,
6748                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6749                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6750                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6751
6752                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6753                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6754                                                         sizeof(uint32_t);
6755         }
6756
6757         return i40e_hw_rss_hash_set(pf, &rss_conf);
6758 }
6759
6760 static int
6761 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6762                                struct rte_eth_tunnel_filter_conf *filter)
6763 {
6764         if (pf == NULL || filter == NULL) {
6765                 PMD_DRV_LOG(ERR, "Invalid parameter");
6766                 return -EINVAL;
6767         }
6768
6769         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6770                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6771                 return -EINVAL;
6772         }
6773
6774         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6775                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6776                 return -EINVAL;
6777         }
6778
6779         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6780                 (is_zero_ether_addr(&filter->outer_mac))) {
6781                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6782                 return -EINVAL;
6783         }
6784
6785         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6786                 (is_zero_ether_addr(&filter->inner_mac))) {
6787                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6788                 return -EINVAL;
6789         }
6790
6791         return 0;
6792 }
6793
6794 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6795 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6796 static int
6797 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6798 {
6799         uint32_t val, reg;
6800         int ret = -EINVAL;
6801
6802         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6803         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6804
6805         if (len == 3) {
6806                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6807         } else if (len == 4) {
6808                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6809         } else {
6810                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6811                 return ret;
6812         }
6813
6814         if (reg != val) {
6815                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6816                                                    reg, NULL);
6817                 if (ret != 0)
6818                         return ret;
6819         } else {
6820                 ret = 0;
6821         }
6822         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6823                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6824
6825         return ret;
6826 }
6827
6828 static int
6829 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6830 {
6831         int ret = -EINVAL;
6832
6833         if (!hw || !cfg)
6834                 return -EINVAL;
6835
6836         switch (cfg->cfg_type) {
6837         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6838                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6839                 break;
6840         default:
6841                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6842                 break;
6843         }
6844
6845         return ret;
6846 }
6847
6848 static int
6849 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6850                                enum rte_filter_op filter_op,
6851                                void *arg)
6852 {
6853         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6854         int ret = I40E_ERR_PARAM;
6855
6856         switch (filter_op) {
6857         case RTE_ETH_FILTER_SET:
6858                 ret = i40e_dev_global_config_set(hw,
6859                         (struct rte_eth_global_cfg *)arg);
6860                 break;
6861         default:
6862                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6863                 break;
6864         }
6865
6866         return ret;
6867 }
6868
6869 static int
6870 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6871                           enum rte_filter_op filter_op,
6872                           void *arg)
6873 {
6874         struct rte_eth_tunnel_filter_conf *filter;
6875         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6876         int ret = I40E_SUCCESS;
6877
6878         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6879
6880         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6881                 return I40E_ERR_PARAM;
6882
6883         switch (filter_op) {
6884         case RTE_ETH_FILTER_NOP:
6885                 if (!(pf->flags & I40E_FLAG_VXLAN))
6886                         ret = I40E_NOT_SUPPORTED;
6887                 break;
6888         case RTE_ETH_FILTER_ADD:
6889                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6890                 break;
6891         case RTE_ETH_FILTER_DELETE:
6892                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6893                 break;
6894         default:
6895                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6896                 ret = I40E_ERR_PARAM;
6897                 break;
6898         }
6899
6900         return ret;
6901 }
6902
6903 static int
6904 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6905 {
6906         int ret = 0;
6907         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6908
6909         /* RSS setup */
6910         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6911                 ret = i40e_pf_config_rss(pf);
6912         else
6913                 i40e_pf_disable_rss(pf);
6914
6915         return ret;
6916 }
6917
6918 /* Get the symmetric hash enable configurations per port */
6919 static void
6920 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6921 {
6922         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6923
6924         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6925 }
6926
6927 /* Set the symmetric hash enable configurations per port */
6928 static void
6929 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6930 {
6931         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6932
6933         if (enable > 0) {
6934                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6935                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6936                                                         "been enabled");
6937                         return;
6938                 }
6939                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6940         } else {
6941                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6942                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6943                                                         "been disabled");
6944                         return;
6945                 }
6946                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6947         }
6948         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6949         I40E_WRITE_FLUSH(hw);
6950 }
6951
6952 /*
6953  * Get global configurations of hash function type and symmetric hash enable
6954  * per flow type (pctype). Note that global configuration means it affects all
6955  * the ports on the same NIC.
6956  */
6957 static int
6958 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6959                                    struct rte_eth_hash_global_conf *g_cfg)
6960 {
6961         uint32_t reg, mask = I40E_FLOW_TYPES;
6962         uint16_t i;
6963         enum i40e_filter_pctype pctype;
6964
6965         memset(g_cfg, 0, sizeof(*g_cfg));
6966         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6967         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6968                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6969         else
6970                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6971         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6972                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6973
6974         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6975                 if (!(mask & (1UL << i)))
6976                         continue;
6977                 mask &= ~(1UL << i);
6978                 /* Bit set indicats the coresponding flow type is supported */
6979                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6980                 /* if flowtype is invalid, continue */
6981                 if (!I40E_VALID_FLOW(i))
6982                         continue;
6983                 pctype = i40e_flowtype_to_pctype(i);
6984                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6985                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6986                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6987         }
6988
6989         return 0;
6990 }
6991
6992 static int
6993 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6994 {
6995         uint32_t i;
6996         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6997
6998         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6999                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7000                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7001                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7002                                                 g_cfg->hash_func);
7003                 return -EINVAL;
7004         }
7005
7006         /*
7007          * As i40e supports less than 32 flow types, only first 32 bits need to
7008          * be checked.
7009          */
7010         mask0 = g_cfg->valid_bit_mask[0];
7011         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7012                 if (i == 0) {
7013                         /* Check if any unsupported flow type configured */
7014                         if ((mask0 | i40e_mask) ^ i40e_mask)
7015                                 goto mask_err;
7016                 } else {
7017                         if (g_cfg->valid_bit_mask[i])
7018                                 goto mask_err;
7019                 }
7020         }
7021
7022         return 0;
7023
7024 mask_err:
7025         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7026
7027         return -EINVAL;
7028 }
7029
7030 /*
7031  * Set global configurations of hash function type and symmetric hash enable
7032  * per flow type (pctype). Note any modifying global configuration will affect
7033  * all the ports on the same NIC.
7034  */
7035 static int
7036 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7037                                    struct rte_eth_hash_global_conf *g_cfg)
7038 {
7039         int ret;
7040         uint16_t i;
7041         uint32_t reg;
7042         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7043         enum i40e_filter_pctype pctype;
7044
7045         /* Check the input parameters */
7046         ret = i40e_hash_global_config_check(g_cfg);
7047         if (ret < 0)
7048                 return ret;
7049
7050         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7051                 if (!(mask0 & (1UL << i)))
7052                         continue;
7053                 mask0 &= ~(1UL << i);
7054                 /* if flowtype is invalid, continue */
7055                 if (!I40E_VALID_FLOW(i))
7056                         continue;
7057                 pctype = i40e_flowtype_to_pctype(i);
7058                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7059                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7060                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7061         }
7062
7063         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7064         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7065                 /* Toeplitz */
7066                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7067                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7068                                                                 "Toeplitz");
7069                         goto out;
7070                 }
7071                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7072         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7073                 /* Simple XOR */
7074                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7075                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7076                                                         "Simple XOR");
7077                         goto out;
7078                 }
7079                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7080         } else
7081                 /* Use the default, and keep it as it is */
7082                 goto out;
7083
7084         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7085
7086 out:
7087         I40E_WRITE_FLUSH(hw);
7088
7089         return 0;
7090 }
7091
7092 /**
7093  * Valid input sets for hash and flow director filters per PCTYPE
7094  */
7095 static uint64_t
7096 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7097                 enum rte_filter_type filter)
7098 {
7099         uint64_t valid;
7100
7101         static const uint64_t valid_hash_inset_table[] = {
7102                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7103                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7104                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7105                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7106                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7107                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7108                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7109                         I40E_INSET_FLEX_PAYLOAD,
7110                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7111                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7112                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7113                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7114                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7115                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7116                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7117                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7118                         I40E_INSET_FLEX_PAYLOAD,
7119 #ifdef X722_SUPPORT
7120                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7121                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7122                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7123                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7124                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7125                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7126                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7127                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7128                         I40E_INSET_FLEX_PAYLOAD,
7129                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7130                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7131                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7132                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7133                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7134                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7135                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7136                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7137                         I40E_INSET_FLEX_PAYLOAD,
7138 #endif
7139                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7140                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7141                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7142                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7143                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7144                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7145                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7146                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7147                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7148 #ifdef X722_SUPPORT
7149                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7150                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7151                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7152                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7153                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7154                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7155                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7156                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7157                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7158 #endif
7159                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7160                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7161                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7162                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7163                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7164                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7165                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7166                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7167                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7168                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7169                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7170                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7171                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7172                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7173                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7174                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7175                         I40E_INSET_FLEX_PAYLOAD,
7176                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7177                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7178                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7179                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7180                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7181                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7182                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7183                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7184                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7185                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7186                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7187                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7188                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7189                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7190                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7191                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7192 #ifdef X722_SUPPORT
7193                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7194                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7195                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7196                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7197                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7198                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7199                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7200                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7201                         I40E_INSET_FLEX_PAYLOAD,
7202                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7203                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7204                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7205                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7206                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7207                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7208                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7209                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7210                         I40E_INSET_FLEX_PAYLOAD,
7211 #endif
7212                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7213                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7214                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7215                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7216                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7217                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7218                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7219                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7220                         I40E_INSET_FLEX_PAYLOAD,
7221 #ifdef X722_SUPPORT
7222                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7223                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7224                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7225                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7226                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7227                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7228                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7229                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7230                         I40E_INSET_FLEX_PAYLOAD,
7231 #endif
7232                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7233                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7234                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7235                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7236                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7237                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7238                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7239                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7240                         I40E_INSET_FLEX_PAYLOAD,
7241                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7242                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7243                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7244                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7245                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7246                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7247                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7248                         I40E_INSET_FLEX_PAYLOAD,
7249                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7250                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7251                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7252                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7253                         I40E_INSET_FLEX_PAYLOAD,
7254         };
7255
7256         /**
7257          * Flow director supports only fields defined in
7258          * union rte_eth_fdir_flow.
7259          */
7260         static const uint64_t valid_fdir_inset_table[] = {
7261                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7262                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7263                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7264                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7265                 I40E_INSET_IPV4_TTL,
7266                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7267                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7268                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7269                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7270                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7271 #ifdef X722_SUPPORT
7272                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7273                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7274                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7275                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7276                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7277                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7278                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7279                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7280                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7281                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7282 #endif
7283                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7284                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7285                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7286                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7287                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7288 #ifdef X722_SUPPORT
7289                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7290                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7291                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7292                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7293                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7294 #endif
7295                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7296                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7297                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7298                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7299                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7300                 I40E_INSET_SCTP_VT,
7301                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7302                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7303                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7304                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7305                 I40E_INSET_IPV4_TTL,
7306                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7307                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7308                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7309                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7310                 I40E_INSET_IPV6_HOP_LIMIT,
7311                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7312                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7313                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7314                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7315                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7316 #ifdef X722_SUPPORT
7317                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7318                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7319                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7320                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7321                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7322                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7323                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7324                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7325                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7326                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7327 #endif
7328                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7329                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7330                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7331                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7332                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7333 #ifdef X722_SUPPORT
7334                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7335                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7336                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7337                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7338                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7339 #endif
7340                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7341                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7342                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7343                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7344                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7345                 I40E_INSET_SCTP_VT,
7346                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7347                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7348                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7349                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7350                 I40E_INSET_IPV6_HOP_LIMIT,
7351                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7352                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7353                 I40E_INSET_LAST_ETHER_TYPE,
7354         };
7355
7356         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7357                 return 0;
7358         if (filter == RTE_ETH_FILTER_HASH)
7359                 valid = valid_hash_inset_table[pctype];
7360         else
7361                 valid = valid_fdir_inset_table[pctype];
7362
7363         return valid;
7364 }
7365
7366 /**
7367  * Validate if the input set is allowed for a specific PCTYPE
7368  */
7369 static int
7370 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7371                 enum rte_filter_type filter, uint64_t inset)
7372 {
7373         uint64_t valid;
7374
7375         valid = i40e_get_valid_input_set(pctype, filter);
7376         if (inset & (~valid))
7377                 return -EINVAL;
7378
7379         return 0;
7380 }
7381
7382 /* default input set fields combination per pctype */
7383 static uint64_t
7384 i40e_get_default_input_set(uint16_t pctype)
7385 {
7386         static const uint64_t default_inset_table[] = {
7387                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7388                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7389                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7390                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7391                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7392 #ifdef X722_SUPPORT
7393                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7394                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7395                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7396                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7397                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7398                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7399 #endif
7400                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7401                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7402                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7403 #ifdef X722_SUPPORT
7404                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7405                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7406                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7407 #endif
7408                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7409                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7410                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7411                         I40E_INSET_SCTP_VT,
7412                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7413                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7414                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7415                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7416                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7417                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7418                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7419 #ifdef X722_SUPPORT
7420                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7421                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7422                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7423                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7424                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7425                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7426 #endif
7427                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7428                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7429                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7430 #ifdef X722_SUPPORT
7431                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7432                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7433                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7434 #endif
7435                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7436                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7437                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7438                         I40E_INSET_SCTP_VT,
7439                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7440                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7441                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7442                         I40E_INSET_LAST_ETHER_TYPE,
7443         };
7444
7445         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7446                 return 0;
7447
7448         return default_inset_table[pctype];
7449 }
7450
7451 /**
7452  * Parse the input set from index to logical bit masks
7453  */
7454 static int
7455 i40e_parse_input_set(uint64_t *inset,
7456                      enum i40e_filter_pctype pctype,
7457                      enum rte_eth_input_set_field *field,
7458                      uint16_t size)
7459 {
7460         uint16_t i, j;
7461         int ret = -EINVAL;
7462
7463         static const struct {
7464                 enum rte_eth_input_set_field field;
7465                 uint64_t inset;
7466         } inset_convert_table[] = {
7467                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7468                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7469                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7470                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7471                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7472                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7473                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7474                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7475                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7476                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7477                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7478                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7479                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7480                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7481                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7482                         I40E_INSET_IPV6_NEXT_HDR},
7483                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7484                         I40E_INSET_IPV6_HOP_LIMIT},
7485                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7486                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7487                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7488                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7489                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7490                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7491                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7492                         I40E_INSET_SCTP_VT},
7493                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7494                         I40E_INSET_TUNNEL_DMAC},
7495                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7496                         I40E_INSET_VLAN_TUNNEL},
7497                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7498                         I40E_INSET_TUNNEL_ID},
7499                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7500                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7501                         I40E_INSET_FLEX_PAYLOAD_W1},
7502                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7503                         I40E_INSET_FLEX_PAYLOAD_W2},
7504                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7505                         I40E_INSET_FLEX_PAYLOAD_W3},
7506                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7507                         I40E_INSET_FLEX_PAYLOAD_W4},
7508                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7509                         I40E_INSET_FLEX_PAYLOAD_W5},
7510                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7511                         I40E_INSET_FLEX_PAYLOAD_W6},
7512                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7513                         I40E_INSET_FLEX_PAYLOAD_W7},
7514                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7515                         I40E_INSET_FLEX_PAYLOAD_W8},
7516         };
7517
7518         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7519                 return ret;
7520
7521         /* Only one item allowed for default or all */
7522         if (size == 1) {
7523                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7524                         *inset = i40e_get_default_input_set(pctype);
7525                         return 0;
7526                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7527                         *inset = I40E_INSET_NONE;
7528                         return 0;
7529                 }
7530         }
7531
7532         for (i = 0, *inset = 0; i < size; i++) {
7533                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7534                         if (field[i] == inset_convert_table[j].field) {
7535                                 *inset |= inset_convert_table[j].inset;
7536                                 break;
7537                         }
7538                 }
7539
7540                 /* It contains unsupported input set, return immediately */
7541                 if (j == RTE_DIM(inset_convert_table))
7542                         return ret;
7543         }
7544
7545         return 0;
7546 }
7547
7548 /**
7549  * Translate the input set from bit masks to register aware bit masks
7550  * and vice versa
7551  */
7552 static uint64_t
7553 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7554 {
7555         uint64_t val = 0;
7556         uint16_t i;
7557
7558         struct inset_map {
7559                 uint64_t inset;
7560                 uint64_t inset_reg;
7561         };
7562
7563         static const struct inset_map inset_map_common[] = {
7564                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7565                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7566                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7567                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7568                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7569                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7570                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7571                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7572                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7573                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7574                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7575                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7576                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7577                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7578                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7579                 {I40E_INSET_TUNNEL_DMAC,
7580                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7581                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7582                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7583                 {I40E_INSET_TUNNEL_SRC_PORT,
7584                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7585                 {I40E_INSET_TUNNEL_DST_PORT,
7586                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7587                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7588                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7589                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7590                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7591                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7592                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7593                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7594                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7595                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7596         };
7597
7598     /* some different registers map in x722*/
7599         static const struct inset_map inset_map_diff_x722[] = {
7600                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7601                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7602                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7603                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7604         };
7605
7606         static const struct inset_map inset_map_diff_not_x722[] = {
7607                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7608                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7609                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7610                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7611         };
7612
7613         if (input == 0)
7614                 return val;
7615
7616         /* Translate input set to register aware inset */
7617         if (type == I40E_MAC_X722) {
7618                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7619                         if (input & inset_map_diff_x722[i].inset)
7620                                 val |= inset_map_diff_x722[i].inset_reg;
7621                 }
7622         } else {
7623                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7624                         if (input & inset_map_diff_not_x722[i].inset)
7625                                 val |= inset_map_diff_not_x722[i].inset_reg;
7626                 }
7627         }
7628
7629         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7630                 if (input & inset_map_common[i].inset)
7631                         val |= inset_map_common[i].inset_reg;
7632         }
7633
7634         return val;
7635 }
7636
7637 static int
7638 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7639 {
7640         uint8_t i, idx = 0;
7641         uint64_t inset_need_mask = inset;
7642
7643         static const struct {
7644                 uint64_t inset;
7645                 uint32_t mask;
7646         } inset_mask_map[] = {
7647                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7648                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7649                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7650                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7651                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7652                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7653                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7654                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7655         };
7656
7657         if (!inset || !mask || !nb_elem)
7658                 return 0;
7659
7660         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7661                 /* Clear the inset bit, if no MASK is required,
7662                  * for example proto + ttl
7663                  */
7664                 if ((inset & inset_mask_map[i].inset) ==
7665                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7666                         inset_need_mask &= ~inset_mask_map[i].inset;
7667                 if (!inset_need_mask)
7668                         return 0;
7669         }
7670         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7671                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7672                     inset_mask_map[i].inset) {
7673                         if (idx >= nb_elem) {
7674                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7675                                 return -EINVAL;
7676                         }
7677                         mask[idx] = inset_mask_map[i].mask;
7678                         idx++;
7679                 }
7680         }
7681
7682         return idx;
7683 }
7684
7685 static void
7686 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7687 {
7688         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7689
7690         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7691         if (reg != val)
7692                 i40e_write_rx_ctl(hw, addr, val);
7693         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7694                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7695 }
7696
7697 static void
7698 i40e_filter_input_set_init(struct i40e_pf *pf)
7699 {
7700         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7701         enum i40e_filter_pctype pctype;
7702         uint64_t input_set, inset_reg;
7703         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7704         int num, i;
7705
7706         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7707              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7708                 if (hw->mac.type == I40E_MAC_X722) {
7709                         if (!I40E_VALID_PCTYPE_X722(pctype))
7710                                 continue;
7711                 } else {
7712                         if (!I40E_VALID_PCTYPE(pctype))
7713                                 continue;
7714                 }
7715
7716                 input_set = i40e_get_default_input_set(pctype);
7717
7718                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7719                                                    I40E_INSET_MASK_NUM_REG);
7720                 if (num < 0)
7721                         return;
7722                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
7723                                         input_set);
7724
7725                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7726                                       (uint32_t)(inset_reg & UINT32_MAX));
7727                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7728                                      (uint32_t)((inset_reg >>
7729                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7730                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7731                                       (uint32_t)(inset_reg & UINT32_MAX));
7732                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7733                                      (uint32_t)((inset_reg >>
7734                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7735
7736                 for (i = 0; i < num; i++) {
7737                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7738                                              mask_reg[i]);
7739                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7740                                              mask_reg[i]);
7741                 }
7742                 /*clear unused mask registers of the pctype */
7743                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7744                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7745                                              0);
7746                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7747                                              0);
7748                 }
7749                 I40E_WRITE_FLUSH(hw);
7750
7751                 /* store the default input set */
7752                 pf->hash_input_set[pctype] = input_set;
7753                 pf->fdir.input_set[pctype] = input_set;
7754         }
7755 }
7756
7757 int
7758 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7759                          struct rte_eth_input_set_conf *conf)
7760 {
7761         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7762         enum i40e_filter_pctype pctype;
7763         uint64_t input_set, inset_reg = 0;
7764         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7765         int ret, i, num;
7766
7767         if (!conf) {
7768                 PMD_DRV_LOG(ERR, "Invalid pointer");
7769                 return -EFAULT;
7770         }
7771         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7772             conf->op != RTE_ETH_INPUT_SET_ADD) {
7773                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7774                 return -EINVAL;
7775         }
7776
7777         if (!I40E_VALID_FLOW(conf->flow_type)) {
7778                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7779                 return -EINVAL;
7780         }
7781
7782         if (hw->mac.type == I40E_MAC_X722) {
7783                 /* get translated pctype value in fd pctype register */
7784                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
7785                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
7786                         conf->flow_type)));
7787         } else
7788                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7789
7790         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7791                                    conf->inset_size);
7792         if (ret) {
7793                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7794                 return -EINVAL;
7795         }
7796         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7797                                     input_set) != 0) {
7798                 PMD_DRV_LOG(ERR, "Invalid input set");
7799                 return -EINVAL;
7800         }
7801         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7802                 /* get inset value in register */
7803                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7804                 inset_reg <<= I40E_32_BIT_WIDTH;
7805                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7806                 input_set |= pf->hash_input_set[pctype];
7807         }
7808         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7809                                            I40E_INSET_MASK_NUM_REG);
7810         if (num < 0)
7811                 return -EINVAL;
7812
7813         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7814
7815         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7816                               (uint32_t)(inset_reg & UINT32_MAX));
7817         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7818                              (uint32_t)((inset_reg >>
7819                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7820
7821         for (i = 0; i < num; i++)
7822                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7823                                      mask_reg[i]);
7824         /*clear unused mask registers of the pctype */
7825         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7826                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7827                                      0);
7828         I40E_WRITE_FLUSH(hw);
7829
7830         pf->hash_input_set[pctype] = input_set;
7831         return 0;
7832 }
7833
7834 int
7835 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7836                          struct rte_eth_input_set_conf *conf)
7837 {
7838         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7839         enum i40e_filter_pctype pctype;
7840         uint64_t input_set, inset_reg = 0;
7841         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7842         int ret, i, num;
7843
7844         if (!hw || !conf) {
7845                 PMD_DRV_LOG(ERR, "Invalid pointer");
7846                 return -EFAULT;
7847         }
7848         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7849             conf->op != RTE_ETH_INPUT_SET_ADD) {
7850                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7851                 return -EINVAL;
7852         }
7853
7854         if (!I40E_VALID_FLOW(conf->flow_type)) {
7855                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7856                 return -EINVAL;
7857         }
7858
7859         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7860
7861         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7862                                    conf->inset_size);
7863         if (ret) {
7864                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7865                 return -EINVAL;
7866         }
7867         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7868                                     input_set) != 0) {
7869                 PMD_DRV_LOG(ERR, "Invalid input set");
7870                 return -EINVAL;
7871         }
7872
7873         /* get inset value in register */
7874         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7875         inset_reg <<= I40E_32_BIT_WIDTH;
7876         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7877
7878         /* Can not change the inset reg for flex payload for fdir,
7879          * it is done by writing I40E_PRTQF_FD_FLXINSET
7880          * in i40e_set_flex_mask_on_pctype.
7881          */
7882         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7883                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7884         else
7885                 input_set |= pf->fdir.input_set[pctype];
7886         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7887                                            I40E_INSET_MASK_NUM_REG);
7888         if (num < 0)
7889                 return -EINVAL;
7890
7891         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7892
7893         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7894                               (uint32_t)(inset_reg & UINT32_MAX));
7895         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7896                              (uint32_t)((inset_reg >>
7897                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7898
7899         for (i = 0; i < num; i++)
7900                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7901                                      mask_reg[i]);
7902         /*clear unused mask registers of the pctype */
7903         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7904                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7905                                      0);
7906         I40E_WRITE_FLUSH(hw);
7907
7908         pf->fdir.input_set[pctype] = input_set;
7909         return 0;
7910 }
7911
7912 static int
7913 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7914 {
7915         int ret = 0;
7916
7917         if (!hw || !info) {
7918                 PMD_DRV_LOG(ERR, "Invalid pointer");
7919                 return -EFAULT;
7920         }
7921
7922         switch (info->info_type) {
7923         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7924                 i40e_get_symmetric_hash_enable_per_port(hw,
7925                                         &(info->info.enable));
7926                 break;
7927         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7928                 ret = i40e_get_hash_filter_global_config(hw,
7929                                 &(info->info.global_conf));
7930                 break;
7931         default:
7932                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7933                                                         info->info_type);
7934                 ret = -EINVAL;
7935                 break;
7936         }
7937
7938         return ret;
7939 }
7940
7941 static int
7942 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7943 {
7944         int ret = 0;
7945
7946         if (!hw || !info) {
7947                 PMD_DRV_LOG(ERR, "Invalid pointer");
7948                 return -EFAULT;
7949         }
7950
7951         switch (info->info_type) {
7952         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7953                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7954                 break;
7955         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7956                 ret = i40e_set_hash_filter_global_config(hw,
7957                                 &(info->info.global_conf));
7958                 break;
7959         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7960                 ret = i40e_hash_filter_inset_select(hw,
7961                                                &(info->info.input_set_conf));
7962                 break;
7963
7964         default:
7965                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7966                                                         info->info_type);
7967                 ret = -EINVAL;
7968                 break;
7969         }
7970
7971         return ret;
7972 }
7973
7974 /* Operations for hash function */
7975 static int
7976 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7977                       enum rte_filter_op filter_op,
7978                       void *arg)
7979 {
7980         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7981         int ret = 0;
7982
7983         switch (filter_op) {
7984         case RTE_ETH_FILTER_NOP:
7985                 break;
7986         case RTE_ETH_FILTER_GET:
7987                 ret = i40e_hash_filter_get(hw,
7988                         (struct rte_eth_hash_filter_info *)arg);
7989                 break;
7990         case RTE_ETH_FILTER_SET:
7991                 ret = i40e_hash_filter_set(hw,
7992                         (struct rte_eth_hash_filter_info *)arg);
7993                 break;
7994         default:
7995                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7996                                                                 filter_op);
7997                 ret = -ENOTSUP;
7998                 break;
7999         }
8000
8001         return ret;
8002 }
8003
8004 /*
8005  * Configure ethertype filter, which can director packet by filtering
8006  * with mac address and ether_type or only ether_type
8007  */
8008 static int
8009 i40e_ethertype_filter_set(struct i40e_pf *pf,
8010                         struct rte_eth_ethertype_filter *filter,
8011                         bool add)
8012 {
8013         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8014         struct i40e_control_filter_stats stats;
8015         uint16_t flags = 0;
8016         int ret;
8017
8018         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8019                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8020                 return -EINVAL;
8021         }
8022         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8023                 filter->ether_type == ETHER_TYPE_IPv6) {
8024                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8025                         " control packet filter.", filter->ether_type);
8026                 return -EINVAL;
8027         }
8028         if (filter->ether_type == ETHER_TYPE_VLAN)
8029                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8030                         " not supported.");
8031
8032         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8033                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8034         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8035                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8036         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8037
8038         memset(&stats, 0, sizeof(stats));
8039         ret = i40e_aq_add_rem_control_packet_filter(hw,
8040                         filter->mac_addr.addr_bytes,
8041                         filter->ether_type, flags,
8042                         pf->main_vsi->seid,
8043                         filter->queue, add, &stats, NULL);
8044
8045         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8046                          " mac_etype_used = %u, etype_used = %u,"
8047                          " mac_etype_free = %u, etype_free = %u\n",
8048                          ret, stats.mac_etype_used, stats.etype_used,
8049                          stats.mac_etype_free, stats.etype_free);
8050         if (ret < 0)
8051                 return -ENOSYS;
8052         return 0;
8053 }
8054
8055 /*
8056  * Handle operations for ethertype filter.
8057  */
8058 static int
8059 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8060                                 enum rte_filter_op filter_op,
8061                                 void *arg)
8062 {
8063         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8064         int ret = 0;
8065
8066         if (filter_op == RTE_ETH_FILTER_NOP)
8067                 return ret;
8068
8069         if (arg == NULL) {
8070                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8071                             filter_op);
8072                 return -EINVAL;
8073         }
8074
8075         switch (filter_op) {
8076         case RTE_ETH_FILTER_ADD:
8077                 ret = i40e_ethertype_filter_set(pf,
8078                         (struct rte_eth_ethertype_filter *)arg,
8079                         TRUE);
8080                 break;
8081         case RTE_ETH_FILTER_DELETE:
8082                 ret = i40e_ethertype_filter_set(pf,
8083                         (struct rte_eth_ethertype_filter *)arg,
8084                         FALSE);
8085                 break;
8086         default:
8087                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8088                 ret = -ENOSYS;
8089                 break;
8090         }
8091         return ret;
8092 }
8093
8094 static int
8095 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8096                      enum rte_filter_type filter_type,
8097                      enum rte_filter_op filter_op,
8098                      void *arg)
8099 {
8100         int ret = 0;
8101
8102         if (dev == NULL)
8103                 return -EINVAL;
8104
8105         switch (filter_type) {
8106         case RTE_ETH_FILTER_NONE:
8107                 /* For global configuration */
8108                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8109                 break;
8110         case RTE_ETH_FILTER_HASH:
8111                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8112                 break;
8113         case RTE_ETH_FILTER_MACVLAN:
8114                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8115                 break;
8116         case RTE_ETH_FILTER_ETHERTYPE:
8117                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8118                 break;
8119         case RTE_ETH_FILTER_TUNNEL:
8120                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8121                 break;
8122         case RTE_ETH_FILTER_FDIR:
8123                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8124                 break;
8125         default:
8126                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8127                                                         filter_type);
8128                 ret = -EINVAL;
8129                 break;
8130         }
8131
8132         return ret;
8133 }
8134
8135 /*
8136  * Check and enable Extended Tag.
8137  * Enabling Extended Tag is important for 40G performance.
8138  */
8139 static void
8140 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8141 {
8142         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8143         uint32_t buf = 0;
8144         int ret;
8145
8146         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8147                                       PCI_DEV_CAP_REG);
8148         if (ret < 0) {
8149                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8150                             PCI_DEV_CAP_REG);
8151                 return;
8152         }
8153         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8154                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8155                 return;
8156         }
8157
8158         buf = 0;
8159         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8160                                       PCI_DEV_CTRL_REG);
8161         if (ret < 0) {
8162                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8163                             PCI_DEV_CTRL_REG);
8164                 return;
8165         }
8166         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8167                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8168                 return;
8169         }
8170         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8171         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8172                                        PCI_DEV_CTRL_REG);
8173         if (ret < 0) {
8174                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8175                             PCI_DEV_CTRL_REG);
8176                 return;
8177         }
8178 }
8179
8180 /*
8181  * As some registers wouldn't be reset unless a global hardware reset,
8182  * hardware initialization is needed to put those registers into an
8183  * expected initial state.
8184  */
8185 static void
8186 i40e_hw_init(struct rte_eth_dev *dev)
8187 {
8188         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8189
8190         i40e_enable_extended_tag(dev);
8191
8192         /* clear the PF Queue Filter control register */
8193         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8194
8195         /* Disable symmetric hash per port */
8196         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8197 }
8198
8199 enum i40e_filter_pctype
8200 i40e_flowtype_to_pctype(uint16_t flow_type)
8201 {
8202         static const enum i40e_filter_pctype pctype_table[] = {
8203                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8204                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8205                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8206                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8207                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8208                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8209                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8210                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8211                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8212                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8213                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8214                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8215                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8216                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8217                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8218                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8219                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8220                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8221                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8222         };
8223
8224         return pctype_table[flow_type];
8225 }
8226
8227 uint16_t
8228 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8229 {
8230         static const uint16_t flowtype_table[] = {
8231                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8232                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8233                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8234 #ifdef X722_SUPPORT
8235                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8236                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8237                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8238                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8239 #endif
8240                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8241                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8242 #ifdef X722_SUPPORT
8243                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8244                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8245 #endif
8246                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8247                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8248                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8249                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8250                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8251                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8252                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8253 #ifdef X722_SUPPORT
8254                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8255                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8256                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8257                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8258 #endif
8259                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8260                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8261 #ifdef X722_SUPPORT
8262                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8263                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8264 #endif
8265                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8266                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8267                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8268                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8269                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8270         };
8271
8272         return flowtype_table[pctype];
8273 }
8274
8275 /*
8276  * On X710, performance number is far from the expectation on recent firmware
8277  * versions; on XL710, performance number is also far from the expectation on
8278  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8279  * mode is enabled and port MAC address is equal to the packet destination MAC
8280  * address. The fix for this issue may not be integrated in the following
8281  * firmware version. So the workaround in software driver is needed. It needs
8282  * to modify the initial values of 3 internal only registers for both X710 and
8283  * XL710. Note that the values for X710 or XL710 could be different, and the
8284  * workaround can be removed when it is fixed in firmware in the future.
8285  */
8286
8287 /* For both X710 and XL710 */
8288 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8289 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8290
8291 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8292 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8293
8294 /* For X710 */
8295 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8296 /* For XL710 */
8297 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8298 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8299
8300 static int
8301 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8302 {
8303         enum i40e_status_code status;
8304         struct i40e_aq_get_phy_abilities_resp phy_ab;
8305         int ret = -ENOTSUP;
8306
8307         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8308                                               NULL);
8309
8310         if (status)
8311                 return ret;
8312
8313         return 0;
8314 }
8315
8316
8317 static void
8318 i40e_configure_registers(struct i40e_hw *hw)
8319 {
8320         static struct {
8321                 uint32_t addr;
8322                 uint64_t val;
8323         } reg_table[] = {
8324                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8325                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8326                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8327         };
8328         uint64_t reg;
8329         uint32_t i;
8330         int ret;
8331
8332         for (i = 0; i < RTE_DIM(reg_table); i++) {
8333                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8334                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8335                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8336                                 reg_table[i].val =
8337                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8338                         else /* For X710 */
8339                                 reg_table[i].val =
8340                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8341                 }
8342
8343                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8344                                                         &reg, NULL);
8345                 if (ret < 0) {
8346                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8347                                                         reg_table[i].addr);
8348                         break;
8349                 }
8350                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8351                                                 reg_table[i].addr, reg);
8352                 if (reg == reg_table[i].val)
8353                         continue;
8354
8355                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8356                                                 reg_table[i].val, NULL);
8357                 if (ret < 0) {
8358                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8359                                 "address of 0x%"PRIx32, reg_table[i].val,
8360                                                         reg_table[i].addr);
8361                         break;
8362                 }
8363                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8364                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8365         }
8366 }
8367
8368 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8369 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8370 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8371 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8372 static int
8373 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8374 {
8375         uint32_t reg;
8376         int ret;
8377
8378         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8379                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8380                 return -EINVAL;
8381         }
8382
8383         /* Configure for double VLAN RX stripping */
8384         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8385         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8386                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8387                 ret = i40e_aq_debug_write_register(hw,
8388                                                    I40E_VSI_TSR(vsi->vsi_id),
8389                                                    reg, NULL);
8390                 if (ret < 0) {
8391                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8392                                     vsi->vsi_id);
8393                         return I40E_ERR_CONFIG;
8394                 }
8395         }
8396
8397         /* Configure for double VLAN TX insertion */
8398         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8399         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8400                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8401                 ret = i40e_aq_debug_write_register(hw,
8402                                                    I40E_VSI_L2TAGSTXVALID(
8403                                                    vsi->vsi_id), reg, NULL);
8404                 if (ret < 0) {
8405                         PMD_DRV_LOG(ERR, "Failed to update "
8406                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8407                         return I40E_ERR_CONFIG;
8408                 }
8409         }
8410
8411         return 0;
8412 }
8413
8414 /**
8415  * i40e_aq_add_mirror_rule
8416  * @hw: pointer to the hardware structure
8417  * @seid: VEB seid to add mirror rule to
8418  * @dst_id: destination vsi seid
8419  * @entries: Buffer which contains the entities to be mirrored
8420  * @count: number of entities contained in the buffer
8421  * @rule_id:the rule_id of the rule to be added
8422  *
8423  * Add a mirror rule for a given veb.
8424  *
8425  **/
8426 static enum i40e_status_code
8427 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8428                         uint16_t seid, uint16_t dst_id,
8429                         uint16_t rule_type, uint16_t *entries,
8430                         uint16_t count, uint16_t *rule_id)
8431 {
8432         struct i40e_aq_desc desc;
8433         struct i40e_aqc_add_delete_mirror_rule cmd;
8434         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8435                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8436                 &desc.params.raw;
8437         uint16_t buff_len;
8438         enum i40e_status_code status;
8439
8440         i40e_fill_default_direct_cmd_desc(&desc,
8441                                           i40e_aqc_opc_add_mirror_rule);
8442         memset(&cmd, 0, sizeof(cmd));
8443
8444         buff_len = sizeof(uint16_t) * count;
8445         desc.datalen = rte_cpu_to_le_16(buff_len);
8446         if (buff_len > 0)
8447                 desc.flags |= rte_cpu_to_le_16(
8448                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8449         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8450                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8451         cmd.num_entries = rte_cpu_to_le_16(count);
8452         cmd.seid = rte_cpu_to_le_16(seid);
8453         cmd.destination = rte_cpu_to_le_16(dst_id);
8454
8455         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8456         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8457         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8458                          "rule_id = %u"
8459                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8460                          hw->aq.asq_last_status, resp->rule_id,
8461                          resp->mirror_rules_used, resp->mirror_rules_free);
8462         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8463
8464         return status;
8465 }
8466
8467 /**
8468  * i40e_aq_del_mirror_rule
8469  * @hw: pointer to the hardware structure
8470  * @seid: VEB seid to add mirror rule to
8471  * @entries: Buffer which contains the entities to be mirrored
8472  * @count: number of entities contained in the buffer
8473  * @rule_id:the rule_id of the rule to be delete
8474  *
8475  * Delete a mirror rule for a given veb.
8476  *
8477  **/
8478 static enum i40e_status_code
8479 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8480                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8481                 uint16_t count, uint16_t rule_id)
8482 {
8483         struct i40e_aq_desc desc;
8484         struct i40e_aqc_add_delete_mirror_rule cmd;
8485         uint16_t buff_len = 0;
8486         enum i40e_status_code status;
8487         void *buff = NULL;
8488
8489         i40e_fill_default_direct_cmd_desc(&desc,
8490                                           i40e_aqc_opc_delete_mirror_rule);
8491         memset(&cmd, 0, sizeof(cmd));
8492         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8493                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8494                                                           I40E_AQ_FLAG_RD));
8495                 cmd.num_entries = count;
8496                 buff_len = sizeof(uint16_t) * count;
8497                 desc.datalen = rte_cpu_to_le_16(buff_len);
8498                 buff = (void *)entries;
8499         } else
8500                 /* rule id is filled in destination field for deleting mirror rule */
8501                 cmd.destination = rte_cpu_to_le_16(rule_id);
8502
8503         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8504                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8505         cmd.seid = rte_cpu_to_le_16(seid);
8506
8507         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8508         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8509
8510         return status;
8511 }
8512
8513 /**
8514  * i40e_mirror_rule_set
8515  * @dev: pointer to the hardware structure
8516  * @mirror_conf: mirror rule info
8517  * @sw_id: mirror rule's sw_id
8518  * @on: enable/disable
8519  *
8520  * set a mirror rule.
8521  *
8522  **/
8523 static int
8524 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8525                         struct rte_eth_mirror_conf *mirror_conf,
8526                         uint8_t sw_id, uint8_t on)
8527 {
8528         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8529         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8530         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8531         struct i40e_mirror_rule *parent = NULL;
8532         uint16_t seid, dst_seid, rule_id;
8533         uint16_t i, j = 0;
8534         int ret;
8535
8536         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8537
8538         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8539                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8540                         " without veb or vfs.");
8541                 return -ENOSYS;
8542         }
8543         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8544                 PMD_DRV_LOG(ERR, "mirror table is full.");
8545                 return -ENOSPC;
8546         }
8547         if (mirror_conf->dst_pool > pf->vf_num) {
8548                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8549                                  mirror_conf->dst_pool);
8550                 return -EINVAL;
8551         }
8552
8553         seid = pf->main_vsi->veb->seid;
8554
8555         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8556                 if (sw_id <= it->index) {
8557                         mirr_rule = it;
8558                         break;
8559                 }
8560                 parent = it;
8561         }
8562         if (mirr_rule && sw_id == mirr_rule->index) {
8563                 if (on) {
8564                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8565                         return -EEXIST;
8566                 } else {
8567                         ret = i40e_aq_del_mirror_rule(hw, seid,
8568                                         mirr_rule->rule_type,
8569                                         mirr_rule->entries,
8570                                         mirr_rule->num_entries, mirr_rule->id);
8571                         if (ret < 0) {
8572                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8573                                                    " ret = %d, aq_err = %d.",
8574                                                    ret, hw->aq.asq_last_status);
8575                                 return -ENOSYS;
8576                         }
8577                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8578                         rte_free(mirr_rule);
8579                         pf->nb_mirror_rule--;
8580                         return 0;
8581                 }
8582         } else if (!on) {
8583                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8584                 return -ENOENT;
8585         }
8586
8587         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8588                                 sizeof(struct i40e_mirror_rule) , 0);
8589         if (!mirr_rule) {
8590                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8591                 return I40E_ERR_NO_MEMORY;
8592         }
8593         switch (mirror_conf->rule_type) {
8594         case ETH_MIRROR_VLAN:
8595                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8596                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8597                                 mirr_rule->entries[j] =
8598                                         mirror_conf->vlan.vlan_id[i];
8599                                 j++;
8600                         }
8601                 }
8602                 if (j == 0) {
8603                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8604                         rte_free(mirr_rule);
8605                         return -EINVAL;
8606                 }
8607                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8608                 break;
8609         case ETH_MIRROR_VIRTUAL_POOL_UP:
8610         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8611                 /* check if the specified pool bit is out of range */
8612                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8613                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8614                         rte_free(mirr_rule);
8615                         return -EINVAL;
8616                 }
8617                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8618                         if (mirror_conf->pool_mask & (1ULL << i)) {
8619                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8620                                 j++;
8621                         }
8622                 }
8623                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8624                         /* add pf vsi to entries */
8625                         mirr_rule->entries[j] = pf->main_vsi_seid;
8626                         j++;
8627                 }
8628                 if (j == 0) {
8629                         PMD_DRV_LOG(ERR, "pool is not specified.");
8630                         rte_free(mirr_rule);
8631                         return -EINVAL;
8632                 }
8633                 /* egress and ingress in aq commands means from switch but not port */
8634                 mirr_rule->rule_type =
8635                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8636                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8637                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8638                 break;
8639         case ETH_MIRROR_UPLINK_PORT:
8640                 /* egress and ingress in aq commands means from switch but not port*/
8641                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8642                 break;
8643         case ETH_MIRROR_DOWNLINK_PORT:
8644                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8645                 break;
8646         default:
8647                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8648                         mirror_conf->rule_type);
8649                 rte_free(mirr_rule);
8650                 return -EINVAL;
8651         }
8652
8653         /* If the dst_pool is equal to vf_num, consider it as PF */
8654         if (mirror_conf->dst_pool == pf->vf_num)
8655                 dst_seid = pf->main_vsi_seid;
8656         else
8657                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8658
8659         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8660                                       mirr_rule->rule_type, mirr_rule->entries,
8661                                       j, &rule_id);
8662         if (ret < 0) {
8663                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8664                                    " ret = %d, aq_err = %d.",
8665                                    ret, hw->aq.asq_last_status);
8666                 rte_free(mirr_rule);
8667                 return -ENOSYS;
8668         }
8669
8670         mirr_rule->index = sw_id;
8671         mirr_rule->num_entries = j;
8672         mirr_rule->id = rule_id;
8673         mirr_rule->dst_vsi_seid = dst_seid;
8674
8675         if (parent)
8676                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8677         else
8678                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8679
8680         pf->nb_mirror_rule++;
8681         return 0;
8682 }
8683
8684 /**
8685  * i40e_mirror_rule_reset
8686  * @dev: pointer to the device
8687  * @sw_id: mirror rule's sw_id
8688  *
8689  * reset a mirror rule.
8690  *
8691  **/
8692 static int
8693 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8694 {
8695         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8696         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8697         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8698         uint16_t seid;
8699         int ret;
8700
8701         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8702
8703         seid = pf->main_vsi->veb->seid;
8704
8705         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8706                 if (sw_id == it->index) {
8707                         mirr_rule = it;
8708                         break;
8709                 }
8710         }
8711         if (mirr_rule) {
8712                 ret = i40e_aq_del_mirror_rule(hw, seid,
8713                                 mirr_rule->rule_type,
8714                                 mirr_rule->entries,
8715                                 mirr_rule->num_entries, mirr_rule->id);
8716                 if (ret < 0) {
8717                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8718                                            " status = %d, aq_err = %d.",
8719                                            ret, hw->aq.asq_last_status);
8720                         return -ENOSYS;
8721                 }
8722                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8723                 rte_free(mirr_rule);
8724                 pf->nb_mirror_rule--;
8725         } else {
8726                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8727                 return -ENOENT;
8728         }
8729         return 0;
8730 }
8731
8732 static uint64_t
8733 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8734 {
8735         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8736         uint64_t systim_cycles;
8737
8738         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8739         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8740                         << 32;
8741
8742         return systim_cycles;
8743 }
8744
8745 static uint64_t
8746 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8747 {
8748         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8749         uint64_t rx_tstamp;
8750
8751         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8752         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8753                         << 32;
8754
8755         return rx_tstamp;
8756 }
8757
8758 static uint64_t
8759 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8760 {
8761         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8762         uint64_t tx_tstamp;
8763
8764         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8765         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8766                         << 32;
8767
8768         return tx_tstamp;
8769 }
8770
8771 static void
8772 i40e_start_timecounters(struct rte_eth_dev *dev)
8773 {
8774         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8775         struct i40e_adapter *adapter =
8776                         (struct i40e_adapter *)dev->data->dev_private;
8777         struct rte_eth_link link;
8778         uint32_t tsync_inc_l;
8779         uint32_t tsync_inc_h;
8780
8781         /* Get current link speed. */
8782         memset(&link, 0, sizeof(link));
8783         i40e_dev_link_update(dev, 1);
8784         rte_i40e_dev_atomic_read_link_status(dev, &link);
8785
8786         switch (link.link_speed) {
8787         case ETH_SPEED_NUM_40G:
8788                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8789                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8790                 break;
8791         case ETH_SPEED_NUM_10G:
8792                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8793                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8794                 break;
8795         case ETH_SPEED_NUM_1G:
8796                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8797                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8798                 break;
8799         default:
8800                 tsync_inc_l = 0x0;
8801                 tsync_inc_h = 0x0;
8802         }
8803
8804         /* Set the timesync increment value. */
8805         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8806         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8807
8808         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8809         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8810         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8811
8812         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8813         adapter->systime_tc.cc_shift = 0;
8814         adapter->systime_tc.nsec_mask = 0;
8815
8816         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8817         adapter->rx_tstamp_tc.cc_shift = 0;
8818         adapter->rx_tstamp_tc.nsec_mask = 0;
8819
8820         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8821         adapter->tx_tstamp_tc.cc_shift = 0;
8822         adapter->tx_tstamp_tc.nsec_mask = 0;
8823 }
8824
8825 static int
8826 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8827 {
8828         struct i40e_adapter *adapter =
8829                         (struct i40e_adapter *)dev->data->dev_private;
8830
8831         adapter->systime_tc.nsec += delta;
8832         adapter->rx_tstamp_tc.nsec += delta;
8833         adapter->tx_tstamp_tc.nsec += delta;
8834
8835         return 0;
8836 }
8837
8838 static int
8839 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8840 {
8841         uint64_t ns;
8842         struct i40e_adapter *adapter =
8843                         (struct i40e_adapter *)dev->data->dev_private;
8844
8845         ns = rte_timespec_to_ns(ts);
8846
8847         /* Set the timecounters to a new value. */
8848         adapter->systime_tc.nsec = ns;
8849         adapter->rx_tstamp_tc.nsec = ns;
8850         adapter->tx_tstamp_tc.nsec = ns;
8851
8852         return 0;
8853 }
8854
8855 static int
8856 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8857 {
8858         uint64_t ns, systime_cycles;
8859         struct i40e_adapter *adapter =
8860                         (struct i40e_adapter *)dev->data->dev_private;
8861
8862         systime_cycles = i40e_read_systime_cyclecounter(dev);
8863         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8864         *ts = rte_ns_to_timespec(ns);
8865
8866         return 0;
8867 }
8868
8869 static int
8870 i40e_timesync_enable(struct rte_eth_dev *dev)
8871 {
8872         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8873         uint32_t tsync_ctl_l;
8874         uint32_t tsync_ctl_h;
8875
8876         /* Stop the timesync system time. */
8877         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8878         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8879         /* Reset the timesync system time value. */
8880         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8881         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8882
8883         i40e_start_timecounters(dev);
8884
8885         /* Clear timesync registers. */
8886         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8887         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8888         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8889         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8890         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8891         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8892
8893         /* Enable timestamping of PTP packets. */
8894         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8895         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8896
8897         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8898         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8899         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8900
8901         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8902         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8903
8904         return 0;
8905 }
8906
8907 static int
8908 i40e_timesync_disable(struct rte_eth_dev *dev)
8909 {
8910         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8911         uint32_t tsync_ctl_l;
8912         uint32_t tsync_ctl_h;
8913
8914         /* Disable timestamping of transmitted PTP packets. */
8915         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8916         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8917
8918         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8919         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8920
8921         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8922         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8923
8924         /* Reset the timesync increment value. */
8925         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8926         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8927
8928         return 0;
8929 }
8930
8931 static int
8932 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8933                                 struct timespec *timestamp, uint32_t flags)
8934 {
8935         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8936         struct i40e_adapter *adapter =
8937                 (struct i40e_adapter *)dev->data->dev_private;
8938
8939         uint32_t sync_status;
8940         uint32_t index = flags & 0x03;
8941         uint64_t rx_tstamp_cycles;
8942         uint64_t ns;
8943
8944         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8945         if ((sync_status & (1 << index)) == 0)
8946                 return -EINVAL;
8947
8948         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8949         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8950         *timestamp = rte_ns_to_timespec(ns);
8951
8952         return 0;
8953 }
8954
8955 static int
8956 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8957                                 struct timespec *timestamp)
8958 {
8959         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8960         struct i40e_adapter *adapter =
8961                 (struct i40e_adapter *)dev->data->dev_private;
8962
8963         uint32_t sync_status;
8964         uint64_t tx_tstamp_cycles;
8965         uint64_t ns;
8966
8967         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8968         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8969                 return -EINVAL;
8970
8971         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8972         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8973         *timestamp = rte_ns_to_timespec(ns);
8974
8975         return 0;
8976 }
8977
8978 /*
8979  * i40e_parse_dcb_configure - parse dcb configure from user
8980  * @dev: the device being configured
8981  * @dcb_cfg: pointer of the result of parse
8982  * @*tc_map: bit map of enabled traffic classes
8983  *
8984  * Returns 0 on success, negative value on failure
8985  */
8986 static int
8987 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8988                          struct i40e_dcbx_config *dcb_cfg,
8989                          uint8_t *tc_map)
8990 {
8991         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8992         uint8_t i, tc_bw, bw_lf;
8993
8994         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8995
8996         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8997         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8998                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8999                 return -EINVAL;
9000         }
9001
9002         /* assume each tc has the same bw */
9003         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9004         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9005                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9006         /* to ensure the sum of tcbw is equal to 100 */
9007         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9008         for (i = 0; i < bw_lf; i++)
9009                 dcb_cfg->etscfg.tcbwtable[i]++;
9010
9011         /* assume each tc has the same Transmission Selection Algorithm */
9012         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9013                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9014
9015         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9016                 dcb_cfg->etscfg.prioritytable[i] =
9017                                 dcb_rx_conf->dcb_tc[i];
9018
9019         /* FW needs one App to configure HW */
9020         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9021         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9022         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9023         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9024
9025         if (dcb_rx_conf->nb_tcs == 0)
9026                 *tc_map = 1; /* tc0 only */
9027         else
9028                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9029
9030         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9031                 dcb_cfg->pfc.willing = 0;
9032                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9033                 dcb_cfg->pfc.pfcenable = *tc_map;
9034         }
9035         return 0;
9036 }
9037
9038
9039 static enum i40e_status_code
9040 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9041                               struct i40e_aqc_vsi_properties_data *info,
9042                               uint8_t enabled_tcmap)
9043 {
9044         enum i40e_status_code ret;
9045         int i, total_tc = 0;
9046         uint16_t qpnum_per_tc, bsf, qp_idx;
9047         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9048         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9049         uint16_t used_queues;
9050
9051         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9052         if (ret != I40E_SUCCESS)
9053                 return ret;
9054
9055         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9056                 if (enabled_tcmap & (1 << i))
9057                         total_tc++;
9058         }
9059         if (total_tc == 0)
9060                 total_tc = 1;
9061         vsi->enabled_tc = enabled_tcmap;
9062
9063         /* different VSI has different queues assigned */
9064         if (vsi->type == I40E_VSI_MAIN)
9065                 used_queues = dev_data->nb_rx_queues -
9066                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9067         else if (vsi->type == I40E_VSI_VMDQ2)
9068                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9069         else {
9070                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9071                 return I40E_ERR_NO_AVAILABLE_VSI;
9072         }
9073
9074         qpnum_per_tc = used_queues / total_tc;
9075         /* Number of queues per enabled TC */
9076         if (qpnum_per_tc == 0) {
9077                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9078                 return I40E_ERR_INVALID_QP_ID;
9079         }
9080         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9081                                 I40E_MAX_Q_PER_TC);
9082         bsf = rte_bsf32(qpnum_per_tc);
9083
9084         /**
9085          * Configure TC and queue mapping parameters, for enabled TC,
9086          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9087          * default queue will serve it.
9088          */
9089         qp_idx = 0;
9090         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9091                 if (vsi->enabled_tc & (1 << i)) {
9092                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9093                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9094                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9095                         qp_idx += qpnum_per_tc;
9096                 } else
9097                         info->tc_mapping[i] = 0;
9098         }
9099
9100         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9101         if (vsi->type == I40E_VSI_SRIOV) {
9102                 info->mapping_flags |=
9103                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9104                 for (i = 0; i < vsi->nb_qps; i++)
9105                         info->queue_mapping[i] =
9106                                 rte_cpu_to_le_16(vsi->base_queue + i);
9107         } else {
9108                 info->mapping_flags |=
9109                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9110                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9111         }
9112         info->valid_sections |=
9113                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9114
9115         return I40E_SUCCESS;
9116 }
9117
9118 /*
9119  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9120  * @veb: VEB to be configured
9121  * @tc_map: enabled TC bitmap
9122  *
9123  * Returns 0 on success, negative value on failure
9124  */
9125 static enum i40e_status_code
9126 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9127 {
9128         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9129         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9130         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9131         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9132         enum i40e_status_code ret = I40E_SUCCESS;
9133         int i;
9134         uint32_t bw_max;
9135
9136         /* Check if enabled_tc is same as existing or new TCs */
9137         if (veb->enabled_tc == tc_map)
9138                 return ret;
9139
9140         /* configure tc bandwidth */
9141         memset(&veb_bw, 0, sizeof(veb_bw));
9142         veb_bw.tc_valid_bits = tc_map;
9143         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9144         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9145                 if (tc_map & BIT_ULL(i))
9146                         veb_bw.tc_bw_share_credits[i] = 1;
9147         }
9148         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9149                                                    &veb_bw, NULL);
9150         if (ret) {
9151                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9152                                   " per TC failed = %d",
9153                                   hw->aq.asq_last_status);
9154                 return ret;
9155         }
9156
9157         memset(&ets_query, 0, sizeof(ets_query));
9158         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9159                                                    &ets_query, NULL);
9160         if (ret != I40E_SUCCESS) {
9161                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9162                                  " configuration %u", hw->aq.asq_last_status);
9163                 return ret;
9164         }
9165         memset(&bw_query, 0, sizeof(bw_query));
9166         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9167                                                   &bw_query, NULL);
9168         if (ret != I40E_SUCCESS) {
9169                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9170                                  " configuration %u", hw->aq.asq_last_status);
9171                 return ret;
9172         }
9173
9174         /* store and print out BW info */
9175         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9176         veb->bw_info.bw_max = ets_query.tc_bw_max;
9177         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9178         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9179         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9180                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9181                      I40E_16_BIT_WIDTH);
9182         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9183                 veb->bw_info.bw_ets_share_credits[i] =
9184                                 bw_query.tc_bw_share_credits[i];
9185                 veb->bw_info.bw_ets_credits[i] =
9186                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9187                 /* 4 bits per TC, 4th bit is reserved */
9188                 veb->bw_info.bw_ets_max[i] =
9189                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9190                                   RTE_LEN2MASK(3, uint8_t));
9191                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9192                             veb->bw_info.bw_ets_share_credits[i]);
9193                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9194                             veb->bw_info.bw_ets_credits[i]);
9195                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9196                             veb->bw_info.bw_ets_max[i]);
9197         }
9198
9199         veb->enabled_tc = tc_map;
9200
9201         return ret;
9202 }
9203
9204
9205 /*
9206  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9207  * @vsi: VSI to be configured
9208  * @tc_map: enabled TC bitmap
9209  *
9210  * Returns 0 on success, negative value on failure
9211  */
9212 static enum i40e_status_code
9213 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9214 {
9215         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9216         struct i40e_vsi_context ctxt;
9217         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9218         enum i40e_status_code ret = I40E_SUCCESS;
9219         int i;
9220
9221         /* Check if enabled_tc is same as existing or new TCs */
9222         if (vsi->enabled_tc == tc_map)
9223                 return ret;
9224
9225         /* configure tc bandwidth */
9226         memset(&bw_data, 0, sizeof(bw_data));
9227         bw_data.tc_valid_bits = tc_map;
9228         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9229         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9230                 if (tc_map & BIT_ULL(i))
9231                         bw_data.tc_bw_credits[i] = 1;
9232         }
9233         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9234         if (ret) {
9235                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9236                         " per TC failed = %d",
9237                         hw->aq.asq_last_status);
9238                 goto out;
9239         }
9240         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9241                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9242
9243         /* Update Queue Pairs Mapping for currently enabled UPs */
9244         ctxt.seid = vsi->seid;
9245         ctxt.pf_num = hw->pf_id;
9246         ctxt.vf_num = 0;
9247         ctxt.uplink_seid = vsi->uplink_seid;
9248         ctxt.info = vsi->info;
9249         i40e_get_cap(hw);
9250         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9251         if (ret)
9252                 goto out;
9253
9254         /* Update the VSI after updating the VSI queue-mapping information */
9255         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9256         if (ret) {
9257                 PMD_INIT_LOG(ERR, "Failed to configure "
9258                             "TC queue mapping = %d",
9259                             hw->aq.asq_last_status);
9260                 goto out;
9261         }
9262         /* update the local VSI info with updated queue map */
9263         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9264                                         sizeof(vsi->info.tc_mapping));
9265         (void)rte_memcpy(&vsi->info.queue_mapping,
9266                         &ctxt.info.queue_mapping,
9267                 sizeof(vsi->info.queue_mapping));
9268         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9269         vsi->info.valid_sections = 0;
9270
9271         /* query and update current VSI BW information */
9272         ret = i40e_vsi_get_bw_config(vsi);
9273         if (ret) {
9274                 PMD_INIT_LOG(ERR,
9275                          "Failed updating vsi bw info, err %s aq_err %s",
9276                          i40e_stat_str(hw, ret),
9277                          i40e_aq_str(hw, hw->aq.asq_last_status));
9278                 goto out;
9279         }
9280
9281         vsi->enabled_tc = tc_map;
9282
9283 out:
9284         return ret;
9285 }
9286
9287 /*
9288  * i40e_dcb_hw_configure - program the dcb setting to hw
9289  * @pf: pf the configuration is taken on
9290  * @new_cfg: new configuration
9291  * @tc_map: enabled TC bitmap
9292  *
9293  * Returns 0 on success, negative value on failure
9294  */
9295 static enum i40e_status_code
9296 i40e_dcb_hw_configure(struct i40e_pf *pf,
9297                       struct i40e_dcbx_config *new_cfg,
9298                       uint8_t tc_map)
9299 {
9300         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9301         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9302         struct i40e_vsi *main_vsi = pf->main_vsi;
9303         struct i40e_vsi_list *vsi_list;
9304         enum i40e_status_code ret;
9305         int i;
9306         uint32_t val;
9307
9308         /* Use the FW API if FW > v4.4*/
9309         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9310               (hw->aq.fw_maj_ver >= 5))) {
9311                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9312                                   " to configure DCB");
9313                 return I40E_ERR_FIRMWARE_API_VERSION;
9314         }
9315
9316         /* Check if need reconfiguration */
9317         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9318                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9319                 return I40E_SUCCESS;
9320         }
9321
9322         /* Copy the new config to the current config */
9323         *old_cfg = *new_cfg;
9324         old_cfg->etsrec = old_cfg->etscfg;
9325         ret = i40e_set_dcb_config(hw);
9326         if (ret) {
9327                 PMD_INIT_LOG(ERR,
9328                          "Set DCB Config failed, err %s aq_err %s\n",
9329                          i40e_stat_str(hw, ret),
9330                          i40e_aq_str(hw, hw->aq.asq_last_status));
9331                 return ret;
9332         }
9333         /* set receive Arbiter to RR mode and ETS scheme by default */
9334         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9335                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9336                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9337                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9338                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9339                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9340                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9341                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9342                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9343                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9344                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9345                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9346                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9347         }
9348         /* get local mib to check whether it is configured correctly */
9349         /* IEEE mode */
9350         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9351         /* Get Local DCB Config */
9352         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9353                                      &hw->local_dcbx_config);
9354
9355         /* if Veb is created, need to update TC of it at first */
9356         if (main_vsi->veb) {
9357                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9358                 if (ret)
9359                         PMD_INIT_LOG(WARNING,
9360                                  "Failed configuring TC for VEB seid=%d\n",
9361                                  main_vsi->veb->seid);
9362         }
9363         /* Update each VSI */
9364         i40e_vsi_config_tc(main_vsi, tc_map);
9365         if (main_vsi->veb) {
9366                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9367                         /* Beside main VSI and VMDQ VSIs, only enable default
9368                          * TC for other VSIs
9369                          */
9370                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9371                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9372                                                          tc_map);
9373                         else
9374                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9375                                                          I40E_DEFAULT_TCMAP);
9376                         if (ret)
9377                                 PMD_INIT_LOG(WARNING,
9378                                          "Failed configuring TC for VSI seid=%d\n",
9379                                          vsi_list->vsi->seid);
9380                         /* continue */
9381                 }
9382         }
9383         return I40E_SUCCESS;
9384 }
9385
9386 /*
9387  * i40e_dcb_init_configure - initial dcb config
9388  * @dev: device being configured
9389  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9390  *
9391  * Returns 0 on success, negative value on failure
9392  */
9393 static int
9394 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9395 {
9396         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9397         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9398         int ret = 0;
9399
9400         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9401                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9402                 return -ENOTSUP;
9403         }
9404
9405         /* DCB initialization:
9406          * Update DCB configuration from the Firmware and configure
9407          * LLDP MIB change event.
9408          */
9409         if (sw_dcb == TRUE) {
9410                 ret = i40e_init_dcb(hw);
9411                 /* If lldp agent is stopped, the return value from
9412                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9413                  * adminq status. Otherwise, it should return success.
9414                  */
9415                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9416                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9417                         memset(&hw->local_dcbx_config, 0,
9418                                 sizeof(struct i40e_dcbx_config));
9419                         /* set dcb default configuration */
9420                         hw->local_dcbx_config.etscfg.willing = 0;
9421                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9422                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9423                         hw->local_dcbx_config.etscfg.tsatable[0] =
9424                                                 I40E_IEEE_TSA_ETS;
9425                         hw->local_dcbx_config.etsrec =
9426                                 hw->local_dcbx_config.etscfg;
9427                         hw->local_dcbx_config.pfc.willing = 0;
9428                         hw->local_dcbx_config.pfc.pfccap =
9429                                                 I40E_MAX_TRAFFIC_CLASS;
9430                         /* FW needs one App to configure HW */
9431                         hw->local_dcbx_config.numapps = 1;
9432                         hw->local_dcbx_config.app[0].selector =
9433                                                 I40E_APP_SEL_ETHTYPE;
9434                         hw->local_dcbx_config.app[0].priority = 3;
9435                         hw->local_dcbx_config.app[0].protocolid =
9436                                                 I40E_APP_PROTOID_FCOE;
9437                         ret = i40e_set_dcb_config(hw);
9438                         if (ret) {
9439                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9440                                         " err = %d, aq_err = %d.", ret,
9441                                           hw->aq.asq_last_status);
9442                                 return -ENOSYS;
9443                         }
9444                 } else {
9445                         PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9446                                           " err = %d, aq_err = %d.", ret,
9447                                           hw->aq.asq_last_status);
9448                         return -ENOTSUP;
9449                 }
9450         } else {
9451                 ret = i40e_aq_start_lldp(hw, NULL);
9452                 if (ret != I40E_SUCCESS)
9453                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9454
9455                 ret = i40e_init_dcb(hw);
9456                 if (!ret) {
9457                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9458                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9459                                                   " DCBX offload.");
9460                                 return -ENOTSUP;
9461                         }
9462                 } else {
9463                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9464                                           " aq_err = %d.", ret,
9465                                           hw->aq.asq_last_status);
9466                         return -ENOTSUP;
9467                 }
9468         }
9469         return 0;
9470 }
9471
9472 /*
9473  * i40e_dcb_setup - setup dcb related config
9474  * @dev: device being configured
9475  *
9476  * Returns 0 on success, negative value on failure
9477  */
9478 static int
9479 i40e_dcb_setup(struct rte_eth_dev *dev)
9480 {
9481         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9482         struct i40e_dcbx_config dcb_cfg;
9483         uint8_t tc_map = 0;
9484         int ret = 0;
9485
9486         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9487                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9488                 return -ENOTSUP;
9489         }
9490
9491         if (pf->vf_num != 0)
9492                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9493
9494         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9495         if (ret) {
9496                 PMD_INIT_LOG(ERR, "invalid dcb config");
9497                 return -EINVAL;
9498         }
9499         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9500         if (ret) {
9501                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9502                 return -ENOSYS;
9503         }
9504
9505         return 0;
9506 }
9507
9508 static int
9509 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9510                       struct rte_eth_dcb_info *dcb_info)
9511 {
9512         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9513         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9514         struct i40e_vsi *vsi = pf->main_vsi;
9515         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9516         uint16_t bsf, tc_mapping;
9517         int i, j = 0;
9518
9519         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9520                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9521         else
9522                 dcb_info->nb_tcs = 1;
9523         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9524                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9525         for (i = 0; i < dcb_info->nb_tcs; i++)
9526                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9527
9528         /* get queue mapping if vmdq is disabled */
9529         if (!pf->nb_cfg_vmdq_vsi) {
9530                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9531                         if (!(vsi->enabled_tc & (1 << i)))
9532                                 continue;
9533                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9534                         dcb_info->tc_queue.tc_rxq[j][i].base =
9535                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9536                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9537                         dcb_info->tc_queue.tc_txq[j][i].base =
9538                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9539                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9540                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9541                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9542                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9543                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9544                 }
9545                 return 0;
9546         }
9547
9548         /* get queue mapping if vmdq is enabled */
9549         do {
9550                 vsi = pf->vmdq[j].vsi;
9551                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9552                         if (!(vsi->enabled_tc & (1 << i)))
9553                                 continue;
9554                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9555                         dcb_info->tc_queue.tc_rxq[j][i].base =
9556                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9557                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9558                         dcb_info->tc_queue.tc_txq[j][i].base =
9559                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9560                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9561                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9562                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9563                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9564                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9565                 }
9566                 j++;
9567         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9568         return 0;
9569 }
9570
9571 static int
9572 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9573 {
9574         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9575         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
9576         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9577         uint16_t interval =
9578                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9579         uint16_t msix_intr;
9580
9581         msix_intr = intr_handle->intr_vec[queue_id];
9582         if (msix_intr == I40E_MISC_VEC_ID)
9583                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9584                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9585                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9586                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9587                                (interval <<
9588                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9589         else
9590                 I40E_WRITE_REG(hw,
9591                                I40E_PFINT_DYN_CTLN(msix_intr -
9592                                                    I40E_RX_VEC_START),
9593                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9594                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9595                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9596                                (interval <<
9597                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9598
9599         I40E_WRITE_FLUSH(hw);
9600         rte_intr_enable(&pci_dev->intr_handle);
9601
9602         return 0;
9603 }
9604
9605 static int
9606 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9607 {
9608         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9609         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
9610         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9611         uint16_t msix_intr;
9612
9613         msix_intr = intr_handle->intr_vec[queue_id];
9614         if (msix_intr == I40E_MISC_VEC_ID)
9615                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9616         else
9617                 I40E_WRITE_REG(hw,
9618                                I40E_PFINT_DYN_CTLN(msix_intr -
9619                                                    I40E_RX_VEC_START),
9620                                0);
9621         I40E_WRITE_FLUSH(hw);
9622
9623         return 0;
9624 }
9625
9626 static int i40e_get_regs(struct rte_eth_dev *dev,
9627                          struct rte_dev_reg_info *regs)
9628 {
9629         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9630         uint32_t *ptr_data = regs->data;
9631         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9632         const struct i40e_reg_info *reg_info;
9633
9634         if (ptr_data == NULL) {
9635                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9636                 regs->width = sizeof(uint32_t);
9637                 return 0;
9638         }
9639
9640         /* The first few registers have to be read using AQ operations */
9641         reg_idx = 0;
9642         while (i40e_regs_adminq[reg_idx].name) {
9643                 reg_info = &i40e_regs_adminq[reg_idx++];
9644                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9645                         for (arr_idx2 = 0;
9646                                         arr_idx2 <= reg_info->count2;
9647                                         arr_idx2++) {
9648                                 reg_offset = arr_idx * reg_info->stride1 +
9649                                         arr_idx2 * reg_info->stride2;
9650                                 reg_offset += reg_info->base_addr;
9651                                 ptr_data[reg_offset >> 2] =
9652                                         i40e_read_rx_ctl(hw, reg_offset);
9653                         }
9654         }
9655
9656         /* The remaining registers can be read using primitives */
9657         reg_idx = 0;
9658         while (i40e_regs_others[reg_idx].name) {
9659                 reg_info = &i40e_regs_others[reg_idx++];
9660                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9661                         for (arr_idx2 = 0;
9662                                         arr_idx2 <= reg_info->count2;
9663                                         arr_idx2++) {
9664                                 reg_offset = arr_idx * reg_info->stride1 +
9665                                         arr_idx2 * reg_info->stride2;
9666                                 reg_offset += reg_info->base_addr;
9667                                 ptr_data[reg_offset >> 2] =
9668                                         I40E_READ_REG(hw, reg_offset);
9669                         }
9670         }
9671
9672         return 0;
9673 }
9674
9675 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9676 {
9677         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9678
9679         /* Convert word count to byte count */
9680         return hw->nvm.sr_size << 1;
9681 }
9682
9683 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9684                            struct rte_dev_eeprom_info *eeprom)
9685 {
9686         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9687         uint16_t *data = eeprom->data;
9688         uint16_t offset, length, cnt_words;
9689         int ret_code;
9690
9691         offset = eeprom->offset >> 1;
9692         length = eeprom->length >> 1;
9693         cnt_words = length;
9694
9695         if (offset > hw->nvm.sr_size ||
9696                 offset + length > hw->nvm.sr_size) {
9697                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9698                 return -EINVAL;
9699         }
9700
9701         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9702
9703         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9704         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9705                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9706                 return -EIO;
9707         }
9708
9709         return 0;
9710 }
9711
9712 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9713                                       struct ether_addr *mac_addr)
9714 {
9715         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9716
9717         if (!is_valid_assigned_ether_addr(mac_addr)) {
9718                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9719                 return;
9720         }
9721
9722         /* Flags: 0x3 updates port address */
9723         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9724 }
9725
9726 static int
9727 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9728 {
9729         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9730         struct rte_eth_dev_data *dev_data = pf->dev_data;
9731         uint32_t frame_size = mtu + ETHER_HDR_LEN
9732                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9733         int ret = 0;
9734
9735         /* check if mtu is within the allowed range */
9736         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9737                 return -EINVAL;
9738
9739         /* mtu setting is forbidden if port is start */
9740         if (dev_data->dev_started) {
9741                 PMD_DRV_LOG(ERR,
9742                             "port %d must be stopped before configuration\n",
9743                             dev_data->port_id);
9744                 return -EBUSY;
9745         }
9746
9747         if (frame_size > ETHER_MAX_LEN)
9748                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9749         else
9750                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9751
9752         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9753
9754         return ret;
9755 }