drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68 #include "rte_pmd_i40e.h"
  69
  70 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  71 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  72
  73 #define I40E_CLEAR_PXE_WAIT_MS     200
  74
  75 /* Maximun number of capability elements */
  76 #define I40E_MAX_CAP_ELE_NUM       128
  77
  78 /* Wait count and interval */
  79 #define I40E_CHK_Q_ENA_COUNT       1000
  80 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  81
  82 /* Maximun number of VSI */
  83 #define I40E_MAX_NUM_VSIS          (384UL)
  84
  85 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  86
  87 /* Flow control default timer */
  88 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  89
  90 /* Flow control enable fwd bit */
  91 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  92
  93 /* Receive Packet Buffer size */
  94 #define I40E_RXPBSIZE (968 * 1024)
  95
  96 /* Kilobytes shift */
  97 #define I40E_KILOSHIFT 10
  98
  99 /* Flow control default high water */
 100 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
 101
 102 /* Flow control default low water */
 103 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
 104
 105 /* Receive Average Packet Size in Byte*/
 106 #define I40E_PACKET_AVERAGE_SIZE 128
 107
 108 /* Mask of PF interrupt causes */
 109 #define I40E_PFINT_ICR0_ENA_MASK ( \
 110                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 112                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 114                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 115                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 118                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 119
 120 #define I40E_FLOW_TYPES ( \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 130         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 131         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 132
 133 /* Additional timesync values. */
 134 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 135 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 136 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 137 #define I40E_PRTTSYN_TSYNENA     0x80000000
 138 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 139 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define I40E_MAX_PERCENT            100
 142 #define I40E_DEFAULT_DCB_APP_NUM    1
 143 #define I40E_DEFAULT_DCB_APP_PRIO   3
 144
 145 /**
 146  * Below are values for writing un-exposed registers suggested
 147  * by silicon experts
 148  */
 149 /* Destination MAC address */
 150 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 151 /* Source MAC address */
 152 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 153 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 154 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 155 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 156 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 157 /* Single VLAN tag in the inner L2 header */
 158 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 159 /* Source IPv4 address */
 160 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 161 /* Destination IPv4 address */
 162 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 163 /* Source IPv4 address for X722 */
 164 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 165 /* Destination IPv4 address for X722 */
 166 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 167 /* IPv4 Protocol for X722 */
 168 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 169 /* IPv4 Time to Live for X722 */
 170 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 171 /* IPv4 Type of Service (TOS) */
 172 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 173 /* IPv4 Protocol */
 174 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 175 /* IPv4 Time to Live */
 176 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 177 /* Source IPv6 address */
 178 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 179 /* Destination IPv6 address */
 180 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 181 /* IPv6 Traffic Class (TC) */
 182 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 183 /* IPv6 Next Header */
 184 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 185 /* IPv6 Hop Limit */
 186 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 187 /* Source L4 port */
 188 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 189 /* Destination L4 port */
 190 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 191 /* SCTP verification tag */
 192 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 193 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 194 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 195 /* Source port of tunneling UDP */
 196 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 197 /* Destination port of tunneling UDP */
 198 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 199 /* UDP Tunneling ID, NVGRE/GRE key */
 200 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 201 /* Last ether type */
 202 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 203 /* Tunneling outer destination IPv4 address */
 204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 205 /* Tunneling outer destination IPv6 address */
 206 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 207 /* 1st word of flex payload */
 208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 209 /* 2nd word of flex payload */
 210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 211 /* 3rd word of flex payload */
 212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 213 /* 4th word of flex payload */
 214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 215 /* 5th word of flex payload */
 216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 217 /* 6th word of flex payload */
 218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 219 /* 7th word of flex payload */
 220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 221 /* 8th word of flex payload */
 222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 223 /* all 8 words flex payload */
 224 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 225 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 226
 227 #define I40E_TRANSLATE_INSET 0
 228 #define I40E_TRANSLATE_REG   1
 229
 230 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 231 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 232 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 233 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 234 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 235 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 236
 237 /* PCI offset for querying capability */
 238 #define PCI_DEV_CAP_REG            0xA4
 239 /* PCI offset for enabling/disabling Extended Tag */
 240 #define PCI_DEV_CTRL_REG           0xA8
 241 /* Bit mask of Extended Tag capability */
 242 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 243 /* Bit shift of Extended Tag enable/disable */
 244 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 245 /* Bit mask of Extended Tag enable/disable */
 246 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 247
 248 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 249 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 250 static int i40e_dev_configure(struct rte_eth_dev *dev);
 251 static int i40e_dev_start(struct rte_eth_dev *dev);
 252 static void i40e_dev_stop(struct rte_eth_dev *dev);
 253 static void i40e_dev_close(struct rte_eth_dev *dev);
 254 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 255 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 256 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 257 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 258 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 259 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 260 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 261 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 262                                struct rte_eth_stats *stats);
 263 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 264                                struct rte_eth_xstat *xstats, unsigned n);
 265 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 266                                      struct rte_eth_xstat_name *xstats_names,
 267                                      unsigned limit);
 268 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 269 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 270                                             uint16_t queue_id,
 271                                             uint8_t stat_idx,
 272                                             uint8_t is_rx);
 273 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 274                                 char *fw_version, size_t fw_size);
 275 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 276                               struct rte_eth_dev_info *dev_info);
 277 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 278                                 uint16_t vlan_id,
 279                                 int on);
 280 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 281                               enum rte_vlan_type vlan_type,
 282                               uint16_t tpid);
 283 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 284 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 285                                       uint16_t queue,
 286                                       int on);
 287 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 288 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 289 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 290 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 291                               struct rte_eth_fc_conf *fc_conf);
 292 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 293                               struct rte_eth_fc_conf *fc_conf);
 294 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 295                                        struct rte_eth_pfc_conf *pfc_conf);
 296 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 297                             struct ether_addr *mac_addr,
 298                             uint32_t index,
 299                             uint32_t pool);
 300 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 301 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 302                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 303                                     uint16_t reta_size);
 304 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 305                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 306                                    uint16_t reta_size);
 307
 308 static int i40e_get_cap(struct i40e_hw *hw);
 309 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 310 static int i40e_pf_setup(struct i40e_pf *pf);
 311 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 312 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 313 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 314 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 315 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 316                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 317 static void i40e_stat_update_48(struct i40e_hw *hw,
 318                                uint32_t hireg,
 319                                uint32_t loreg,
 320                                bool offset_loaded,
 321                                uint64_t *offset,
 322                                uint64_t *stat);
 323 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 324 static void i40e_dev_interrupt_handler(void *param);
 325 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 326                                 uint32_t base, uint32_t num);
 327 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 328 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 329                         uint32_t base);
 330 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 331                         uint16_t num);
 332 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 333 static int i40e_veb_release(struct i40e_veb *veb);
 334 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 335                                                 struct i40e_vsi *vsi);
 336 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 337 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 338 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 339                                              struct i40e_macvlan_filter *mv_f,
 340                                              int num,
 341                                              uint16_t vlan);
 342 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 343 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 344                                     struct rte_eth_rss_conf *rss_conf);
 345 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 346                                       struct rte_eth_rss_conf *rss_conf);
 347 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 348                                         struct rte_eth_udp_tunnel *udp_tunnel);
 349 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 350                                         struct rte_eth_udp_tunnel *udp_tunnel);
 351 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 352 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 353                                 enum rte_filter_op filter_op,
 354                                 void *arg);
 355 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 356                                 enum rte_filter_type filter_type,
 357                                 enum rte_filter_op filter_op,
 358                                 void *arg);
 359 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 360                                   struct rte_eth_dcb_info *dcb_info);
 361 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 362 static void i40e_configure_registers(struct i40e_hw *hw);
 363 static void i40e_hw_init(struct rte_eth_dev *dev);
 364 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 365 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 366                                                      uint16_t seid,
 367                                                      uint16_t rule_type,
 368                                                      uint16_t *entries,
 369                                                      uint16_t count,
 370                                                      uint16_t rule_id);
 371 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 372                         struct rte_eth_mirror_conf *mirror_conf,
 373                         uint8_t sw_id, uint8_t on);
 374 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 375
 376 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 377 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 378 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 379                                            struct timespec *timestamp,
 380                                            uint32_t flags);
 381 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 382                                            struct timespec *timestamp);
 383 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 384
 385 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 386
 387 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 388                                    struct timespec *timestamp);
 389 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 390                                     const struct timespec *timestamp);
 391
 392 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 393                                          uint16_t queue_id);
 394 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 395                                           uint16_t queue_id);
 396
 397 static int i40e_get_regs(struct rte_eth_dev *dev,
 398                          struct rte_dev_reg_info *regs);
 399
 400 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 401
 402 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 403                            struct rte_dev_eeprom_info *eeprom);
 404
 405 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 406                                       struct ether_addr *mac_addr);
 407
 408 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 409
 410 static int i40e_ethertype_filter_convert(
 411         const struct rte_eth_ethertype_filter *input,
 412         struct i40e_ethertype_filter *filter);
 413 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 414                                    struct i40e_ethertype_filter *filter);
 415
 416 static int i40e_tunnel_filter_convert(
 417         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 418         struct i40e_tunnel_filter *tunnel_filter);
 419 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 420                                 struct i40e_tunnel_filter *tunnel_filter);
 421 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 422
 423 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 424 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 425 static void i40e_filter_restore(struct i40e_pf *pf);
 426 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 427
 428 int i40e_logtype_init;
 429 int i40e_logtype_driver;
 430
 431 static const struct rte_pci_id pci_id_i40e_map[] = {
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 445         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 446         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 447         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 448         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 449         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 450         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 451         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 452         { .vendor_id = 0, /* sentinel */ },
 453 };
 454
 455 static const struct eth_dev_ops i40e_eth_dev_ops = {
 456         .dev_configure                = i40e_dev_configure,
 457         .dev_start                    = i40e_dev_start,
 458         .dev_stop                     = i40e_dev_stop,
 459         .dev_close                    = i40e_dev_close,
 460         .dev_reset                    = i40e_dev_reset,
 461         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 462         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 463         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 464         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 465         .dev_set_link_up              = i40e_dev_set_link_up,
 466         .dev_set_link_down            = i40e_dev_set_link_down,
 467         .link_update                  = i40e_dev_link_update,
 468         .stats_get                    = i40e_dev_stats_get,
 469         .xstats_get                   = i40e_dev_xstats_get,
 470         .xstats_get_names             = i40e_dev_xstats_get_names,
 471         .stats_reset                  = i40e_dev_stats_reset,
 472         .xstats_reset                 = i40e_dev_stats_reset,
 473         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 474         .fw_version_get               = i40e_fw_version_get,
 475         .dev_infos_get                = i40e_dev_info_get,
 476         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 477         .vlan_filter_set              = i40e_vlan_filter_set,
 478         .vlan_tpid_set                = i40e_vlan_tpid_set,
 479         .vlan_offload_set             = i40e_vlan_offload_set,
 480         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 481         .vlan_pvid_set                = i40e_vlan_pvid_set,
 482         .rx_queue_start               = i40e_dev_rx_queue_start,
 483         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 484         .tx_queue_start               = i40e_dev_tx_queue_start,
 485         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 486         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 487         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 488         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 489         .rx_queue_release             = i40e_dev_rx_queue_release,
 490         .rx_queue_count               = i40e_dev_rx_queue_count,
 491         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 492         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 493         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 494         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 495         .tx_queue_release             = i40e_dev_tx_queue_release,
 496         .dev_led_on                   = i40e_dev_led_on,
 497         .dev_led_off                  = i40e_dev_led_off,
 498         .flow_ctrl_get                = i40e_flow_ctrl_get,
 499         .flow_ctrl_set                = i40e_flow_ctrl_set,
 500         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 501         .mac_addr_add                 = i40e_macaddr_add,
 502         .mac_addr_remove              = i40e_macaddr_remove,
 503         .reta_update                  = i40e_dev_rss_reta_update,
 504         .reta_query                   = i40e_dev_rss_reta_query,
 505         .rss_hash_update              = i40e_dev_rss_hash_update,
 506         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 507         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 508         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 509         .filter_ctrl                  = i40e_dev_filter_ctrl,
 510         .rxq_info_get                 = i40e_rxq_info_get,
 511         .txq_info_get                 = i40e_txq_info_get,
 512         .mirror_rule_set              = i40e_mirror_rule_set,
 513         .mirror_rule_reset            = i40e_mirror_rule_reset,
 514         .timesync_enable              = i40e_timesync_enable,
 515         .timesync_disable             = i40e_timesync_disable,
 516         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 517         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 518         .get_dcb_info                 = i40e_dev_get_dcb_info,
 519         .timesync_adjust_time         = i40e_timesync_adjust_time,
 520         .timesync_read_time           = i40e_timesync_read_time,
 521         .timesync_write_time          = i40e_timesync_write_time,
 522         .get_reg                      = i40e_get_regs,
 523         .get_eeprom_length            = i40e_get_eeprom_length,
 524         .get_eeprom                   = i40e_get_eeprom,
 525         .mac_addr_set                 = i40e_set_default_mac_addr,
 526         .mtu_set                      = i40e_dev_mtu_set,
 527         .tm_ops_get                   = i40e_tm_ops_get,
 528 };
 529
 530 /* store statistics names and its offset in stats structure */
 531 struct rte_i40e_xstats_name_off {
 532         char name[RTE_ETH_XSTATS_NAME_SIZE];
 533         unsigned offset;
 534 };
 535
 536 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 537         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 538         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 539         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 540         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 541         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 542                 rx_unknown_protocol)},
 543         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 544         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 545         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 546         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 547 };
 548
 549 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 550                 sizeof(rte_i40e_stats_strings[0]))
 551
 552 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 553         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 554                 tx_dropped_link_down)},
 555         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 556         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 557                 illegal_bytes)},
 558         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 559         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 560                 mac_local_faults)},
 561         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 562                 mac_remote_faults)},
 563         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 564                 rx_length_errors)},
 565         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 566         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 567         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 568         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 569         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 570         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 571                 rx_size_127)},
 572         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 573                 rx_size_255)},
 574         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 575                 rx_size_511)},
 576         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 577                 rx_size_1023)},
 578         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 579                 rx_size_1522)},
 580         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 581                 rx_size_big)},
 582         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 583                 rx_undersize)},
 584         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 585                 rx_oversize)},
 586         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 587                 mac_short_packet_dropped)},
 588         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 589                 rx_fragments)},
 590         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 591         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 592         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 593                 tx_size_127)},
 594         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 595                 tx_size_255)},
 596         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 597                 tx_size_511)},
 598         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 599                 tx_size_1023)},
 600         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 601                 tx_size_1522)},
 602         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 603                 tx_size_big)},
 604         {"rx_flow_director_atr_match_packets",
 605                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 606         {"rx_flow_director_sb_match_packets",
 607                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 608         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 609                 tx_lpi_status)},
 610         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 611                 rx_lpi_status)},
 612         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 613                 tx_lpi_count)},
 614         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 615                 rx_lpi_count)},
 616 };
 617
 618 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 619                 sizeof(rte_i40e_hw_port_strings[0]))
 620
 621 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 622         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 623                 priority_xon_rx)},
 624         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 625                 priority_xoff_rx)},
 626 };
 627
 628 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 629                 sizeof(rte_i40e_rxq_prio_strings[0]))
 630
 631 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 632         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 633                 priority_xon_tx)},
 634         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 635                 priority_xoff_tx)},
 636         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 637                 priority_xon_2_xoff)},
 638 };
 639
 640 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 641                 sizeof(rte_i40e_txq_prio_strings[0]))
 642
 643 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 644         struct rte_pci_device *pci_dev)
 645 {
 646         return rte_eth_dev_pci_generic_probe(pci_dev,
 647                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 648 }
 649
 650 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 651 {
 652         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 653 }
 654
 655 static struct rte_pci_driver rte_i40e_pmd = {
 656         .id_table = pci_id_i40e_map,
 657         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 658         .probe = eth_i40e_pci_probe,
 659         .remove = eth_i40e_pci_remove,
 660 };
 661
 662 static inline int
 663 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 664                                      struct rte_eth_link *link)
 665 {
 666         struct rte_eth_link *dst = link;
 667         struct rte_eth_link *src = &(dev->data->dev_link);
 668
 669         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 670                                         *(uint64_t *)src) == 0)
 671                 return -1;
 672
 673         return 0;
 674 }
 675
 676 static inline int
 677 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 678                                       struct rte_eth_link *link)
 679 {
 680         struct rte_eth_link *dst = &(dev->data->dev_link);
 681         struct rte_eth_link *src = link;
 682
 683         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 684                                         *(uint64_t *)src) == 0)
 685                 return -1;
 686
 687         return 0;
 688 }
 689
 690 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 691 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 692 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 693
 694 #ifndef I40E_GLQF_ORT
 695 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 696 #endif
 697 #ifndef I40E_GLQF_PIT
 698 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 699 #endif
 700 #ifndef I40E_GLQF_L3_MAP
 701 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 702 #endif
 703
 704 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 705 {
 706         /*
 707          * Initialize registers for flexible payload, which should be set by NVM.
 708          * This should be removed from code once it is fixed in NVM.
 709          */
 710         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 711         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 712         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 713         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 714         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 715         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 716         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 717         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 718         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 719         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 720         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 721         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 722
 723         /* Initialize registers for parsing packet type of QinQ */
 724         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 725         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 726 }
 727
 728 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 729
 730 /*
 731  * Add a ethertype filter to drop all flow control frames transmitted
 732  * from VSIs.
 733 */
 734 static void
 735 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 736 {
 737         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 738         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 739                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 740                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 741         int ret;
 742
 743         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 744                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 745                                 pf->main_vsi_seid, 0,
 746                                 TRUE, NULL, NULL);
 747         if (ret)
 748                 PMD_INIT_LOG(ERR,
 749                         "Failed to add filter to drop flow control frames from VSIs.");
 750 }
 751
 752 static int
 753 floating_veb_list_handler(__rte_unused const char *key,
 754                           const char *floating_veb_value,
 755                           void *opaque)
 756 {
 757         int idx = 0;
 758         unsigned int count = 0;
 759         char *end = NULL;
 760         int min, max;
 761         bool *vf_floating_veb = opaque;
 762
 763         while (isblank(*floating_veb_value))
 764                 floating_veb_value++;
 765
 766         /* Reset floating VEB configuration for VFs */
 767         for (idx = 0; idx < I40E_MAX_VF; idx++)
 768                 vf_floating_veb[idx] = false;
 769
 770         min = I40E_MAX_VF;
 771         do {
 772                 while (isblank(*floating_veb_value))
 773                         floating_veb_value++;
 774                 if (*floating_veb_value == '\0')
 775                         return -1;
 776                 errno = 0;
 777                 idx = strtoul(floating_veb_value, &end, 10);
 778                 if (errno || end == NULL)
 779                         return -1;
 780                 while (isblank(*end))
 781                         end++;
 782                 if (*end == '-') {
 783                         min = idx;
 784                 } else if ((*end == ';') || (*end == '\0')) {
 785                         max = idx;
 786                         if (min == I40E_MAX_VF)
 787                                 min = idx;
 788                         if (max >= I40E_MAX_VF)
 789                                 max = I40E_MAX_VF - 1;
 790                         for (idx = min; idx <= max; idx++) {
 791                                 vf_floating_veb[idx] = true;
 792                                 count++;
 793                         }
 794                         min = I40E_MAX_VF;
 795                 } else {
 796                         return -1;
 797                 }
 798                 floating_veb_value = end + 1;
 799         } while (*end != '\0');
 800
 801         if (count == 0)
 802                 return -1;
 803
 804         return 0;
 805 }
 806
 807 static void
 808 config_vf_floating_veb(struct rte_devargs *devargs,
 809                        uint16_t floating_veb,
 810                        bool *vf_floating_veb)
 811 {
 812         struct rte_kvargs *kvlist;
 813         int i;
 814         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 815
 816         if (!floating_veb)
 817                 return;
 818         /* All the VFs attach to the floating VEB by default
 819          * when the floating VEB is enabled.
 820          */
 821         for (i = 0; i < I40E_MAX_VF; i++)
 822                 vf_floating_veb[i] = true;
 823
 824         if (devargs == NULL)
 825                 return;
 826
 827         kvlist = rte_kvargs_parse(devargs->args, NULL);
 828         if (kvlist == NULL)
 829                 return;
 830
 831         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 832                 rte_kvargs_free(kvlist);
 833                 return;
 834         }
 835         /* When the floating_veb_list parameter exists, all the VFs
 836          * will attach to the legacy VEB firstly, then configure VFs
 837          * to the floating VEB according to the floating_veb_list.
 838          */
 839         if (rte_kvargs_process(kvlist, floating_veb_list,
 840                                floating_veb_list_handler,
 841                                vf_floating_veb) < 0) {
 842                 rte_kvargs_free(kvlist);
 843                 return;
 844         }
 845         rte_kvargs_free(kvlist);
 846 }
 847
 848 static int
 849 i40e_check_floating_handler(__rte_unused const char *key,
 850                             const char *value,
 851                             __rte_unused void *opaque)
 852 {
 853         if (strcmp(value, "1"))
 854                 return -1;
 855
 856         return 0;
 857 }
 858
 859 static int
 860 is_floating_veb_supported(struct rte_devargs *devargs)
 861 {
 862         struct rte_kvargs *kvlist;
 863         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 864
 865         if (devargs == NULL)
 866                 return 0;
 867
 868         kvlist = rte_kvargs_parse(devargs->args, NULL);
 869         if (kvlist == NULL)
 870                 return 0;
 871
 872         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 873                 rte_kvargs_free(kvlist);
 874                 return 0;
 875         }
 876         /* Floating VEB is enabled when there's key-value:
 877          * enable_floating_veb=1
 878          */
 879         if (rte_kvargs_process(kvlist, floating_veb_key,
 880                                i40e_check_floating_handler, NULL) < 0) {
 881                 rte_kvargs_free(kvlist);
 882                 return 0;
 883         }
 884         rte_kvargs_free(kvlist);
 885
 886         return 1;
 887 }
 888
 889 static void
 890 config_floating_veb(struct rte_eth_dev *dev)
 891 {
 892         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 893         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 894         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 895
 896         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 897
 898         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 899                 pf->floating_veb =
 900                         is_floating_veb_supported(pci_dev->device.devargs);
 901                 config_vf_floating_veb(pci_dev->device.devargs,
 902                                        pf->floating_veb,
 903                                        pf->floating_veb_list);
 904         } else {
 905                 pf->floating_veb = false;
 906         }
 907 }
 908
 909 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 910 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 911
 912 static int
 913 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 914 {
 915         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 916         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 917         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 918         int ret;
 919
 920         struct rte_hash_parameters ethertype_hash_params = {
 921                 .name = ethertype_hash_name,
 922                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 923                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 924                 .hash_func = rte_hash_crc,
 925                 .hash_func_init_val = 0,
 926                 .socket_id = rte_socket_id(),
 927         };
 928
 929         /* Initialize ethertype filter rule list and hash */
 930         TAILQ_INIT(&ethertype_rule->ethertype_list);
 931         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 932                  "ethertype_%s", dev->device->name);
 933         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 934         if (!ethertype_rule->hash_table) {
 935                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 936                 return -EINVAL;
 937         }
 938         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 939                                        sizeof(struct i40e_ethertype_filter *) *
 940                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 941                                        0);
 942         if (!ethertype_rule->hash_map) {
 943                 PMD_INIT_LOG(ERR,
 944                              "Failed to allocate memory for ethertype hash map!");
 945                 ret = -ENOMEM;
 946                 goto err_ethertype_hash_map_alloc;
 947         }
 948
 949         return 0;
 950
 951 err_ethertype_hash_map_alloc:
 952         rte_hash_free(ethertype_rule->hash_table);
 953
 954         return ret;
 955 }
 956
 957 static int
 958 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 959 {
 960         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 961         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 962         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 963         int ret;
 964
 965         struct rte_hash_parameters tunnel_hash_params = {
 966                 .name = tunnel_hash_name,
 967                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 968                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 969                 .hash_func = rte_hash_crc,
 970                 .hash_func_init_val = 0,
 971                 .socket_id = rte_socket_id(),
 972         };
 973
 974         /* Initialize tunnel filter rule list and hash */
 975         TAILQ_INIT(&tunnel_rule->tunnel_list);
 976         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 977                  "tunnel_%s", dev->device->name);
 978         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 979         if (!tunnel_rule->hash_table) {
 980                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 981                 return -EINVAL;
 982         }
 983         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 984                                     sizeof(struct i40e_tunnel_filter *) *
 985                                     I40E_MAX_TUNNEL_FILTER_NUM,
 986                                     0);
 987         if (!tunnel_rule->hash_map) {
 988                 PMD_INIT_LOG(ERR,
 989                              "Failed to allocate memory for tunnel hash map!");
 990                 ret = -ENOMEM;
 991                 goto err_tunnel_hash_map_alloc;
 992         }
 993
 994         return 0;
 995
 996 err_tunnel_hash_map_alloc:
 997         rte_hash_free(tunnel_rule->hash_table);
 998
 999         return ret;
1000 }
1001
1002 static int
1003 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1004 {
1005         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1006         struct i40e_fdir_info *fdir_info = &pf->fdir;
1007         char fdir_hash_name[RTE_HASH_NAMESIZE];
1008         int ret;
1009
1010         struct rte_hash_parameters fdir_hash_params = {
1011                 .name = fdir_hash_name,
1012                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1013                 .key_len = sizeof(struct rte_eth_fdir_input),
1014                 .hash_func = rte_hash_crc,
1015                 .hash_func_init_val = 0,
1016                 .socket_id = rte_socket_id(),
1017         };
1018
1019         /* Initialize flow director filter rule list and hash */
1020         TAILQ_INIT(&fdir_info->fdir_list);
1021         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1022                  "fdir_%s", dev->device->name);
1023         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1024         if (!fdir_info->hash_table) {
1025                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1026                 return -EINVAL;
1027         }
1028         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1029                                           sizeof(struct i40e_fdir_filter *) *
1030                                           I40E_MAX_FDIR_FILTER_NUM,
1031                                           0);
1032         if (!fdir_info->hash_map) {
1033                 PMD_INIT_LOG(ERR,
1034                              "Failed to allocate memory for fdir hash map!");
1035                 ret = -ENOMEM;
1036                 goto err_fdir_hash_map_alloc;
1037         }
1038         return 0;
1039
1040 err_fdir_hash_map_alloc:
1041         rte_hash_free(fdir_info->hash_table);
1042
1043         return ret;
1044 }
1045
1046 static void
1047 i40e_init_customized_info(struct i40e_pf *pf)
1048 {
1049         int i;
1050
1051         /* Initialize customized pctype */
1052         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1053                 pf->customized_pctype[i].index = i;
1054                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1055                 pf->customized_pctype[i].valid = false;
1056         }
1057
1058         pf->gtp_support = false;
1059 }
1060
1061 static int
1062 eth_i40e_dev_init(struct rte_eth_dev *dev)
1063 {
1064         struct rte_pci_device *pci_dev;
1065         struct rte_intr_handle *intr_handle;
1066         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1067         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1068         struct i40e_vsi *vsi;
1069         int ret;
1070         uint32_t len;
1071         uint8_t aq_fail = 0;
1072
1073         PMD_INIT_FUNC_TRACE();
1074
1075         dev->dev_ops = &i40e_eth_dev_ops;
1076         dev->rx_pkt_burst = i40e_recv_pkts;
1077         dev->tx_pkt_burst = i40e_xmit_pkts;
1078         dev->tx_pkt_prepare = i40e_prep_pkts;
1079
1080         /* for secondary processes, we don't initialise any further as primary
1081          * has already done this work. Only check we don't need a different
1082          * RX function */
1083         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1084                 i40e_set_rx_function(dev);
1085                 i40e_set_tx_function(dev);
1086                 return 0;
1087         }
1088         i40e_set_default_ptype_table(dev);
1089         i40e_set_default_pctype_table(dev);
1090         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1091         intr_handle = &pci_dev->intr_handle;
1092
1093         rte_eth_copy_pci_info(dev, pci_dev);
1094         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1095
1096         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1097         pf->adapter->eth_dev = dev;
1098         pf->dev_data = dev->data;
1099
1100         hw->back = I40E_PF_TO_ADAPTER(pf);
1101         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1102         if (!hw->hw_addr) {
1103                 PMD_INIT_LOG(ERR,
1104                         "Hardware is not available, as address is NULL");
1105                 return -ENODEV;
1106         }
1107
1108         hw->vendor_id = pci_dev->id.vendor_id;
1109         hw->device_id = pci_dev->id.device_id;
1110         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1111         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1112         hw->bus.device = pci_dev->addr.devid;
1113         hw->bus.func = pci_dev->addr.function;
1114         hw->adapter_stopped = 0;
1115
1116         /* Make sure all is clean before doing PF reset */
1117         i40e_clear_hw(hw);
1118
1119         /* Initialize the hardware */
1120         i40e_hw_init(dev);
1121
1122         /* Reset here to make sure all is clean for each PF */
1123         ret = i40e_pf_reset(hw);
1124         if (ret) {
1125                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1126                 return ret;
1127         }
1128
1129         /* Initialize the shared code (base driver) */
1130         ret = i40e_init_shared_code(hw);
1131         if (ret) {
1132                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1133                 return ret;
1134         }
1135
1136         /*
1137          * To work around the NVM issue, initialize registers
1138          * for flexible payload and packet type of QinQ by
1139          * software. It should be removed once issues are fixed
1140          * in NVM.
1141          */
1142         i40e_GLQF_reg_init(hw);
1143
1144         /* Initialize the input set for filters (hash and fd) to default value */
1145         i40e_filter_input_set_init(pf);
1146
1147         /* Initialize the parameters for adminq */
1148         i40e_init_adminq_parameter(hw);
1149         ret = i40e_init_adminq(hw);
1150         if (ret != I40E_SUCCESS) {
1151                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1152                 return -EIO;
1153         }
1154         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1155                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1156                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1157                      ((hw->nvm.version >> 12) & 0xf),
1158                      ((hw->nvm.version >> 4) & 0xff),
1159                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1160
1161         /* initialise the L3_MAP register */
1162         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1163                                    0x00000028,  NULL);
1164         if (ret)
1165                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1166
1167         /* Need the special FW version to support floating VEB */
1168         config_floating_veb(dev);
1169         /* Clear PXE mode */
1170         i40e_clear_pxe_mode(hw);
1171         i40e_dev_sync_phy_type(hw);
1172
1173         /*
1174          * On X710, performance number is far from the expectation on recent
1175          * firmware versions. The fix for this issue may not be integrated in
1176          * the following firmware version. So the workaround in software driver
1177          * is needed. It needs to modify the initial values of 3 internal only
1178          * registers. Note that the workaround can be removed when it is fixed
1179          * in firmware in the future.
1180          */
1181         i40e_configure_registers(hw);
1182
1183         /* Get hw capabilities */
1184         ret = i40e_get_cap(hw);
1185         if (ret != I40E_SUCCESS) {
1186                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1187                 goto err_get_capabilities;
1188         }
1189
1190         /* Initialize parameters for PF */
1191         ret = i40e_pf_parameter_init(dev);
1192         if (ret != 0) {
1193                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1194                 goto err_parameter_init;
1195         }
1196
1197         /* Initialize the queue management */
1198         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1199         if (ret < 0) {
1200                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1201                 goto err_qp_pool_init;
1202         }
1203         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1204                                 hw->func_caps.num_msix_vectors - 1);
1205         if (ret < 0) {
1206                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1207                 goto err_msix_pool_init;
1208         }
1209
1210         /* Initialize lan hmc */
1211         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1212                                 hw->func_caps.num_rx_qp, 0, 0);
1213         if (ret != I40E_SUCCESS) {
1214                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1215                 goto err_init_lan_hmc;
1216         }
1217
1218         /* Configure lan hmc */
1219         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1220         if (ret != I40E_SUCCESS) {
1221                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1222                 goto err_configure_lan_hmc;
1223         }
1224
1225         /* Get and check the mac address */
1226         i40e_get_mac_addr(hw, hw->mac.addr);
1227         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1228                 PMD_INIT_LOG(ERR, "mac address is not valid");
1229                 ret = -EIO;
1230                 goto err_get_mac_addr;
1231         }
1232         /* Copy the permanent MAC address */
1233         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1234                         (struct ether_addr *) hw->mac.perm_addr);
1235
1236         /* Disable flow control */
1237         hw->fc.requested_mode = I40E_FC_NONE;
1238         i40e_set_fc(hw, &aq_fail, TRUE);
1239
1240         /* Set the global registers with default ether type value */
1241         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1242         if (ret != I40E_SUCCESS) {
1243                 PMD_INIT_LOG(ERR,
1244                         "Failed to set the default outer VLAN ether type");
1245                 goto err_setup_pf_switch;
1246         }
1247
1248         /* PF setup, which includes VSI setup */
1249         ret = i40e_pf_setup(pf);
1250         if (ret) {
1251                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1252                 goto err_setup_pf_switch;
1253         }
1254
1255         /* reset all stats of the device, including pf and main vsi */
1256         i40e_dev_stats_reset(dev);
1257
1258         vsi = pf->main_vsi;
1259
1260         /* Disable double vlan by default */
1261         i40e_vsi_config_double_vlan(vsi, FALSE);
1262
1263         /* Disable S-TAG identification when floating_veb is disabled */
1264         if (!pf->floating_veb) {
1265                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1266                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1267                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1268                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1269                 }
1270         }
1271
1272         if (!vsi->max_macaddrs)
1273                 len = ETHER_ADDR_LEN;
1274         else
1275                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1276
1277         /* Should be after VSI initialized */
1278         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1279         if (!dev->data->mac_addrs) {
1280                 PMD_INIT_LOG(ERR,
1281                         "Failed to allocated memory for storing mac address");
1282                 goto err_mac_alloc;
1283         }
1284         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1285                                         &dev->data->mac_addrs[0]);
1286
1287         /* Init dcb to sw mode by default */
1288         ret = i40e_dcb_init_configure(dev, TRUE);
1289         if (ret != I40E_SUCCESS) {
1290                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1291                 pf->flags &= ~I40E_FLAG_DCB;
1292         }
1293         /* Update HW struct after DCB configuration */
1294         i40e_get_cap(hw);
1295
1296         /* initialize pf host driver to setup SRIOV resource if applicable */
1297         i40e_pf_host_init(dev);
1298
1299         /* register callback func to eal lib */
1300         rte_intr_callback_register(intr_handle,
1301                                    i40e_dev_interrupt_handler, dev);
1302
1303         /* configure and enable device interrupt */
1304         i40e_pf_config_irq0(hw, TRUE);
1305         i40e_pf_enable_irq0(hw);
1306
1307         /* enable uio intr after callback register */
1308         rte_intr_enable(intr_handle);
1309         /*
1310          * Add an ethertype filter to drop all flow control frames transmitted
1311          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1312          * frames to wire.
1313          */
1314         i40e_add_tx_flow_control_drop_filter(pf);
1315
1316         /* Set the max frame size to 0x2600 by default,
1317          * in case other drivers changed the default value.
1318          */
1319         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1320
1321         /* initialize mirror rule list */
1322         TAILQ_INIT(&pf->mirror_list);
1323
1324         /* initialize Traffic Manager configuration */
1325         i40e_tm_conf_init(dev);
1326
1327         /* Initialize customized information */
1328         i40e_init_customized_info(pf);
1329
1330         ret = i40e_init_ethtype_filter_list(dev);
1331         if (ret < 0)
1332                 goto err_init_ethtype_filter_list;
1333         ret = i40e_init_tunnel_filter_list(dev);
1334         if (ret < 0)
1335                 goto err_init_tunnel_filter_list;
1336         ret = i40e_init_fdir_filter_list(dev);
1337         if (ret < 0)
1338                 goto err_init_fdir_filter_list;
1339
1340         return 0;
1341
1342 err_init_fdir_filter_list:
1343         rte_free(pf->tunnel.hash_table);
1344         rte_free(pf->tunnel.hash_map);
1345 err_init_tunnel_filter_list:
1346         rte_free(pf->ethertype.hash_table);
1347         rte_free(pf->ethertype.hash_map);
1348 err_init_ethtype_filter_list:
1349         rte_free(dev->data->mac_addrs);
1350 err_mac_alloc:
1351         i40e_vsi_release(pf->main_vsi);
1352 err_setup_pf_switch:
1353 err_get_mac_addr:
1354 err_configure_lan_hmc:
1355         (void)i40e_shutdown_lan_hmc(hw);
1356 err_init_lan_hmc:
1357         i40e_res_pool_destroy(&pf->msix_pool);
1358 err_msix_pool_init:
1359         i40e_res_pool_destroy(&pf->qp_pool);
1360 err_qp_pool_init:
1361 err_parameter_init:
1362 err_get_capabilities:
1363         (void)i40e_shutdown_adminq(hw);
1364
1365         return ret;
1366 }
1367
1368 static void
1369 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1370 {
1371         struct i40e_ethertype_filter *p_ethertype;
1372         struct i40e_ethertype_rule *ethertype_rule;
1373
1374         ethertype_rule = &pf->ethertype;
1375         /* Remove all ethertype filter rules and hash */
1376         if (ethertype_rule->hash_map)
1377                 rte_free(ethertype_rule->hash_map);
1378         if (ethertype_rule->hash_table)
1379                 rte_hash_free(ethertype_rule->hash_table);
1380
1381         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1382                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1383                              p_ethertype, rules);
1384                 rte_free(p_ethertype);
1385         }
1386 }
1387
1388 static void
1389 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1390 {
1391         struct i40e_tunnel_filter *p_tunnel;
1392         struct i40e_tunnel_rule *tunnel_rule;
1393
1394         tunnel_rule = &pf->tunnel;
1395         /* Remove all tunnel director rules and hash */
1396         if (tunnel_rule->hash_map)
1397                 rte_free(tunnel_rule->hash_map);
1398         if (tunnel_rule->hash_table)
1399                 rte_hash_free(tunnel_rule->hash_table);
1400
1401         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1402                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1403                 rte_free(p_tunnel);
1404         }
1405 }
1406
1407 static void
1408 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1409 {
1410         struct i40e_fdir_filter *p_fdir;
1411         struct i40e_fdir_info *fdir_info;
1412
1413         fdir_info = &pf->fdir;
1414         /* Remove all flow director rules and hash */
1415         if (fdir_info->hash_map)
1416                 rte_free(fdir_info->hash_map);
1417         if (fdir_info->hash_table)
1418                 rte_hash_free(fdir_info->hash_table);
1419
1420         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1421                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1422                 rte_free(p_fdir);
1423         }
1424 }
1425
1426 static int
1427 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1428 {
1429         struct i40e_pf *pf;
1430         struct rte_pci_device *pci_dev;
1431         struct rte_intr_handle *intr_handle;
1432         struct i40e_hw *hw;
1433         struct i40e_filter_control_settings settings;
1434         struct rte_flow *p_flow;
1435         int ret;
1436         uint8_t aq_fail = 0;
1437
1438         PMD_INIT_FUNC_TRACE();
1439
1440         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1441                 return 0;
1442
1443         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1444         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1445         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1446         intr_handle = &pci_dev->intr_handle;
1447
1448         if (hw->adapter_stopped == 0)
1449                 i40e_dev_close(dev);
1450
1451         dev->dev_ops = NULL;
1452         dev->rx_pkt_burst = NULL;
1453         dev->tx_pkt_burst = NULL;
1454
1455         /* Clear PXE mode */
1456         i40e_clear_pxe_mode(hw);
1457
1458         /* Unconfigure filter control */
1459         memset(&settings, 0, sizeof(settings));
1460         ret = i40e_set_filter_control(hw, &settings);
1461         if (ret)
1462                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1463                                         ret);
1464
1465         /* Disable flow control */
1466         hw->fc.requested_mode = I40E_FC_NONE;
1467         i40e_set_fc(hw, &aq_fail, TRUE);
1468
1469         /* uninitialize pf host driver */
1470         i40e_pf_host_uninit(dev);
1471
1472         rte_free(dev->data->mac_addrs);
1473         dev->data->mac_addrs = NULL;
1474
1475         /* disable uio intr before callback unregister */
1476         rte_intr_disable(intr_handle);
1477
1478         /* register callback func to eal lib */
1479         rte_intr_callback_unregister(intr_handle,
1480                                      i40e_dev_interrupt_handler, dev);
1481
1482         i40e_rm_ethtype_filter_list(pf);
1483         i40e_rm_tunnel_filter_list(pf);
1484         i40e_rm_fdir_filter_list(pf);
1485
1486         /* Remove all flows */
1487         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1488                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1489                 rte_free(p_flow);
1490         }
1491
1492         /* Remove all Traffic Manager configuration */
1493         i40e_tm_conf_uninit(dev);
1494
1495         return 0;
1496 }
1497
1498 static int
1499 i40e_dev_configure(struct rte_eth_dev *dev)
1500 {
1501         struct i40e_adapter *ad =
1502                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1503         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1504         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1505         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1506         int i, ret;
1507
1508         ret = i40e_dev_sync_phy_type(hw);
1509         if (ret)
1510                 return ret;
1511
1512         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1513          * bulk allocation or vector Rx preconditions we will reset it.
1514          */
1515         ad->rx_bulk_alloc_allowed = true;
1516         ad->rx_vec_allowed = true;
1517         ad->tx_simple_allowed = true;
1518         ad->tx_vec_allowed = true;
1519
1520         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1521                 ret = i40e_fdir_setup(pf);
1522                 if (ret != I40E_SUCCESS) {
1523                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1524                         return -ENOTSUP;
1525                 }
1526                 ret = i40e_fdir_configure(dev);
1527                 if (ret < 0) {
1528                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1529                         goto err;
1530                 }
1531         } else
1532                 i40e_fdir_teardown(pf);
1533
1534         ret = i40e_dev_init_vlan(dev);
1535         if (ret < 0)
1536                 goto err;
1537
1538         /* VMDQ setup.
1539          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1540          *  RSS setting have different requirements.
1541          *  General PMD driver call sequence are NIC init, configure,
1542          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1543          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1544          *  applicable. So, VMDQ setting has to be done before
1545          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1546          *  For RSS setting, it will try to calculate actual configured RX queue
1547          *  number, which will be available after rx_queue_setup(). dev_start()
1548          *  function is good to place RSS setup.
1549          */
1550         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1551                 ret = i40e_vmdq_setup(dev);
1552                 if (ret)
1553                         goto err;
1554         }
1555
1556         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1557                 ret = i40e_dcb_setup(dev);
1558                 if (ret) {
1559                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1560                         goto err_dcb;
1561                 }
1562         }
1563
1564         TAILQ_INIT(&pf->flow_list);
1565
1566         return 0;
1567
1568 err_dcb:
1569         /* need to release vmdq resource if exists */
1570         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1571                 i40e_vsi_release(pf->vmdq[i].vsi);
1572                 pf->vmdq[i].vsi = NULL;
1573         }
1574         rte_free(pf->vmdq);
1575         pf->vmdq = NULL;
1576 err:
1577         /* need to release fdir resource if exists */
1578         i40e_fdir_teardown(pf);
1579         return ret;
1580 }
1581
1582 void
1583 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1584 {
1585         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1586         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1587         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1588         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1589         uint16_t msix_vect = vsi->msix_intr;
1590         uint16_t i;
1591
1592         for (i = 0; i < vsi->nb_qps; i++) {
1593                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1594                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1595                 rte_wmb();
1596         }
1597
1598         if (vsi->type != I40E_VSI_SRIOV) {
1599                 if (!rte_intr_allow_others(intr_handle)) {
1600                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1601                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1602                         I40E_WRITE_REG(hw,
1603                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1604                                        0);
1605                 } else {
1606                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1607                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1608                         I40E_WRITE_REG(hw,
1609                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1610                                                        msix_vect - 1), 0);
1611                 }
1612         } else {
1613                 uint32_t reg;
1614                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1615                         vsi->user_param + (msix_vect - 1);
1616
1617                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1618                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1619         }
1620         I40E_WRITE_FLUSH(hw);
1621 }
1622
1623 static void
1624 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1625                        int base_queue, int nb_queue,
1626                        uint16_t itr_idx)
1627 {
1628         int i;
1629         uint32_t val;
1630         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1631
1632         /* Bind all RX queues to allocated MSIX interrupt */
1633         for (i = 0; i < nb_queue; i++) {
1634                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1635                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1636                         ((base_queue + i + 1) <<
1637                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1638                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1639                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1640
1641                 if (i == nb_queue - 1)
1642                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1643                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1644         }
1645
1646         /* Write first RX queue to Link list register as the head element */
1647         if (vsi->type != I40E_VSI_SRIOV) {
1648                 uint16_t interval =
1649                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1650
1651                 if (msix_vect == I40E_MISC_VEC_ID) {
1652                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1653                                        (base_queue <<
1654                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1655                                        (0x0 <<
1656                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1657                         I40E_WRITE_REG(hw,
1658                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1659                                        interval);
1660                 } else {
1661                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1662                                        (base_queue <<
1663                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1664                                        (0x0 <<
1665                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1666                         I40E_WRITE_REG(hw,
1667                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1668                                                        msix_vect - 1),
1669                                        interval);
1670                 }
1671         } else {
1672                 uint32_t reg;
1673
1674                 if (msix_vect == I40E_MISC_VEC_ID) {
1675                         I40E_WRITE_REG(hw,
1676                                        I40E_VPINT_LNKLST0(vsi->user_param),
1677                                        (base_queue <<
1678                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1679                                        (0x0 <<
1680                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1681                 } else {
1682                         /* num_msix_vectors_vf needs to minus irq0 */
1683                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1684                                 vsi->user_param + (msix_vect - 1);
1685
1686                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1687                                        (base_queue <<
1688                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1689                                        (0x0 <<
1690                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1691                 }
1692         }
1693
1694         I40E_WRITE_FLUSH(hw);
1695 }
1696
1697 void
1698 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1699 {
1700         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1701         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1702         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1703         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1704         uint16_t msix_vect = vsi->msix_intr;
1705         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1706         uint16_t queue_idx = 0;
1707         int record = 0;
1708         uint32_t val;
1709         int i;
1710
1711         for (i = 0; i < vsi->nb_qps; i++) {
1712                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1713                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1714         }
1715
1716         /* INTENA flag is not auto-cleared for interrupt */
1717         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1718         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1719                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1720                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1721         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1722
1723         /* VF bind interrupt */
1724         if (vsi->type == I40E_VSI_SRIOV) {
1725                 __vsi_queues_bind_intr(vsi, msix_vect,
1726                                        vsi->base_queue, vsi->nb_qps,
1727                                        itr_idx);
1728                 return;
1729         }
1730
1731         /* PF & VMDq bind interrupt */
1732         if (rte_intr_dp_is_en(intr_handle)) {
1733                 if (vsi->type == I40E_VSI_MAIN) {
1734                         queue_idx = 0;
1735                         record = 1;
1736                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1737                         struct i40e_vsi *main_vsi =
1738                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1739                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1740                         record = 1;
1741                 }
1742         }
1743
1744         for (i = 0; i < vsi->nb_used_qps; i++) {
1745                 if (nb_msix <= 1) {
1746                         if (!rte_intr_allow_others(intr_handle))
1747                                 /* allow to share MISC_VEC_ID */
1748                                 msix_vect = I40E_MISC_VEC_ID;
1749
1750                         /* no enough msix_vect, map all to one */
1751                         __vsi_queues_bind_intr(vsi, msix_vect,
1752                                                vsi->base_queue + i,
1753                                                vsi->nb_used_qps - i,
1754                                                itr_idx);
1755                         for (; !!record && i < vsi->nb_used_qps; i++)
1756                                 intr_handle->intr_vec[queue_idx + i] =
1757                                         msix_vect;
1758                         break;
1759                 }
1760                 /* 1:1 queue/msix_vect mapping */
1761                 __vsi_queues_bind_intr(vsi, msix_vect,
1762                                        vsi->base_queue + i, 1,
1763                                        itr_idx);
1764                 if (!!record)
1765                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1766
1767                 msix_vect++;
1768                 nb_msix--;
1769         }
1770 }
1771
1772 static void
1773 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1774 {
1775         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1776         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1777         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1778         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1779         uint16_t interval = i40e_calc_itr_interval(\
1780                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1781         uint16_t msix_intr, i;
1782
1783         if (rte_intr_allow_others(intr_handle))
1784                 for (i = 0; i < vsi->nb_msix; i++) {
1785                         msix_intr = vsi->msix_intr + i;
1786                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1787                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1788                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1789                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1790                                 (interval <<
1791                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1792                 }
1793         else
1794                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1795                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1796                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1797                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1798                                (interval <<
1799                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1800
1801         I40E_WRITE_FLUSH(hw);
1802 }
1803
1804 static void
1805 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1806 {
1807         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1808         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1809         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1810         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1811         uint16_t msix_intr, i;
1812
1813         if (rte_intr_allow_others(intr_handle))
1814                 for (i = 0; i < vsi->nb_msix; i++) {
1815                         msix_intr = vsi->msix_intr + i;
1816                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1817                                        0);
1818                 }
1819         else
1820                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1821
1822         I40E_WRITE_FLUSH(hw);
1823 }
1824
1825 static inline uint8_t
1826 i40e_parse_link_speeds(uint16_t link_speeds)
1827 {
1828         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1829
1830         if (link_speeds & ETH_LINK_SPEED_40G)
1831                 link_speed |= I40E_LINK_SPEED_40GB;
1832         if (link_speeds & ETH_LINK_SPEED_25G)
1833                 link_speed |= I40E_LINK_SPEED_25GB;
1834         if (link_speeds & ETH_LINK_SPEED_20G)
1835                 link_speed |= I40E_LINK_SPEED_20GB;
1836         if (link_speeds & ETH_LINK_SPEED_10G)
1837                 link_speed |= I40E_LINK_SPEED_10GB;
1838         if (link_speeds & ETH_LINK_SPEED_1G)
1839                 link_speed |= I40E_LINK_SPEED_1GB;
1840         if (link_speeds & ETH_LINK_SPEED_100M)
1841                 link_speed |= I40E_LINK_SPEED_100MB;
1842
1843         return link_speed;
1844 }
1845
1846 static int
1847 i40e_phy_conf_link(struct i40e_hw *hw,
1848                    uint8_t abilities,
1849                    uint8_t force_speed,
1850                    bool is_up)
1851 {
1852         enum i40e_status_code status;
1853         struct i40e_aq_get_phy_abilities_resp phy_ab;
1854         struct i40e_aq_set_phy_config phy_conf;
1855         enum i40e_aq_phy_type cnt;
1856         uint32_t phy_type_mask = 0;
1857
1858         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1859                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1860                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1861                         I40E_AQ_PHY_FLAG_LOW_POWER;
1862         const uint8_t advt = I40E_LINK_SPEED_40GB |
1863                         I40E_LINK_SPEED_25GB |
1864                         I40E_LINK_SPEED_10GB |
1865                         I40E_LINK_SPEED_1GB |
1866                         I40E_LINK_SPEED_100MB;
1867         int ret = -ENOTSUP;
1868
1869
1870         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1871                                               NULL);
1872         if (status)
1873                 return ret;
1874
1875         /* If link already up, no need to set up again */
1876         if (is_up && phy_ab.phy_type != 0)
1877                 return I40E_SUCCESS;
1878
1879         memset(&phy_conf, 0, sizeof(phy_conf));
1880
1881         /* bits 0-2 use the values from get_phy_abilities_resp */
1882         abilities &= ~mask;
1883         abilities |= phy_ab.abilities & mask;
1884
1885         /* update ablities and speed */
1886         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1887                 phy_conf.link_speed = advt;
1888         else
1889                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1890
1891         phy_conf.abilities = abilities;
1892
1893
1894
1895         /* To enable link, phy_type mask needs to include each type */
1896         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1897                 phy_type_mask |= 1 << cnt;
1898
1899         /* use get_phy_abilities_resp value for the rest */
1900         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1901         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1902                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1903                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1904         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1905         phy_conf.eee_capability = phy_ab.eee_capability;
1906         phy_conf.eeer = phy_ab.eeer_val;
1907         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1908
1909         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1910                     phy_ab.abilities, phy_ab.link_speed);
1911         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1912                     phy_conf.abilities, phy_conf.link_speed);
1913
1914         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1915         if (status)
1916                 return ret;
1917
1918         return I40E_SUCCESS;
1919 }
1920
1921 static int
1922 i40e_apply_link_speed(struct rte_eth_dev *dev)
1923 {
1924         uint8_t speed;
1925         uint8_t abilities = 0;
1926         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1927         struct rte_eth_conf *conf = &dev->data->dev_conf;
1928
1929         speed = i40e_parse_link_speeds(conf->link_speeds);
1930         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1931         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1932                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1933         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1934
1935         return i40e_phy_conf_link(hw, abilities, speed, true);
1936 }
1937
1938 static int
1939 i40e_dev_start(struct rte_eth_dev *dev)
1940 {
1941         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1942         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1943         struct i40e_vsi *main_vsi = pf->main_vsi;
1944         int ret, i;
1945         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1946         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1947         uint32_t intr_vector = 0;
1948         struct i40e_vsi *vsi;
1949
1950         hw->adapter_stopped = 0;
1951
1952         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1953                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1954                              dev->data->port_id);
1955                 return -EINVAL;
1956         }
1957
1958         rte_intr_disable(intr_handle);
1959
1960         if ((rte_intr_cap_multiple(intr_handle) ||
1961              !RTE_ETH_DEV_SRIOV(dev).active) &&
1962             dev->data->dev_conf.intr_conf.rxq != 0) {
1963                 intr_vector = dev->data->nb_rx_queues;
1964                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1965                 if (ret)
1966                         return ret;
1967         }
1968
1969         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1970                 intr_handle->intr_vec =
1971                         rte_zmalloc("intr_vec",
1972                                     dev->data->nb_rx_queues * sizeof(int),
1973                                     0);
1974                 if (!intr_handle->intr_vec) {
1975                         PMD_INIT_LOG(ERR,
1976                                 "Failed to allocate %d rx_queues intr_vec",
1977                                 dev->data->nb_rx_queues);
1978                         return -ENOMEM;
1979                 }
1980         }
1981
1982         /* Initialize VSI */
1983         ret = i40e_dev_rxtx_init(pf);
1984         if (ret != I40E_SUCCESS) {
1985                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1986                 goto err_up;
1987         }
1988
1989         /* Map queues with MSIX interrupt */
1990         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1991                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1992         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1993         i40e_vsi_enable_queues_intr(main_vsi);
1994
1995         /* Map VMDQ VSI queues with MSIX interrupt */
1996         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1997                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1998                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
1999                                           I40E_ITR_INDEX_DEFAULT);
2000                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2001         }
2002
2003         /* enable FDIR MSIX interrupt */
2004         if (pf->fdir.fdir_vsi) {
2005                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2006                                           I40E_ITR_INDEX_NONE);
2007                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2008         }
2009
2010         /* Enable all queues which have been configured */
2011         ret = i40e_dev_switch_queues(pf, TRUE);
2012         if (ret != I40E_SUCCESS) {
2013                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2014                 goto err_up;
2015         }
2016
2017         /* Enable receiving broadcast packets */
2018         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2019         if (ret != I40E_SUCCESS)
2020                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2021
2022         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2023                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2024                                                 true, NULL);
2025                 if (ret != I40E_SUCCESS)
2026                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2027         }
2028
2029         /* Enable the VLAN promiscuous mode. */
2030         if (pf->vfs) {
2031                 for (i = 0; i < pf->vf_num; i++) {
2032                         vsi = pf->vfs[i].vsi;
2033                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2034                                                      true, NULL);
2035                 }
2036         }
2037
2038         /* Apply link configure */
2039         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2040                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2041                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2042                                 ETH_LINK_SPEED_40G)) {
2043                 PMD_DRV_LOG(ERR, "Invalid link setting");
2044                 goto err_up;
2045         }
2046         ret = i40e_apply_link_speed(dev);
2047         if (I40E_SUCCESS != ret) {
2048                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2049                 goto err_up;
2050         }
2051
2052         if (!rte_intr_allow_others(intr_handle)) {
2053                 rte_intr_callback_unregister(intr_handle,
2054                                              i40e_dev_interrupt_handler,
2055                                              (void *)dev);
2056                 /* configure and enable device interrupt */
2057                 i40e_pf_config_irq0(hw, FALSE);
2058                 i40e_pf_enable_irq0(hw);
2059
2060                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2061                         PMD_INIT_LOG(INFO,
2062                                 "lsc won't enable because of no intr multiplex");
2063         } else {
2064                 ret = i40e_aq_set_phy_int_mask(hw,
2065                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2066                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2067                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2068                 if (ret != I40E_SUCCESS)
2069                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2070
2071                 /* Call get_link_info aq commond to enable/disable LSE */
2072                 i40e_dev_link_update(dev, 0);
2073         }
2074
2075         /* enable uio intr after callback register */
2076         rte_intr_enable(intr_handle);
2077
2078         i40e_filter_restore(pf);
2079
2080         if (pf->tm_conf.root && !pf->tm_conf.committed)
2081                 PMD_DRV_LOG(WARNING,
2082                             "please call hierarchy_commit() "
2083                             "before starting the port");
2084
2085         return I40E_SUCCESS;
2086
2087 err_up:
2088         i40e_dev_switch_queues(pf, FALSE);
2089         i40e_dev_clear_queues(dev);
2090
2091         return ret;
2092 }
2093
2094 static void
2095 i40e_dev_stop(struct rte_eth_dev *dev)
2096 {
2097         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2098         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099         struct i40e_vsi *main_vsi = pf->main_vsi;
2100         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2101         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2102         int i;
2103
2104         if (hw->adapter_stopped == 1)
2105                 return;
2106         /* Disable all queues */
2107         i40e_dev_switch_queues(pf, FALSE);
2108
2109         /* un-map queues with interrupt registers */
2110         i40e_vsi_disable_queues_intr(main_vsi);
2111         i40e_vsi_queues_unbind_intr(main_vsi);
2112
2113         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2114                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2115                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2116         }
2117
2118         if (pf->fdir.fdir_vsi) {
2119                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2120                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2121         }
2122         /* Clear all queues and release memory */
2123         i40e_dev_clear_queues(dev);
2124
2125         /* Set link down */
2126         i40e_dev_set_link_down(dev);
2127
2128         if (!rte_intr_allow_others(intr_handle))
2129                 /* resume to the default handler */
2130                 rte_intr_callback_register(intr_handle,
2131                                            i40e_dev_interrupt_handler,
2132                                            (void *)dev);
2133
2134         /* Clean datapath event and queue/vec mapping */
2135         rte_intr_efd_disable(intr_handle);
2136         if (intr_handle->intr_vec) {
2137                 rte_free(intr_handle->intr_vec);
2138                 intr_handle->intr_vec = NULL;
2139         }
2140
2141         /* reset hierarchy commit */
2142         pf->tm_conf.committed = false;
2143
2144         hw->adapter_stopped = 1;
2145 }
2146
2147 static void
2148 i40e_dev_close(struct rte_eth_dev *dev)
2149 {
2150         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2151         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2152         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2153         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2154         struct i40e_mirror_rule *p_mirror;
2155         uint32_t reg;
2156         int i;
2157         int ret;
2158
2159         PMD_INIT_FUNC_TRACE();
2160
2161         i40e_dev_stop(dev);
2162
2163         /* Remove all mirror rules */
2164         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2165                 ret = i40e_aq_del_mirror_rule(hw,
2166                                               pf->main_vsi->veb->seid,
2167                                               p_mirror->rule_type,
2168                                               p_mirror->entries,
2169                                               p_mirror->num_entries,
2170                                               p_mirror->id);
2171                 if (ret < 0)
2172                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2173                                     "status = %d, aq_err = %d.", ret,
2174                                     hw->aq.asq_last_status);
2175
2176                 /* remove mirror software resource anyway */
2177                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2178                 rte_free(p_mirror);
2179                 pf->nb_mirror_rule--;
2180         }
2181
2182         i40e_dev_free_queues(dev);
2183
2184         /* Disable interrupt */
2185         i40e_pf_disable_irq0(hw);
2186         rte_intr_disable(intr_handle);
2187
2188         /* shutdown and destroy the HMC */
2189         i40e_shutdown_lan_hmc(hw);
2190
2191         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2192                 i40e_vsi_release(pf->vmdq[i].vsi);
2193                 pf->vmdq[i].vsi = NULL;
2194         }
2195         rte_free(pf->vmdq);
2196         pf->vmdq = NULL;
2197
2198         /* release all the existing VSIs and VEBs */
2199         i40e_fdir_teardown(pf);
2200         i40e_vsi_release(pf->main_vsi);
2201
2202         /* shutdown the adminq */
2203         i40e_aq_queue_shutdown(hw, true);
2204         i40e_shutdown_adminq(hw);
2205
2206         i40e_res_pool_destroy(&pf->qp_pool);
2207         i40e_res_pool_destroy(&pf->msix_pool);
2208
2209         /* force a PF reset to clean anything leftover */
2210         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2211         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2212                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2213         I40E_WRITE_FLUSH(hw);
2214 }
2215
2216 /*
2217  * Reset PF device only to re-initialize resources in PMD layer
2218  */
2219 static int
2220 i40e_dev_reset(struct rte_eth_dev *dev)
2221 {
2222         int ret;
2223
2224         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2225          * its VF to make them align with it. The detailed notification
2226          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2227          * To avoid unexpected behavior in VF, currently reset of PF with
2228          * SR-IOV activation is not supported. It might be supported later.
2229          */
2230         if (dev->data->sriov.active)
2231                 return -ENOTSUP;
2232
2233         ret = eth_i40e_dev_uninit(dev);
2234         if (ret)
2235                 return ret;
2236
2237         ret = eth_i40e_dev_init(dev);
2238
2239         return ret;
2240 }
2241
2242 static void
2243 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2244 {
2245         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2246         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2247         struct i40e_vsi *vsi = pf->main_vsi;
2248         int status;
2249
2250         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2251                                                      true, NULL, true);
2252         if (status != I40E_SUCCESS)
2253                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2254
2255         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2256                                                         TRUE, NULL);
2257         if (status != I40E_SUCCESS)
2258                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2259
2260 }
2261
2262 static void
2263 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2264 {
2265         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2266         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2267         struct i40e_vsi *vsi = pf->main_vsi;
2268         int status;
2269
2270         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2271                                                      false, NULL, true);
2272         if (status != I40E_SUCCESS)
2273                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2274
2275         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2276                                                         false, NULL);
2277         if (status != I40E_SUCCESS)
2278                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2279 }
2280
2281 static void
2282 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2283 {
2284         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2285         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2286         struct i40e_vsi *vsi = pf->main_vsi;
2287         int ret;
2288
2289         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2290         if (ret != I40E_SUCCESS)
2291                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2292 }
2293
2294 static void
2295 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2296 {
2297         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2298         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2299         struct i40e_vsi *vsi = pf->main_vsi;
2300         int ret;
2301
2302         if (dev->data->promiscuous == 1)
2303                 return; /* must remain in all_multicast mode */
2304
2305         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2306                                 vsi->seid, FALSE, NULL);
2307         if (ret != I40E_SUCCESS)
2308                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2309 }
2310
2311 /*
2312  * Set device link up.
2313  */
2314 static int
2315 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2316 {
2317         /* re-apply link speed setting */
2318         return i40e_apply_link_speed(dev);
2319 }
2320
2321 /*
2322  * Set device link down.
2323  */
2324 static int
2325 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2326 {
2327         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2328         uint8_t abilities = 0;
2329         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2330
2331         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2332         return i40e_phy_conf_link(hw, abilities, speed, false);
2333 }
2334
2335 int
2336 i40e_dev_link_update(struct rte_eth_dev *dev,
2337                      int wait_to_complete)
2338 {
2339 #define CHECK_INTERVAL 100  /* 100ms */
2340 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2341         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2342         struct i40e_link_status link_status;
2343         struct rte_eth_link link, old;
2344         int status;
2345         unsigned rep_cnt = MAX_REPEAT_TIME;
2346         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2347
2348         memset(&link, 0, sizeof(link));
2349         memset(&old, 0, sizeof(old));
2350         memset(&link_status, 0, sizeof(link_status));
2351         rte_i40e_dev_atomic_read_link_status(dev, &old);
2352
2353         do {
2354                 /* Get link status information from hardware */
2355                 status = i40e_aq_get_link_info(hw, enable_lse,
2356                                                 &link_status, NULL);
2357                 if (status != I40E_SUCCESS) {
2358                         link.link_speed = ETH_SPEED_NUM_100M;
2359                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2360                         PMD_DRV_LOG(ERR, "Failed to get link info");
2361                         goto out;
2362                 }
2363
2364                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2365                 if (!wait_to_complete || link.link_status)
2366                         break;
2367
2368                 rte_delay_ms(CHECK_INTERVAL);
2369         } while (--rep_cnt);
2370
2371         if (!link.link_status)
2372                 goto out;
2373
2374         /* i40e uses full duplex only */
2375         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2376
2377         /* Parse the link status */
2378         switch (link_status.link_speed) {
2379         case I40E_LINK_SPEED_100MB:
2380                 link.link_speed = ETH_SPEED_NUM_100M;
2381                 break;
2382         case I40E_LINK_SPEED_1GB:
2383                 link.link_speed = ETH_SPEED_NUM_1G;
2384                 break;
2385         case I40E_LINK_SPEED_10GB:
2386                 link.link_speed = ETH_SPEED_NUM_10G;
2387                 break;
2388         case I40E_LINK_SPEED_20GB:
2389                 link.link_speed = ETH_SPEED_NUM_20G;
2390                 break;
2391         case I40E_LINK_SPEED_25GB:
2392                 link.link_speed = ETH_SPEED_NUM_25G;
2393                 break;
2394         case I40E_LINK_SPEED_40GB:
2395                 link.link_speed = ETH_SPEED_NUM_40G;
2396                 break;
2397         default:
2398                 link.link_speed = ETH_SPEED_NUM_100M;
2399                 break;
2400         }
2401
2402         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2403                         ETH_LINK_SPEED_FIXED);
2404
2405 out:
2406         rte_i40e_dev_atomic_write_link_status(dev, &link);
2407         if (link.link_status == old.link_status)
2408                 return -1;
2409
2410         i40e_notify_all_vfs_link_status(dev);
2411
2412         return 0;
2413 }
2414
2415 /* Get all the statistics of a VSI */
2416 void
2417 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2418 {
2419         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2420         struct i40e_eth_stats *nes = &vsi->eth_stats;
2421         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2422         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2423
2424         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2425                             vsi->offset_loaded, &oes->rx_bytes,
2426                             &nes->rx_bytes);
2427         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2428                             vsi->offset_loaded, &oes->rx_unicast,
2429                             &nes->rx_unicast);
2430         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2431                             vsi->offset_loaded, &oes->rx_multicast,
2432                             &nes->rx_multicast);
2433         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2434                             vsi->offset_loaded, &oes->rx_broadcast,
2435                             &nes->rx_broadcast);
2436         /* exclude CRC bytes */
2437         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2438                 nes->rx_broadcast) * ETHER_CRC_LEN;
2439
2440         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2441                             &oes->rx_discards, &nes->rx_discards);
2442         /* GLV_REPC not supported */
2443         /* GLV_RMPC not supported */
2444         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2445                             &oes->rx_unknown_protocol,
2446                             &nes->rx_unknown_protocol);
2447         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2448                             vsi->offset_loaded, &oes->tx_bytes,
2449                             &nes->tx_bytes);
2450         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2451                             vsi->offset_loaded, &oes->tx_unicast,
2452                             &nes->tx_unicast);
2453         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2454                             vsi->offset_loaded, &oes->tx_multicast,
2455                             &nes->tx_multicast);
2456         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2457                             vsi->offset_loaded,  &oes->tx_broadcast,
2458                             &nes->tx_broadcast);
2459         /* GLV_TDPC not supported */
2460         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2461                             &oes->tx_errors, &nes->tx_errors);
2462         vsi->offset_loaded = true;
2463
2464         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2465                     vsi->vsi_id);
2466         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2467         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2468         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2469         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2470         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2471         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2472                     nes->rx_unknown_protocol);
2473         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2474         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2475         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2476         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2477         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2478         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2479         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2480                     vsi->vsi_id);
2481 }
2482
2483 static void
2484 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2485 {
2486         unsigned int i;
2487         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2488         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2489
2490         /* Get rx/tx bytes of internal transfer packets */
2491         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2492                         I40E_GLV_GORCL(hw->port),
2493                         pf->offset_loaded,
2494                         &pf->internal_stats_offset.rx_bytes,
2495                         &pf->internal_stats.rx_bytes);
2496
2497         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2498                         I40E_GLV_GOTCL(hw->port),
2499                         pf->offset_loaded,
2500                         &pf->internal_stats_offset.tx_bytes,
2501                         &pf->internal_stats.tx_bytes);
2502         /* Get total internal rx packet count */
2503         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2504                             I40E_GLV_UPRCL(hw->port),
2505                             pf->offset_loaded,
2506                             &pf->internal_stats_offset.rx_unicast,
2507                             &pf->internal_stats.rx_unicast);
2508         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2509                             I40E_GLV_MPRCL(hw->port),
2510                             pf->offset_loaded,
2511                             &pf->internal_stats_offset.rx_multicast,
2512                             &pf->internal_stats.rx_multicast);
2513         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2514                             I40E_GLV_BPRCL(hw->port),
2515                             pf->offset_loaded,
2516                             &pf->internal_stats_offset.rx_broadcast,
2517                             &pf->internal_stats.rx_broadcast);
2518
2519         /* exclude CRC size */
2520         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2521                 pf->internal_stats.rx_multicast +
2522                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2523
2524         /* Get statistics of struct i40e_eth_stats */
2525         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2526                             I40E_GLPRT_GORCL(hw->port),
2527                             pf->offset_loaded, &os->eth.rx_bytes,
2528                             &ns->eth.rx_bytes);
2529         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2530                             I40E_GLPRT_UPRCL(hw->port),
2531                             pf->offset_loaded, &os->eth.rx_unicast,
2532                             &ns->eth.rx_unicast);
2533         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2534                             I40E_GLPRT_MPRCL(hw->port),
2535                             pf->offset_loaded, &os->eth.rx_multicast,
2536                             &ns->eth.rx_multicast);
2537         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2538                             I40E_GLPRT_BPRCL(hw->port),
2539                             pf->offset_loaded, &os->eth.rx_broadcast,
2540                             &ns->eth.rx_broadcast);
2541         /* Workaround: CRC size should not be included in byte statistics,
2542          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2543          */
2544         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2545                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2546
2547         /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2548          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2549          * value.
2550          */
2551         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2552                 ns->eth.rx_bytes = 0;
2553         /* exlude internal rx bytes */
2554         else
2555                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2556
2557         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2558                             pf->offset_loaded, &os->eth.rx_discards,
2559                             &ns->eth.rx_discards);
2560         /* GLPRT_REPC not supported */
2561         /* GLPRT_RMPC not supported */
2562         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2563                             pf->offset_loaded,
2564                             &os->eth.rx_unknown_protocol,
2565                             &ns->eth.rx_unknown_protocol);
2566         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2567                             I40E_GLPRT_GOTCL(hw->port),
2568                             pf->offset_loaded, &os->eth.tx_bytes,
2569                             &ns->eth.tx_bytes);
2570         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2571                             I40E_GLPRT_UPTCL(hw->port),
2572                             pf->offset_loaded, &os->eth.tx_unicast,
2573                             &ns->eth.tx_unicast);
2574         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2575                             I40E_GLPRT_MPTCL(hw->port),
2576                             pf->offset_loaded, &os->eth.tx_multicast,
2577                             &ns->eth.tx_multicast);
2578         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2579                             I40E_GLPRT_BPTCL(hw->port),
2580                             pf->offset_loaded, &os->eth.tx_broadcast,
2581                             &ns->eth.tx_broadcast);
2582         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2583                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2584
2585         /* exclude internal tx bytes */
2586         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2587                 ns->eth.tx_bytes = 0;
2588         else
2589                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2590
2591         /* GLPRT_TEPC not supported */
2592
2593         /* additional port specific stats */
2594         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2595                             pf->offset_loaded, &os->tx_dropped_link_down,
2596                             &ns->tx_dropped_link_down);
2597         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2598                             pf->offset_loaded, &os->crc_errors,
2599                             &ns->crc_errors);
2600         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2601                             pf->offset_loaded, &os->illegal_bytes,
2602                             &ns->illegal_bytes);
2603         /* GLPRT_ERRBC not supported */
2604         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2605                             pf->offset_loaded, &os->mac_local_faults,
2606                             &ns->mac_local_faults);
2607         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2608                             pf->offset_loaded, &os->mac_remote_faults,
2609                             &ns->mac_remote_faults);
2610         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2611                             pf->offset_loaded, &os->rx_length_errors,
2612                             &ns->rx_length_errors);
2613         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2614                             pf->offset_loaded, &os->link_xon_rx,
2615                             &ns->link_xon_rx);
2616         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2617                             pf->offset_loaded, &os->link_xoff_rx,
2618                             &ns->link_xoff_rx);
2619         for (i = 0; i < 8; i++) {
2620                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2621                                     pf->offset_loaded,
2622                                     &os->priority_xon_rx[i],
2623                                     &ns->priority_xon_rx[i]);
2624                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2625                                     pf->offset_loaded,
2626                                     &os->priority_xoff_rx[i],
2627                                     &ns->priority_xoff_rx[i]);
2628         }
2629         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2630                             pf->offset_loaded, &os->link_xon_tx,
2631                             &ns->link_xon_tx);
2632         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2633                             pf->offset_loaded, &os->link_xoff_tx,
2634                             &ns->link_xoff_tx);
2635         for (i = 0; i < 8; i++) {
2636                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2637                                     pf->offset_loaded,
2638                                     &os->priority_xon_tx[i],
2639                                     &ns->priority_xon_tx[i]);
2640                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2641                                     pf->offset_loaded,
2642                                     &os->priority_xoff_tx[i],
2643                                     &ns->priority_xoff_tx[i]);
2644                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2645                                     pf->offset_loaded,
2646                                     &os->priority_xon_2_xoff[i],
2647                                     &ns->priority_xon_2_xoff[i]);
2648         }
2649         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2650                             I40E_GLPRT_PRC64L(hw->port),
2651                             pf->offset_loaded, &os->rx_size_64,
2652                             &ns->rx_size_64);
2653         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2654                             I40E_GLPRT_PRC127L(hw->port),
2655                             pf->offset_loaded, &os->rx_size_127,
2656                             &ns->rx_size_127);
2657         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2658                             I40E_GLPRT_PRC255L(hw->port),
2659                             pf->offset_loaded, &os->rx_size_255,
2660                             &ns->rx_size_255);
2661         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2662                             I40E_GLPRT_PRC511L(hw->port),
2663                             pf->offset_loaded, &os->rx_size_511,
2664                             &ns->rx_size_511);
2665         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2666                             I40E_GLPRT_PRC1023L(hw->port),
2667                             pf->offset_loaded, &os->rx_size_1023,
2668                             &ns->rx_size_1023);
2669         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2670                             I40E_GLPRT_PRC1522L(hw->port),
2671                             pf->offset_loaded, &os->rx_size_1522,
2672                             &ns->rx_size_1522);
2673         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2674                             I40E_GLPRT_PRC9522L(hw->port),
2675                             pf->offset_loaded, &os->rx_size_big,
2676                             &ns->rx_size_big);
2677         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2678                             pf->offset_loaded, &os->rx_undersize,
2679                             &ns->rx_undersize);
2680         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2681                             pf->offset_loaded, &os->rx_fragments,
2682                             &ns->rx_fragments);
2683         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2684                             pf->offset_loaded, &os->rx_oversize,
2685                             &ns->rx_oversize);
2686         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2687                             pf->offset_loaded, &os->rx_jabber,
2688                             &ns->rx_jabber);
2689         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2690                             I40E_GLPRT_PTC64L(hw->port),
2691                             pf->offset_loaded, &os->tx_size_64,
2692                             &ns->tx_size_64);
2693         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2694                             I40E_GLPRT_PTC127L(hw->port),
2695                             pf->offset_loaded, &os->tx_size_127,
2696                             &ns->tx_size_127);
2697         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2698                             I40E_GLPRT_PTC255L(hw->port),
2699                             pf->offset_loaded, &os->tx_size_255,
2700                             &ns->tx_size_255);
2701         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2702                             I40E_GLPRT_PTC511L(hw->port),
2703                             pf->offset_loaded, &os->tx_size_511,
2704                             &ns->tx_size_511);
2705         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2706                             I40E_GLPRT_PTC1023L(hw->port),
2707                             pf->offset_loaded, &os->tx_size_1023,
2708                             &ns->tx_size_1023);
2709         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2710                             I40E_GLPRT_PTC1522L(hw->port),
2711                             pf->offset_loaded, &os->tx_size_1522,
2712                             &ns->tx_size_1522);
2713         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2714                             I40E_GLPRT_PTC9522L(hw->port),
2715                             pf->offset_loaded, &os->tx_size_big,
2716                             &ns->tx_size_big);
2717         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2718                            pf->offset_loaded,
2719                            &os->fd_sb_match, &ns->fd_sb_match);
2720         /* GLPRT_MSPDC not supported */
2721         /* GLPRT_XEC not supported */
2722
2723         pf->offset_loaded = true;
2724
2725         if (pf->main_vsi)
2726                 i40e_update_vsi_stats(pf->main_vsi);
2727 }
2728
2729 /* Get all statistics of a port */
2730 static void
2731 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2732 {
2733         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2734         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2735         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2736         unsigned i;
2737
2738         /* call read registers - updates values, now write them to struct */
2739         i40e_read_stats_registers(pf, hw);
2740
2741         stats->ipackets = ns->eth.rx_unicast +
2742                         ns->eth.rx_multicast +
2743                         ns->eth.rx_broadcast -
2744                         ns->eth.rx_discards -
2745                         pf->main_vsi->eth_stats.rx_discards;
2746         stats->opackets = ns->eth.tx_unicast +
2747                         ns->eth.tx_multicast +
2748                         ns->eth.tx_broadcast;
2749         stats->ibytes   = ns->eth.rx_bytes;
2750         stats->obytes   = ns->eth.tx_bytes;
2751         stats->oerrors  = ns->eth.tx_errors +
2752                         pf->main_vsi->eth_stats.tx_errors;
2753
2754         /* Rx Errors */
2755         stats->imissed  = ns->eth.rx_discards +
2756                         pf->main_vsi->eth_stats.rx_discards;
2757         stats->ierrors  = ns->crc_errors +
2758                         ns->rx_length_errors + ns->rx_undersize +
2759                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2760
2761         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2762         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2763         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2764         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2765         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2766         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2767         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2768                     ns->eth.rx_unknown_protocol);
2769         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2770         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2771         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2772         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2773         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2774         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2775
2776         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2777                     ns->tx_dropped_link_down);
2778         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2779         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2780                     ns->illegal_bytes);
2781         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2782         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2783                     ns->mac_local_faults);
2784         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2785                     ns->mac_remote_faults);
2786         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2787                     ns->rx_length_errors);
2788         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2789         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2790         for (i = 0; i < 8; i++) {
2791                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2792                                 i, ns->priority_xon_rx[i]);
2793                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2794                                 i, ns->priority_xoff_rx[i]);
2795         }
2796         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2797         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2798         for (i = 0; i < 8; i++) {
2799                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2800                                 i, ns->priority_xon_tx[i]);
2801                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2802                                 i, ns->priority_xoff_tx[i]);
2803                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2804                                 i, ns->priority_xon_2_xoff[i]);
2805         }
2806         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2807         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2808         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2809         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2810         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2811         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2812         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2813         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2814         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2815         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2816         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2817         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2818         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2819         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2820         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2821         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2822         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2823         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2824         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2825                         ns->mac_short_packet_dropped);
2826         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2827                     ns->checksum_error);
2828         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2829         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2830 }
2831
2832 /* Reset the statistics */
2833 static void
2834 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2835 {
2836         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2837         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2838
2839         /* Mark PF and VSI stats to update the offset, aka "reset" */
2840         pf->offset_loaded = false;
2841         if (pf->main_vsi)
2842                 pf->main_vsi->offset_loaded = false;
2843
2844         /* read the stats, reading current register values into offset */
2845         i40e_read_stats_registers(pf, hw);
2846 }
2847
2848 static uint32_t
2849 i40e_xstats_calc_num(void)
2850 {
2851         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2852                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2853                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2854 }
2855
2856 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2857                                      struct rte_eth_xstat_name *xstats_names,
2858                                      __rte_unused unsigned limit)
2859 {
2860         unsigned count = 0;
2861         unsigned i, prio;
2862
2863         if (xstats_names == NULL)
2864                 return i40e_xstats_calc_num();
2865
2866         /* Note: limit checked in rte_eth_xstats_names() */
2867
2868         /* Get stats from i40e_eth_stats struct */
2869         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2870                 snprintf(xstats_names[count].name,
2871                          sizeof(xstats_names[count].name),
2872                          "%s", rte_i40e_stats_strings[i].name);
2873                 count++;
2874         }
2875
2876         /* Get individiual stats from i40e_hw_port struct */
2877         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2878                 snprintf(xstats_names[count].name,
2879                         sizeof(xstats_names[count].name),
2880                          "%s", rte_i40e_hw_port_strings[i].name);
2881                 count++;
2882         }
2883
2884         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2885                 for (prio = 0; prio < 8; prio++) {
2886                         snprintf(xstats_names[count].name,
2887                                  sizeof(xstats_names[count].name),
2888                                  "rx_priority%u_%s", prio,
2889                                  rte_i40e_rxq_prio_strings[i].name);
2890                         count++;
2891                 }
2892         }
2893
2894         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2895                 for (prio = 0; prio < 8; prio++) {
2896                         snprintf(xstats_names[count].name,
2897                                  sizeof(xstats_names[count].name),
2898                                  "tx_priority%u_%s", prio,
2899                                  rte_i40e_txq_prio_strings[i].name);
2900                         count++;
2901                 }
2902         }
2903         return count;
2904 }
2905
2906 static int
2907 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2908                     unsigned n)
2909 {
2910         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2911         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2912         unsigned i, count, prio;
2913         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2914
2915         count = i40e_xstats_calc_num();
2916         if (n < count)
2917                 return count;
2918
2919         i40e_read_stats_registers(pf, hw);
2920
2921         if (xstats == NULL)
2922                 return 0;
2923
2924         count = 0;
2925
2926         /* Get stats from i40e_eth_stats struct */
2927         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2928                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2929                         rte_i40e_stats_strings[i].offset);
2930                 xstats[count].id = count;
2931                 count++;
2932         }
2933
2934         /* Get individiual stats from i40e_hw_port struct */
2935         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2936                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2937                         rte_i40e_hw_port_strings[i].offset);
2938                 xstats[count].id = count;
2939                 count++;
2940         }
2941
2942         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2943                 for (prio = 0; prio < 8; prio++) {
2944                         xstats[count].value =
2945                                 *(uint64_t *)(((char *)hw_stats) +
2946                                 rte_i40e_rxq_prio_strings[i].offset +
2947                                 (sizeof(uint64_t) * prio));
2948                         xstats[count].id = count;
2949                         count++;
2950                 }
2951         }
2952
2953         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2954                 for (prio = 0; prio < 8; prio++) {
2955                         xstats[count].value =
2956                                 *(uint64_t *)(((char *)hw_stats) +
2957                                 rte_i40e_txq_prio_strings[i].offset +
2958                                 (sizeof(uint64_t) * prio));
2959                         xstats[count].id = count;
2960                         count++;
2961                 }
2962         }
2963
2964         return count;
2965 }
2966
2967 static int
2968 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2969                                  __rte_unused uint16_t queue_id,
2970                                  __rte_unused uint8_t stat_idx,
2971                                  __rte_unused uint8_t is_rx)
2972 {
2973         PMD_INIT_FUNC_TRACE();
2974
2975         return -ENOSYS;
2976 }
2977
2978 static int
2979 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2980 {
2981         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2982         u32 full_ver;
2983         u8 ver, patch;
2984         u16 build;
2985         int ret;
2986
2987         full_ver = hw->nvm.oem_ver;
2988         ver = (u8)(full_ver >> 24);
2989         build = (u16)((full_ver >> 8) & 0xffff);
2990         patch = (u8)(full_ver & 0xff);
2991
2992         ret = snprintf(fw_version, fw_size,
2993                  "%d.%d%d 0x%08x %d.%d.%d",
2994                  ((hw->nvm.version >> 12) & 0xf),
2995                  ((hw->nvm.version >> 4) & 0xff),
2996                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2997                  ver, build, patch);
2998
2999         ret += 1; /* add the size of '\0' */
3000         if (fw_size < (u32)ret)
3001                 return ret;
3002         else
3003                 return 0;
3004 }
3005
3006 static void
3007 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3008 {
3009         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3010         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3011         struct i40e_vsi *vsi = pf->main_vsi;
3012         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3013
3014         dev_info->pci_dev = pci_dev;
3015         dev_info->max_rx_queues = vsi->nb_qps;
3016         dev_info->max_tx_queues = vsi->nb_qps;
3017         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3018         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3019         dev_info->max_mac_addrs = vsi->max_macaddrs;
3020         dev_info->max_vfs = pci_dev->max_vfs;
3021         dev_info->rx_offload_capa =
3022                 DEV_RX_OFFLOAD_VLAN_STRIP |
3023                 DEV_RX_OFFLOAD_QINQ_STRIP |
3024                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3025                 DEV_RX_OFFLOAD_UDP_CKSUM |
3026                 DEV_RX_OFFLOAD_TCP_CKSUM;
3027         dev_info->tx_offload_capa =
3028                 DEV_TX_OFFLOAD_VLAN_INSERT |
3029                 DEV_TX_OFFLOAD_QINQ_INSERT |
3030                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3031                 DEV_TX_OFFLOAD_UDP_CKSUM |
3032                 DEV_TX_OFFLOAD_TCP_CKSUM |
3033                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3034                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3035                 DEV_TX_OFFLOAD_TCP_TSO |
3036                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3037                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3038                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3039                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3040         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3041                                                 sizeof(uint32_t);
3042         dev_info->reta_size = pf->hash_lut_size;
3043         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3044
3045         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3046                 .rx_thresh = {
3047                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3048                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3049                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3050                 },
3051                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3052                 .rx_drop_en = 0,
3053         };
3054
3055         dev_info->default_txconf = (struct rte_eth_txconf) {
3056                 .tx_thresh = {
3057                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3058                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3059                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3060                 },
3061                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3062                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3063                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3064                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3065         };
3066
3067         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3068                 .nb_max = I40E_MAX_RING_DESC,
3069                 .nb_min = I40E_MIN_RING_DESC,
3070                 .nb_align = I40E_ALIGN_RING_DESC,
3071         };
3072
3073         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3074                 .nb_max = I40E_MAX_RING_DESC,
3075                 .nb_min = I40E_MIN_RING_DESC,
3076                 .nb_align = I40E_ALIGN_RING_DESC,
3077                 .nb_seg_max = I40E_TX_MAX_SEG,
3078                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3079         };
3080
3081         if (pf->flags & I40E_FLAG_VMDQ) {
3082                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3083                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3084                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3085                                                 pf->max_nb_vmdq_vsi;
3086                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3087                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3088                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3089         }
3090
3091         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3092                 /* For XL710 */
3093                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3094         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3095                 /* For XXV710 */
3096                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3097         else
3098                 /* For X710 */
3099                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3100 }
3101
3102 static int
3103 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3104 {
3105         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3106         struct i40e_vsi *vsi = pf->main_vsi;
3107         PMD_INIT_FUNC_TRACE();
3108
3109         if (on)
3110                 return i40e_vsi_add_vlan(vsi, vlan_id);
3111         else
3112                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3113 }
3114
3115 static int
3116 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3117                                 enum rte_vlan_type vlan_type,
3118                                 uint16_t tpid, int qinq)
3119 {
3120         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3121         uint64_t reg_r = 0;
3122         uint64_t reg_w = 0;
3123         uint16_t reg_id = 3;
3124         int ret;
3125
3126         if (qinq) {
3127                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3128                         reg_id = 2;
3129         }
3130
3131         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3132                                           &reg_r, NULL);
3133         if (ret != I40E_SUCCESS) {
3134                 PMD_DRV_LOG(ERR,
3135                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3136                            reg_id);
3137                 return -EIO;
3138         }
3139         PMD_DRV_LOG(DEBUG,
3140                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3141                     reg_id, reg_r);
3142
3143         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3144         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3145         if (reg_r == reg_w) {
3146                 PMD_DRV_LOG(DEBUG, "No need to write");
3147                 return 0;
3148         }
3149
3150         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3151                                            reg_w, NULL);
3152         if (ret != I40E_SUCCESS) {
3153                 PMD_DRV_LOG(ERR,
3154                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3155                             reg_id);
3156                 return -EIO;
3157         }
3158         PMD_DRV_LOG(DEBUG,
3159                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3160                     reg_w, reg_id);
3161
3162         return 0;
3163 }
3164
3165 static int
3166 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3167                    enum rte_vlan_type vlan_type,
3168                    uint16_t tpid)
3169 {
3170         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3171         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3172         int ret = 0;
3173
3174         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3175              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3176             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3177                 PMD_DRV_LOG(ERR,
3178                             "Unsupported vlan type.");
3179                 return -EINVAL;
3180         }
3181         /* 802.1ad frames ability is added in NVM API 1.7*/
3182         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3183                 if (qinq) {
3184                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3185                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3186                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3187                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3188                 } else {
3189                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3190                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3191                 }
3192                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3193                 if (ret != I40E_SUCCESS) {
3194                         PMD_DRV_LOG(ERR,
3195                                     "Set switch config failed aq_err: %d",
3196                                     hw->aq.asq_last_status);
3197                         ret = -EIO;
3198                 }
3199         } else
3200                 /* If NVM API < 1.7, keep the register setting */
3201                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3202                                                       tpid, qinq);
3203
3204         return ret;
3205 }
3206
3207 static void
3208 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3209 {
3210         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3211         struct i40e_vsi *vsi = pf->main_vsi;
3212
3213         if (mask & ETH_VLAN_FILTER_MASK) {
3214                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3215                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3216                 else
3217                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3218         }
3219
3220         if (mask & ETH_VLAN_STRIP_MASK) {
3221                 /* Enable or disable VLAN stripping */
3222                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3223                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3224                 else
3225                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3226         }
3227
3228         if (mask & ETH_VLAN_EXTEND_MASK) {
3229                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3230                         i40e_vsi_config_double_vlan(vsi, TRUE);
3231                         /* Set global registers with default ethertype. */
3232                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3233                                            ETHER_TYPE_VLAN);
3234                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3235                                            ETHER_TYPE_VLAN);
3236                 }
3237                 else
3238                         i40e_vsi_config_double_vlan(vsi, FALSE);
3239         }
3240 }
3241
3242 static void
3243 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3244                           __rte_unused uint16_t queue,
3245                           __rte_unused int on)
3246 {
3247         PMD_INIT_FUNC_TRACE();
3248 }
3249
3250 static int
3251 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3252 {
3253         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3254         struct i40e_vsi *vsi = pf->main_vsi;
3255         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3256         struct i40e_vsi_vlan_pvid_info info;
3257
3258         memset(&info, 0, sizeof(info));
3259         info.on = on;
3260         if (info.on)
3261                 info.config.pvid = pvid;
3262         else {
3263                 info.config.reject.tagged =
3264                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3265                 info.config.reject.untagged =
3266                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3267         }
3268
3269         return i40e_vsi_vlan_pvid_set(vsi, &info);
3270 }
3271
3272 static int
3273 i40e_dev_led_on(struct rte_eth_dev *dev)
3274 {
3275         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3276         uint32_t mode = i40e_led_get(hw);
3277
3278         if (mode == 0)
3279                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3280
3281         return 0;
3282 }
3283
3284 static int
3285 i40e_dev_led_off(struct rte_eth_dev *dev)
3286 {
3287         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3288         uint32_t mode = i40e_led_get(hw);
3289
3290         if (mode != 0)
3291                 i40e_led_set(hw, 0, false);
3292
3293         return 0;
3294 }
3295
3296 static int
3297 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3298 {
3299         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3301
3302         fc_conf->pause_time = pf->fc_conf.pause_time;
3303
3304         /* read out from register, in case they are modified by other port */
3305         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3306                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3307         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3308                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3309
3310         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3311         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3312
3313          /* Return current mode according to actual setting*/
3314         switch (hw->fc.current_mode) {
3315         case I40E_FC_FULL:
3316                 fc_conf->mode = RTE_FC_FULL;
3317                 break;
3318         case I40E_FC_TX_PAUSE:
3319                 fc_conf->mode = RTE_FC_TX_PAUSE;
3320                 break;
3321         case I40E_FC_RX_PAUSE:
3322                 fc_conf->mode = RTE_FC_RX_PAUSE;
3323                 break;
3324         case I40E_FC_NONE:
3325         default:
3326                 fc_conf->mode = RTE_FC_NONE;
3327         };
3328
3329         return 0;
3330 }
3331
3332 static int
3333 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3334 {
3335         uint32_t mflcn_reg, fctrl_reg, reg;
3336         uint32_t max_high_water;
3337         uint8_t i, aq_failure;
3338         int err;
3339         struct i40e_hw *hw;
3340         struct i40e_pf *pf;
3341         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3342                 [RTE_FC_NONE] = I40E_FC_NONE,
3343                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3344                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3345                 [RTE_FC_FULL] = I40E_FC_FULL
3346         };
3347
3348         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3349
3350         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3351         if ((fc_conf->high_water > max_high_water) ||
3352                         (fc_conf->high_water < fc_conf->low_water)) {
3353                 PMD_INIT_LOG(ERR,
3354                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3355                         max_high_water);
3356                 return -EINVAL;
3357         }
3358
3359         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3360         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3361         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3362
3363         pf->fc_conf.pause_time = fc_conf->pause_time;
3364         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3365         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3366
3367         PMD_INIT_FUNC_TRACE();
3368
3369         /* All the link flow control related enable/disable register
3370          * configuration is handle by the F/W
3371          */
3372         err = i40e_set_fc(hw, &aq_failure, true);
3373         if (err < 0)
3374                 return -ENOSYS;
3375
3376         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3377                 /* Configure flow control refresh threshold,
3378                  * the value for stat_tx_pause_refresh_timer[8]
3379                  * is used for global pause operation.
3380                  */
3381
3382                 I40E_WRITE_REG(hw,
3383                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3384                                pf->fc_conf.pause_time);
3385
3386                 /* configure the timer value included in transmitted pause
3387                  * frame,
3388                  * the value for stat_tx_pause_quanta[8] is used for global
3389                  * pause operation
3390                  */
3391                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3392                                pf->fc_conf.pause_time);
3393
3394                 fctrl_reg = I40E_READ_REG(hw,
3395                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3396
3397                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3398                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3399                 else
3400                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3401
3402                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3403                                fctrl_reg);
3404         } else {
3405                 /* Configure pause time (2 TCs per register) */
3406                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3407                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3408                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3409
3410                 /* Configure flow control refresh threshold value */
3411                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3412                                pf->fc_conf.pause_time / 2);
3413
3414                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3415
3416                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3417                  *depending on configuration
3418                  */
3419                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3420                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3421                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3422                 } else {
3423                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3424                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3425                 }
3426
3427                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3428         }
3429
3430         /* config the water marker both based on the packets and bytes */
3431         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3432                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3433                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3434         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3435                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3436                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3437         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3438                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3439                        << I40E_KILOSHIFT);
3440         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3441                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3442                        << I40E_KILOSHIFT);
3443
3444         I40E_WRITE_FLUSH(hw);
3445
3446         return 0;
3447 }
3448
3449 static int
3450 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3451                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3452 {
3453         PMD_INIT_FUNC_TRACE();
3454
3455         return -ENOSYS;
3456 }
3457
3458 /* Add a MAC address, and update filters */
3459 static int
3460 i40e_macaddr_add(struct rte_eth_dev *dev,
3461                  struct ether_addr *mac_addr,
3462                  __rte_unused uint32_t index,
3463                  uint32_t pool)
3464 {
3465         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3466         struct i40e_mac_filter_info mac_filter;
3467         struct i40e_vsi *vsi;
3468         int ret;
3469
3470         /* If VMDQ not enabled or configured, return */
3471         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3472                           !pf->nb_cfg_vmdq_vsi)) {
3473                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3474                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3475                         pool);
3476                 return -ENOTSUP;
3477         }
3478
3479         if (pool > pf->nb_cfg_vmdq_vsi) {
3480                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3481                                 pool, pf->nb_cfg_vmdq_vsi);
3482                 return -EINVAL;
3483         }
3484
3485         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3486         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3487                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3488         else
3489                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3490
3491         if (pool == 0)
3492                 vsi = pf->main_vsi;
3493         else
3494                 vsi = pf->vmdq[pool - 1].vsi;
3495
3496         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3497         if (ret != I40E_SUCCESS) {
3498                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3499                 return -ENODEV;
3500         }
3501         return 0;
3502 }
3503
3504 /* Remove a MAC address, and update filters */
3505 static void
3506 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3507 {
3508         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3509         struct i40e_vsi *vsi;
3510         struct rte_eth_dev_data *data = dev->data;
3511         struct ether_addr *macaddr;
3512         int ret;
3513         uint32_t i;
3514         uint64_t pool_sel;
3515
3516         macaddr = &(data->mac_addrs[index]);
3517
3518         pool_sel = dev->data->mac_pool_sel[index];
3519
3520         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3521                 if (pool_sel & (1ULL << i)) {
3522                         if (i == 0)
3523                                 vsi = pf->main_vsi;
3524                         else {
3525                                 /* No VMDQ pool enabled or configured */
3526                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3527                                         (i > pf->nb_cfg_vmdq_vsi)) {
3528                                         PMD_DRV_LOG(ERR,
3529                                                 "No VMDQ pool enabled/configured");
3530                                         return;
3531                                 }
3532                                 vsi = pf->vmdq[i - 1].vsi;
3533                         }
3534                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3535
3536                         if (ret) {
3537                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3538                                 return;
3539                         }
3540                 }
3541         }
3542 }
3543
3544 /* Set perfect match or hash match of MAC and VLAN for a VF */
3545 static int
3546 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3547                  struct rte_eth_mac_filter *filter,
3548                  bool add)
3549 {
3550         struct i40e_hw *hw;
3551         struct i40e_mac_filter_info mac_filter;
3552         struct ether_addr old_mac;
3553         struct ether_addr *new_mac;
3554         struct i40e_pf_vf *vf = NULL;
3555         uint16_t vf_id;
3556         int ret;
3557
3558         if (pf == NULL) {
3559                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3560                 return -EINVAL;
3561         }
3562         hw = I40E_PF_TO_HW(pf);
3563
3564         if (filter == NULL) {
3565                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3566                 return -EINVAL;
3567         }
3568
3569         new_mac = &filter->mac_addr;
3570
3571         if (is_zero_ether_addr(new_mac)) {
3572                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3573                 return -EINVAL;
3574         }
3575
3576         vf_id = filter->dst_id;
3577
3578         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3579                 PMD_DRV_LOG(ERR, "Invalid argument.");
3580                 return -EINVAL;
3581         }
3582         vf = &pf->vfs[vf_id];
3583
3584         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3585                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3586                 return -EINVAL;
3587         }
3588
3589         if (add) {
3590                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3591                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3592                                 ETHER_ADDR_LEN);
3593                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3594                                  ETHER_ADDR_LEN);
3595
3596                 mac_filter.filter_type = filter->filter_type;
3597                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3598                 if (ret != I40E_SUCCESS) {
3599                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3600                         return -1;
3601                 }
3602                 ether_addr_copy(new_mac, &pf->dev_addr);
3603         } else {
3604                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3605                                 ETHER_ADDR_LEN);
3606                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3607                 if (ret != I40E_SUCCESS) {
3608                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3609                         return -1;
3610                 }
3611
3612                 /* Clear device address as it has been removed */
3613                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3614                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3615         }
3616
3617         return 0;
3618 }
3619
3620 /* MAC filter handle */
3621 static int
3622 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3623                 void *arg)
3624 {
3625         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3626         struct rte_eth_mac_filter *filter;
3627         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3628         int ret = I40E_NOT_SUPPORTED;
3629
3630         filter = (struct rte_eth_mac_filter *)(arg);
3631
3632         switch (filter_op) {
3633         case RTE_ETH_FILTER_NOP:
3634                 ret = I40E_SUCCESS;
3635                 break;
3636         case RTE_ETH_FILTER_ADD:
3637                 i40e_pf_disable_irq0(hw);
3638                 if (filter->is_vf)
3639                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3640                 i40e_pf_enable_irq0(hw);
3641                 break;
3642         case RTE_ETH_FILTER_DELETE:
3643                 i40e_pf_disable_irq0(hw);
3644                 if (filter->is_vf)
3645                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3646                 i40e_pf_enable_irq0(hw);
3647                 break;
3648         default:
3649                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3650                 ret = I40E_ERR_PARAM;
3651                 break;
3652         }
3653
3654         return ret;
3655 }
3656
3657 static int
3658 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3659 {
3660         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3661         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3662         int ret;
3663
3664         if (!lut)
3665                 return -EINVAL;
3666
3667         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3668                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3669                                           lut, lut_size);
3670                 if (ret) {
3671                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3672                         return ret;
3673                 }
3674         } else {
3675                 uint32_t *lut_dw = (uint32_t *)lut;
3676                 uint16_t i, lut_size_dw = lut_size / 4;
3677
3678                 for (i = 0; i < lut_size_dw; i++)
3679                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3680         }
3681
3682         return 0;
3683 }
3684
3685 static int
3686 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3687 {
3688         struct i40e_pf *pf;
3689         struct i40e_hw *hw;
3690         int ret;
3691
3692         if (!vsi || !lut)
3693                 return -EINVAL;
3694
3695         pf = I40E_VSI_TO_PF(vsi);
3696         hw = I40E_VSI_TO_HW(vsi);
3697
3698         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3699                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3700                                           lut, lut_size);
3701                 if (ret) {
3702                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3703                         return ret;
3704                 }
3705         } else {
3706                 uint32_t *lut_dw = (uint32_t *)lut;
3707                 uint16_t i, lut_size_dw = lut_size / 4;
3708
3709                 for (i = 0; i < lut_size_dw; i++)
3710                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3711                 I40E_WRITE_FLUSH(hw);
3712         }
3713
3714         return 0;
3715 }
3716
3717 static int
3718 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3719                          struct rte_eth_rss_reta_entry64 *reta_conf,
3720                          uint16_t reta_size)
3721 {
3722         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3723         uint16_t i, lut_size = pf->hash_lut_size;
3724         uint16_t idx, shift;
3725         uint8_t *lut;
3726         int ret;
3727
3728         if (reta_size != lut_size ||
3729                 reta_size > ETH_RSS_RETA_SIZE_512) {
3730                 PMD_DRV_LOG(ERR,
3731                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3732                         reta_size, lut_size);
3733                 return -EINVAL;
3734         }
3735
3736         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3737         if (!lut) {
3738                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3739                 return -ENOMEM;
3740         }
3741         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3742         if (ret)
3743                 goto out;
3744         for (i = 0; i < reta_size; i++) {
3745                 idx = i / RTE_RETA_GROUP_SIZE;
3746                 shift = i % RTE_RETA_GROUP_SIZE;
3747                 if (reta_conf[idx].mask & (1ULL << shift))
3748                         lut[i] = reta_conf[idx].reta[shift];
3749         }
3750         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3751
3752 out:
3753         rte_free(lut);
3754
3755         return ret;
3756 }
3757
3758 static int
3759 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3760                         struct rte_eth_rss_reta_entry64 *reta_conf,
3761                         uint16_t reta_size)
3762 {
3763         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3764         uint16_t i, lut_size = pf->hash_lut_size;
3765         uint16_t idx, shift;
3766         uint8_t *lut;
3767         int ret;
3768
3769         if (reta_size != lut_size ||
3770                 reta_size > ETH_RSS_RETA_SIZE_512) {
3771                 PMD_DRV_LOG(ERR,
3772                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3773                         reta_size, lut_size);
3774                 return -EINVAL;
3775         }
3776
3777         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3778         if (!lut) {
3779                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3780                 return -ENOMEM;
3781         }
3782
3783         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3784         if (ret)
3785                 goto out;
3786         for (i = 0; i < reta_size; i++) {
3787                 idx = i / RTE_RETA_GROUP_SIZE;
3788                 shift = i % RTE_RETA_GROUP_SIZE;
3789                 if (reta_conf[idx].mask & (1ULL << shift))
3790                         reta_conf[idx].reta[shift] = lut[i];
3791         }
3792
3793 out:
3794         rte_free(lut);
3795
3796         return ret;
3797 }
3798
3799 /**
3800  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3801  * @hw:   pointer to the HW structure
3802  * @mem:  pointer to mem struct to fill out
3803  * @size: size of memory requested
3804  * @alignment: what to align the allocation to
3805  **/
3806 enum i40e_status_code
3807 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3808                         struct i40e_dma_mem *mem,
3809                         u64 size,
3810                         u32 alignment)
3811 {
3812         const struct rte_memzone *mz = NULL;
3813         char z_name[RTE_MEMZONE_NAMESIZE];
3814
3815         if (!mem)
3816                 return I40E_ERR_PARAM;
3817
3818         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3819         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3820                                          alignment, RTE_PGSIZE_2M);
3821         if (!mz)
3822                 return I40E_ERR_NO_MEMORY;
3823
3824         mem->size = size;
3825         mem->va = mz->addr;
3826         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3827         mem->zone = (const void *)mz;
3828         PMD_DRV_LOG(DEBUG,
3829                 "memzone %s allocated with physical address: %"PRIu64,
3830                 mz->name, mem->pa);
3831
3832         return I40E_SUCCESS;
3833 }
3834
3835 /**
3836  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3837  * @hw:   pointer to the HW structure
3838  * @mem:  ptr to mem struct to free
3839  **/
3840 enum i40e_status_code
3841 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3842                     struct i40e_dma_mem *mem)
3843 {
3844         if (!mem)
3845                 return I40E_ERR_PARAM;
3846
3847         PMD_DRV_LOG(DEBUG,
3848                 "memzone %s to be freed with physical address: %"PRIu64,
3849                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3850         rte_memzone_free((const struct rte_memzone *)mem->zone);
3851         mem->zone = NULL;
3852         mem->va = NULL;
3853         mem->pa = (u64)0;
3854
3855         return I40E_SUCCESS;
3856 }
3857
3858 /**
3859  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3860  * @hw:   pointer to the HW structure
3861  * @mem:  pointer to mem struct to fill out
3862  * @size: size of memory requested
3863  **/
3864 enum i40e_status_code
3865 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3866                          struct i40e_virt_mem *mem,
3867                          u32 size)
3868 {
3869         if (!mem)
3870                 return I40E_ERR_PARAM;
3871
3872         mem->size = size;
3873         mem->va = rte_zmalloc("i40e", size, 0);
3874
3875         if (mem->va)
3876                 return I40E_SUCCESS;
3877         else
3878                 return I40E_ERR_NO_MEMORY;
3879 }
3880
3881 /**
3882  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3883  * @hw:   pointer to the HW structure
3884  * @mem:  pointer to mem struct to free
3885  **/
3886 enum i40e_status_code
3887 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3888                      struct i40e_virt_mem *mem)
3889 {
3890         if (!mem)
3891                 return I40E_ERR_PARAM;
3892
3893         rte_free(mem->va);
3894         mem->va = NULL;
3895
3896         return I40E_SUCCESS;
3897 }
3898
3899 void
3900 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3901 {
3902         rte_spinlock_init(&sp->spinlock);
3903 }
3904
3905 void
3906 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3907 {
3908         rte_spinlock_lock(&sp->spinlock);
3909 }
3910
3911 void
3912 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3913 {
3914         rte_spinlock_unlock(&sp->spinlock);
3915 }
3916
3917 void
3918 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3919 {
3920         return;
3921 }
3922
3923 /**
3924  * Get the hardware capabilities, which will be parsed
3925  * and saved into struct i40e_hw.
3926  */
3927 static int
3928 i40e_get_cap(struct i40e_hw *hw)
3929 {
3930         struct i40e_aqc_list_capabilities_element_resp *buf;
3931         uint16_t len, size = 0;
3932         int ret;
3933
3934         /* Calculate a huge enough buff for saving response data temporarily */
3935         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3936                                                 I40E_MAX_CAP_ELE_NUM;
3937         buf = rte_zmalloc("i40e", len, 0);
3938         if (!buf) {
3939                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3940                 return I40E_ERR_NO_MEMORY;
3941         }
3942
3943         /* Get, parse the capabilities and save it to hw */
3944         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3945                         i40e_aqc_opc_list_func_capabilities, NULL);
3946         if (ret != I40E_SUCCESS)
3947                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3948
3949         /* Free the temporary buffer after being used */
3950         rte_free(buf);
3951
3952         return ret;
3953 }
3954
3955 static int
3956 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3957 {
3958         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3959         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3960         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3961         uint16_t qp_count = 0, vsi_count = 0;
3962
3963         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3964                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3965                 return -EINVAL;
3966         }
3967         /* Add the parameter init for LFC */
3968         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3969         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3970         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3971
3972         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3973         pf->max_num_vsi = hw->func_caps.num_vsis;
3974         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3975         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3976         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3977
3978         /* FDir queue/VSI allocation */
3979         pf->fdir_qp_offset = 0;
3980         if (hw->func_caps.fd) {
3981                 pf->flags |= I40E_FLAG_FDIR;
3982                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3983         } else {
3984                 pf->fdir_nb_qps = 0;
3985         }
3986         qp_count += pf->fdir_nb_qps;
3987         vsi_count += 1;
3988
3989         /* LAN queue/VSI allocation */
3990         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3991         if (!hw->func_caps.rss) {
3992                 pf->lan_nb_qps = 1;
3993         } else {
3994                 pf->flags |= I40E_FLAG_RSS;
3995                 if (hw->mac.type == I40E_MAC_X722)
3996                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3997                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3998         }
3999         qp_count += pf->lan_nb_qps;
4000         vsi_count += 1;
4001
4002         /* VF queue/VSI allocation */
4003         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4004         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4005                 pf->flags |= I40E_FLAG_SRIOV;
4006                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4007                 pf->vf_num = pci_dev->max_vfs;
4008                 PMD_DRV_LOG(DEBUG,
4009                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4010                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4011         } else {
4012                 pf->vf_nb_qps = 0;
4013                 pf->vf_num = 0;
4014         }
4015         qp_count += pf->vf_nb_qps * pf->vf_num;
4016         vsi_count += pf->vf_num;
4017
4018         /* VMDq queue/VSI allocation */
4019         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4020         pf->vmdq_nb_qps = 0;
4021         pf->max_nb_vmdq_vsi = 0;
4022         if (hw->func_caps.vmdq) {
4023                 if (qp_count < hw->func_caps.num_tx_qp &&
4024                         vsi_count < hw->func_caps.num_vsis) {
4025                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4026                                 qp_count) / pf->vmdq_nb_qp_max;
4027
4028                         /* Limit the maximum number of VMDq vsi to the maximum
4029                          * ethdev can support
4030                          */
4031                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4032                                 hw->func_caps.num_vsis - vsi_count);
4033                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4034                                 ETH_64_POOLS);
4035                         if (pf->max_nb_vmdq_vsi) {
4036                                 pf->flags |= I40E_FLAG_VMDQ;
4037                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4038                                 PMD_DRV_LOG(DEBUG,
4039                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4040                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4041                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4042                         } else {
4043                                 PMD_DRV_LOG(INFO,
4044                                         "No enough queues left for VMDq");
4045                         }
4046                 } else {
4047                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4048                 }
4049         }
4050         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4051         vsi_count += pf->max_nb_vmdq_vsi;
4052
4053         if (hw->func_caps.dcb)
4054                 pf->flags |= I40E_FLAG_DCB;
4055
4056         if (qp_count > hw->func_caps.num_tx_qp) {
4057                 PMD_DRV_LOG(ERR,
4058                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4059                         qp_count, hw->func_caps.num_tx_qp);
4060                 return -EINVAL;
4061         }
4062         if (vsi_count > hw->func_caps.num_vsis) {
4063                 PMD_DRV_LOG(ERR,
4064                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4065                         vsi_count, hw->func_caps.num_vsis);
4066                 return -EINVAL;
4067         }
4068
4069         return 0;
4070 }
4071
4072 static int
4073 i40e_pf_get_switch_config(struct i40e_pf *pf)
4074 {
4075         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4076         struct i40e_aqc_get_switch_config_resp *switch_config;
4077         struct i40e_aqc_switch_config_element_resp *element;
4078         uint16_t start_seid = 0, num_reported;
4079         int ret;
4080
4081         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4082                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4083         if (!switch_config) {
4084                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4085                 return -ENOMEM;
4086         }
4087
4088         /* Get the switch configurations */
4089         ret = i40e_aq_get_switch_config(hw, switch_config,
4090                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4091         if (ret != I40E_SUCCESS) {
4092                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4093                 goto fail;
4094         }
4095         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4096         if (num_reported != 1) { /* The number should be 1 */
4097                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4098                 goto fail;
4099         }
4100
4101         /* Parse the switch configuration elements */
4102         element = &(switch_config->element[0]);
4103         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4104                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4105                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4106         } else
4107                 PMD_DRV_LOG(INFO, "Unknown element type");
4108
4109 fail:
4110         rte_free(switch_config);
4111
4112         return ret;
4113 }
4114
4115 static int
4116 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4117                         uint32_t num)
4118 {
4119         struct pool_entry *entry;
4120
4121         if (pool == NULL || num == 0)
4122                 return -EINVAL;
4123
4124         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4125         if (entry == NULL) {
4126                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4127                 return -ENOMEM;
4128         }
4129
4130         /* queue heap initialize */
4131         pool->num_free = num;
4132         pool->num_alloc = 0;
4133         pool->base = base;
4134         LIST_INIT(&pool->alloc_list);
4135         LIST_INIT(&pool->free_list);
4136
4137         /* Initialize element  */
4138         entry->base = 0;
4139         entry->len = num;
4140
4141         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4142         return 0;
4143 }
4144
4145 static void
4146 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4147 {
4148         struct pool_entry *entry, *next_entry;
4149
4150         if (pool == NULL)
4151                 return;
4152
4153         for (entry = LIST_FIRST(&pool->alloc_list);
4154                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4155                         entry = next_entry) {
4156                 LIST_REMOVE(entry, next);
4157                 rte_free(entry);
4158         }
4159
4160         for (entry = LIST_FIRST(&pool->free_list);
4161                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4162                         entry = next_entry) {
4163                 LIST_REMOVE(entry, next);
4164                 rte_free(entry);
4165         }
4166
4167         pool->num_free = 0;
4168         pool->num_alloc = 0;
4169         pool->base = 0;
4170         LIST_INIT(&pool->alloc_list);
4171         LIST_INIT(&pool->free_list);
4172 }
4173
4174 static int
4175 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4176                        uint32_t base)
4177 {
4178         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4179         uint32_t pool_offset;
4180         int insert;
4181
4182         if (pool == NULL) {
4183                 PMD_DRV_LOG(ERR, "Invalid parameter");
4184                 return -EINVAL;
4185         }
4186
4187         pool_offset = base - pool->base;
4188         /* Lookup in alloc list */
4189         LIST_FOREACH(entry, &pool->alloc_list, next) {
4190                 if (entry->base == pool_offset) {
4191                         valid_entry = entry;
4192                         LIST_REMOVE(entry, next);
4193                         break;
4194                 }
4195         }
4196
4197         /* Not find, return */
4198         if (valid_entry == NULL) {
4199                 PMD_DRV_LOG(ERR, "Failed to find entry");
4200                 return -EINVAL;
4201         }
4202
4203         /**
4204          * Found it, move it to free list  and try to merge.
4205          * In order to make merge easier, always sort it by qbase.
4206          * Find adjacent prev and last entries.
4207          */
4208         prev = next = NULL;
4209         LIST_FOREACH(entry, &pool->free_list, next) {
4210                 if (entry->base > valid_entry->base) {
4211                         next = entry;
4212                         break;
4213                 }
4214                 prev = entry;
4215         }
4216
4217         insert = 0;
4218         /* Try to merge with next one*/
4219         if (next != NULL) {
4220                 /* Merge with next one */
4221                 if (valid_entry->base + valid_entry->len == next->base) {
4222                         next->base = valid_entry->base;
4223                         next->len += valid_entry->len;
4224                         rte_free(valid_entry);
4225                         valid_entry = next;
4226                         insert = 1;
4227                 }
4228         }
4229
4230         if (prev != NULL) {
4231                 /* Merge with previous one */
4232                 if (prev->base + prev->len == valid_entry->base) {
4233                         prev->len += valid_entry->len;
4234                         /* If it merge with next one, remove next node */
4235                         if (insert == 1) {
4236                                 LIST_REMOVE(valid_entry, next);
4237                                 rte_free(valid_entry);
4238                         } else {
4239                                 rte_free(valid_entry);
4240                                 insert = 1;
4241                         }
4242                 }
4243         }
4244
4245         /* Not find any entry to merge, insert */
4246         if (insert == 0) {
4247                 if (prev != NULL)
4248                         LIST_INSERT_AFTER(prev, valid_entry, next);
4249                 else if (next != NULL)
4250                         LIST_INSERT_BEFORE(next, valid_entry, next);
4251                 else /* It's empty list, insert to head */
4252                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4253         }
4254
4255         pool->num_free += valid_entry->len;
4256         pool->num_alloc -= valid_entry->len;
4257
4258         return 0;
4259 }
4260
4261 static int
4262 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4263                        uint16_t num)
4264 {
4265         struct pool_entry *entry, *valid_entry;
4266
4267         if (pool == NULL || num == 0) {
4268                 PMD_DRV_LOG(ERR, "Invalid parameter");
4269                 return -EINVAL;
4270         }
4271
4272         if (pool->num_free < num) {
4273                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4274                             num, pool->num_free);
4275                 return -ENOMEM;
4276         }
4277
4278         valid_entry = NULL;
4279         /* Lookup  in free list and find most fit one */
4280         LIST_FOREACH(entry, &pool->free_list, next) {
4281                 if (entry->len >= num) {
4282                         /* Find best one */
4283                         if (entry->len == num) {
4284                                 valid_entry = entry;
4285                                 break;
4286                         }
4287                         if (valid_entry == NULL || valid_entry->len > entry->len)
4288                                 valid_entry = entry;
4289                 }
4290         }
4291
4292         /* Not find one to satisfy the request, return */
4293         if (valid_entry == NULL) {
4294                 PMD_DRV_LOG(ERR, "No valid entry found");
4295                 return -ENOMEM;
4296         }
4297         /**
4298          * The entry have equal queue number as requested,
4299          * remove it from alloc_list.
4300          */
4301         if (valid_entry->len == num) {
4302                 LIST_REMOVE(valid_entry, next);
4303         } else {
4304                 /**
4305                  * The entry have more numbers than requested,
4306                  * create a new entry for alloc_list and minus its
4307                  * queue base and number in free_list.
4308                  */
4309                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4310                 if (entry == NULL) {
4311                         PMD_DRV_LOG(ERR,
4312                                 "Failed to allocate memory for resource pool");
4313                         return -ENOMEM;
4314                 }
4315                 entry->base = valid_entry->base;
4316                 entry->len = num;
4317                 valid_entry->base += num;
4318                 valid_entry->len -= num;
4319                 valid_entry = entry;
4320         }
4321
4322         /* Insert it into alloc list, not sorted */
4323         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4324
4325         pool->num_free -= valid_entry->len;
4326         pool->num_alloc += valid_entry->len;
4327
4328         return valid_entry->base + pool->base;
4329 }
4330
4331 /**
4332  * bitmap_is_subset - Check whether src2 is subset of src1
4333  **/
4334 static inline int
4335 bitmap_is_subset(uint8_t src1, uint8_t src2)
4336 {
4337         return !((src1 ^ src2) & src2);
4338 }
4339
4340 static enum i40e_status_code
4341 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4342 {
4343         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4344
4345         /* If DCB is not supported, only default TC is supported */
4346         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4347                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4348                 return I40E_NOT_SUPPORTED;
4349         }
4350
4351         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4352                 PMD_DRV_LOG(ERR,
4353                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4354                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4355                 return I40E_NOT_SUPPORTED;
4356         }
4357         return I40E_SUCCESS;
4358 }
4359
4360 int
4361 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4362                                 struct i40e_vsi_vlan_pvid_info *info)
4363 {
4364         struct i40e_hw *hw;
4365         struct i40e_vsi_context ctxt;
4366         uint8_t vlan_flags = 0;
4367         int ret;
4368
4369         if (vsi == NULL || info == NULL) {
4370                 PMD_DRV_LOG(ERR, "invalid parameters");
4371                 return I40E_ERR_PARAM;
4372         }
4373
4374         if (info->on) {
4375                 vsi->info.pvid = info->config.pvid;
4376                 /**
4377                  * If insert pvid is enabled, only tagged pkts are
4378                  * allowed to be sent out.
4379                  */
4380                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4381                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4382         } else {
4383                 vsi->info.pvid = 0;
4384                 if (info->config.reject.tagged == 0)
4385                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4386
4387                 if (info->config.reject.untagged == 0)
4388                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4389         }
4390         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4391                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4392         vsi->info.port_vlan_flags |= vlan_flags;
4393         vsi->info.valid_sections =
4394                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4395         memset(&ctxt, 0, sizeof(ctxt));
4396         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4397         ctxt.seid = vsi->seid;
4398
4399         hw = I40E_VSI_TO_HW(vsi);
4400         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4401         if (ret != I40E_SUCCESS)
4402                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4403
4404         return ret;
4405 }
4406
4407 static int
4408 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4409 {
4410         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4411         int i, ret;
4412         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4413
4414         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4415         if (ret != I40E_SUCCESS)
4416                 return ret;
4417
4418         if (!vsi->seid) {
4419                 PMD_DRV_LOG(ERR, "seid not valid");
4420                 return -EINVAL;
4421         }
4422
4423         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4424         tc_bw_data.tc_valid_bits = enabled_tcmap;
4425         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4426                 tc_bw_data.tc_bw_credits[i] =
4427                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4428
4429         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4430         if (ret != I40E_SUCCESS) {
4431                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4432                 return ret;
4433         }
4434
4435         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4436                                         sizeof(vsi->info.qs_handle));
4437         return I40E_SUCCESS;
4438 }
4439
4440 static enum i40e_status_code
4441 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4442                                  struct i40e_aqc_vsi_properties_data *info,
4443                                  uint8_t enabled_tcmap)
4444 {
4445         enum i40e_status_code ret;
4446         int i, total_tc = 0;
4447         uint16_t qpnum_per_tc, bsf, qp_idx;
4448
4449         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4450         if (ret != I40E_SUCCESS)
4451                 return ret;
4452
4453         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4454                 if (enabled_tcmap & (1 << i))
4455                         total_tc++;
4456         if (total_tc == 0)
4457                 total_tc = 1;
4458         vsi->enabled_tc = enabled_tcmap;
4459
4460         /* Number of queues per enabled TC */
4461         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4462         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4463         bsf = rte_bsf32(qpnum_per_tc);
4464
4465         /* Adjust the queue number to actual queues that can be applied */
4466         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4467                 vsi->nb_qps = qpnum_per_tc * total_tc;
4468
4469         /**
4470          * Configure TC and queue mapping parameters, for enabled TC,
4471          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4472          * default queue will serve it.
4473          */
4474         qp_idx = 0;
4475         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4476                 if (vsi->enabled_tc & (1 << i)) {
4477                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4478                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4479                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4480                         qp_idx += qpnum_per_tc;
4481                 } else
4482                         info->tc_mapping[i] = 0;
4483         }
4484
4485         /* Associate queue number with VSI */
4486         if (vsi->type == I40E_VSI_SRIOV) {
4487                 info->mapping_flags |=
4488                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4489                 for (i = 0; i < vsi->nb_qps; i++)
4490                         info->queue_mapping[i] =
4491                                 rte_cpu_to_le_16(vsi->base_queue + i);
4492         } else {
4493                 info->mapping_flags |=
4494                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4495                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4496         }
4497         info->valid_sections |=
4498                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4499
4500         return I40E_SUCCESS;
4501 }
4502
4503 static int
4504 i40e_veb_release(struct i40e_veb *veb)
4505 {
4506         struct i40e_vsi *vsi;
4507         struct i40e_hw *hw;
4508
4509         if (veb == NULL)
4510                 return -EINVAL;
4511
4512         if (!TAILQ_EMPTY(&veb->head)) {
4513                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4514                 return -EACCES;
4515         }
4516         /* associate_vsi field is NULL for floating VEB */
4517         if (veb->associate_vsi != NULL) {
4518                 vsi = veb->associate_vsi;
4519                 hw = I40E_VSI_TO_HW(vsi);
4520
4521                 vsi->uplink_seid = veb->uplink_seid;
4522                 vsi->veb = NULL;
4523         } else {
4524                 veb->associate_pf->main_vsi->floating_veb = NULL;
4525                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4526         }
4527
4528         i40e_aq_delete_element(hw, veb->seid, NULL);
4529         rte_free(veb);
4530         return I40E_SUCCESS;
4531 }
4532
4533 /* Setup a veb */
4534 static struct i40e_veb *
4535 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4536 {
4537         struct i40e_veb *veb;
4538         int ret;
4539         struct i40e_hw *hw;
4540
4541         if (pf == NULL) {
4542                 PMD_DRV_LOG(ERR,
4543                             "veb setup failed, associated PF shouldn't null");
4544                 return NULL;
4545         }
4546         hw = I40E_PF_TO_HW(pf);
4547
4548         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4549         if (!veb) {
4550                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4551                 goto fail;
4552         }
4553
4554         veb->associate_vsi = vsi;
4555         veb->associate_pf = pf;
4556         TAILQ_INIT(&veb->head);
4557         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4558
4559         /* create floating veb if vsi is NULL */
4560         if (vsi != NULL) {
4561                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4562                                       I40E_DEFAULT_TCMAP, false,
4563                                       &veb->seid, false, NULL);
4564         } else {
4565                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4566                                       true, &veb->seid, false, NULL);
4567         }
4568
4569         if (ret != I40E_SUCCESS) {
4570                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4571                             hw->aq.asq_last_status);
4572                 goto fail;
4573         }
4574         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4575
4576         /* get statistics index */
4577         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4578                                 &veb->stats_idx, NULL, NULL, NULL);
4579         if (ret != I40E_SUCCESS) {
4580                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4581                             hw->aq.asq_last_status);
4582                 goto fail;
4583         }
4584         /* Get VEB bandwidth, to be implemented */
4585         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4586         if (vsi)
4587                 vsi->uplink_seid = veb->seid;
4588
4589         return veb;
4590 fail:
4591         rte_free(veb);
4592         return NULL;
4593 }
4594
4595 int
4596 i40e_vsi_release(struct i40e_vsi *vsi)
4597 {
4598         struct i40e_pf *pf;
4599         struct i40e_hw *hw;
4600         struct i40e_vsi_list *vsi_list;
4601         void *temp;
4602         int ret;
4603         struct i40e_mac_filter *f;
4604         uint16_t user_param;
4605
4606         if (!vsi)
4607                 return I40E_SUCCESS;
4608
4609         if (!vsi->adapter)
4610                 return -EFAULT;
4611
4612         user_param = vsi->user_param;
4613
4614         pf = I40E_VSI_TO_PF(vsi);
4615         hw = I40E_VSI_TO_HW(vsi);
4616
4617         /* VSI has child to attach, release child first */
4618         if (vsi->veb) {
4619                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4620                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4621                                 return -1;
4622                 }
4623                 i40e_veb_release(vsi->veb);
4624         }
4625
4626         if (vsi->floating_veb) {
4627                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4628                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4629                                 return -1;
4630                 }
4631         }
4632
4633         /* Remove all macvlan filters of the VSI */
4634         i40e_vsi_remove_all_macvlan_filter(vsi);
4635         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4636                 rte_free(f);
4637
4638         if (vsi->type != I40E_VSI_MAIN &&
4639             ((vsi->type != I40E_VSI_SRIOV) ||
4640             !pf->floating_veb_list[user_param])) {
4641                 /* Remove vsi from parent's sibling list */
4642                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4643                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4644                         return I40E_ERR_PARAM;
4645                 }
4646                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4647                                 &vsi->sib_vsi_list, list);
4648
4649                 /* Remove all switch element of the VSI */
4650                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4651                 if (ret != I40E_SUCCESS)
4652                         PMD_DRV_LOG(ERR, "Failed to delete element");
4653         }
4654
4655         if ((vsi->type == I40E_VSI_SRIOV) &&
4656             pf->floating_veb_list[user_param]) {
4657                 /* Remove vsi from parent's sibling list */
4658                 if (vsi->parent_vsi == NULL ||
4659                     vsi->parent_vsi->floating_veb == NULL) {
4660                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4661                         return I40E_ERR_PARAM;
4662                 }
4663                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4664                              &vsi->sib_vsi_list, list);
4665
4666                 /* Remove all switch element of the VSI */
4667                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4668                 if (ret != I40E_SUCCESS)
4669                         PMD_DRV_LOG(ERR, "Failed to delete element");
4670         }
4671
4672         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4673
4674         if (vsi->type != I40E_VSI_SRIOV)
4675                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4676         rte_free(vsi);
4677
4678         return I40E_SUCCESS;
4679 }
4680
4681 static int
4682 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4683 {
4684         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4685         struct i40e_aqc_remove_macvlan_element_data def_filter;
4686         struct i40e_mac_filter_info filter;
4687         int ret;
4688
4689         if (vsi->type != I40E_VSI_MAIN)
4690                 return I40E_ERR_CONFIG;
4691         memset(&def_filter, 0, sizeof(def_filter));
4692         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4693                                         ETH_ADDR_LEN);
4694         def_filter.vlan_tag = 0;
4695         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4696                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4697         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4698         if (ret != I40E_SUCCESS) {
4699                 struct i40e_mac_filter *f;
4700                 struct ether_addr *mac;
4701
4702                 PMD_DRV_LOG(DEBUG,
4703                             "Cannot remove the default macvlan filter");
4704                 /* It needs to add the permanent mac into mac list */
4705                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4706                 if (f == NULL) {
4707                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4708                         return I40E_ERR_NO_MEMORY;
4709                 }
4710                 mac = &f->mac_info.mac_addr;
4711                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4712                                 ETH_ADDR_LEN);
4713                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4714                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4715                 vsi->mac_num++;
4716
4717                 return ret;
4718         }
4719         rte_memcpy(&filter.mac_addr,
4720                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4721         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4722         return i40e_vsi_add_mac(vsi, &filter);
4723 }
4724
4725 /*
4726  * i40e_vsi_get_bw_config - Query VSI BW Information
4727  * @vsi: the VSI to be queried
4728  *
4729  * Returns 0 on success, negative value on failure
4730  */
4731 static enum i40e_status_code
4732 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4733 {
4734         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4735         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4736         struct i40e_hw *hw = &vsi->adapter->hw;
4737         i40e_status ret;
4738         int i;
4739         uint32_t bw_max;
4740
4741         memset(&bw_config, 0, sizeof(bw_config));
4742         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4743         if (ret != I40E_SUCCESS) {
4744                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4745                             hw->aq.asq_last_status);
4746                 return ret;
4747         }
4748
4749         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4750         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4751                                         &ets_sla_config, NULL);
4752         if (ret != I40E_SUCCESS) {
4753                 PMD_DRV_LOG(ERR,
4754                         "VSI failed to get TC bandwdith configuration %u",
4755                         hw->aq.asq_last_status);
4756                 return ret;
4757         }
4758
4759         /* store and print out BW info */
4760         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4761         vsi->bw_info.bw_max = bw_config.max_bw;
4762         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4763         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4764         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4765                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4766                      I40E_16_BIT_WIDTH);
4767         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4768                 vsi->bw_info.bw_ets_share_credits[i] =
4769                                 ets_sla_config.share_credits[i];
4770                 vsi->bw_info.bw_ets_credits[i] =
4771                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4772                 /* 4 bits per TC, 4th bit is reserved */
4773                 vsi->bw_info.bw_ets_max[i] =
4774                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4775                                   RTE_LEN2MASK(3, uint8_t));
4776                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4777                             vsi->bw_info.bw_ets_share_credits[i]);
4778                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4779                             vsi->bw_info.bw_ets_credits[i]);
4780                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4781                             vsi->bw_info.bw_ets_max[i]);
4782         }
4783
4784         return I40E_SUCCESS;
4785 }
4786
4787 /* i40e_enable_pf_lb
4788  * @pf: pointer to the pf structure
4789  *
4790  * allow loopback on pf
4791  */
4792 static inline void
4793 i40e_enable_pf_lb(struct i40e_pf *pf)
4794 {
4795         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4796         struct i40e_vsi_context ctxt;
4797         int ret;
4798
4799         /* Use the FW API if FW >= v5.0 */
4800         if (hw->aq.fw_maj_ver < 5) {
4801                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4802                 return;
4803         }
4804
4805         memset(&ctxt, 0, sizeof(ctxt));
4806         ctxt.seid = pf->main_vsi_seid;
4807         ctxt.pf_num = hw->pf_id;
4808         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4809         if (ret) {
4810                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4811                             ret, hw->aq.asq_last_status);
4812                 return;
4813         }
4814         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4815         ctxt.info.valid_sections =
4816                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4817         ctxt.info.switch_id |=
4818                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4819
4820         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4821         if (ret)
4822                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4823                             hw->aq.asq_last_status);
4824 }
4825
4826 /* Setup a VSI */
4827 struct i40e_vsi *
4828 i40e_vsi_setup(struct i40e_pf *pf,
4829                enum i40e_vsi_type type,
4830                struct i40e_vsi *uplink_vsi,
4831                uint16_t user_param)
4832 {
4833         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4834         struct i40e_vsi *vsi;
4835         struct i40e_mac_filter_info filter;
4836         int ret;
4837         struct i40e_vsi_context ctxt;
4838         struct ether_addr broadcast =
4839                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4840
4841         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4842             uplink_vsi == NULL) {
4843                 PMD_DRV_LOG(ERR,
4844                         "VSI setup failed, VSI link shouldn't be NULL");
4845                 return NULL;
4846         }
4847
4848         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4849                 PMD_DRV_LOG(ERR,
4850                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4851                 return NULL;
4852         }
4853
4854         /* two situations
4855          * 1.type is not MAIN and uplink vsi is not NULL
4856          * If uplink vsi didn't setup VEB, create one first under veb field
4857          * 2.type is SRIOV and the uplink is NULL
4858          * If floating VEB is NULL, create one veb under floating veb field
4859          */
4860
4861         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4862             uplink_vsi->veb == NULL) {
4863                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4864
4865                 if (uplink_vsi->veb == NULL) {
4866                         PMD_DRV_LOG(ERR, "VEB setup failed");
4867                         return NULL;
4868                 }
4869                 /* set ALLOWLOOPBACk on pf, when veb is created */
4870                 i40e_enable_pf_lb(pf);
4871         }
4872
4873         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4874             pf->main_vsi->floating_veb == NULL) {
4875                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4876
4877                 if (pf->main_vsi->floating_veb == NULL) {
4878                         PMD_DRV_LOG(ERR, "VEB setup failed");
4879                         return NULL;
4880                 }
4881         }
4882
4883         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4884         if (!vsi) {
4885                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4886                 return NULL;
4887         }
4888         TAILQ_INIT(&vsi->mac_list);
4889         vsi->type = type;
4890         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4891         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4892         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4893         vsi->user_param = user_param;
4894         vsi->vlan_anti_spoof_on = 0;
4895         vsi->vlan_filter_on = 0;
4896         /* Allocate queues */
4897         switch (vsi->type) {
4898         case I40E_VSI_MAIN  :
4899                 vsi->nb_qps = pf->lan_nb_qps;
4900                 break;
4901         case I40E_VSI_SRIOV :
4902                 vsi->nb_qps = pf->vf_nb_qps;
4903                 break;
4904         case I40E_VSI_VMDQ2:
4905                 vsi->nb_qps = pf->vmdq_nb_qps;
4906                 break;
4907         case I40E_VSI_FDIR:
4908                 vsi->nb_qps = pf->fdir_nb_qps;
4909                 break;
4910         default:
4911                 goto fail_mem;
4912         }
4913         /*
4914          * The filter status descriptor is reported in rx queue 0,
4915          * while the tx queue for fdir filter programming has no
4916          * such constraints, can be non-zero queues.
4917          * To simplify it, choose FDIR vsi use queue 0 pair.
4918          * To make sure it will use queue 0 pair, queue allocation
4919          * need be done before this function is called
4920          */
4921         if (type != I40E_VSI_FDIR) {
4922                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4923                         if (ret < 0) {
4924                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4925                                                 vsi->seid, ret);
4926                                 goto fail_mem;
4927                         }
4928                         vsi->base_queue = ret;
4929         } else
4930                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4931
4932         /* VF has MSIX interrupt in VF range, don't allocate here */
4933         if (type == I40E_VSI_MAIN) {
4934                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4935                                           RTE_MIN(vsi->nb_qps,
4936                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4937                 if (ret < 0) {
4938                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4939                                     vsi->seid, ret);
4940                         goto fail_queue_alloc;
4941                 }
4942                 vsi->msix_intr = ret;
4943                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4944         } else if (type != I40E_VSI_SRIOV) {
4945                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4946                 if (ret < 0) {
4947                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4948                         goto fail_queue_alloc;
4949                 }
4950                 vsi->msix_intr = ret;
4951                 vsi->nb_msix = 1;
4952         } else {
4953                 vsi->msix_intr = 0;
4954                 vsi->nb_msix = 0;
4955         }
4956
4957         /* Add VSI */
4958         if (type == I40E_VSI_MAIN) {
4959                 /* For main VSI, no need to add since it's default one */
4960                 vsi->uplink_seid = pf->mac_seid;
4961                 vsi->seid = pf->main_vsi_seid;
4962                 /* Bind queues with specific MSIX interrupt */
4963                 /**
4964                  * Needs 2 interrupt at least, one for misc cause which will
4965                  * enabled from OS side, Another for queues binding the
4966                  * interrupt from device side only.
4967                  */
4968
4969                 /* Get default VSI parameters from hardware */
4970                 memset(&ctxt, 0, sizeof(ctxt));
4971                 ctxt.seid = vsi->seid;
4972                 ctxt.pf_num = hw->pf_id;
4973                 ctxt.uplink_seid = vsi->uplink_seid;
4974                 ctxt.vf_num = 0;
4975                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4976                 if (ret != I40E_SUCCESS) {
4977                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4978                         goto fail_msix_alloc;
4979                 }
4980                 rte_memcpy(&vsi->info, &ctxt.info,
4981                         sizeof(struct i40e_aqc_vsi_properties_data));
4982                 vsi->vsi_id = ctxt.vsi_number;
4983                 vsi->info.valid_sections = 0;
4984
4985                 /* Configure tc, enabled TC0 only */
4986                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4987                         I40E_SUCCESS) {
4988                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4989                         goto fail_msix_alloc;
4990                 }
4991
4992                 /* TC, queue mapping */
4993                 memset(&ctxt, 0, sizeof(ctxt));
4994                 vsi->info.valid_sections |=
4995                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4996                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4997                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4998                 rte_memcpy(&ctxt.info, &vsi->info,
4999                         sizeof(struct i40e_aqc_vsi_properties_data));
5000                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5001                                                 I40E_DEFAULT_TCMAP);
5002                 if (ret != I40E_SUCCESS) {
5003                         PMD_DRV_LOG(ERR,
5004                                 "Failed to configure TC queue mapping");
5005                         goto fail_msix_alloc;
5006                 }
5007                 ctxt.seid = vsi->seid;
5008                 ctxt.pf_num = hw->pf_id;
5009                 ctxt.uplink_seid = vsi->uplink_seid;
5010                 ctxt.vf_num = 0;
5011
5012                 /* Update VSI parameters */
5013                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5014                 if (ret != I40E_SUCCESS) {
5015                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5016                         goto fail_msix_alloc;
5017                 }
5018
5019                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5020                                                 sizeof(vsi->info.tc_mapping));
5021                 rte_memcpy(&vsi->info.queue_mapping,
5022                                 &ctxt.info.queue_mapping,
5023                         sizeof(vsi->info.queue_mapping));
5024                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5025                 vsi->info.valid_sections = 0;
5026
5027                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5028                                 ETH_ADDR_LEN);
5029
5030                 /**
5031                  * Updating default filter settings are necessary to prevent
5032                  * reception of tagged packets.
5033                  * Some old firmware configurations load a default macvlan
5034                  * filter which accepts both tagged and untagged packets.
5035                  * The updating is to use a normal filter instead if needed.
5036                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5037                  * The firmware with correct configurations load the default
5038                  * macvlan filter which is expected and cannot be removed.
5039                  */
5040                 i40e_update_default_filter_setting(vsi);
5041                 i40e_config_qinq(hw, vsi);
5042         } else if (type == I40E_VSI_SRIOV) {
5043                 memset(&ctxt, 0, sizeof(ctxt));
5044                 /**
5045                  * For other VSI, the uplink_seid equals to uplink VSI's
5046                  * uplink_seid since they share same VEB
5047                  */
5048                 if (uplink_vsi == NULL)
5049                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5050                 else
5051                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5052                 ctxt.pf_num = hw->pf_id;
5053                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5054                 ctxt.uplink_seid = vsi->uplink_seid;
5055                 ctxt.connection_type = 0x1;
5056                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5057
5058                 /* Use the VEB configuration if FW >= v5.0 */
5059                 if (hw->aq.fw_maj_ver >= 5) {
5060                         /* Configure switch ID */
5061                         ctxt.info.valid_sections |=
5062                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5063                         ctxt.info.switch_id =
5064                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5065                 }
5066
5067                 /* Configure port/vlan */
5068                 ctxt.info.valid_sections |=
5069                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5070                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5071                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5072                                                 hw->func_caps.enabled_tcmap);
5073                 if (ret != I40E_SUCCESS) {
5074                         PMD_DRV_LOG(ERR,
5075                                 "Failed to configure TC queue mapping");
5076                         goto fail_msix_alloc;
5077                 }
5078
5079                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5080                 ctxt.info.valid_sections |=
5081                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5082                 /**
5083                  * Since VSI is not created yet, only configure parameter,
5084                  * will add vsi below.
5085                  */
5086
5087                 i40e_config_qinq(hw, vsi);
5088         } else if (type == I40E_VSI_VMDQ2) {
5089                 memset(&ctxt, 0, sizeof(ctxt));
5090                 /*
5091                  * For other VSI, the uplink_seid equals to uplink VSI's
5092                  * uplink_seid since they share same VEB
5093                  */
5094                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5095                 ctxt.pf_num = hw->pf_id;
5096                 ctxt.vf_num = 0;
5097                 ctxt.uplink_seid = vsi->uplink_seid;
5098                 ctxt.connection_type = 0x1;
5099                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5100
5101                 ctxt.info.valid_sections |=
5102                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5103                 /* user_param carries flag to enable loop back */
5104                 if (user_param) {
5105                         ctxt.info.switch_id =
5106                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5107                         ctxt.info.switch_id |=
5108                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5109                 }
5110
5111                 /* Configure port/vlan */
5112                 ctxt.info.valid_sections |=
5113                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5114                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5115                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5116                                                 I40E_DEFAULT_TCMAP);
5117                 if (ret != I40E_SUCCESS) {
5118                         PMD_DRV_LOG(ERR,
5119                                 "Failed to configure TC queue mapping");
5120                         goto fail_msix_alloc;
5121                 }
5122                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5123                 ctxt.info.valid_sections |=
5124                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5125         } else if (type == I40E_VSI_FDIR) {
5126                 memset(&ctxt, 0, sizeof(ctxt));
5127                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5128                 ctxt.pf_num = hw->pf_id;
5129                 ctxt.vf_num = 0;
5130                 ctxt.uplink_seid = vsi->uplink_seid;
5131                 ctxt.connection_type = 0x1;     /* regular data port */
5132                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5133                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5134                                                 I40E_DEFAULT_TCMAP);
5135                 if (ret != I40E_SUCCESS) {
5136                         PMD_DRV_LOG(ERR,
5137                                 "Failed to configure TC queue mapping.");
5138                         goto fail_msix_alloc;
5139                 }
5140                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5141                 ctxt.info.valid_sections |=
5142                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5143         } else {
5144                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5145                 goto fail_msix_alloc;
5146         }
5147
5148         if (vsi->type != I40E_VSI_MAIN) {
5149                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5150                 if (ret != I40E_SUCCESS) {
5151                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5152                                     hw->aq.asq_last_status);
5153                         goto fail_msix_alloc;
5154                 }
5155                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5156                 vsi->info.valid_sections = 0;
5157                 vsi->seid = ctxt.seid;
5158                 vsi->vsi_id = ctxt.vsi_number;
5159                 vsi->sib_vsi_list.vsi = vsi;
5160                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5161                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5162                                           &vsi->sib_vsi_list, list);
5163                 } else {
5164                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5165                                           &vsi->sib_vsi_list, list);
5166                 }
5167         }
5168
5169         /* MAC/VLAN configuration */
5170         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5171         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5172
5173         ret = i40e_vsi_add_mac(vsi, &filter);
5174         if (ret != I40E_SUCCESS) {
5175                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5176                 goto fail_msix_alloc;
5177         }
5178
5179         /* Get VSI BW information */
5180         i40e_vsi_get_bw_config(vsi);
5181         return vsi;
5182 fail_msix_alloc:
5183         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5184 fail_queue_alloc:
5185         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5186 fail_mem:
5187         rte_free(vsi);
5188         return NULL;
5189 }
5190
5191 /* Configure vlan filter on or off */
5192 int
5193 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5194 {
5195         int i, num;
5196         struct i40e_mac_filter *f;
5197         void *temp;
5198         struct i40e_mac_filter_info *mac_filter;
5199         enum rte_mac_filter_type desired_filter;
5200         int ret = I40E_SUCCESS;
5201
5202         if (on) {
5203                 /* Filter to match MAC and VLAN */
5204                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5205         } else {
5206                 /* Filter to match only MAC */
5207                 desired_filter = RTE_MAC_PERFECT_MATCH;
5208         }
5209
5210         num = vsi->mac_num;
5211
5212         mac_filter = rte_zmalloc("mac_filter_info_data",
5213                                  num * sizeof(*mac_filter), 0);
5214         if (mac_filter == NULL) {
5215                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5216                 return I40E_ERR_NO_MEMORY;
5217         }
5218
5219         i = 0;
5220
5221         /* Remove all existing mac */
5222         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5223                 mac_filter[i] = f->mac_info;
5224                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5225                 if (ret) {
5226                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5227                                     on ? "enable" : "disable");
5228                         goto DONE;
5229                 }
5230                 i++;
5231         }
5232
5233         /* Override with new filter */
5234         for (i = 0; i < num; i++) {
5235                 mac_filter[i].filter_type = desired_filter;
5236                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5237                 if (ret) {
5238                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5239                                     on ? "enable" : "disable");
5240                         goto DONE;
5241                 }
5242         }
5243
5244 DONE:
5245         rte_free(mac_filter);
5246         return ret;
5247 }
5248
5249 /* Configure vlan stripping on or off */
5250 int
5251 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5252 {
5253         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5254         struct i40e_vsi_context ctxt;
5255         uint8_t vlan_flags;
5256         int ret = I40E_SUCCESS;
5257
5258         /* Check if it has been already on or off */
5259         if (vsi->info.valid_sections &
5260                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5261                 if (on) {
5262                         if ((vsi->info.port_vlan_flags &
5263                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5264                                 return 0; /* already on */
5265                 } else {
5266                         if ((vsi->info.port_vlan_flags &
5267                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5268                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5269                                 return 0; /* already off */
5270                 }
5271         }
5272
5273         if (on)
5274                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5275         else
5276                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5277         vsi->info.valid_sections =
5278                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5279         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5280         vsi->info.port_vlan_flags |= vlan_flags;
5281         ctxt.seid = vsi->seid;
5282         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5283         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5284         if (ret)
5285                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5286                             on ? "enable" : "disable");
5287
5288         return ret;
5289 }
5290
5291 static int
5292 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5293 {
5294         struct rte_eth_dev_data *data = dev->data;
5295         int ret;
5296         int mask = 0;
5297
5298         /* Apply vlan offload setting */
5299         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5300         i40e_vlan_offload_set(dev, mask);
5301
5302         /* Apply double-vlan setting, not implemented yet */
5303
5304         /* Apply pvid setting */
5305         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5306                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5307         if (ret)
5308                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5309
5310         return ret;
5311 }
5312
5313 static int
5314 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5315 {
5316         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5317
5318         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5319 }
5320
5321 static int
5322 i40e_update_flow_control(struct i40e_hw *hw)
5323 {
5324 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5325         struct i40e_link_status link_status;
5326         uint32_t rxfc = 0, txfc = 0, reg;
5327         uint8_t an_info;
5328         int ret;
5329
5330         memset(&link_status, 0, sizeof(link_status));
5331         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5332         if (ret != I40E_SUCCESS) {
5333                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5334                 goto write_reg; /* Disable flow control */
5335         }
5336
5337         an_info = hw->phy.link_info.an_info;
5338         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5339                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5340                 ret = I40E_ERR_NOT_READY;
5341                 goto write_reg; /* Disable flow control */
5342         }
5343         /**
5344          * If link auto negotiation is enabled, flow control needs to
5345          * be configured according to it
5346          */
5347         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5348         case I40E_LINK_PAUSE_RXTX:
5349                 rxfc = 1;
5350                 txfc = 1;
5351                 hw->fc.current_mode = I40E_FC_FULL;
5352                 break;
5353         case I40E_AQ_LINK_PAUSE_RX:
5354                 rxfc = 1;
5355                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5356                 break;
5357         case I40E_AQ_LINK_PAUSE_TX:
5358                 txfc = 1;
5359                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5360                 break;
5361         default:
5362                 hw->fc.current_mode = I40E_FC_NONE;
5363                 break;
5364         }
5365
5366 write_reg:
5367         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5368                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5369         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5370         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5371         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5372         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5373
5374         return ret;
5375 }
5376
5377 /* PF setup */
5378 static int
5379 i40e_pf_setup(struct i40e_pf *pf)
5380 {
5381         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5382         struct i40e_filter_control_settings settings;
5383         struct i40e_vsi *vsi;
5384         int ret;
5385
5386         /* Clear all stats counters */
5387         pf->offset_loaded = FALSE;
5388         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5389         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5390         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5391         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5392
5393         ret = i40e_pf_get_switch_config(pf);
5394         if (ret != I40E_SUCCESS) {
5395                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5396                 return ret;
5397         }
5398         if (pf->flags & I40E_FLAG_FDIR) {
5399                 /* make queue allocated first, let FDIR use queue pair 0*/
5400                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5401                 if (ret != I40E_FDIR_QUEUE_ID) {
5402                         PMD_DRV_LOG(ERR,
5403                                 "queue allocation fails for FDIR: ret =%d",
5404                                 ret);
5405                         pf->flags &= ~I40E_FLAG_FDIR;
5406                 }
5407         }
5408         /*  main VSI setup */
5409         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5410         if (!vsi) {
5411                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5412                 return I40E_ERR_NOT_READY;
5413         }
5414         pf->main_vsi = vsi;
5415
5416         /* Configure filter control */
5417         memset(&settings, 0, sizeof(settings));
5418         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5419                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5420         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5421                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5422         else {
5423                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5424                         hw->func_caps.rss_table_size);
5425                 return I40E_ERR_PARAM;
5426         }
5427         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5428                 hw->func_caps.rss_table_size);
5429         pf->hash_lut_size = hw->func_caps.rss_table_size;
5430
5431         /* Enable ethtype and macvlan filters */
5432         settings.enable_ethtype = TRUE;
5433         settings.enable_macvlan = TRUE;
5434         ret = i40e_set_filter_control(hw, &settings);
5435         if (ret)
5436                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5437                                                                 ret);
5438
5439         /* Update flow control according to the auto negotiation */
5440         i40e_update_flow_control(hw);
5441
5442         return I40E_SUCCESS;
5443 }
5444
5445 int
5446 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5447 {
5448         uint32_t reg;
5449         uint16_t j;
5450
5451         /**
5452          * Set or clear TX Queue Disable flags,
5453          * which is required by hardware.
5454          */
5455         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5456         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5457
5458         /* Wait until the request is finished */
5459         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5460                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5461                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5462                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5463                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5464                                                         & 0x1))) {
5465                         break;
5466                 }
5467         }
5468         if (on) {
5469                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5470                         return I40E_SUCCESS; /* already on, skip next steps */
5471
5472                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5473                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5474         } else {
5475                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5476                         return I40E_SUCCESS; /* already off, skip next steps */
5477                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5478         }
5479         /* Write the register */
5480         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5481         /* Check the result */
5482         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5483                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5484                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5485                 if (on) {
5486                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5487                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5488                                 break;
5489                 } else {
5490                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5491                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5492                                 break;
5493                 }
5494         }
5495         /* Check if it is timeout */
5496         if (j >= I40E_CHK_Q_ENA_COUNT) {
5497                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5498                             (on ? "enable" : "disable"), q_idx);
5499                 return I40E_ERR_TIMEOUT;
5500         }
5501
5502         return I40E_SUCCESS;
5503 }
5504
5505 /* Swith on or off the tx queues */
5506 static int
5507 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5508 {
5509         struct rte_eth_dev_data *dev_data = pf->dev_data;
5510         struct i40e_tx_queue *txq;
5511         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5512         uint16_t i;
5513         int ret;
5514
5515         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5516                 txq = dev_data->tx_queues[i];
5517                 /* Don't operate the queue if not configured or
5518                  * if starting only per queue */
5519                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5520                         continue;
5521                 if (on)
5522                         ret = i40e_dev_tx_queue_start(dev, i);
5523                 else
5524                         ret = i40e_dev_tx_queue_stop(dev, i);
5525                 if ( ret != I40E_SUCCESS)
5526                         return ret;
5527         }
5528
5529         return I40E_SUCCESS;
5530 }
5531
5532 int
5533 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5534 {
5535         uint32_t reg;
5536         uint16_t j;
5537
5538         /* Wait until the request is finished */
5539         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5540                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5541                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5542                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5543                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5544                         break;
5545         }
5546
5547         if (on) {
5548                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5549                         return I40E_SUCCESS; /* Already on, skip next steps */
5550                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5551         } else {
5552                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5553                         return I40E_SUCCESS; /* Already off, skip next steps */
5554                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5555         }
5556
5557         /* Write the register */
5558         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5559         /* Check the result */
5560         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5561                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5562                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5563                 if (on) {
5564                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5565                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5566                                 break;
5567                 } else {
5568                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5569                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5570                                 break;
5571                 }
5572         }
5573
5574         /* Check if it is timeout */
5575         if (j >= I40E_CHK_Q_ENA_COUNT) {
5576                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5577                             (on ? "enable" : "disable"), q_idx);
5578                 return I40E_ERR_TIMEOUT;
5579         }
5580
5581         return I40E_SUCCESS;
5582 }
5583 /* Switch on or off the rx queues */
5584 static int
5585 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5586 {
5587         struct rte_eth_dev_data *dev_data = pf->dev_data;
5588         struct i40e_rx_queue *rxq;
5589         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5590         uint16_t i;
5591         int ret;
5592
5593         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5594                 rxq = dev_data->rx_queues[i];
5595                 /* Don't operate the queue if not configured or
5596                  * if starting only per queue */
5597                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5598                         continue;
5599                 if (on)
5600                         ret = i40e_dev_rx_queue_start(dev, i);
5601                 else
5602                         ret = i40e_dev_rx_queue_stop(dev, i);
5603                 if (ret != I40E_SUCCESS)
5604                         return ret;
5605         }
5606
5607         return I40E_SUCCESS;
5608 }
5609
5610 /* Switch on or off all the rx/tx queues */
5611 int
5612 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5613 {
5614         int ret;
5615
5616         if (on) {
5617                 /* enable rx queues before enabling tx queues */
5618                 ret = i40e_dev_switch_rx_queues(pf, on);
5619                 if (ret) {
5620                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5621                         return ret;
5622                 }
5623                 ret = i40e_dev_switch_tx_queues(pf, on);
5624         } else {
5625                 /* Stop tx queues before stopping rx queues */
5626                 ret = i40e_dev_switch_tx_queues(pf, on);
5627                 if (ret) {
5628                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5629                         return ret;
5630                 }
5631                 ret = i40e_dev_switch_rx_queues(pf, on);
5632         }
5633
5634         return ret;
5635 }
5636
5637 /* Initialize VSI for TX */
5638 static int
5639 i40e_dev_tx_init(struct i40e_pf *pf)
5640 {
5641         struct rte_eth_dev_data *data = pf->dev_data;
5642         uint16_t i;
5643         uint32_t ret = I40E_SUCCESS;
5644         struct i40e_tx_queue *txq;
5645
5646         for (i = 0; i < data->nb_tx_queues; i++) {
5647                 txq = data->tx_queues[i];
5648                 if (!txq || !txq->q_set)
5649                         continue;
5650                 ret = i40e_tx_queue_init(txq);
5651                 if (ret != I40E_SUCCESS)
5652                         break;
5653         }
5654         if (ret == I40E_SUCCESS)
5655                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5656                                      ->eth_dev);
5657
5658         return ret;
5659 }
5660
5661 /* Initialize VSI for RX */
5662 static int
5663 i40e_dev_rx_init(struct i40e_pf *pf)
5664 {
5665         struct rte_eth_dev_data *data = pf->dev_data;
5666         int ret = I40E_SUCCESS;
5667         uint16_t i;
5668         struct i40e_rx_queue *rxq;
5669
5670         i40e_pf_config_mq_rx(pf);
5671         for (i = 0; i < data->nb_rx_queues; i++) {
5672                 rxq = data->rx_queues[i];
5673                 if (!rxq || !rxq->q_set)
5674                         continue;
5675
5676                 ret = i40e_rx_queue_init(rxq);
5677                 if (ret != I40E_SUCCESS) {
5678                         PMD_DRV_LOG(ERR,
5679                                 "Failed to do RX queue initialization");
5680                         break;
5681                 }
5682         }
5683         if (ret == I40E_SUCCESS)
5684                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5685                                      ->eth_dev);
5686
5687         return ret;
5688 }
5689
5690 static int
5691 i40e_dev_rxtx_init(struct i40e_pf *pf)
5692 {
5693         int err;
5694
5695         err = i40e_dev_tx_init(pf);
5696         if (err) {
5697                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5698                 return err;
5699         }
5700         err = i40e_dev_rx_init(pf);
5701         if (err) {
5702                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5703                 return err;
5704         }
5705
5706         return err;
5707 }
5708
5709 static int
5710 i40e_vmdq_setup(struct rte_eth_dev *dev)
5711 {
5712         struct rte_eth_conf *conf = &dev->data->dev_conf;
5713         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5714         int i, err, conf_vsis, j, loop;
5715         struct i40e_vsi *vsi;
5716         struct i40e_vmdq_info *vmdq_info;
5717         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5718         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5719
5720         /*
5721          * Disable interrupt to avoid message from VF. Furthermore, it will
5722          * avoid race condition in VSI creation/destroy.
5723          */
5724         i40e_pf_disable_irq0(hw);
5725
5726         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5727                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5728                 return -ENOTSUP;
5729         }
5730
5731         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5732         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5733                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5734                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5735                         pf->max_nb_vmdq_vsi);
5736                 return -ENOTSUP;
5737         }
5738
5739         if (pf->vmdq != NULL) {
5740                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5741                 return 0;
5742         }
5743
5744         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5745                                 sizeof(*vmdq_info) * conf_vsis, 0);
5746
5747         if (pf->vmdq == NULL) {
5748                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5749                 return -ENOMEM;
5750         }
5751
5752         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5753
5754         /* Create VMDQ VSI */
5755         for (i = 0; i < conf_vsis; i++) {
5756                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5757                                 vmdq_conf->enable_loop_back);
5758                 if (vsi == NULL) {
5759                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5760                         err = -1;
5761                         goto err_vsi_setup;
5762                 }
5763                 vmdq_info = &pf->vmdq[i];
5764                 vmdq_info->pf = pf;
5765                 vmdq_info->vsi = vsi;
5766         }
5767         pf->nb_cfg_vmdq_vsi = conf_vsis;
5768
5769         /* Configure Vlan */
5770         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5771         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5772                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5773                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5774                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5775                                         vmdq_conf->pool_map[i].vlan_id, j);
5776
5777                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5778                                                 vmdq_conf->pool_map[i].vlan_id);
5779                                 if (err) {
5780                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5781                                         err = -1;
5782                                         goto err_vsi_setup;
5783                                 }
5784                         }
5785                 }
5786         }
5787
5788         i40e_pf_enable_irq0(hw);
5789
5790         return 0;
5791
5792 err_vsi_setup:
5793         for (i = 0; i < conf_vsis; i++)
5794                 if (pf->vmdq[i].vsi == NULL)
5795                         break;
5796                 else
5797                         i40e_vsi_release(pf->vmdq[i].vsi);
5798
5799         rte_free(pf->vmdq);
5800         pf->vmdq = NULL;
5801         i40e_pf_enable_irq0(hw);
5802         return err;
5803 }
5804
5805 static void
5806 i40e_stat_update_32(struct i40e_hw *hw,
5807                    uint32_t reg,
5808                    bool offset_loaded,
5809                    uint64_t *offset,
5810                    uint64_t *stat)
5811 {
5812         uint64_t new_data;
5813
5814         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5815         if (!offset_loaded)
5816                 *offset = new_data;
5817
5818         if (new_data >= *offset)
5819                 *stat = (uint64_t)(new_data - *offset);
5820         else
5821                 *stat = (uint64_t)((new_data +
5822                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5823 }
5824
5825 static void
5826 i40e_stat_update_48(struct i40e_hw *hw,
5827                    uint32_t hireg,
5828                    uint32_t loreg,
5829                    bool offset_loaded,
5830                    uint64_t *offset,
5831                    uint64_t *stat)
5832 {
5833         uint64_t new_data;
5834
5835         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5836         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5837                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5838
5839         if (!offset_loaded)
5840                 *offset = new_data;
5841
5842         if (new_data >= *offset)
5843                 *stat = new_data - *offset;
5844         else
5845                 *stat = (uint64_t)((new_data +
5846                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5847
5848         *stat &= I40E_48_BIT_MASK;
5849 }
5850
5851 /* Disable IRQ0 */
5852 void
5853 i40e_pf_disable_irq0(struct i40e_hw *hw)
5854 {
5855         /* Disable all interrupt types */
5856         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5857         I40E_WRITE_FLUSH(hw);
5858 }
5859
5860 /* Enable IRQ0 */
5861 void
5862 i40e_pf_enable_irq0(struct i40e_hw *hw)
5863 {
5864         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5865                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5866                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5867                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5868         I40E_WRITE_FLUSH(hw);
5869 }
5870
5871 static void
5872 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5873 {
5874         /* read pending request and disable first */
5875         i40e_pf_disable_irq0(hw);
5876         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5877         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5878                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5879
5880         if (no_queue)
5881                 /* Link no queues with irq0 */
5882                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5883                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5884 }
5885
5886 static void
5887 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5888 {
5889         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5890         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5891         int i;
5892         uint16_t abs_vf_id;
5893         uint32_t index, offset, val;
5894
5895         if (!pf->vfs)
5896                 return;
5897         /**
5898          * Try to find which VF trigger a reset, use absolute VF id to access
5899          * since the reg is global register.
5900          */
5901         for (i = 0; i < pf->vf_num; i++) {
5902                 abs_vf_id = hw->func_caps.vf_base_id + i;
5903                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5904                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5905                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5906                 /* VFR event occurred */
5907                 if (val & (0x1 << offset)) {
5908                         int ret;
5909
5910                         /* Clear the event first */
5911                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5912                                                         (0x1 << offset));
5913                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5914                         /**
5915                          * Only notify a VF reset event occurred,
5916                          * don't trigger another SW reset
5917                          */
5918                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5919                         if (ret != I40E_SUCCESS)
5920                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5921                 }
5922         }
5923 }
5924
5925 static void
5926 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5927 {
5928         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5929         int i;
5930
5931         for (i = 0; i < pf->vf_num; i++)
5932                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5933 }
5934
5935 static void
5936 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5937 {
5938         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5939         struct i40e_arq_event_info info;
5940         uint16_t pending, opcode;
5941         int ret;
5942
5943         info.buf_len = I40E_AQ_BUF_SZ;
5944         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5945         if (!info.msg_buf) {
5946                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5947                 return;
5948         }
5949
5950         pending = 1;
5951         while (pending) {
5952                 ret = i40e_clean_arq_element(hw, &info, &pending);
5953
5954                 if (ret != I40E_SUCCESS) {
5955                         PMD_DRV_LOG(INFO,
5956                                 "Failed to read msg from AdminQ, aq_err: %u",
5957                                 hw->aq.asq_last_status);
5958                         break;
5959                 }
5960                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5961
5962                 switch (opcode) {
5963                 case i40e_aqc_opc_send_msg_to_pf:
5964                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5965                         i40e_pf_host_handle_vf_msg(dev,
5966                                         rte_le_to_cpu_16(info.desc.retval),
5967                                         rte_le_to_cpu_32(info.desc.cookie_high),
5968                                         rte_le_to_cpu_32(info.desc.cookie_low),
5969                                         info.msg_buf,
5970                                         info.msg_len);
5971                         break;
5972                 case i40e_aqc_opc_get_link_status:
5973                         ret = i40e_dev_link_update(dev, 0);
5974                         if (!ret)
5975                                 _rte_eth_dev_callback_process(dev,
5976                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5977                         break;
5978                 default:
5979                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5980                                     opcode);
5981                         break;
5982                 }
5983         }
5984         rte_free(info.msg_buf);
5985 }
5986
5987 /**
5988  * Interrupt handler triggered by NIC  for handling
5989  * specific interrupt.
5990  *
5991  * @param handle
5992  *  Pointer to interrupt handle.
5993  * @param param
5994  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5995  *
5996  * @return
5997  *  void
5998  */
5999 static void
6000 i40e_dev_interrupt_handler(void *param)
6001 {
6002         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6003         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6004         uint32_t icr0;
6005
6006         /* Disable interrupt */
6007         i40e_pf_disable_irq0(hw);
6008
6009         /* read out interrupt causes */
6010         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6011
6012         /* No interrupt event indicated */
6013         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6014                 PMD_DRV_LOG(INFO, "No interrupt event");
6015                 goto done;
6016         }
6017         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6018                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6019         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6020                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6021         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6022                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6023         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6024                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6025         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6026                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6027         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6028                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6029         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6030                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6031
6032         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6033                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6034                 i40e_dev_handle_vfr_event(dev);
6035         }
6036         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6037                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6038                 i40e_dev_handle_aq_msg(dev);
6039         }
6040
6041 done:
6042         /* Enable interrupt */
6043         i40e_pf_enable_irq0(hw);
6044         rte_intr_enable(dev->intr_handle);
6045 }
6046
6047 int
6048 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6049                          struct i40e_macvlan_filter *filter,
6050                          int total)
6051 {
6052         int ele_num, ele_buff_size;
6053         int num, actual_num, i;
6054         uint16_t flags;
6055         int ret = I40E_SUCCESS;
6056         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6057         struct i40e_aqc_add_macvlan_element_data *req_list;
6058
6059         if (filter == NULL  || total == 0)
6060                 return I40E_ERR_PARAM;
6061         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6062         ele_buff_size = hw->aq.asq_buf_size;
6063
6064         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6065         if (req_list == NULL) {
6066                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6067                 return I40E_ERR_NO_MEMORY;
6068         }
6069
6070         num = 0;
6071         do {
6072                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6073                 memset(req_list, 0, ele_buff_size);
6074
6075                 for (i = 0; i < actual_num; i++) {
6076                         rte_memcpy(req_list[i].mac_addr,
6077                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6078                         req_list[i].vlan_tag =
6079                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6080
6081                         switch (filter[num + i].filter_type) {
6082                         case RTE_MAC_PERFECT_MATCH:
6083                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6084                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6085                                 break;
6086                         case RTE_MACVLAN_PERFECT_MATCH:
6087                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6088                                 break;
6089                         case RTE_MAC_HASH_MATCH:
6090                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6091                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6092                                 break;
6093                         case RTE_MACVLAN_HASH_MATCH:
6094                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6095                                 break;
6096                         default:
6097                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6098                                 ret = I40E_ERR_PARAM;
6099                                 goto DONE;
6100                         }
6101
6102                         req_list[i].queue_number = 0;
6103
6104                         req_list[i].flags = rte_cpu_to_le_16(flags);
6105                 }
6106
6107                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6108                                                 actual_num, NULL);
6109                 if (ret != I40E_SUCCESS) {
6110                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6111                         goto DONE;
6112                 }
6113                 num += actual_num;
6114         } while (num < total);
6115
6116 DONE:
6117         rte_free(req_list);
6118         return ret;
6119 }
6120
6121 int
6122 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6123                             struct i40e_macvlan_filter *filter,
6124                             int total)
6125 {
6126         int ele_num, ele_buff_size;
6127         int num, actual_num, i;
6128         uint16_t flags;
6129         int ret = I40E_SUCCESS;
6130         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6131         struct i40e_aqc_remove_macvlan_element_data *req_list;
6132
6133         if (filter == NULL  || total == 0)
6134                 return I40E_ERR_PARAM;
6135
6136         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6137         ele_buff_size = hw->aq.asq_buf_size;
6138
6139         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6140         if (req_list == NULL) {
6141                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6142                 return I40E_ERR_NO_MEMORY;
6143         }
6144
6145         num = 0;
6146         do {
6147                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6148                 memset(req_list, 0, ele_buff_size);
6149
6150                 for (i = 0; i < actual_num; i++) {
6151                         rte_memcpy(req_list[i].mac_addr,
6152                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6153                         req_list[i].vlan_tag =
6154                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6155
6156                         switch (filter[num + i].filter_type) {
6157                         case RTE_MAC_PERFECT_MATCH:
6158                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6159                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6160                                 break;
6161                         case RTE_MACVLAN_PERFECT_MATCH:
6162                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6163                                 break;
6164                         case RTE_MAC_HASH_MATCH:
6165                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6166                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6167                                 break;
6168                         case RTE_MACVLAN_HASH_MATCH:
6169                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6170                                 break;
6171                         default:
6172                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6173                                 ret = I40E_ERR_PARAM;
6174                                 goto DONE;
6175                         }
6176                         req_list[i].flags = rte_cpu_to_le_16(flags);
6177                 }
6178
6179                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6180                                                 actual_num, NULL);
6181                 if (ret != I40E_SUCCESS) {
6182                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6183                         goto DONE;
6184                 }
6185                 num += actual_num;
6186         } while (num < total);
6187
6188 DONE:
6189         rte_free(req_list);
6190         return ret;
6191 }
6192
6193 /* Find out specific MAC filter */
6194 static struct i40e_mac_filter *
6195 i40e_find_mac_filter(struct i40e_vsi *vsi,
6196                          struct ether_addr *macaddr)
6197 {
6198         struct i40e_mac_filter *f;
6199
6200         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6201                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6202                         return f;
6203         }
6204
6205         return NULL;
6206 }
6207
6208 static bool
6209 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6210                          uint16_t vlan_id)
6211 {
6212         uint32_t vid_idx, vid_bit;
6213
6214         if (vlan_id > ETH_VLAN_ID_MAX)
6215                 return 0;
6216
6217         vid_idx = I40E_VFTA_IDX(vlan_id);
6218         vid_bit = I40E_VFTA_BIT(vlan_id);
6219
6220         if (vsi->vfta[vid_idx] & vid_bit)
6221                 return 1;
6222         else
6223                 return 0;
6224 }
6225
6226 static void
6227 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6228                        uint16_t vlan_id, bool on)
6229 {
6230         uint32_t vid_idx, vid_bit;
6231
6232         vid_idx = I40E_VFTA_IDX(vlan_id);
6233         vid_bit = I40E_VFTA_BIT(vlan_id);
6234
6235         if (on)
6236                 vsi->vfta[vid_idx] |= vid_bit;
6237         else
6238                 vsi->vfta[vid_idx] &= ~vid_bit;
6239 }
6240
6241 void
6242 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6243                      uint16_t vlan_id, bool on)
6244 {
6245         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6246         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6247         int ret;
6248
6249         if (vlan_id > ETH_VLAN_ID_MAX)
6250                 return;
6251
6252         i40e_store_vlan_filter(vsi, vlan_id, on);
6253
6254         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6255                 return;
6256
6257         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6258
6259         if (on) {
6260                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6261                                        &vlan_data, 1, NULL);
6262                 if (ret != I40E_SUCCESS)
6263                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6264         } else {
6265                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6266                                           &vlan_data, 1, NULL);
6267                 if (ret != I40E_SUCCESS)
6268                         PMD_DRV_LOG(ERR,
6269                                     "Failed to remove vlan filter");
6270         }
6271 }
6272
6273 /**
6274  * Find all vlan options for specific mac addr,
6275  * return with actual vlan found.
6276  */
6277 int
6278 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6279                            struct i40e_macvlan_filter *mv_f,
6280                            int num, struct ether_addr *addr)
6281 {
6282         int i;
6283         uint32_t j, k;
6284
6285         /**
6286          * Not to use i40e_find_vlan_filter to decrease the loop time,
6287          * although the code looks complex.
6288           */
6289         if (num < vsi->vlan_num)
6290                 return I40E_ERR_PARAM;
6291
6292         i = 0;
6293         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6294                 if (vsi->vfta[j]) {
6295                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6296                                 if (vsi->vfta[j] & (1 << k)) {
6297                                         if (i > num - 1) {
6298                                                 PMD_DRV_LOG(ERR,
6299                                                         "vlan number doesn't match");
6300                                                 return I40E_ERR_PARAM;
6301                                         }
6302                                         rte_memcpy(&mv_f[i].macaddr,
6303                                                         addr, ETH_ADDR_LEN);
6304                                         mv_f[i].vlan_id =
6305                                                 j * I40E_UINT32_BIT_SIZE + k;
6306                                         i++;
6307                                 }
6308                         }
6309                 }
6310         }
6311         return I40E_SUCCESS;
6312 }
6313
6314 static inline int
6315 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6316                            struct i40e_macvlan_filter *mv_f,
6317                            int num,
6318                            uint16_t vlan)
6319 {
6320         int i = 0;
6321         struct i40e_mac_filter *f;
6322
6323         if (num < vsi->mac_num)
6324                 return I40E_ERR_PARAM;
6325
6326         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6327                 if (i > num - 1) {
6328                         PMD_DRV_LOG(ERR, "buffer number not match");
6329                         return I40E_ERR_PARAM;
6330                 }
6331                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6332                                 ETH_ADDR_LEN);
6333                 mv_f[i].vlan_id = vlan;
6334                 mv_f[i].filter_type = f->mac_info.filter_type;
6335                 i++;
6336         }
6337
6338         return I40E_SUCCESS;
6339 }
6340
6341 static int
6342 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6343 {
6344         int i, j, num;
6345         struct i40e_mac_filter *f;
6346         struct i40e_macvlan_filter *mv_f;
6347         int ret = I40E_SUCCESS;
6348
6349         if (vsi == NULL || vsi->mac_num == 0)
6350                 return I40E_ERR_PARAM;
6351
6352         /* Case that no vlan is set */
6353         if (vsi->vlan_num == 0)
6354                 num = vsi->mac_num;
6355         else
6356                 num = vsi->mac_num * vsi->vlan_num;
6357
6358         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6359         if (mv_f == NULL) {
6360                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6361                 return I40E_ERR_NO_MEMORY;
6362         }
6363
6364         i = 0;
6365         if (vsi->vlan_num == 0) {
6366                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6367                         rte_memcpy(&mv_f[i].macaddr,
6368                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6369                         mv_f[i].filter_type = f->mac_info.filter_type;
6370                         mv_f[i].vlan_id = 0;
6371                         i++;
6372                 }
6373         } else {
6374                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6375                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6376                                         vsi->vlan_num, &f->mac_info.mac_addr);
6377                         if (ret != I40E_SUCCESS)
6378                                 goto DONE;
6379                         for (j = i; j < i + vsi->vlan_num; j++)
6380                                 mv_f[j].filter_type = f->mac_info.filter_type;
6381                         i += vsi->vlan_num;
6382                 }
6383         }
6384
6385         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6386 DONE:
6387         rte_free(mv_f);
6388
6389         return ret;
6390 }
6391
6392 int
6393 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6394 {
6395         struct i40e_macvlan_filter *mv_f;
6396         int mac_num;
6397         int ret = I40E_SUCCESS;
6398
6399         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6400                 return I40E_ERR_PARAM;
6401
6402         /* If it's already set, just return */
6403         if (i40e_find_vlan_filter(vsi,vlan))
6404                 return I40E_SUCCESS;
6405
6406         mac_num = vsi->mac_num;
6407
6408         if (mac_num == 0) {
6409                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6410                 return I40E_ERR_PARAM;
6411         }
6412
6413         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6414
6415         if (mv_f == NULL) {
6416                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6417                 return I40E_ERR_NO_MEMORY;
6418         }
6419
6420         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6421
6422         if (ret != I40E_SUCCESS)
6423                 goto DONE;
6424
6425         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6426
6427         if (ret != I40E_SUCCESS)
6428                 goto DONE;
6429
6430         i40e_set_vlan_filter(vsi, vlan, 1);
6431
6432         vsi->vlan_num++;
6433         ret = I40E_SUCCESS;
6434 DONE:
6435         rte_free(mv_f);
6436         return ret;
6437 }
6438
6439 int
6440 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6441 {
6442         struct i40e_macvlan_filter *mv_f;
6443         int mac_num;
6444         int ret = I40E_SUCCESS;
6445
6446         /**
6447          * Vlan 0 is the generic filter for untagged packets
6448          * and can't be removed.
6449          */
6450         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6451                 return I40E_ERR_PARAM;
6452
6453         /* If can't find it, just return */
6454         if (!i40e_find_vlan_filter(vsi, vlan))
6455                 return I40E_ERR_PARAM;
6456
6457         mac_num = vsi->mac_num;
6458
6459         if (mac_num == 0) {
6460                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6461                 return I40E_ERR_PARAM;
6462         }
6463
6464         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6465
6466         if (mv_f == NULL) {
6467                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6468                 return I40E_ERR_NO_MEMORY;
6469         }
6470
6471         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6472
6473         if (ret != I40E_SUCCESS)
6474                 goto DONE;
6475
6476         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6477
6478         if (ret != I40E_SUCCESS)
6479                 goto DONE;
6480
6481         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6482         if (vsi->vlan_num == 1) {
6483                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6484                 if (ret != I40E_SUCCESS)
6485                         goto DONE;
6486
6487                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6488                 if (ret != I40E_SUCCESS)
6489                         goto DONE;
6490         }
6491
6492         i40e_set_vlan_filter(vsi, vlan, 0);
6493
6494         vsi->vlan_num--;
6495         ret = I40E_SUCCESS;
6496 DONE:
6497         rte_free(mv_f);
6498         return ret;
6499 }
6500
6501 int
6502 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6503 {
6504         struct i40e_mac_filter *f;
6505         struct i40e_macvlan_filter *mv_f;
6506         int i, vlan_num = 0;
6507         int ret = I40E_SUCCESS;
6508
6509         /* If it's add and we've config it, return */
6510         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6511         if (f != NULL)
6512                 return I40E_SUCCESS;
6513         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6514                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6515
6516                 /**
6517                  * If vlan_num is 0, that's the first time to add mac,
6518                  * set mask for vlan_id 0.
6519                  */
6520                 if (vsi->vlan_num == 0) {
6521                         i40e_set_vlan_filter(vsi, 0, 1);
6522                         vsi->vlan_num = 1;
6523                 }
6524                 vlan_num = vsi->vlan_num;
6525         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6526                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6527                 vlan_num = 1;
6528
6529         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6530         if (mv_f == NULL) {
6531                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6532                 return I40E_ERR_NO_MEMORY;
6533         }
6534
6535         for (i = 0; i < vlan_num; i++) {
6536                 mv_f[i].filter_type = mac_filter->filter_type;
6537                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6538                                 ETH_ADDR_LEN);
6539         }
6540
6541         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6542                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6543                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6544                                         &mac_filter->mac_addr);
6545                 if (ret != I40E_SUCCESS)
6546                         goto DONE;
6547         }
6548
6549         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6550         if (ret != I40E_SUCCESS)
6551                 goto DONE;
6552
6553         /* Add the mac addr into mac list */
6554         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6555         if (f == NULL) {
6556                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6557                 ret = I40E_ERR_NO_MEMORY;
6558                 goto DONE;
6559         }
6560         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6561                         ETH_ADDR_LEN);
6562         f->mac_info.filter_type = mac_filter->filter_type;
6563         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6564         vsi->mac_num++;
6565
6566         ret = I40E_SUCCESS;
6567 DONE:
6568         rte_free(mv_f);
6569
6570         return ret;
6571 }
6572
6573 int
6574 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6575 {
6576         struct i40e_mac_filter *f;
6577         struct i40e_macvlan_filter *mv_f;
6578         int i, vlan_num;
6579         enum rte_mac_filter_type filter_type;
6580         int ret = I40E_SUCCESS;
6581
6582         /* Can't find it, return an error */
6583         f = i40e_find_mac_filter(vsi, addr);
6584         if (f == NULL)
6585                 return I40E_ERR_PARAM;
6586
6587         vlan_num = vsi->vlan_num;
6588         filter_type = f->mac_info.filter_type;
6589         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6590                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6591                 if (vlan_num == 0) {
6592                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6593                         return I40E_ERR_PARAM;
6594                 }
6595         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6596                         filter_type == RTE_MAC_HASH_MATCH)
6597                 vlan_num = 1;
6598
6599         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6600         if (mv_f == NULL) {
6601                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6602                 return I40E_ERR_NO_MEMORY;
6603         }
6604
6605         for (i = 0; i < vlan_num; i++) {
6606                 mv_f[i].filter_type = filter_type;
6607                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6608                                 ETH_ADDR_LEN);
6609         }
6610         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6611                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6612                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6613                 if (ret != I40E_SUCCESS)
6614                         goto DONE;
6615         }
6616
6617         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6618         if (ret != I40E_SUCCESS)
6619                 goto DONE;
6620
6621         /* Remove the mac addr into mac list */
6622         TAILQ_REMOVE(&vsi->mac_list, f, next);
6623         rte_free(f);
6624         vsi->mac_num--;
6625
6626         ret = I40E_SUCCESS;
6627 DONE:
6628         rte_free(mv_f);
6629         return ret;
6630 }
6631
6632 /* Configure hash enable flags for RSS */
6633 uint64_t
6634 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6635 {
6636         uint64_t hena = 0;
6637         int i;
6638
6639         if (!flags)
6640                 return hena;
6641
6642         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6643                 if (flags & (1ULL << i))
6644                         hena |= adapter->pctypes_tbl[i];
6645         }
6646
6647         return hena;
6648 }
6649
6650 /* Parse the hash enable flags */
6651 uint64_t
6652 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6653 {
6654         uint64_t rss_hf = 0;
6655
6656         if (!flags)
6657                 return rss_hf;
6658         int i;
6659
6660         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6661                 if (flags & adapter->pctypes_tbl[i])
6662                         rss_hf |= (1ULL << i);
6663         }
6664         return rss_hf;
6665 }
6666
6667 /* Disable RSS */
6668 static void
6669 i40e_pf_disable_rss(struct i40e_pf *pf)
6670 {
6671         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6672
6673         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6674         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6675         I40E_WRITE_FLUSH(hw);
6676 }
6677
6678 static int
6679 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6680 {
6681         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6682         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6683         int ret = 0;
6684
6685         if (!key || key_len == 0) {
6686                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6687                 return 0;
6688         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6689                 sizeof(uint32_t)) {
6690                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6691                 return -EINVAL;
6692         }
6693
6694         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6695                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6696                         (struct i40e_aqc_get_set_rss_key_data *)key;
6697
6698                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6699                 if (ret)
6700                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6701         } else {
6702                 uint32_t *hash_key = (uint32_t *)key;
6703                 uint16_t i;
6704
6705                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6706                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6707                 I40E_WRITE_FLUSH(hw);
6708         }
6709
6710         return ret;
6711 }
6712
6713 static int
6714 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6715 {
6716         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6717         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6718         int ret;
6719
6720         if (!key || !key_len)
6721                 return -EINVAL;
6722
6723         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6724                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6725                         (struct i40e_aqc_get_set_rss_key_data *)key);
6726                 if (ret) {
6727                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6728                         return ret;
6729                 }
6730         } else {
6731                 uint32_t *key_dw = (uint32_t *)key;
6732                 uint16_t i;
6733
6734                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6735                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6736         }
6737         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6738
6739         return 0;
6740 }
6741
6742 static int
6743 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6744 {
6745         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6746         uint64_t hena;
6747         int ret;
6748
6749         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6750                                rss_conf->rss_key_len);
6751         if (ret)
6752                 return ret;
6753
6754         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6755         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6756         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6757         I40E_WRITE_FLUSH(hw);
6758
6759         return 0;
6760 }
6761
6762 static int
6763 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6764                          struct rte_eth_rss_conf *rss_conf)
6765 {
6766         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6767         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6768         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6769         uint64_t hena;
6770
6771         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6772         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6773
6774         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6775                 if (rss_hf != 0) /* Enable RSS */
6776                         return -EINVAL;
6777                 return 0; /* Nothing to do */
6778         }
6779         /* RSS enabled */
6780         if (rss_hf == 0) /* Disable RSS */
6781                 return -EINVAL;
6782
6783         return i40e_hw_rss_hash_set(pf, rss_conf);
6784 }
6785
6786 static int
6787 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6788                            struct rte_eth_rss_conf *rss_conf)
6789 {
6790         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6791         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6792         uint64_t hena;
6793
6794         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6795                          &rss_conf->rss_key_len);
6796
6797         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6798         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6799         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6800
6801         return 0;
6802 }
6803
6804 static int
6805 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6806 {
6807         switch (filter_type) {
6808         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6809                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6810                 break;
6811         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6812                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6813                 break;
6814         case RTE_TUNNEL_FILTER_IMAC_TENID:
6815                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6816                 break;
6817         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6818                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6819                 break;
6820         case ETH_TUNNEL_FILTER_IMAC:
6821                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6822                 break;
6823         case ETH_TUNNEL_FILTER_OIP:
6824                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6825                 break;
6826         case ETH_TUNNEL_FILTER_IIP:
6827                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6828                 break;
6829         default:
6830                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6831                 return -EINVAL;
6832         }
6833
6834         return 0;
6835 }
6836
6837 /* Convert tunnel filter structure */
6838 static int
6839 i40e_tunnel_filter_convert(
6840         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6841         struct i40e_tunnel_filter *tunnel_filter)
6842 {
6843         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6844                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6845         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6846                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6847         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6848         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6849              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6850             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6851                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6852         else
6853                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6854         tunnel_filter->input.flags = cld_filter->element.flags;
6855         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6856         tunnel_filter->queue = cld_filter->element.queue_number;
6857         rte_memcpy(tunnel_filter->input.general_fields,
6858                    cld_filter->general_fields,
6859                    sizeof(cld_filter->general_fields));
6860
6861         return 0;
6862 }
6863
6864 /* Check if there exists the tunnel filter */
6865 struct i40e_tunnel_filter *
6866 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6867                              const struct i40e_tunnel_filter_input *input)
6868 {
6869         int ret;
6870
6871         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6872         if (ret < 0)
6873                 return NULL;
6874
6875         return tunnel_rule->hash_map[ret];
6876 }
6877
6878 /* Add a tunnel filter into the SW list */
6879 static int
6880 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6881                              struct i40e_tunnel_filter *tunnel_filter)
6882 {
6883         struct i40e_tunnel_rule *rule = &pf->tunnel;
6884         int ret;
6885
6886         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6887         if (ret < 0) {
6888                 PMD_DRV_LOG(ERR,
6889                             "Failed to insert tunnel filter to hash table %d!",
6890                             ret);
6891                 return ret;
6892         }
6893         rule->hash_map[ret] = tunnel_filter;
6894
6895         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6896
6897         return 0;
6898 }
6899
6900 /* Delete a tunnel filter from the SW list */
6901 int
6902 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6903                           struct i40e_tunnel_filter_input *input)
6904 {
6905         struct i40e_tunnel_rule *rule = &pf->tunnel;
6906         struct i40e_tunnel_filter *tunnel_filter;
6907         int ret;
6908
6909         ret = rte_hash_del_key(rule->hash_table, input);
6910         if (ret < 0) {
6911                 PMD_DRV_LOG(ERR,
6912                             "Failed to delete tunnel filter to hash table %d!",
6913                             ret);
6914                 return ret;
6915         }
6916         tunnel_filter = rule->hash_map[ret];
6917         rule->hash_map[ret] = NULL;
6918
6919         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6920         rte_free(tunnel_filter);
6921
6922         return 0;
6923 }
6924
6925 int
6926 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6927                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6928                         uint8_t add)
6929 {
6930         uint16_t ip_type;
6931         uint32_t ipv4_addr;
6932         uint8_t i, tun_type = 0;
6933         /* internal varialbe to convert ipv6 byte order */
6934         uint32_t convert_ipv6[4];
6935         int val, ret = 0;
6936         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6937         struct i40e_vsi *vsi = pf->main_vsi;
6938         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6939         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6940         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6941         struct i40e_tunnel_filter *tunnel, *node;
6942         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6943
6944         cld_filter = rte_zmalloc("tunnel_filter",
6945                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6946         0);
6947
6948         if (NULL == cld_filter) {
6949                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6950                 return -ENOMEM;
6951         }
6952         pfilter = cld_filter;
6953
6954         ether_addr_copy(&tunnel_filter->outer_mac,
6955                         (struct ether_addr *)&pfilter->element.outer_mac);
6956         ether_addr_copy(&tunnel_filter->inner_mac,
6957                         (struct ether_addr *)&pfilter->element.inner_mac);
6958
6959         pfilter->element.inner_vlan =
6960                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6961         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6962                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6963                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6964                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6965                                 &rte_cpu_to_le_32(ipv4_addr),
6966                                 sizeof(pfilter->element.ipaddr.v4.data));
6967         } else {
6968                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6969                 for (i = 0; i < 4; i++) {
6970                         convert_ipv6[i] =
6971                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6972                 }
6973                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6974                            &convert_ipv6,
6975                            sizeof(pfilter->element.ipaddr.v6.data));
6976         }
6977
6978         /* check tunneled type */
6979         switch (tunnel_filter->tunnel_type) {
6980         case RTE_TUNNEL_TYPE_VXLAN:
6981                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6982                 break;
6983         case RTE_TUNNEL_TYPE_NVGRE:
6984                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6985                 break;
6986         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6987                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6988                 break;
6989         default:
6990                 /* Other tunnel types is not supported. */
6991                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6992                 rte_free(cld_filter);
6993                 return -EINVAL;
6994         }
6995
6996         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6997                                        &pfilter->element.flags);
6998         if (val < 0) {
6999                 rte_free(cld_filter);
7000                 return -EINVAL;
7001         }
7002
7003         pfilter->element.flags |= rte_cpu_to_le_16(
7004                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7005                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7006         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7007         pfilter->element.queue_number =
7008                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7009
7010         /* Check if there is the filter in SW list */
7011         memset(&check_filter, 0, sizeof(check_filter));
7012         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7013         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7014         if (add && node) {
7015                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7016                 return -EINVAL;
7017         }
7018
7019         if (!add && !node) {
7020                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7021                 return -EINVAL;
7022         }
7023
7024         if (add) {
7025                 ret = i40e_aq_add_cloud_filters(hw,
7026                                         vsi->seid, &cld_filter->element, 1);
7027                 if (ret < 0) {
7028                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7029                         return -ENOTSUP;
7030                 }
7031                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7032                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7033                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7034         } else {
7035                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7036                                                    &cld_filter->element, 1);
7037                 if (ret < 0) {
7038                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7039                         return -ENOTSUP;
7040                 }
7041                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7042         }
7043
7044         rte_free(cld_filter);
7045         return ret;
7046 }
7047
7048 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7049 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7050 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7051 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7052 #define I40E_TR_GRE_KEY_MASK                    0x400
7053 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7054 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7055
7056 static enum
7057 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7058 {
7059         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7060         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7061         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7062         enum i40e_status_code status = I40E_SUCCESS;
7063
7064         memset(&filter_replace, 0,
7065                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7066         memset(&filter_replace_buf, 0,
7067                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7068
7069         /* create L1 filter */
7070         filter_replace.old_filter_type =
7071                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7072         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7073         filter_replace.tr_bit = 0;
7074
7075         /* Prepare the buffer, 3 entries */
7076         filter_replace_buf.data[0] =
7077                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7078         filter_replace_buf.data[0] |=
7079                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7080         filter_replace_buf.data[2] = 0xFF;
7081         filter_replace_buf.data[3] = 0xFF;
7082         filter_replace_buf.data[4] =
7083                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7084         filter_replace_buf.data[4] |=
7085                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7086         filter_replace_buf.data[7] = 0xF0;
7087         filter_replace_buf.data[8]
7088                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7089         filter_replace_buf.data[8] |=
7090                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7091         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7092                 I40E_TR_GENEVE_KEY_MASK |
7093                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7094         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7095                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7096                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7097
7098         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7099                                                &filter_replace_buf);
7100         return status;
7101 }
7102
7103 static enum
7104 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7105 {
7106         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7107         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7108         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7109         enum i40e_status_code status = I40E_SUCCESS;
7110
7111         /* For MPLSoUDP */
7112         memset(&filter_replace, 0,
7113                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7114         memset(&filter_replace_buf, 0,
7115                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7116         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7117                 I40E_AQC_MIRROR_CLOUD_FILTER;
7118         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7119         filter_replace.new_filter_type =
7120                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7121         /* Prepare the buffer, 2 entries */
7122         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7123         filter_replace_buf.data[0] |=
7124                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7125         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7126         filter_replace_buf.data[4] |=
7127                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7128         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7129                                                &filter_replace_buf);
7130         if (status < 0)
7131                 return status;
7132
7133         /* For MPLSoGRE */
7134         memset(&filter_replace, 0,
7135                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7136         memset(&filter_replace_buf, 0,
7137                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7138
7139         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7140                 I40E_AQC_MIRROR_CLOUD_FILTER;
7141         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7142         filter_replace.new_filter_type =
7143                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7144         /* Prepare the buffer, 2 entries */
7145         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7146         filter_replace_buf.data[0] |=
7147                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7148         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7149         filter_replace_buf.data[4] |=
7150                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7151
7152         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7153                                                &filter_replace_buf);
7154         return status;
7155 }
7156
7157 static enum i40e_status_code
7158 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7159 {
7160         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7161         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7162         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7163         enum i40e_status_code status = I40E_SUCCESS;
7164
7165         /* For GTP-C */
7166         memset(&filter_replace, 0,
7167                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7168         memset(&filter_replace_buf, 0,
7169                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7170         /* create L1 filter */
7171         filter_replace.old_filter_type =
7172                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7173         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7174         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7175                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7176         /* Prepare the buffer, 2 entries */
7177         filter_replace_buf.data[0] =
7178                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7179         filter_replace_buf.data[0] |=
7180                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7181         filter_replace_buf.data[2] = 0xFF;
7182         filter_replace_buf.data[3] = 0xFF;
7183         filter_replace_buf.data[4] =
7184                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7185         filter_replace_buf.data[4] |=
7186                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7187         filter_replace_buf.data[6] = 0xFF;
7188         filter_replace_buf.data[7] = 0xFF;
7189         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7190                                                &filter_replace_buf);
7191         if (status < 0)
7192                 return status;
7193
7194         /* for GTP-U */
7195         memset(&filter_replace, 0,
7196                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7197         memset(&filter_replace_buf, 0,
7198                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7199         /* create L1 filter */
7200         filter_replace.old_filter_type =
7201                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7202         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7203         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7204                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7205         /* Prepare the buffer, 2 entries */
7206         filter_replace_buf.data[0] =
7207                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7208         filter_replace_buf.data[0] |=
7209                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7210         filter_replace_buf.data[2] = 0xFF;
7211         filter_replace_buf.data[3] = 0xFF;
7212         filter_replace_buf.data[4] =
7213                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7214         filter_replace_buf.data[4] |=
7215                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7216         filter_replace_buf.data[6] = 0xFF;
7217         filter_replace_buf.data[7] = 0xFF;
7218
7219         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7220                                                &filter_replace_buf);
7221         return status;
7222 }
7223
7224 static enum
7225 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7226 {
7227         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7228         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7229         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7230         enum i40e_status_code status = I40E_SUCCESS;
7231
7232         /* for GTP-C */
7233         memset(&filter_replace, 0,
7234                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7235         memset(&filter_replace_buf, 0,
7236                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7237         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7238         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7239         filter_replace.new_filter_type =
7240                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7241         /* Prepare the buffer, 2 entries */
7242         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7243         filter_replace_buf.data[0] |=
7244                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7245         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7246         filter_replace_buf.data[4] |=
7247                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7248         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7249                                                &filter_replace_buf);
7250         if (status < 0)
7251                 return status;
7252
7253         /* for GTP-U */
7254         memset(&filter_replace, 0,
7255                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7256         memset(&filter_replace_buf, 0,
7257                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7258         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7259         filter_replace.old_filter_type =
7260                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7261         filter_replace.new_filter_type =
7262                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7263         /* Prepare the buffer, 2 entries */
7264         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7265         filter_replace_buf.data[0] |=
7266                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7267         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7268         filter_replace_buf.data[4] |=
7269                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7270
7271         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7272                                                &filter_replace_buf);
7273         return status;
7274 }
7275
7276 int
7277 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7278                       struct i40e_tunnel_filter_conf *tunnel_filter,
7279                       uint8_t add)
7280 {
7281         uint16_t ip_type;
7282         uint32_t ipv4_addr;
7283         uint8_t i, tun_type = 0;
7284         /* internal variable to convert ipv6 byte order */
7285         uint32_t convert_ipv6[4];
7286         int val, ret = 0;
7287         struct i40e_pf_vf *vf = NULL;
7288         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7289         struct i40e_vsi *vsi;
7290         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7291         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7292         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7293         struct i40e_tunnel_filter *tunnel, *node;
7294         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7295         uint32_t teid_le;
7296         bool big_buffer = 0;
7297
7298         cld_filter = rte_zmalloc("tunnel_filter",
7299                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7300                          0);
7301
7302         if (cld_filter == NULL) {
7303                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7304                 return -ENOMEM;
7305         }
7306         pfilter = cld_filter;
7307
7308         ether_addr_copy(&tunnel_filter->outer_mac,
7309                         (struct ether_addr *)&pfilter->element.outer_mac);
7310         ether_addr_copy(&tunnel_filter->inner_mac,
7311                         (struct ether_addr *)&pfilter->element.inner_mac);
7312
7313         pfilter->element.inner_vlan =
7314                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7315         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7316                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7317                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7318                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7319                                 &rte_cpu_to_le_32(ipv4_addr),
7320                                 sizeof(pfilter->element.ipaddr.v4.data));
7321         } else {
7322                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7323                 for (i = 0; i < 4; i++) {
7324                         convert_ipv6[i] =
7325                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7326                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7327                 }
7328                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7329                            &convert_ipv6,
7330                            sizeof(pfilter->element.ipaddr.v6.data));
7331         }
7332
7333         /* check tunneled type */
7334         switch (tunnel_filter->tunnel_type) {
7335         case I40E_TUNNEL_TYPE_VXLAN:
7336                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7337                 break;
7338         case I40E_TUNNEL_TYPE_NVGRE:
7339                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7340                 break;
7341         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7342                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7343                 break;
7344         case I40E_TUNNEL_TYPE_MPLSoUDP:
7345                 if (!pf->mpls_replace_flag) {
7346                         i40e_replace_mpls_l1_filter(pf);
7347                         i40e_replace_mpls_cloud_filter(pf);
7348                         pf->mpls_replace_flag = 1;
7349                 }
7350                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7351                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7352                         teid_le >> 4;
7353                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7354                         (teid_le & 0xF) << 12;
7355                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7356                         0x40;
7357                 big_buffer = 1;
7358                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7359                 break;
7360         case I40E_TUNNEL_TYPE_MPLSoGRE:
7361                 if (!pf->mpls_replace_flag) {
7362                         i40e_replace_mpls_l1_filter(pf);
7363                         i40e_replace_mpls_cloud_filter(pf);
7364                         pf->mpls_replace_flag = 1;
7365                 }
7366                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7367                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7368                         teid_le >> 4;
7369                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7370                         (teid_le & 0xF) << 12;
7371                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7372                         0x0;
7373                 big_buffer = 1;
7374                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7375                 break;
7376         case I40E_TUNNEL_TYPE_GTPC:
7377                 if (!pf->gtp_replace_flag) {
7378                         i40e_replace_gtp_l1_filter(pf);
7379                         i40e_replace_gtp_cloud_filter(pf);
7380                         pf->gtp_replace_flag = 1;
7381                 }
7382                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7383                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7384                         (teid_le >> 16) & 0xFFFF;
7385                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7386                         teid_le & 0xFFFF;
7387                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7388                         0x0;
7389                 big_buffer = 1;
7390                 break;
7391         case I40E_TUNNEL_TYPE_GTPU:
7392                 if (!pf->gtp_replace_flag) {
7393                         i40e_replace_gtp_l1_filter(pf);
7394                         i40e_replace_gtp_cloud_filter(pf);
7395                         pf->gtp_replace_flag = 1;
7396                 }
7397                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7398                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7399                         (teid_le >> 16) & 0xFFFF;
7400                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7401                         teid_le & 0xFFFF;
7402                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7403                         0x0;
7404                 big_buffer = 1;
7405                 break;
7406         case I40E_TUNNEL_TYPE_QINQ:
7407                 if (!pf->qinq_replace_flag) {
7408                         ret = i40e_cloud_filter_qinq_create(pf);
7409                         if (ret < 0)
7410                                 PMD_DRV_LOG(DEBUG,
7411                                             "QinQ tunnel filter already created.");
7412                         pf->qinq_replace_flag = 1;
7413                 }
7414                 /*      Add in the General fields the values of
7415                  *      the Outer and Inner VLAN
7416                  *      Big Buffer should be set, see changes in
7417                  *      i40e_aq_add_cloud_filters
7418                  */
7419                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7420                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7421                 big_buffer = 1;
7422                 break;
7423         default:
7424                 /* Other tunnel types is not supported. */
7425                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7426                 rte_free(cld_filter);
7427                 return -EINVAL;
7428         }
7429
7430         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7431                 pfilter->element.flags =
7432                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7433         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7434                 pfilter->element.flags =
7435                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7436         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7437                 pfilter->element.flags =
7438                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7439         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7440                 pfilter->element.flags =
7441                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7442         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7443                 pfilter->element.flags |=
7444                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7445         else {
7446                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7447                                                 &pfilter->element.flags);
7448                 if (val < 0) {
7449                         rte_free(cld_filter);
7450                         return -EINVAL;
7451                 }
7452         }
7453
7454         pfilter->element.flags |= rte_cpu_to_le_16(
7455                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7456                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7457         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7458         pfilter->element.queue_number =
7459                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7460
7461         if (!tunnel_filter->is_to_vf)
7462                 vsi = pf->main_vsi;
7463         else {
7464                 if (tunnel_filter->vf_id >= pf->vf_num) {
7465                         PMD_DRV_LOG(ERR, "Invalid argument.");
7466                         return -EINVAL;
7467                 }
7468                 vf = &pf->vfs[tunnel_filter->vf_id];
7469                 vsi = vf->vsi;
7470         }
7471
7472         /* Check if there is the filter in SW list */
7473         memset(&check_filter, 0, sizeof(check_filter));
7474         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7475         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7476         check_filter.vf_id = tunnel_filter->vf_id;
7477         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7478         if (add && node) {
7479                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7480                 return -EINVAL;
7481         }
7482
7483         if (!add && !node) {
7484                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7485                 return -EINVAL;
7486         }
7487
7488         if (add) {
7489                 if (big_buffer)
7490                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7491                                                    vsi->seid, cld_filter, 1);
7492                 else
7493                         ret = i40e_aq_add_cloud_filters(hw,
7494                                         vsi->seid, &cld_filter->element, 1);
7495                 if (ret < 0) {
7496                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7497                         return -ENOTSUP;
7498                 }
7499                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7500                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7501                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7502         } else {
7503                 if (big_buffer)
7504                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7505                                 hw, vsi->seid, cld_filter, 1);
7506                 else
7507                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7508                                                    &cld_filter->element, 1);
7509                 if (ret < 0) {
7510                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7511                         return -ENOTSUP;
7512                 }
7513                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7514         }
7515
7516         rte_free(cld_filter);
7517         return ret;
7518 }
7519
7520 static int
7521 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7522 {
7523         uint8_t i;
7524
7525         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7526                 if (pf->vxlan_ports[i] == port)
7527                         return i;
7528         }
7529
7530         return -1;
7531 }
7532
7533 static int
7534 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7535 {
7536         int  idx, ret;
7537         uint8_t filter_idx;
7538         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7539
7540         idx = i40e_get_vxlan_port_idx(pf, port);
7541
7542         /* Check if port already exists */
7543         if (idx >= 0) {
7544                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7545                 return -EINVAL;
7546         }
7547
7548         /* Now check if there is space to add the new port */
7549         idx = i40e_get_vxlan_port_idx(pf, 0);
7550         if (idx < 0) {
7551                 PMD_DRV_LOG(ERR,
7552                         "Maximum number of UDP ports reached, not adding port %d",
7553                         port);
7554                 return -ENOSPC;
7555         }
7556
7557         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7558                                         &filter_idx, NULL);
7559         if (ret < 0) {
7560                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7561                 return -1;
7562         }
7563
7564         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7565                          port,  filter_idx);
7566
7567         /* New port: add it and mark its index in the bitmap */
7568         pf->vxlan_ports[idx] = port;
7569         pf->vxlan_bitmap |= (1 << idx);
7570
7571         if (!(pf->flags & I40E_FLAG_VXLAN))
7572                 pf->flags |= I40E_FLAG_VXLAN;
7573
7574         return 0;
7575 }
7576
7577 static int
7578 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7579 {
7580         int idx;
7581         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7582
7583         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7584                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7585                 return -EINVAL;
7586         }
7587
7588         idx = i40e_get_vxlan_port_idx(pf, port);
7589
7590         if (idx < 0) {
7591                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7592                 return -EINVAL;
7593         }
7594
7595         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7596                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7597                 return -1;
7598         }
7599
7600         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7601                         port, idx);
7602
7603         pf->vxlan_ports[idx] = 0;
7604         pf->vxlan_bitmap &= ~(1 << idx);
7605
7606         if (!pf->vxlan_bitmap)
7607                 pf->flags &= ~I40E_FLAG_VXLAN;
7608
7609         return 0;
7610 }
7611
7612 /* Add UDP tunneling port */
7613 static int
7614 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7615                              struct rte_eth_udp_tunnel *udp_tunnel)
7616 {
7617         int ret = 0;
7618         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7619
7620         if (udp_tunnel == NULL)
7621                 return -EINVAL;
7622
7623         switch (udp_tunnel->prot_type) {
7624         case RTE_TUNNEL_TYPE_VXLAN:
7625                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7626                 break;
7627
7628         case RTE_TUNNEL_TYPE_GENEVE:
7629         case RTE_TUNNEL_TYPE_TEREDO:
7630                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7631                 ret = -1;
7632                 break;
7633
7634         default:
7635                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7636                 ret = -1;
7637                 break;
7638         }
7639
7640         return ret;
7641 }
7642
7643 /* Remove UDP tunneling port */
7644 static int
7645 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7646                              struct rte_eth_udp_tunnel *udp_tunnel)
7647 {
7648         int ret = 0;
7649         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7650
7651         if (udp_tunnel == NULL)
7652                 return -EINVAL;
7653
7654         switch (udp_tunnel->prot_type) {
7655         case RTE_TUNNEL_TYPE_VXLAN:
7656                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7657                 break;
7658         case RTE_TUNNEL_TYPE_GENEVE:
7659         case RTE_TUNNEL_TYPE_TEREDO:
7660                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7661                 ret = -1;
7662                 break;
7663         default:
7664                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7665                 ret = -1;
7666                 break;
7667         }
7668
7669         return ret;
7670 }
7671
7672 /* Calculate the maximum number of contiguous PF queues that are configured */
7673 static int
7674 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7675 {
7676         struct rte_eth_dev_data *data = pf->dev_data;
7677         int i, num;
7678         struct i40e_rx_queue *rxq;
7679
7680         num = 0;
7681         for (i = 0; i < pf->lan_nb_qps; i++) {
7682                 rxq = data->rx_queues[i];
7683                 if (rxq && rxq->q_set)
7684                         num++;
7685                 else
7686                         break;
7687         }
7688
7689         return num;
7690 }
7691
7692 /* Configure RSS */
7693 static int
7694 i40e_pf_config_rss(struct i40e_pf *pf)
7695 {
7696         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7697         struct rte_eth_rss_conf rss_conf;
7698         uint32_t i, lut = 0;
7699         uint16_t j, num;
7700
7701         /*
7702          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7703          * It's necessary to calculate the actual PF queues that are configured.
7704          */
7705         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7706                 num = i40e_pf_calc_configured_queues_num(pf);
7707         else
7708                 num = pf->dev_data->nb_rx_queues;
7709
7710         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7711         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7712                         num);
7713
7714         if (num == 0) {
7715                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7716                 return -ENOTSUP;
7717         }
7718
7719         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7720                 if (j == num)
7721                         j = 0;
7722                 lut = (lut << 8) | (j & ((0x1 <<
7723                         hw->func_caps.rss_table_entry_width) - 1));
7724                 if ((i & 3) == 3)
7725                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7726         }
7727
7728         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7729         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7730                 i40e_pf_disable_rss(pf);
7731                 return 0;
7732         }
7733         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7734                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7735                 /* Random default keys */
7736                 static uint32_t rss_key_default[] = {0x6b793944,
7737                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7738                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7739                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7740
7741                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7742                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7743                                                         sizeof(uint32_t);
7744         }
7745
7746         return i40e_hw_rss_hash_set(pf, &rss_conf);
7747 }
7748
7749 static int
7750 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7751                                struct rte_eth_tunnel_filter_conf *filter)
7752 {
7753         if (pf == NULL || filter == NULL) {
7754                 PMD_DRV_LOG(ERR, "Invalid parameter");
7755                 return -EINVAL;
7756         }
7757
7758         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7759                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7760                 return -EINVAL;
7761         }
7762
7763         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7764                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7765                 return -EINVAL;
7766         }
7767
7768         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7769                 (is_zero_ether_addr(&filter->outer_mac))) {
7770                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7771                 return -EINVAL;
7772         }
7773
7774         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7775                 (is_zero_ether_addr(&filter->inner_mac))) {
7776                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7777                 return -EINVAL;
7778         }
7779
7780         return 0;
7781 }
7782
7783 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7784 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7785 static int
7786 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7787 {
7788         uint32_t val, reg;
7789         int ret = -EINVAL;
7790
7791         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7792         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7793
7794         if (len == 3) {
7795                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7796         } else if (len == 4) {
7797                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7798         } else {
7799                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7800                 return ret;
7801         }
7802
7803         if (reg != val) {
7804                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7805                                                    reg, NULL);
7806                 if (ret != 0)
7807                         return ret;
7808         } else {
7809                 ret = 0;
7810         }
7811         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7812                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7813
7814         return ret;
7815 }
7816
7817 static int
7818 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7819 {
7820         int ret = -EINVAL;
7821
7822         if (!hw || !cfg)
7823                 return -EINVAL;
7824
7825         switch (cfg->cfg_type) {
7826         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7827                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7828                 break;
7829         default:
7830                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7831                 break;
7832         }
7833
7834         return ret;
7835 }
7836
7837 static int
7838 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7839                                enum rte_filter_op filter_op,
7840                                void *arg)
7841 {
7842         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7843         int ret = I40E_ERR_PARAM;
7844
7845         switch (filter_op) {
7846         case RTE_ETH_FILTER_SET:
7847                 ret = i40e_dev_global_config_set(hw,
7848                         (struct rte_eth_global_cfg *)arg);
7849                 break;
7850         default:
7851                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7852                 break;
7853         }
7854
7855         return ret;
7856 }
7857
7858 static int
7859 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7860                           enum rte_filter_op filter_op,
7861                           void *arg)
7862 {
7863         struct rte_eth_tunnel_filter_conf *filter;
7864         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7865         int ret = I40E_SUCCESS;
7866
7867         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7868
7869         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7870                 return I40E_ERR_PARAM;
7871
7872         switch (filter_op) {
7873         case RTE_ETH_FILTER_NOP:
7874                 if (!(pf->flags & I40E_FLAG_VXLAN))
7875                         ret = I40E_NOT_SUPPORTED;
7876                 break;
7877         case RTE_ETH_FILTER_ADD:
7878                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7879                 break;
7880         case RTE_ETH_FILTER_DELETE:
7881                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7882                 break;
7883         default:
7884                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7885                 ret = I40E_ERR_PARAM;
7886                 break;
7887         }
7888
7889         return ret;
7890 }
7891
7892 static int
7893 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7894 {
7895         int ret = 0;
7896         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7897
7898         /* RSS setup */
7899         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7900                 ret = i40e_pf_config_rss(pf);
7901         else
7902                 i40e_pf_disable_rss(pf);
7903
7904         return ret;
7905 }
7906
7907 /* Get the symmetric hash enable configurations per port */
7908 static void
7909 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7910 {
7911         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7912
7913         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7914 }
7915
7916 /* Set the symmetric hash enable configurations per port */
7917 static void
7918 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7919 {
7920         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7921
7922         if (enable > 0) {
7923                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7924                         PMD_DRV_LOG(INFO,
7925                                 "Symmetric hash has already been enabled");
7926                         return;
7927                 }
7928                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7929         } else {
7930                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7931                         PMD_DRV_LOG(INFO,
7932                                 "Symmetric hash has already been disabled");
7933                         return;
7934                 }
7935                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7936         }
7937         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7938         I40E_WRITE_FLUSH(hw);
7939 }
7940
7941 /*
7942  * Get global configurations of hash function type and symmetric hash enable
7943  * per flow type (pctype). Note that global configuration means it affects all
7944  * the ports on the same NIC.
7945  */
7946 static int
7947 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7948                                    struct rte_eth_hash_global_conf *g_cfg)
7949 {
7950         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
7951         uint32_t reg;
7952         uint16_t i, j;
7953
7954         memset(g_cfg, 0, sizeof(*g_cfg));
7955         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7956         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7957                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7958         else
7959                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7960         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7961                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7962
7963         /*
7964          * We work only with lowest 32 bits which is not correct, but to work
7965          * properly the valid_bit_mask size should be increased up to 64 bits
7966          * and this will brake ABI. This modification will be done in next
7967          * release
7968          */
7969         g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
7970
7971         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
7972                 if (!adapter->pctypes_tbl[i])
7973                         continue;
7974                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
7975                      j < I40E_FILTER_PCTYPE_MAX; j++) {
7976                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
7977                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
7978                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
7979                                         g_cfg->sym_hash_enable_mask[0] |=
7980                                                                 (1UL << i);
7981                                 }
7982                         }
7983                 }
7984         }
7985
7986         return 0;
7987 }
7988
7989 static int
7990 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
7991                               const struct rte_eth_hash_global_conf *g_cfg)
7992 {
7993         uint32_t i;
7994         uint32_t mask0, i40e_mask = adapter->flow_types_mask;
7995
7996         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7997                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7998                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7999                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8000                                                 g_cfg->hash_func);
8001                 return -EINVAL;
8002         }
8003
8004         /*
8005          * As i40e supports less than 32 flow types, only first 32 bits need to
8006          * be checked.
8007          */
8008         mask0 = g_cfg->valid_bit_mask[0];
8009         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8010                 if (i == 0) {
8011                         /* Check if any unsupported flow type configured */
8012                         if ((mask0 | i40e_mask) ^ i40e_mask)
8013                                 goto mask_err;
8014                 } else {
8015                         if (g_cfg->valid_bit_mask[i])
8016                                 goto mask_err;
8017                 }
8018         }
8019
8020         return 0;
8021
8022 mask_err:
8023         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8024
8025         return -EINVAL;
8026 }
8027
8028 /*
8029  * Set global configurations of hash function type and symmetric hash enable
8030  * per flow type (pctype). Note any modifying global configuration will affect
8031  * all the ports on the same NIC.
8032  */
8033 static int
8034 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8035                                    struct rte_eth_hash_global_conf *g_cfg)
8036 {
8037         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8038         int ret;
8039         uint16_t i, j;
8040         uint32_t reg;
8041         /*
8042          * We work only with lowest 32 bits which is not correct, but to work
8043          * properly the valid_bit_mask size should be increased up to 64 bits
8044          * and this will brake ABI. This modification will be done in next
8045          * release
8046          */
8047         uint32_t mask0 = g_cfg->valid_bit_mask[0] &
8048                                         (uint32_t)adapter->flow_types_mask;
8049
8050         /* Check the input parameters */
8051         ret = i40e_hash_global_config_check(adapter, g_cfg);
8052         if (ret < 0)
8053                 return ret;
8054
8055         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
8056                 if (mask0 & (1UL << i)) {
8057                         reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
8058                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8059
8060                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8061                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8062                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8063                                         i40e_write_rx_ctl(hw,
8064                                                           I40E_GLQF_HSYM(j),
8065                                                           reg);
8066                         }
8067                 }
8068         }
8069
8070         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8071         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8072                 /* Toeplitz */
8073                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8074                         PMD_DRV_LOG(DEBUG,
8075                                 "Hash function already set to Toeplitz");
8076                         goto out;
8077                 }
8078                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8079         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8080                 /* Simple XOR */
8081                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8082                         PMD_DRV_LOG(DEBUG,
8083                                 "Hash function already set to Simple XOR");
8084                         goto out;
8085                 }
8086                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8087         } else
8088                 /* Use the default, and keep it as it is */
8089                 goto out;
8090
8091         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8092
8093 out:
8094         I40E_WRITE_FLUSH(hw);
8095
8096         return 0;
8097 }
8098
8099 /**
8100  * Valid input sets for hash and flow director filters per PCTYPE
8101  */
8102 static uint64_t
8103 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8104                 enum rte_filter_type filter)
8105 {
8106         uint64_t valid;
8107
8108         static const uint64_t valid_hash_inset_table[] = {
8109                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8110                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8111                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8112                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8113                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8114                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8115                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8116                         I40E_INSET_FLEX_PAYLOAD,
8117                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8118                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8119                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8120                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8121                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8122                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8123                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8124                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8125                         I40E_INSET_FLEX_PAYLOAD,
8126                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8127                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8128                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8129                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8130                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8131                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8132                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8133                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8134                         I40E_INSET_FLEX_PAYLOAD,
8135                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8136                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8137                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8138                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8139                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8140                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8141                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8142                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8143                         I40E_INSET_FLEX_PAYLOAD,
8144                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8145                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8146                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8147                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8148                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8149                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8150                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8151                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8152                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8153                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8154                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8155                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8156                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8157                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8158                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8159                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8160                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8161                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8162                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8163                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8164                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8165                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8166                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8167                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8168                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8169                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8170                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8171                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8172                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8173                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8174                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8175                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8176                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8177                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8178                         I40E_INSET_FLEX_PAYLOAD,
8179                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8180                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8181                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8182                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8183                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8184                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8185                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8186                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8187                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8188                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8189                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8190                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8191                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8192                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8193                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8194                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8195                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8196                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8197                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8198                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8199                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8200                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8201                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8202                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8203                         I40E_INSET_FLEX_PAYLOAD,
8204                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8205                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8206                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8207                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8208                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8209                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8210                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8211                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8212                         I40E_INSET_FLEX_PAYLOAD,
8213                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8214                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8215                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8216                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8217                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8218                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8219                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8220                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8221                         I40E_INSET_FLEX_PAYLOAD,
8222                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8223                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8224                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8225                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8226                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8227                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8228                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8229                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8230                         I40E_INSET_FLEX_PAYLOAD,
8231                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8232                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8233                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8234                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8235                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8236                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8237                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8238                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8239                         I40E_INSET_FLEX_PAYLOAD,
8240                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8241                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8242                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8243                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8244                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8245                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8246                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8247                         I40E_INSET_FLEX_PAYLOAD,
8248                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8249                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8250                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8251                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8252                         I40E_INSET_FLEX_PAYLOAD,
8253         };
8254
8255         /**
8256          * Flow director supports only fields defined in
8257          * union rte_eth_fdir_flow.
8258          */
8259         static const uint64_t valid_fdir_inset_table[] = {
8260                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8261                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8262                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8263                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8264                 I40E_INSET_IPV4_TTL,
8265                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8266                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8267                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8268                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8269                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8270                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8271                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8272                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8273                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8274                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8275                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8276                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8277                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8278                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8279                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8280                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8281                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8282                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8283                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8284                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8285                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8286                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8287                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8288                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8289                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8290                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8291                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8292                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8293                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8294                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8295                 I40E_INSET_SCTP_VT,
8296                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8297                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8298                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8299                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8300                 I40E_INSET_IPV4_TTL,
8301                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8302                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8303                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8304                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8305                 I40E_INSET_IPV6_HOP_LIMIT,
8306                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8307                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8308                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8309                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8310                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8311                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8312                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8313                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8314                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8315                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8316                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8317                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8318                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8319                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8320                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8321                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8322                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8323                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8324                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8325                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8326                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8327                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8328                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8329                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8330                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8331                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8332                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8333                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8334                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8335                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8336                 I40E_INSET_SCTP_VT,
8337                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8338                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8339                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8340                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8341                 I40E_INSET_IPV6_HOP_LIMIT,
8342                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8343                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8344                 I40E_INSET_LAST_ETHER_TYPE,
8345         };
8346
8347         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8348                 return 0;
8349         if (filter == RTE_ETH_FILTER_HASH)
8350                 valid = valid_hash_inset_table[pctype];
8351         else
8352                 valid = valid_fdir_inset_table[pctype];
8353
8354         return valid;
8355 }
8356
8357 /**
8358  * Validate if the input set is allowed for a specific PCTYPE
8359  */
8360 int
8361 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8362                 enum rte_filter_type filter, uint64_t inset)
8363 {
8364         uint64_t valid;
8365
8366         valid = i40e_get_valid_input_set(pctype, filter);
8367         if (inset & (~valid))
8368                 return -EINVAL;
8369
8370         return 0;
8371 }
8372
8373 /* default input set fields combination per pctype */
8374 uint64_t
8375 i40e_get_default_input_set(uint16_t pctype)
8376 {
8377         static const uint64_t default_inset_table[] = {
8378                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8379                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8380                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8381                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8382                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8383                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8384                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8385                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8386                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8387                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8388                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8389                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8390                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8391                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8392                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8393                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8394                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8395                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8396                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8397                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8398                         I40E_INSET_SCTP_VT,
8399                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8400                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8401                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8402                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8403                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8404                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8405                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8406                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8407                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8408                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8409                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8410                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8411                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8412                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8413                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8414                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8415                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8416                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8417                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8418                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8419                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8420                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8421                         I40E_INSET_SCTP_VT,
8422                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8423                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8424                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8425                         I40E_INSET_LAST_ETHER_TYPE,
8426         };
8427
8428         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8429                 return 0;
8430
8431         return default_inset_table[pctype];
8432 }
8433
8434 /**
8435  * Parse the input set from index to logical bit masks
8436  */
8437 static int
8438 i40e_parse_input_set(uint64_t *inset,
8439                      enum i40e_filter_pctype pctype,
8440                      enum rte_eth_input_set_field *field,
8441                      uint16_t size)
8442 {
8443         uint16_t i, j;
8444         int ret = -EINVAL;
8445
8446         static const struct {
8447                 enum rte_eth_input_set_field field;
8448                 uint64_t inset;
8449         } inset_convert_table[] = {
8450                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8451                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8452                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8453                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8454                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8455                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8456                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8457                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8458                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8459                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8460                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8461                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8462                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8463                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8464                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8465                         I40E_INSET_IPV6_NEXT_HDR},
8466                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8467                         I40E_INSET_IPV6_HOP_LIMIT},
8468                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8469                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8470                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8471                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8472                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8473                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8474                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8475                         I40E_INSET_SCTP_VT},
8476                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8477                         I40E_INSET_TUNNEL_DMAC},
8478                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8479                         I40E_INSET_VLAN_TUNNEL},
8480                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8481                         I40E_INSET_TUNNEL_ID},
8482                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8483                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8484                         I40E_INSET_FLEX_PAYLOAD_W1},
8485                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8486                         I40E_INSET_FLEX_PAYLOAD_W2},
8487                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8488                         I40E_INSET_FLEX_PAYLOAD_W3},
8489                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8490                         I40E_INSET_FLEX_PAYLOAD_W4},
8491                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8492                         I40E_INSET_FLEX_PAYLOAD_W5},
8493                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8494                         I40E_INSET_FLEX_PAYLOAD_W6},
8495                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8496                         I40E_INSET_FLEX_PAYLOAD_W7},
8497                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8498                         I40E_INSET_FLEX_PAYLOAD_W8},
8499         };
8500
8501         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8502                 return ret;
8503
8504         /* Only one item allowed for default or all */
8505         if (size == 1) {
8506                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8507                         *inset = i40e_get_default_input_set(pctype);
8508                         return 0;
8509                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8510                         *inset = I40E_INSET_NONE;
8511                         return 0;
8512                 }
8513         }
8514
8515         for (i = 0, *inset = 0; i < size; i++) {
8516                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8517                         if (field[i] == inset_convert_table[j].field) {
8518                                 *inset |= inset_convert_table[j].inset;
8519                                 break;
8520                         }
8521                 }
8522
8523                 /* It contains unsupported input set, return immediately */
8524                 if (j == RTE_DIM(inset_convert_table))
8525                         return ret;
8526         }
8527
8528         return 0;
8529 }
8530
8531 /**
8532  * Translate the input set from bit masks to register aware bit masks
8533  * and vice versa
8534  */
8535 uint64_t
8536 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8537 {
8538         uint64_t val = 0;
8539         uint16_t i;
8540
8541         struct inset_map {
8542                 uint64_t inset;
8543                 uint64_t inset_reg;
8544         };
8545
8546         static const struct inset_map inset_map_common[] = {
8547                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8548                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8549                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8550                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8551                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8552                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8553                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8554                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8555                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8556                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8557                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8558                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8559                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8560                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8561                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8562                 {I40E_INSET_TUNNEL_DMAC,
8563                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8564                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8565                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8566                 {I40E_INSET_TUNNEL_SRC_PORT,
8567                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8568                 {I40E_INSET_TUNNEL_DST_PORT,
8569                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8570                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8571                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8572                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8573                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8574                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8575                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8576                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8577                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8578                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8579         };
8580
8581     /* some different registers map in x722*/
8582         static const struct inset_map inset_map_diff_x722[] = {
8583                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8584                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8585                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8586                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8587         };
8588
8589         static const struct inset_map inset_map_diff_not_x722[] = {
8590                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8591                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8592                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8593                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8594         };
8595
8596         if (input == 0)
8597                 return val;
8598
8599         /* Translate input set to register aware inset */
8600         if (type == I40E_MAC_X722) {
8601                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8602                         if (input & inset_map_diff_x722[i].inset)
8603                                 val |= inset_map_diff_x722[i].inset_reg;
8604                 }
8605         } else {
8606                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8607                         if (input & inset_map_diff_not_x722[i].inset)
8608                                 val |= inset_map_diff_not_x722[i].inset_reg;
8609                 }
8610         }
8611
8612         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8613                 if (input & inset_map_common[i].inset)
8614                         val |= inset_map_common[i].inset_reg;
8615         }
8616
8617         return val;
8618 }
8619
8620 int
8621 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8622 {
8623         uint8_t i, idx = 0;
8624         uint64_t inset_need_mask = inset;
8625
8626         static const struct {
8627                 uint64_t inset;
8628                 uint32_t mask;
8629         } inset_mask_map[] = {
8630                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8631                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8632                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8633                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8634                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8635                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8636                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8637                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8638         };
8639
8640         if (!inset || !mask || !nb_elem)
8641                 return 0;
8642
8643         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8644                 /* Clear the inset bit, if no MASK is required,
8645                  * for example proto + ttl
8646                  */
8647                 if ((inset & inset_mask_map[i].inset) ==
8648                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8649                         inset_need_mask &= ~inset_mask_map[i].inset;
8650                 if (!inset_need_mask)
8651                         return 0;
8652         }
8653         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8654                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8655                     inset_mask_map[i].inset) {
8656                         if (idx >= nb_elem) {
8657                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8658                                 return -EINVAL;
8659                         }
8660                         mask[idx] = inset_mask_map[i].mask;
8661                         idx++;
8662                 }
8663         }
8664
8665         return idx;
8666 }
8667
8668 void
8669 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8670 {
8671         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8672
8673         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8674         if (reg != val)
8675                 i40e_write_rx_ctl(hw, addr, val);
8676         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8677                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8678 }
8679
8680 static void
8681 i40e_filter_input_set_init(struct i40e_pf *pf)
8682 {
8683         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8684         enum i40e_filter_pctype pctype;
8685         uint64_t input_set, inset_reg;
8686         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8687         int num, i;
8688         uint16_t flow_type;
8689
8690         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8691              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8692                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8693
8694                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8695                         continue;
8696
8697                 input_set = i40e_get_default_input_set(pctype);
8698
8699                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8700                                                    I40E_INSET_MASK_NUM_REG);
8701                 if (num < 0)
8702                         return;
8703                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8704                                         input_set);
8705
8706                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8707                                       (uint32_t)(inset_reg & UINT32_MAX));
8708                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8709                                      (uint32_t)((inset_reg >>
8710                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8711                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8712                                       (uint32_t)(inset_reg & UINT32_MAX));
8713                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8714                                      (uint32_t)((inset_reg >>
8715                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8716
8717                 for (i = 0; i < num; i++) {
8718                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8719                                              mask_reg[i]);
8720                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8721                                              mask_reg[i]);
8722                 }
8723                 /*clear unused mask registers of the pctype */
8724                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8725                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8726                                              0);
8727                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8728                                              0);
8729                 }
8730                 I40E_WRITE_FLUSH(hw);
8731
8732                 /* store the default input set */
8733                 pf->hash_input_set[pctype] = input_set;
8734                 pf->fdir.input_set[pctype] = input_set;
8735         }
8736 }
8737
8738 int
8739 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8740                          struct rte_eth_input_set_conf *conf)
8741 {
8742         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8743         enum i40e_filter_pctype pctype;
8744         uint64_t input_set, inset_reg = 0;
8745         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8746         int ret, i, num;
8747
8748         if (!conf) {
8749                 PMD_DRV_LOG(ERR, "Invalid pointer");
8750                 return -EFAULT;
8751         }
8752         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8753             conf->op != RTE_ETH_INPUT_SET_ADD) {
8754                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8755                 return -EINVAL;
8756         }
8757
8758         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8759         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8760                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8761                 return -EINVAL;
8762         }
8763
8764         if (hw->mac.type == I40E_MAC_X722) {
8765                 /* get translated pctype value in fd pctype register */
8766                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8767                         I40E_GLQF_FD_PCTYPES((int)pctype));
8768         }
8769
8770         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8771                                    conf->inset_size);
8772         if (ret) {
8773                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8774                 return -EINVAL;
8775         }
8776
8777         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8778                 /* get inset value in register */
8779                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8780                 inset_reg <<= I40E_32_BIT_WIDTH;
8781                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8782                 input_set |= pf->hash_input_set[pctype];
8783         }
8784         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8785                                            I40E_INSET_MASK_NUM_REG);
8786         if (num < 0)
8787                 return -EINVAL;
8788
8789         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8790
8791         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8792                               (uint32_t)(inset_reg & UINT32_MAX));
8793         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8794                              (uint32_t)((inset_reg >>
8795                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8796
8797         for (i = 0; i < num; i++)
8798                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8799                                      mask_reg[i]);
8800         /*clear unused mask registers of the pctype */
8801         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8802                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8803                                      0);
8804         I40E_WRITE_FLUSH(hw);
8805
8806         pf->hash_input_set[pctype] = input_set;
8807         return 0;
8808 }
8809
8810 int
8811 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8812                          struct rte_eth_input_set_conf *conf)
8813 {
8814         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8815         enum i40e_filter_pctype pctype;
8816         uint64_t input_set, inset_reg = 0;
8817         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8818         int ret, i, num;
8819
8820         if (!hw || !conf) {
8821                 PMD_DRV_LOG(ERR, "Invalid pointer");
8822                 return -EFAULT;
8823         }
8824         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8825             conf->op != RTE_ETH_INPUT_SET_ADD) {
8826                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8827                 return -EINVAL;
8828         }
8829
8830         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8831
8832         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8833                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8834                 return -EINVAL;
8835         }
8836
8837         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8838                                    conf->inset_size);
8839         if (ret) {
8840                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8841                 return -EINVAL;
8842         }
8843
8844         /* get inset value in register */
8845         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8846         inset_reg <<= I40E_32_BIT_WIDTH;
8847         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8848
8849         /* Can not change the inset reg for flex payload for fdir,
8850          * it is done by writing I40E_PRTQF_FD_FLXINSET
8851          * in i40e_set_flex_mask_on_pctype.
8852          */
8853         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8854                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8855         else
8856                 input_set |= pf->fdir.input_set[pctype];
8857         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8858                                            I40E_INSET_MASK_NUM_REG);
8859         if (num < 0)
8860                 return -EINVAL;
8861
8862         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8863
8864         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8865                               (uint32_t)(inset_reg & UINT32_MAX));
8866         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8867                              (uint32_t)((inset_reg >>
8868                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8869
8870         for (i = 0; i < num; i++)
8871                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8872                                      mask_reg[i]);
8873         /*clear unused mask registers of the pctype */
8874         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8875                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8876                                      0);
8877         I40E_WRITE_FLUSH(hw);
8878
8879         pf->fdir.input_set[pctype] = input_set;
8880         return 0;
8881 }
8882
8883 static int
8884 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8885 {
8886         int ret = 0;
8887
8888         if (!hw || !info) {
8889                 PMD_DRV_LOG(ERR, "Invalid pointer");
8890                 return -EFAULT;
8891         }
8892
8893         switch (info->info_type) {
8894         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8895                 i40e_get_symmetric_hash_enable_per_port(hw,
8896                                         &(info->info.enable));
8897                 break;
8898         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8899                 ret = i40e_get_hash_filter_global_config(hw,
8900                                 &(info->info.global_conf));
8901                 break;
8902         default:
8903                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8904                                                         info->info_type);
8905                 ret = -EINVAL;
8906                 break;
8907         }
8908
8909         return ret;
8910 }
8911
8912 static int
8913 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8914 {
8915         int ret = 0;
8916
8917         if (!hw || !info) {
8918                 PMD_DRV_LOG(ERR, "Invalid pointer");
8919                 return -EFAULT;
8920         }
8921
8922         switch (info->info_type) {
8923         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8924                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8925                 break;
8926         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8927                 ret = i40e_set_hash_filter_global_config(hw,
8928                                 &(info->info.global_conf));
8929                 break;
8930         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8931                 ret = i40e_hash_filter_inset_select(hw,
8932                                                &(info->info.input_set_conf));
8933                 break;
8934
8935         default:
8936                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8937                                                         info->info_type);
8938                 ret = -EINVAL;
8939                 break;
8940         }
8941
8942         return ret;
8943 }
8944
8945 /* Operations for hash function */
8946 static int
8947 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8948                       enum rte_filter_op filter_op,
8949                       void *arg)
8950 {
8951         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8952         int ret = 0;
8953
8954         switch (filter_op) {
8955         case RTE_ETH_FILTER_NOP:
8956                 break;
8957         case RTE_ETH_FILTER_GET:
8958                 ret = i40e_hash_filter_get(hw,
8959                         (struct rte_eth_hash_filter_info *)arg);
8960                 break;
8961         case RTE_ETH_FILTER_SET:
8962                 ret = i40e_hash_filter_set(hw,
8963                         (struct rte_eth_hash_filter_info *)arg);
8964                 break;
8965         default:
8966                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8967                                                                 filter_op);
8968                 ret = -ENOTSUP;
8969                 break;
8970         }
8971
8972         return ret;
8973 }
8974
8975 /* Convert ethertype filter structure */
8976 static int
8977 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8978                               struct i40e_ethertype_filter *filter)
8979 {
8980         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8981         filter->input.ether_type = input->ether_type;
8982         filter->flags = input->flags;
8983         filter->queue = input->queue;
8984
8985         return 0;
8986 }
8987
8988 /* Check if there exists the ehtertype filter */
8989 struct i40e_ethertype_filter *
8990 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8991                                 const struct i40e_ethertype_filter_input *input)
8992 {
8993         int ret;
8994
8995         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8996         if (ret < 0)
8997                 return NULL;
8998
8999         return ethertype_rule->hash_map[ret];
9000 }
9001
9002 /* Add ethertype filter in SW list */
9003 static int
9004 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9005                                 struct i40e_ethertype_filter *filter)
9006 {
9007         struct i40e_ethertype_rule *rule = &pf->ethertype;
9008         int ret;
9009
9010         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9011         if (ret < 0) {
9012                 PMD_DRV_LOG(ERR,
9013                             "Failed to insert ethertype filter"
9014                             " to hash table %d!",
9015                             ret);
9016                 return ret;
9017         }
9018         rule->hash_map[ret] = filter;
9019
9020         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9021
9022         return 0;
9023 }
9024
9025 /* Delete ethertype filter in SW list */
9026 int
9027 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9028                              struct i40e_ethertype_filter_input *input)
9029 {
9030         struct i40e_ethertype_rule *rule = &pf->ethertype;
9031         struct i40e_ethertype_filter *filter;
9032         int ret;
9033
9034         ret = rte_hash_del_key(rule->hash_table, input);
9035         if (ret < 0) {
9036                 PMD_DRV_LOG(ERR,
9037                             "Failed to delete ethertype filter"
9038                             " to hash table %d!",
9039                             ret);
9040                 return ret;
9041         }
9042         filter = rule->hash_map[ret];
9043         rule->hash_map[ret] = NULL;
9044
9045         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9046         rte_free(filter);
9047
9048         return 0;
9049 }
9050
9051 /*
9052  * Configure ethertype filter, which can director packet by filtering
9053  * with mac address and ether_type or only ether_type
9054  */
9055 int
9056 i40e_ethertype_filter_set(struct i40e_pf *pf,
9057                         struct rte_eth_ethertype_filter *filter,
9058                         bool add)
9059 {
9060         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9061         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9062         struct i40e_ethertype_filter *ethertype_filter, *node;
9063         struct i40e_ethertype_filter check_filter;
9064         struct i40e_control_filter_stats stats;
9065         uint16_t flags = 0;
9066         int ret;
9067
9068         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9069                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9070                 return -EINVAL;
9071         }
9072         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9073                 filter->ether_type == ETHER_TYPE_IPv6) {
9074                 PMD_DRV_LOG(ERR,
9075                         "unsupported ether_type(0x%04x) in control packet filter.",
9076                         filter->ether_type);
9077                 return -EINVAL;
9078         }
9079         if (filter->ether_type == ETHER_TYPE_VLAN)
9080                 PMD_DRV_LOG(WARNING,
9081                         "filter vlan ether_type in first tag is not supported.");
9082
9083         /* Check if there is the filter in SW list */
9084         memset(&check_filter, 0, sizeof(check_filter));
9085         i40e_ethertype_filter_convert(filter, &check_filter);
9086         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9087                                                &check_filter.input);
9088         if (add && node) {
9089                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9090                 return -EINVAL;
9091         }
9092
9093         if (!add && !node) {
9094                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9095                 return -EINVAL;
9096         }
9097
9098         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9099                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9100         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9101                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9102         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9103
9104         memset(&stats, 0, sizeof(stats));
9105         ret = i40e_aq_add_rem_control_packet_filter(hw,
9106                         filter->mac_addr.addr_bytes,
9107                         filter->ether_type, flags,
9108                         pf->main_vsi->seid,
9109                         filter->queue, add, &stats, NULL);
9110
9111         PMD_DRV_LOG(INFO,
9112                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9113                 ret, stats.mac_etype_used, stats.etype_used,
9114                 stats.mac_etype_free, stats.etype_free);
9115         if (ret < 0)
9116                 return -ENOSYS;
9117
9118         /* Add or delete a filter in SW list */
9119         if (add) {
9120                 ethertype_filter = rte_zmalloc("ethertype_filter",
9121                                        sizeof(*ethertype_filter), 0);
9122                 rte_memcpy(ethertype_filter, &check_filter,
9123                            sizeof(check_filter));
9124                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9125         } else {
9126                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9127         }
9128
9129         return ret;
9130 }
9131
9132 /*
9133  * Handle operations for ethertype filter.
9134  */
9135 static int
9136 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9137                                 enum rte_filter_op filter_op,
9138                                 void *arg)
9139 {
9140         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9141         int ret = 0;
9142
9143         if (filter_op == RTE_ETH_FILTER_NOP)
9144                 return ret;
9145
9146         if (arg == NULL) {
9147                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9148                             filter_op);
9149                 return -EINVAL;
9150         }
9151
9152         switch (filter_op) {
9153         case RTE_ETH_FILTER_ADD:
9154                 ret = i40e_ethertype_filter_set(pf,
9155                         (struct rte_eth_ethertype_filter *)arg,
9156                         TRUE);
9157                 break;
9158         case RTE_ETH_FILTER_DELETE:
9159                 ret = i40e_ethertype_filter_set(pf,
9160                         (struct rte_eth_ethertype_filter *)arg,
9161                         FALSE);
9162                 break;
9163         default:
9164                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9165                 ret = -ENOSYS;
9166                 break;
9167         }
9168         return ret;
9169 }
9170
9171 static int
9172 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9173                      enum rte_filter_type filter_type,
9174                      enum rte_filter_op filter_op,
9175                      void *arg)
9176 {
9177         int ret = 0;
9178
9179         if (dev == NULL)
9180                 return -EINVAL;
9181
9182         switch (filter_type) {
9183         case RTE_ETH_FILTER_NONE:
9184                 /* For global configuration */
9185                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9186                 break;
9187         case RTE_ETH_FILTER_HASH:
9188                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9189                 break;
9190         case RTE_ETH_FILTER_MACVLAN:
9191                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9192                 break;
9193         case RTE_ETH_FILTER_ETHERTYPE:
9194                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9195                 break;
9196         case RTE_ETH_FILTER_TUNNEL:
9197                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9198                 break;
9199         case RTE_ETH_FILTER_FDIR:
9200                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9201                 break;
9202         case RTE_ETH_FILTER_GENERIC:
9203                 if (filter_op != RTE_ETH_FILTER_GET)
9204                         return -EINVAL;
9205                 *(const void **)arg = &i40e_flow_ops;
9206                 break;
9207         default:
9208                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9209                                                         filter_type);
9210                 ret = -EINVAL;
9211                 break;
9212         }
9213
9214         return ret;
9215 }
9216
9217 /*
9218  * Check and enable Extended Tag.
9219  * Enabling Extended Tag is important for 40G performance.
9220  */
9221 static void
9222 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9223 {
9224         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9225         uint32_t buf = 0;
9226         int ret;
9227
9228         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9229                                       PCI_DEV_CAP_REG);
9230         if (ret < 0) {
9231                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9232                             PCI_DEV_CAP_REG);
9233                 return;
9234         }
9235         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9236                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9237                 return;
9238         }
9239
9240         buf = 0;
9241         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9242                                       PCI_DEV_CTRL_REG);
9243         if (ret < 0) {
9244                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9245                             PCI_DEV_CTRL_REG);
9246                 return;
9247         }
9248         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9249                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9250                 return;
9251         }
9252         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9253         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9254                                        PCI_DEV_CTRL_REG);
9255         if (ret < 0) {
9256                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9257                             PCI_DEV_CTRL_REG);
9258                 return;
9259         }
9260 }
9261
9262 /*
9263  * As some registers wouldn't be reset unless a global hardware reset,
9264  * hardware initialization is needed to put those registers into an
9265  * expected initial state.
9266  */
9267 static void
9268 i40e_hw_init(struct rte_eth_dev *dev)
9269 {
9270         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9271
9272         i40e_enable_extended_tag(dev);
9273
9274         /* clear the PF Queue Filter control register */
9275         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9276
9277         /* Disable symmetric hash per port */
9278         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9279 }
9280
9281 /*
9282  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9283  * however this function will return only one highest pctype index,
9284  * which is not quite correct. This is known problem of i40e driver
9285  * and needs to be fixed later.
9286  */
9287 enum i40e_filter_pctype
9288 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9289 {
9290         int i;
9291         uint64_t pctype_mask;
9292
9293         if (flow_type < I40E_FLOW_TYPE_MAX) {
9294                 pctype_mask = adapter->pctypes_tbl[flow_type];
9295                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9296                         if (pctype_mask & (1ULL << i))
9297                                 return (enum i40e_filter_pctype)i;
9298                 }
9299         }
9300         return I40E_FILTER_PCTYPE_INVALID;
9301 }
9302
9303 uint16_t
9304 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9305                         enum i40e_filter_pctype pctype)
9306 {
9307         uint16_t flowtype;
9308         uint64_t pctype_mask = 1ULL << pctype;
9309
9310         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9311              flowtype++) {
9312                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9313                         return flowtype;
9314         }
9315
9316         return RTE_ETH_FLOW_UNKNOWN;
9317 }
9318
9319 /*
9320  * On X710, performance number is far from the expectation on recent firmware
9321  * versions; on XL710, performance number is also far from the expectation on
9322  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9323  * mode is enabled and port MAC address is equal to the packet destination MAC
9324  * address. The fix for this issue may not be integrated in the following
9325  * firmware version. So the workaround in software driver is needed. It needs
9326  * to modify the initial values of 3 internal only registers for both X710 and
9327  * XL710. Note that the values for X710 or XL710 could be different, and the
9328  * workaround can be removed when it is fixed in firmware in the future.
9329  */
9330
9331 /* For both X710 and XL710 */
9332 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9333 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x20000200
9334 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9335
9336 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9337 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9338
9339 /* For X722 */
9340 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9341 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9342
9343 /* For X710 */
9344 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9345 /* For XL710 */
9346 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9347 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9348
9349 static int
9350 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9351 {
9352         enum i40e_status_code status;
9353         struct i40e_aq_get_phy_abilities_resp phy_ab;
9354         int ret = -ENOTSUP;
9355         int retries = 0;
9356
9357         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9358                                               NULL);
9359
9360         while (status) {
9361                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9362                         status);
9363                 retries++;
9364                 rte_delay_us(100000);
9365                 if  (retries < 5)
9366                         status = i40e_aq_get_phy_capabilities(hw, false,
9367                                         true, &phy_ab, NULL);
9368                 else
9369                         return ret;
9370         }
9371         return 0;
9372 }
9373
9374 static void
9375 i40e_configure_registers(struct i40e_hw *hw)
9376 {
9377         static struct {
9378                 uint32_t addr;
9379                 uint64_t val;
9380         } reg_table[] = {
9381                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9382                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9383                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9384         };
9385         uint64_t reg;
9386         uint32_t i;
9387         int ret;
9388
9389         for (i = 0; i < RTE_DIM(reg_table); i++) {
9390                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9391                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9392                                 reg_table[i].val =
9393                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9394                         else /* For X710/XL710/XXV710 */
9395                                 if (hw->aq.fw_maj_ver < 6)
9396                                         reg_table[i].val =
9397                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9398                                 else
9399                                         reg_table[i].val =
9400                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9401                 }
9402
9403                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9404                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9405                                 reg_table[i].val =
9406                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9407                         else /* For X710/XL710/XXV710 */
9408                                 reg_table[i].val =
9409                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9410                 }
9411
9412                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9413                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9414                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9415                                 reg_table[i].val =
9416                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9417                         else /* For X710 */
9418                                 reg_table[i].val =
9419                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9420                 }
9421
9422                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9423                                                         &reg, NULL);
9424                 if (ret < 0) {
9425                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9426                                                         reg_table[i].addr);
9427                         break;
9428                 }
9429                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9430                                                 reg_table[i].addr, reg);
9431                 if (reg == reg_table[i].val)
9432                         continue;
9433
9434                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9435                                                 reg_table[i].val, NULL);
9436                 if (ret < 0) {
9437                         PMD_DRV_LOG(ERR,
9438                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9439                                 reg_table[i].val, reg_table[i].addr);
9440                         break;
9441                 }
9442                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9443                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9444         }
9445 }
9446
9447 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9448 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9449 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9450 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9451 static int
9452 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9453 {
9454         uint32_t reg;
9455         int ret;
9456
9457         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9458                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9459                 return -EINVAL;
9460         }
9461
9462         /* Configure for double VLAN RX stripping */
9463         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9464         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9465                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9466                 ret = i40e_aq_debug_write_register(hw,
9467                                                    I40E_VSI_TSR(vsi->vsi_id),
9468                                                    reg, NULL);
9469                 if (ret < 0) {
9470                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9471                                     vsi->vsi_id);
9472                         return I40E_ERR_CONFIG;
9473                 }
9474         }
9475
9476         /* Configure for double VLAN TX insertion */
9477         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9478         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9479                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9480                 ret = i40e_aq_debug_write_register(hw,
9481                                                    I40E_VSI_L2TAGSTXVALID(
9482                                                    vsi->vsi_id), reg, NULL);
9483                 if (ret < 0) {
9484                         PMD_DRV_LOG(ERR,
9485                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9486                                 vsi->vsi_id);
9487                         return I40E_ERR_CONFIG;
9488                 }
9489         }
9490
9491         return 0;
9492 }
9493
9494 /**
9495  * i40e_aq_add_mirror_rule
9496  * @hw: pointer to the hardware structure
9497  * @seid: VEB seid to add mirror rule to
9498  * @dst_id: destination vsi seid
9499  * @entries: Buffer which contains the entities to be mirrored
9500  * @count: number of entities contained in the buffer
9501  * @rule_id:the rule_id of the rule to be added
9502  *
9503  * Add a mirror rule for a given veb.
9504  *
9505  **/
9506 static enum i40e_status_code
9507 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9508                         uint16_t seid, uint16_t dst_id,
9509                         uint16_t rule_type, uint16_t *entries,
9510                         uint16_t count, uint16_t *rule_id)
9511 {
9512         struct i40e_aq_desc desc;
9513         struct i40e_aqc_add_delete_mirror_rule cmd;
9514         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9515                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9516                 &desc.params.raw;
9517         uint16_t buff_len;
9518         enum i40e_status_code status;
9519
9520         i40e_fill_default_direct_cmd_desc(&desc,
9521                                           i40e_aqc_opc_add_mirror_rule);
9522         memset(&cmd, 0, sizeof(cmd));
9523
9524         buff_len = sizeof(uint16_t) * count;
9525         desc.datalen = rte_cpu_to_le_16(buff_len);
9526         if (buff_len > 0)
9527                 desc.flags |= rte_cpu_to_le_16(
9528                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9529         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9530                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9531         cmd.num_entries = rte_cpu_to_le_16(count);
9532         cmd.seid = rte_cpu_to_le_16(seid);
9533         cmd.destination = rte_cpu_to_le_16(dst_id);
9534
9535         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9536         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9537         PMD_DRV_LOG(INFO,
9538                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9539                 hw->aq.asq_last_status, resp->rule_id,
9540                 resp->mirror_rules_used, resp->mirror_rules_free);
9541         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9542
9543         return status;
9544 }
9545
9546 /**
9547  * i40e_aq_del_mirror_rule
9548  * @hw: pointer to the hardware structure
9549  * @seid: VEB seid to add mirror rule to
9550  * @entries: Buffer which contains the entities to be mirrored
9551  * @count: number of entities contained in the buffer
9552  * @rule_id:the rule_id of the rule to be delete
9553  *
9554  * Delete a mirror rule for a given veb.
9555  *
9556  **/
9557 static enum i40e_status_code
9558 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9559                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9560                 uint16_t count, uint16_t rule_id)
9561 {
9562         struct i40e_aq_desc desc;
9563         struct i40e_aqc_add_delete_mirror_rule cmd;
9564         uint16_t buff_len = 0;
9565         enum i40e_status_code status;
9566         void *buff = NULL;
9567
9568         i40e_fill_default_direct_cmd_desc(&desc,
9569                                           i40e_aqc_opc_delete_mirror_rule);
9570         memset(&cmd, 0, sizeof(cmd));
9571         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9572                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9573                                                           I40E_AQ_FLAG_RD));
9574                 cmd.num_entries = count;
9575                 buff_len = sizeof(uint16_t) * count;
9576                 desc.datalen = rte_cpu_to_le_16(buff_len);
9577                 buff = (void *)entries;
9578         } else
9579                 /* rule id is filled in destination field for deleting mirror rule */
9580                 cmd.destination = rte_cpu_to_le_16(rule_id);
9581
9582         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9583                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9584         cmd.seid = rte_cpu_to_le_16(seid);
9585
9586         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9587         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9588
9589         return status;
9590 }
9591
9592 /**
9593  * i40e_mirror_rule_set
9594  * @dev: pointer to the hardware structure
9595  * @mirror_conf: mirror rule info
9596  * @sw_id: mirror rule's sw_id
9597  * @on: enable/disable
9598  *
9599  * set a mirror rule.
9600  *
9601  **/
9602 static int
9603 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9604                         struct rte_eth_mirror_conf *mirror_conf,
9605                         uint8_t sw_id, uint8_t on)
9606 {
9607         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9608         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9609         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9610         struct i40e_mirror_rule *parent = NULL;
9611         uint16_t seid, dst_seid, rule_id;
9612         uint16_t i, j = 0;
9613         int ret;
9614
9615         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9616
9617         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9618                 PMD_DRV_LOG(ERR,
9619                         "mirror rule can not be configured without veb or vfs.");
9620                 return -ENOSYS;
9621         }
9622         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9623                 PMD_DRV_LOG(ERR, "mirror table is full.");
9624                 return -ENOSPC;
9625         }
9626         if (mirror_conf->dst_pool > pf->vf_num) {
9627                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9628                                  mirror_conf->dst_pool);
9629                 return -EINVAL;
9630         }
9631
9632         seid = pf->main_vsi->veb->seid;
9633
9634         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9635                 if (sw_id <= it->index) {
9636                         mirr_rule = it;
9637                         break;
9638                 }
9639                 parent = it;
9640         }
9641         if (mirr_rule && sw_id == mirr_rule->index) {
9642                 if (on) {
9643                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9644                         return -EEXIST;
9645                 } else {
9646                         ret = i40e_aq_del_mirror_rule(hw, seid,
9647                                         mirr_rule->rule_type,
9648                                         mirr_rule->entries,
9649                                         mirr_rule->num_entries, mirr_rule->id);
9650                         if (ret < 0) {
9651                                 PMD_DRV_LOG(ERR,
9652                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9653                                         ret, hw->aq.asq_last_status);
9654                                 return -ENOSYS;
9655                         }
9656                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9657                         rte_free(mirr_rule);
9658                         pf->nb_mirror_rule--;
9659                         return 0;
9660                 }
9661         } else if (!on) {
9662                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9663                 return -ENOENT;
9664         }
9665
9666         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9667                                 sizeof(struct i40e_mirror_rule) , 0);
9668         if (!mirr_rule) {
9669                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9670                 return I40E_ERR_NO_MEMORY;
9671         }
9672         switch (mirror_conf->rule_type) {
9673         case ETH_MIRROR_VLAN:
9674                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9675                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9676                                 mirr_rule->entries[j] =
9677                                         mirror_conf->vlan.vlan_id[i];
9678                                 j++;
9679                         }
9680                 }
9681                 if (j == 0) {
9682                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9683                         rte_free(mirr_rule);
9684                         return -EINVAL;
9685                 }
9686                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9687                 break;
9688         case ETH_MIRROR_VIRTUAL_POOL_UP:
9689         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9690                 /* check if the specified pool bit is out of range */
9691                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9692                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9693                         rte_free(mirr_rule);
9694                         return -EINVAL;
9695                 }
9696                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9697                         if (mirror_conf->pool_mask & (1ULL << i)) {
9698                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9699                                 j++;
9700                         }
9701                 }
9702                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9703                         /* add pf vsi to entries */
9704                         mirr_rule->entries[j] = pf->main_vsi_seid;
9705                         j++;
9706                 }
9707                 if (j == 0) {
9708                         PMD_DRV_LOG(ERR, "pool is not specified.");
9709                         rte_free(mirr_rule);
9710                         return -EINVAL;
9711                 }
9712                 /* egress and ingress in aq commands means from switch but not port */
9713                 mirr_rule->rule_type =
9714                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9715                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9716                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9717                 break;
9718         case ETH_MIRROR_UPLINK_PORT:
9719                 /* egress and ingress in aq commands means from switch but not port*/
9720                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9721                 break;
9722         case ETH_MIRROR_DOWNLINK_PORT:
9723                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9724                 break;
9725         default:
9726                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9727                         mirror_conf->rule_type);
9728                 rte_free(mirr_rule);
9729                 return -EINVAL;
9730         }
9731
9732         /* If the dst_pool is equal to vf_num, consider it as PF */
9733         if (mirror_conf->dst_pool == pf->vf_num)
9734                 dst_seid = pf->main_vsi_seid;
9735         else
9736                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9737
9738         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9739                                       mirr_rule->rule_type, mirr_rule->entries,
9740                                       j, &rule_id);
9741         if (ret < 0) {
9742                 PMD_DRV_LOG(ERR,
9743                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9744                         ret, hw->aq.asq_last_status);
9745                 rte_free(mirr_rule);
9746                 return -ENOSYS;
9747         }
9748
9749         mirr_rule->index = sw_id;
9750         mirr_rule->num_entries = j;
9751         mirr_rule->id = rule_id;
9752         mirr_rule->dst_vsi_seid = dst_seid;
9753
9754         if (parent)
9755                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9756         else
9757                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9758
9759         pf->nb_mirror_rule++;
9760         return 0;
9761 }
9762
9763 /**
9764  * i40e_mirror_rule_reset
9765  * @dev: pointer to the device
9766  * @sw_id: mirror rule's sw_id
9767  *
9768  * reset a mirror rule.
9769  *
9770  **/
9771 static int
9772 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9773 {
9774         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9775         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9776         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9777         uint16_t seid;
9778         int ret;
9779
9780         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9781
9782         seid = pf->main_vsi->veb->seid;
9783
9784         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9785                 if (sw_id == it->index) {
9786                         mirr_rule = it;
9787                         break;
9788                 }
9789         }
9790         if (mirr_rule) {
9791                 ret = i40e_aq_del_mirror_rule(hw, seid,
9792                                 mirr_rule->rule_type,
9793                                 mirr_rule->entries,
9794                                 mirr_rule->num_entries, mirr_rule->id);
9795                 if (ret < 0) {
9796                         PMD_DRV_LOG(ERR,
9797                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9798                                 ret, hw->aq.asq_last_status);
9799                         return -ENOSYS;
9800                 }
9801                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9802                 rte_free(mirr_rule);
9803                 pf->nb_mirror_rule--;
9804         } else {
9805                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9806                 return -ENOENT;
9807         }
9808         return 0;
9809 }
9810
9811 static uint64_t
9812 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9813 {
9814         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9815         uint64_t systim_cycles;
9816
9817         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9818         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9819                         << 32;
9820
9821         return systim_cycles;
9822 }
9823
9824 static uint64_t
9825 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9826 {
9827         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9828         uint64_t rx_tstamp;
9829
9830         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9831         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9832                         << 32;
9833
9834         return rx_tstamp;
9835 }
9836
9837 static uint64_t
9838 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9839 {
9840         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9841         uint64_t tx_tstamp;
9842
9843         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9844         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9845                         << 32;
9846
9847         return tx_tstamp;
9848 }
9849
9850 static void
9851 i40e_start_timecounters(struct rte_eth_dev *dev)
9852 {
9853         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9854         struct i40e_adapter *adapter =
9855                         (struct i40e_adapter *)dev->data->dev_private;
9856         struct rte_eth_link link;
9857         uint32_t tsync_inc_l;
9858         uint32_t tsync_inc_h;
9859
9860         /* Get current link speed. */
9861         memset(&link, 0, sizeof(link));
9862         i40e_dev_link_update(dev, 1);
9863         rte_i40e_dev_atomic_read_link_status(dev, &link);
9864
9865         switch (link.link_speed) {
9866         case ETH_SPEED_NUM_40G:
9867                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9868                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9869                 break;
9870         case ETH_SPEED_NUM_10G:
9871                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9872                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9873                 break;
9874         case ETH_SPEED_NUM_1G:
9875                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9876                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9877                 break;
9878         default:
9879                 tsync_inc_l = 0x0;
9880                 tsync_inc_h = 0x0;
9881         }
9882
9883         /* Set the timesync increment value. */
9884         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9885         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9886
9887         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9888         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9889         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9890
9891         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9892         adapter->systime_tc.cc_shift = 0;
9893         adapter->systime_tc.nsec_mask = 0;
9894
9895         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9896         adapter->rx_tstamp_tc.cc_shift = 0;
9897         adapter->rx_tstamp_tc.nsec_mask = 0;
9898
9899         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9900         adapter->tx_tstamp_tc.cc_shift = 0;
9901         adapter->tx_tstamp_tc.nsec_mask = 0;
9902 }
9903
9904 static int
9905 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9906 {
9907         struct i40e_adapter *adapter =
9908                         (struct i40e_adapter *)dev->data->dev_private;
9909
9910         adapter->systime_tc.nsec += delta;
9911         adapter->rx_tstamp_tc.nsec += delta;
9912         adapter->tx_tstamp_tc.nsec += delta;
9913
9914         return 0;
9915 }
9916
9917 static int
9918 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9919 {
9920         uint64_t ns;
9921         struct i40e_adapter *adapter =
9922                         (struct i40e_adapter *)dev->data->dev_private;
9923
9924         ns = rte_timespec_to_ns(ts);
9925
9926         /* Set the timecounters to a new value. */
9927         adapter->systime_tc.nsec = ns;
9928         adapter->rx_tstamp_tc.nsec = ns;
9929         adapter->tx_tstamp_tc.nsec = ns;
9930
9931         return 0;
9932 }
9933
9934 static int
9935 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9936 {
9937         uint64_t ns, systime_cycles;
9938         struct i40e_adapter *adapter =
9939                         (struct i40e_adapter *)dev->data->dev_private;
9940
9941         systime_cycles = i40e_read_systime_cyclecounter(dev);
9942         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9943         *ts = rte_ns_to_timespec(ns);
9944
9945         return 0;
9946 }
9947
9948 static int
9949 i40e_timesync_enable(struct rte_eth_dev *dev)
9950 {
9951         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9952         uint32_t tsync_ctl_l;
9953         uint32_t tsync_ctl_h;
9954
9955         /* Stop the timesync system time. */
9956         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9957         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9958         /* Reset the timesync system time value. */
9959         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9960         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9961
9962         i40e_start_timecounters(dev);
9963
9964         /* Clear timesync registers. */
9965         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9966         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9967         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9968         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9969         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9970         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9971
9972         /* Enable timestamping of PTP packets. */
9973         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9974         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9975
9976         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9977         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9978         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9979
9980         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9981         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9982
9983         return 0;
9984 }
9985
9986 static int
9987 i40e_timesync_disable(struct rte_eth_dev *dev)
9988 {
9989         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9990         uint32_t tsync_ctl_l;
9991         uint32_t tsync_ctl_h;
9992
9993         /* Disable timestamping of transmitted PTP packets. */
9994         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9995         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9996
9997         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9998         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9999
10000         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10001         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10002
10003         /* Reset the timesync increment value. */
10004         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10005         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10006
10007         return 0;
10008 }
10009
10010 static int
10011 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10012                                 struct timespec *timestamp, uint32_t flags)
10013 {
10014         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10015         struct i40e_adapter *adapter =
10016                 (struct i40e_adapter *)dev->data->dev_private;
10017
10018         uint32_t sync_status;
10019         uint32_t index = flags & 0x03;
10020         uint64_t rx_tstamp_cycles;
10021         uint64_t ns;
10022
10023         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10024         if ((sync_status & (1 << index)) == 0)
10025                 return -EINVAL;
10026
10027         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10028         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10029         *timestamp = rte_ns_to_timespec(ns);
10030
10031         return 0;
10032 }
10033
10034 static int
10035 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10036                                 struct timespec *timestamp)
10037 {
10038         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10039         struct i40e_adapter *adapter =
10040                 (struct i40e_adapter *)dev->data->dev_private;
10041
10042         uint32_t sync_status;
10043         uint64_t tx_tstamp_cycles;
10044         uint64_t ns;
10045
10046         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10047         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10048                 return -EINVAL;
10049
10050         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10051         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10052         *timestamp = rte_ns_to_timespec(ns);
10053
10054         return 0;
10055 }
10056
10057 /*
10058  * i40e_parse_dcb_configure - parse dcb configure from user
10059  * @dev: the device being configured
10060  * @dcb_cfg: pointer of the result of parse
10061  * @*tc_map: bit map of enabled traffic classes
10062  *
10063  * Returns 0 on success, negative value on failure
10064  */
10065 static int
10066 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10067                          struct i40e_dcbx_config *dcb_cfg,
10068                          uint8_t *tc_map)
10069 {
10070         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10071         uint8_t i, tc_bw, bw_lf;
10072
10073         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10074
10075         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10076         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10077                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10078                 return -EINVAL;
10079         }
10080
10081         /* assume each tc has the same bw */
10082         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10083         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10084                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10085         /* to ensure the sum of tcbw is equal to 100 */
10086         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10087         for (i = 0; i < bw_lf; i++)
10088                 dcb_cfg->etscfg.tcbwtable[i]++;
10089
10090         /* assume each tc has the same Transmission Selection Algorithm */
10091         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10092                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10093
10094         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10095                 dcb_cfg->etscfg.prioritytable[i] =
10096                                 dcb_rx_conf->dcb_tc[i];
10097
10098         /* FW needs one App to configure HW */
10099         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10100         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10101         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10102         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10103
10104         if (dcb_rx_conf->nb_tcs == 0)
10105                 *tc_map = 1; /* tc0 only */
10106         else
10107                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10108
10109         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10110                 dcb_cfg->pfc.willing = 0;
10111                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10112                 dcb_cfg->pfc.pfcenable = *tc_map;
10113         }
10114         return 0;
10115 }
10116
10117
10118 static enum i40e_status_code
10119 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10120                               struct i40e_aqc_vsi_properties_data *info,
10121                               uint8_t enabled_tcmap)
10122 {
10123         enum i40e_status_code ret;
10124         int i, total_tc = 0;
10125         uint16_t qpnum_per_tc, bsf, qp_idx;
10126         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10127         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10128         uint16_t used_queues;
10129
10130         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10131         if (ret != I40E_SUCCESS)
10132                 return ret;
10133
10134         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10135                 if (enabled_tcmap & (1 << i))
10136                         total_tc++;
10137         }
10138         if (total_tc == 0)
10139                 total_tc = 1;
10140         vsi->enabled_tc = enabled_tcmap;
10141
10142         /* different VSI has different queues assigned */
10143         if (vsi->type == I40E_VSI_MAIN)
10144                 used_queues = dev_data->nb_rx_queues -
10145                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10146         else if (vsi->type == I40E_VSI_VMDQ2)
10147                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10148         else {
10149                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10150                 return I40E_ERR_NO_AVAILABLE_VSI;
10151         }
10152
10153         qpnum_per_tc = used_queues / total_tc;
10154         /* Number of queues per enabled TC */
10155         if (qpnum_per_tc == 0) {
10156                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10157                 return I40E_ERR_INVALID_QP_ID;
10158         }
10159         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10160                                 I40E_MAX_Q_PER_TC);
10161         bsf = rte_bsf32(qpnum_per_tc);
10162
10163         /**
10164          * Configure TC and queue mapping parameters, for enabled TC,
10165          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10166          * default queue will serve it.
10167          */
10168         qp_idx = 0;
10169         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10170                 if (vsi->enabled_tc & (1 << i)) {
10171                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10172                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10173                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10174                         qp_idx += qpnum_per_tc;
10175                 } else
10176                         info->tc_mapping[i] = 0;
10177         }
10178
10179         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10180         if (vsi->type == I40E_VSI_SRIOV) {
10181                 info->mapping_flags |=
10182                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10183                 for (i = 0; i < vsi->nb_qps; i++)
10184                         info->queue_mapping[i] =
10185                                 rte_cpu_to_le_16(vsi->base_queue + i);
10186         } else {
10187                 info->mapping_flags |=
10188                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10189                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10190         }
10191         info->valid_sections |=
10192                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10193
10194         return I40E_SUCCESS;
10195 }
10196
10197 /*
10198  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10199  * @veb: VEB to be configured
10200  * @tc_map: enabled TC bitmap
10201  *
10202  * Returns 0 on success, negative value on failure
10203  */
10204 static enum i40e_status_code
10205 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10206 {
10207         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10208         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10209         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10210         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10211         enum i40e_status_code ret = I40E_SUCCESS;
10212         int i;
10213         uint32_t bw_max;
10214
10215         /* Check if enabled_tc is same as existing or new TCs */
10216         if (veb->enabled_tc == tc_map)
10217                 return ret;
10218
10219         /* configure tc bandwidth */
10220         memset(&veb_bw, 0, sizeof(veb_bw));
10221         veb_bw.tc_valid_bits = tc_map;
10222         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10223         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10224                 if (tc_map & BIT_ULL(i))
10225                         veb_bw.tc_bw_share_credits[i] = 1;
10226         }
10227         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10228                                                    &veb_bw, NULL);
10229         if (ret) {
10230                 PMD_INIT_LOG(ERR,
10231                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10232                         hw->aq.asq_last_status);
10233                 return ret;
10234         }
10235
10236         memset(&ets_query, 0, sizeof(ets_query));
10237         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10238                                                    &ets_query, NULL);
10239         if (ret != I40E_SUCCESS) {
10240                 PMD_DRV_LOG(ERR,
10241                         "Failed to get switch_comp ETS configuration %u",
10242                         hw->aq.asq_last_status);
10243                 return ret;
10244         }
10245         memset(&bw_query, 0, sizeof(bw_query));
10246         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10247                                                   &bw_query, NULL);
10248         if (ret != I40E_SUCCESS) {
10249                 PMD_DRV_LOG(ERR,
10250                         "Failed to get switch_comp bandwidth configuration %u",
10251                         hw->aq.asq_last_status);
10252                 return ret;
10253         }
10254
10255         /* store and print out BW info */
10256         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10257         veb->bw_info.bw_max = ets_query.tc_bw_max;
10258         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10259         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10260         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10261                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10262                      I40E_16_BIT_WIDTH);
10263         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10264                 veb->bw_info.bw_ets_share_credits[i] =
10265                                 bw_query.tc_bw_share_credits[i];
10266                 veb->bw_info.bw_ets_credits[i] =
10267                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10268                 /* 4 bits per TC, 4th bit is reserved */
10269                 veb->bw_info.bw_ets_max[i] =
10270                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10271                                   RTE_LEN2MASK(3, uint8_t));
10272                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10273                             veb->bw_info.bw_ets_share_credits[i]);
10274                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10275                             veb->bw_info.bw_ets_credits[i]);
10276                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10277                             veb->bw_info.bw_ets_max[i]);
10278         }
10279
10280         veb->enabled_tc = tc_map;
10281
10282         return ret;
10283 }
10284
10285
10286 /*
10287  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10288  * @vsi: VSI to be configured
10289  * @tc_map: enabled TC bitmap
10290  *
10291  * Returns 0 on success, negative value on failure
10292  */
10293 static enum i40e_status_code
10294 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10295 {
10296         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10297         struct i40e_vsi_context ctxt;
10298         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10299         enum i40e_status_code ret = I40E_SUCCESS;
10300         int i;
10301
10302         /* Check if enabled_tc is same as existing or new TCs */
10303         if (vsi->enabled_tc == tc_map)
10304                 return ret;
10305
10306         /* configure tc bandwidth */
10307         memset(&bw_data, 0, sizeof(bw_data));
10308         bw_data.tc_valid_bits = tc_map;
10309         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10310         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10311                 if (tc_map & BIT_ULL(i))
10312                         bw_data.tc_bw_credits[i] = 1;
10313         }
10314         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10315         if (ret) {
10316                 PMD_INIT_LOG(ERR,
10317                         "AQ command Config VSI BW allocation per TC failed = %d",
10318                         hw->aq.asq_last_status);
10319                 goto out;
10320         }
10321         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10322                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10323
10324         /* Update Queue Pairs Mapping for currently enabled UPs */
10325         ctxt.seid = vsi->seid;
10326         ctxt.pf_num = hw->pf_id;
10327         ctxt.vf_num = 0;
10328         ctxt.uplink_seid = vsi->uplink_seid;
10329         ctxt.info = vsi->info;
10330         i40e_get_cap(hw);
10331         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10332         if (ret)
10333                 goto out;
10334
10335         /* Update the VSI after updating the VSI queue-mapping information */
10336         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10337         if (ret) {
10338                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10339                         hw->aq.asq_last_status);
10340                 goto out;
10341         }
10342         /* update the local VSI info with updated queue map */
10343         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10344                                         sizeof(vsi->info.tc_mapping));
10345         rte_memcpy(&vsi->info.queue_mapping,
10346                         &ctxt.info.queue_mapping,
10347                 sizeof(vsi->info.queue_mapping));
10348         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10349         vsi->info.valid_sections = 0;
10350
10351         /* query and update current VSI BW information */
10352         ret = i40e_vsi_get_bw_config(vsi);
10353         if (ret) {
10354                 PMD_INIT_LOG(ERR,
10355                          "Failed updating vsi bw info, err %s aq_err %s",
10356                          i40e_stat_str(hw, ret),
10357                          i40e_aq_str(hw, hw->aq.asq_last_status));
10358                 goto out;
10359         }
10360
10361         vsi->enabled_tc = tc_map;
10362
10363 out:
10364         return ret;
10365 }
10366
10367 /*
10368  * i40e_dcb_hw_configure - program the dcb setting to hw
10369  * @pf: pf the configuration is taken on
10370  * @new_cfg: new configuration
10371  * @tc_map: enabled TC bitmap
10372  *
10373  * Returns 0 on success, negative value on failure
10374  */
10375 static enum i40e_status_code
10376 i40e_dcb_hw_configure(struct i40e_pf *pf,
10377                       struct i40e_dcbx_config *new_cfg,
10378                       uint8_t tc_map)
10379 {
10380         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10381         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10382         struct i40e_vsi *main_vsi = pf->main_vsi;
10383         struct i40e_vsi_list *vsi_list;
10384         enum i40e_status_code ret;
10385         int i;
10386         uint32_t val;
10387
10388         /* Use the FW API if FW > v4.4*/
10389         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10390               (hw->aq.fw_maj_ver >= 5))) {
10391                 PMD_INIT_LOG(ERR,
10392                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10393                 return I40E_ERR_FIRMWARE_API_VERSION;
10394         }
10395
10396         /* Check if need reconfiguration */
10397         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10398                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10399                 return I40E_SUCCESS;
10400         }
10401
10402         /* Copy the new config to the current config */
10403         *old_cfg = *new_cfg;
10404         old_cfg->etsrec = old_cfg->etscfg;
10405         ret = i40e_set_dcb_config(hw);
10406         if (ret) {
10407                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10408                          i40e_stat_str(hw, ret),
10409                          i40e_aq_str(hw, hw->aq.asq_last_status));
10410                 return ret;
10411         }
10412         /* set receive Arbiter to RR mode and ETS scheme by default */
10413         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10414                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10415                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10416                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10417                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10418                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10419                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10420                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10421                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10422                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10423                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10424                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10425                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10426         }
10427         /* get local mib to check whether it is configured correctly */
10428         /* IEEE mode */
10429         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10430         /* Get Local DCB Config */
10431         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10432                                      &hw->local_dcbx_config);
10433
10434         /* if Veb is created, need to update TC of it at first */
10435         if (main_vsi->veb) {
10436                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10437                 if (ret)
10438                         PMD_INIT_LOG(WARNING,
10439                                  "Failed configuring TC for VEB seid=%d",
10440                                  main_vsi->veb->seid);
10441         }
10442         /* Update each VSI */
10443         i40e_vsi_config_tc(main_vsi, tc_map);
10444         if (main_vsi->veb) {
10445                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10446                         /* Beside main VSI and VMDQ VSIs, only enable default
10447                          * TC for other VSIs
10448                          */
10449                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10450                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10451                                                          tc_map);
10452                         else
10453                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10454                                                          I40E_DEFAULT_TCMAP);
10455                         if (ret)
10456                                 PMD_INIT_LOG(WARNING,
10457                                         "Failed configuring TC for VSI seid=%d",
10458                                         vsi_list->vsi->seid);
10459                         /* continue */
10460                 }
10461         }
10462         return I40E_SUCCESS;
10463 }
10464
10465 /*
10466  * i40e_dcb_init_configure - initial dcb config
10467  * @dev: device being configured
10468  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10469  *
10470  * Returns 0 on success, negative value on failure
10471  */
10472 static int
10473 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10474 {
10475         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10476         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10477         int i, ret = 0;
10478
10479         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10480                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10481                 return -ENOTSUP;
10482         }
10483
10484         /* DCB initialization:
10485          * Update DCB configuration from the Firmware and configure
10486          * LLDP MIB change event.
10487          */
10488         if (sw_dcb == TRUE) {
10489                 ret = i40e_init_dcb(hw);
10490                 /* If lldp agent is stopped, the return value from
10491                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10492                  * adminq status. Otherwise, it should return success.
10493                  */
10494                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10495                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10496                         memset(&hw->local_dcbx_config, 0,
10497                                 sizeof(struct i40e_dcbx_config));
10498                         /* set dcb default configuration */
10499                         hw->local_dcbx_config.etscfg.willing = 0;
10500                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10501                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10502                         hw->local_dcbx_config.etscfg.tsatable[0] =
10503                                                 I40E_IEEE_TSA_ETS;
10504                         /* all UPs mapping to TC0 */
10505                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10506                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10507                         hw->local_dcbx_config.etsrec =
10508                                 hw->local_dcbx_config.etscfg;
10509                         hw->local_dcbx_config.pfc.willing = 0;
10510                         hw->local_dcbx_config.pfc.pfccap =
10511                                                 I40E_MAX_TRAFFIC_CLASS;
10512                         /* FW needs one App to configure HW */
10513                         hw->local_dcbx_config.numapps = 1;
10514                         hw->local_dcbx_config.app[0].selector =
10515                                                 I40E_APP_SEL_ETHTYPE;
10516                         hw->local_dcbx_config.app[0].priority = 3;
10517                         hw->local_dcbx_config.app[0].protocolid =
10518                                                 I40E_APP_PROTOID_FCOE;
10519                         ret = i40e_set_dcb_config(hw);
10520                         if (ret) {
10521                                 PMD_INIT_LOG(ERR,
10522                                         "default dcb config fails. err = %d, aq_err = %d.",
10523                                         ret, hw->aq.asq_last_status);
10524                                 return -ENOSYS;
10525                         }
10526                 } else {
10527                         PMD_INIT_LOG(ERR,
10528                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10529                                 ret, hw->aq.asq_last_status);
10530                         return -ENOTSUP;
10531                 }
10532         } else {
10533                 ret = i40e_aq_start_lldp(hw, NULL);
10534                 if (ret != I40E_SUCCESS)
10535                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10536
10537                 ret = i40e_init_dcb(hw);
10538                 if (!ret) {
10539                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10540                                 PMD_INIT_LOG(ERR,
10541                                         "HW doesn't support DCBX offload.");
10542                                 return -ENOTSUP;
10543                         }
10544                 } else {
10545                         PMD_INIT_LOG(ERR,
10546                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10547                                 ret, hw->aq.asq_last_status);
10548                         return -ENOTSUP;
10549                 }
10550         }
10551         return 0;
10552 }
10553
10554 /*
10555  * i40e_dcb_setup - setup dcb related config
10556  * @dev: device being configured
10557  *
10558  * Returns 0 on success, negative value on failure
10559  */
10560 static int
10561 i40e_dcb_setup(struct rte_eth_dev *dev)
10562 {
10563         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10564         struct i40e_dcbx_config dcb_cfg;
10565         uint8_t tc_map = 0;
10566         int ret = 0;
10567
10568         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10569                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10570                 return -ENOTSUP;
10571         }
10572
10573         if (pf->vf_num != 0)
10574                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10575
10576         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10577         if (ret) {
10578                 PMD_INIT_LOG(ERR, "invalid dcb config");
10579                 return -EINVAL;
10580         }
10581         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10582         if (ret) {
10583                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10584                 return -ENOSYS;
10585         }
10586
10587         return 0;
10588 }
10589
10590 static int
10591 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10592                       struct rte_eth_dcb_info *dcb_info)
10593 {
10594         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10595         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10596         struct i40e_vsi *vsi = pf->main_vsi;
10597         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10598         uint16_t bsf, tc_mapping;
10599         int i, j = 0;
10600
10601         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10602                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10603         else
10604                 dcb_info->nb_tcs = 1;
10605         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10606                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10607         for (i = 0; i < dcb_info->nb_tcs; i++)
10608                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10609
10610         /* get queue mapping if vmdq is disabled */
10611         if (!pf->nb_cfg_vmdq_vsi) {
10612                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10613                         if (!(vsi->enabled_tc & (1 << i)))
10614                                 continue;
10615                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10616                         dcb_info->tc_queue.tc_rxq[j][i].base =
10617                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10618                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10619                         dcb_info->tc_queue.tc_txq[j][i].base =
10620                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10621                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10622                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10623                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10624                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10625                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10626                 }
10627                 return 0;
10628         }
10629
10630         /* get queue mapping if vmdq is enabled */
10631         do {
10632                 vsi = pf->vmdq[j].vsi;
10633                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10634                         if (!(vsi->enabled_tc & (1 << i)))
10635                                 continue;
10636                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10637                         dcb_info->tc_queue.tc_rxq[j][i].base =
10638                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10639                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10640                         dcb_info->tc_queue.tc_txq[j][i].base =
10641                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10642                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10643                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10644                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10645                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10646                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10647                 }
10648                 j++;
10649         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10650         return 0;
10651 }
10652
10653 static int
10654 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10655 {
10656         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10657         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10658         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10659         uint16_t interval =
10660                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10661         uint16_t msix_intr;
10662
10663         msix_intr = intr_handle->intr_vec[queue_id];
10664         if (msix_intr == I40E_MISC_VEC_ID)
10665                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10666                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10667                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10668                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10669                                (interval <<
10670                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10671         else
10672                 I40E_WRITE_REG(hw,
10673                                I40E_PFINT_DYN_CTLN(msix_intr -
10674                                                    I40E_RX_VEC_START),
10675                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10676                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10677                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10678                                (interval <<
10679                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10680
10681         I40E_WRITE_FLUSH(hw);
10682         rte_intr_enable(&pci_dev->intr_handle);
10683
10684         return 0;
10685 }
10686
10687 static int
10688 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10689 {
10690         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10691         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10692         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10693         uint16_t msix_intr;
10694
10695         msix_intr = intr_handle->intr_vec[queue_id];
10696         if (msix_intr == I40E_MISC_VEC_ID)
10697                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10698         else
10699                 I40E_WRITE_REG(hw,
10700                                I40E_PFINT_DYN_CTLN(msix_intr -
10701                                                    I40E_RX_VEC_START),
10702                                0);
10703         I40E_WRITE_FLUSH(hw);
10704
10705         return 0;
10706 }
10707
10708 static int i40e_get_regs(struct rte_eth_dev *dev,
10709                          struct rte_dev_reg_info *regs)
10710 {
10711         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10712         uint32_t *ptr_data = regs->data;
10713         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10714         const struct i40e_reg_info *reg_info;
10715
10716         if (ptr_data == NULL) {
10717                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10718                 regs->width = sizeof(uint32_t);
10719                 return 0;
10720         }
10721
10722         /* The first few registers have to be read using AQ operations */
10723         reg_idx = 0;
10724         while (i40e_regs_adminq[reg_idx].name) {
10725                 reg_info = &i40e_regs_adminq[reg_idx++];
10726                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10727                         for (arr_idx2 = 0;
10728                                         arr_idx2 <= reg_info->count2;
10729                                         arr_idx2++) {
10730                                 reg_offset = arr_idx * reg_info->stride1 +
10731                                         arr_idx2 * reg_info->stride2;
10732                                 reg_offset += reg_info->base_addr;
10733                                 ptr_data[reg_offset >> 2] =
10734                                         i40e_read_rx_ctl(hw, reg_offset);
10735                         }
10736         }
10737
10738         /* The remaining registers can be read using primitives */
10739         reg_idx = 0;
10740         while (i40e_regs_others[reg_idx].name) {
10741                 reg_info = &i40e_regs_others[reg_idx++];
10742                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10743                         for (arr_idx2 = 0;
10744                                         arr_idx2 <= reg_info->count2;
10745                                         arr_idx2++) {
10746                                 reg_offset = arr_idx * reg_info->stride1 +
10747                                         arr_idx2 * reg_info->stride2;
10748                                 reg_offset += reg_info->base_addr;
10749                                 ptr_data[reg_offset >> 2] =
10750                                         I40E_READ_REG(hw, reg_offset);
10751                         }
10752         }
10753
10754         return 0;
10755 }
10756
10757 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10758 {
10759         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10760
10761         /* Convert word count to byte count */
10762         return hw->nvm.sr_size << 1;
10763 }
10764
10765 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10766                            struct rte_dev_eeprom_info *eeprom)
10767 {
10768         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10769         uint16_t *data = eeprom->data;
10770         uint16_t offset, length, cnt_words;
10771         int ret_code;
10772
10773         offset = eeprom->offset >> 1;
10774         length = eeprom->length >> 1;
10775         cnt_words = length;
10776
10777         if (offset > hw->nvm.sr_size ||
10778                 offset + length > hw->nvm.sr_size) {
10779                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10780                 return -EINVAL;
10781         }
10782
10783         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10784
10785         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10786         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10787                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10788                 return -EIO;
10789         }
10790
10791         return 0;
10792 }
10793
10794 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10795                                       struct ether_addr *mac_addr)
10796 {
10797         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10798
10799         if (!is_valid_assigned_ether_addr(mac_addr)) {
10800                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10801                 return;
10802         }
10803
10804         /* Flags: 0x3 updates port address */
10805         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10806 }
10807
10808 static int
10809 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10810 {
10811         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10812         struct rte_eth_dev_data *dev_data = pf->dev_data;
10813         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10814         int ret = 0;
10815
10816         /* check if mtu is within the allowed range */
10817         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10818                 return -EINVAL;
10819
10820         /* mtu setting is forbidden if port is start */
10821         if (dev_data->dev_started) {
10822                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10823                             dev_data->port_id);
10824                 return -EBUSY;
10825         }
10826
10827         if (frame_size > ETHER_MAX_LEN)
10828                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10829         else
10830                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10831
10832         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10833
10834         return ret;
10835 }
10836
10837 /* Restore ethertype filter */
10838 static void
10839 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10840 {
10841         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10842         struct i40e_ethertype_filter_list
10843                 *ethertype_list = &pf->ethertype.ethertype_list;
10844         struct i40e_ethertype_filter *f;
10845         struct i40e_control_filter_stats stats;
10846         uint16_t flags;
10847
10848         TAILQ_FOREACH(f, ethertype_list, rules) {
10849                 flags = 0;
10850                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10851                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10852                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10853                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10854                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10855
10856                 memset(&stats, 0, sizeof(stats));
10857                 i40e_aq_add_rem_control_packet_filter(hw,
10858                                             f->input.mac_addr.addr_bytes,
10859                                             f->input.ether_type,
10860                                             flags, pf->main_vsi->seid,
10861                                             f->queue, 1, &stats, NULL);
10862         }
10863         PMD_DRV_LOG(INFO, "Ethertype filter:"
10864                     " mac_etype_used = %u, etype_used = %u,"
10865                     " mac_etype_free = %u, etype_free = %u",
10866                     stats.mac_etype_used, stats.etype_used,
10867                     stats.mac_etype_free, stats.etype_free);
10868 }
10869
10870 /* Restore tunnel filter */
10871 static void
10872 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10873 {
10874         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10875         struct i40e_vsi *vsi;
10876         struct i40e_pf_vf *vf;
10877         struct i40e_tunnel_filter_list
10878                 *tunnel_list = &pf->tunnel.tunnel_list;
10879         struct i40e_tunnel_filter *f;
10880         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10881         bool big_buffer = 0;
10882
10883         TAILQ_FOREACH(f, tunnel_list, rules) {
10884                 if (!f->is_to_vf)
10885                         vsi = pf->main_vsi;
10886                 else {
10887                         vf = &pf->vfs[f->vf_id];
10888                         vsi = vf->vsi;
10889                 }
10890                 memset(&cld_filter, 0, sizeof(cld_filter));
10891                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10892                         (struct ether_addr *)&cld_filter.element.outer_mac);
10893                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10894                         (struct ether_addr *)&cld_filter.element.inner_mac);
10895                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10896                 cld_filter.element.flags = f->input.flags;
10897                 cld_filter.element.tenant_id = f->input.tenant_id;
10898                 cld_filter.element.queue_number = f->queue;
10899                 rte_memcpy(cld_filter.general_fields,
10900                            f->input.general_fields,
10901                            sizeof(f->input.general_fields));
10902
10903                 if (((f->input.flags &
10904                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
10905                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
10906                     ((f->input.flags &
10907                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
10908                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
10909                     ((f->input.flags &
10910                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
10911                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
10912                         big_buffer = 1;
10913
10914                 if (big_buffer)
10915                         i40e_aq_add_cloud_filters_big_buffer(hw,
10916                                              vsi->seid, &cld_filter, 1);
10917                 else
10918                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10919                                                   &cld_filter.element, 1);
10920         }
10921 }
10922
10923 static void
10924 i40e_filter_restore(struct i40e_pf *pf)
10925 {
10926         i40e_ethertype_filter_restore(pf);
10927         i40e_tunnel_filter_restore(pf);
10928         i40e_fdir_filter_restore(pf);
10929 }
10930
10931 static bool
10932 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10933 {
10934         if (strcmp(dev->device->driver->name, drv->driver.name))
10935                 return false;
10936
10937         return true;
10938 }
10939
10940 bool
10941 is_i40e_supported(struct rte_eth_dev *dev)
10942 {
10943         return is_device_supported(dev, &rte_i40e_pmd);
10944 }
10945
10946 struct i40e_customized_pctype*
10947 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
10948 {
10949         int i;
10950
10951         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
10952                 if (pf->customized_pctype[i].index == index)
10953                         return &pf->customized_pctype[i];
10954         }
10955         return NULL;
10956 }
10957
10958 static int
10959 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
10960                               uint32_t pkg_size, uint32_t proto_num,
10961                               struct rte_pmd_i40e_proto_info *proto)
10962 {
10963         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10964         uint32_t pctype_num;
10965         struct rte_pmd_i40e_ptype_info *pctype;
10966         uint32_t buff_size;
10967         struct i40e_customized_pctype *new_pctype = NULL;
10968         uint8_t proto_id;
10969         uint8_t pctype_value;
10970         char name[64];
10971         uint32_t i, j, n;
10972         int ret;
10973
10974         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
10975                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
10976                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
10977         if (ret) {
10978                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
10979                 return -1;
10980         }
10981         if (!pctype_num) {
10982                 PMD_DRV_LOG(INFO, "No new pctype added");
10983                 return -1;
10984         }
10985
10986         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
10987         pctype = rte_zmalloc("new_pctype", buff_size, 0);
10988         if (!pctype) {
10989                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
10990                 return -1;
10991         }
10992         /* get information about new pctype list */
10993         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
10994                                         (uint8_t *)pctype, buff_size,
10995                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
10996         if (ret) {
10997                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
10998                 rte_free(pctype);
10999                 return -1;
11000         }
11001
11002         /* Update customized pctype. */
11003         for (i = 0; i < pctype_num; i++) {
11004                 pctype_value = pctype[i].ptype_id;
11005                 memset(name, 0, sizeof(name));
11006                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11007                         proto_id = pctype[i].protocols[j];
11008                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11009                                 continue;
11010                         for (n = 0; n < proto_num; n++) {
11011                                 if (proto[n].proto_id != proto_id)
11012                                         continue;
11013                                 strcat(name, proto[n].name);
11014                                 strcat(name, "_");
11015                                 break;
11016                         }
11017                 }
11018                 name[strlen(name) - 1] = '\0';
11019                 if (!strcmp(name, "GTPC"))
11020                         new_pctype =
11021                                 i40e_find_customized_pctype(pf,
11022                                                       I40E_CUSTOMIZED_GTPC);
11023                 else if (!strcmp(name, "GTPU_IPV4"))
11024                         new_pctype =
11025                                 i40e_find_customized_pctype(pf,
11026                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11027                 else if (!strcmp(name, "GTPU_IPV6"))
11028                         new_pctype =
11029                                 i40e_find_customized_pctype(pf,
11030                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11031                 else if (!strcmp(name, "GTPU"))
11032                         new_pctype =
11033                                 i40e_find_customized_pctype(pf,
11034                                                       I40E_CUSTOMIZED_GTPU);
11035                 if (new_pctype) {
11036                         new_pctype->pctype = pctype_value;
11037                         new_pctype->valid = true;
11038                 }
11039         }
11040
11041         rte_free(pctype);
11042         return 0;
11043 }
11044
11045 static int
11046 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11047                                uint32_t pkg_size, uint32_t proto_num,
11048                                struct rte_pmd_i40e_proto_info *proto)
11049 {
11050         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11051         uint8_t port_id = dev->data->port_id;
11052         uint32_t ptype_num;
11053         struct rte_pmd_i40e_ptype_info *ptype;
11054         uint32_t buff_size;
11055         uint8_t proto_id;
11056         char name[16];
11057         uint32_t i, j, n;
11058         bool inner_ip;
11059         int ret;
11060
11061         /* get information about new ptype num */
11062         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11063                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11064                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11065         if (ret) {
11066                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11067                 return ret;
11068         }
11069         if (!ptype_num) {
11070                 PMD_DRV_LOG(INFO, "No new ptype added");
11071                 return -1;
11072         }
11073
11074         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11075         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11076         if (!ptype) {
11077                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11078                 return -1;
11079         }
11080
11081         /* get information about new ptype list */
11082         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11083                                         (uint8_t *)ptype, buff_size,
11084                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11085         if (ret) {
11086                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11087                 rte_free(ptype);
11088                 return ret;
11089         }
11090
11091         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11092         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11093         if (!ptype_mapping) {
11094                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11095                 rte_free(ptype);
11096                 return -1;
11097         }
11098
11099         /* Update ptype mapping table. */
11100         for (i = 0; i < ptype_num; i++) {
11101                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11102                 ptype_mapping[i].sw_ptype = 0;
11103                 inner_ip = false;
11104                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11105                         proto_id = ptype[i].protocols[j];
11106                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11107                                 continue;
11108                         for (n = 0; n < proto_num; n++) {
11109                                 if (proto[n].proto_id != proto_id)
11110                                         continue;
11111                                 memset(name, 0, sizeof(name));
11112                                 strcpy(name, proto[n].name);
11113                                 if (!strncmp(name, "IPV4", 4) && !inner_ip) {
11114                                         ptype_mapping[i].sw_ptype |=
11115                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11116                                         inner_ip = true;
11117                                 } else if (!strncmp(name, "IPV4", 4) &&
11118                                            inner_ip) {
11119                                         ptype_mapping[i].sw_ptype |=
11120                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11121                                 } else if (!strncmp(name, "IPV6", 4) &&
11122                                            !inner_ip) {
11123                                         ptype_mapping[i].sw_ptype |=
11124                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11125                                         inner_ip = true;
11126                                 } else if (!strncmp(name, "IPV6", 4) &&
11127                                            inner_ip) {
11128                                         ptype_mapping[i].sw_ptype |=
11129                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11130                                 } else if (!strncmp(name, "IPV4FRAG", 8)) {
11131                                         ptype_mapping[i].sw_ptype |=
11132                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11133                                         ptype_mapping[i].sw_ptype |=
11134                                                 RTE_PTYPE_INNER_L4_FRAG;
11135                                 } else if (!strncmp(name, "IPV6FRAG", 8)) {
11136                                         ptype_mapping[i].sw_ptype |=
11137                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11138                                         ptype_mapping[i].sw_ptype |=
11139                                                 RTE_PTYPE_INNER_L4_FRAG;
11140                                 } else if (!strncmp(name, "GTPC", 4))
11141                                         ptype_mapping[i].sw_ptype |=
11142                                                 RTE_PTYPE_TUNNEL_GTPC;
11143                                 else if (!strncmp(name, "GTPU", 4))
11144                                         ptype_mapping[i].sw_ptype |=
11145                                                 RTE_PTYPE_TUNNEL_GTPU;
11146                                 else if (!strncmp(name, "UDP", 3))
11147                                         ptype_mapping[i].sw_ptype |=
11148                                                 RTE_PTYPE_INNER_L4_UDP;
11149                                 else if (!strncmp(name, "TCP", 3))
11150                                         ptype_mapping[i].sw_ptype |=
11151                                                 RTE_PTYPE_INNER_L4_TCP;
11152                                 else if (!strncmp(name, "SCTP", 4))
11153                                         ptype_mapping[i].sw_ptype |=
11154                                                 RTE_PTYPE_INNER_L4_SCTP;
11155                                 else if (!strncmp(name, "ICMP", 4) ||
11156                                          !strncmp(name, "ICMPV6", 6))
11157                                         ptype_mapping[i].sw_ptype |=
11158                                                 RTE_PTYPE_INNER_L4_ICMP;
11159
11160                                 break;
11161                         }
11162                 }
11163         }
11164
11165         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11166                                                 ptype_num, 0);
11167         if (ret)
11168                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11169
11170         rte_free(ptype_mapping);
11171         rte_free(ptype);
11172         return ret;
11173 }
11174
11175 void
11176 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11177                               uint32_t pkg_size)
11178 {
11179         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11180         uint32_t proto_num;
11181         struct rte_pmd_i40e_proto_info *proto;
11182         uint32_t buff_size;
11183         uint32_t i;
11184         int ret;
11185
11186         /* get information about protocol number */
11187         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11188                                        (uint8_t *)&proto_num, sizeof(proto_num),
11189                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11190         if (ret) {
11191                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11192                 return;
11193         }
11194         if (!proto_num) {
11195                 PMD_DRV_LOG(INFO, "No new protocol added");
11196                 return;
11197         }
11198
11199         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11200         proto = rte_zmalloc("new_proto", buff_size, 0);
11201         if (!proto) {
11202                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11203                 return;
11204         }
11205
11206         /* get information about protocol list */
11207         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11208                                         (uint8_t *)proto, buff_size,
11209                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11210         if (ret) {
11211                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11212                 rte_free(proto);
11213                 return;
11214         }
11215
11216         /* Check if GTP is supported. */
11217         for (i = 0; i < proto_num; i++) {
11218                 if (!strncmp(proto[i].name, "GTP", 3)) {
11219                         pf->gtp_support = true;
11220                         break;
11221                 }
11222         }
11223
11224         /* Update customized pctype info */
11225         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11226                                             proto_num, proto);
11227         if (ret)
11228                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11229
11230         /* Update customized ptype info */
11231         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11232                                            proto_num, proto);
11233         if (ret)
11234                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11235
11236         rte_free(proto);
11237 }
11238
11239 /* Create a QinQ cloud filter
11240  *
11241  * The Fortville NIC has limited resources for tunnel filters,
11242  * so we can only reuse existing filters.
11243  *
11244  * In step 1 we define which Field Vector fields can be used for
11245  * filter types.
11246  * As we do not have the inner tag defined as a field,
11247  * we have to define it first, by reusing one of L1 entries.
11248  *
11249  * In step 2 we are replacing one of existing filter types with
11250  * a new one for QinQ.
11251  * As we reusing L1 and replacing L2, some of the default filter
11252  * types will disappear,which depends on L1 and L2 entries we reuse.
11253  *
11254  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11255  *
11256  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11257  *              later when we define the cloud filter.
11258  *      a.      Valid_flags.replace_cloud = 0
11259  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11260  *      c.      New_filter = 0x10
11261  *      d.      TR bit = 0xff (optional, not used here)
11262  *      e.      Buffer – 2 entries:
11263  *              i.      Byte 0 = 8 (outer vlan FV index).
11264  *                      Byte 1 = 0 (rsv)
11265  *                      Byte 2-3 = 0x0fff
11266  *              ii.     Byte 0 = 37 (inner vlan FV index).
11267  *                      Byte 1 =0 (rsv)
11268  *                      Byte 2-3 = 0x0fff
11269  *
11270  * Step 2:
11271  * 2.   Create cloud filter using two L1 filters entries: stag and
11272  *              new filter(outer vlan+ inner vlan)
11273  *      a.      Valid_flags.replace_cloud = 1
11274  *      b.      Old_filter = 1 (instead of outer IP)
11275  *      c.      New_filter = 0x10
11276  *      d.      Buffer – 2 entries:
11277  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11278  *                      Byte 1-3 = 0 (rsv)
11279  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11280  *                      Byte 9-11 = 0 (rsv)
11281  */
11282 static int
11283 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11284 {
11285         int ret = -ENOTSUP;
11286         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11287         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11288         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11289
11290         /* Init */
11291         memset(&filter_replace, 0,
11292                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11293         memset(&filter_replace_buf, 0,
11294                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11295
11296         /* create L1 filter */
11297         filter_replace.old_filter_type =
11298                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11299         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11300         filter_replace.tr_bit = 0;
11301
11302         /* Prepare the buffer, 2 entries */
11303         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11304         filter_replace_buf.data[0] |=
11305                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11306         /* Field Vector 12b mask */
11307         filter_replace_buf.data[2] = 0xff;
11308         filter_replace_buf.data[3] = 0x0f;
11309         filter_replace_buf.data[4] =
11310                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11311         filter_replace_buf.data[4] |=
11312                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11313         /* Field Vector 12b mask */
11314         filter_replace_buf.data[6] = 0xff;
11315         filter_replace_buf.data[7] = 0x0f;
11316         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11317                         &filter_replace_buf);
11318         if (ret != I40E_SUCCESS)
11319                 return ret;
11320
11321         /* Apply the second L2 cloud filter */
11322         memset(&filter_replace, 0,
11323                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11324         memset(&filter_replace_buf, 0,
11325                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11326
11327         /* create L2 filter, input for L2 filter will be L1 filter  */
11328         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11329         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11330         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11331
11332         /* Prepare the buffer, 2 entries */
11333         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11334         filter_replace_buf.data[0] |=
11335                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11336         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11337         filter_replace_buf.data[4] |=
11338                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11339         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11340                         &filter_replace_buf);
11341         return ret;
11342 }
11343
11344 RTE_INIT(i40e_init_log);
11345 static void
11346 i40e_init_log(void)
11347 {
11348         i40e_logtype_init = rte_log_register("pmd.i40e.init");
11349         if (i40e_logtype_init >= 0)
11350                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11351         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11352         if (i40e_logtype_driver >= 0)
11353                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
11354 }