drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 115
 116 #define I40E_FLOW_TYPES ( \
 117         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 122         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 127         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 128
 129 /* Additional timesync values. */
 130 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 131 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 132 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 133 #define I40E_PRTTSYN_TSYNENA     0x80000000
 134 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 135 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 136
 137 #define I40E_MAX_PERCENT            100
 138 #define I40E_DEFAULT_DCB_APP_NUM    1
 139 #define I40E_DEFAULT_DCB_APP_PRIO   3
 140
 141 #define I40E_INSET_NONE            0x00000000000000000ULL
 142
 143 /* bit0 ~ bit 7 */
 144 #define I40E_INSET_DMAC            0x0000000000000001ULL
 145 #define I40E_INSET_SMAC            0x0000000000000002ULL
 146 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 147 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 148 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 149
 150 /* bit 8 ~ bit 15 */
 151 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 152 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 153 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 154 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 155 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 156 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 157 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 158
 159 /* bit 16 ~ bit 31 */
 160 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 161 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 162 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 163 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 164 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 165 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 166 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 167 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 168
 169 /* bit 32 ~ bit 47, tunnel fields */
 170 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 171 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 172 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 173 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 174 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 175 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 176
 177 /* bit 48 ~ bit 55 */
 178 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 179
 180 /* bit 56 ~ bit 63, Flex Payload */
 181 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD \
 190         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 191         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 192         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 193         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 194
 195 /**
 196  * Below are values for writing un-exposed registers suggested
 197  * by silicon experts
 198  */
 199 /* Destination MAC address */
 200 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 201 /* Source MAC address */
 202 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 203 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 204 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 205 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 206 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 207 /* Single VLAN tag in the inner L2 header */
 208 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 209 /* Source IPv4 address */
 210 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 211 /* Destination IPv4 address */
 212 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 213 /* Source IPv4 address for X722 */
 214 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 215 /* Destination IPv4 address for X722 */
 216 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 217 /* IPv4 Protocol for X722 */
 218 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 219 /* IPv4 Time to Live for X722 */
 220 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 221 /* IPv4 Type of Service (TOS) */
 222 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 223 /* IPv4 Protocol */
 224 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 225 /* IPv4 Time to Live */
 226 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 227 /* Source IPv6 address */
 228 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 229 /* Destination IPv6 address */
 230 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 231 /* IPv6 Traffic Class (TC) */
 232 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 233 /* IPv6 Next Header */
 234 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 235 /* IPv6 Hop Limit */
 236 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 237 /* Source L4 port */
 238 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 239 /* Destination L4 port */
 240 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 241 /* SCTP verification tag */
 242 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 243 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 244 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 245 /* Source port of tunneling UDP */
 246 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 247 /* Destination port of tunneling UDP */
 248 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 249 /* UDP Tunneling ID, NVGRE/GRE key */
 250 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 251 /* Last ether type */
 252 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 253 /* Tunneling outer destination IPv4 address */
 254 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 255 /* Tunneling outer destination IPv6 address */
 256 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 257 /* 1st word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 259 /* 2nd word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 261 /* 3rd word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 263 /* 4th word of flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 265 /* 5th word of flex payload */
 266 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 267 /* 6th word of flex payload */
 268 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 269 /* 7th word of flex payload */
 270 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 271 /* 8th word of flex payload */
 272 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 273 /* all 8 words flex payload */
 274 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 275 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 276
 277 #define I40E_TRANSLATE_INSET 0
 278 #define I40E_TRANSLATE_REG   1
 279
 280 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 281 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 282 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 283 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 284 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 285 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 286
 287 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 288 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 290         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 291
 292 /* PCI offset for querying capability */
 293 #define PCI_DEV_CAP_REG            0xA4
 294 /* PCI offset for enabling/disabling Extended Tag */
 295 #define PCI_DEV_CTRL_REG           0xA8
 296 /* Bit mask of Extended Tag capability */
 297 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 298 /* Bit shift of Extended Tag enable/disable */
 299 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 300 /* Bit mask of Extended Tag enable/disable */
 301 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 302
 303 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 304 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 305 static int i40e_dev_configure(struct rte_eth_dev *dev);
 306 static int i40e_dev_start(struct rte_eth_dev *dev);
 307 static void i40e_dev_stop(struct rte_eth_dev *dev);
 308 static void i40e_dev_close(struct rte_eth_dev *dev);
 309 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 310 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 311 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 312 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 313 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 314 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 315 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 316                                struct rte_eth_stats *stats);
 317 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 318                                struct rte_eth_xstat *xstats, unsigned n);
 319 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 320                                      struct rte_eth_xstat_name *xstats_names,
 321                                      unsigned limit);
 322 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 323 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 324                                             uint16_t queue_id,
 325                                             uint8_t stat_idx,
 326                                             uint8_t is_rx);
 327 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 328                               struct rte_eth_dev_info *dev_info);
 329 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 330                                 uint16_t vlan_id,
 331                                 int on);
 332 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 333                               enum rte_vlan_type vlan_type,
 334                               uint16_t tpid);
 335 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 336 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 337                                       uint16_t queue,
 338                                       int on);
 339 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 340 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 341 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 342 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 343                               struct rte_eth_fc_conf *fc_conf);
 344 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 345                               struct rte_eth_fc_conf *fc_conf);
 346 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 347                                        struct rte_eth_pfc_conf *pfc_conf);
 348 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 349                           struct ether_addr *mac_addr,
 350                           uint32_t index,
 351                           uint32_t pool);
 352 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 353 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 354                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 355                                     uint16_t reta_size);
 356 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 357                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 358                                    uint16_t reta_size);
 359
 360 static int i40e_get_cap(struct i40e_hw *hw);
 361 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 362 static int i40e_pf_setup(struct i40e_pf *pf);
 363 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 364 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 365 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 366 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 367 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 368                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 369 static void i40e_stat_update_48(struct i40e_hw *hw,
 370                                uint32_t hireg,
 371                                uint32_t loreg,
 372                                bool offset_loaded,
 373                                uint64_t *offset,
 374                                uint64_t *stat);
 375 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 376 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 377                                        void *param);
 378 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 379                                 uint32_t base, uint32_t num);
 380 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 381 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 382                         uint32_t base);
 383 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 384                         uint16_t num);
 385 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 386 static int i40e_veb_release(struct i40e_veb *veb);
 387 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 388                                                 struct i40e_vsi *vsi);
 389 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 390 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 391 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 392                                              struct i40e_macvlan_filter *mv_f,
 393                                              int num,
 394                                              struct ether_addr *addr);
 395 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 396                                              struct i40e_macvlan_filter *mv_f,
 397                                              int num,
 398                                              uint16_t vlan);
 399 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 400 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 401                                     struct rte_eth_rss_conf *rss_conf);
 402 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 403                                       struct rte_eth_rss_conf *rss_conf);
 404 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 405                                         struct rte_eth_udp_tunnel *udp_tunnel);
 406 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 407                                         struct rte_eth_udp_tunnel *udp_tunnel);
 408 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 409 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 410                         struct rte_eth_ethertype_filter *filter,
 411                         bool add);
 412 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 413                                 enum rte_filter_op filter_op,
 414                                 void *arg);
 415 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 416                                 enum rte_filter_type filter_type,
 417                                 enum rte_filter_op filter_op,
 418                                 void *arg);
 419 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 420                                   struct rte_eth_dcb_info *dcb_info);
 421 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 422 static void i40e_configure_registers(struct i40e_hw *hw);
 423 static void i40e_hw_init(struct rte_eth_dev *dev);
 424 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 425 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 426                         struct rte_eth_mirror_conf *mirror_conf,
 427                         uint8_t sw_id, uint8_t on);
 428 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 429
 430 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 431 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 432 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 433                                            struct timespec *timestamp,
 434                                            uint32_t flags);
 435 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 436                                            struct timespec *timestamp);
 437 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 438
 439 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 440
 441 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 442                                    struct timespec *timestamp);
 443 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 444                                     const struct timespec *timestamp);
 445
 446 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 447                                          uint16_t queue_id);
 448 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 449                                           uint16_t queue_id);
 450
 451 static int i40e_get_regs(struct rte_eth_dev *dev,
 452                          struct rte_dev_reg_info *regs);
 453
 454 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 455
 456 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 457                            struct rte_dev_eeprom_info *eeprom);
 458
 459 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 460                                       struct ether_addr *mac_addr);
 461
 462 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 463
 464 static const struct rte_pci_id pci_id_i40e_map[] = {
 465         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 466         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 467         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 468         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 469         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 470         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 471         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 478         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 479         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 480         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 481         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 482         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 483         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 484         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 485         { .vendor_id = 0, /* sentinel */ },
 486 };
 487
 488 static const struct eth_dev_ops i40e_eth_dev_ops = {
 489         .dev_configure                = i40e_dev_configure,
 490         .dev_start                    = i40e_dev_start,
 491         .dev_stop                     = i40e_dev_stop,
 492         .dev_close                    = i40e_dev_close,
 493         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 494         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 495         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 496         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 497         .dev_set_link_up              = i40e_dev_set_link_up,
 498         .dev_set_link_down            = i40e_dev_set_link_down,
 499         .link_update                  = i40e_dev_link_update,
 500         .stats_get                    = i40e_dev_stats_get,
 501         .xstats_get                   = i40e_dev_xstats_get,
 502         .xstats_get_names             = i40e_dev_xstats_get_names,
 503         .stats_reset                  = i40e_dev_stats_reset,
 504         .xstats_reset                 = i40e_dev_stats_reset,
 505         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 506         .dev_infos_get                = i40e_dev_info_get,
 507         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 508         .vlan_filter_set              = i40e_vlan_filter_set,
 509         .vlan_tpid_set                = i40e_vlan_tpid_set,
 510         .vlan_offload_set             = i40e_vlan_offload_set,
 511         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 512         .vlan_pvid_set                = i40e_vlan_pvid_set,
 513         .rx_queue_start               = i40e_dev_rx_queue_start,
 514         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 515         .tx_queue_start               = i40e_dev_tx_queue_start,
 516         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 517         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 518         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 519         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 520         .rx_queue_release             = i40e_dev_rx_queue_release,
 521         .rx_queue_count               = i40e_dev_rx_queue_count,
 522         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 523         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 524         .tx_queue_release             = i40e_dev_tx_queue_release,
 525         .dev_led_on                   = i40e_dev_led_on,
 526         .dev_led_off                  = i40e_dev_led_off,
 527         .flow_ctrl_get                = i40e_flow_ctrl_get,
 528         .flow_ctrl_set                = i40e_flow_ctrl_set,
 529         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 530         .mac_addr_add                 = i40e_macaddr_add,
 531         .mac_addr_remove              = i40e_macaddr_remove,
 532         .reta_update                  = i40e_dev_rss_reta_update,
 533         .reta_query                   = i40e_dev_rss_reta_query,
 534         .rss_hash_update              = i40e_dev_rss_hash_update,
 535         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 536         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 537         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 538         .filter_ctrl                  = i40e_dev_filter_ctrl,
 539         .rxq_info_get                 = i40e_rxq_info_get,
 540         .txq_info_get                 = i40e_txq_info_get,
 541         .mirror_rule_set              = i40e_mirror_rule_set,
 542         .mirror_rule_reset            = i40e_mirror_rule_reset,
 543         .timesync_enable              = i40e_timesync_enable,
 544         .timesync_disable             = i40e_timesync_disable,
 545         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 546         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 547         .get_dcb_info                 = i40e_dev_get_dcb_info,
 548         .timesync_adjust_time         = i40e_timesync_adjust_time,
 549         .timesync_read_time           = i40e_timesync_read_time,
 550         .timesync_write_time          = i40e_timesync_write_time,
 551         .get_reg                      = i40e_get_regs,
 552         .get_eeprom_length            = i40e_get_eeprom_length,
 553         .get_eeprom                   = i40e_get_eeprom,
 554         .mac_addr_set                 = i40e_set_default_mac_addr,
 555         .mtu_set                      = i40e_dev_mtu_set,
 556 };
 557
 558 /* store statistics names and its offset in stats structure */
 559 struct rte_i40e_xstats_name_off {
 560         char name[RTE_ETH_XSTATS_NAME_SIZE];
 561         unsigned offset;
 562 };
 563
 564 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 565         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 566         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 567         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 568         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 569         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 570                 rx_unknown_protocol)},
 571         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 572         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 573         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 574         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 575 };
 576
 577 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 578                 sizeof(rte_i40e_stats_strings[0]))
 579
 580 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 581         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 582                 tx_dropped_link_down)},
 583         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 584         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 585                 illegal_bytes)},
 586         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 587         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 588                 mac_local_faults)},
 589         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 590                 mac_remote_faults)},
 591         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 592                 rx_length_errors)},
 593         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 594         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 595         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 596         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 597         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 598         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 599                 rx_size_127)},
 600         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 601                 rx_size_255)},
 602         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 603                 rx_size_511)},
 604         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 605                 rx_size_1023)},
 606         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 607                 rx_size_1522)},
 608         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 609                 rx_size_big)},
 610         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 611                 rx_undersize)},
 612         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 613                 rx_oversize)},
 614         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 615                 mac_short_packet_dropped)},
 616         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 617                 rx_fragments)},
 618         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 619         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 620         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 621                 tx_size_127)},
 622         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 623                 tx_size_255)},
 624         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 625                 tx_size_511)},
 626         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 627                 tx_size_1023)},
 628         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 629                 tx_size_1522)},
 630         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 631                 tx_size_big)},
 632         {"rx_flow_director_atr_match_packets",
 633                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 634         {"rx_flow_director_sb_match_packets",
 635                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 636         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 637                 tx_lpi_status)},
 638         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 639                 rx_lpi_status)},
 640         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 641                 tx_lpi_count)},
 642         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 643                 rx_lpi_count)},
 644 };
 645
 646 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 647                 sizeof(rte_i40e_hw_port_strings[0]))
 648
 649 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 650         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 651                 priority_xon_rx)},
 652         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 653                 priority_xoff_rx)},
 654 };
 655
 656 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 657                 sizeof(rte_i40e_rxq_prio_strings[0]))
 658
 659 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 660         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 661                 priority_xon_tx)},
 662         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 663                 priority_xoff_tx)},
 664         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 665                 priority_xon_2_xoff)},
 666 };
 667
 668 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 669                 sizeof(rte_i40e_txq_prio_strings[0]))
 670
 671 static struct eth_driver rte_i40e_pmd = {
 672         .pci_drv = {
 673                 .id_table = pci_id_i40e_map,
 674                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 675                 .probe = rte_eth_dev_pci_probe,
 676                 .remove = rte_eth_dev_pci_remove,
 677         },
 678         .eth_dev_init = eth_i40e_dev_init,
 679         .eth_dev_uninit = eth_i40e_dev_uninit,
 680         .dev_private_size = sizeof(struct i40e_adapter),
 681 };
 682
 683 static inline int
 684 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 685                                      struct rte_eth_link *link)
 686 {
 687         struct rte_eth_link *dst = link;
 688         struct rte_eth_link *src = &(dev->data->dev_link);
 689
 690         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 691                                         *(uint64_t *)src) == 0)
 692                 return -1;
 693
 694         return 0;
 695 }
 696
 697 static inline int
 698 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 699                                       struct rte_eth_link *link)
 700 {
 701         struct rte_eth_link *dst = &(dev->data->dev_link);
 702         struct rte_eth_link *src = link;
 703
 704         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 705                                         *(uint64_t *)src) == 0)
 706                 return -1;
 707
 708         return 0;
 709 }
 710
 711 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 712 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 713 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 714
 715 #ifndef I40E_GLQF_ORT
 716 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 717 #endif
 718 #ifndef I40E_GLQF_PIT
 719 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 720 #endif
 721
 722 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 723 {
 724         /*
 725          * Initialize registers for flexible payload, which should be set by NVM.
 726          * This should be removed from code once it is fixed in NVM.
 727          */
 728         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 729         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 730         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 731         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 732         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 733         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 734         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 735         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 736         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 737         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 738         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 739         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 740
 741         /* Initialize registers for parsing packet type of QinQ */
 742         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 743         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 744 }
 745
 746 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 747
 748 /*
 749  * Add a ethertype filter to drop all flow control frames transmitted
 750  * from VSIs.
 751 */
 752 static void
 753 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 754 {
 755         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 756         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 757                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 758                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 759         int ret;
 760
 761         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 762                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 763                                 pf->main_vsi_seid, 0,
 764                                 TRUE, NULL, NULL);
 765         if (ret)
 766                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 767                                   " frames from VSIs.");
 768 }
 769
 770 static int
 771 floating_veb_list_handler(__rte_unused const char *key,
 772                           const char *floating_veb_value,
 773                           void *opaque)
 774 {
 775         int idx = 0;
 776         unsigned int count = 0;
 777         char *end = NULL;
 778         int min, max;
 779         bool *vf_floating_veb = opaque;
 780
 781         while (isblank(*floating_veb_value))
 782                 floating_veb_value++;
 783
 784         /* Reset floating VEB configuration for VFs */
 785         for (idx = 0; idx < I40E_MAX_VF; idx++)
 786                 vf_floating_veb[idx] = false;
 787
 788         min = I40E_MAX_VF;
 789         do {
 790                 while (isblank(*floating_veb_value))
 791                         floating_veb_value++;
 792                 if (*floating_veb_value == '\0')
 793                         return -1;
 794                 errno = 0;
 795                 idx = strtoul(floating_veb_value, &end, 10);
 796                 if (errno || end == NULL)
 797                         return -1;
 798                 while (isblank(*end))
 799                         end++;
 800                 if (*end == '-') {
 801                         min = idx;
 802                 } else if ((*end == ';') || (*end == '\0')) {
 803                         max = idx;
 804                         if (min == I40E_MAX_VF)
 805                                 min = idx;
 806                         if (max >= I40E_MAX_VF)
 807                                 max = I40E_MAX_VF - 1;
 808                         for (idx = min; idx <= max; idx++) {
 809                                 vf_floating_veb[idx] = true;
 810                                 count++;
 811                         }
 812                         min = I40E_MAX_VF;
 813                 } else {
 814                         return -1;
 815                 }
 816                 floating_veb_value = end + 1;
 817         } while (*end != '\0');
 818
 819         if (count == 0)
 820                 return -1;
 821
 822         return 0;
 823 }
 824
 825 static void
 826 config_vf_floating_veb(struct rte_devargs *devargs,
 827                        uint16_t floating_veb,
 828                        bool *vf_floating_veb)
 829 {
 830         struct rte_kvargs *kvlist;
 831         int i;
 832         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 833
 834         if (!floating_veb)
 835                 return;
 836         /* All the VFs attach to the floating VEB by default
 837          * when the floating VEB is enabled.
 838          */
 839         for (i = 0; i < I40E_MAX_VF; i++)
 840                 vf_floating_veb[i] = true;
 841
 842         if (devargs == NULL)
 843                 return;
 844
 845         kvlist = rte_kvargs_parse(devargs->args, NULL);
 846         if (kvlist == NULL)
 847                 return;
 848
 849         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 850                 rte_kvargs_free(kvlist);
 851                 return;
 852         }
 853         /* When the floating_veb_list parameter exists, all the VFs
 854          * will attach to the legacy VEB firstly, then configure VFs
 855          * to the floating VEB according to the floating_veb_list.
 856          */
 857         if (rte_kvargs_process(kvlist, floating_veb_list,
 858                                floating_veb_list_handler,
 859                                vf_floating_veb) < 0) {
 860                 rte_kvargs_free(kvlist);
 861                 return;
 862         }
 863         rte_kvargs_free(kvlist);
 864 }
 865
 866 static int
 867 i40e_check_floating_handler(__rte_unused const char *key,
 868                             const char *value,
 869                             __rte_unused void *opaque)
 870 {
 871         if (strcmp(value, "1"))
 872                 return -1;
 873
 874         return 0;
 875 }
 876
 877 static int
 878 is_floating_veb_supported(struct rte_devargs *devargs)
 879 {
 880         struct rte_kvargs *kvlist;
 881         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 882
 883         if (devargs == NULL)
 884                 return 0;
 885
 886         kvlist = rte_kvargs_parse(devargs->args, NULL);
 887         if (kvlist == NULL)
 888                 return 0;
 889
 890         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 891                 rte_kvargs_free(kvlist);
 892                 return 0;
 893         }
 894         /* Floating VEB is enabled when there's key-value:
 895          * enable_floating_veb=1
 896          */
 897         if (rte_kvargs_process(kvlist, floating_veb_key,
 898                                i40e_check_floating_handler, NULL) < 0) {
 899                 rte_kvargs_free(kvlist);
 900                 return 0;
 901         }
 902         rte_kvargs_free(kvlist);
 903
 904         return 1;
 905 }
 906
 907 static void
 908 config_floating_veb(struct rte_eth_dev *dev)
 909 {
 910         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 911         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 912         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 913
 914         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 915
 916         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 917                 pf->floating_veb =
 918                         is_floating_veb_supported(pci_dev->device.devargs);
 919                 config_vf_floating_veb(pci_dev->device.devargs,
 920                                        pf->floating_veb,
 921                                        pf->floating_veb_list);
 922         } else {
 923                 pf->floating_veb = false;
 924         }
 925 }
 926
 927 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 928 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 929
 930 static int
 931 eth_i40e_dev_init(struct rte_eth_dev *dev)
 932 {
 933         struct rte_pci_device *pci_dev;
 934         struct rte_intr_handle *intr_handle;
 935         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 936         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 937         struct i40e_vsi *vsi;
 938         int ret;
 939         uint32_t len;
 940         uint8_t aq_fail = 0;
 941
 942         PMD_INIT_FUNC_TRACE();
 943
 944         dev->dev_ops = &i40e_eth_dev_ops;
 945         dev->rx_pkt_burst = i40e_recv_pkts;
 946         dev->tx_pkt_burst = i40e_xmit_pkts;
 947         dev->tx_pkt_prepare = i40e_prep_pkts;
 948
 949         /* for secondary processes, we don't initialise any further as primary
 950          * has already done this work. Only check we don't need a different
 951          * RX function */
 952         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 953                 i40e_set_rx_function(dev);
 954                 i40e_set_tx_function(dev);
 955                 return 0;
 956         }
 957         pci_dev = I40E_DEV_TO_PCI(dev);
 958         intr_handle = &pci_dev->intr_handle;
 959
 960         rte_eth_copy_pci_info(dev, pci_dev);
 961         dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
 962
 963         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 964         pf->adapter->eth_dev = dev;
 965         pf->dev_data = dev->data;
 966
 967         hw->back = I40E_PF_TO_ADAPTER(pf);
 968         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 969         if (!hw->hw_addr) {
 970                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 971                              "as address is NULL");
 972                 return -ENODEV;
 973         }
 974
 975         hw->vendor_id = pci_dev->id.vendor_id;
 976         hw->device_id = pci_dev->id.device_id;
 977         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 978         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 979         hw->bus.device = pci_dev->addr.devid;
 980         hw->bus.func = pci_dev->addr.function;
 981         hw->adapter_stopped = 0;
 982
 983         /* Make sure all is clean before doing PF reset */
 984         i40e_clear_hw(hw);
 985
 986         /* Initialize the hardware */
 987         i40e_hw_init(dev);
 988
 989         /* Reset here to make sure all is clean for each PF */
 990         ret = i40e_pf_reset(hw);
 991         if (ret) {
 992                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 993                 return ret;
 994         }
 995
 996         /* Initialize the shared code (base driver) */
 997         ret = i40e_init_shared_code(hw);
 998         if (ret) {
 999                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1000                 return ret;
1001         }
1002
1003         /*
1004          * To work around the NVM issue, initialize registers
1005          * for flexible payload and packet type of QinQ by
1006          * software. It should be removed once issues are fixed
1007          * in NVM.
1008          */
1009         i40e_GLQF_reg_init(hw);
1010
1011         /* Initialize the input set for filters (hash and fd) to default value */
1012         i40e_filter_input_set_init(pf);
1013
1014         /* Initialize the parameters for adminq */
1015         i40e_init_adminq_parameter(hw);
1016         ret = i40e_init_adminq(hw);
1017         if (ret != I40E_SUCCESS) {
1018                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1019                 return -EIO;
1020         }
1021         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1022                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1023                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1024                      ((hw->nvm.version >> 12) & 0xf),
1025                      ((hw->nvm.version >> 4) & 0xff),
1026                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1027
1028         /* Need the special FW version to support floating VEB */
1029         config_floating_veb(dev);
1030         /* Clear PXE mode */
1031         i40e_clear_pxe_mode(hw);
1032         ret = i40e_dev_sync_phy_type(hw);
1033         if (ret) {
1034                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1035                 goto err_sync_phy_type;
1036         }
1037         /*
1038          * On X710, performance number is far from the expectation on recent
1039          * firmware versions. The fix for this issue may not be integrated in
1040          * the following firmware version. So the workaround in software driver
1041          * is needed. It needs to modify the initial values of 3 internal only
1042          * registers. Note that the workaround can be removed when it is fixed
1043          * in firmware in the future.
1044          */
1045         i40e_configure_registers(hw);
1046
1047         /* Get hw capabilities */
1048         ret = i40e_get_cap(hw);
1049         if (ret != I40E_SUCCESS) {
1050                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1051                 goto err_get_capabilities;
1052         }
1053
1054         /* Initialize parameters for PF */
1055         ret = i40e_pf_parameter_init(dev);
1056         if (ret != 0) {
1057                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1058                 goto err_parameter_init;
1059         }
1060
1061         /* Initialize the queue management */
1062         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1063         if (ret < 0) {
1064                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1065                 goto err_qp_pool_init;
1066         }
1067         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1068                                 hw->func_caps.num_msix_vectors - 1);
1069         if (ret < 0) {
1070                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1071                 goto err_msix_pool_init;
1072         }
1073
1074         /* Initialize lan hmc */
1075         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1076                                 hw->func_caps.num_rx_qp, 0, 0);
1077         if (ret != I40E_SUCCESS) {
1078                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1079                 goto err_init_lan_hmc;
1080         }
1081
1082         /* Configure lan hmc */
1083         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1084         if (ret != I40E_SUCCESS) {
1085                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1086                 goto err_configure_lan_hmc;
1087         }
1088
1089         /* Get and check the mac address */
1090         i40e_get_mac_addr(hw, hw->mac.addr);
1091         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1092                 PMD_INIT_LOG(ERR, "mac address is not valid");
1093                 ret = -EIO;
1094                 goto err_get_mac_addr;
1095         }
1096         /* Copy the permanent MAC address */
1097         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1098                         (struct ether_addr *) hw->mac.perm_addr);
1099
1100         /* Disable flow control */
1101         hw->fc.requested_mode = I40E_FC_NONE;
1102         i40e_set_fc(hw, &aq_fail, TRUE);
1103
1104         /* Set the global registers with default ether type value */
1105         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1106         if (ret != I40E_SUCCESS) {
1107                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1108                              "VLAN ether type");
1109                 goto err_setup_pf_switch;
1110         }
1111
1112         /* PF setup, which includes VSI setup */
1113         ret = i40e_pf_setup(pf);
1114         if (ret) {
1115                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1116                 goto err_setup_pf_switch;
1117         }
1118
1119         /* reset all stats of the device, including pf and main vsi */
1120         i40e_dev_stats_reset(dev);
1121
1122         vsi = pf->main_vsi;
1123
1124         /* Disable double vlan by default */
1125         i40e_vsi_config_double_vlan(vsi, FALSE);
1126
1127         /* Disable S-TAG identification when floating_veb is disabled */
1128         if (!pf->floating_veb) {
1129                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1130                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1131                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1132                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1133                 }
1134         }
1135
1136         if (!vsi->max_macaddrs)
1137                 len = ETHER_ADDR_LEN;
1138         else
1139                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1140
1141         /* Should be after VSI initialized */
1142         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1143         if (!dev->data->mac_addrs) {
1144                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1145                                         "for storing mac address");
1146                 goto err_mac_alloc;
1147         }
1148         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1149                                         &dev->data->mac_addrs[0]);
1150
1151         /* initialize pf host driver to setup SRIOV resource if applicable */
1152         i40e_pf_host_init(dev);
1153
1154         /* register callback func to eal lib */
1155         rte_intr_callback_register(intr_handle,
1156                                    i40e_dev_interrupt_handler, dev);
1157
1158         /* configure and enable device interrupt */
1159         i40e_pf_config_irq0(hw, TRUE);
1160         i40e_pf_enable_irq0(hw);
1161
1162         /* enable uio intr after callback register */
1163         rte_intr_enable(intr_handle);
1164         /*
1165          * Add an ethertype filter to drop all flow control frames transmitted
1166          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1167          * frames to wire.
1168          */
1169         i40e_add_tx_flow_control_drop_filter(pf);
1170
1171         /* Set the max frame size to 0x2600 by default,
1172          * in case other drivers changed the default value.
1173          */
1174         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1175
1176         /* initialize mirror rule list */
1177         TAILQ_INIT(&pf->mirror_list);
1178
1179         /* Init dcb to sw mode by default */
1180         ret = i40e_dcb_init_configure(dev, TRUE);
1181         if (ret != I40E_SUCCESS) {
1182                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1183                 pf->flags &= ~I40E_FLAG_DCB;
1184         }
1185
1186         return 0;
1187
1188 err_mac_alloc:
1189         i40e_vsi_release(pf->main_vsi);
1190 err_setup_pf_switch:
1191 err_get_mac_addr:
1192 err_configure_lan_hmc:
1193         (void)i40e_shutdown_lan_hmc(hw);
1194 err_init_lan_hmc:
1195         i40e_res_pool_destroy(&pf->msix_pool);
1196 err_msix_pool_init:
1197         i40e_res_pool_destroy(&pf->qp_pool);
1198 err_qp_pool_init:
1199 err_parameter_init:
1200 err_get_capabilities:
1201 err_sync_phy_type:
1202         (void)i40e_shutdown_adminq(hw);
1203
1204         return ret;
1205 }
1206
1207 static int
1208 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1209 {
1210         struct rte_pci_device *pci_dev;
1211         struct rte_intr_handle *intr_handle;
1212         struct i40e_hw *hw;
1213         struct i40e_filter_control_settings settings;
1214         int ret;
1215         uint8_t aq_fail = 0;
1216
1217         PMD_INIT_FUNC_TRACE();
1218
1219         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1220                 return 0;
1221
1222         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1223         pci_dev = I40E_DEV_TO_PCI(dev);
1224         intr_handle = &pci_dev->intr_handle;
1225
1226         if (hw->adapter_stopped == 0)
1227                 i40e_dev_close(dev);
1228
1229         dev->dev_ops = NULL;
1230         dev->rx_pkt_burst = NULL;
1231         dev->tx_pkt_burst = NULL;
1232
1233         /* Clear PXE mode */
1234         i40e_clear_pxe_mode(hw);
1235
1236         /* Unconfigure filter control */
1237         memset(&settings, 0, sizeof(settings));
1238         ret = i40e_set_filter_control(hw, &settings);
1239         if (ret)
1240                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1241                                         ret);
1242
1243         /* Disable flow control */
1244         hw->fc.requested_mode = I40E_FC_NONE;
1245         i40e_set_fc(hw, &aq_fail, TRUE);
1246
1247         /* uninitialize pf host driver */
1248         i40e_pf_host_uninit(dev);
1249
1250         rte_free(dev->data->mac_addrs);
1251         dev->data->mac_addrs = NULL;
1252
1253         /* disable uio intr before callback unregister */
1254         rte_intr_disable(intr_handle);
1255
1256         /* register callback func to eal lib */
1257         rte_intr_callback_unregister(intr_handle,
1258                                      i40e_dev_interrupt_handler, dev);
1259
1260         return 0;
1261 }
1262
1263 static int
1264 i40e_dev_configure(struct rte_eth_dev *dev)
1265 {
1266         struct i40e_adapter *ad =
1267                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1268         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1269         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1270         int i, ret;
1271
1272         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1273          * bulk allocation or vector Rx preconditions we will reset it.
1274          */
1275         ad->rx_bulk_alloc_allowed = true;
1276         ad->rx_vec_allowed = true;
1277         ad->tx_simple_allowed = true;
1278         ad->tx_vec_allowed = true;
1279
1280         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1281                 ret = i40e_fdir_setup(pf);
1282                 if (ret != I40E_SUCCESS) {
1283                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1284                         return -ENOTSUP;
1285                 }
1286                 ret = i40e_fdir_configure(dev);
1287                 if (ret < 0) {
1288                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1289                         goto err;
1290                 }
1291         } else
1292                 i40e_fdir_teardown(pf);
1293
1294         ret = i40e_dev_init_vlan(dev);
1295         if (ret < 0)
1296                 goto err;
1297
1298         /* VMDQ setup.
1299          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1300          *  RSS setting have different requirements.
1301          *  General PMD driver call sequence are NIC init, configure,
1302          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1303          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1304          *  applicable. So, VMDQ setting has to be done before
1305          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1306          *  For RSS setting, it will try to calculate actual configured RX queue
1307          *  number, which will be available after rx_queue_setup(). dev_start()
1308          *  function is good to place RSS setup.
1309          */
1310         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1311                 ret = i40e_vmdq_setup(dev);
1312                 if (ret)
1313                         goto err;
1314         }
1315
1316         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1317                 ret = i40e_dcb_setup(dev);
1318                 if (ret) {
1319                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1320                         goto err_dcb;
1321                 }
1322         }
1323
1324         return 0;
1325
1326 err_dcb:
1327         /* need to release vmdq resource if exists */
1328         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1329                 i40e_vsi_release(pf->vmdq[i].vsi);
1330                 pf->vmdq[i].vsi = NULL;
1331         }
1332         rte_free(pf->vmdq);
1333         pf->vmdq = NULL;
1334 err:
1335         /* need to release fdir resource if exists */
1336         i40e_fdir_teardown(pf);
1337         return ret;
1338 }
1339
1340 void
1341 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1342 {
1343         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1344         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1345         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1346         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1347         uint16_t msix_vect = vsi->msix_intr;
1348         uint16_t i;
1349
1350         for (i = 0; i < vsi->nb_qps; i++) {
1351                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1352                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1353                 rte_wmb();
1354         }
1355
1356         if (vsi->type != I40E_VSI_SRIOV) {
1357                 if (!rte_intr_allow_others(intr_handle)) {
1358                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1359                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1360                         I40E_WRITE_REG(hw,
1361                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1362                                        0);
1363                 } else {
1364                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1365                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1366                         I40E_WRITE_REG(hw,
1367                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1368                                                        msix_vect - 1), 0);
1369                 }
1370         } else {
1371                 uint32_t reg;
1372                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1373                         vsi->user_param + (msix_vect - 1);
1374
1375                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1376                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1377         }
1378         I40E_WRITE_FLUSH(hw);
1379 }
1380
1381 static void
1382 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1383                        int base_queue, int nb_queue)
1384 {
1385         int i;
1386         uint32_t val;
1387         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1388
1389         /* Bind all RX queues to allocated MSIX interrupt */
1390         for (i = 0; i < nb_queue; i++) {
1391                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1392                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1393                         ((base_queue + i + 1) <<
1394                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1395                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1396                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1397
1398                 if (i == nb_queue - 1)
1399                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1400                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1401         }
1402
1403         /* Write first RX queue to Link list register as the head element */
1404         if (vsi->type != I40E_VSI_SRIOV) {
1405                 uint16_t interval =
1406                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1407
1408                 if (msix_vect == I40E_MISC_VEC_ID) {
1409                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1410                                        (base_queue <<
1411                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1412                                        (0x0 <<
1413                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1414                         I40E_WRITE_REG(hw,
1415                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1416                                        interval);
1417                 } else {
1418                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1419                                        (base_queue <<
1420                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1421                                        (0x0 <<
1422                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1423                         I40E_WRITE_REG(hw,
1424                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1425                                                        msix_vect - 1),
1426                                        interval);
1427                 }
1428         } else {
1429                 uint32_t reg;
1430
1431                 if (msix_vect == I40E_MISC_VEC_ID) {
1432                         I40E_WRITE_REG(hw,
1433                                        I40E_VPINT_LNKLST0(vsi->user_param),
1434                                        (base_queue <<
1435                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1436                                        (0x0 <<
1437                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1438                 } else {
1439                         /* num_msix_vectors_vf needs to minus irq0 */
1440                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1441                                 vsi->user_param + (msix_vect - 1);
1442
1443                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1444                                        (base_queue <<
1445                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1446                                        (0x0 <<
1447                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1448                 }
1449         }
1450
1451         I40E_WRITE_FLUSH(hw);
1452 }
1453
1454 void
1455 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1456 {
1457         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1458         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1459         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1460         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1461         uint16_t msix_vect = vsi->msix_intr;
1462         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1463         uint16_t queue_idx = 0;
1464         int record = 0;
1465         uint32_t val;
1466         int i;
1467
1468         for (i = 0; i < vsi->nb_qps; i++) {
1469                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1470                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1471         }
1472
1473         /* INTENA flag is not auto-cleared for interrupt */
1474         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1475         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1476                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1477                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1478         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1479
1480         /* VF bind interrupt */
1481         if (vsi->type == I40E_VSI_SRIOV) {
1482                 __vsi_queues_bind_intr(vsi, msix_vect,
1483                                        vsi->base_queue, vsi->nb_qps);
1484                 return;
1485         }
1486
1487         /* PF & VMDq bind interrupt */
1488         if (rte_intr_dp_is_en(intr_handle)) {
1489                 if (vsi->type == I40E_VSI_MAIN) {
1490                         queue_idx = 0;
1491                         record = 1;
1492                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1493                         struct i40e_vsi *main_vsi =
1494                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1495                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1496                         record = 1;
1497                 }
1498         }
1499
1500         for (i = 0; i < vsi->nb_used_qps; i++) {
1501                 if (nb_msix <= 1) {
1502                         if (!rte_intr_allow_others(intr_handle))
1503                                 /* allow to share MISC_VEC_ID */
1504                                 msix_vect = I40E_MISC_VEC_ID;
1505
1506                         /* no enough msix_vect, map all to one */
1507                         __vsi_queues_bind_intr(vsi, msix_vect,
1508                                                vsi->base_queue + i,
1509                                                vsi->nb_used_qps - i);
1510                         for (; !!record && i < vsi->nb_used_qps; i++)
1511                                 intr_handle->intr_vec[queue_idx + i] =
1512                                         msix_vect;
1513                         break;
1514                 }
1515                 /* 1:1 queue/msix_vect mapping */
1516                 __vsi_queues_bind_intr(vsi, msix_vect,
1517                                        vsi->base_queue + i, 1);
1518                 if (!!record)
1519                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1520
1521                 msix_vect++;
1522                 nb_msix--;
1523         }
1524 }
1525
1526 static void
1527 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1528 {
1529         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1530         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1531         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1532         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1533         uint16_t interval = i40e_calc_itr_interval(\
1534                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1535         uint16_t msix_intr, i;
1536
1537         if (rte_intr_allow_others(intr_handle))
1538                 for (i = 0; i < vsi->nb_msix; i++) {
1539                         msix_intr = vsi->msix_intr + i;
1540                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1541                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1542                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1543                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1544                                 (interval <<
1545                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1546                 }
1547         else
1548                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1549                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1550                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1551                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1552                                (interval <<
1553                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1554
1555         I40E_WRITE_FLUSH(hw);
1556 }
1557
1558 static void
1559 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1560 {
1561         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1562         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1563         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1564         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1565         uint16_t msix_intr, i;
1566
1567         if (rte_intr_allow_others(intr_handle))
1568                 for (i = 0; i < vsi->nb_msix; i++) {
1569                         msix_intr = vsi->msix_intr + i;
1570                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1571                                        0);
1572                 }
1573         else
1574                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1575
1576         I40E_WRITE_FLUSH(hw);
1577 }
1578
1579 static inline uint8_t
1580 i40e_parse_link_speeds(uint16_t link_speeds)
1581 {
1582         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1583
1584         if (link_speeds & ETH_LINK_SPEED_40G)
1585                 link_speed |= I40E_LINK_SPEED_40GB;
1586         if (link_speeds & ETH_LINK_SPEED_25G)
1587                 link_speed |= I40E_LINK_SPEED_25GB;
1588         if (link_speeds & ETH_LINK_SPEED_20G)
1589                 link_speed |= I40E_LINK_SPEED_20GB;
1590         if (link_speeds & ETH_LINK_SPEED_10G)
1591                 link_speed |= I40E_LINK_SPEED_10GB;
1592         if (link_speeds & ETH_LINK_SPEED_1G)
1593                 link_speed |= I40E_LINK_SPEED_1GB;
1594         if (link_speeds & ETH_LINK_SPEED_100M)
1595                 link_speed |= I40E_LINK_SPEED_100MB;
1596
1597         return link_speed;
1598 }
1599
1600 static int
1601 i40e_phy_conf_link(struct i40e_hw *hw,
1602                    uint8_t abilities,
1603                    uint8_t force_speed)
1604 {
1605         enum i40e_status_code status;
1606         struct i40e_aq_get_phy_abilities_resp phy_ab;
1607         struct i40e_aq_set_phy_config phy_conf;
1608         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1609                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1610                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1611                         I40E_AQ_PHY_FLAG_LOW_POWER;
1612         const uint8_t advt = I40E_LINK_SPEED_40GB |
1613                         I40E_LINK_SPEED_25GB |
1614                         I40E_LINK_SPEED_10GB |
1615                         I40E_LINK_SPEED_1GB |
1616                         I40E_LINK_SPEED_100MB;
1617         int ret = -ENOTSUP;
1618
1619
1620         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1621                                               NULL);
1622         if (status)
1623                 return ret;
1624
1625         memset(&phy_conf, 0, sizeof(phy_conf));
1626
1627         /* bits 0-2 use the values from get_phy_abilities_resp */
1628         abilities &= ~mask;
1629         abilities |= phy_ab.abilities & mask;
1630
1631         /* update ablities and speed */
1632         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1633                 phy_conf.link_speed = advt;
1634         else
1635                 phy_conf.link_speed = force_speed;
1636
1637         phy_conf.abilities = abilities;
1638
1639         /* use get_phy_abilities_resp value for the rest */
1640         phy_conf.phy_type = phy_ab.phy_type;
1641         phy_conf.eee_capability = phy_ab.eee_capability;
1642         phy_conf.eeer = phy_ab.eeer_val;
1643         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1644
1645         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1646                     phy_ab.abilities, phy_ab.link_speed);
1647         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1648                     phy_conf.abilities, phy_conf.link_speed);
1649
1650         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1651         if (status)
1652                 return ret;
1653
1654         return I40E_SUCCESS;
1655 }
1656
1657 static int
1658 i40e_apply_link_speed(struct rte_eth_dev *dev)
1659 {
1660         uint8_t speed;
1661         uint8_t abilities = 0;
1662         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663         struct rte_eth_conf *conf = &dev->data->dev_conf;
1664
1665         speed = i40e_parse_link_speeds(conf->link_speeds);
1666         if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
1667                 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1668         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1669                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1670         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1671
1672         /* Skip changing speed on 40G interfaces, FW does not support */
1673         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1674                 speed =  I40E_LINK_SPEED_UNKNOWN;
1675                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1676         }
1677
1678         return i40e_phy_conf_link(hw, abilities, speed);
1679 }
1680
1681 static int
1682 i40e_dev_start(struct rte_eth_dev *dev)
1683 {
1684         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1685         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1686         struct i40e_vsi *main_vsi = pf->main_vsi;
1687         int ret, i;
1688         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1689         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1690         uint32_t intr_vector = 0;
1691
1692         hw->adapter_stopped = 0;
1693
1694         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1695                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1696                              dev->data->port_id);
1697                 return -EINVAL;
1698         }
1699
1700         rte_intr_disable(intr_handle);
1701
1702         if ((rte_intr_cap_multiple(intr_handle) ||
1703              !RTE_ETH_DEV_SRIOV(dev).active) &&
1704             dev->data->dev_conf.intr_conf.rxq != 0) {
1705                 intr_vector = dev->data->nb_rx_queues;
1706                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1707                         return -1;
1708         }
1709
1710         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1711                 intr_handle->intr_vec =
1712                         rte_zmalloc("intr_vec",
1713                                     dev->data->nb_rx_queues * sizeof(int),
1714                                     0);
1715                 if (!intr_handle->intr_vec) {
1716                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1717                                      " intr_vec\n", dev->data->nb_rx_queues);
1718                         return -ENOMEM;
1719                 }
1720         }
1721
1722         /* Initialize VSI */
1723         ret = i40e_dev_rxtx_init(pf);
1724         if (ret != I40E_SUCCESS) {
1725                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1726                 goto err_up;
1727         }
1728
1729         /* Map queues with MSIX interrupt */
1730         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1731                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1732         i40e_vsi_queues_bind_intr(main_vsi);
1733         i40e_vsi_enable_queues_intr(main_vsi);
1734
1735         /* Map VMDQ VSI queues with MSIX interrupt */
1736         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1737                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1738                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1739                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1740         }
1741
1742         /* enable FDIR MSIX interrupt */
1743         if (pf->fdir.fdir_vsi) {
1744                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1745                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1746         }
1747
1748         /* Enable all queues which have been configured */
1749         ret = i40e_dev_switch_queues(pf, TRUE);
1750         if (ret != I40E_SUCCESS) {
1751                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1752                 goto err_up;
1753         }
1754
1755         /* Enable receiving broadcast packets */
1756         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1757         if (ret != I40E_SUCCESS)
1758                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1759
1760         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1761                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1762                                                 true, NULL);
1763                 if (ret != I40E_SUCCESS)
1764                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1765         }
1766
1767         /* Apply link configure */
1768         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1769                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1770                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1771                                 ETH_LINK_SPEED_40G)) {
1772                 PMD_DRV_LOG(ERR, "Invalid link setting");
1773                 goto err_up;
1774         }
1775         ret = i40e_apply_link_speed(dev);
1776         if (I40E_SUCCESS != ret) {
1777                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1778                 goto err_up;
1779         }
1780
1781         if (!rte_intr_allow_others(intr_handle)) {
1782                 rte_intr_callback_unregister(intr_handle,
1783                                              i40e_dev_interrupt_handler,
1784                                              (void *)dev);
1785                 /* configure and enable device interrupt */
1786                 i40e_pf_config_irq0(hw, FALSE);
1787                 i40e_pf_enable_irq0(hw);
1788
1789                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1790                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1791                                      " no intr multiplex\n");
1792         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1793                 ret = i40e_aq_set_phy_int_mask(hw,
1794                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1795                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1796                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1797                 if (ret != I40E_SUCCESS)
1798                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1799
1800                 /* Call get_link_info aq commond to enable LSE */
1801                 i40e_dev_link_update(dev, 0);
1802         }
1803
1804         /* enable uio intr after callback register */
1805         rte_intr_enable(intr_handle);
1806
1807         return I40E_SUCCESS;
1808
1809 err_up:
1810         i40e_dev_switch_queues(pf, FALSE);
1811         i40e_dev_clear_queues(dev);
1812
1813         return ret;
1814 }
1815
1816 static void
1817 i40e_dev_stop(struct rte_eth_dev *dev)
1818 {
1819         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1820         struct i40e_vsi *main_vsi = pf->main_vsi;
1821         struct i40e_mirror_rule *p_mirror;
1822         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1823         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1824         int i;
1825
1826         /* Disable all queues */
1827         i40e_dev_switch_queues(pf, FALSE);
1828
1829         /* un-map queues with interrupt registers */
1830         i40e_vsi_disable_queues_intr(main_vsi);
1831         i40e_vsi_queues_unbind_intr(main_vsi);
1832
1833         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1834                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1835                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1836         }
1837
1838         if (pf->fdir.fdir_vsi) {
1839                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1840                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1841         }
1842         /* Clear all queues and release memory */
1843         i40e_dev_clear_queues(dev);
1844
1845         /* Set link down */
1846         i40e_dev_set_link_down(dev);
1847
1848         /* Remove all mirror rules */
1849         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1850                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1851                 rte_free(p_mirror);
1852         }
1853         pf->nb_mirror_rule = 0;
1854
1855         if (!rte_intr_allow_others(intr_handle))
1856                 /* resume to the default handler */
1857                 rte_intr_callback_register(intr_handle,
1858                                            i40e_dev_interrupt_handler,
1859                                            (void *)dev);
1860
1861         /* Clean datapath event and queue/vec mapping */
1862         rte_intr_efd_disable(intr_handle);
1863         if (intr_handle->intr_vec) {
1864                 rte_free(intr_handle->intr_vec);
1865                 intr_handle->intr_vec = NULL;
1866         }
1867 }
1868
1869 static void
1870 i40e_dev_close(struct rte_eth_dev *dev)
1871 {
1872         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1873         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1874         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1875         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1876         uint32_t reg;
1877         int i;
1878
1879         PMD_INIT_FUNC_TRACE();
1880
1881         i40e_dev_stop(dev);
1882         hw->adapter_stopped = 1;
1883         i40e_dev_free_queues(dev);
1884
1885         /* Disable interrupt */
1886         i40e_pf_disable_irq0(hw);
1887         rte_intr_disable(intr_handle);
1888
1889         /* shutdown and destroy the HMC */
1890         i40e_shutdown_lan_hmc(hw);
1891
1892         /* release all the existing VSIs and VEBs */
1893         i40e_fdir_teardown(pf);
1894         i40e_vsi_release(pf->main_vsi);
1895
1896         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1897                 i40e_vsi_release(pf->vmdq[i].vsi);
1898                 pf->vmdq[i].vsi = NULL;
1899         }
1900
1901         rte_free(pf->vmdq);
1902         pf->vmdq = NULL;
1903
1904         /* shutdown the adminq */
1905         i40e_aq_queue_shutdown(hw, true);
1906         i40e_shutdown_adminq(hw);
1907
1908         i40e_res_pool_destroy(&pf->qp_pool);
1909         i40e_res_pool_destroy(&pf->msix_pool);
1910
1911         /* force a PF reset to clean anything leftover */
1912         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1913         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1914                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1915         I40E_WRITE_FLUSH(hw);
1916 }
1917
1918 static void
1919 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1920 {
1921         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1922         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1923         struct i40e_vsi *vsi = pf->main_vsi;
1924         int status;
1925
1926         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1927                                                      true, NULL, true);
1928         if (status != I40E_SUCCESS)
1929                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1930
1931         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1932                                                         TRUE, NULL);
1933         if (status != I40E_SUCCESS)
1934                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1935
1936 }
1937
1938 static void
1939 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1940 {
1941         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1942         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1943         struct i40e_vsi *vsi = pf->main_vsi;
1944         int status;
1945
1946         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1947                                                      false, NULL, true);
1948         if (status != I40E_SUCCESS)
1949                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1950
1951         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1952                                                         false, NULL);
1953         if (status != I40E_SUCCESS)
1954                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1955 }
1956
1957 static void
1958 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1959 {
1960         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1961         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1962         struct i40e_vsi *vsi = pf->main_vsi;
1963         int ret;
1964
1965         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1966         if (ret != I40E_SUCCESS)
1967                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1968 }
1969
1970 static void
1971 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1972 {
1973         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1974         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1975         struct i40e_vsi *vsi = pf->main_vsi;
1976         int ret;
1977
1978         if (dev->data->promiscuous == 1)
1979                 return; /* must remain in all_multicast mode */
1980
1981         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1982                                 vsi->seid, FALSE, NULL);
1983         if (ret != I40E_SUCCESS)
1984                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1985 }
1986
1987 /*
1988  * Set device link up.
1989  */
1990 static int
1991 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1992 {
1993         /* re-apply link speed setting */
1994         return i40e_apply_link_speed(dev);
1995 }
1996
1997 /*
1998  * Set device link down.
1999  */
2000 static int
2001 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2002 {
2003         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2004         uint8_t abilities = 0;
2005         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2006
2007         if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2008                 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2009         return i40e_phy_conf_link(hw, abilities, speed);
2010 }
2011
2012 int
2013 i40e_dev_link_update(struct rte_eth_dev *dev,
2014                      int wait_to_complete)
2015 {
2016 #define CHECK_INTERVAL 100  /* 100ms */
2017 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2018         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2019         struct i40e_link_status link_status;
2020         struct rte_eth_link link, old;
2021         int status;
2022         unsigned rep_cnt = MAX_REPEAT_TIME;
2023         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2024
2025         memset(&link, 0, sizeof(link));
2026         memset(&old, 0, sizeof(old));
2027         memset(&link_status, 0, sizeof(link_status));
2028         rte_i40e_dev_atomic_read_link_status(dev, &old);
2029
2030         do {
2031                 /* Get link status information from hardware */
2032                 status = i40e_aq_get_link_info(hw, enable_lse,
2033                                                 &link_status, NULL);
2034                 if (status != I40E_SUCCESS) {
2035                         link.link_speed = ETH_SPEED_NUM_100M;
2036                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2037                         PMD_DRV_LOG(ERR, "Failed to get link info");
2038                         goto out;
2039                 }
2040
2041                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2042                 if (!wait_to_complete)
2043                         break;
2044
2045                 rte_delay_ms(CHECK_INTERVAL);
2046         } while (!link.link_status && rep_cnt--);
2047
2048         if (!link.link_status)
2049                 goto out;
2050
2051         /* i40e uses full duplex only */
2052         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2053
2054         /* Parse the link status */
2055         switch (link_status.link_speed) {
2056         case I40E_LINK_SPEED_100MB:
2057                 link.link_speed = ETH_SPEED_NUM_100M;
2058                 break;
2059         case I40E_LINK_SPEED_1GB:
2060                 link.link_speed = ETH_SPEED_NUM_1G;
2061                 break;
2062         case I40E_LINK_SPEED_10GB:
2063                 link.link_speed = ETH_SPEED_NUM_10G;
2064                 break;
2065         case I40E_LINK_SPEED_20GB:
2066                 link.link_speed = ETH_SPEED_NUM_20G;
2067                 break;
2068         case I40E_LINK_SPEED_25GB:
2069                 link.link_speed = ETH_SPEED_NUM_25G;
2070                 break;
2071         case I40E_LINK_SPEED_40GB:
2072                 link.link_speed = ETH_SPEED_NUM_40G;
2073                 break;
2074         default:
2075                 link.link_speed = ETH_SPEED_NUM_100M;
2076                 break;
2077         }
2078
2079         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2080                         ETH_LINK_SPEED_FIXED);
2081
2082 out:
2083         rte_i40e_dev_atomic_write_link_status(dev, &link);
2084         if (link.link_status == old.link_status)
2085                 return -1;
2086
2087         return 0;
2088 }
2089
2090 /* Get all the statistics of a VSI */
2091 void
2092 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2093 {
2094         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2095         struct i40e_eth_stats *nes = &vsi->eth_stats;
2096         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2097         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2098
2099         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2100                             vsi->offset_loaded, &oes->rx_bytes,
2101                             &nes->rx_bytes);
2102         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2103                             vsi->offset_loaded, &oes->rx_unicast,
2104                             &nes->rx_unicast);
2105         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2106                             vsi->offset_loaded, &oes->rx_multicast,
2107                             &nes->rx_multicast);
2108         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2109                             vsi->offset_loaded, &oes->rx_broadcast,
2110                             &nes->rx_broadcast);
2111         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2112                             &oes->rx_discards, &nes->rx_discards);
2113         /* GLV_REPC not supported */
2114         /* GLV_RMPC not supported */
2115         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2116                             &oes->rx_unknown_protocol,
2117                             &nes->rx_unknown_protocol);
2118         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2119                             vsi->offset_loaded, &oes->tx_bytes,
2120                             &nes->tx_bytes);
2121         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2122                             vsi->offset_loaded, &oes->tx_unicast,
2123                             &nes->tx_unicast);
2124         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2125                             vsi->offset_loaded, &oes->tx_multicast,
2126                             &nes->tx_multicast);
2127         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2128                             vsi->offset_loaded,  &oes->tx_broadcast,
2129                             &nes->tx_broadcast);
2130         /* GLV_TDPC not supported */
2131         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2132                             &oes->tx_errors, &nes->tx_errors);
2133         vsi->offset_loaded = true;
2134
2135         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2136                     vsi->vsi_id);
2137         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2138         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2139         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2140         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2141         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2142         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2143                     nes->rx_unknown_protocol);
2144         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2145         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2146         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2147         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2148         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2149         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2150         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2151                     vsi->vsi_id);
2152 }
2153
2154 static void
2155 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2156 {
2157         unsigned int i;
2158         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2159         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2160
2161         /* Get statistics of struct i40e_eth_stats */
2162         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2163                             I40E_GLPRT_GORCL(hw->port),
2164                             pf->offset_loaded, &os->eth.rx_bytes,
2165                             &ns->eth.rx_bytes);
2166         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2167                             I40E_GLPRT_UPRCL(hw->port),
2168                             pf->offset_loaded, &os->eth.rx_unicast,
2169                             &ns->eth.rx_unicast);
2170         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2171                             I40E_GLPRT_MPRCL(hw->port),
2172                             pf->offset_loaded, &os->eth.rx_multicast,
2173                             &ns->eth.rx_multicast);
2174         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2175                             I40E_GLPRT_BPRCL(hw->port),
2176                             pf->offset_loaded, &os->eth.rx_broadcast,
2177                             &ns->eth.rx_broadcast);
2178         /* Workaround: CRC size should not be included in byte statistics,
2179          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2180          */
2181         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2182                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2183
2184         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2185                             pf->offset_loaded, &os->eth.rx_discards,
2186                             &ns->eth.rx_discards);
2187         /* GLPRT_REPC not supported */
2188         /* GLPRT_RMPC not supported */
2189         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2190                             pf->offset_loaded,
2191                             &os->eth.rx_unknown_protocol,
2192                             &ns->eth.rx_unknown_protocol);
2193         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2194                             I40E_GLPRT_GOTCL(hw->port),
2195                             pf->offset_loaded, &os->eth.tx_bytes,
2196                             &ns->eth.tx_bytes);
2197         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2198                             I40E_GLPRT_UPTCL(hw->port),
2199                             pf->offset_loaded, &os->eth.tx_unicast,
2200                             &ns->eth.tx_unicast);
2201         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2202                             I40E_GLPRT_MPTCL(hw->port),
2203                             pf->offset_loaded, &os->eth.tx_multicast,
2204                             &ns->eth.tx_multicast);
2205         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2206                             I40E_GLPRT_BPTCL(hw->port),
2207                             pf->offset_loaded, &os->eth.tx_broadcast,
2208                             &ns->eth.tx_broadcast);
2209         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2210                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2211         /* GLPRT_TEPC not supported */
2212
2213         /* additional port specific stats */
2214         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2215                             pf->offset_loaded, &os->tx_dropped_link_down,
2216                             &ns->tx_dropped_link_down);
2217         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2218                             pf->offset_loaded, &os->crc_errors,
2219                             &ns->crc_errors);
2220         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2221                             pf->offset_loaded, &os->illegal_bytes,
2222                             &ns->illegal_bytes);
2223         /* GLPRT_ERRBC not supported */
2224         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2225                             pf->offset_loaded, &os->mac_local_faults,
2226                             &ns->mac_local_faults);
2227         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2228                             pf->offset_loaded, &os->mac_remote_faults,
2229                             &ns->mac_remote_faults);
2230         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2231                             pf->offset_loaded, &os->rx_length_errors,
2232                             &ns->rx_length_errors);
2233         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2234                             pf->offset_loaded, &os->link_xon_rx,
2235                             &ns->link_xon_rx);
2236         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2237                             pf->offset_loaded, &os->link_xoff_rx,
2238                             &ns->link_xoff_rx);
2239         for (i = 0; i < 8; i++) {
2240                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2241                                     pf->offset_loaded,
2242                                     &os->priority_xon_rx[i],
2243                                     &ns->priority_xon_rx[i]);
2244                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2245                                     pf->offset_loaded,
2246                                     &os->priority_xoff_rx[i],
2247                                     &ns->priority_xoff_rx[i]);
2248         }
2249         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2250                             pf->offset_loaded, &os->link_xon_tx,
2251                             &ns->link_xon_tx);
2252         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2253                             pf->offset_loaded, &os->link_xoff_tx,
2254                             &ns->link_xoff_tx);
2255         for (i = 0; i < 8; i++) {
2256                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2257                                     pf->offset_loaded,
2258                                     &os->priority_xon_tx[i],
2259                                     &ns->priority_xon_tx[i]);
2260                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2261                                     pf->offset_loaded,
2262                                     &os->priority_xoff_tx[i],
2263                                     &ns->priority_xoff_tx[i]);
2264                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2265                                     pf->offset_loaded,
2266                                     &os->priority_xon_2_xoff[i],
2267                                     &ns->priority_xon_2_xoff[i]);
2268         }
2269         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2270                             I40E_GLPRT_PRC64L(hw->port),
2271                             pf->offset_loaded, &os->rx_size_64,
2272                             &ns->rx_size_64);
2273         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2274                             I40E_GLPRT_PRC127L(hw->port),
2275                             pf->offset_loaded, &os->rx_size_127,
2276                             &ns->rx_size_127);
2277         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2278                             I40E_GLPRT_PRC255L(hw->port),
2279                             pf->offset_loaded, &os->rx_size_255,
2280                             &ns->rx_size_255);
2281         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2282                             I40E_GLPRT_PRC511L(hw->port),
2283                             pf->offset_loaded, &os->rx_size_511,
2284                             &ns->rx_size_511);
2285         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2286                             I40E_GLPRT_PRC1023L(hw->port),
2287                             pf->offset_loaded, &os->rx_size_1023,
2288                             &ns->rx_size_1023);
2289         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2290                             I40E_GLPRT_PRC1522L(hw->port),
2291                             pf->offset_loaded, &os->rx_size_1522,
2292                             &ns->rx_size_1522);
2293         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2294                             I40E_GLPRT_PRC9522L(hw->port),
2295                             pf->offset_loaded, &os->rx_size_big,
2296                             &ns->rx_size_big);
2297         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2298                             pf->offset_loaded, &os->rx_undersize,
2299                             &ns->rx_undersize);
2300         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2301                             pf->offset_loaded, &os->rx_fragments,
2302                             &ns->rx_fragments);
2303         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2304                             pf->offset_loaded, &os->rx_oversize,
2305                             &ns->rx_oversize);
2306         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2307                             pf->offset_loaded, &os->rx_jabber,
2308                             &ns->rx_jabber);
2309         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2310                             I40E_GLPRT_PTC64L(hw->port),
2311                             pf->offset_loaded, &os->tx_size_64,
2312                             &ns->tx_size_64);
2313         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2314                             I40E_GLPRT_PTC127L(hw->port),
2315                             pf->offset_loaded, &os->tx_size_127,
2316                             &ns->tx_size_127);
2317         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2318                             I40E_GLPRT_PTC255L(hw->port),
2319                             pf->offset_loaded, &os->tx_size_255,
2320                             &ns->tx_size_255);
2321         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2322                             I40E_GLPRT_PTC511L(hw->port),
2323                             pf->offset_loaded, &os->tx_size_511,
2324                             &ns->tx_size_511);
2325         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2326                             I40E_GLPRT_PTC1023L(hw->port),
2327                             pf->offset_loaded, &os->tx_size_1023,
2328                             &ns->tx_size_1023);
2329         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2330                             I40E_GLPRT_PTC1522L(hw->port),
2331                             pf->offset_loaded, &os->tx_size_1522,
2332                             &ns->tx_size_1522);
2333         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2334                             I40E_GLPRT_PTC9522L(hw->port),
2335                             pf->offset_loaded, &os->tx_size_big,
2336                             &ns->tx_size_big);
2337         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2338                            pf->offset_loaded,
2339                            &os->fd_sb_match, &ns->fd_sb_match);
2340         /* GLPRT_MSPDC not supported */
2341         /* GLPRT_XEC not supported */
2342
2343         pf->offset_loaded = true;
2344
2345         if (pf->main_vsi)
2346                 i40e_update_vsi_stats(pf->main_vsi);
2347 }
2348
2349 /* Get all statistics of a port */
2350 static void
2351 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2352 {
2353         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2354         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2355         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2356         unsigned i;
2357
2358         /* call read registers - updates values, now write them to struct */
2359         i40e_read_stats_registers(pf, hw);
2360
2361         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2362                         pf->main_vsi->eth_stats.rx_multicast +
2363                         pf->main_vsi->eth_stats.rx_broadcast -
2364                         pf->main_vsi->eth_stats.rx_discards;
2365         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2366                         pf->main_vsi->eth_stats.tx_multicast +
2367                         pf->main_vsi->eth_stats.tx_broadcast;
2368         stats->ibytes   = ns->eth.rx_bytes;
2369         stats->obytes   = ns->eth.tx_bytes;
2370         stats->oerrors  = ns->eth.tx_errors +
2371                         pf->main_vsi->eth_stats.tx_errors;
2372
2373         /* Rx Errors */
2374         stats->imissed  = ns->eth.rx_discards +
2375                         pf->main_vsi->eth_stats.rx_discards;
2376         stats->ierrors  = ns->crc_errors +
2377                         ns->rx_length_errors + ns->rx_undersize +
2378                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2379
2380         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2381         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2382         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2383         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2384         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2385         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2386         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2387                     ns->eth.rx_unknown_protocol);
2388         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2389         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2390         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2391         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2392         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2393         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2394
2395         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2396                     ns->tx_dropped_link_down);
2397         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2398         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2399                     ns->illegal_bytes);
2400         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2401         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2402                     ns->mac_local_faults);
2403         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2404                     ns->mac_remote_faults);
2405         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2406                     ns->rx_length_errors);
2407         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2408         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2409         for (i = 0; i < 8; i++) {
2410                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2411                                 i, ns->priority_xon_rx[i]);
2412                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2413                                 i, ns->priority_xoff_rx[i]);
2414         }
2415         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2416         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2417         for (i = 0; i < 8; i++) {
2418                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2419                                 i, ns->priority_xon_tx[i]);
2420                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2421                                 i, ns->priority_xoff_tx[i]);
2422                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2423                                 i, ns->priority_xon_2_xoff[i]);
2424         }
2425         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2426         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2427         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2428         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2429         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2430         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2431         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2432         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2433         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2434         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2435         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2436         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2437         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2438         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2439         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2440         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2441         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2442         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2443         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2444                         ns->mac_short_packet_dropped);
2445         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2446                     ns->checksum_error);
2447         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2448         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2449 }
2450
2451 /* Reset the statistics */
2452 static void
2453 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2454 {
2455         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2456         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2457
2458         /* Mark PF and VSI stats to update the offset, aka "reset" */
2459         pf->offset_loaded = false;
2460         if (pf->main_vsi)
2461                 pf->main_vsi->offset_loaded = false;
2462
2463         /* read the stats, reading current register values into offset */
2464         i40e_read_stats_registers(pf, hw);
2465 }
2466
2467 static uint32_t
2468 i40e_xstats_calc_num(void)
2469 {
2470         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2471                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2472                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2473 }
2474
2475 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2476                                      struct rte_eth_xstat_name *xstats_names,
2477                                      __rte_unused unsigned limit)
2478 {
2479         unsigned count = 0;
2480         unsigned i, prio;
2481
2482         if (xstats_names == NULL)
2483                 return i40e_xstats_calc_num();
2484
2485         /* Note: limit checked in rte_eth_xstats_names() */
2486
2487         /* Get stats from i40e_eth_stats struct */
2488         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2489                 snprintf(xstats_names[count].name,
2490                          sizeof(xstats_names[count].name),
2491                          "%s", rte_i40e_stats_strings[i].name);
2492                 count++;
2493         }
2494
2495         /* Get individiual stats from i40e_hw_port struct */
2496         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2497                 snprintf(xstats_names[count].name,
2498                         sizeof(xstats_names[count].name),
2499                          "%s", rte_i40e_hw_port_strings[i].name);
2500                 count++;
2501         }
2502
2503         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2504                 for (prio = 0; prio < 8; prio++) {
2505                         snprintf(xstats_names[count].name,
2506                                  sizeof(xstats_names[count].name),
2507                                  "rx_priority%u_%s", prio,
2508                                  rte_i40e_rxq_prio_strings[i].name);
2509                         count++;
2510                 }
2511         }
2512
2513         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2514                 for (prio = 0; prio < 8; prio++) {
2515                         snprintf(xstats_names[count].name,
2516                                  sizeof(xstats_names[count].name),
2517                                  "tx_priority%u_%s", prio,
2518                                  rte_i40e_txq_prio_strings[i].name);
2519                         count++;
2520                 }
2521         }
2522         return count;
2523 }
2524
2525 static int
2526 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2527                     unsigned n)
2528 {
2529         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2530         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2531         unsigned i, count, prio;
2532         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2533
2534         count = i40e_xstats_calc_num();
2535         if (n < count)
2536                 return count;
2537
2538         i40e_read_stats_registers(pf, hw);
2539
2540         if (xstats == NULL)
2541                 return 0;
2542
2543         count = 0;
2544
2545         /* Get stats from i40e_eth_stats struct */
2546         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2547                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2548                         rte_i40e_stats_strings[i].offset);
2549                 xstats[count].id = count;
2550                 count++;
2551         }
2552
2553         /* Get individiual stats from i40e_hw_port struct */
2554         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2555                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2556                         rte_i40e_hw_port_strings[i].offset);
2557                 xstats[count].id = count;
2558                 count++;
2559         }
2560
2561         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2562                 for (prio = 0; prio < 8; prio++) {
2563                         xstats[count].value =
2564                                 *(uint64_t *)(((char *)hw_stats) +
2565                                 rte_i40e_rxq_prio_strings[i].offset +
2566                                 (sizeof(uint64_t) * prio));
2567                         xstats[count].id = count;
2568                         count++;
2569                 }
2570         }
2571
2572         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2573                 for (prio = 0; prio < 8; prio++) {
2574                         xstats[count].value =
2575                                 *(uint64_t *)(((char *)hw_stats) +
2576                                 rte_i40e_txq_prio_strings[i].offset +
2577                                 (sizeof(uint64_t) * prio));
2578                         xstats[count].id = count;
2579                         count++;
2580                 }
2581         }
2582
2583         return count;
2584 }
2585
2586 static int
2587 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2588                                  __rte_unused uint16_t queue_id,
2589                                  __rte_unused uint8_t stat_idx,
2590                                  __rte_unused uint8_t is_rx)
2591 {
2592         PMD_INIT_FUNC_TRACE();
2593
2594         return -ENOSYS;
2595 }
2596
2597 static void
2598 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2599 {
2600         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2601         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2602         struct i40e_vsi *vsi = pf->main_vsi;
2603         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2604
2605         dev_info->pci_dev = pci_dev;
2606         dev_info->max_rx_queues = vsi->nb_qps;
2607         dev_info->max_tx_queues = vsi->nb_qps;
2608         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2609         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2610         dev_info->max_mac_addrs = vsi->max_macaddrs;
2611         dev_info->max_vfs = pci_dev->max_vfs;
2612         dev_info->rx_offload_capa =
2613                 DEV_RX_OFFLOAD_VLAN_STRIP |
2614                 DEV_RX_OFFLOAD_QINQ_STRIP |
2615                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2616                 DEV_RX_OFFLOAD_UDP_CKSUM |
2617                 DEV_RX_OFFLOAD_TCP_CKSUM;
2618         dev_info->tx_offload_capa =
2619                 DEV_TX_OFFLOAD_VLAN_INSERT |
2620                 DEV_TX_OFFLOAD_QINQ_INSERT |
2621                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2622                 DEV_TX_OFFLOAD_UDP_CKSUM |
2623                 DEV_TX_OFFLOAD_TCP_CKSUM |
2624                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2625                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2626                 DEV_TX_OFFLOAD_TCP_TSO |
2627                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2628                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2629                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2630                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2631         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2632                                                 sizeof(uint32_t);
2633         dev_info->reta_size = pf->hash_lut_size;
2634         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2635
2636         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2637                 .rx_thresh = {
2638                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2639                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2640                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2641                 },
2642                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2643                 .rx_drop_en = 0,
2644         };
2645
2646         dev_info->default_txconf = (struct rte_eth_txconf) {
2647                 .tx_thresh = {
2648                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2649                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2650                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2651                 },
2652                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2653                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2654                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2655                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2656         };
2657
2658         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2659                 .nb_max = I40E_MAX_RING_DESC,
2660                 .nb_min = I40E_MIN_RING_DESC,
2661                 .nb_align = I40E_ALIGN_RING_DESC,
2662         };
2663
2664         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2665                 .nb_max = I40E_MAX_RING_DESC,
2666                 .nb_min = I40E_MIN_RING_DESC,
2667                 .nb_align = I40E_ALIGN_RING_DESC,
2668                 .nb_seg_max = I40E_TX_MAX_SEG,
2669                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2670         };
2671
2672         if (pf->flags & I40E_FLAG_VMDQ) {
2673                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2674                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2675                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2676                                                 pf->max_nb_vmdq_vsi;
2677                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2678                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2679                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2680         }
2681
2682         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2683                 /* For XL710 */
2684                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2685         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2686                 /* For XXV710 */
2687                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2688         else
2689                 /* For X710 */
2690                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2691 }
2692
2693 static int
2694 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2695 {
2696         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2697         struct i40e_vsi *vsi = pf->main_vsi;
2698         PMD_INIT_FUNC_TRACE();
2699
2700         if (on)
2701                 return i40e_vsi_add_vlan(vsi, vlan_id);
2702         else
2703                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2704 }
2705
2706 static int
2707 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2708                    enum rte_vlan_type vlan_type,
2709                    uint16_t tpid)
2710 {
2711         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2712         uint64_t reg_r = 0, reg_w = 0;
2713         uint16_t reg_id = 0;
2714         int ret = 0;
2715         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2716
2717         switch (vlan_type) {
2718         case ETH_VLAN_TYPE_OUTER:
2719                 if (qinq)
2720                         reg_id = 2;
2721                 else
2722                         reg_id = 3;
2723                 break;
2724         case ETH_VLAN_TYPE_INNER:
2725                 if (qinq)
2726                         reg_id = 3;
2727                 else {
2728                         ret = -EINVAL;
2729                         PMD_DRV_LOG(ERR,
2730                                 "Unsupported vlan type in single vlan.\n");
2731                         return ret;
2732                 }
2733                 break;
2734         default:
2735                 ret = -EINVAL;
2736                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2737                 return ret;
2738         }
2739         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2740                                           &reg_r, NULL);
2741         if (ret != I40E_SUCCESS) {
2742                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2743                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2744                 ret = -EIO;
2745                 return ret;
2746         }
2747         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2748                     "0x%08"PRIx64"", reg_id, reg_r);
2749
2750         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2751         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2752         if (reg_r == reg_w) {
2753                 ret = 0;
2754                 PMD_DRV_LOG(DEBUG, "No need to write");
2755                 return ret;
2756         }
2757
2758         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2759                                            reg_w, NULL);
2760         if (ret != I40E_SUCCESS) {
2761                 ret = -EIO;
2762                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2763                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2764                 return ret;
2765         }
2766         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2767                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2768
2769         return ret;
2770 }
2771
2772 static void
2773 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2774 {
2775         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2776         struct i40e_vsi *vsi = pf->main_vsi;
2777
2778         if (mask & ETH_VLAN_FILTER_MASK) {
2779                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2780                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2781                 else
2782                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2783         }
2784
2785         if (mask & ETH_VLAN_STRIP_MASK) {
2786                 /* Enable or disable VLAN stripping */
2787                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2788                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2789                 else
2790                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2791         }
2792
2793         if (mask & ETH_VLAN_EXTEND_MASK) {
2794                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2795                         i40e_vsi_config_double_vlan(vsi, TRUE);
2796                         /* Set global registers with default ether type value */
2797                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2798                                            ETHER_TYPE_VLAN);
2799                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2800                                            ETHER_TYPE_VLAN);
2801                 }
2802                 else
2803                         i40e_vsi_config_double_vlan(vsi, FALSE);
2804         }
2805 }
2806
2807 static void
2808 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2809                           __rte_unused uint16_t queue,
2810                           __rte_unused int on)
2811 {
2812         PMD_INIT_FUNC_TRACE();
2813 }
2814
2815 static int
2816 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2817 {
2818         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2819         struct i40e_vsi *vsi = pf->main_vsi;
2820         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2821         struct i40e_vsi_vlan_pvid_info info;
2822
2823         memset(&info, 0, sizeof(info));
2824         info.on = on;
2825         if (info.on)
2826                 info.config.pvid = pvid;
2827         else {
2828                 info.config.reject.tagged =
2829                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2830                 info.config.reject.untagged =
2831                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2832         }
2833
2834         return i40e_vsi_vlan_pvid_set(vsi, &info);
2835 }
2836
2837 static int
2838 i40e_dev_led_on(struct rte_eth_dev *dev)
2839 {
2840         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2841         uint32_t mode = i40e_led_get(hw);
2842
2843         if (mode == 0)
2844                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2845
2846         return 0;
2847 }
2848
2849 static int
2850 i40e_dev_led_off(struct rte_eth_dev *dev)
2851 {
2852         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2853         uint32_t mode = i40e_led_get(hw);
2854
2855         if (mode != 0)
2856                 i40e_led_set(hw, 0, false);
2857
2858         return 0;
2859 }
2860
2861 static int
2862 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2863 {
2864         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2865         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2866
2867         fc_conf->pause_time = pf->fc_conf.pause_time;
2868         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2869         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2870
2871          /* Return current mode according to actual setting*/
2872         switch (hw->fc.current_mode) {
2873         case I40E_FC_FULL:
2874                 fc_conf->mode = RTE_FC_FULL;
2875                 break;
2876         case I40E_FC_TX_PAUSE:
2877                 fc_conf->mode = RTE_FC_TX_PAUSE;
2878                 break;
2879         case I40E_FC_RX_PAUSE:
2880                 fc_conf->mode = RTE_FC_RX_PAUSE;
2881                 break;
2882         case I40E_FC_NONE:
2883         default:
2884                 fc_conf->mode = RTE_FC_NONE;
2885         };
2886
2887         return 0;
2888 }
2889
2890 static int
2891 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2892 {
2893         uint32_t mflcn_reg, fctrl_reg, reg;
2894         uint32_t max_high_water;
2895         uint8_t i, aq_failure;
2896         int err;
2897         struct i40e_hw *hw;
2898         struct i40e_pf *pf;
2899         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2900                 [RTE_FC_NONE] = I40E_FC_NONE,
2901                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2902                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2903                 [RTE_FC_FULL] = I40E_FC_FULL
2904         };
2905
2906         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2907
2908         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2909         if ((fc_conf->high_water > max_high_water) ||
2910                         (fc_conf->high_water < fc_conf->low_water)) {
2911                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2912                         "High_water must <= %d.", max_high_water);
2913                 return -EINVAL;
2914         }
2915
2916         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2917         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2918         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2919
2920         pf->fc_conf.pause_time = fc_conf->pause_time;
2921         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2922         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2923
2924         PMD_INIT_FUNC_TRACE();
2925
2926         /* All the link flow control related enable/disable register
2927          * configuration is handle by the F/W
2928          */
2929         err = i40e_set_fc(hw, &aq_failure, true);
2930         if (err < 0)
2931                 return -ENOSYS;
2932
2933         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
2934                 /* Configure flow control refresh threshold,
2935                  * the value for stat_tx_pause_refresh_timer[8]
2936                  * is used for global pause operation.
2937                  */
2938
2939                 I40E_WRITE_REG(hw,
2940                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2941                                pf->fc_conf.pause_time);
2942
2943                 /* configure the timer value included in transmitted pause
2944                  * frame,
2945                  * the value for stat_tx_pause_quanta[8] is used for global
2946                  * pause operation
2947                  */
2948                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2949                                pf->fc_conf.pause_time);
2950
2951                 fctrl_reg = I40E_READ_REG(hw,
2952                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2953
2954                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2955                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2956                 else
2957                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2958
2959                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2960                                fctrl_reg);
2961         } else {
2962                 /* Configure pause time (2 TCs per register) */
2963                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2964                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2965                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2966
2967                 /* Configure flow control refresh threshold value */
2968                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2969                                pf->fc_conf.pause_time / 2);
2970
2971                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2972
2973                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2974                  *depending on configuration
2975                  */
2976                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2977                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2978                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2979                 } else {
2980                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2981                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2982                 }
2983
2984                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2985         }
2986
2987         /* config the water marker both based on the packets and bytes */
2988         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2989                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2990                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2991         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2992                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2993                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2994         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2995                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2996                        << I40E_KILOSHIFT);
2997         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2998                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2999                        << I40E_KILOSHIFT);
3000
3001         I40E_WRITE_FLUSH(hw);
3002
3003         return 0;
3004 }
3005
3006 static int
3007 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3008                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3009 {
3010         PMD_INIT_FUNC_TRACE();
3011
3012         return -ENOSYS;
3013 }
3014
3015 /* Add a MAC address, and update filters */
3016 static void
3017 i40e_macaddr_add(struct rte_eth_dev *dev,
3018                  struct ether_addr *mac_addr,
3019                  __rte_unused uint32_t index,
3020                  uint32_t pool)
3021 {
3022         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3023         struct i40e_mac_filter_info mac_filter;
3024         struct i40e_vsi *vsi;
3025         int ret;
3026
3027         /* If VMDQ not enabled or configured, return */
3028         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3029                           !pf->nb_cfg_vmdq_vsi)) {
3030                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3031                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3032                         pool);
3033                 return;
3034         }
3035
3036         if (pool > pf->nb_cfg_vmdq_vsi) {
3037                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3038                                 pool, pf->nb_cfg_vmdq_vsi);
3039                 return;
3040         }
3041
3042         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3043         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3044                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3045         else
3046                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3047
3048         if (pool == 0)
3049                 vsi = pf->main_vsi;
3050         else
3051                 vsi = pf->vmdq[pool - 1].vsi;
3052
3053         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3054         if (ret != I40E_SUCCESS) {
3055                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3056                 return;
3057         }
3058 }
3059
3060 /* Remove a MAC address, and update filters */
3061 static void
3062 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3063 {
3064         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3065         struct i40e_vsi *vsi;
3066         struct rte_eth_dev_data *data = dev->data;
3067         struct ether_addr *macaddr;
3068         int ret;
3069         uint32_t i;
3070         uint64_t pool_sel;
3071
3072         macaddr = &(data->mac_addrs[index]);
3073
3074         pool_sel = dev->data->mac_pool_sel[index];
3075
3076         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3077                 if (pool_sel & (1ULL << i)) {
3078                         if (i == 0)
3079                                 vsi = pf->main_vsi;
3080                         else {
3081                                 /* No VMDQ pool enabled or configured */
3082                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3083                                         (i > pf->nb_cfg_vmdq_vsi)) {
3084                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3085                                                         "/configured");
3086                                         return;
3087                                 }
3088                                 vsi = pf->vmdq[i - 1].vsi;
3089                         }
3090                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3091
3092                         if (ret) {
3093                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3094                                 return;
3095                         }
3096                 }
3097         }
3098 }
3099
3100 /* Set perfect match or hash match of MAC and VLAN for a VF */
3101 static int
3102 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3103                  struct rte_eth_mac_filter *filter,
3104                  bool add)
3105 {
3106         struct i40e_hw *hw;
3107         struct i40e_mac_filter_info mac_filter;
3108         struct ether_addr old_mac;
3109         struct ether_addr *new_mac;
3110         struct i40e_pf_vf *vf = NULL;
3111         uint16_t vf_id;
3112         int ret;
3113
3114         if (pf == NULL) {
3115                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3116                 return -EINVAL;
3117         }
3118         hw = I40E_PF_TO_HW(pf);
3119
3120         if (filter == NULL) {
3121                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3122                 return -EINVAL;
3123         }
3124
3125         new_mac = &filter->mac_addr;
3126
3127         if (is_zero_ether_addr(new_mac)) {
3128                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3129                 return -EINVAL;
3130         }
3131
3132         vf_id = filter->dst_id;
3133
3134         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3135                 PMD_DRV_LOG(ERR, "Invalid argument.");
3136                 return -EINVAL;
3137         }
3138         vf = &pf->vfs[vf_id];
3139
3140         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3141                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3142                 return -EINVAL;
3143         }
3144
3145         if (add) {
3146                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3147                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3148                                 ETHER_ADDR_LEN);
3149                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3150                                  ETHER_ADDR_LEN);
3151
3152                 mac_filter.filter_type = filter->filter_type;
3153                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3154                 if (ret != I40E_SUCCESS) {
3155                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3156                         return -1;
3157                 }
3158                 ether_addr_copy(new_mac, &pf->dev_addr);
3159         } else {
3160                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3161                                 ETHER_ADDR_LEN);
3162                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3163                 if (ret != I40E_SUCCESS) {
3164                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3165                         return -1;
3166                 }
3167
3168                 /* Clear device address as it has been removed */
3169                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3170                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3171         }
3172
3173         return 0;
3174 }
3175
3176 /* MAC filter handle */
3177 static int
3178 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3179                 void *arg)
3180 {
3181         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3182         struct rte_eth_mac_filter *filter;
3183         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3184         int ret = I40E_NOT_SUPPORTED;
3185
3186         filter = (struct rte_eth_mac_filter *)(arg);
3187
3188         switch (filter_op) {
3189         case RTE_ETH_FILTER_NOP:
3190                 ret = I40E_SUCCESS;
3191                 break;
3192         case RTE_ETH_FILTER_ADD:
3193                 i40e_pf_disable_irq0(hw);
3194                 if (filter->is_vf)
3195                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3196                 i40e_pf_enable_irq0(hw);
3197                 break;
3198         case RTE_ETH_FILTER_DELETE:
3199                 i40e_pf_disable_irq0(hw);
3200                 if (filter->is_vf)
3201                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3202                 i40e_pf_enable_irq0(hw);
3203                 break;
3204         default:
3205                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3206                 ret = I40E_ERR_PARAM;
3207                 break;
3208         }
3209
3210         return ret;
3211 }
3212
3213 static int
3214 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3215 {
3216         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3217         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3218         int ret;
3219
3220         if (!lut)
3221                 return -EINVAL;
3222
3223         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3224                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3225                                           lut, lut_size);
3226                 if (ret) {
3227                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3228                         return ret;
3229                 }
3230         } else {
3231                 uint32_t *lut_dw = (uint32_t *)lut;
3232                 uint16_t i, lut_size_dw = lut_size / 4;
3233
3234                 for (i = 0; i < lut_size_dw; i++)
3235                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3236         }
3237
3238         return 0;
3239 }
3240
3241 static int
3242 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3243 {
3244         struct i40e_pf *pf;
3245         struct i40e_hw *hw;
3246         int ret;
3247
3248         if (!vsi || !lut)
3249                 return -EINVAL;
3250
3251         pf = I40E_VSI_TO_PF(vsi);
3252         hw = I40E_VSI_TO_HW(vsi);
3253
3254         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3255                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3256                                           lut, lut_size);
3257                 if (ret) {
3258                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3259                         return ret;
3260                 }
3261         } else {
3262                 uint32_t *lut_dw = (uint32_t *)lut;
3263                 uint16_t i, lut_size_dw = lut_size / 4;
3264
3265                 for (i = 0; i < lut_size_dw; i++)
3266                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3267                 I40E_WRITE_FLUSH(hw);
3268         }
3269
3270         return 0;
3271 }
3272
3273 static int
3274 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3275                          struct rte_eth_rss_reta_entry64 *reta_conf,
3276                          uint16_t reta_size)
3277 {
3278         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3279         uint16_t i, lut_size = pf->hash_lut_size;
3280         uint16_t idx, shift;
3281         uint8_t *lut;
3282         int ret;
3283
3284         if (reta_size != lut_size ||
3285                 reta_size > ETH_RSS_RETA_SIZE_512) {
3286                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3287                         "(%d) doesn't match the number hardware can supported "
3288                                         "(%d)\n", reta_size, lut_size);
3289                 return -EINVAL;
3290         }
3291
3292         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3293         if (!lut) {
3294                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3295                 return -ENOMEM;
3296         }
3297         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3298         if (ret)
3299                 goto out;
3300         for (i = 0; i < reta_size; i++) {
3301                 idx = i / RTE_RETA_GROUP_SIZE;
3302                 shift = i % RTE_RETA_GROUP_SIZE;
3303                 if (reta_conf[idx].mask & (1ULL << shift))
3304                         lut[i] = reta_conf[idx].reta[shift];
3305         }
3306         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3307
3308 out:
3309         rte_free(lut);
3310
3311         return ret;
3312 }
3313
3314 static int
3315 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3316                         struct rte_eth_rss_reta_entry64 *reta_conf,
3317                         uint16_t reta_size)
3318 {
3319         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3320         uint16_t i, lut_size = pf->hash_lut_size;
3321         uint16_t idx, shift;
3322         uint8_t *lut;
3323         int ret;
3324
3325         if (reta_size != lut_size ||
3326                 reta_size > ETH_RSS_RETA_SIZE_512) {
3327                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3328                         "(%d) doesn't match the number hardware can supported "
3329                                         "(%d)\n", reta_size, lut_size);
3330                 return -EINVAL;
3331         }
3332
3333         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3334         if (!lut) {
3335                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3336                 return -ENOMEM;
3337         }
3338
3339         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3340         if (ret)
3341                 goto out;
3342         for (i = 0; i < reta_size; i++) {
3343                 idx = i / RTE_RETA_GROUP_SIZE;
3344                 shift = i % RTE_RETA_GROUP_SIZE;
3345                 if (reta_conf[idx].mask & (1ULL << shift))
3346                         reta_conf[idx].reta[shift] = lut[i];
3347         }
3348
3349 out:
3350         rte_free(lut);
3351
3352         return ret;
3353 }
3354
3355 /**
3356  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3357  * @hw:   pointer to the HW structure
3358  * @mem:  pointer to mem struct to fill out
3359  * @size: size of memory requested
3360  * @alignment: what to align the allocation to
3361  **/
3362 enum i40e_status_code
3363 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3364                         struct i40e_dma_mem *mem,
3365                         u64 size,
3366                         u32 alignment)
3367 {
3368         const struct rte_memzone *mz = NULL;
3369         char z_name[RTE_MEMZONE_NAMESIZE];
3370
3371         if (!mem)
3372                 return I40E_ERR_PARAM;
3373
3374         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3375         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3376                                          alignment, RTE_PGSIZE_2M);
3377         if (!mz)
3378                 return I40E_ERR_NO_MEMORY;
3379
3380         mem->size = size;
3381         mem->va = mz->addr;
3382         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3383         mem->zone = (const void *)mz;
3384         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3385                     "%"PRIu64, mz->name, mem->pa);
3386
3387         return I40E_SUCCESS;
3388 }
3389
3390 /**
3391  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3392  * @hw:   pointer to the HW structure
3393  * @mem:  ptr to mem struct to free
3394  **/
3395 enum i40e_status_code
3396 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3397                     struct i40e_dma_mem *mem)
3398 {
3399         if (!mem)
3400                 return I40E_ERR_PARAM;
3401
3402         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3403                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3404                     mem->pa);
3405         rte_memzone_free((const struct rte_memzone *)mem->zone);
3406         mem->zone = NULL;
3407         mem->va = NULL;
3408         mem->pa = (u64)0;
3409
3410         return I40E_SUCCESS;
3411 }
3412
3413 /**
3414  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3415  * @hw:   pointer to the HW structure
3416  * @mem:  pointer to mem struct to fill out
3417  * @size: size of memory requested
3418  **/
3419 enum i40e_status_code
3420 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3421                          struct i40e_virt_mem *mem,
3422                          u32 size)
3423 {
3424         if (!mem)
3425                 return I40E_ERR_PARAM;
3426
3427         mem->size = size;
3428         mem->va = rte_zmalloc("i40e", size, 0);
3429
3430         if (mem->va)
3431                 return I40E_SUCCESS;
3432         else
3433                 return I40E_ERR_NO_MEMORY;
3434 }
3435
3436 /**
3437  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3438  * @hw:   pointer to the HW structure
3439  * @mem:  pointer to mem struct to free
3440  **/
3441 enum i40e_status_code
3442 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3443                      struct i40e_virt_mem *mem)
3444 {
3445         if (!mem)
3446                 return I40E_ERR_PARAM;
3447
3448         rte_free(mem->va);
3449         mem->va = NULL;
3450
3451         return I40E_SUCCESS;
3452 }
3453
3454 void
3455 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3456 {
3457         rte_spinlock_init(&sp->spinlock);
3458 }
3459
3460 void
3461 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3462 {
3463         rte_spinlock_lock(&sp->spinlock);
3464 }
3465
3466 void
3467 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3468 {
3469         rte_spinlock_unlock(&sp->spinlock);
3470 }
3471
3472 void
3473 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3474 {
3475         return;
3476 }
3477
3478 /**
3479  * Get the hardware capabilities, which will be parsed
3480  * and saved into struct i40e_hw.
3481  */
3482 static int
3483 i40e_get_cap(struct i40e_hw *hw)
3484 {
3485         struct i40e_aqc_list_capabilities_element_resp *buf;
3486         uint16_t len, size = 0;
3487         int ret;
3488
3489         /* Calculate a huge enough buff for saving response data temporarily */
3490         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3491                                                 I40E_MAX_CAP_ELE_NUM;
3492         buf = rte_zmalloc("i40e", len, 0);
3493         if (!buf) {
3494                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3495                 return I40E_ERR_NO_MEMORY;
3496         }
3497
3498         /* Get, parse the capabilities and save it to hw */
3499         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3500                         i40e_aqc_opc_list_func_capabilities, NULL);
3501         if (ret != I40E_SUCCESS)
3502                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3503
3504         /* Free the temporary buffer after being used */
3505         rte_free(buf);
3506
3507         return ret;
3508 }
3509
3510 static int
3511 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3512 {
3513         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3514         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3515         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3516         uint16_t qp_count = 0, vsi_count = 0;
3517
3518         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3519                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3520                 return -EINVAL;
3521         }
3522         /* Add the parameter init for LFC */
3523         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3524         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3525         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3526
3527         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3528         pf->max_num_vsi = hw->func_caps.num_vsis;
3529         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3530         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3531         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3532
3533         /* FDir queue/VSI allocation */
3534         pf->fdir_qp_offset = 0;
3535         if (hw->func_caps.fd) {
3536                 pf->flags |= I40E_FLAG_FDIR;
3537                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3538         } else {
3539                 pf->fdir_nb_qps = 0;
3540         }
3541         qp_count += pf->fdir_nb_qps;
3542         vsi_count += 1;
3543
3544         /* LAN queue/VSI allocation */
3545         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3546         if (!hw->func_caps.rss) {
3547                 pf->lan_nb_qps = 1;
3548         } else {
3549                 pf->flags |= I40E_FLAG_RSS;
3550                 if (hw->mac.type == I40E_MAC_X722)
3551                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3552                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3553         }
3554         qp_count += pf->lan_nb_qps;
3555         vsi_count += 1;
3556
3557         /* VF queue/VSI allocation */
3558         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3559         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3560                 pf->flags |= I40E_FLAG_SRIOV;
3561                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3562                 pf->vf_num = pci_dev->max_vfs;
3563                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3564                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3565                             pf->vf_nb_qps * pf->vf_num);
3566         } else {
3567                 pf->vf_nb_qps = 0;
3568                 pf->vf_num = 0;
3569         }
3570         qp_count += pf->vf_nb_qps * pf->vf_num;
3571         vsi_count += pf->vf_num;
3572
3573         /* VMDq queue/VSI allocation */
3574         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3575         pf->vmdq_nb_qps = 0;
3576         pf->max_nb_vmdq_vsi = 0;
3577         if (hw->func_caps.vmdq) {
3578                 if (qp_count < hw->func_caps.num_tx_qp &&
3579                         vsi_count < hw->func_caps.num_vsis) {
3580                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3581                                 qp_count) / pf->vmdq_nb_qp_max;
3582
3583                         /* Limit the maximum number of VMDq vsi to the maximum
3584                          * ethdev can support
3585                          */
3586                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3587                                 hw->func_caps.num_vsis - vsi_count);
3588                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3589                                 ETH_64_POOLS);
3590                         if (pf->max_nb_vmdq_vsi) {
3591                                 pf->flags |= I40E_FLAG_VMDQ;
3592                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3593                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3594                                             "per VMDQ VSI, in total %u queues",
3595                                             pf->max_nb_vmdq_vsi,
3596                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3597                                             pf->max_nb_vmdq_vsi);
3598                         } else {
3599                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3600                                             "VMDq");
3601                         }
3602                 } else {
3603                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3604                 }
3605         }
3606         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3607         vsi_count += pf->max_nb_vmdq_vsi;
3608
3609         if (hw->func_caps.dcb)
3610                 pf->flags |= I40E_FLAG_DCB;
3611
3612         if (qp_count > hw->func_caps.num_tx_qp) {
3613                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3614                             "the hardware maximum %u", qp_count,
3615                             hw->func_caps.num_tx_qp);
3616                 return -EINVAL;
3617         }
3618         if (vsi_count > hw->func_caps.num_vsis) {
3619                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3620                             "the hardware maximum %u", vsi_count,
3621                             hw->func_caps.num_vsis);
3622                 return -EINVAL;
3623         }
3624
3625         return 0;
3626 }
3627
3628 static int
3629 i40e_pf_get_switch_config(struct i40e_pf *pf)
3630 {
3631         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3632         struct i40e_aqc_get_switch_config_resp *switch_config;
3633         struct i40e_aqc_switch_config_element_resp *element;
3634         uint16_t start_seid = 0, num_reported;
3635         int ret;
3636
3637         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3638                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3639         if (!switch_config) {
3640                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3641                 return -ENOMEM;
3642         }
3643
3644         /* Get the switch configurations */
3645         ret = i40e_aq_get_switch_config(hw, switch_config,
3646                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3647         if (ret != I40E_SUCCESS) {
3648                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3649                 goto fail;
3650         }
3651         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3652         if (num_reported != 1) { /* The number should be 1 */
3653                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3654                 goto fail;
3655         }
3656
3657         /* Parse the switch configuration elements */
3658         element = &(switch_config->element[0]);
3659         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3660                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3661                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3662         } else
3663                 PMD_DRV_LOG(INFO, "Unknown element type");
3664
3665 fail:
3666         rte_free(switch_config);
3667
3668         return ret;
3669 }
3670
3671 static int
3672 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3673                         uint32_t num)
3674 {
3675         struct pool_entry *entry;
3676
3677         if (pool == NULL || num == 0)
3678                 return -EINVAL;
3679
3680         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3681         if (entry == NULL) {
3682                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3683                 return -ENOMEM;
3684         }
3685
3686         /* queue heap initialize */
3687         pool->num_free = num;
3688         pool->num_alloc = 0;
3689         pool->base = base;
3690         LIST_INIT(&pool->alloc_list);
3691         LIST_INIT(&pool->free_list);
3692
3693         /* Initialize element  */
3694         entry->base = 0;
3695         entry->len = num;
3696
3697         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3698         return 0;
3699 }
3700
3701 static void
3702 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3703 {
3704         struct pool_entry *entry, *next_entry;
3705
3706         if (pool == NULL)
3707                 return;
3708
3709         for (entry = LIST_FIRST(&pool->alloc_list);
3710                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3711                         entry = next_entry) {
3712                 LIST_REMOVE(entry, next);
3713                 rte_free(entry);
3714         }
3715
3716         for (entry = LIST_FIRST(&pool->free_list);
3717                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3718                         entry = next_entry) {
3719                 LIST_REMOVE(entry, next);
3720                 rte_free(entry);
3721         }
3722
3723         pool->num_free = 0;
3724         pool->num_alloc = 0;
3725         pool->base = 0;
3726         LIST_INIT(&pool->alloc_list);
3727         LIST_INIT(&pool->free_list);
3728 }
3729
3730 static int
3731 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3732                        uint32_t base)
3733 {
3734         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3735         uint32_t pool_offset;
3736         int insert;
3737
3738         if (pool == NULL) {
3739                 PMD_DRV_LOG(ERR, "Invalid parameter");
3740                 return -EINVAL;
3741         }
3742
3743         pool_offset = base - pool->base;
3744         /* Lookup in alloc list */
3745         LIST_FOREACH(entry, &pool->alloc_list, next) {
3746                 if (entry->base == pool_offset) {
3747                         valid_entry = entry;
3748                         LIST_REMOVE(entry, next);
3749                         break;
3750                 }
3751         }
3752
3753         /* Not find, return */
3754         if (valid_entry == NULL) {
3755                 PMD_DRV_LOG(ERR, "Failed to find entry");
3756                 return -EINVAL;
3757         }
3758
3759         /**
3760          * Found it, move it to free list  and try to merge.
3761          * In order to make merge easier, always sort it by qbase.
3762          * Find adjacent prev and last entries.
3763          */
3764         prev = next = NULL;
3765         LIST_FOREACH(entry, &pool->free_list, next) {
3766                 if (entry->base > valid_entry->base) {
3767                         next = entry;
3768                         break;
3769                 }
3770                 prev = entry;
3771         }
3772
3773         insert = 0;
3774         /* Try to merge with next one*/
3775         if (next != NULL) {
3776                 /* Merge with next one */
3777                 if (valid_entry->base + valid_entry->len == next->base) {
3778                         next->base = valid_entry->base;
3779                         next->len += valid_entry->len;
3780                         rte_free(valid_entry);
3781                         valid_entry = next;
3782                         insert = 1;
3783                 }
3784         }
3785
3786         if (prev != NULL) {
3787                 /* Merge with previous one */
3788                 if (prev->base + prev->len == valid_entry->base) {
3789                         prev->len += valid_entry->len;
3790                         /* If it merge with next one, remove next node */
3791                         if (insert == 1) {
3792                                 LIST_REMOVE(valid_entry, next);
3793                                 rte_free(valid_entry);
3794                         } else {
3795                                 rte_free(valid_entry);
3796                                 insert = 1;
3797                         }
3798                 }
3799         }
3800
3801         /* Not find any entry to merge, insert */
3802         if (insert == 0) {
3803                 if (prev != NULL)
3804                         LIST_INSERT_AFTER(prev, valid_entry, next);
3805                 else if (next != NULL)
3806                         LIST_INSERT_BEFORE(next, valid_entry, next);
3807                 else /* It's empty list, insert to head */
3808                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3809         }
3810
3811         pool->num_free += valid_entry->len;
3812         pool->num_alloc -= valid_entry->len;
3813
3814         return 0;
3815 }
3816
3817 static int
3818 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3819                        uint16_t num)
3820 {
3821         struct pool_entry *entry, *valid_entry;
3822
3823         if (pool == NULL || num == 0) {
3824                 PMD_DRV_LOG(ERR, "Invalid parameter");
3825                 return -EINVAL;
3826         }
3827
3828         if (pool->num_free < num) {
3829                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3830                             num, pool->num_free);
3831                 return -ENOMEM;
3832         }
3833
3834         valid_entry = NULL;
3835         /* Lookup  in free list and find most fit one */
3836         LIST_FOREACH(entry, &pool->free_list, next) {
3837                 if (entry->len >= num) {
3838                         /* Find best one */
3839                         if (entry->len == num) {
3840                                 valid_entry = entry;
3841                                 break;
3842                         }
3843                         if (valid_entry == NULL || valid_entry->len > entry->len)
3844                                 valid_entry = entry;
3845                 }
3846         }
3847
3848         /* Not find one to satisfy the request, return */
3849         if (valid_entry == NULL) {
3850                 PMD_DRV_LOG(ERR, "No valid entry found");
3851                 return -ENOMEM;
3852         }
3853         /**
3854          * The entry have equal queue number as requested,
3855          * remove it from alloc_list.
3856          */
3857         if (valid_entry->len == num) {
3858                 LIST_REMOVE(valid_entry, next);
3859         } else {
3860                 /**
3861                  * The entry have more numbers than requested,
3862                  * create a new entry for alloc_list and minus its
3863                  * queue base and number in free_list.
3864                  */
3865                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3866                 if (entry == NULL) {
3867                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3868                                     "resource pool");
3869                         return -ENOMEM;
3870                 }
3871                 entry->base = valid_entry->base;
3872                 entry->len = num;
3873                 valid_entry->base += num;
3874                 valid_entry->len -= num;
3875                 valid_entry = entry;
3876         }
3877
3878         /* Insert it into alloc list, not sorted */
3879         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3880
3881         pool->num_free -= valid_entry->len;
3882         pool->num_alloc += valid_entry->len;
3883
3884         return valid_entry->base + pool->base;
3885 }
3886
3887 /**
3888  * bitmap_is_subset - Check whether src2 is subset of src1
3889  **/
3890 static inline int
3891 bitmap_is_subset(uint8_t src1, uint8_t src2)
3892 {
3893         return !((src1 ^ src2) & src2);
3894 }
3895
3896 static enum i40e_status_code
3897 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3898 {
3899         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3900
3901         /* If DCB is not supported, only default TC is supported */
3902         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3903                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3904                 return I40E_NOT_SUPPORTED;
3905         }
3906
3907         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3908                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3909                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3910                             enabled_tcmap);
3911                 return I40E_NOT_SUPPORTED;
3912         }
3913         return I40E_SUCCESS;
3914 }
3915
3916 int
3917 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3918                                 struct i40e_vsi_vlan_pvid_info *info)
3919 {
3920         struct i40e_hw *hw;
3921         struct i40e_vsi_context ctxt;
3922         uint8_t vlan_flags = 0;
3923         int ret;
3924
3925         if (vsi == NULL || info == NULL) {
3926                 PMD_DRV_LOG(ERR, "invalid parameters");
3927                 return I40E_ERR_PARAM;
3928         }
3929
3930         if (info->on) {
3931                 vsi->info.pvid = info->config.pvid;
3932                 /**
3933                  * If insert pvid is enabled, only tagged pkts are
3934                  * allowed to be sent out.
3935                  */
3936                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3937                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3938         } else {
3939                 vsi->info.pvid = 0;
3940                 if (info->config.reject.tagged == 0)
3941                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3942
3943                 if (info->config.reject.untagged == 0)
3944                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3945         }
3946         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3947                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3948         vsi->info.port_vlan_flags |= vlan_flags;
3949         vsi->info.valid_sections =
3950                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3951         memset(&ctxt, 0, sizeof(ctxt));
3952         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3953         ctxt.seid = vsi->seid;
3954
3955         hw = I40E_VSI_TO_HW(vsi);
3956         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3957         if (ret != I40E_SUCCESS)
3958                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3959
3960         return ret;
3961 }
3962
3963 static int
3964 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3965 {
3966         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3967         int i, ret;
3968         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3969
3970         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3971         if (ret != I40E_SUCCESS)
3972                 return ret;
3973
3974         if (!vsi->seid) {
3975                 PMD_DRV_LOG(ERR, "seid not valid");
3976                 return -EINVAL;
3977         }
3978
3979         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3980         tc_bw_data.tc_valid_bits = enabled_tcmap;
3981         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3982                 tc_bw_data.tc_bw_credits[i] =
3983                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3984
3985         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3986         if (ret != I40E_SUCCESS) {
3987                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3988                 return ret;
3989         }
3990
3991         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3992                                         sizeof(vsi->info.qs_handle));
3993         return I40E_SUCCESS;
3994 }
3995
3996 static enum i40e_status_code
3997 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3998                                  struct i40e_aqc_vsi_properties_data *info,
3999                                  uint8_t enabled_tcmap)
4000 {
4001         enum i40e_status_code ret;
4002         int i, total_tc = 0;
4003         uint16_t qpnum_per_tc, bsf, qp_idx;
4004
4005         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4006         if (ret != I40E_SUCCESS)
4007                 return ret;
4008
4009         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4010                 if (enabled_tcmap & (1 << i))
4011                         total_tc++;
4012         vsi->enabled_tc = enabled_tcmap;
4013
4014         /* Number of queues per enabled TC */
4015         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4016         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4017         bsf = rte_bsf32(qpnum_per_tc);
4018
4019         /* Adjust the queue number to actual queues that can be applied */
4020         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4021                 vsi->nb_qps = qpnum_per_tc * total_tc;
4022
4023         /**
4024          * Configure TC and queue mapping parameters, for enabled TC,
4025          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4026          * default queue will serve it.
4027          */
4028         qp_idx = 0;
4029         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4030                 if (vsi->enabled_tc & (1 << i)) {
4031                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4032                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4033                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4034                         qp_idx += qpnum_per_tc;
4035                 } else
4036                         info->tc_mapping[i] = 0;
4037         }
4038
4039         /* Associate queue number with VSI */
4040         if (vsi->type == I40E_VSI_SRIOV) {
4041                 info->mapping_flags |=
4042                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4043                 for (i = 0; i < vsi->nb_qps; i++)
4044                         info->queue_mapping[i] =
4045                                 rte_cpu_to_le_16(vsi->base_queue + i);
4046         } else {
4047                 info->mapping_flags |=
4048                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4049                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4050         }
4051         info->valid_sections |=
4052                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4053
4054         return I40E_SUCCESS;
4055 }
4056
4057 static int
4058 i40e_veb_release(struct i40e_veb *veb)
4059 {
4060         struct i40e_vsi *vsi;
4061         struct i40e_hw *hw;
4062
4063         if (veb == NULL)
4064                 return -EINVAL;
4065
4066         if (!TAILQ_EMPTY(&veb->head)) {
4067                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4068                 return -EACCES;
4069         }
4070         /* associate_vsi field is NULL for floating VEB */
4071         if (veb->associate_vsi != NULL) {
4072                 vsi = veb->associate_vsi;
4073                 hw = I40E_VSI_TO_HW(vsi);
4074
4075                 vsi->uplink_seid = veb->uplink_seid;
4076                 vsi->veb = NULL;
4077         } else {
4078                 veb->associate_pf->main_vsi->floating_veb = NULL;
4079                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4080         }
4081
4082         i40e_aq_delete_element(hw, veb->seid, NULL);
4083         rte_free(veb);
4084         return I40E_SUCCESS;
4085 }
4086
4087 /* Setup a veb */
4088 static struct i40e_veb *
4089 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4090 {
4091         struct i40e_veb *veb;
4092         int ret;
4093         struct i40e_hw *hw;
4094
4095         if (pf == NULL) {
4096                 PMD_DRV_LOG(ERR,
4097                             "veb setup failed, associated PF shouldn't null");
4098                 return NULL;
4099         }
4100         hw = I40E_PF_TO_HW(pf);
4101
4102         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4103         if (!veb) {
4104                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4105                 goto fail;
4106         }
4107
4108         veb->associate_vsi = vsi;
4109         veb->associate_pf = pf;
4110         TAILQ_INIT(&veb->head);
4111         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4112
4113         /* create floating veb if vsi is NULL */
4114         if (vsi != NULL) {
4115                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4116                                       I40E_DEFAULT_TCMAP, false,
4117                                       &veb->seid, false, NULL);
4118         } else {
4119                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4120                                       true, &veb->seid, false, NULL);
4121         }
4122
4123         if (ret != I40E_SUCCESS) {
4124                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4125                             hw->aq.asq_last_status);
4126                 goto fail;
4127         }
4128
4129         /* get statistics index */
4130         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4131                                 &veb->stats_idx, NULL, NULL, NULL);
4132         if (ret != I40E_SUCCESS) {
4133                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4134                             hw->aq.asq_last_status);
4135                 goto fail;
4136         }
4137         /* Get VEB bandwidth, to be implemented */
4138         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4139         if (vsi)
4140                 vsi->uplink_seid = veb->seid;
4141
4142         return veb;
4143 fail:
4144         rte_free(veb);
4145         return NULL;
4146 }
4147
4148 int
4149 i40e_vsi_release(struct i40e_vsi *vsi)
4150 {
4151         struct i40e_pf *pf;
4152         struct i40e_hw *hw;
4153         struct i40e_vsi_list *vsi_list;
4154         void *temp;
4155         int ret;
4156         struct i40e_mac_filter *f;
4157         uint16_t user_param;
4158
4159         if (!vsi)
4160                 return I40E_SUCCESS;
4161
4162         user_param = vsi->user_param;
4163
4164         pf = I40E_VSI_TO_PF(vsi);
4165         hw = I40E_VSI_TO_HW(vsi);
4166
4167         /* VSI has child to attach, release child first */
4168         if (vsi->veb) {
4169                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4170                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4171                                 return -1;
4172                 }
4173                 i40e_veb_release(vsi->veb);
4174         }
4175
4176         if (vsi->floating_veb) {
4177                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4178                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4179                                 return -1;
4180                 }
4181         }
4182
4183         /* Remove all macvlan filters of the VSI */
4184         i40e_vsi_remove_all_macvlan_filter(vsi);
4185         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4186                 rte_free(f);
4187
4188         if (vsi->type != I40E_VSI_MAIN &&
4189             ((vsi->type != I40E_VSI_SRIOV) ||
4190             !pf->floating_veb_list[user_param])) {
4191                 /* Remove vsi from parent's sibling list */
4192                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4193                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4194                         return I40E_ERR_PARAM;
4195                 }
4196                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4197                                 &vsi->sib_vsi_list, list);
4198
4199                 /* Remove all switch element of the VSI */
4200                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4201                 if (ret != I40E_SUCCESS)
4202                         PMD_DRV_LOG(ERR, "Failed to delete element");
4203         }
4204
4205         if ((vsi->type == I40E_VSI_SRIOV) &&
4206             pf->floating_veb_list[user_param]) {
4207                 /* Remove vsi from parent's sibling list */
4208                 if (vsi->parent_vsi == NULL ||
4209                     vsi->parent_vsi->floating_veb == NULL) {
4210                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4211                         return I40E_ERR_PARAM;
4212                 }
4213                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4214                              &vsi->sib_vsi_list, list);
4215
4216                 /* Remove all switch element of the VSI */
4217                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4218                 if (ret != I40E_SUCCESS)
4219                         PMD_DRV_LOG(ERR, "Failed to delete element");
4220         }
4221
4222         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4223
4224         if (vsi->type != I40E_VSI_SRIOV)
4225                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4226         rte_free(vsi);
4227
4228         return I40E_SUCCESS;
4229 }
4230
4231 static int
4232 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4233 {
4234         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4235         struct i40e_aqc_remove_macvlan_element_data def_filter;
4236         struct i40e_mac_filter_info filter;
4237         int ret;
4238
4239         if (vsi->type != I40E_VSI_MAIN)
4240                 return I40E_ERR_CONFIG;
4241         memset(&def_filter, 0, sizeof(def_filter));
4242         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4243                                         ETH_ADDR_LEN);
4244         def_filter.vlan_tag = 0;
4245         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4246                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4247         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4248         if (ret != I40E_SUCCESS) {
4249                 struct i40e_mac_filter *f;
4250                 struct ether_addr *mac;
4251
4252                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4253                             "macvlan filter");
4254                 /* It needs to add the permanent mac into mac list */
4255                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4256                 if (f == NULL) {
4257                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4258                         return I40E_ERR_NO_MEMORY;
4259                 }
4260                 mac = &f->mac_info.mac_addr;
4261                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4262                                 ETH_ADDR_LEN);
4263                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4264                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4265                 vsi->mac_num++;
4266
4267                 return ret;
4268         }
4269         (void)rte_memcpy(&filter.mac_addr,
4270                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4271         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4272         return i40e_vsi_add_mac(vsi, &filter);
4273 }
4274
4275 /*
4276  * i40e_vsi_get_bw_config - Query VSI BW Information
4277  * @vsi: the VSI to be queried
4278  *
4279  * Returns 0 on success, negative value on failure
4280  */
4281 static enum i40e_status_code
4282 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4283 {
4284         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4285         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4286         struct i40e_hw *hw = &vsi->adapter->hw;
4287         i40e_status ret;
4288         int i;
4289         uint32_t bw_max;
4290
4291         memset(&bw_config, 0, sizeof(bw_config));
4292         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4293         if (ret != I40E_SUCCESS) {
4294                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4295                             hw->aq.asq_last_status);
4296                 return ret;
4297         }
4298
4299         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4300         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4301                                         &ets_sla_config, NULL);
4302         if (ret != I40E_SUCCESS) {
4303                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4304                             "configuration %u", hw->aq.asq_last_status);
4305                 return ret;
4306         }
4307
4308         /* store and print out BW info */
4309         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4310         vsi->bw_info.bw_max = bw_config.max_bw;
4311         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4312         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4313         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4314                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4315                      I40E_16_BIT_WIDTH);
4316         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4317                 vsi->bw_info.bw_ets_share_credits[i] =
4318                                 ets_sla_config.share_credits[i];
4319                 vsi->bw_info.bw_ets_credits[i] =
4320                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4321                 /* 4 bits per TC, 4th bit is reserved */
4322                 vsi->bw_info.bw_ets_max[i] =
4323                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4324                                   RTE_LEN2MASK(3, uint8_t));
4325                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4326                             vsi->bw_info.bw_ets_share_credits[i]);
4327                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4328                             vsi->bw_info.bw_ets_credits[i]);
4329                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4330                             vsi->bw_info.bw_ets_max[i]);
4331         }
4332
4333         return I40E_SUCCESS;
4334 }
4335
4336 /* i40e_enable_pf_lb
4337  * @pf: pointer to the pf structure
4338  *
4339  * allow loopback on pf
4340  */
4341 static inline void
4342 i40e_enable_pf_lb(struct i40e_pf *pf)
4343 {
4344         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4345         struct i40e_vsi_context ctxt;
4346         int ret;
4347
4348         /* Use the FW API if FW >= v5.0 */
4349         if (hw->aq.fw_maj_ver < 5) {
4350                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4351                 return;
4352         }
4353
4354         memset(&ctxt, 0, sizeof(ctxt));
4355         ctxt.seid = pf->main_vsi_seid;
4356         ctxt.pf_num = hw->pf_id;
4357         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4358         if (ret) {
4359                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4360                             ret, hw->aq.asq_last_status);
4361                 return;
4362         }
4363         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4364         ctxt.info.valid_sections =
4365                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4366         ctxt.info.switch_id |=
4367                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4368
4369         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4370         if (ret)
4371                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4372                             hw->aq.asq_last_status);
4373 }
4374
4375 /* Setup a VSI */
4376 struct i40e_vsi *
4377 i40e_vsi_setup(struct i40e_pf *pf,
4378                enum i40e_vsi_type type,
4379                struct i40e_vsi *uplink_vsi,
4380                uint16_t user_param)
4381 {
4382         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4383         struct i40e_vsi *vsi;
4384         struct i40e_mac_filter_info filter;
4385         int ret;
4386         struct i40e_vsi_context ctxt;
4387         struct ether_addr broadcast =
4388                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4389
4390         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4391             uplink_vsi == NULL) {
4392                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4393                             "VSI link shouldn't be NULL");
4394                 return NULL;
4395         }
4396
4397         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4398                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4399                             "uplink VSI should be NULL");
4400                 return NULL;
4401         }
4402
4403         /* two situations
4404          * 1.type is not MAIN and uplink vsi is not NULL
4405          * If uplink vsi didn't setup VEB, create one first under veb field
4406          * 2.type is SRIOV and the uplink is NULL
4407          * If floating VEB is NULL, create one veb under floating veb field
4408          */
4409
4410         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4411             uplink_vsi->veb == NULL) {
4412                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4413
4414                 if (uplink_vsi->veb == NULL) {
4415                         PMD_DRV_LOG(ERR, "VEB setup failed");
4416                         return NULL;
4417                 }
4418                 /* set ALLOWLOOPBACk on pf, when veb is created */
4419                 i40e_enable_pf_lb(pf);
4420         }
4421
4422         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4423             pf->main_vsi->floating_veb == NULL) {
4424                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4425
4426                 if (pf->main_vsi->floating_veb == NULL) {
4427                         PMD_DRV_LOG(ERR, "VEB setup failed");
4428                         return NULL;
4429                 }
4430         }
4431
4432         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4433         if (!vsi) {
4434                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4435                 return NULL;
4436         }
4437         TAILQ_INIT(&vsi->mac_list);
4438         vsi->type = type;
4439         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4440         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4441         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4442         vsi->user_param = user_param;
4443         /* Allocate queues */
4444         switch (vsi->type) {
4445         case I40E_VSI_MAIN  :
4446                 vsi->nb_qps = pf->lan_nb_qps;
4447                 break;
4448         case I40E_VSI_SRIOV :
4449                 vsi->nb_qps = pf->vf_nb_qps;
4450                 break;
4451         case I40E_VSI_VMDQ2:
4452                 vsi->nb_qps = pf->vmdq_nb_qps;
4453                 break;
4454         case I40E_VSI_FDIR:
4455                 vsi->nb_qps = pf->fdir_nb_qps;
4456                 break;
4457         default:
4458                 goto fail_mem;
4459         }
4460         /*
4461          * The filter status descriptor is reported in rx queue 0,
4462          * while the tx queue for fdir filter programming has no
4463          * such constraints, can be non-zero queues.
4464          * To simplify it, choose FDIR vsi use queue 0 pair.
4465          * To make sure it will use queue 0 pair, queue allocation
4466          * need be done before this function is called
4467          */
4468         if (type != I40E_VSI_FDIR) {
4469                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4470                         if (ret < 0) {
4471                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4472                                                 vsi->seid, ret);
4473                                 goto fail_mem;
4474                         }
4475                         vsi->base_queue = ret;
4476         } else
4477                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4478
4479         /* VF has MSIX interrupt in VF range, don't allocate here */
4480         if (type == I40E_VSI_MAIN) {
4481                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4482                                           RTE_MIN(vsi->nb_qps,
4483                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4484                 if (ret < 0) {
4485                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4486                                     vsi->seid, ret);
4487                         goto fail_queue_alloc;
4488                 }
4489                 vsi->msix_intr = ret;
4490                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4491         } else if (type != I40E_VSI_SRIOV) {
4492                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4493                 if (ret < 0) {
4494                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4495                         goto fail_queue_alloc;
4496                 }
4497                 vsi->msix_intr = ret;
4498                 vsi->nb_msix = 1;
4499         } else {
4500                 vsi->msix_intr = 0;
4501                 vsi->nb_msix = 0;
4502         }
4503
4504         /* Add VSI */
4505         if (type == I40E_VSI_MAIN) {
4506                 /* For main VSI, no need to add since it's default one */
4507                 vsi->uplink_seid = pf->mac_seid;
4508                 vsi->seid = pf->main_vsi_seid;
4509                 /* Bind queues with specific MSIX interrupt */
4510                 /**
4511                  * Needs 2 interrupt at least, one for misc cause which will
4512                  * enabled from OS side, Another for queues binding the
4513                  * interrupt from device side only.
4514                  */
4515
4516                 /* Get default VSI parameters from hardware */
4517                 memset(&ctxt, 0, sizeof(ctxt));
4518                 ctxt.seid = vsi->seid;
4519                 ctxt.pf_num = hw->pf_id;
4520                 ctxt.uplink_seid = vsi->uplink_seid;
4521                 ctxt.vf_num = 0;
4522                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4523                 if (ret != I40E_SUCCESS) {
4524                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4525                         goto fail_msix_alloc;
4526                 }
4527                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4528                         sizeof(struct i40e_aqc_vsi_properties_data));
4529                 vsi->vsi_id = ctxt.vsi_number;
4530                 vsi->info.valid_sections = 0;
4531
4532                 /* Configure tc, enabled TC0 only */
4533                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4534                         I40E_SUCCESS) {
4535                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4536                         goto fail_msix_alloc;
4537                 }
4538
4539                 /* TC, queue mapping */
4540                 memset(&ctxt, 0, sizeof(ctxt));
4541                 vsi->info.valid_sections |=
4542                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4543                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4544                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4545                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4546                         sizeof(struct i40e_aqc_vsi_properties_data));
4547                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4548                                                 I40E_DEFAULT_TCMAP);
4549                 if (ret != I40E_SUCCESS) {
4550                         PMD_DRV_LOG(ERR, "Failed to configure "
4551                                     "TC queue mapping");
4552                         goto fail_msix_alloc;
4553                 }
4554                 ctxt.seid = vsi->seid;
4555                 ctxt.pf_num = hw->pf_id;
4556                 ctxt.uplink_seid = vsi->uplink_seid;
4557                 ctxt.vf_num = 0;
4558
4559                 /* Update VSI parameters */
4560                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4561                 if (ret != I40E_SUCCESS) {
4562                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4563                         goto fail_msix_alloc;
4564                 }
4565
4566                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4567                                                 sizeof(vsi->info.tc_mapping));
4568                 (void)rte_memcpy(&vsi->info.queue_mapping,
4569                                 &ctxt.info.queue_mapping,
4570                         sizeof(vsi->info.queue_mapping));
4571                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4572                 vsi->info.valid_sections = 0;
4573
4574                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4575                                 ETH_ADDR_LEN);
4576
4577                 /**
4578                  * Updating default filter settings are necessary to prevent
4579                  * reception of tagged packets.
4580                  * Some old firmware configurations load a default macvlan
4581                  * filter which accepts both tagged and untagged packets.
4582                  * The updating is to use a normal filter instead if needed.
4583                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4584                  * The firmware with correct configurations load the default
4585                  * macvlan filter which is expected and cannot be removed.
4586                  */
4587                 i40e_update_default_filter_setting(vsi);
4588                 i40e_config_qinq(hw, vsi);
4589         } else if (type == I40E_VSI_SRIOV) {
4590                 memset(&ctxt, 0, sizeof(ctxt));
4591                 /**
4592                  * For other VSI, the uplink_seid equals to uplink VSI's
4593                  * uplink_seid since they share same VEB
4594                  */
4595                 if (uplink_vsi == NULL)
4596                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4597                 else
4598                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4599                 ctxt.pf_num = hw->pf_id;
4600                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4601                 ctxt.uplink_seid = vsi->uplink_seid;
4602                 ctxt.connection_type = 0x1;
4603                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4604
4605                 /* Use the VEB configuration if FW >= v5.0 */
4606                 if (hw->aq.fw_maj_ver >= 5) {
4607                         /* Configure switch ID */
4608                         ctxt.info.valid_sections |=
4609                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4610                         ctxt.info.switch_id =
4611                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4612                 }
4613
4614                 /* Configure port/vlan */
4615                 ctxt.info.valid_sections |=
4616                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4617                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4618                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4619                                                 I40E_DEFAULT_TCMAP);
4620                 if (ret != I40E_SUCCESS) {
4621                         PMD_DRV_LOG(ERR, "Failed to configure "
4622                                     "TC queue mapping");
4623                         goto fail_msix_alloc;
4624                 }
4625                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4626                 ctxt.info.valid_sections |=
4627                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4628                 /**
4629                  * Since VSI is not created yet, only configure parameter,
4630                  * will add vsi below.
4631                  */
4632
4633                 i40e_config_qinq(hw, vsi);
4634         } else if (type == I40E_VSI_VMDQ2) {
4635                 memset(&ctxt, 0, sizeof(ctxt));
4636                 /*
4637                  * For other VSI, the uplink_seid equals to uplink VSI's
4638                  * uplink_seid since they share same VEB
4639                  */
4640                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4641                 ctxt.pf_num = hw->pf_id;
4642                 ctxt.vf_num = 0;
4643                 ctxt.uplink_seid = vsi->uplink_seid;
4644                 ctxt.connection_type = 0x1;
4645                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4646
4647                 ctxt.info.valid_sections |=
4648                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4649                 /* user_param carries flag to enable loop back */
4650                 if (user_param) {
4651                         ctxt.info.switch_id =
4652                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4653                         ctxt.info.switch_id |=
4654                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4655                 }
4656
4657                 /* Configure port/vlan */
4658                 ctxt.info.valid_sections |=
4659                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4660                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4661                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4662                                                 I40E_DEFAULT_TCMAP);
4663                 if (ret != I40E_SUCCESS) {
4664                         PMD_DRV_LOG(ERR, "Failed to configure "
4665                                         "TC queue mapping");
4666                         goto fail_msix_alloc;
4667                 }
4668                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4669                 ctxt.info.valid_sections |=
4670                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4671         } else if (type == I40E_VSI_FDIR) {
4672                 memset(&ctxt, 0, sizeof(ctxt));
4673                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4674                 ctxt.pf_num = hw->pf_id;
4675                 ctxt.vf_num = 0;
4676                 ctxt.uplink_seid = vsi->uplink_seid;
4677                 ctxt.connection_type = 0x1;     /* regular data port */
4678                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4679                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4680                                                 I40E_DEFAULT_TCMAP);
4681                 if (ret != I40E_SUCCESS) {
4682                         PMD_DRV_LOG(ERR, "Failed to configure "
4683                                         "TC queue mapping.");
4684                         goto fail_msix_alloc;
4685                 }
4686                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4687                 ctxt.info.valid_sections |=
4688                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4689         } else {
4690                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4691                 goto fail_msix_alloc;
4692         }
4693
4694         if (vsi->type != I40E_VSI_MAIN) {
4695                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4696                 if (ret != I40E_SUCCESS) {
4697                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4698                                     hw->aq.asq_last_status);
4699                         goto fail_msix_alloc;
4700                 }
4701                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4702                 vsi->info.valid_sections = 0;
4703                 vsi->seid = ctxt.seid;
4704                 vsi->vsi_id = ctxt.vsi_number;
4705                 vsi->sib_vsi_list.vsi = vsi;
4706                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4707                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4708                                           &vsi->sib_vsi_list, list);
4709                 } else {
4710                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4711                                           &vsi->sib_vsi_list, list);
4712                 }
4713         }
4714
4715         /* MAC/VLAN configuration */
4716         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4717         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4718
4719         ret = i40e_vsi_add_mac(vsi, &filter);
4720         if (ret != I40E_SUCCESS) {
4721                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4722                 goto fail_msix_alloc;
4723         }
4724
4725         /* Get VSI BW information */
4726         i40e_vsi_get_bw_config(vsi);
4727         return vsi;
4728 fail_msix_alloc:
4729         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4730 fail_queue_alloc:
4731         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4732 fail_mem:
4733         rte_free(vsi);
4734         return NULL;
4735 }
4736
4737 /* Configure vlan filter on or off */
4738 int
4739 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4740 {
4741         int i, num;
4742         struct i40e_mac_filter *f;
4743         void *temp;
4744         struct i40e_mac_filter_info *mac_filter;
4745         enum rte_mac_filter_type desired_filter;
4746         int ret = I40E_SUCCESS;
4747
4748         if (on) {
4749                 /* Filter to match MAC and VLAN */
4750                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4751         } else {
4752                 /* Filter to match only MAC */
4753                 desired_filter = RTE_MAC_PERFECT_MATCH;
4754         }
4755
4756         num = vsi->mac_num;
4757
4758         mac_filter = rte_zmalloc("mac_filter_info_data",
4759                                  num * sizeof(*mac_filter), 0);
4760         if (mac_filter == NULL) {
4761                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4762                 return I40E_ERR_NO_MEMORY;
4763         }
4764
4765         i = 0;
4766
4767         /* Remove all existing mac */
4768         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4769                 mac_filter[i] = f->mac_info;
4770                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4771                 if (ret) {
4772                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4773                                     on ? "enable" : "disable");
4774                         goto DONE;
4775                 }
4776                 i++;
4777         }
4778
4779         /* Override with new filter */
4780         for (i = 0; i < num; i++) {
4781                 mac_filter[i].filter_type = desired_filter;
4782                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4783                 if (ret) {
4784                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4785                                     on ? "enable" : "disable");
4786                         goto DONE;
4787                 }
4788         }
4789
4790 DONE:
4791         rte_free(mac_filter);
4792         return ret;
4793 }
4794
4795 /* Configure vlan stripping on or off */
4796 int
4797 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4798 {
4799         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4800         struct i40e_vsi_context ctxt;
4801         uint8_t vlan_flags;
4802         int ret = I40E_SUCCESS;
4803
4804         /* Check if it has been already on or off */
4805         if (vsi->info.valid_sections &
4806                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4807                 if (on) {
4808                         if ((vsi->info.port_vlan_flags &
4809                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4810                                 return 0; /* already on */
4811                 } else {
4812                         if ((vsi->info.port_vlan_flags &
4813                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4814                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4815                                 return 0; /* already off */
4816                 }
4817         }
4818
4819         if (on)
4820                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4821         else
4822                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4823         vsi->info.valid_sections =
4824                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4825         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4826         vsi->info.port_vlan_flags |= vlan_flags;
4827         ctxt.seid = vsi->seid;
4828         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4829         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4830         if (ret)
4831                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4832                             on ? "enable" : "disable");
4833
4834         return ret;
4835 }
4836
4837 static int
4838 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4839 {
4840         struct rte_eth_dev_data *data = dev->data;
4841         int ret;
4842         int mask = 0;
4843
4844         /* Apply vlan offload setting */
4845         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4846         i40e_vlan_offload_set(dev, mask);
4847
4848         /* Apply double-vlan setting, not implemented yet */
4849
4850         /* Apply pvid setting */
4851         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4852                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4853         if (ret)
4854                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4855
4856         return ret;
4857 }
4858
4859 static int
4860 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4861 {
4862         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4863
4864         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4865 }
4866
4867 static int
4868 i40e_update_flow_control(struct i40e_hw *hw)
4869 {
4870 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4871         struct i40e_link_status link_status;
4872         uint32_t rxfc = 0, txfc = 0, reg;
4873         uint8_t an_info;
4874         int ret;
4875
4876         memset(&link_status, 0, sizeof(link_status));
4877         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4878         if (ret != I40E_SUCCESS) {
4879                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4880                 goto write_reg; /* Disable flow control */
4881         }
4882
4883         an_info = hw->phy.link_info.an_info;
4884         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4885                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4886                 ret = I40E_ERR_NOT_READY;
4887                 goto write_reg; /* Disable flow control */
4888         }
4889         /**
4890          * If link auto negotiation is enabled, flow control needs to
4891          * be configured according to it
4892          */
4893         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4894         case I40E_LINK_PAUSE_RXTX:
4895                 rxfc = 1;
4896                 txfc = 1;
4897                 hw->fc.current_mode = I40E_FC_FULL;
4898                 break;
4899         case I40E_AQ_LINK_PAUSE_RX:
4900                 rxfc = 1;
4901                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4902                 break;
4903         case I40E_AQ_LINK_PAUSE_TX:
4904                 txfc = 1;
4905                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4906                 break;
4907         default:
4908                 hw->fc.current_mode = I40E_FC_NONE;
4909                 break;
4910         }
4911
4912 write_reg:
4913         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4914                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4915         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4916         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4917         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4918         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4919
4920         return ret;
4921 }
4922
4923 /* PF setup */
4924 static int
4925 i40e_pf_setup(struct i40e_pf *pf)
4926 {
4927         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4928         struct i40e_filter_control_settings settings;
4929         struct i40e_vsi *vsi;
4930         int ret;
4931
4932         /* Clear all stats counters */
4933         pf->offset_loaded = FALSE;
4934         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4935         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4936
4937         ret = i40e_pf_get_switch_config(pf);
4938         if (ret != I40E_SUCCESS) {
4939                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4940                 return ret;
4941         }
4942         if (pf->flags & I40E_FLAG_FDIR) {
4943                 /* make queue allocated first, let FDIR use queue pair 0*/
4944                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4945                 if (ret != I40E_FDIR_QUEUE_ID) {
4946                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4947                                     " ret =%d", ret);
4948                         pf->flags &= ~I40E_FLAG_FDIR;
4949                 }
4950         }
4951         /*  main VSI setup */
4952         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4953         if (!vsi) {
4954                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4955                 return I40E_ERR_NOT_READY;
4956         }
4957         pf->main_vsi = vsi;
4958
4959         /* Configure filter control */
4960         memset(&settings, 0, sizeof(settings));
4961         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4962                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4963         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4964                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4965         else {
4966                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4967                                                 hw->func_caps.rss_table_size);
4968                 return I40E_ERR_PARAM;
4969         }
4970         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4971                         "size: %u\n", hw->func_caps.rss_table_size);
4972         pf->hash_lut_size = hw->func_caps.rss_table_size;
4973
4974         /* Enable ethtype and macvlan filters */
4975         settings.enable_ethtype = TRUE;
4976         settings.enable_macvlan = TRUE;
4977         ret = i40e_set_filter_control(hw, &settings);
4978         if (ret)
4979                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4980                                                                 ret);
4981
4982         /* Update flow control according to the auto negotiation */
4983         i40e_update_flow_control(hw);
4984
4985         return I40E_SUCCESS;
4986 }
4987
4988 int
4989 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4990 {
4991         uint32_t reg;
4992         uint16_t j;
4993
4994         /**
4995          * Set or clear TX Queue Disable flags,
4996          * which is required by hardware.
4997          */
4998         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4999         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5000
5001         /* Wait until the request is finished */
5002         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5003                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5004                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5005                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5006                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5007                                                         & 0x1))) {
5008                         break;
5009                 }
5010         }
5011         if (on) {
5012                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5013                         return I40E_SUCCESS; /* already on, skip next steps */
5014
5015                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5016                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5017         } else {
5018                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5019                         return I40E_SUCCESS; /* already off, skip next steps */
5020                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5021         }
5022         /* Write the register */
5023         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5024         /* Check the result */
5025         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5026                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5027                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5028                 if (on) {
5029                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5030                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5031                                 break;
5032                 } else {
5033                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5034                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5035                                 break;
5036                 }
5037         }
5038         /* Check if it is timeout */
5039         if (j >= I40E_CHK_Q_ENA_COUNT) {
5040                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5041                             (on ? "enable" : "disable"), q_idx);
5042                 return I40E_ERR_TIMEOUT;
5043         }
5044
5045         return I40E_SUCCESS;
5046 }
5047
5048 /* Swith on or off the tx queues */
5049 static int
5050 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5051 {
5052         struct rte_eth_dev_data *dev_data = pf->dev_data;
5053         struct i40e_tx_queue *txq;
5054         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5055         uint16_t i;
5056         int ret;
5057
5058         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5059                 txq = dev_data->tx_queues[i];
5060                 /* Don't operate the queue if not configured or
5061                  * if starting only per queue */
5062                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5063                         continue;
5064                 if (on)
5065                         ret = i40e_dev_tx_queue_start(dev, i);
5066                 else
5067                         ret = i40e_dev_tx_queue_stop(dev, i);
5068                 if ( ret != I40E_SUCCESS)
5069                         return ret;
5070         }
5071
5072         return I40E_SUCCESS;
5073 }
5074
5075 int
5076 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5077 {
5078         uint32_t reg;
5079         uint16_t j;
5080
5081         /* Wait until the request is finished */
5082         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5083                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5084                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5085                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5086                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5087                         break;
5088         }
5089
5090         if (on) {
5091                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5092                         return I40E_SUCCESS; /* Already on, skip next steps */
5093                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5094         } else {
5095                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5096                         return I40E_SUCCESS; /* Already off, skip next steps */
5097                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5098         }
5099
5100         /* Write the register */
5101         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5102         /* Check the result */
5103         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5104                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5105                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5106                 if (on) {
5107                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5108                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5109                                 break;
5110                 } else {
5111                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5112                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5113                                 break;
5114                 }
5115         }
5116
5117         /* Check if it is timeout */
5118         if (j >= I40E_CHK_Q_ENA_COUNT) {
5119                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5120                             (on ? "enable" : "disable"), q_idx);
5121                 return I40E_ERR_TIMEOUT;
5122         }
5123
5124         return I40E_SUCCESS;
5125 }
5126 /* Switch on or off the rx queues */
5127 static int
5128 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5129 {
5130         struct rte_eth_dev_data *dev_data = pf->dev_data;
5131         struct i40e_rx_queue *rxq;
5132         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5133         uint16_t i;
5134         int ret;
5135
5136         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5137                 rxq = dev_data->rx_queues[i];
5138                 /* Don't operate the queue if not configured or
5139                  * if starting only per queue */
5140                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5141                         continue;
5142                 if (on)
5143                         ret = i40e_dev_rx_queue_start(dev, i);
5144                 else
5145                         ret = i40e_dev_rx_queue_stop(dev, i);
5146                 if (ret != I40E_SUCCESS)
5147                         return ret;
5148         }
5149
5150         return I40E_SUCCESS;
5151 }
5152
5153 /* Switch on or off all the rx/tx queues */
5154 int
5155 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5156 {
5157         int ret;
5158
5159         if (on) {
5160                 /* enable rx queues before enabling tx queues */
5161                 ret = i40e_dev_switch_rx_queues(pf, on);
5162                 if (ret) {
5163                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5164                         return ret;
5165                 }
5166                 ret = i40e_dev_switch_tx_queues(pf, on);
5167         } else {
5168                 /* Stop tx queues before stopping rx queues */
5169                 ret = i40e_dev_switch_tx_queues(pf, on);
5170                 if (ret) {
5171                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5172                         return ret;
5173                 }
5174                 ret = i40e_dev_switch_rx_queues(pf, on);
5175         }
5176
5177         return ret;
5178 }
5179
5180 /* Initialize VSI for TX */
5181 static int
5182 i40e_dev_tx_init(struct i40e_pf *pf)
5183 {
5184         struct rte_eth_dev_data *data = pf->dev_data;
5185         uint16_t i;
5186         uint32_t ret = I40E_SUCCESS;
5187         struct i40e_tx_queue *txq;
5188
5189         for (i = 0; i < data->nb_tx_queues; i++) {
5190                 txq = data->tx_queues[i];
5191                 if (!txq || !txq->q_set)
5192                         continue;
5193                 ret = i40e_tx_queue_init(txq);
5194                 if (ret != I40E_SUCCESS)
5195                         break;
5196         }
5197         if (ret == I40E_SUCCESS)
5198                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5199                                      ->eth_dev);
5200
5201         return ret;
5202 }
5203
5204 /* Initialize VSI for RX */
5205 static int
5206 i40e_dev_rx_init(struct i40e_pf *pf)
5207 {
5208         struct rte_eth_dev_data *data = pf->dev_data;
5209         int ret = I40E_SUCCESS;
5210         uint16_t i;
5211         struct i40e_rx_queue *rxq;
5212
5213         i40e_pf_config_mq_rx(pf);
5214         for (i = 0; i < data->nb_rx_queues; i++) {
5215                 rxq = data->rx_queues[i];
5216                 if (!rxq || !rxq->q_set)
5217                         continue;
5218
5219                 ret = i40e_rx_queue_init(rxq);
5220                 if (ret != I40E_SUCCESS) {
5221                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5222                                     "initialization");
5223                         break;
5224                 }
5225         }
5226         if (ret == I40E_SUCCESS)
5227                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5228                                      ->eth_dev);
5229
5230         return ret;
5231 }
5232
5233 static int
5234 i40e_dev_rxtx_init(struct i40e_pf *pf)
5235 {
5236         int err;
5237
5238         err = i40e_dev_tx_init(pf);
5239         if (err) {
5240                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5241                 return err;
5242         }
5243         err = i40e_dev_rx_init(pf);
5244         if (err) {
5245                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5246                 return err;
5247         }
5248
5249         return err;
5250 }
5251
5252 static int
5253 i40e_vmdq_setup(struct rte_eth_dev *dev)
5254 {
5255         struct rte_eth_conf *conf = &dev->data->dev_conf;
5256         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5257         int i, err, conf_vsis, j, loop;
5258         struct i40e_vsi *vsi;
5259         struct i40e_vmdq_info *vmdq_info;
5260         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5261         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5262
5263         /*
5264          * Disable interrupt to avoid message from VF. Furthermore, it will
5265          * avoid race condition in VSI creation/destroy.
5266          */
5267         i40e_pf_disable_irq0(hw);
5268
5269         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5270                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5271                 return -ENOTSUP;
5272         }
5273
5274         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5275         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5276                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5277                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5278                         pf->max_nb_vmdq_vsi);
5279                 return -ENOTSUP;
5280         }
5281
5282         if (pf->vmdq != NULL) {
5283                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5284                 return 0;
5285         }
5286
5287         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5288                                 sizeof(*vmdq_info) * conf_vsis, 0);
5289
5290         if (pf->vmdq == NULL) {
5291                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5292                 return -ENOMEM;
5293         }
5294
5295         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5296
5297         /* Create VMDQ VSI */
5298         for (i = 0; i < conf_vsis; i++) {
5299                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5300                                 vmdq_conf->enable_loop_back);
5301                 if (vsi == NULL) {
5302                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5303                         err = -1;
5304                         goto err_vsi_setup;
5305                 }
5306                 vmdq_info = &pf->vmdq[i];
5307                 vmdq_info->pf = pf;
5308                 vmdq_info->vsi = vsi;
5309         }
5310         pf->nb_cfg_vmdq_vsi = conf_vsis;
5311
5312         /* Configure Vlan */
5313         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5314         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5315                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5316                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5317                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5318                                         vmdq_conf->pool_map[i].vlan_id, j);
5319
5320                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5321                                                 vmdq_conf->pool_map[i].vlan_id);
5322                                 if (err) {
5323                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5324                                         err = -1;
5325                                         goto err_vsi_setup;
5326                                 }
5327                         }
5328                 }
5329         }
5330
5331         i40e_pf_enable_irq0(hw);
5332
5333         return 0;
5334
5335 err_vsi_setup:
5336         for (i = 0; i < conf_vsis; i++)
5337                 if (pf->vmdq[i].vsi == NULL)
5338                         break;
5339                 else
5340                         i40e_vsi_release(pf->vmdq[i].vsi);
5341
5342         rte_free(pf->vmdq);
5343         pf->vmdq = NULL;
5344         i40e_pf_enable_irq0(hw);
5345         return err;
5346 }
5347
5348 static void
5349 i40e_stat_update_32(struct i40e_hw *hw,
5350                    uint32_t reg,
5351                    bool offset_loaded,
5352                    uint64_t *offset,
5353                    uint64_t *stat)
5354 {
5355         uint64_t new_data;
5356
5357         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5358         if (!offset_loaded)
5359                 *offset = new_data;
5360
5361         if (new_data >= *offset)
5362                 *stat = (uint64_t)(new_data - *offset);
5363         else
5364                 *stat = (uint64_t)((new_data +
5365                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5366 }
5367
5368 static void
5369 i40e_stat_update_48(struct i40e_hw *hw,
5370                    uint32_t hireg,
5371                    uint32_t loreg,
5372                    bool offset_loaded,
5373                    uint64_t *offset,
5374                    uint64_t *stat)
5375 {
5376         uint64_t new_data;
5377
5378         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5379         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5380                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5381
5382         if (!offset_loaded)
5383                 *offset = new_data;
5384
5385         if (new_data >= *offset)
5386                 *stat = new_data - *offset;
5387         else
5388                 *stat = (uint64_t)((new_data +
5389                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5390
5391         *stat &= I40E_48_BIT_MASK;
5392 }
5393
5394 /* Disable IRQ0 */
5395 void
5396 i40e_pf_disable_irq0(struct i40e_hw *hw)
5397 {
5398         /* Disable all interrupt types */
5399         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5400         I40E_WRITE_FLUSH(hw);
5401 }
5402
5403 /* Enable IRQ0 */
5404 void
5405 i40e_pf_enable_irq0(struct i40e_hw *hw)
5406 {
5407         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5408                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5409                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5410                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5411         I40E_WRITE_FLUSH(hw);
5412 }
5413
5414 static void
5415 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5416 {
5417         /* read pending request and disable first */
5418         i40e_pf_disable_irq0(hw);
5419         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5420         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5421                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5422
5423         if (no_queue)
5424                 /* Link no queues with irq0 */
5425                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5426                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5427 }
5428
5429 static void
5430 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5431 {
5432         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5433         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5434         int i;
5435         uint16_t abs_vf_id;
5436         uint32_t index, offset, val;
5437
5438         if (!pf->vfs)
5439                 return;
5440         /**
5441          * Try to find which VF trigger a reset, use absolute VF id to access
5442          * since the reg is global register.
5443          */
5444         for (i = 0; i < pf->vf_num; i++) {
5445                 abs_vf_id = hw->func_caps.vf_base_id + i;
5446                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5447                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5448                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5449                 /* VFR event occured */
5450                 if (val & (0x1 << offset)) {
5451                         int ret;
5452
5453                         /* Clear the event first */
5454                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5455                                                         (0x1 << offset));
5456                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5457                         /**
5458                          * Only notify a VF reset event occured,
5459                          * don't trigger another SW reset
5460                          */
5461                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5462                         if (ret != I40E_SUCCESS)
5463                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5464                 }
5465         }
5466 }
5467
5468 static void
5469 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5470 {
5471         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5472         struct i40e_virtchnl_pf_event event;
5473         int i;
5474
5475         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5476         event.event_data.link_event.link_status =
5477                 dev->data->dev_link.link_status;
5478         event.event_data.link_event.link_speed =
5479                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5480
5481         for (i = 0; i < pf->vf_num; i++)
5482                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5483                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5484 }
5485
5486 static void
5487 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5488 {
5489         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5490         struct i40e_arq_event_info info;
5491         uint16_t pending, opcode;
5492         int ret;
5493
5494         info.buf_len = I40E_AQ_BUF_SZ;
5495         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5496         if (!info.msg_buf) {
5497                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5498                 return;
5499         }
5500
5501         pending = 1;
5502         while (pending) {
5503                 ret = i40e_clean_arq_element(hw, &info, &pending);
5504
5505                 if (ret != I40E_SUCCESS) {
5506                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5507                                     "aq_err: %u", hw->aq.asq_last_status);
5508                         break;
5509                 }
5510                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5511
5512                 switch (opcode) {
5513                 case i40e_aqc_opc_send_msg_to_pf:
5514                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5515                         i40e_pf_host_handle_vf_msg(dev,
5516                                         rte_le_to_cpu_16(info.desc.retval),
5517                                         rte_le_to_cpu_32(info.desc.cookie_high),
5518                                         rte_le_to_cpu_32(info.desc.cookie_low),
5519                                         info.msg_buf,
5520                                         info.msg_len);
5521                         break;
5522                 case i40e_aqc_opc_get_link_status:
5523                         ret = i40e_dev_link_update(dev, 0);
5524                         if (!ret) {
5525                                 i40e_notify_all_vfs_link_status(dev);
5526                                 _rte_eth_dev_callback_process(dev,
5527                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5528                         }
5529                         break;
5530                 default:
5531                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5532                                     opcode);
5533                         break;
5534                 }
5535         }
5536         rte_free(info.msg_buf);
5537 }
5538
5539 /**
5540  * Interrupt handler triggered by NIC  for handling
5541  * specific interrupt.
5542  *
5543  * @param handle
5544  *  Pointer to interrupt handle.
5545  * @param param
5546  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5547  *
5548  * @return
5549  *  void
5550  */
5551 static void
5552 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5553                            void *param)
5554 {
5555         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5556         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5557         uint32_t icr0;
5558
5559         /* Disable interrupt */
5560         i40e_pf_disable_irq0(hw);
5561
5562         /* read out interrupt causes */
5563         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5564
5565         /* No interrupt event indicated */
5566         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5567                 PMD_DRV_LOG(INFO, "No interrupt event");
5568                 goto done;
5569         }
5570 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5571         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5572                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5573         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5574                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5575         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5576                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5577         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5578                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5579         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5580                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5581         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5582                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5583         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5584                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5585 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5586
5587         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5588                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5589                 i40e_dev_handle_vfr_event(dev);
5590         }
5591         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5592                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5593                 i40e_dev_handle_aq_msg(dev);
5594         }
5595
5596 done:
5597         /* Enable interrupt */
5598         i40e_pf_enable_irq0(hw);
5599         rte_intr_enable(intr_handle);
5600 }
5601
5602 static int
5603 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5604                          struct i40e_macvlan_filter *filter,
5605                          int total)
5606 {
5607         int ele_num, ele_buff_size;
5608         int num, actual_num, i;
5609         uint16_t flags;
5610         int ret = I40E_SUCCESS;
5611         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5612         struct i40e_aqc_add_macvlan_element_data *req_list;
5613
5614         if (filter == NULL  || total == 0)
5615                 return I40E_ERR_PARAM;
5616         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5617         ele_buff_size = hw->aq.asq_buf_size;
5618
5619         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5620         if (req_list == NULL) {
5621                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5622                 return I40E_ERR_NO_MEMORY;
5623         }
5624
5625         num = 0;
5626         do {
5627                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5628                 memset(req_list, 0, ele_buff_size);
5629
5630                 for (i = 0; i < actual_num; i++) {
5631                         (void)rte_memcpy(req_list[i].mac_addr,
5632                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5633                         req_list[i].vlan_tag =
5634                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5635
5636                         switch (filter[num + i].filter_type) {
5637                         case RTE_MAC_PERFECT_MATCH:
5638                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5639                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5640                                 break;
5641                         case RTE_MACVLAN_PERFECT_MATCH:
5642                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5643                                 break;
5644                         case RTE_MAC_HASH_MATCH:
5645                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5646                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5647                                 break;
5648                         case RTE_MACVLAN_HASH_MATCH:
5649                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5650                                 break;
5651                         default:
5652                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5653                                 ret = I40E_ERR_PARAM;
5654                                 goto DONE;
5655                         }
5656
5657                         req_list[i].queue_number = 0;
5658
5659                         req_list[i].flags = rte_cpu_to_le_16(flags);
5660                 }
5661
5662                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5663                                                 actual_num, NULL);
5664                 if (ret != I40E_SUCCESS) {
5665                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5666                         goto DONE;
5667                 }
5668                 num += actual_num;
5669         } while (num < total);
5670
5671 DONE:
5672         rte_free(req_list);
5673         return ret;
5674 }
5675
5676 static int
5677 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5678                             struct i40e_macvlan_filter *filter,
5679                             int total)
5680 {
5681         int ele_num, ele_buff_size;
5682         int num, actual_num, i;
5683         uint16_t flags;
5684         int ret = I40E_SUCCESS;
5685         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5686         struct i40e_aqc_remove_macvlan_element_data *req_list;
5687
5688         if (filter == NULL  || total == 0)
5689                 return I40E_ERR_PARAM;
5690
5691         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5692         ele_buff_size = hw->aq.asq_buf_size;
5693
5694         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5695         if (req_list == NULL) {
5696                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5697                 return I40E_ERR_NO_MEMORY;
5698         }
5699
5700         num = 0;
5701         do {
5702                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5703                 memset(req_list, 0, ele_buff_size);
5704
5705                 for (i = 0; i < actual_num; i++) {
5706                         (void)rte_memcpy(req_list[i].mac_addr,
5707                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5708                         req_list[i].vlan_tag =
5709                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5710
5711                         switch (filter[num + i].filter_type) {
5712                         case RTE_MAC_PERFECT_MATCH:
5713                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5714                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5715                                 break;
5716                         case RTE_MACVLAN_PERFECT_MATCH:
5717                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5718                                 break;
5719                         case RTE_MAC_HASH_MATCH:
5720                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5721                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5722                                 break;
5723                         case RTE_MACVLAN_HASH_MATCH:
5724                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5725                                 break;
5726                         default:
5727                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5728                                 ret = I40E_ERR_PARAM;
5729                                 goto DONE;
5730                         }
5731                         req_list[i].flags = rte_cpu_to_le_16(flags);
5732                 }
5733
5734                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5735                                                 actual_num, NULL);
5736                 if (ret != I40E_SUCCESS) {
5737                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5738                         goto DONE;
5739                 }
5740                 num += actual_num;
5741         } while (num < total);
5742
5743 DONE:
5744         rte_free(req_list);
5745         return ret;
5746 }
5747
5748 /* Find out specific MAC filter */
5749 static struct i40e_mac_filter *
5750 i40e_find_mac_filter(struct i40e_vsi *vsi,
5751                          struct ether_addr *macaddr)
5752 {
5753         struct i40e_mac_filter *f;
5754
5755         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5756                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5757                         return f;
5758         }
5759
5760         return NULL;
5761 }
5762
5763 static bool
5764 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5765                          uint16_t vlan_id)
5766 {
5767         uint32_t vid_idx, vid_bit;
5768
5769         if (vlan_id > ETH_VLAN_ID_MAX)
5770                 return 0;
5771
5772         vid_idx = I40E_VFTA_IDX(vlan_id);
5773         vid_bit = I40E_VFTA_BIT(vlan_id);
5774
5775         if (vsi->vfta[vid_idx] & vid_bit)
5776                 return 1;
5777         else
5778                 return 0;
5779 }
5780
5781 static void
5782 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5783                          uint16_t vlan_id, bool on)
5784 {
5785         uint32_t vid_idx, vid_bit;
5786
5787         if (vlan_id > ETH_VLAN_ID_MAX)
5788                 return;
5789
5790         vid_idx = I40E_VFTA_IDX(vlan_id);
5791         vid_bit = I40E_VFTA_BIT(vlan_id);
5792
5793         if (on)
5794                 vsi->vfta[vid_idx] |= vid_bit;
5795         else
5796                 vsi->vfta[vid_idx] &= ~vid_bit;
5797 }
5798
5799 /**
5800  * Find all vlan options for specific mac addr,
5801  * return with actual vlan found.
5802  */
5803 static inline int
5804 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5805                            struct i40e_macvlan_filter *mv_f,
5806                            int num, struct ether_addr *addr)
5807 {
5808         int i;
5809         uint32_t j, k;
5810
5811         /**
5812          * Not to use i40e_find_vlan_filter to decrease the loop time,
5813          * although the code looks complex.
5814           */
5815         if (num < vsi->vlan_num)
5816                 return I40E_ERR_PARAM;
5817
5818         i = 0;
5819         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5820                 if (vsi->vfta[j]) {
5821                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5822                                 if (vsi->vfta[j] & (1 << k)) {
5823                                         if (i > num - 1) {
5824                                                 PMD_DRV_LOG(ERR, "vlan number "
5825                                                             "not match");
5826                                                 return I40E_ERR_PARAM;
5827                                         }
5828                                         (void)rte_memcpy(&mv_f[i].macaddr,
5829                                                         addr, ETH_ADDR_LEN);
5830                                         mv_f[i].vlan_id =
5831                                                 j * I40E_UINT32_BIT_SIZE + k;
5832                                         i++;
5833                                 }
5834                         }
5835                 }
5836         }
5837         return I40E_SUCCESS;
5838 }
5839
5840 static inline int
5841 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5842                            struct i40e_macvlan_filter *mv_f,
5843                            int num,
5844                            uint16_t vlan)
5845 {
5846         int i = 0;
5847         struct i40e_mac_filter *f;
5848
5849         if (num < vsi->mac_num)
5850                 return I40E_ERR_PARAM;
5851
5852         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5853                 if (i > num - 1) {
5854                         PMD_DRV_LOG(ERR, "buffer number not match");
5855                         return I40E_ERR_PARAM;
5856                 }
5857                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5858                                 ETH_ADDR_LEN);
5859                 mv_f[i].vlan_id = vlan;
5860                 mv_f[i].filter_type = f->mac_info.filter_type;
5861                 i++;
5862         }
5863
5864         return I40E_SUCCESS;
5865 }
5866
5867 static int
5868 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5869 {
5870         int i, num;
5871         struct i40e_mac_filter *f;
5872         struct i40e_macvlan_filter *mv_f;
5873         int ret = I40E_SUCCESS;
5874
5875         if (vsi == NULL || vsi->mac_num == 0)
5876                 return I40E_ERR_PARAM;
5877
5878         /* Case that no vlan is set */
5879         if (vsi->vlan_num == 0)
5880                 num = vsi->mac_num;
5881         else
5882                 num = vsi->mac_num * vsi->vlan_num;
5883
5884         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5885         if (mv_f == NULL) {
5886                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5887                 return I40E_ERR_NO_MEMORY;
5888         }
5889
5890         i = 0;
5891         if (vsi->vlan_num == 0) {
5892                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5893                         (void)rte_memcpy(&mv_f[i].macaddr,
5894                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5895                         mv_f[i].vlan_id = 0;
5896                         i++;
5897                 }
5898         } else {
5899                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5900                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5901                                         vsi->vlan_num, &f->mac_info.mac_addr);
5902                         if (ret != I40E_SUCCESS)
5903                                 goto DONE;
5904                         i += vsi->vlan_num;
5905                 }
5906         }
5907
5908         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5909 DONE:
5910         rte_free(mv_f);
5911
5912         return ret;
5913 }
5914
5915 int
5916 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5917 {
5918         struct i40e_macvlan_filter *mv_f;
5919         int mac_num;
5920         int ret = I40E_SUCCESS;
5921
5922         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5923                 return I40E_ERR_PARAM;
5924
5925         /* If it's already set, just return */
5926         if (i40e_find_vlan_filter(vsi,vlan))
5927                 return I40E_SUCCESS;
5928
5929         mac_num = vsi->mac_num;
5930
5931         if (mac_num == 0) {
5932                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5933                 return I40E_ERR_PARAM;
5934         }
5935
5936         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5937
5938         if (mv_f == NULL) {
5939                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5940                 return I40E_ERR_NO_MEMORY;
5941         }
5942
5943         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5944
5945         if (ret != I40E_SUCCESS)
5946                 goto DONE;
5947
5948         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5949
5950         if (ret != I40E_SUCCESS)
5951                 goto DONE;
5952
5953         i40e_set_vlan_filter(vsi, vlan, 1);
5954
5955         vsi->vlan_num++;
5956         ret = I40E_SUCCESS;
5957 DONE:
5958         rte_free(mv_f);
5959         return ret;
5960 }
5961
5962 int
5963 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5964 {
5965         struct i40e_macvlan_filter *mv_f;
5966         int mac_num;
5967         int ret = I40E_SUCCESS;
5968
5969         /**
5970          * Vlan 0 is the generic filter for untagged packets
5971          * and can't be removed.
5972          */
5973         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5974                 return I40E_ERR_PARAM;
5975
5976         /* If can't find it, just return */
5977         if (!i40e_find_vlan_filter(vsi, vlan))
5978                 return I40E_ERR_PARAM;
5979
5980         mac_num = vsi->mac_num;
5981
5982         if (mac_num == 0) {
5983                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5984                 return I40E_ERR_PARAM;
5985         }
5986
5987         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5988
5989         if (mv_f == NULL) {
5990                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5991                 return I40E_ERR_NO_MEMORY;
5992         }
5993
5994         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5995
5996         if (ret != I40E_SUCCESS)
5997                 goto DONE;
5998
5999         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6000
6001         if (ret != I40E_SUCCESS)
6002                 goto DONE;
6003
6004         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6005         if (vsi->vlan_num == 1) {
6006                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6007                 if (ret != I40E_SUCCESS)
6008                         goto DONE;
6009
6010                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6011                 if (ret != I40E_SUCCESS)
6012                         goto DONE;
6013         }
6014
6015         i40e_set_vlan_filter(vsi, vlan, 0);
6016
6017         vsi->vlan_num--;
6018         ret = I40E_SUCCESS;
6019 DONE:
6020         rte_free(mv_f);
6021         return ret;
6022 }
6023
6024 int
6025 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6026 {
6027         struct i40e_mac_filter *f;
6028         struct i40e_macvlan_filter *mv_f;
6029         int i, vlan_num = 0;
6030         int ret = I40E_SUCCESS;
6031
6032         /* If it's add and we've config it, return */
6033         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6034         if (f != NULL)
6035                 return I40E_SUCCESS;
6036         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6037                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6038
6039                 /**
6040                  * If vlan_num is 0, that's the first time to add mac,
6041                  * set mask for vlan_id 0.
6042                  */
6043                 if (vsi->vlan_num == 0) {
6044                         i40e_set_vlan_filter(vsi, 0, 1);
6045                         vsi->vlan_num = 1;
6046                 }
6047                 vlan_num = vsi->vlan_num;
6048         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6049                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6050                 vlan_num = 1;
6051
6052         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6053         if (mv_f == NULL) {
6054                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6055                 return I40E_ERR_NO_MEMORY;
6056         }
6057
6058         for (i = 0; i < vlan_num; i++) {
6059                 mv_f[i].filter_type = mac_filter->filter_type;
6060                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6061                                 ETH_ADDR_LEN);
6062         }
6063
6064         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6065                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6066                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6067                                         &mac_filter->mac_addr);
6068                 if (ret != I40E_SUCCESS)
6069                         goto DONE;
6070         }
6071
6072         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6073         if (ret != I40E_SUCCESS)
6074                 goto DONE;
6075
6076         /* Add the mac addr into mac list */
6077         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6078         if (f == NULL) {
6079                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6080                 ret = I40E_ERR_NO_MEMORY;
6081                 goto DONE;
6082         }
6083         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6084                         ETH_ADDR_LEN);
6085         f->mac_info.filter_type = mac_filter->filter_type;
6086         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6087         vsi->mac_num++;
6088
6089         ret = I40E_SUCCESS;
6090 DONE:
6091         rte_free(mv_f);
6092
6093         return ret;
6094 }
6095
6096 int
6097 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6098 {
6099         struct i40e_mac_filter *f;
6100         struct i40e_macvlan_filter *mv_f;
6101         int i, vlan_num;
6102         enum rte_mac_filter_type filter_type;
6103         int ret = I40E_SUCCESS;
6104
6105         /* Can't find it, return an error */
6106         f = i40e_find_mac_filter(vsi, addr);
6107         if (f == NULL)
6108                 return I40E_ERR_PARAM;
6109
6110         vlan_num = vsi->vlan_num;
6111         filter_type = f->mac_info.filter_type;
6112         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6113                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6114                 if (vlan_num == 0) {
6115                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6116                         return I40E_ERR_PARAM;
6117                 }
6118         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6119                         filter_type == RTE_MAC_HASH_MATCH)
6120                 vlan_num = 1;
6121
6122         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6123         if (mv_f == NULL) {
6124                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6125                 return I40E_ERR_NO_MEMORY;
6126         }
6127
6128         for (i = 0; i < vlan_num; i++) {
6129                 mv_f[i].filter_type = filter_type;
6130                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6131                                 ETH_ADDR_LEN);
6132         }
6133         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6134                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6135                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6136                 if (ret != I40E_SUCCESS)
6137                         goto DONE;
6138         }
6139
6140         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6141         if (ret != I40E_SUCCESS)
6142                 goto DONE;
6143
6144         /* Remove the mac addr into mac list */
6145         TAILQ_REMOVE(&vsi->mac_list, f, next);
6146         rte_free(f);
6147         vsi->mac_num--;
6148
6149         ret = I40E_SUCCESS;
6150 DONE:
6151         rte_free(mv_f);
6152         return ret;
6153 }
6154
6155 /* Configure hash enable flags for RSS */
6156 uint64_t
6157 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6158 {
6159         uint64_t hena = 0;
6160
6161         if (!flags)
6162                 return hena;
6163
6164         if (flags & ETH_RSS_FRAG_IPV4)
6165                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6166         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6167                 if (type == I40E_MAC_X722) {
6168                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6169                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6170                 } else
6171                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6172         }
6173         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6174                 if (type == I40E_MAC_X722) {
6175                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6176                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6177                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6178                 } else
6179                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6180         }
6181         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6182                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6183         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6184                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6185         if (flags & ETH_RSS_FRAG_IPV6)
6186                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6187         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6188                 if (type == I40E_MAC_X722) {
6189                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6190                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6191                 } else
6192                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6193         }
6194         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6195                 if (type == I40E_MAC_X722) {
6196                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6197                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6198                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6199                 } else
6200                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6201         }
6202         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6203                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6204         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6205                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6206         if (flags & ETH_RSS_L2_PAYLOAD)
6207                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6208
6209         return hena;
6210 }
6211
6212 /* Parse the hash enable flags */
6213 uint64_t
6214 i40e_parse_hena(uint64_t flags)
6215 {
6216         uint64_t rss_hf = 0;
6217
6218         if (!flags)
6219                 return rss_hf;
6220         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6221                 rss_hf |= ETH_RSS_FRAG_IPV4;
6222         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6223                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6224 #ifdef X722_SUPPORT
6225         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6226                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6227 #endif
6228         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6229                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6230 #ifdef X722_SUPPORT
6231         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6232                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6233         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6234                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6235 #endif
6236         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6237                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6238         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6239                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6240         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6241                 rss_hf |= ETH_RSS_FRAG_IPV6;
6242         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6243                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6244 #ifdef X722_SUPPORT
6245         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6246                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6247 #endif
6248         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6249                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6250 #ifdef X722_SUPPORT
6251         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6252                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6253         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6254                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6255 #endif
6256         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6257                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6258         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6259                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6260         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6261                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6262
6263         return rss_hf;
6264 }
6265
6266 /* Disable RSS */
6267 static void
6268 i40e_pf_disable_rss(struct i40e_pf *pf)
6269 {
6270         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6271         uint64_t hena;
6272
6273         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6274         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6275         if (hw->mac.type == I40E_MAC_X722)
6276                 hena &= ~I40E_RSS_HENA_ALL_X722;
6277         else
6278                 hena &= ~I40E_RSS_HENA_ALL;
6279         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6280         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6281         I40E_WRITE_FLUSH(hw);
6282 }
6283
6284 static int
6285 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6286 {
6287         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6288         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6289         int ret = 0;
6290
6291         if (!key || key_len == 0) {
6292                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6293                 return 0;
6294         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6295                 sizeof(uint32_t)) {
6296                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6297                 return -EINVAL;
6298         }
6299
6300         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6301                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6302                         (struct i40e_aqc_get_set_rss_key_data *)key;
6303
6304                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6305                 if (ret)
6306                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6307                                      "via AQ");
6308         } else {
6309                 uint32_t *hash_key = (uint32_t *)key;
6310                 uint16_t i;
6311
6312                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6313                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6314                 I40E_WRITE_FLUSH(hw);
6315         }
6316
6317         return ret;
6318 }
6319
6320 static int
6321 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6322 {
6323         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6324         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6325         int ret;
6326
6327         if (!key || !key_len)
6328                 return -EINVAL;
6329
6330         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6331                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6332                         (struct i40e_aqc_get_set_rss_key_data *)key);
6333                 if (ret) {
6334                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6335                         return ret;
6336                 }
6337         } else {
6338                 uint32_t *key_dw = (uint32_t *)key;
6339                 uint16_t i;
6340
6341                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6342                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6343         }
6344         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6345
6346         return 0;
6347 }
6348
6349 static int
6350 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6351 {
6352         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6353         uint64_t rss_hf;
6354         uint64_t hena;
6355         int ret;
6356
6357         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6358                                rss_conf->rss_key_len);
6359         if (ret)
6360                 return ret;
6361
6362         rss_hf = rss_conf->rss_hf;
6363         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6364         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6365         if (hw->mac.type == I40E_MAC_X722)
6366                 hena &= ~I40E_RSS_HENA_ALL_X722;
6367         else
6368                 hena &= ~I40E_RSS_HENA_ALL;
6369         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6370         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6371         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6372         I40E_WRITE_FLUSH(hw);
6373
6374         return 0;
6375 }
6376
6377 static int
6378 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6379                          struct rte_eth_rss_conf *rss_conf)
6380 {
6381         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6382         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6383         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6384         uint64_t hena;
6385
6386         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6387         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6388         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6389                  ? I40E_RSS_HENA_ALL_X722
6390                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6391                 if (rss_hf != 0) /* Enable RSS */
6392                         return -EINVAL;
6393                 return 0; /* Nothing to do */
6394         }
6395         /* RSS enabled */
6396         if (rss_hf == 0) /* Disable RSS */
6397                 return -EINVAL;
6398
6399         return i40e_hw_rss_hash_set(pf, rss_conf);
6400 }
6401
6402 static int
6403 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6404                            struct rte_eth_rss_conf *rss_conf)
6405 {
6406         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6407         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6408         uint64_t hena;
6409
6410         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6411                          &rss_conf->rss_key_len);
6412
6413         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6414         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6415         rss_conf->rss_hf = i40e_parse_hena(hena);
6416
6417         return 0;
6418 }
6419
6420 static int
6421 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6422 {
6423         switch (filter_type) {
6424         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6425                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6426                 break;
6427         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6428                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6429                 break;
6430         case RTE_TUNNEL_FILTER_IMAC_TENID:
6431                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6432                 break;
6433         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6434                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6435                 break;
6436         case ETH_TUNNEL_FILTER_IMAC:
6437                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6438                 break;
6439         case ETH_TUNNEL_FILTER_OIP:
6440                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6441                 break;
6442         case ETH_TUNNEL_FILTER_IIP:
6443                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6444                 break;
6445         default:
6446                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6447                 return -EINVAL;
6448         }
6449
6450         return 0;
6451 }
6452
6453 static int
6454 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6455                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6456                         uint8_t add)
6457 {
6458         uint16_t ip_type;
6459         uint32_t ipv4_addr;
6460         uint8_t i, tun_type = 0;
6461         /* internal varialbe to convert ipv6 byte order */
6462         uint32_t convert_ipv6[4];
6463         int val, ret = 0;
6464         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6465         struct i40e_vsi *vsi = pf->main_vsi;
6466         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6467         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6468
6469         cld_filter = rte_zmalloc("tunnel_filter",
6470                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6471                 0);
6472
6473         if (NULL == cld_filter) {
6474                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6475                 return -EINVAL;
6476         }
6477         pfilter = cld_filter;
6478
6479         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6480         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6481
6482         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6483         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6484                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6485                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6486                 rte_memcpy(&pfilter->ipaddr.v4.data,
6487                                 &rte_cpu_to_le_32(ipv4_addr),
6488                                 sizeof(pfilter->ipaddr.v4.data));
6489         } else {
6490                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6491                 for (i = 0; i < 4; i++) {
6492                         convert_ipv6[i] =
6493                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6494                 }
6495                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6496                                 sizeof(pfilter->ipaddr.v6.data));
6497         }
6498
6499         /* check tunneled type */
6500         switch (tunnel_filter->tunnel_type) {
6501         case RTE_TUNNEL_TYPE_VXLAN:
6502                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6503                 break;
6504         case RTE_TUNNEL_TYPE_NVGRE:
6505                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6506                 break;
6507         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6508                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6509                 break;
6510         default:
6511                 /* Other tunnel types is not supported. */
6512                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6513                 rte_free(cld_filter);
6514                 return -EINVAL;
6515         }
6516
6517         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6518                                                 &pfilter->flags);
6519         if (val < 0) {
6520                 rte_free(cld_filter);
6521                 return -EINVAL;
6522         }
6523
6524         pfilter->flags |= rte_cpu_to_le_16(
6525                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6526                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6527         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6528         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6529
6530         if (add)
6531                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6532         else
6533                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6534                                                 cld_filter, 1);
6535
6536         rte_free(cld_filter);
6537         return ret;
6538 }
6539
6540 static int
6541 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6542 {
6543         uint8_t i;
6544
6545         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6546                 if (pf->vxlan_ports[i] == port)
6547                         return i;
6548         }
6549
6550         return -1;
6551 }
6552
6553 static int
6554 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6555 {
6556         int  idx, ret;
6557         uint8_t filter_idx;
6558         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6559
6560         idx = i40e_get_vxlan_port_idx(pf, port);
6561
6562         /* Check if port already exists */
6563         if (idx >= 0) {
6564                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6565                 return -EINVAL;
6566         }
6567
6568         /* Now check if there is space to add the new port */
6569         idx = i40e_get_vxlan_port_idx(pf, 0);
6570         if (idx < 0) {
6571                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6572                         "not adding port %d", port);
6573                 return -ENOSPC;
6574         }
6575
6576         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6577                                         &filter_idx, NULL);
6578         if (ret < 0) {
6579                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6580                 return -1;
6581         }
6582
6583         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6584                          port,  filter_idx);
6585
6586         /* New port: add it and mark its index in the bitmap */
6587         pf->vxlan_ports[idx] = port;
6588         pf->vxlan_bitmap |= (1 << idx);
6589
6590         if (!(pf->flags & I40E_FLAG_VXLAN))
6591                 pf->flags |= I40E_FLAG_VXLAN;
6592
6593         return 0;
6594 }
6595
6596 static int
6597 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6598 {
6599         int idx;
6600         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6601
6602         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6603                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6604                 return -EINVAL;
6605         }
6606
6607         idx = i40e_get_vxlan_port_idx(pf, port);
6608
6609         if (idx < 0) {
6610                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6611                 return -EINVAL;
6612         }
6613
6614         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6615                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6616                 return -1;
6617         }
6618
6619         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6620                         port, idx);
6621
6622         pf->vxlan_ports[idx] = 0;
6623         pf->vxlan_bitmap &= ~(1 << idx);
6624
6625         if (!pf->vxlan_bitmap)
6626                 pf->flags &= ~I40E_FLAG_VXLAN;
6627
6628         return 0;
6629 }
6630
6631 /* Add UDP tunneling port */
6632 static int
6633 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6634                              struct rte_eth_udp_tunnel *udp_tunnel)
6635 {
6636         int ret = 0;
6637         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6638
6639         if (udp_tunnel == NULL)
6640                 return -EINVAL;
6641
6642         switch (udp_tunnel->prot_type) {
6643         case RTE_TUNNEL_TYPE_VXLAN:
6644                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6645                 break;
6646
6647         case RTE_TUNNEL_TYPE_GENEVE:
6648         case RTE_TUNNEL_TYPE_TEREDO:
6649                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6650                 ret = -1;
6651                 break;
6652
6653         default:
6654                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6655                 ret = -1;
6656                 break;
6657         }
6658
6659         return ret;
6660 }
6661
6662 /* Remove UDP tunneling port */
6663 static int
6664 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6665                              struct rte_eth_udp_tunnel *udp_tunnel)
6666 {
6667         int ret = 0;
6668         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6669
6670         if (udp_tunnel == NULL)
6671                 return -EINVAL;
6672
6673         switch (udp_tunnel->prot_type) {
6674         case RTE_TUNNEL_TYPE_VXLAN:
6675                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6676                 break;
6677         case RTE_TUNNEL_TYPE_GENEVE:
6678         case RTE_TUNNEL_TYPE_TEREDO:
6679                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6680                 ret = -1;
6681                 break;
6682         default:
6683                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6684                 ret = -1;
6685                 break;
6686         }
6687
6688         return ret;
6689 }
6690
6691 /* Calculate the maximum number of contiguous PF queues that are configured */
6692 static int
6693 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6694 {
6695         struct rte_eth_dev_data *data = pf->dev_data;
6696         int i, num;
6697         struct i40e_rx_queue *rxq;
6698
6699         num = 0;
6700         for (i = 0; i < pf->lan_nb_qps; i++) {
6701                 rxq = data->rx_queues[i];
6702                 if (rxq && rxq->q_set)
6703                         num++;
6704                 else
6705                         break;
6706         }
6707
6708         return num;
6709 }
6710
6711 /* Configure RSS */
6712 static int
6713 i40e_pf_config_rss(struct i40e_pf *pf)
6714 {
6715         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6716         struct rte_eth_rss_conf rss_conf;
6717         uint32_t i, lut = 0;
6718         uint16_t j, num;
6719
6720         /*
6721          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6722          * It's necessary to calulate the actual PF queues that are configured.
6723          */
6724         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6725                 num = i40e_pf_calc_configured_queues_num(pf);
6726         else
6727                 num = pf->dev_data->nb_rx_queues;
6728
6729         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6730         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6731                         num);
6732
6733         if (num == 0) {
6734                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6735                 return -ENOTSUP;
6736         }
6737
6738         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6739                 if (j == num)
6740                         j = 0;
6741                 lut = (lut << 8) | (j & ((0x1 <<
6742                         hw->func_caps.rss_table_entry_width) - 1));
6743                 if ((i & 3) == 3)
6744                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6745         }
6746
6747         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6748         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6749                 i40e_pf_disable_rss(pf);
6750                 return 0;
6751         }
6752         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6753                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6754                 /* Random default keys */
6755                 static uint32_t rss_key_default[] = {0x6b793944,
6756                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6757                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6758                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6759
6760                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6761                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6762                                                         sizeof(uint32_t);
6763         }
6764
6765         return i40e_hw_rss_hash_set(pf, &rss_conf);
6766 }
6767
6768 static int
6769 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6770                                struct rte_eth_tunnel_filter_conf *filter)
6771 {
6772         if (pf == NULL || filter == NULL) {
6773                 PMD_DRV_LOG(ERR, "Invalid parameter");
6774                 return -EINVAL;
6775         }
6776
6777         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6778                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6779                 return -EINVAL;
6780         }
6781
6782         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6783                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6784                 return -EINVAL;
6785         }
6786
6787         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6788                 (is_zero_ether_addr(&filter->outer_mac))) {
6789                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6790                 return -EINVAL;
6791         }
6792
6793         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6794                 (is_zero_ether_addr(&filter->inner_mac))) {
6795                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6796                 return -EINVAL;
6797         }
6798
6799         return 0;
6800 }
6801
6802 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6803 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6804 static int
6805 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6806 {
6807         uint32_t val, reg;
6808         int ret = -EINVAL;
6809
6810         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6811         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6812
6813         if (len == 3) {
6814                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6815         } else if (len == 4) {
6816                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6817         } else {
6818                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6819                 return ret;
6820         }
6821
6822         if (reg != val) {
6823                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6824                                                    reg, NULL);
6825                 if (ret != 0)
6826                         return ret;
6827         } else {
6828                 ret = 0;
6829         }
6830         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6831                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6832
6833         return ret;
6834 }
6835
6836 static int
6837 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6838 {
6839         int ret = -EINVAL;
6840
6841         if (!hw || !cfg)
6842                 return -EINVAL;
6843
6844         switch (cfg->cfg_type) {
6845         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6846                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6847                 break;
6848         default:
6849                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6850                 break;
6851         }
6852
6853         return ret;
6854 }
6855
6856 static int
6857 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6858                                enum rte_filter_op filter_op,
6859                                void *arg)
6860 {
6861         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6862         int ret = I40E_ERR_PARAM;
6863
6864         switch (filter_op) {
6865         case RTE_ETH_FILTER_SET:
6866                 ret = i40e_dev_global_config_set(hw,
6867                         (struct rte_eth_global_cfg *)arg);
6868                 break;
6869         default:
6870                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6871                 break;
6872         }
6873
6874         return ret;
6875 }
6876
6877 static int
6878 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6879                           enum rte_filter_op filter_op,
6880                           void *arg)
6881 {
6882         struct rte_eth_tunnel_filter_conf *filter;
6883         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6884         int ret = I40E_SUCCESS;
6885
6886         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6887
6888         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6889                 return I40E_ERR_PARAM;
6890
6891         switch (filter_op) {
6892         case RTE_ETH_FILTER_NOP:
6893                 if (!(pf->flags & I40E_FLAG_VXLAN))
6894                         ret = I40E_NOT_SUPPORTED;
6895                 break;
6896         case RTE_ETH_FILTER_ADD:
6897                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6898                 break;
6899         case RTE_ETH_FILTER_DELETE:
6900                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6901                 break;
6902         default:
6903                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6904                 ret = I40E_ERR_PARAM;
6905                 break;
6906         }
6907
6908         return ret;
6909 }
6910
6911 static int
6912 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6913 {
6914         int ret = 0;
6915         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6916
6917         /* RSS setup */
6918         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6919                 ret = i40e_pf_config_rss(pf);
6920         else
6921                 i40e_pf_disable_rss(pf);
6922
6923         return ret;
6924 }
6925
6926 /* Get the symmetric hash enable configurations per port */
6927 static void
6928 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6929 {
6930         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6931
6932         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6933 }
6934
6935 /* Set the symmetric hash enable configurations per port */
6936 static void
6937 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6938 {
6939         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6940
6941         if (enable > 0) {
6942                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6943                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6944                                                         "been enabled");
6945                         return;
6946                 }
6947                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6948         } else {
6949                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6950                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6951                                                         "been disabled");
6952                         return;
6953                 }
6954                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6955         }
6956         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6957         I40E_WRITE_FLUSH(hw);
6958 }
6959
6960 /*
6961  * Get global configurations of hash function type and symmetric hash enable
6962  * per flow type (pctype). Note that global configuration means it affects all
6963  * the ports on the same NIC.
6964  */
6965 static int
6966 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6967                                    struct rte_eth_hash_global_conf *g_cfg)
6968 {
6969         uint32_t reg, mask = I40E_FLOW_TYPES;
6970         uint16_t i;
6971         enum i40e_filter_pctype pctype;
6972
6973         memset(g_cfg, 0, sizeof(*g_cfg));
6974         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6975         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6976                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6977         else
6978                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6979         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6980                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6981
6982         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6983                 if (!(mask & (1UL << i)))
6984                         continue;
6985                 mask &= ~(1UL << i);
6986                 /* Bit set indicats the coresponding flow type is supported */
6987                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6988                 /* if flowtype is invalid, continue */
6989                 if (!I40E_VALID_FLOW(i))
6990                         continue;
6991                 pctype = i40e_flowtype_to_pctype(i);
6992                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6993                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6994                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6995         }
6996
6997         return 0;
6998 }
6999
7000 static int
7001 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7002 {
7003         uint32_t i;
7004         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7005
7006         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7007                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7008                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7009                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7010                                                 g_cfg->hash_func);
7011                 return -EINVAL;
7012         }
7013
7014         /*
7015          * As i40e supports less than 32 flow types, only first 32 bits need to
7016          * be checked.
7017          */
7018         mask0 = g_cfg->valid_bit_mask[0];
7019         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7020                 if (i == 0) {
7021                         /* Check if any unsupported flow type configured */
7022                         if ((mask0 | i40e_mask) ^ i40e_mask)
7023                                 goto mask_err;
7024                 } else {
7025                         if (g_cfg->valid_bit_mask[i])
7026                                 goto mask_err;
7027                 }
7028         }
7029
7030         return 0;
7031
7032 mask_err:
7033         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7034
7035         return -EINVAL;
7036 }
7037
7038 /*
7039  * Set global configurations of hash function type and symmetric hash enable
7040  * per flow type (pctype). Note any modifying global configuration will affect
7041  * all the ports on the same NIC.
7042  */
7043 static int
7044 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7045                                    struct rte_eth_hash_global_conf *g_cfg)
7046 {
7047         int ret;
7048         uint16_t i;
7049         uint32_t reg;
7050         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7051         enum i40e_filter_pctype pctype;
7052
7053         /* Check the input parameters */
7054         ret = i40e_hash_global_config_check(g_cfg);
7055         if (ret < 0)
7056                 return ret;
7057
7058         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7059                 if (!(mask0 & (1UL << i)))
7060                         continue;
7061                 mask0 &= ~(1UL << i);
7062                 /* if flowtype is invalid, continue */
7063                 if (!I40E_VALID_FLOW(i))
7064                         continue;
7065                 pctype = i40e_flowtype_to_pctype(i);
7066                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7067                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7068                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7069         }
7070
7071         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7072         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7073                 /* Toeplitz */
7074                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7075                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7076                                                                 "Toeplitz");
7077                         goto out;
7078                 }
7079                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7080         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7081                 /* Simple XOR */
7082                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7083                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7084                                                         "Simple XOR");
7085                         goto out;
7086                 }
7087                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7088         } else
7089                 /* Use the default, and keep it as it is */
7090                 goto out;
7091
7092         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7093
7094 out:
7095         I40E_WRITE_FLUSH(hw);
7096
7097         return 0;
7098 }
7099
7100 /**
7101  * Valid input sets for hash and flow director filters per PCTYPE
7102  */
7103 static uint64_t
7104 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7105                 enum rte_filter_type filter)
7106 {
7107         uint64_t valid;
7108
7109         static const uint64_t valid_hash_inset_table[] = {
7110                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7111                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7112                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7113                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7114                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7115                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7116                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7117                         I40E_INSET_FLEX_PAYLOAD,
7118                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7119                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7120                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7121                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7122                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7123                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7124                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7125                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7126                         I40E_INSET_FLEX_PAYLOAD,
7127 #ifdef X722_SUPPORT
7128                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7129                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7130                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7131                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7132                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7133                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7134                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7135                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7136                         I40E_INSET_FLEX_PAYLOAD,
7137                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7138                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7139                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7140                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7141                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7142                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7143                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7144                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7145                         I40E_INSET_FLEX_PAYLOAD,
7146 #endif
7147                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7148                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7149                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7150                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7151                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7152                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7153                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7154                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7155                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7156 #ifdef X722_SUPPORT
7157                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7158                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7159                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7160                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7161                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7162                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7163                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7164                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7165                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7166 #endif
7167                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7168                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7169                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7170                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7171                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7172                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7173                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7174                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7175                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7176                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7177                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7178                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7179                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7180                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7181                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7182                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7183                         I40E_INSET_FLEX_PAYLOAD,
7184                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7185                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7186                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7187                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7188                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7189                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7190                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7191                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7192                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7193                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7194                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7195                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7196                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7197                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7198                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7199                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7200 #ifdef X722_SUPPORT
7201                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7202                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7203                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7204                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7205                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7206                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7207                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7208                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7209                         I40E_INSET_FLEX_PAYLOAD,
7210                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7211                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7212                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7213                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7214                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7215                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7216                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7217                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7218                         I40E_INSET_FLEX_PAYLOAD,
7219 #endif
7220                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7221                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7222                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7223                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7224                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7225                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7226                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7227                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7228                         I40E_INSET_FLEX_PAYLOAD,
7229 #ifdef X722_SUPPORT
7230                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7231                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7232                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7233                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7234                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7235                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7236                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7237                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7238                         I40E_INSET_FLEX_PAYLOAD,
7239 #endif
7240                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7241                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7242                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7243                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7244                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7245                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7246                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7247                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7248                         I40E_INSET_FLEX_PAYLOAD,
7249                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7250                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7251                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7252                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7253                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7254                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7255                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7256                         I40E_INSET_FLEX_PAYLOAD,
7257                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7258                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7259                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7260                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7261                         I40E_INSET_FLEX_PAYLOAD,
7262         };
7263
7264         /**
7265          * Flow director supports only fields defined in
7266          * union rte_eth_fdir_flow.
7267          */
7268         static const uint64_t valid_fdir_inset_table[] = {
7269                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7270                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7271                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7272                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7273                 I40E_INSET_IPV4_TTL,
7274                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7275                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7276                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7277                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7278                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7279 #ifdef X722_SUPPORT
7280                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7281                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7282                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7283                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7284                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7285                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7286                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7287                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7288                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7289                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7290 #endif
7291                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7292                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7293                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7294                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7295                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7296 #ifdef X722_SUPPORT
7297                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7298                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7299                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7300                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7301                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7302 #endif
7303                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7304                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7305                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7306                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7307                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7308                 I40E_INSET_SCTP_VT,
7309                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7310                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7311                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7312                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7313                 I40E_INSET_IPV4_TTL,
7314                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7315                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7316                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7317                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7318                 I40E_INSET_IPV6_HOP_LIMIT,
7319                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7320                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7321                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7322                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7323                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7324 #ifdef X722_SUPPORT
7325                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7326                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7327                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7328                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7329                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7330                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7331                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7332                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7333                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7334                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7335 #endif
7336                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7337                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7338                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7339                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7340                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7341 #ifdef X722_SUPPORT
7342                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7343                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7344                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7345                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7346                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7347 #endif
7348                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7349                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7350                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7351                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7352                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7353                 I40E_INSET_SCTP_VT,
7354                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7355                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7356                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7357                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7358                 I40E_INSET_IPV6_HOP_LIMIT,
7359                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7360                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7361                 I40E_INSET_LAST_ETHER_TYPE,
7362         };
7363
7364         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7365                 return 0;
7366         if (filter == RTE_ETH_FILTER_HASH)
7367                 valid = valid_hash_inset_table[pctype];
7368         else
7369                 valid = valid_fdir_inset_table[pctype];
7370
7371         return valid;
7372 }
7373
7374 /**
7375  * Validate if the input set is allowed for a specific PCTYPE
7376  */
7377 static int
7378 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7379                 enum rte_filter_type filter, uint64_t inset)
7380 {
7381         uint64_t valid;
7382
7383         valid = i40e_get_valid_input_set(pctype, filter);
7384         if (inset & (~valid))
7385                 return -EINVAL;
7386
7387         return 0;
7388 }
7389
7390 /* default input set fields combination per pctype */
7391 static uint64_t
7392 i40e_get_default_input_set(uint16_t pctype)
7393 {
7394         static const uint64_t default_inset_table[] = {
7395                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7396                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7397                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7398                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7399                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7400 #ifdef X722_SUPPORT
7401                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7402                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7403                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7404                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7405                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7406                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7407 #endif
7408                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7409                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7410                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7411 #ifdef X722_SUPPORT
7412                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7413                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7414                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7415 #endif
7416                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7417                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7418                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7419                         I40E_INSET_SCTP_VT,
7420                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7421                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7422                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7423                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7424                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7425                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7426                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7427 #ifdef X722_SUPPORT
7428                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7429                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7430                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7431                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7432                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7433                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7434 #endif
7435                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7436                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7437                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7438 #ifdef X722_SUPPORT
7439                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7440                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7441                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7442 #endif
7443                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7444                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7445                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7446                         I40E_INSET_SCTP_VT,
7447                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7448                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7449                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7450                         I40E_INSET_LAST_ETHER_TYPE,
7451         };
7452
7453         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7454                 return 0;
7455
7456         return default_inset_table[pctype];
7457 }
7458
7459 /**
7460  * Parse the input set from index to logical bit masks
7461  */
7462 static int
7463 i40e_parse_input_set(uint64_t *inset,
7464                      enum i40e_filter_pctype pctype,
7465                      enum rte_eth_input_set_field *field,
7466                      uint16_t size)
7467 {
7468         uint16_t i, j;
7469         int ret = -EINVAL;
7470
7471         static const struct {
7472                 enum rte_eth_input_set_field field;
7473                 uint64_t inset;
7474         } inset_convert_table[] = {
7475                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7476                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7477                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7478                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7479                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7480                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7481                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7482                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7483                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7484                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7485                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7486                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7487                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7488                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7489                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7490                         I40E_INSET_IPV6_NEXT_HDR},
7491                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7492                         I40E_INSET_IPV6_HOP_LIMIT},
7493                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7494                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7495                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7496                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7497                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7498                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7499                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7500                         I40E_INSET_SCTP_VT},
7501                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7502                         I40E_INSET_TUNNEL_DMAC},
7503                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7504                         I40E_INSET_VLAN_TUNNEL},
7505                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7506                         I40E_INSET_TUNNEL_ID},
7507                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7508                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7509                         I40E_INSET_FLEX_PAYLOAD_W1},
7510                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7511                         I40E_INSET_FLEX_PAYLOAD_W2},
7512                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7513                         I40E_INSET_FLEX_PAYLOAD_W3},
7514                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7515                         I40E_INSET_FLEX_PAYLOAD_W4},
7516                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7517                         I40E_INSET_FLEX_PAYLOAD_W5},
7518                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7519                         I40E_INSET_FLEX_PAYLOAD_W6},
7520                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7521                         I40E_INSET_FLEX_PAYLOAD_W7},
7522                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7523                         I40E_INSET_FLEX_PAYLOAD_W8},
7524         };
7525
7526         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7527                 return ret;
7528
7529         /* Only one item allowed for default or all */
7530         if (size == 1) {
7531                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7532                         *inset = i40e_get_default_input_set(pctype);
7533                         return 0;
7534                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7535                         *inset = I40E_INSET_NONE;
7536                         return 0;
7537                 }
7538         }
7539
7540         for (i = 0, *inset = 0; i < size; i++) {
7541                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7542                         if (field[i] == inset_convert_table[j].field) {
7543                                 *inset |= inset_convert_table[j].inset;
7544                                 break;
7545                         }
7546                 }
7547
7548                 /* It contains unsupported input set, return immediately */
7549                 if (j == RTE_DIM(inset_convert_table))
7550                         return ret;
7551         }
7552
7553         return 0;
7554 }
7555
7556 /**
7557  * Translate the input set from bit masks to register aware bit masks
7558  * and vice versa
7559  */
7560 static uint64_t
7561 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7562 {
7563         uint64_t val = 0;
7564         uint16_t i;
7565
7566         struct inset_map {
7567                 uint64_t inset;
7568                 uint64_t inset_reg;
7569         };
7570
7571         static const struct inset_map inset_map_common[] = {
7572                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7573                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7574                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7575                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7576                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7577                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7578                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7579                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7580                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7581                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7582                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7583                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7584                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7585                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7586                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7587                 {I40E_INSET_TUNNEL_DMAC,
7588                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7589                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7590                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7591                 {I40E_INSET_TUNNEL_SRC_PORT,
7592                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7593                 {I40E_INSET_TUNNEL_DST_PORT,
7594                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7595                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7596                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7597                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7598                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7599                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7600                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7601                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7602                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7603                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7604         };
7605
7606     /* some different registers map in x722*/
7607         static const struct inset_map inset_map_diff_x722[] = {
7608                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7609                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7610                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7611                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7612         };
7613
7614         static const struct inset_map inset_map_diff_not_x722[] = {
7615                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7616                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7617                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7618                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7619         };
7620
7621         if (input == 0)
7622                 return val;
7623
7624         /* Translate input set to register aware inset */
7625         if (type == I40E_MAC_X722) {
7626                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7627                         if (input & inset_map_diff_x722[i].inset)
7628                                 val |= inset_map_diff_x722[i].inset_reg;
7629                 }
7630         } else {
7631                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7632                         if (input & inset_map_diff_not_x722[i].inset)
7633                                 val |= inset_map_diff_not_x722[i].inset_reg;
7634                 }
7635         }
7636
7637         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7638                 if (input & inset_map_common[i].inset)
7639                         val |= inset_map_common[i].inset_reg;
7640         }
7641
7642         return val;
7643 }
7644
7645 static int
7646 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7647 {
7648         uint8_t i, idx = 0;
7649         uint64_t inset_need_mask = inset;
7650
7651         static const struct {
7652                 uint64_t inset;
7653                 uint32_t mask;
7654         } inset_mask_map[] = {
7655                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7656                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7657                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7658                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7659                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7660                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7661                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7662                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7663         };
7664
7665         if (!inset || !mask || !nb_elem)
7666                 return 0;
7667
7668         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7669                 /* Clear the inset bit, if no MASK is required,
7670                  * for example proto + ttl
7671                  */
7672                 if ((inset & inset_mask_map[i].inset) ==
7673                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7674                         inset_need_mask &= ~inset_mask_map[i].inset;
7675                 if (!inset_need_mask)
7676                         return 0;
7677         }
7678         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7679                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7680                     inset_mask_map[i].inset) {
7681                         if (idx >= nb_elem) {
7682                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7683                                 return -EINVAL;
7684                         }
7685                         mask[idx] = inset_mask_map[i].mask;
7686                         idx++;
7687                 }
7688         }
7689
7690         return idx;
7691 }
7692
7693 static void
7694 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7695 {
7696         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7697
7698         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7699         if (reg != val)
7700                 i40e_write_rx_ctl(hw, addr, val);
7701         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7702                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7703 }
7704
7705 static void
7706 i40e_filter_input_set_init(struct i40e_pf *pf)
7707 {
7708         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7709         enum i40e_filter_pctype pctype;
7710         uint64_t input_set, inset_reg;
7711         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7712         int num, i;
7713
7714         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7715              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7716                 if (hw->mac.type == I40E_MAC_X722) {
7717                         if (!I40E_VALID_PCTYPE_X722(pctype))
7718                                 continue;
7719                 } else {
7720                         if (!I40E_VALID_PCTYPE(pctype))
7721                                 continue;
7722                 }
7723
7724                 input_set = i40e_get_default_input_set(pctype);
7725
7726                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7727                                                    I40E_INSET_MASK_NUM_REG);
7728                 if (num < 0)
7729                         return;
7730                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
7731                                         input_set);
7732
7733                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7734                                       (uint32_t)(inset_reg & UINT32_MAX));
7735                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7736                                      (uint32_t)((inset_reg >>
7737                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7738                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7739                                       (uint32_t)(inset_reg & UINT32_MAX));
7740                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7741                                      (uint32_t)((inset_reg >>
7742                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7743
7744                 for (i = 0; i < num; i++) {
7745                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7746                                              mask_reg[i]);
7747                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7748                                              mask_reg[i]);
7749                 }
7750                 /*clear unused mask registers of the pctype */
7751                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7752                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7753                                              0);
7754                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7755                                              0);
7756                 }
7757                 I40E_WRITE_FLUSH(hw);
7758
7759                 /* store the default input set */
7760                 pf->hash_input_set[pctype] = input_set;
7761                 pf->fdir.input_set[pctype] = input_set;
7762         }
7763 }
7764
7765 int
7766 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7767                          struct rte_eth_input_set_conf *conf)
7768 {
7769         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7770         enum i40e_filter_pctype pctype;
7771         uint64_t input_set, inset_reg = 0;
7772         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7773         int ret, i, num;
7774
7775         if (!conf) {
7776                 PMD_DRV_LOG(ERR, "Invalid pointer");
7777                 return -EFAULT;
7778         }
7779         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7780             conf->op != RTE_ETH_INPUT_SET_ADD) {
7781                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7782                 return -EINVAL;
7783         }
7784
7785         if (!I40E_VALID_FLOW(conf->flow_type)) {
7786                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7787                 return -EINVAL;
7788         }
7789
7790         if (hw->mac.type == I40E_MAC_X722) {
7791                 /* get translated pctype value in fd pctype register */
7792                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
7793                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
7794                         conf->flow_type)));
7795         } else
7796                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7797
7798         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7799                                    conf->inset_size);
7800         if (ret) {
7801                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7802                 return -EINVAL;
7803         }
7804         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7805                                     input_set) != 0) {
7806                 PMD_DRV_LOG(ERR, "Invalid input set");
7807                 return -EINVAL;
7808         }
7809         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7810                 /* get inset value in register */
7811                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7812                 inset_reg <<= I40E_32_BIT_WIDTH;
7813                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7814                 input_set |= pf->hash_input_set[pctype];
7815         }
7816         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7817                                            I40E_INSET_MASK_NUM_REG);
7818         if (num < 0)
7819                 return -EINVAL;
7820
7821         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7822
7823         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7824                               (uint32_t)(inset_reg & UINT32_MAX));
7825         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7826                              (uint32_t)((inset_reg >>
7827                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7828
7829         for (i = 0; i < num; i++)
7830                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7831                                      mask_reg[i]);
7832         /*clear unused mask registers of the pctype */
7833         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7834                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7835                                      0);
7836         I40E_WRITE_FLUSH(hw);
7837
7838         pf->hash_input_set[pctype] = input_set;
7839         return 0;
7840 }
7841
7842 int
7843 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7844                          struct rte_eth_input_set_conf *conf)
7845 {
7846         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7847         enum i40e_filter_pctype pctype;
7848         uint64_t input_set, inset_reg = 0;
7849         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7850         int ret, i, num;
7851
7852         if (!hw || !conf) {
7853                 PMD_DRV_LOG(ERR, "Invalid pointer");
7854                 return -EFAULT;
7855         }
7856         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7857             conf->op != RTE_ETH_INPUT_SET_ADD) {
7858                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7859                 return -EINVAL;
7860         }
7861
7862         if (!I40E_VALID_FLOW(conf->flow_type)) {
7863                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7864                 return -EINVAL;
7865         }
7866
7867         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7868
7869         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7870                                    conf->inset_size);
7871         if (ret) {
7872                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7873                 return -EINVAL;
7874         }
7875         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7876                                     input_set) != 0) {
7877                 PMD_DRV_LOG(ERR, "Invalid input set");
7878                 return -EINVAL;
7879         }
7880
7881         /* get inset value in register */
7882         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7883         inset_reg <<= I40E_32_BIT_WIDTH;
7884         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7885
7886         /* Can not change the inset reg for flex payload for fdir,
7887          * it is done by writing I40E_PRTQF_FD_FLXINSET
7888          * in i40e_set_flex_mask_on_pctype.
7889          */
7890         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7891                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7892         else
7893                 input_set |= pf->fdir.input_set[pctype];
7894         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7895                                            I40E_INSET_MASK_NUM_REG);
7896         if (num < 0)
7897                 return -EINVAL;
7898
7899         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7900
7901         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7902                               (uint32_t)(inset_reg & UINT32_MAX));
7903         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7904                              (uint32_t)((inset_reg >>
7905                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7906
7907         for (i = 0; i < num; i++)
7908                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7909                                      mask_reg[i]);
7910         /*clear unused mask registers of the pctype */
7911         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7912                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7913                                      0);
7914         I40E_WRITE_FLUSH(hw);
7915
7916         pf->fdir.input_set[pctype] = input_set;
7917         return 0;
7918 }
7919
7920 static int
7921 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7922 {
7923         int ret = 0;
7924
7925         if (!hw || !info) {
7926                 PMD_DRV_LOG(ERR, "Invalid pointer");
7927                 return -EFAULT;
7928         }
7929
7930         switch (info->info_type) {
7931         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7932                 i40e_get_symmetric_hash_enable_per_port(hw,
7933                                         &(info->info.enable));
7934                 break;
7935         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7936                 ret = i40e_get_hash_filter_global_config(hw,
7937                                 &(info->info.global_conf));
7938                 break;
7939         default:
7940                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7941                                                         info->info_type);
7942                 ret = -EINVAL;
7943                 break;
7944         }
7945
7946         return ret;
7947 }
7948
7949 static int
7950 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7951 {
7952         int ret = 0;
7953
7954         if (!hw || !info) {
7955                 PMD_DRV_LOG(ERR, "Invalid pointer");
7956                 return -EFAULT;
7957         }
7958
7959         switch (info->info_type) {
7960         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7961                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7962                 break;
7963         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7964                 ret = i40e_set_hash_filter_global_config(hw,
7965                                 &(info->info.global_conf));
7966                 break;
7967         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7968                 ret = i40e_hash_filter_inset_select(hw,
7969                                                &(info->info.input_set_conf));
7970                 break;
7971
7972         default:
7973                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7974                                                         info->info_type);
7975                 ret = -EINVAL;
7976                 break;
7977         }
7978
7979         return ret;
7980 }
7981
7982 /* Operations for hash function */
7983 static int
7984 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7985                       enum rte_filter_op filter_op,
7986                       void *arg)
7987 {
7988         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7989         int ret = 0;
7990
7991         switch (filter_op) {
7992         case RTE_ETH_FILTER_NOP:
7993                 break;
7994         case RTE_ETH_FILTER_GET:
7995                 ret = i40e_hash_filter_get(hw,
7996                         (struct rte_eth_hash_filter_info *)arg);
7997                 break;
7998         case RTE_ETH_FILTER_SET:
7999                 ret = i40e_hash_filter_set(hw,
8000                         (struct rte_eth_hash_filter_info *)arg);
8001                 break;
8002         default:
8003                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8004                                                                 filter_op);
8005                 ret = -ENOTSUP;
8006                 break;
8007         }
8008
8009         return ret;
8010 }
8011
8012 /*
8013  * Configure ethertype filter, which can director packet by filtering
8014  * with mac address and ether_type or only ether_type
8015  */
8016 static int
8017 i40e_ethertype_filter_set(struct i40e_pf *pf,
8018                         struct rte_eth_ethertype_filter *filter,
8019                         bool add)
8020 {
8021         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8022         struct i40e_control_filter_stats stats;
8023         uint16_t flags = 0;
8024         int ret;
8025
8026         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8027                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8028                 return -EINVAL;
8029         }
8030         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8031                 filter->ether_type == ETHER_TYPE_IPv6) {
8032                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8033                         " control packet filter.", filter->ether_type);
8034                 return -EINVAL;
8035         }
8036         if (filter->ether_type == ETHER_TYPE_VLAN)
8037                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8038                         " not supported.");
8039
8040         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8041                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8042         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8043                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8044         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8045
8046         memset(&stats, 0, sizeof(stats));
8047         ret = i40e_aq_add_rem_control_packet_filter(hw,
8048                         filter->mac_addr.addr_bytes,
8049                         filter->ether_type, flags,
8050                         pf->main_vsi->seid,
8051                         filter->queue, add, &stats, NULL);
8052
8053         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8054                          " mac_etype_used = %u, etype_used = %u,"
8055                          " mac_etype_free = %u, etype_free = %u\n",
8056                          ret, stats.mac_etype_used, stats.etype_used,
8057                          stats.mac_etype_free, stats.etype_free);
8058         if (ret < 0)
8059                 return -ENOSYS;
8060         return 0;
8061 }
8062
8063 /*
8064  * Handle operations for ethertype filter.
8065  */
8066 static int
8067 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8068                                 enum rte_filter_op filter_op,
8069                                 void *arg)
8070 {
8071         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8072         int ret = 0;
8073
8074         if (filter_op == RTE_ETH_FILTER_NOP)
8075                 return ret;
8076
8077         if (arg == NULL) {
8078                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8079                             filter_op);
8080                 return -EINVAL;
8081         }
8082
8083         switch (filter_op) {
8084         case RTE_ETH_FILTER_ADD:
8085                 ret = i40e_ethertype_filter_set(pf,
8086                         (struct rte_eth_ethertype_filter *)arg,
8087                         TRUE);
8088                 break;
8089         case RTE_ETH_FILTER_DELETE:
8090                 ret = i40e_ethertype_filter_set(pf,
8091                         (struct rte_eth_ethertype_filter *)arg,
8092                         FALSE);
8093                 break;
8094         default:
8095                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8096                 ret = -ENOSYS;
8097                 break;
8098         }
8099         return ret;
8100 }
8101
8102 static int
8103 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8104                      enum rte_filter_type filter_type,
8105                      enum rte_filter_op filter_op,
8106                      void *arg)
8107 {
8108         int ret = 0;
8109
8110         if (dev == NULL)
8111                 return -EINVAL;
8112
8113         switch (filter_type) {
8114         case RTE_ETH_FILTER_NONE:
8115                 /* For global configuration */
8116                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8117                 break;
8118         case RTE_ETH_FILTER_HASH:
8119                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8120                 break;
8121         case RTE_ETH_FILTER_MACVLAN:
8122                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8123                 break;
8124         case RTE_ETH_FILTER_ETHERTYPE:
8125                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8126                 break;
8127         case RTE_ETH_FILTER_TUNNEL:
8128                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8129                 break;
8130         case RTE_ETH_FILTER_FDIR:
8131                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8132                 break;
8133         default:
8134                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8135                                                         filter_type);
8136                 ret = -EINVAL;
8137                 break;
8138         }
8139
8140         return ret;
8141 }
8142
8143 /*
8144  * Check and enable Extended Tag.
8145  * Enabling Extended Tag is important for 40G performance.
8146  */
8147 static void
8148 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8149 {
8150         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8151         uint32_t buf = 0;
8152         int ret;
8153
8154         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8155                                       PCI_DEV_CAP_REG);
8156         if (ret < 0) {
8157                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8158                             PCI_DEV_CAP_REG);
8159                 return;
8160         }
8161         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8162                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8163                 return;
8164         }
8165
8166         buf = 0;
8167         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8168                                       PCI_DEV_CTRL_REG);
8169         if (ret < 0) {
8170                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8171                             PCI_DEV_CTRL_REG);
8172                 return;
8173         }
8174         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8175                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8176                 return;
8177         }
8178         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8179         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8180                                        PCI_DEV_CTRL_REG);
8181         if (ret < 0) {
8182                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8183                             PCI_DEV_CTRL_REG);
8184                 return;
8185         }
8186 }
8187
8188 /*
8189  * As some registers wouldn't be reset unless a global hardware reset,
8190  * hardware initialization is needed to put those registers into an
8191  * expected initial state.
8192  */
8193 static void
8194 i40e_hw_init(struct rte_eth_dev *dev)
8195 {
8196         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8197
8198         i40e_enable_extended_tag(dev);
8199
8200         /* clear the PF Queue Filter control register */
8201         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8202
8203         /* Disable symmetric hash per port */
8204         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8205 }
8206
8207 enum i40e_filter_pctype
8208 i40e_flowtype_to_pctype(uint16_t flow_type)
8209 {
8210         static const enum i40e_filter_pctype pctype_table[] = {
8211                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8212                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8213                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8214                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8215                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8216                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8217                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8218                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8219                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8220                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8221                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8222                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8223                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8224                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8225                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8226                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8227                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8228                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8229                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8230         };
8231
8232         return pctype_table[flow_type];
8233 }
8234
8235 uint16_t
8236 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8237 {
8238         static const uint16_t flowtype_table[] = {
8239                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8240                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8241                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8242 #ifdef X722_SUPPORT
8243                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8244                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8245                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8246                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8247 #endif
8248                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8249                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8250 #ifdef X722_SUPPORT
8251                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8252                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8253 #endif
8254                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8255                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8256                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8257                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8258                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8259                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8260                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8261 #ifdef X722_SUPPORT
8262                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8263                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8264                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8265                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8266 #endif
8267                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8268                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8269 #ifdef X722_SUPPORT
8270                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8271                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8272 #endif
8273                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8274                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8275                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8276                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8277                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8278         };
8279
8280         return flowtype_table[pctype];
8281 }
8282
8283 /*
8284  * On X710, performance number is far from the expectation on recent firmware
8285  * versions; on XL710, performance number is also far from the expectation on
8286  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8287  * mode is enabled and port MAC address is equal to the packet destination MAC
8288  * address. The fix for this issue may not be integrated in the following
8289  * firmware version. So the workaround in software driver is needed. It needs
8290  * to modify the initial values of 3 internal only registers for both X710 and
8291  * XL710. Note that the values for X710 or XL710 could be different, and the
8292  * workaround can be removed when it is fixed in firmware in the future.
8293  */
8294
8295 /* For both X710 and XL710 */
8296 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8297 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8298
8299 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8300 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8301
8302 /* For X710 */
8303 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8304 /* For XL710 */
8305 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8306 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8307
8308 static int
8309 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8310 {
8311         enum i40e_status_code status;
8312         struct i40e_aq_get_phy_abilities_resp phy_ab;
8313         int ret = -ENOTSUP;
8314
8315         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8316                                               NULL);
8317
8318         if (status)
8319                 return ret;
8320
8321         return 0;
8322 }
8323
8324
8325 static void
8326 i40e_configure_registers(struct i40e_hw *hw)
8327 {
8328         static struct {
8329                 uint32_t addr;
8330                 uint64_t val;
8331         } reg_table[] = {
8332                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8333                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8334                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8335         };
8336         uint64_t reg;
8337         uint32_t i;
8338         int ret;
8339
8340         for (i = 0; i < RTE_DIM(reg_table); i++) {
8341                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8342                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8343                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8344                                 reg_table[i].val =
8345                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8346                         else /* For X710 */
8347                                 reg_table[i].val =
8348                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8349                 }
8350
8351                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8352                                                         &reg, NULL);
8353                 if (ret < 0) {
8354                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8355                                                         reg_table[i].addr);
8356                         break;
8357                 }
8358                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8359                                                 reg_table[i].addr, reg);
8360                 if (reg == reg_table[i].val)
8361                         continue;
8362
8363                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8364                                                 reg_table[i].val, NULL);
8365                 if (ret < 0) {
8366                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8367                                 "address of 0x%"PRIx32, reg_table[i].val,
8368                                                         reg_table[i].addr);
8369                         break;
8370                 }
8371                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8372                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8373         }
8374 }
8375
8376 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8377 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8378 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8379 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8380 static int
8381 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8382 {
8383         uint32_t reg;
8384         int ret;
8385
8386         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8387                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8388                 return -EINVAL;
8389         }
8390
8391         /* Configure for double VLAN RX stripping */
8392         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8393         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8394                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8395                 ret = i40e_aq_debug_write_register(hw,
8396                                                    I40E_VSI_TSR(vsi->vsi_id),
8397                                                    reg, NULL);
8398                 if (ret < 0) {
8399                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8400                                     vsi->vsi_id);
8401                         return I40E_ERR_CONFIG;
8402                 }
8403         }
8404
8405         /* Configure for double VLAN TX insertion */
8406         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8407         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8408                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8409                 ret = i40e_aq_debug_write_register(hw,
8410                                                    I40E_VSI_L2TAGSTXVALID(
8411                                                    vsi->vsi_id), reg, NULL);
8412                 if (ret < 0) {
8413                         PMD_DRV_LOG(ERR, "Failed to update "
8414                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8415                         return I40E_ERR_CONFIG;
8416                 }
8417         }
8418
8419         return 0;
8420 }
8421
8422 /**
8423  * i40e_aq_add_mirror_rule
8424  * @hw: pointer to the hardware structure
8425  * @seid: VEB seid to add mirror rule to
8426  * @dst_id: destination vsi seid
8427  * @entries: Buffer which contains the entities to be mirrored
8428  * @count: number of entities contained in the buffer
8429  * @rule_id:the rule_id of the rule to be added
8430  *
8431  * Add a mirror rule for a given veb.
8432  *
8433  **/
8434 static enum i40e_status_code
8435 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8436                         uint16_t seid, uint16_t dst_id,
8437                         uint16_t rule_type, uint16_t *entries,
8438                         uint16_t count, uint16_t *rule_id)
8439 {
8440         struct i40e_aq_desc desc;
8441         struct i40e_aqc_add_delete_mirror_rule cmd;
8442         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8443                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8444                 &desc.params.raw;
8445         uint16_t buff_len;
8446         enum i40e_status_code status;
8447
8448         i40e_fill_default_direct_cmd_desc(&desc,
8449                                           i40e_aqc_opc_add_mirror_rule);
8450         memset(&cmd, 0, sizeof(cmd));
8451
8452         buff_len = sizeof(uint16_t) * count;
8453         desc.datalen = rte_cpu_to_le_16(buff_len);
8454         if (buff_len > 0)
8455                 desc.flags |= rte_cpu_to_le_16(
8456                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8457         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8458                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8459         cmd.num_entries = rte_cpu_to_le_16(count);
8460         cmd.seid = rte_cpu_to_le_16(seid);
8461         cmd.destination = rte_cpu_to_le_16(dst_id);
8462
8463         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8464         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8465         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8466                          "rule_id = %u"
8467                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8468                          hw->aq.asq_last_status, resp->rule_id,
8469                          resp->mirror_rules_used, resp->mirror_rules_free);
8470         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8471
8472         return status;
8473 }
8474
8475 /**
8476  * i40e_aq_del_mirror_rule
8477  * @hw: pointer to the hardware structure
8478  * @seid: VEB seid to add mirror rule to
8479  * @entries: Buffer which contains the entities to be mirrored
8480  * @count: number of entities contained in the buffer
8481  * @rule_id:the rule_id of the rule to be delete
8482  *
8483  * Delete a mirror rule for a given veb.
8484  *
8485  **/
8486 static enum i40e_status_code
8487 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8488                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8489                 uint16_t count, uint16_t rule_id)
8490 {
8491         struct i40e_aq_desc desc;
8492         struct i40e_aqc_add_delete_mirror_rule cmd;
8493         uint16_t buff_len = 0;
8494         enum i40e_status_code status;
8495         void *buff = NULL;
8496
8497         i40e_fill_default_direct_cmd_desc(&desc,
8498                                           i40e_aqc_opc_delete_mirror_rule);
8499         memset(&cmd, 0, sizeof(cmd));
8500         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8501                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8502                                                           I40E_AQ_FLAG_RD));
8503                 cmd.num_entries = count;
8504                 buff_len = sizeof(uint16_t) * count;
8505                 desc.datalen = rte_cpu_to_le_16(buff_len);
8506                 buff = (void *)entries;
8507         } else
8508                 /* rule id is filled in destination field for deleting mirror rule */
8509                 cmd.destination = rte_cpu_to_le_16(rule_id);
8510
8511         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8512                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8513         cmd.seid = rte_cpu_to_le_16(seid);
8514
8515         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8516         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8517
8518         return status;
8519 }
8520
8521 /**
8522  * i40e_mirror_rule_set
8523  * @dev: pointer to the hardware structure
8524  * @mirror_conf: mirror rule info
8525  * @sw_id: mirror rule's sw_id
8526  * @on: enable/disable
8527  *
8528  * set a mirror rule.
8529  *
8530  **/
8531 static int
8532 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8533                         struct rte_eth_mirror_conf *mirror_conf,
8534                         uint8_t sw_id, uint8_t on)
8535 {
8536         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8537         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8538         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8539         struct i40e_mirror_rule *parent = NULL;
8540         uint16_t seid, dst_seid, rule_id;
8541         uint16_t i, j = 0;
8542         int ret;
8543
8544         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8545
8546         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8547                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8548                         " without veb or vfs.");
8549                 return -ENOSYS;
8550         }
8551         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8552                 PMD_DRV_LOG(ERR, "mirror table is full.");
8553                 return -ENOSPC;
8554         }
8555         if (mirror_conf->dst_pool > pf->vf_num) {
8556                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8557                                  mirror_conf->dst_pool);
8558                 return -EINVAL;
8559         }
8560
8561         seid = pf->main_vsi->veb->seid;
8562
8563         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8564                 if (sw_id <= it->index) {
8565                         mirr_rule = it;
8566                         break;
8567                 }
8568                 parent = it;
8569         }
8570         if (mirr_rule && sw_id == mirr_rule->index) {
8571                 if (on) {
8572                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8573                         return -EEXIST;
8574                 } else {
8575                         ret = i40e_aq_del_mirror_rule(hw, seid,
8576                                         mirr_rule->rule_type,
8577                                         mirr_rule->entries,
8578                                         mirr_rule->num_entries, mirr_rule->id);
8579                         if (ret < 0) {
8580                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8581                                                    " ret = %d, aq_err = %d.",
8582                                                    ret, hw->aq.asq_last_status);
8583                                 return -ENOSYS;
8584                         }
8585                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8586                         rte_free(mirr_rule);
8587                         pf->nb_mirror_rule--;
8588                         return 0;
8589                 }
8590         } else if (!on) {
8591                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8592                 return -ENOENT;
8593         }
8594
8595         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8596                                 sizeof(struct i40e_mirror_rule) , 0);
8597         if (!mirr_rule) {
8598                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8599                 return I40E_ERR_NO_MEMORY;
8600         }
8601         switch (mirror_conf->rule_type) {
8602         case ETH_MIRROR_VLAN:
8603                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8604                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8605                                 mirr_rule->entries[j] =
8606                                         mirror_conf->vlan.vlan_id[i];
8607                                 j++;
8608                         }
8609                 }
8610                 if (j == 0) {
8611                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8612                         rte_free(mirr_rule);
8613                         return -EINVAL;
8614                 }
8615                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8616                 break;
8617         case ETH_MIRROR_VIRTUAL_POOL_UP:
8618         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8619                 /* check if the specified pool bit is out of range */
8620                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8621                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8622                         rte_free(mirr_rule);
8623                         return -EINVAL;
8624                 }
8625                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8626                         if (mirror_conf->pool_mask & (1ULL << i)) {
8627                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8628                                 j++;
8629                         }
8630                 }
8631                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8632                         /* add pf vsi to entries */
8633                         mirr_rule->entries[j] = pf->main_vsi_seid;
8634                         j++;
8635                 }
8636                 if (j == 0) {
8637                         PMD_DRV_LOG(ERR, "pool is not specified.");
8638                         rte_free(mirr_rule);
8639                         return -EINVAL;
8640                 }
8641                 /* egress and ingress in aq commands means from switch but not port */
8642                 mirr_rule->rule_type =
8643                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8644                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8645                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8646                 break;
8647         case ETH_MIRROR_UPLINK_PORT:
8648                 /* egress and ingress in aq commands means from switch but not port*/
8649                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8650                 break;
8651         case ETH_MIRROR_DOWNLINK_PORT:
8652                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8653                 break;
8654         default:
8655                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8656                         mirror_conf->rule_type);
8657                 rte_free(mirr_rule);
8658                 return -EINVAL;
8659         }
8660
8661         /* If the dst_pool is equal to vf_num, consider it as PF */
8662         if (mirror_conf->dst_pool == pf->vf_num)
8663                 dst_seid = pf->main_vsi_seid;
8664         else
8665                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8666
8667         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8668                                       mirr_rule->rule_type, mirr_rule->entries,
8669                                       j, &rule_id);
8670         if (ret < 0) {
8671                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8672                                    " ret = %d, aq_err = %d.",
8673                                    ret, hw->aq.asq_last_status);
8674                 rte_free(mirr_rule);
8675                 return -ENOSYS;
8676         }
8677
8678         mirr_rule->index = sw_id;
8679         mirr_rule->num_entries = j;
8680         mirr_rule->id = rule_id;
8681         mirr_rule->dst_vsi_seid = dst_seid;
8682
8683         if (parent)
8684                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8685         else
8686                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8687
8688         pf->nb_mirror_rule++;
8689         return 0;
8690 }
8691
8692 /**
8693  * i40e_mirror_rule_reset
8694  * @dev: pointer to the device
8695  * @sw_id: mirror rule's sw_id
8696  *
8697  * reset a mirror rule.
8698  *
8699  **/
8700 static int
8701 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8702 {
8703         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8704         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8705         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8706         uint16_t seid;
8707         int ret;
8708
8709         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8710
8711         seid = pf->main_vsi->veb->seid;
8712
8713         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8714                 if (sw_id == it->index) {
8715                         mirr_rule = it;
8716                         break;
8717                 }
8718         }
8719         if (mirr_rule) {
8720                 ret = i40e_aq_del_mirror_rule(hw, seid,
8721                                 mirr_rule->rule_type,
8722                                 mirr_rule->entries,
8723                                 mirr_rule->num_entries, mirr_rule->id);
8724                 if (ret < 0) {
8725                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8726                                            " status = %d, aq_err = %d.",
8727                                            ret, hw->aq.asq_last_status);
8728                         return -ENOSYS;
8729                 }
8730                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8731                 rte_free(mirr_rule);
8732                 pf->nb_mirror_rule--;
8733         } else {
8734                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8735                 return -ENOENT;
8736         }
8737         return 0;
8738 }
8739
8740 static uint64_t
8741 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8742 {
8743         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8744         uint64_t systim_cycles;
8745
8746         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8747         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8748                         << 32;
8749
8750         return systim_cycles;
8751 }
8752
8753 static uint64_t
8754 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8755 {
8756         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8757         uint64_t rx_tstamp;
8758
8759         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8760         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8761                         << 32;
8762
8763         return rx_tstamp;
8764 }
8765
8766 static uint64_t
8767 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8768 {
8769         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8770         uint64_t tx_tstamp;
8771
8772         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8773         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8774                         << 32;
8775
8776         return tx_tstamp;
8777 }
8778
8779 static void
8780 i40e_start_timecounters(struct rte_eth_dev *dev)
8781 {
8782         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8783         struct i40e_adapter *adapter =
8784                         (struct i40e_adapter *)dev->data->dev_private;
8785         struct rte_eth_link link;
8786         uint32_t tsync_inc_l;
8787         uint32_t tsync_inc_h;
8788
8789         /* Get current link speed. */
8790         memset(&link, 0, sizeof(link));
8791         i40e_dev_link_update(dev, 1);
8792         rte_i40e_dev_atomic_read_link_status(dev, &link);
8793
8794         switch (link.link_speed) {
8795         case ETH_SPEED_NUM_40G:
8796                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8797                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8798                 break;
8799         case ETH_SPEED_NUM_10G:
8800                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8801                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8802                 break;
8803         case ETH_SPEED_NUM_1G:
8804                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8805                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8806                 break;
8807         default:
8808                 tsync_inc_l = 0x0;
8809                 tsync_inc_h = 0x0;
8810         }
8811
8812         /* Set the timesync increment value. */
8813         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8814         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8815
8816         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8817         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8818         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8819
8820         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8821         adapter->systime_tc.cc_shift = 0;
8822         adapter->systime_tc.nsec_mask = 0;
8823
8824         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8825         adapter->rx_tstamp_tc.cc_shift = 0;
8826         adapter->rx_tstamp_tc.nsec_mask = 0;
8827
8828         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8829         adapter->tx_tstamp_tc.cc_shift = 0;
8830         adapter->tx_tstamp_tc.nsec_mask = 0;
8831 }
8832
8833 static int
8834 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8835 {
8836         struct i40e_adapter *adapter =
8837                         (struct i40e_adapter *)dev->data->dev_private;
8838
8839         adapter->systime_tc.nsec += delta;
8840         adapter->rx_tstamp_tc.nsec += delta;
8841         adapter->tx_tstamp_tc.nsec += delta;
8842
8843         return 0;
8844 }
8845
8846 static int
8847 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8848 {
8849         uint64_t ns;
8850         struct i40e_adapter *adapter =
8851                         (struct i40e_adapter *)dev->data->dev_private;
8852
8853         ns = rte_timespec_to_ns(ts);
8854
8855         /* Set the timecounters to a new value. */
8856         adapter->systime_tc.nsec = ns;
8857         adapter->rx_tstamp_tc.nsec = ns;
8858         adapter->tx_tstamp_tc.nsec = ns;
8859
8860         return 0;
8861 }
8862
8863 static int
8864 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8865 {
8866         uint64_t ns, systime_cycles;
8867         struct i40e_adapter *adapter =
8868                         (struct i40e_adapter *)dev->data->dev_private;
8869
8870         systime_cycles = i40e_read_systime_cyclecounter(dev);
8871         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8872         *ts = rte_ns_to_timespec(ns);
8873
8874         return 0;
8875 }
8876
8877 static int
8878 i40e_timesync_enable(struct rte_eth_dev *dev)
8879 {
8880         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8881         uint32_t tsync_ctl_l;
8882         uint32_t tsync_ctl_h;
8883
8884         /* Stop the timesync system time. */
8885         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8886         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8887         /* Reset the timesync system time value. */
8888         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8889         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8890
8891         i40e_start_timecounters(dev);
8892
8893         /* Clear timesync registers. */
8894         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8895         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8896         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8897         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8898         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8899         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8900
8901         /* Enable timestamping of PTP packets. */
8902         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8903         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8904
8905         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8906         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8907         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8908
8909         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8910         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8911
8912         return 0;
8913 }
8914
8915 static int
8916 i40e_timesync_disable(struct rte_eth_dev *dev)
8917 {
8918         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8919         uint32_t tsync_ctl_l;
8920         uint32_t tsync_ctl_h;
8921
8922         /* Disable timestamping of transmitted PTP packets. */
8923         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8924         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8925
8926         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8927         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8928
8929         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8930         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8931
8932         /* Reset the timesync increment value. */
8933         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8934         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8935
8936         return 0;
8937 }
8938
8939 static int
8940 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8941                                 struct timespec *timestamp, uint32_t flags)
8942 {
8943         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8944         struct i40e_adapter *adapter =
8945                 (struct i40e_adapter *)dev->data->dev_private;
8946
8947         uint32_t sync_status;
8948         uint32_t index = flags & 0x03;
8949         uint64_t rx_tstamp_cycles;
8950         uint64_t ns;
8951
8952         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8953         if ((sync_status & (1 << index)) == 0)
8954                 return -EINVAL;
8955
8956         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8957         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8958         *timestamp = rte_ns_to_timespec(ns);
8959
8960         return 0;
8961 }
8962
8963 static int
8964 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8965                                 struct timespec *timestamp)
8966 {
8967         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8968         struct i40e_adapter *adapter =
8969                 (struct i40e_adapter *)dev->data->dev_private;
8970
8971         uint32_t sync_status;
8972         uint64_t tx_tstamp_cycles;
8973         uint64_t ns;
8974
8975         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8976         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8977                 return -EINVAL;
8978
8979         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8980         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8981         *timestamp = rte_ns_to_timespec(ns);
8982
8983         return 0;
8984 }
8985
8986 /*
8987  * i40e_parse_dcb_configure - parse dcb configure from user
8988  * @dev: the device being configured
8989  * @dcb_cfg: pointer of the result of parse
8990  * @*tc_map: bit map of enabled traffic classes
8991  *
8992  * Returns 0 on success, negative value on failure
8993  */
8994 static int
8995 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8996                          struct i40e_dcbx_config *dcb_cfg,
8997                          uint8_t *tc_map)
8998 {
8999         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9000         uint8_t i, tc_bw, bw_lf;
9001
9002         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9003
9004         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9005         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9006                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9007                 return -EINVAL;
9008         }
9009
9010         /* assume each tc has the same bw */
9011         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9012         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9013                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9014         /* to ensure the sum of tcbw is equal to 100 */
9015         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9016         for (i = 0; i < bw_lf; i++)
9017                 dcb_cfg->etscfg.tcbwtable[i]++;
9018
9019         /* assume each tc has the same Transmission Selection Algorithm */
9020         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9021                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9022
9023         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9024                 dcb_cfg->etscfg.prioritytable[i] =
9025                                 dcb_rx_conf->dcb_tc[i];
9026
9027         /* FW needs one App to configure HW */
9028         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9029         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9030         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9031         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9032
9033         if (dcb_rx_conf->nb_tcs == 0)
9034                 *tc_map = 1; /* tc0 only */
9035         else
9036                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9037
9038         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9039                 dcb_cfg->pfc.willing = 0;
9040                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9041                 dcb_cfg->pfc.pfcenable = *tc_map;
9042         }
9043         return 0;
9044 }
9045
9046
9047 static enum i40e_status_code
9048 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9049                               struct i40e_aqc_vsi_properties_data *info,
9050                               uint8_t enabled_tcmap)
9051 {
9052         enum i40e_status_code ret;
9053         int i, total_tc = 0;
9054         uint16_t qpnum_per_tc, bsf, qp_idx;
9055         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9056         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9057         uint16_t used_queues;
9058
9059         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9060         if (ret != I40E_SUCCESS)
9061                 return ret;
9062
9063         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9064                 if (enabled_tcmap & (1 << i))
9065                         total_tc++;
9066         }
9067         if (total_tc == 0)
9068                 total_tc = 1;
9069         vsi->enabled_tc = enabled_tcmap;
9070
9071         /* different VSI has different queues assigned */
9072         if (vsi->type == I40E_VSI_MAIN)
9073                 used_queues = dev_data->nb_rx_queues -
9074                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9075         else if (vsi->type == I40E_VSI_VMDQ2)
9076                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9077         else {
9078                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9079                 return I40E_ERR_NO_AVAILABLE_VSI;
9080         }
9081
9082         qpnum_per_tc = used_queues / total_tc;
9083         /* Number of queues per enabled TC */
9084         if (qpnum_per_tc == 0) {
9085                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9086                 return I40E_ERR_INVALID_QP_ID;
9087         }
9088         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9089                                 I40E_MAX_Q_PER_TC);
9090         bsf = rte_bsf32(qpnum_per_tc);
9091
9092         /**
9093          * Configure TC and queue mapping parameters, for enabled TC,
9094          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9095          * default queue will serve it.
9096          */
9097         qp_idx = 0;
9098         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9099                 if (vsi->enabled_tc & (1 << i)) {
9100                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9101                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9102                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9103                         qp_idx += qpnum_per_tc;
9104                 } else
9105                         info->tc_mapping[i] = 0;
9106         }
9107
9108         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9109         if (vsi->type == I40E_VSI_SRIOV) {
9110                 info->mapping_flags |=
9111                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9112                 for (i = 0; i < vsi->nb_qps; i++)
9113                         info->queue_mapping[i] =
9114                                 rte_cpu_to_le_16(vsi->base_queue + i);
9115         } else {
9116                 info->mapping_flags |=
9117                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9118                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9119         }
9120         info->valid_sections |=
9121                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9122
9123         return I40E_SUCCESS;
9124 }
9125
9126 /*
9127  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9128  * @veb: VEB to be configured
9129  * @tc_map: enabled TC bitmap
9130  *
9131  * Returns 0 on success, negative value on failure
9132  */
9133 static enum i40e_status_code
9134 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9135 {
9136         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9137         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9138         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9139         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9140         enum i40e_status_code ret = I40E_SUCCESS;
9141         int i;
9142         uint32_t bw_max;
9143
9144         /* Check if enabled_tc is same as existing or new TCs */
9145         if (veb->enabled_tc == tc_map)
9146                 return ret;
9147
9148         /* configure tc bandwidth */
9149         memset(&veb_bw, 0, sizeof(veb_bw));
9150         veb_bw.tc_valid_bits = tc_map;
9151         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9152         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9153                 if (tc_map & BIT_ULL(i))
9154                         veb_bw.tc_bw_share_credits[i] = 1;
9155         }
9156         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9157                                                    &veb_bw, NULL);
9158         if (ret) {
9159                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9160                                   " per TC failed = %d",
9161                                   hw->aq.asq_last_status);
9162                 return ret;
9163         }
9164
9165         memset(&ets_query, 0, sizeof(ets_query));
9166         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9167                                                    &ets_query, NULL);
9168         if (ret != I40E_SUCCESS) {
9169                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9170                                  " configuration %u", hw->aq.asq_last_status);
9171                 return ret;
9172         }
9173         memset(&bw_query, 0, sizeof(bw_query));
9174         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9175                                                   &bw_query, NULL);
9176         if (ret != I40E_SUCCESS) {
9177                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9178                                  " configuration %u", hw->aq.asq_last_status);
9179                 return ret;
9180         }
9181
9182         /* store and print out BW info */
9183         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9184         veb->bw_info.bw_max = ets_query.tc_bw_max;
9185         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9186         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9187         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9188                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9189                      I40E_16_BIT_WIDTH);
9190         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9191                 veb->bw_info.bw_ets_share_credits[i] =
9192                                 bw_query.tc_bw_share_credits[i];
9193                 veb->bw_info.bw_ets_credits[i] =
9194                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9195                 /* 4 bits per TC, 4th bit is reserved */
9196                 veb->bw_info.bw_ets_max[i] =
9197                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9198                                   RTE_LEN2MASK(3, uint8_t));
9199                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9200                             veb->bw_info.bw_ets_share_credits[i]);
9201                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9202                             veb->bw_info.bw_ets_credits[i]);
9203                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9204                             veb->bw_info.bw_ets_max[i]);
9205         }
9206
9207         veb->enabled_tc = tc_map;
9208
9209         return ret;
9210 }
9211
9212
9213 /*
9214  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9215  * @vsi: VSI to be configured
9216  * @tc_map: enabled TC bitmap
9217  *
9218  * Returns 0 on success, negative value on failure
9219  */
9220 static enum i40e_status_code
9221 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9222 {
9223         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9224         struct i40e_vsi_context ctxt;
9225         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9226         enum i40e_status_code ret = I40E_SUCCESS;
9227         int i;
9228
9229         /* Check if enabled_tc is same as existing or new TCs */
9230         if (vsi->enabled_tc == tc_map)
9231                 return ret;
9232
9233         /* configure tc bandwidth */
9234         memset(&bw_data, 0, sizeof(bw_data));
9235         bw_data.tc_valid_bits = tc_map;
9236         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9237         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9238                 if (tc_map & BIT_ULL(i))
9239                         bw_data.tc_bw_credits[i] = 1;
9240         }
9241         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9242         if (ret) {
9243                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9244                         " per TC failed = %d",
9245                         hw->aq.asq_last_status);
9246                 goto out;
9247         }
9248         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9249                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9250
9251         /* Update Queue Pairs Mapping for currently enabled UPs */
9252         ctxt.seid = vsi->seid;
9253         ctxt.pf_num = hw->pf_id;
9254         ctxt.vf_num = 0;
9255         ctxt.uplink_seid = vsi->uplink_seid;
9256         ctxt.info = vsi->info;
9257         i40e_get_cap(hw);
9258         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9259         if (ret)
9260                 goto out;
9261
9262         /* Update the VSI after updating the VSI queue-mapping information */
9263         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9264         if (ret) {
9265                 PMD_INIT_LOG(ERR, "Failed to configure "
9266                             "TC queue mapping = %d",
9267                             hw->aq.asq_last_status);
9268                 goto out;
9269         }
9270         /* update the local VSI info with updated queue map */
9271         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9272                                         sizeof(vsi->info.tc_mapping));
9273         (void)rte_memcpy(&vsi->info.queue_mapping,
9274                         &ctxt.info.queue_mapping,
9275                 sizeof(vsi->info.queue_mapping));
9276         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9277         vsi->info.valid_sections = 0;
9278
9279         /* query and update current VSI BW information */
9280         ret = i40e_vsi_get_bw_config(vsi);
9281         if (ret) {
9282                 PMD_INIT_LOG(ERR,
9283                          "Failed updating vsi bw info, err %s aq_err %s",
9284                          i40e_stat_str(hw, ret),
9285                          i40e_aq_str(hw, hw->aq.asq_last_status));
9286                 goto out;
9287         }
9288
9289         vsi->enabled_tc = tc_map;
9290
9291 out:
9292         return ret;
9293 }
9294
9295 /*
9296  * i40e_dcb_hw_configure - program the dcb setting to hw
9297  * @pf: pf the configuration is taken on
9298  * @new_cfg: new configuration
9299  * @tc_map: enabled TC bitmap
9300  *
9301  * Returns 0 on success, negative value on failure
9302  */
9303 static enum i40e_status_code
9304 i40e_dcb_hw_configure(struct i40e_pf *pf,
9305                       struct i40e_dcbx_config *new_cfg,
9306                       uint8_t tc_map)
9307 {
9308         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9309         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9310         struct i40e_vsi *main_vsi = pf->main_vsi;
9311         struct i40e_vsi_list *vsi_list;
9312         enum i40e_status_code ret;
9313         int i;
9314         uint32_t val;
9315
9316         /* Use the FW API if FW > v4.4*/
9317         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9318               (hw->aq.fw_maj_ver >= 5))) {
9319                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9320                                   " to configure DCB");
9321                 return I40E_ERR_FIRMWARE_API_VERSION;
9322         }
9323
9324         /* Check if need reconfiguration */
9325         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9326                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9327                 return I40E_SUCCESS;
9328         }
9329
9330         /* Copy the new config to the current config */
9331         *old_cfg = *new_cfg;
9332         old_cfg->etsrec = old_cfg->etscfg;
9333         ret = i40e_set_dcb_config(hw);
9334         if (ret) {
9335                 PMD_INIT_LOG(ERR,
9336                          "Set DCB Config failed, err %s aq_err %s\n",
9337                          i40e_stat_str(hw, ret),
9338                          i40e_aq_str(hw, hw->aq.asq_last_status));
9339                 return ret;
9340         }
9341         /* set receive Arbiter to RR mode and ETS scheme by default */
9342         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9343                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9344                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9345                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9346                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9347                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9348                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9349                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9350                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9351                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9352                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9353                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9354                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9355         }
9356         /* get local mib to check whether it is configured correctly */
9357         /* IEEE mode */
9358         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9359         /* Get Local DCB Config */
9360         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9361                                      &hw->local_dcbx_config);
9362
9363         /* if Veb is created, need to update TC of it at first */
9364         if (main_vsi->veb) {
9365                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9366                 if (ret)
9367                         PMD_INIT_LOG(WARNING,
9368                                  "Failed configuring TC for VEB seid=%d\n",
9369                                  main_vsi->veb->seid);
9370         }
9371         /* Update each VSI */
9372         i40e_vsi_config_tc(main_vsi, tc_map);
9373         if (main_vsi->veb) {
9374                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9375                         /* Beside main VSI and VMDQ VSIs, only enable default
9376                          * TC for other VSIs
9377                          */
9378                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9379                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9380                                                          tc_map);
9381                         else
9382                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9383                                                          I40E_DEFAULT_TCMAP);
9384                         if (ret)
9385                                 PMD_INIT_LOG(WARNING,
9386                                          "Failed configuring TC for VSI seid=%d\n",
9387                                          vsi_list->vsi->seid);
9388                         /* continue */
9389                 }
9390         }
9391         return I40E_SUCCESS;
9392 }
9393
9394 /*
9395  * i40e_dcb_init_configure - initial dcb config
9396  * @dev: device being configured
9397  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9398  *
9399  * Returns 0 on success, negative value on failure
9400  */
9401 static int
9402 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9403 {
9404         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9405         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9406         int ret = 0;
9407
9408         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9409                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9410                 return -ENOTSUP;
9411         }
9412
9413         /* DCB initialization:
9414          * Update DCB configuration from the Firmware and configure
9415          * LLDP MIB change event.
9416          */
9417         if (sw_dcb == TRUE) {
9418                 ret = i40e_init_dcb(hw);
9419                 /* If lldp agent is stopped, the return value from
9420                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9421                  * adminq status. Otherwise, it should return success.
9422                  */
9423                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9424                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9425                         memset(&hw->local_dcbx_config, 0,
9426                                 sizeof(struct i40e_dcbx_config));
9427                         /* set dcb default configuration */
9428                         hw->local_dcbx_config.etscfg.willing = 0;
9429                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9430                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9431                         hw->local_dcbx_config.etscfg.tsatable[0] =
9432                                                 I40E_IEEE_TSA_ETS;
9433                         hw->local_dcbx_config.etsrec =
9434                                 hw->local_dcbx_config.etscfg;
9435                         hw->local_dcbx_config.pfc.willing = 0;
9436                         hw->local_dcbx_config.pfc.pfccap =
9437                                                 I40E_MAX_TRAFFIC_CLASS;
9438                         /* FW needs one App to configure HW */
9439                         hw->local_dcbx_config.numapps = 1;
9440                         hw->local_dcbx_config.app[0].selector =
9441                                                 I40E_APP_SEL_ETHTYPE;
9442                         hw->local_dcbx_config.app[0].priority = 3;
9443                         hw->local_dcbx_config.app[0].protocolid =
9444                                                 I40E_APP_PROTOID_FCOE;
9445                         ret = i40e_set_dcb_config(hw);
9446                         if (ret) {
9447                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9448                                         " err = %d, aq_err = %d.", ret,
9449                                           hw->aq.asq_last_status);
9450                                 return -ENOSYS;
9451                         }
9452                 } else {
9453                         PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9454                                           " err = %d, aq_err = %d.", ret,
9455                                           hw->aq.asq_last_status);
9456                         return -ENOTSUP;
9457                 }
9458         } else {
9459                 ret = i40e_aq_start_lldp(hw, NULL);
9460                 if (ret != I40E_SUCCESS)
9461                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9462
9463                 ret = i40e_init_dcb(hw);
9464                 if (!ret) {
9465                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9466                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9467                                                   " DCBX offload.");
9468                                 return -ENOTSUP;
9469                         }
9470                 } else {
9471                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9472                                           " aq_err = %d.", ret,
9473                                           hw->aq.asq_last_status);
9474                         return -ENOTSUP;
9475                 }
9476         }
9477         return 0;
9478 }
9479
9480 /*
9481  * i40e_dcb_setup - setup dcb related config
9482  * @dev: device being configured
9483  *
9484  * Returns 0 on success, negative value on failure
9485  */
9486 static int
9487 i40e_dcb_setup(struct rte_eth_dev *dev)
9488 {
9489         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9490         struct i40e_dcbx_config dcb_cfg;
9491         uint8_t tc_map = 0;
9492         int ret = 0;
9493
9494         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9495                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9496                 return -ENOTSUP;
9497         }
9498
9499         if (pf->vf_num != 0)
9500                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9501
9502         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9503         if (ret) {
9504                 PMD_INIT_LOG(ERR, "invalid dcb config");
9505                 return -EINVAL;
9506         }
9507         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9508         if (ret) {
9509                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9510                 return -ENOSYS;
9511         }
9512
9513         return 0;
9514 }
9515
9516 static int
9517 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9518                       struct rte_eth_dcb_info *dcb_info)
9519 {
9520         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9521         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9522         struct i40e_vsi *vsi = pf->main_vsi;
9523         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9524         uint16_t bsf, tc_mapping;
9525         int i, j = 0;
9526
9527         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9528                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9529         else
9530                 dcb_info->nb_tcs = 1;
9531         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9532                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9533         for (i = 0; i < dcb_info->nb_tcs; i++)
9534                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9535
9536         /* get queue mapping if vmdq is disabled */
9537         if (!pf->nb_cfg_vmdq_vsi) {
9538                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9539                         if (!(vsi->enabled_tc & (1 << i)))
9540                                 continue;
9541                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9542                         dcb_info->tc_queue.tc_rxq[j][i].base =
9543                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9544                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9545                         dcb_info->tc_queue.tc_txq[j][i].base =
9546                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9547                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9548                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9549                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9550                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9551                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9552                 }
9553                 return 0;
9554         }
9555
9556         /* get queue mapping if vmdq is enabled */
9557         do {
9558                 vsi = pf->vmdq[j].vsi;
9559                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9560                         if (!(vsi->enabled_tc & (1 << i)))
9561                                 continue;
9562                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9563                         dcb_info->tc_queue.tc_rxq[j][i].base =
9564                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9565                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9566                         dcb_info->tc_queue.tc_txq[j][i].base =
9567                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9568                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9569                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9570                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9571                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9572                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9573                 }
9574                 j++;
9575         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9576         return 0;
9577 }
9578
9579 static int
9580 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9581 {
9582         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9583         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
9584         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9585         uint16_t interval =
9586                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9587         uint16_t msix_intr;
9588
9589         msix_intr = intr_handle->intr_vec[queue_id];
9590         if (msix_intr == I40E_MISC_VEC_ID)
9591                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9592                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9593                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9594                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9595                                (interval <<
9596                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9597         else
9598                 I40E_WRITE_REG(hw,
9599                                I40E_PFINT_DYN_CTLN(msix_intr -
9600                                                    I40E_RX_VEC_START),
9601                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9602                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9603                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9604                                (interval <<
9605                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9606
9607         I40E_WRITE_FLUSH(hw);
9608         rte_intr_enable(&pci_dev->intr_handle);
9609
9610         return 0;
9611 }
9612
9613 static int
9614 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9615 {
9616         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9617         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
9618         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9619         uint16_t msix_intr;
9620
9621         msix_intr = intr_handle->intr_vec[queue_id];
9622         if (msix_intr == I40E_MISC_VEC_ID)
9623                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9624         else
9625                 I40E_WRITE_REG(hw,
9626                                I40E_PFINT_DYN_CTLN(msix_intr -
9627                                                    I40E_RX_VEC_START),
9628                                0);
9629         I40E_WRITE_FLUSH(hw);
9630
9631         return 0;
9632 }
9633
9634 static int i40e_get_regs(struct rte_eth_dev *dev,
9635                          struct rte_dev_reg_info *regs)
9636 {
9637         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9638         uint32_t *ptr_data = regs->data;
9639         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9640         const struct i40e_reg_info *reg_info;
9641
9642         if (ptr_data == NULL) {
9643                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9644                 regs->width = sizeof(uint32_t);
9645                 return 0;
9646         }
9647
9648         /* The first few registers have to be read using AQ operations */
9649         reg_idx = 0;
9650         while (i40e_regs_adminq[reg_idx].name) {
9651                 reg_info = &i40e_regs_adminq[reg_idx++];
9652                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9653                         for (arr_idx2 = 0;
9654                                         arr_idx2 <= reg_info->count2;
9655                                         arr_idx2++) {
9656                                 reg_offset = arr_idx * reg_info->stride1 +
9657                                         arr_idx2 * reg_info->stride2;
9658                                 reg_offset += reg_info->base_addr;
9659                                 ptr_data[reg_offset >> 2] =
9660                                         i40e_read_rx_ctl(hw, reg_offset);
9661                         }
9662         }
9663
9664         /* The remaining registers can be read using primitives */
9665         reg_idx = 0;
9666         while (i40e_regs_others[reg_idx].name) {
9667                 reg_info = &i40e_regs_others[reg_idx++];
9668                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9669                         for (arr_idx2 = 0;
9670                                         arr_idx2 <= reg_info->count2;
9671                                         arr_idx2++) {
9672                                 reg_offset = arr_idx * reg_info->stride1 +
9673                                         arr_idx2 * reg_info->stride2;
9674                                 reg_offset += reg_info->base_addr;
9675                                 ptr_data[reg_offset >> 2] =
9676                                         I40E_READ_REG(hw, reg_offset);
9677                         }
9678         }
9679
9680         return 0;
9681 }
9682
9683 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9684 {
9685         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9686
9687         /* Convert word count to byte count */
9688         return hw->nvm.sr_size << 1;
9689 }
9690
9691 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9692                            struct rte_dev_eeprom_info *eeprom)
9693 {
9694         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9695         uint16_t *data = eeprom->data;
9696         uint16_t offset, length, cnt_words;
9697         int ret_code;
9698
9699         offset = eeprom->offset >> 1;
9700         length = eeprom->length >> 1;
9701         cnt_words = length;
9702
9703         if (offset > hw->nvm.sr_size ||
9704                 offset + length > hw->nvm.sr_size) {
9705                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9706                 return -EINVAL;
9707         }
9708
9709         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9710
9711         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9712         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9713                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9714                 return -EIO;
9715         }
9716
9717         return 0;
9718 }
9719
9720 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9721                                       struct ether_addr *mac_addr)
9722 {
9723         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9724
9725         if (!is_valid_assigned_ether_addr(mac_addr)) {
9726                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9727                 return;
9728         }
9729
9730         /* Flags: 0x3 updates port address */
9731         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9732 }
9733
9734 static int
9735 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9736 {
9737         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9738         struct rte_eth_dev_data *dev_data = pf->dev_data;
9739         uint32_t frame_size = mtu + ETHER_HDR_LEN
9740                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9741         int ret = 0;
9742
9743         /* check if mtu is within the allowed range */
9744         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9745                 return -EINVAL;
9746
9747         /* mtu setting is forbidden if port is start */
9748         if (dev_data->dev_started) {
9749                 PMD_DRV_LOG(ERR,
9750                             "port %d must be stopped before configuration\n",
9751                             dev_data->port_id);
9752                 return -EBUSY;
9753         }
9754
9755         if (frame_size > ETHER_MAX_LEN)
9756                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9757         else
9758                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9759
9760         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9761
9762         return ret;
9763 }