drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68 #include "rte_pmd_i40e.h"
  69
  70 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  71 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  72
  73 #define I40E_CLEAR_PXE_WAIT_MS     200
  74
  75 /* Maximun number of capability elements */
  76 #define I40E_MAX_CAP_ELE_NUM       128
  77
  78 /* Wait count and interval */
  79 #define I40E_CHK_Q_ENA_COUNT       1000
  80 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  81
  82 /* Maximun number of VSI */
  83 #define I40E_MAX_NUM_VSIS          (384UL)
  84
  85 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  86
  87 /* Flow control default timer */
  88 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  89
  90 /* Flow control enable fwd bit */
  91 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  92
  93 /* Receive Packet Buffer size */
  94 #define I40E_RXPBSIZE (968 * 1024)
  95
  96 /* Kilobytes shift */
  97 #define I40E_KILOSHIFT 10
  98
  99 /* Flow control default high water */
 100 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
 101
 102 /* Flow control default low water */
 103 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
 104
 105 /* Receive Average Packet Size in Byte*/
 106 #define I40E_PACKET_AVERAGE_SIZE 128
 107
 108 /* Mask of PF interrupt causes */
 109 #define I40E_PFINT_ICR0_ENA_MASK ( \
 110                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 112                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 114                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 115                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 118                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 119
 120 #define I40E_FLOW_TYPES ( \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 130         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 131         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 132
 133 /* Additional timesync values. */
 134 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 135 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 136 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 137 #define I40E_PRTTSYN_TSYNENA     0x80000000
 138 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 139 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 /**
 142  * Below are values for writing un-exposed registers suggested
 143  * by silicon experts
 144  */
 145 /* Destination MAC address */
 146 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 147 /* Source MAC address */
 148 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 149 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 150 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 151 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 152 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 153 /* Single VLAN tag in the inner L2 header */
 154 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 155 /* Source IPv4 address */
 156 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 157 /* Destination IPv4 address */
 158 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 159 /* Source IPv4 address for X722 */
 160 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 161 /* Destination IPv4 address for X722 */
 162 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 163 /* IPv4 Protocol for X722 */
 164 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 165 /* IPv4 Time to Live for X722 */
 166 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 167 /* IPv4 Type of Service (TOS) */
 168 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 169 /* IPv4 Protocol */
 170 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 171 /* IPv4 Time to Live */
 172 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 173 /* Source IPv6 address */
 174 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 175 /* Destination IPv6 address */
 176 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 177 /* IPv6 Traffic Class (TC) */
 178 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 179 /* IPv6 Next Header */
 180 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 181 /* IPv6 Hop Limit */
 182 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 183 /* Source L4 port */
 184 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 185 /* Destination L4 port */
 186 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 187 /* SCTP verification tag */
 188 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 189 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 190 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 191 /* Source port of tunneling UDP */
 192 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 193 /* Destination port of tunneling UDP */
 194 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 195 /* UDP Tunneling ID, NVGRE/GRE key */
 196 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 197 /* Last ether type */
 198 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 199 /* Tunneling outer destination IPv4 address */
 200 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 201 /* Tunneling outer destination IPv6 address */
 202 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 203 /* 1st word of flex payload */
 204 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 205 /* 2nd word of flex payload */
 206 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 207 /* 3rd word of flex payload */
 208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 209 /* 4th word of flex payload */
 210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 211 /* 5th word of flex payload */
 212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 213 /* 6th word of flex payload */
 214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 215 /* 7th word of flex payload */
 216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 217 /* 8th word of flex payload */
 218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 219 /* all 8 words flex payload */
 220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 221 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 222
 223 #define I40E_TRANSLATE_INSET 0
 224 #define I40E_TRANSLATE_REG   1
 225
 226 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 227 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 228 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 229 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 230 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 231 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 232
 233 /* PCI offset for querying capability */
 234 #define PCI_DEV_CAP_REG            0xA4
 235 /* PCI offset for enabling/disabling Extended Tag */
 236 #define PCI_DEV_CTRL_REG           0xA8
 237 /* Bit mask of Extended Tag capability */
 238 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 239 /* Bit shift of Extended Tag enable/disable */
 240 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 241 /* Bit mask of Extended Tag enable/disable */
 242 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 243
 244 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 245 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 246 static int i40e_dev_configure(struct rte_eth_dev *dev);
 247 static int i40e_dev_start(struct rte_eth_dev *dev);
 248 static void i40e_dev_stop(struct rte_eth_dev *dev);
 249 static void i40e_dev_close(struct rte_eth_dev *dev);
 250 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 251 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 252 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 253 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 254 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 255 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 256 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 257 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 258                                struct rte_eth_stats *stats);
 259 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 260                                struct rte_eth_xstat *xstats, unsigned n);
 261 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 262                                      struct rte_eth_xstat_name *xstats_names,
 263                                      unsigned limit);
 264 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 265 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 266                                             uint16_t queue_id,
 267                                             uint8_t stat_idx,
 268                                             uint8_t is_rx);
 269 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 270                                 char *fw_version, size_t fw_size);
 271 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 272                               struct rte_eth_dev_info *dev_info);
 273 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 274                                 uint16_t vlan_id,
 275                                 int on);
 276 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 277                               enum rte_vlan_type vlan_type,
 278                               uint16_t tpid);
 279 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 280 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 281                                       uint16_t queue,
 282                                       int on);
 283 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 284 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 285 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 286 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 287                               struct rte_eth_fc_conf *fc_conf);
 288 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 289                               struct rte_eth_fc_conf *fc_conf);
 290 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 291                                        struct rte_eth_pfc_conf *pfc_conf);
 292 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 293                             struct ether_addr *mac_addr,
 294                             uint32_t index,
 295                             uint32_t pool);
 296 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 297 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 298                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 299                                     uint16_t reta_size);
 300 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 301                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 302                                    uint16_t reta_size);
 303
 304 static int i40e_get_cap(struct i40e_hw *hw);
 305 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 306 static int i40e_pf_setup(struct i40e_pf *pf);
 307 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 308 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 309 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 310 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 311                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 312 static void i40e_stat_update_48(struct i40e_hw *hw,
 313                                uint32_t hireg,
 314                                uint32_t loreg,
 315                                bool offset_loaded,
 316                                uint64_t *offset,
 317                                uint64_t *stat);
 318 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 319 static void i40e_dev_interrupt_handler(void *param);
 320 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 321                                 uint32_t base, uint32_t num);
 322 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 323 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 324                         uint32_t base);
 325 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 326                         uint16_t num);
 327 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 328 static int i40e_veb_release(struct i40e_veb *veb);
 329 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 330                                                 struct i40e_vsi *vsi);
 331 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 332 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 333 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 334                                              struct i40e_macvlan_filter *mv_f,
 335                                              int num,
 336                                              uint16_t vlan);
 337 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 338 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 339                                     struct rte_eth_rss_conf *rss_conf);
 340 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 341                                       struct rte_eth_rss_conf *rss_conf);
 342 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 343                                         struct rte_eth_udp_tunnel *udp_tunnel);
 344 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 345                                         struct rte_eth_udp_tunnel *udp_tunnel);
 346 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 347 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 348                                 enum rte_filter_op filter_op,
 349                                 void *arg);
 350 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 351                                 enum rte_filter_type filter_type,
 352                                 enum rte_filter_op filter_op,
 353                                 void *arg);
 354 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 355                                   struct rte_eth_dcb_info *dcb_info);
 356 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 357 static void i40e_configure_registers(struct i40e_hw *hw);
 358 static void i40e_hw_init(struct rte_eth_dev *dev);
 359 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 360 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 361                                                      uint16_t seid,
 362                                                      uint16_t rule_type,
 363                                                      uint16_t *entries,
 364                                                      uint16_t count,
 365                                                      uint16_t rule_id);
 366 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 367                         struct rte_eth_mirror_conf *mirror_conf,
 368                         uint8_t sw_id, uint8_t on);
 369 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 370
 371 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 372 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 373 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 374                                            struct timespec *timestamp,
 375                                            uint32_t flags);
 376 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 377                                            struct timespec *timestamp);
 378 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 379
 380 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 381
 382 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 383                                    struct timespec *timestamp);
 384 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 385                                     const struct timespec *timestamp);
 386
 387 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 388                                          uint16_t queue_id);
 389 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 390                                           uint16_t queue_id);
 391
 392 static int i40e_get_regs(struct rte_eth_dev *dev,
 393                          struct rte_dev_reg_info *regs);
 394
 395 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 396
 397 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 398                            struct rte_dev_eeprom_info *eeprom);
 399
 400 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 401                                       struct ether_addr *mac_addr);
 402
 403 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 404
 405 static int i40e_ethertype_filter_convert(
 406         const struct rte_eth_ethertype_filter *input,
 407         struct i40e_ethertype_filter *filter);
 408 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 409                                    struct i40e_ethertype_filter *filter);
 410
 411 static int i40e_tunnel_filter_convert(
 412         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 413         struct i40e_tunnel_filter *tunnel_filter);
 414 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 415                                 struct i40e_tunnel_filter *tunnel_filter);
 416 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 417
 418 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 419 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 420 static void i40e_filter_restore(struct i40e_pf *pf);
 421 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 422
 423 int i40e_logtype_init;
 424 int i40e_logtype_driver;
 425
 426 static const struct rte_pci_id pci_id_i40e_map[] = {
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 445         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 446         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 447         { .vendor_id = 0, /* sentinel */ },
 448 };
 449
 450 static const struct eth_dev_ops i40e_eth_dev_ops = {
 451         .dev_configure                = i40e_dev_configure,
 452         .dev_start                    = i40e_dev_start,
 453         .dev_stop                     = i40e_dev_stop,
 454         .dev_close                    = i40e_dev_close,
 455         .dev_reset                    = i40e_dev_reset,
 456         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 457         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 458         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 459         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 460         .dev_set_link_up              = i40e_dev_set_link_up,
 461         .dev_set_link_down            = i40e_dev_set_link_down,
 462         .link_update                  = i40e_dev_link_update,
 463         .stats_get                    = i40e_dev_stats_get,
 464         .xstats_get                   = i40e_dev_xstats_get,
 465         .xstats_get_names             = i40e_dev_xstats_get_names,
 466         .stats_reset                  = i40e_dev_stats_reset,
 467         .xstats_reset                 = i40e_dev_stats_reset,
 468         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 469         .fw_version_get               = i40e_fw_version_get,
 470         .dev_infos_get                = i40e_dev_info_get,
 471         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 472         .vlan_filter_set              = i40e_vlan_filter_set,
 473         .vlan_tpid_set                = i40e_vlan_tpid_set,
 474         .vlan_offload_set             = i40e_vlan_offload_set,
 475         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 476         .vlan_pvid_set                = i40e_vlan_pvid_set,
 477         .rx_queue_start               = i40e_dev_rx_queue_start,
 478         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 479         .tx_queue_start               = i40e_dev_tx_queue_start,
 480         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 481         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 482         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 483         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 484         .rx_queue_release             = i40e_dev_rx_queue_release,
 485         .rx_queue_count               = i40e_dev_rx_queue_count,
 486         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 487         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 488         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 489         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 490         .tx_queue_release             = i40e_dev_tx_queue_release,
 491         .dev_led_on                   = i40e_dev_led_on,
 492         .dev_led_off                  = i40e_dev_led_off,
 493         .flow_ctrl_get                = i40e_flow_ctrl_get,
 494         .flow_ctrl_set                = i40e_flow_ctrl_set,
 495         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 496         .mac_addr_add                 = i40e_macaddr_add,
 497         .mac_addr_remove              = i40e_macaddr_remove,
 498         .reta_update                  = i40e_dev_rss_reta_update,
 499         .reta_query                   = i40e_dev_rss_reta_query,
 500         .rss_hash_update              = i40e_dev_rss_hash_update,
 501         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 502         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 503         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 504         .filter_ctrl                  = i40e_dev_filter_ctrl,
 505         .rxq_info_get                 = i40e_rxq_info_get,
 506         .txq_info_get                 = i40e_txq_info_get,
 507         .mirror_rule_set              = i40e_mirror_rule_set,
 508         .mirror_rule_reset            = i40e_mirror_rule_reset,
 509         .timesync_enable              = i40e_timesync_enable,
 510         .timesync_disable             = i40e_timesync_disable,
 511         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 512         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 513         .get_dcb_info                 = i40e_dev_get_dcb_info,
 514         .timesync_adjust_time         = i40e_timesync_adjust_time,
 515         .timesync_read_time           = i40e_timesync_read_time,
 516         .timesync_write_time          = i40e_timesync_write_time,
 517         .get_reg                      = i40e_get_regs,
 518         .get_eeprom_length            = i40e_get_eeprom_length,
 519         .get_eeprom                   = i40e_get_eeprom,
 520         .mac_addr_set                 = i40e_set_default_mac_addr,
 521         .mtu_set                      = i40e_dev_mtu_set,
 522         .tm_ops_get                   = i40e_tm_ops_get,
 523 };
 524
 525 /* store statistics names and its offset in stats structure */
 526 struct rte_i40e_xstats_name_off {
 527         char name[RTE_ETH_XSTATS_NAME_SIZE];
 528         unsigned offset;
 529 };
 530
 531 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 532         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 533         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 534         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 535         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 536         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 537                 rx_unknown_protocol)},
 538         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 539         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 540         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 541         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 542 };
 543
 544 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 545                 sizeof(rte_i40e_stats_strings[0]))
 546
 547 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 548         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 549                 tx_dropped_link_down)},
 550         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 551         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 552                 illegal_bytes)},
 553         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 554         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 555                 mac_local_faults)},
 556         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 557                 mac_remote_faults)},
 558         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 559                 rx_length_errors)},
 560         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 561         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 562         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 563         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 564         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 565         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_127)},
 567         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_255)},
 569         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_511)},
 571         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_1023)},
 573         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 574                 rx_size_1522)},
 575         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 576                 rx_size_big)},
 577         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 578                 rx_undersize)},
 579         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 580                 rx_oversize)},
 581         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 582                 mac_short_packet_dropped)},
 583         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 584                 rx_fragments)},
 585         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 586         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 587         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_127)},
 589         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_255)},
 591         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_511)},
 593         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_1023)},
 595         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 596                 tx_size_1522)},
 597         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 598                 tx_size_big)},
 599         {"rx_flow_director_atr_match_packets",
 600                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 601         {"rx_flow_director_sb_match_packets",
 602                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 603         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 604                 tx_lpi_status)},
 605         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 606                 rx_lpi_status)},
 607         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 608                 tx_lpi_count)},
 609         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 610                 rx_lpi_count)},
 611 };
 612
 613 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 614                 sizeof(rte_i40e_hw_port_strings[0]))
 615
 616 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 617         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 618                 priority_xon_rx)},
 619         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 620                 priority_xoff_rx)},
 621 };
 622
 623 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 624                 sizeof(rte_i40e_rxq_prio_strings[0]))
 625
 626 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 627         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 628                 priority_xon_tx)},
 629         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 630                 priority_xoff_tx)},
 631         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 632                 priority_xon_2_xoff)},
 633 };
 634
 635 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 636                 sizeof(rte_i40e_txq_prio_strings[0]))
 637
 638 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 639         struct rte_pci_device *pci_dev)
 640 {
 641         return rte_eth_dev_pci_generic_probe(pci_dev,
 642                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 643 }
 644
 645 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 646 {
 647         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 648 }
 649
 650 static struct rte_pci_driver rte_i40e_pmd = {
 651         .id_table = pci_id_i40e_map,
 652         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 653                      RTE_PCI_DRV_IOVA_AS_VA,
 654         .probe = eth_i40e_pci_probe,
 655         .remove = eth_i40e_pci_remove,
 656 };
 657
 658 static inline int
 659 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 660                                      struct rte_eth_link *link)
 661 {
 662         struct rte_eth_link *dst = link;
 663         struct rte_eth_link *src = &(dev->data->dev_link);
 664
 665         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 666                                         *(uint64_t *)src) == 0)
 667                 return -1;
 668
 669         return 0;
 670 }
 671
 672 static inline int
 673 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 674                                       struct rte_eth_link *link)
 675 {
 676         struct rte_eth_link *dst = &(dev->data->dev_link);
 677         struct rte_eth_link *src = link;
 678
 679         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 680                                         *(uint64_t *)src) == 0)
 681                 return -1;
 682
 683         return 0;
 684 }
 685
 686 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 687 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 688 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 689
 690 #ifndef I40E_GLQF_ORT
 691 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 692 #endif
 693 #ifndef I40E_GLQF_PIT
 694 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 695 #endif
 696 #ifndef I40E_GLQF_L3_MAP
 697 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 698 #endif
 699
 700 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 701 {
 702         /*
 703          * Force global configuration for flexible payload
 704          * to the first 16 bytes of the corresponding L2/L3/L4 paylod.
 705          * This should be removed from code once proper
 706          * configuration API is added to avoid configuration conflicts
 707          * between ports of the same device.
 708          */
 709         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 710         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 711         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 712
 713         /*
 714          * Initialize registers for parsing packet type of QinQ
 715          * This should be removed from code once proper
 716          * configuration API is added to avoid configuration conflicts
 717          * between ports of the same device.
 718          */
 719         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 720         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 721 }
 722
 723 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 724
 725 /*
 726  * Add a ethertype filter to drop all flow control frames transmitted
 727  * from VSIs.
 728 */
 729 static void
 730 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 731 {
 732         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 733         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 734                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 735                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 736         int ret;
 737
 738         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 739                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 740                                 pf->main_vsi_seid, 0,
 741                                 TRUE, NULL, NULL);
 742         if (ret)
 743                 PMD_INIT_LOG(ERR,
 744                         "Failed to add filter to drop flow control frames from VSIs.");
 745 }
 746
 747 static int
 748 floating_veb_list_handler(__rte_unused const char *key,
 749                           const char *floating_veb_value,
 750                           void *opaque)
 751 {
 752         int idx = 0;
 753         unsigned int count = 0;
 754         char *end = NULL;
 755         int min, max;
 756         bool *vf_floating_veb = opaque;
 757
 758         while (isblank(*floating_veb_value))
 759                 floating_veb_value++;
 760
 761         /* Reset floating VEB configuration for VFs */
 762         for (idx = 0; idx < I40E_MAX_VF; idx++)
 763                 vf_floating_veb[idx] = false;
 764
 765         min = I40E_MAX_VF;
 766         do {
 767                 while (isblank(*floating_veb_value))
 768                         floating_veb_value++;
 769                 if (*floating_veb_value == '\0')
 770                         return -1;
 771                 errno = 0;
 772                 idx = strtoul(floating_veb_value, &end, 10);
 773                 if (errno || end == NULL)
 774                         return -1;
 775                 while (isblank(*end))
 776                         end++;
 777                 if (*end == '-') {
 778                         min = idx;
 779                 } else if ((*end == ';') || (*end == '\0')) {
 780                         max = idx;
 781                         if (min == I40E_MAX_VF)
 782                                 min = idx;
 783                         if (max >= I40E_MAX_VF)
 784                                 max = I40E_MAX_VF - 1;
 785                         for (idx = min; idx <= max; idx++) {
 786                                 vf_floating_veb[idx] = true;
 787                                 count++;
 788                         }
 789                         min = I40E_MAX_VF;
 790                 } else {
 791                         return -1;
 792                 }
 793                 floating_veb_value = end + 1;
 794         } while (*end != '\0');
 795
 796         if (count == 0)
 797                 return -1;
 798
 799         return 0;
 800 }
 801
 802 static void
 803 config_vf_floating_veb(struct rte_devargs *devargs,
 804                        uint16_t floating_veb,
 805                        bool *vf_floating_veb)
 806 {
 807         struct rte_kvargs *kvlist;
 808         int i;
 809         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 810
 811         if (!floating_veb)
 812                 return;
 813         /* All the VFs attach to the floating VEB by default
 814          * when the floating VEB is enabled.
 815          */
 816         for (i = 0; i < I40E_MAX_VF; i++)
 817                 vf_floating_veb[i] = true;
 818
 819         if (devargs == NULL)
 820                 return;
 821
 822         kvlist = rte_kvargs_parse(devargs->args, NULL);
 823         if (kvlist == NULL)
 824                 return;
 825
 826         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 827                 rte_kvargs_free(kvlist);
 828                 return;
 829         }
 830         /* When the floating_veb_list parameter exists, all the VFs
 831          * will attach to the legacy VEB firstly, then configure VFs
 832          * to the floating VEB according to the floating_veb_list.
 833          */
 834         if (rte_kvargs_process(kvlist, floating_veb_list,
 835                                floating_veb_list_handler,
 836                                vf_floating_veb) < 0) {
 837                 rte_kvargs_free(kvlist);
 838                 return;
 839         }
 840         rte_kvargs_free(kvlist);
 841 }
 842
 843 static int
 844 i40e_check_floating_handler(__rte_unused const char *key,
 845                             const char *value,
 846                             __rte_unused void *opaque)
 847 {
 848         if (strcmp(value, "1"))
 849                 return -1;
 850
 851         return 0;
 852 }
 853
 854 static int
 855 is_floating_veb_supported(struct rte_devargs *devargs)
 856 {
 857         struct rte_kvargs *kvlist;
 858         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 859
 860         if (devargs == NULL)
 861                 return 0;
 862
 863         kvlist = rte_kvargs_parse(devargs->args, NULL);
 864         if (kvlist == NULL)
 865                 return 0;
 866
 867         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 868                 rte_kvargs_free(kvlist);
 869                 return 0;
 870         }
 871         /* Floating VEB is enabled when there's key-value:
 872          * enable_floating_veb=1
 873          */
 874         if (rte_kvargs_process(kvlist, floating_veb_key,
 875                                i40e_check_floating_handler, NULL) < 0) {
 876                 rte_kvargs_free(kvlist);
 877                 return 0;
 878         }
 879         rte_kvargs_free(kvlist);
 880
 881         return 1;
 882 }
 883
 884 static void
 885 config_floating_veb(struct rte_eth_dev *dev)
 886 {
 887         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 888         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 889         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 890
 891         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 892
 893         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 894                 pf->floating_veb =
 895                         is_floating_veb_supported(pci_dev->device.devargs);
 896                 config_vf_floating_veb(pci_dev->device.devargs,
 897                                        pf->floating_veb,
 898                                        pf->floating_veb_list);
 899         } else {
 900                 pf->floating_veb = false;
 901         }
 902 }
 903
 904 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 905 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 906
 907 static int
 908 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 909 {
 910         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 911         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 912         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 913         int ret;
 914
 915         struct rte_hash_parameters ethertype_hash_params = {
 916                 .name = ethertype_hash_name,
 917                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 918                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 919                 .hash_func = rte_hash_crc,
 920                 .hash_func_init_val = 0,
 921                 .socket_id = rte_socket_id(),
 922         };
 923
 924         /* Initialize ethertype filter rule list and hash */
 925         TAILQ_INIT(&ethertype_rule->ethertype_list);
 926         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 927                  "ethertype_%s", dev->device->name);
 928         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 929         if (!ethertype_rule->hash_table) {
 930                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 931                 return -EINVAL;
 932         }
 933         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 934                                        sizeof(struct i40e_ethertype_filter *) *
 935                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 936                                        0);
 937         if (!ethertype_rule->hash_map) {
 938                 PMD_INIT_LOG(ERR,
 939                              "Failed to allocate memory for ethertype hash map!");
 940                 ret = -ENOMEM;
 941                 goto err_ethertype_hash_map_alloc;
 942         }
 943
 944         return 0;
 945
 946 err_ethertype_hash_map_alloc:
 947         rte_hash_free(ethertype_rule->hash_table);
 948
 949         return ret;
 950 }
 951
 952 static int
 953 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 954 {
 955         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 956         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 957         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 958         int ret;
 959
 960         struct rte_hash_parameters tunnel_hash_params = {
 961                 .name = tunnel_hash_name,
 962                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 963                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 964                 .hash_func = rte_hash_crc,
 965                 .hash_func_init_val = 0,
 966                 .socket_id = rte_socket_id(),
 967         };
 968
 969         /* Initialize tunnel filter rule list and hash */
 970         TAILQ_INIT(&tunnel_rule->tunnel_list);
 971         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 972                  "tunnel_%s", dev->device->name);
 973         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 974         if (!tunnel_rule->hash_table) {
 975                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 976                 return -EINVAL;
 977         }
 978         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 979                                     sizeof(struct i40e_tunnel_filter *) *
 980                                     I40E_MAX_TUNNEL_FILTER_NUM,
 981                                     0);
 982         if (!tunnel_rule->hash_map) {
 983                 PMD_INIT_LOG(ERR,
 984                              "Failed to allocate memory for tunnel hash map!");
 985                 ret = -ENOMEM;
 986                 goto err_tunnel_hash_map_alloc;
 987         }
 988
 989         return 0;
 990
 991 err_tunnel_hash_map_alloc:
 992         rte_hash_free(tunnel_rule->hash_table);
 993
 994         return ret;
 995 }
 996
 997 static int
 998 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 999 {
1000         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1001         struct i40e_fdir_info *fdir_info = &pf->fdir;
1002         char fdir_hash_name[RTE_HASH_NAMESIZE];
1003         int ret;
1004
1005         struct rte_hash_parameters fdir_hash_params = {
1006                 .name = fdir_hash_name,
1007                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1008                 .key_len = sizeof(struct rte_eth_fdir_input),
1009                 .hash_func = rte_hash_crc,
1010                 .hash_func_init_val = 0,
1011                 .socket_id = rte_socket_id(),
1012         };
1013
1014         /* Initialize flow director filter rule list and hash */
1015         TAILQ_INIT(&fdir_info->fdir_list);
1016         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1017                  "fdir_%s", dev->device->name);
1018         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1019         if (!fdir_info->hash_table) {
1020                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1021                 return -EINVAL;
1022         }
1023         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1024                                           sizeof(struct i40e_fdir_filter *) *
1025                                           I40E_MAX_FDIR_FILTER_NUM,
1026                                           0);
1027         if (!fdir_info->hash_map) {
1028                 PMD_INIT_LOG(ERR,
1029                              "Failed to allocate memory for fdir hash map!");
1030                 ret = -ENOMEM;
1031                 goto err_fdir_hash_map_alloc;
1032         }
1033         return 0;
1034
1035 err_fdir_hash_map_alloc:
1036         rte_hash_free(fdir_info->hash_table);
1037
1038         return ret;
1039 }
1040
1041 static void
1042 i40e_init_customized_info(struct i40e_pf *pf)
1043 {
1044         int i;
1045
1046         /* Initialize customized pctype */
1047         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1048                 pf->customized_pctype[i].index = i;
1049                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1050                 pf->customized_pctype[i].valid = false;
1051         }
1052
1053         pf->gtp_support = false;
1054 }
1055
1056 void
1057 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1058 {
1059         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1060         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1061         struct i40e_queue_regions *info = &pf->queue_region;
1062         uint16_t i;
1063
1064         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1065                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1066
1067         memset(info, 0, sizeof(struct i40e_queue_regions));
1068 }
1069
1070 static int
1071 eth_i40e_dev_init(struct rte_eth_dev *dev)
1072 {
1073         struct rte_pci_device *pci_dev;
1074         struct rte_intr_handle *intr_handle;
1075         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1076         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1077         struct i40e_vsi *vsi;
1078         int ret;
1079         uint32_t len;
1080         uint8_t aq_fail = 0;
1081
1082         PMD_INIT_FUNC_TRACE();
1083
1084         dev->dev_ops = &i40e_eth_dev_ops;
1085         dev->rx_pkt_burst = i40e_recv_pkts;
1086         dev->tx_pkt_burst = i40e_xmit_pkts;
1087         dev->tx_pkt_prepare = i40e_prep_pkts;
1088
1089         /* for secondary processes, we don't initialise any further as primary
1090          * has already done this work. Only check we don't need a different
1091          * RX function */
1092         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1093                 i40e_set_rx_function(dev);
1094                 i40e_set_tx_function(dev);
1095                 return 0;
1096         }
1097         i40e_set_default_ptype_table(dev);
1098         i40e_set_default_pctype_table(dev);
1099         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1100         intr_handle = &pci_dev->intr_handle;
1101
1102         rte_eth_copy_pci_info(dev, pci_dev);
1103
1104         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1105         pf->adapter->eth_dev = dev;
1106         pf->dev_data = dev->data;
1107
1108         hw->back = I40E_PF_TO_ADAPTER(pf);
1109         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1110         if (!hw->hw_addr) {
1111                 PMD_INIT_LOG(ERR,
1112                         "Hardware is not available, as address is NULL");
1113                 return -ENODEV;
1114         }
1115
1116         hw->vendor_id = pci_dev->id.vendor_id;
1117         hw->device_id = pci_dev->id.device_id;
1118         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1119         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1120         hw->bus.device = pci_dev->addr.devid;
1121         hw->bus.func = pci_dev->addr.function;
1122         hw->adapter_stopped = 0;
1123
1124         /* Make sure all is clean before doing PF reset */
1125         i40e_clear_hw(hw);
1126
1127         /* Initialize the hardware */
1128         i40e_hw_init(dev);
1129
1130         /* Reset here to make sure all is clean for each PF */
1131         ret = i40e_pf_reset(hw);
1132         if (ret) {
1133                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1134                 return ret;
1135         }
1136
1137         /* Initialize the shared code (base driver) */
1138         ret = i40e_init_shared_code(hw);
1139         if (ret) {
1140                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1141                 return ret;
1142         }
1143
1144         /*
1145          * To work around the NVM issue, initialize registers
1146          * for flexible payload and packet type of QinQ by
1147          * software. It should be removed once issues are fixed
1148          * in NVM.
1149          */
1150         i40e_GLQF_reg_init(hw);
1151
1152         /* Initialize the input set for filters (hash and fd) to default value */
1153         i40e_filter_input_set_init(pf);
1154
1155         /* Initialize the parameters for adminq */
1156         i40e_init_adminq_parameter(hw);
1157         ret = i40e_init_adminq(hw);
1158         if (ret != I40E_SUCCESS) {
1159                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1160                 return -EIO;
1161         }
1162         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1163                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1164                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1165                      ((hw->nvm.version >> 12) & 0xf),
1166                      ((hw->nvm.version >> 4) & 0xff),
1167                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1168
1169         /* initialise the L3_MAP register */
1170         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1171                                    0x00000028,  NULL);
1172         if (ret)
1173                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1174
1175         /* Need the special FW version to support floating VEB */
1176         config_floating_veb(dev);
1177         /* Clear PXE mode */
1178         i40e_clear_pxe_mode(hw);
1179         i40e_dev_sync_phy_type(hw);
1180
1181         /*
1182          * On X710, performance number is far from the expectation on recent
1183          * firmware versions. The fix for this issue may not be integrated in
1184          * the following firmware version. So the workaround in software driver
1185          * is needed. It needs to modify the initial values of 3 internal only
1186          * registers. Note that the workaround can be removed when it is fixed
1187          * in firmware in the future.
1188          */
1189         i40e_configure_registers(hw);
1190
1191         /* Get hw capabilities */
1192         ret = i40e_get_cap(hw);
1193         if (ret != I40E_SUCCESS) {
1194                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1195                 goto err_get_capabilities;
1196         }
1197
1198         /* Initialize parameters for PF */
1199         ret = i40e_pf_parameter_init(dev);
1200         if (ret != 0) {
1201                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1202                 goto err_parameter_init;
1203         }
1204
1205         /* Initialize the queue management */
1206         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1207         if (ret < 0) {
1208                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1209                 goto err_qp_pool_init;
1210         }
1211         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1212                                 hw->func_caps.num_msix_vectors - 1);
1213         if (ret < 0) {
1214                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1215                 goto err_msix_pool_init;
1216         }
1217
1218         /* Initialize lan hmc */
1219         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1220                                 hw->func_caps.num_rx_qp, 0, 0);
1221         if (ret != I40E_SUCCESS) {
1222                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1223                 goto err_init_lan_hmc;
1224         }
1225
1226         /* Configure lan hmc */
1227         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1228         if (ret != I40E_SUCCESS) {
1229                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1230                 goto err_configure_lan_hmc;
1231         }
1232
1233         /* Get and check the mac address */
1234         i40e_get_mac_addr(hw, hw->mac.addr);
1235         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1236                 PMD_INIT_LOG(ERR, "mac address is not valid");
1237                 ret = -EIO;
1238                 goto err_get_mac_addr;
1239         }
1240         /* Copy the permanent MAC address */
1241         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1242                         (struct ether_addr *) hw->mac.perm_addr);
1243
1244         /* Disable flow control */
1245         hw->fc.requested_mode = I40E_FC_NONE;
1246         i40e_set_fc(hw, &aq_fail, TRUE);
1247
1248         /* Set the global registers with default ether type value */
1249         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1250         if (ret != I40E_SUCCESS) {
1251                 PMD_INIT_LOG(ERR,
1252                         "Failed to set the default outer VLAN ether type");
1253                 goto err_setup_pf_switch;
1254         }
1255
1256         /* PF setup, which includes VSI setup */
1257         ret = i40e_pf_setup(pf);
1258         if (ret) {
1259                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1260                 goto err_setup_pf_switch;
1261         }
1262
1263         /* reset all stats of the device, including pf and main vsi */
1264         i40e_dev_stats_reset(dev);
1265
1266         vsi = pf->main_vsi;
1267
1268         /* Disable double vlan by default */
1269         i40e_vsi_config_double_vlan(vsi, FALSE);
1270
1271         /* Disable S-TAG identification when floating_veb is disabled */
1272         if (!pf->floating_veb) {
1273                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1274                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1275                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1276                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1277                 }
1278         }
1279
1280         if (!vsi->max_macaddrs)
1281                 len = ETHER_ADDR_LEN;
1282         else
1283                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1284
1285         /* Should be after VSI initialized */
1286         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1287         if (!dev->data->mac_addrs) {
1288                 PMD_INIT_LOG(ERR,
1289                         "Failed to allocated memory for storing mac address");
1290                 goto err_mac_alloc;
1291         }
1292         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1293                                         &dev->data->mac_addrs[0]);
1294
1295         /* Init dcb to sw mode by default */
1296         ret = i40e_dcb_init_configure(dev, TRUE);
1297         if (ret != I40E_SUCCESS) {
1298                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1299                 pf->flags &= ~I40E_FLAG_DCB;
1300         }
1301         /* Update HW struct after DCB configuration */
1302         i40e_get_cap(hw);
1303
1304         /* initialize pf host driver to setup SRIOV resource if applicable */
1305         i40e_pf_host_init(dev);
1306
1307         /* register callback func to eal lib */
1308         rte_intr_callback_register(intr_handle,
1309                                    i40e_dev_interrupt_handler, dev);
1310
1311         /* configure and enable device interrupt */
1312         i40e_pf_config_irq0(hw, TRUE);
1313         i40e_pf_enable_irq0(hw);
1314
1315         /* enable uio intr after callback register */
1316         rte_intr_enable(intr_handle);
1317         /*
1318          * Add an ethertype filter to drop all flow control frames transmitted
1319          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1320          * frames to wire.
1321          */
1322         i40e_add_tx_flow_control_drop_filter(pf);
1323
1324         /* Set the max frame size to 0x2600 by default,
1325          * in case other drivers changed the default value.
1326          */
1327         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1328
1329         /* initialize mirror rule list */
1330         TAILQ_INIT(&pf->mirror_list);
1331
1332         /* initialize Traffic Manager configuration */
1333         i40e_tm_conf_init(dev);
1334
1335         /* Initialize customized information */
1336         i40e_init_customized_info(pf);
1337
1338         ret = i40e_init_ethtype_filter_list(dev);
1339         if (ret < 0)
1340                 goto err_init_ethtype_filter_list;
1341         ret = i40e_init_tunnel_filter_list(dev);
1342         if (ret < 0)
1343                 goto err_init_tunnel_filter_list;
1344         ret = i40e_init_fdir_filter_list(dev);
1345         if (ret < 0)
1346                 goto err_init_fdir_filter_list;
1347
1348         /* initialize queue region configuration */
1349         i40e_init_queue_region_conf(dev);
1350
1351         return 0;
1352
1353 err_init_fdir_filter_list:
1354         rte_free(pf->tunnel.hash_table);
1355         rte_free(pf->tunnel.hash_map);
1356 err_init_tunnel_filter_list:
1357         rte_free(pf->ethertype.hash_table);
1358         rte_free(pf->ethertype.hash_map);
1359 err_init_ethtype_filter_list:
1360         rte_free(dev->data->mac_addrs);
1361 err_mac_alloc:
1362         i40e_vsi_release(pf->main_vsi);
1363 err_setup_pf_switch:
1364 err_get_mac_addr:
1365 err_configure_lan_hmc:
1366         (void)i40e_shutdown_lan_hmc(hw);
1367 err_init_lan_hmc:
1368         i40e_res_pool_destroy(&pf->msix_pool);
1369 err_msix_pool_init:
1370         i40e_res_pool_destroy(&pf->qp_pool);
1371 err_qp_pool_init:
1372 err_parameter_init:
1373 err_get_capabilities:
1374         (void)i40e_shutdown_adminq(hw);
1375
1376         return ret;
1377 }
1378
1379 static void
1380 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1381 {
1382         struct i40e_ethertype_filter *p_ethertype;
1383         struct i40e_ethertype_rule *ethertype_rule;
1384
1385         ethertype_rule = &pf->ethertype;
1386         /* Remove all ethertype filter rules and hash */
1387         if (ethertype_rule->hash_map)
1388                 rte_free(ethertype_rule->hash_map);
1389         if (ethertype_rule->hash_table)
1390                 rte_hash_free(ethertype_rule->hash_table);
1391
1392         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1393                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1394                              p_ethertype, rules);
1395                 rte_free(p_ethertype);
1396         }
1397 }
1398
1399 static void
1400 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1401 {
1402         struct i40e_tunnel_filter *p_tunnel;
1403         struct i40e_tunnel_rule *tunnel_rule;
1404
1405         tunnel_rule = &pf->tunnel;
1406         /* Remove all tunnel director rules and hash */
1407         if (tunnel_rule->hash_map)
1408                 rte_free(tunnel_rule->hash_map);
1409         if (tunnel_rule->hash_table)
1410                 rte_hash_free(tunnel_rule->hash_table);
1411
1412         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1413                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1414                 rte_free(p_tunnel);
1415         }
1416 }
1417
1418 static void
1419 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1420 {
1421         struct i40e_fdir_filter *p_fdir;
1422         struct i40e_fdir_info *fdir_info;
1423
1424         fdir_info = &pf->fdir;
1425         /* Remove all flow director rules and hash */
1426         if (fdir_info->hash_map)
1427                 rte_free(fdir_info->hash_map);
1428         if (fdir_info->hash_table)
1429                 rte_hash_free(fdir_info->hash_table);
1430
1431         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1432                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1433                 rte_free(p_fdir);
1434         }
1435 }
1436
1437 static int
1438 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1439 {
1440         struct i40e_pf *pf;
1441         struct rte_pci_device *pci_dev;
1442         struct rte_intr_handle *intr_handle;
1443         struct i40e_hw *hw;
1444         struct i40e_filter_control_settings settings;
1445         struct rte_flow *p_flow;
1446         int ret;
1447         uint8_t aq_fail = 0;
1448
1449         PMD_INIT_FUNC_TRACE();
1450
1451         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1452                 return 0;
1453
1454         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1455         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1456         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1457         intr_handle = &pci_dev->intr_handle;
1458
1459         if (hw->adapter_stopped == 0)
1460                 i40e_dev_close(dev);
1461
1462         dev->dev_ops = NULL;
1463         dev->rx_pkt_burst = NULL;
1464         dev->tx_pkt_burst = NULL;
1465
1466         /* Clear PXE mode */
1467         i40e_clear_pxe_mode(hw);
1468
1469         /* Unconfigure filter control */
1470         memset(&settings, 0, sizeof(settings));
1471         ret = i40e_set_filter_control(hw, &settings);
1472         if (ret)
1473                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1474                                         ret);
1475
1476         /* Disable flow control */
1477         hw->fc.requested_mode = I40E_FC_NONE;
1478         i40e_set_fc(hw, &aq_fail, TRUE);
1479
1480         /* uninitialize pf host driver */
1481         i40e_pf_host_uninit(dev);
1482
1483         rte_free(dev->data->mac_addrs);
1484         dev->data->mac_addrs = NULL;
1485
1486         /* disable uio intr before callback unregister */
1487         rte_intr_disable(intr_handle);
1488
1489         /* register callback func to eal lib */
1490         rte_intr_callback_unregister(intr_handle,
1491                                      i40e_dev_interrupt_handler, dev);
1492
1493         i40e_rm_ethtype_filter_list(pf);
1494         i40e_rm_tunnel_filter_list(pf);
1495         i40e_rm_fdir_filter_list(pf);
1496
1497         /* Remove all flows */
1498         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1499                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1500                 rte_free(p_flow);
1501         }
1502
1503         /* Remove all Traffic Manager configuration */
1504         i40e_tm_conf_uninit(dev);
1505
1506         return 0;
1507 }
1508
1509 static int
1510 i40e_dev_configure(struct rte_eth_dev *dev)
1511 {
1512         struct i40e_adapter *ad =
1513                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1514         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1515         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1516         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1517         int i, ret;
1518
1519         ret = i40e_dev_sync_phy_type(hw);
1520         if (ret)
1521                 return ret;
1522
1523         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1524          * bulk allocation or vector Rx preconditions we will reset it.
1525          */
1526         ad->rx_bulk_alloc_allowed = true;
1527         ad->rx_vec_allowed = true;
1528         ad->tx_simple_allowed = true;
1529         ad->tx_vec_allowed = true;
1530
1531         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1532                 ret = i40e_fdir_setup(pf);
1533                 if (ret != I40E_SUCCESS) {
1534                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1535                         return -ENOTSUP;
1536                 }
1537                 ret = i40e_fdir_configure(dev);
1538                 if (ret < 0) {
1539                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1540                         goto err;
1541                 }
1542         } else
1543                 i40e_fdir_teardown(pf);
1544
1545         ret = i40e_dev_init_vlan(dev);
1546         if (ret < 0)
1547                 goto err;
1548
1549         /* VMDQ setup.
1550          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1551          *  RSS setting have different requirements.
1552          *  General PMD driver call sequence are NIC init, configure,
1553          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1554          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1555          *  applicable. So, VMDQ setting has to be done before
1556          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1557          *  For RSS setting, it will try to calculate actual configured RX queue
1558          *  number, which will be available after rx_queue_setup(). dev_start()
1559          *  function is good to place RSS setup.
1560          */
1561         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1562                 ret = i40e_vmdq_setup(dev);
1563                 if (ret)
1564                         goto err;
1565         }
1566
1567         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1568                 ret = i40e_dcb_setup(dev);
1569                 if (ret) {
1570                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1571                         goto err_dcb;
1572                 }
1573         }
1574
1575         TAILQ_INIT(&pf->flow_list);
1576
1577         return 0;
1578
1579 err_dcb:
1580         /* need to release vmdq resource if exists */
1581         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1582                 i40e_vsi_release(pf->vmdq[i].vsi);
1583                 pf->vmdq[i].vsi = NULL;
1584         }
1585         rte_free(pf->vmdq);
1586         pf->vmdq = NULL;
1587 err:
1588         /* need to release fdir resource if exists */
1589         i40e_fdir_teardown(pf);
1590         return ret;
1591 }
1592
1593 void
1594 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1595 {
1596         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1597         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1598         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1599         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1600         uint16_t msix_vect = vsi->msix_intr;
1601         uint16_t i;
1602
1603         for (i = 0; i < vsi->nb_qps; i++) {
1604                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1605                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1606                 rte_wmb();
1607         }
1608
1609         if (vsi->type != I40E_VSI_SRIOV) {
1610                 if (!rte_intr_allow_others(intr_handle)) {
1611                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1612                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1613                         I40E_WRITE_REG(hw,
1614                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1615                                        0);
1616                 } else {
1617                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1618                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1619                         I40E_WRITE_REG(hw,
1620                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1621                                                        msix_vect - 1), 0);
1622                 }
1623         } else {
1624                 uint32_t reg;
1625                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1626                         vsi->user_param + (msix_vect - 1);
1627
1628                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1629                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1630         }
1631         I40E_WRITE_FLUSH(hw);
1632 }
1633
1634 static void
1635 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1636                        int base_queue, int nb_queue,
1637                        uint16_t itr_idx)
1638 {
1639         int i;
1640         uint32_t val;
1641         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1642
1643         /* Bind all RX queues to allocated MSIX interrupt */
1644         for (i = 0; i < nb_queue; i++) {
1645                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1646                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1647                         ((base_queue + i + 1) <<
1648                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1649                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1650                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1651
1652                 if (i == nb_queue - 1)
1653                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1654                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1655         }
1656
1657         /* Write first RX queue to Link list register as the head element */
1658         if (vsi->type != I40E_VSI_SRIOV) {
1659                 uint16_t interval =
1660                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1661
1662                 if (msix_vect == I40E_MISC_VEC_ID) {
1663                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1664                                        (base_queue <<
1665                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1666                                        (0x0 <<
1667                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1668                         I40E_WRITE_REG(hw,
1669                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1670                                        interval);
1671                 } else {
1672                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1673                                        (base_queue <<
1674                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1675                                        (0x0 <<
1676                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1677                         I40E_WRITE_REG(hw,
1678                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1679                                                        msix_vect - 1),
1680                                        interval);
1681                 }
1682         } else {
1683                 uint32_t reg;
1684
1685                 if (msix_vect == I40E_MISC_VEC_ID) {
1686                         I40E_WRITE_REG(hw,
1687                                        I40E_VPINT_LNKLST0(vsi->user_param),
1688                                        (base_queue <<
1689                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1690                                        (0x0 <<
1691                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1692                 } else {
1693                         /* num_msix_vectors_vf needs to minus irq0 */
1694                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1695                                 vsi->user_param + (msix_vect - 1);
1696
1697                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1698                                        (base_queue <<
1699                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1700                                        (0x0 <<
1701                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1702                 }
1703         }
1704
1705         I40E_WRITE_FLUSH(hw);
1706 }
1707
1708 void
1709 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1710 {
1711         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1712         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1713         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1714         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1715         uint16_t msix_vect = vsi->msix_intr;
1716         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1717         uint16_t queue_idx = 0;
1718         int record = 0;
1719         uint32_t val;
1720         int i;
1721
1722         for (i = 0; i < vsi->nb_qps; i++) {
1723                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1724                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1725         }
1726
1727         /* INTENA flag is not auto-cleared for interrupt */
1728         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1729         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1730                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1731                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1732         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1733
1734         /* VF bind interrupt */
1735         if (vsi->type == I40E_VSI_SRIOV) {
1736                 __vsi_queues_bind_intr(vsi, msix_vect,
1737                                        vsi->base_queue, vsi->nb_qps,
1738                                        itr_idx);
1739                 return;
1740         }
1741
1742         /* PF & VMDq bind interrupt */
1743         if (rte_intr_dp_is_en(intr_handle)) {
1744                 if (vsi->type == I40E_VSI_MAIN) {
1745                         queue_idx = 0;
1746                         record = 1;
1747                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1748                         struct i40e_vsi *main_vsi =
1749                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1750                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1751                         record = 1;
1752                 }
1753         }
1754
1755         for (i = 0; i < vsi->nb_used_qps; i++) {
1756                 if (nb_msix <= 1) {
1757                         if (!rte_intr_allow_others(intr_handle))
1758                                 /* allow to share MISC_VEC_ID */
1759                                 msix_vect = I40E_MISC_VEC_ID;
1760
1761                         /* no enough msix_vect, map all to one */
1762                         __vsi_queues_bind_intr(vsi, msix_vect,
1763                                                vsi->base_queue + i,
1764                                                vsi->nb_used_qps - i,
1765                                                itr_idx);
1766                         for (; !!record && i < vsi->nb_used_qps; i++)
1767                                 intr_handle->intr_vec[queue_idx + i] =
1768                                         msix_vect;
1769                         break;
1770                 }
1771                 /* 1:1 queue/msix_vect mapping */
1772                 __vsi_queues_bind_intr(vsi, msix_vect,
1773                                        vsi->base_queue + i, 1,
1774                                        itr_idx);
1775                 if (!!record)
1776                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1777
1778                 msix_vect++;
1779                 nb_msix--;
1780         }
1781 }
1782
1783 static void
1784 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1785 {
1786         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1787         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1788         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1789         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1790         uint16_t interval = i40e_calc_itr_interval(\
1791                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1792         uint16_t msix_intr, i;
1793
1794         if (rte_intr_allow_others(intr_handle))
1795                 for (i = 0; i < vsi->nb_msix; i++) {
1796                         msix_intr = vsi->msix_intr + i;
1797                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1798                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1799                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1800                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1801                                 (interval <<
1802                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1803                 }
1804         else
1805                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1806                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1807                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1808                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1809                                (interval <<
1810                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1811
1812         I40E_WRITE_FLUSH(hw);
1813 }
1814
1815 static void
1816 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1817 {
1818         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1819         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1820         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1821         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1822         uint16_t msix_intr, i;
1823
1824         if (rte_intr_allow_others(intr_handle))
1825                 for (i = 0; i < vsi->nb_msix; i++) {
1826                         msix_intr = vsi->msix_intr + i;
1827                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1828                                        0);
1829                 }
1830         else
1831                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1832
1833         I40E_WRITE_FLUSH(hw);
1834 }
1835
1836 static inline uint8_t
1837 i40e_parse_link_speeds(uint16_t link_speeds)
1838 {
1839         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1840
1841         if (link_speeds & ETH_LINK_SPEED_40G)
1842                 link_speed |= I40E_LINK_SPEED_40GB;
1843         if (link_speeds & ETH_LINK_SPEED_25G)
1844                 link_speed |= I40E_LINK_SPEED_25GB;
1845         if (link_speeds & ETH_LINK_SPEED_20G)
1846                 link_speed |= I40E_LINK_SPEED_20GB;
1847         if (link_speeds & ETH_LINK_SPEED_10G)
1848                 link_speed |= I40E_LINK_SPEED_10GB;
1849         if (link_speeds & ETH_LINK_SPEED_1G)
1850                 link_speed |= I40E_LINK_SPEED_1GB;
1851         if (link_speeds & ETH_LINK_SPEED_100M)
1852                 link_speed |= I40E_LINK_SPEED_100MB;
1853
1854         return link_speed;
1855 }
1856
1857 static int
1858 i40e_phy_conf_link(struct i40e_hw *hw,
1859                    uint8_t abilities,
1860                    uint8_t force_speed,
1861                    bool is_up)
1862 {
1863         enum i40e_status_code status;
1864         struct i40e_aq_get_phy_abilities_resp phy_ab;
1865         struct i40e_aq_set_phy_config phy_conf;
1866         enum i40e_aq_phy_type cnt;
1867         uint32_t phy_type_mask = 0;
1868
1869         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1870                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1871                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1872                         I40E_AQ_PHY_FLAG_LOW_POWER;
1873         const uint8_t advt = I40E_LINK_SPEED_40GB |
1874                         I40E_LINK_SPEED_25GB |
1875                         I40E_LINK_SPEED_10GB |
1876                         I40E_LINK_SPEED_1GB |
1877                         I40E_LINK_SPEED_100MB;
1878         int ret = -ENOTSUP;
1879
1880
1881         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1882                                               NULL);
1883         if (status)
1884                 return ret;
1885
1886         /* If link already up, no need to set up again */
1887         if (is_up && phy_ab.phy_type != 0)
1888                 return I40E_SUCCESS;
1889
1890         memset(&phy_conf, 0, sizeof(phy_conf));
1891
1892         /* bits 0-2 use the values from get_phy_abilities_resp */
1893         abilities &= ~mask;
1894         abilities |= phy_ab.abilities & mask;
1895
1896         /* update ablities and speed */
1897         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1898                 phy_conf.link_speed = advt;
1899         else
1900                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1901
1902         phy_conf.abilities = abilities;
1903
1904
1905
1906         /* To enable link, phy_type mask needs to include each type */
1907         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1908                 phy_type_mask |= 1 << cnt;
1909
1910         /* use get_phy_abilities_resp value for the rest */
1911         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1912         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1913                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1914                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1915         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1916         phy_conf.eee_capability = phy_ab.eee_capability;
1917         phy_conf.eeer = phy_ab.eeer_val;
1918         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1919
1920         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1921                     phy_ab.abilities, phy_ab.link_speed);
1922         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1923                     phy_conf.abilities, phy_conf.link_speed);
1924
1925         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1926         if (status)
1927                 return ret;
1928
1929         return I40E_SUCCESS;
1930 }
1931
1932 static int
1933 i40e_apply_link_speed(struct rte_eth_dev *dev)
1934 {
1935         uint8_t speed;
1936         uint8_t abilities = 0;
1937         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938         struct rte_eth_conf *conf = &dev->data->dev_conf;
1939
1940         speed = i40e_parse_link_speeds(conf->link_speeds);
1941         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1942         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1943                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1944         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1945
1946         return i40e_phy_conf_link(hw, abilities, speed, true);
1947 }
1948
1949 static int
1950 i40e_dev_start(struct rte_eth_dev *dev)
1951 {
1952         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1953         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1954         struct i40e_vsi *main_vsi = pf->main_vsi;
1955         int ret, i;
1956         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1957         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1958         uint32_t intr_vector = 0;
1959         struct i40e_vsi *vsi;
1960
1961         hw->adapter_stopped = 0;
1962
1963         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1964                 PMD_INIT_LOG(ERR,
1965                 "Invalid link_speeds for port %u, autonegotiation disabled",
1966                               dev->data->port_id);
1967                 return -EINVAL;
1968         }
1969
1970         rte_intr_disable(intr_handle);
1971
1972         if ((rte_intr_cap_multiple(intr_handle) ||
1973              !RTE_ETH_DEV_SRIOV(dev).active) &&
1974             dev->data->dev_conf.intr_conf.rxq != 0) {
1975                 intr_vector = dev->data->nb_rx_queues;
1976                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1977                 if (ret)
1978                         return ret;
1979         }
1980
1981         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1982                 intr_handle->intr_vec =
1983                         rte_zmalloc("intr_vec",
1984                                     dev->data->nb_rx_queues * sizeof(int),
1985                                     0);
1986                 if (!intr_handle->intr_vec) {
1987                         PMD_INIT_LOG(ERR,
1988                                 "Failed to allocate %d rx_queues intr_vec",
1989                                 dev->data->nb_rx_queues);
1990                         return -ENOMEM;
1991                 }
1992         }
1993
1994         /* Initialize VSI */
1995         ret = i40e_dev_rxtx_init(pf);
1996         if (ret != I40E_SUCCESS) {
1997                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1998                 goto err_up;
1999         }
2000
2001         /* Map queues with MSIX interrupt */
2002         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2003                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2004         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2005         i40e_vsi_enable_queues_intr(main_vsi);
2006
2007         /* Map VMDQ VSI queues with MSIX interrupt */
2008         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2009                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2010                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2011                                           I40E_ITR_INDEX_DEFAULT);
2012                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2013         }
2014
2015         /* enable FDIR MSIX interrupt */
2016         if (pf->fdir.fdir_vsi) {
2017                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2018                                           I40E_ITR_INDEX_NONE);
2019                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2020         }
2021
2022         /* Enable all queues which have been configured */
2023         ret = i40e_dev_switch_queues(pf, TRUE);
2024         if (ret != I40E_SUCCESS) {
2025                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2026                 goto err_up;
2027         }
2028
2029         /* Enable receiving broadcast packets */
2030         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2031         if (ret != I40E_SUCCESS)
2032                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2033
2034         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2035                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2036                                                 true, NULL);
2037                 if (ret != I40E_SUCCESS)
2038                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2039         }
2040
2041         /* Enable the VLAN promiscuous mode. */
2042         if (pf->vfs) {
2043                 for (i = 0; i < pf->vf_num; i++) {
2044                         vsi = pf->vfs[i].vsi;
2045                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2046                                                      true, NULL);
2047                 }
2048         }
2049
2050         /* Apply link configure */
2051         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2052                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2053                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2054                                 ETH_LINK_SPEED_40G)) {
2055                 PMD_DRV_LOG(ERR, "Invalid link setting");
2056                 goto err_up;
2057         }
2058         ret = i40e_apply_link_speed(dev);
2059         if (I40E_SUCCESS != ret) {
2060                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2061                 goto err_up;
2062         }
2063
2064         if (!rte_intr_allow_others(intr_handle)) {
2065                 rte_intr_callback_unregister(intr_handle,
2066                                              i40e_dev_interrupt_handler,
2067                                              (void *)dev);
2068                 /* configure and enable device interrupt */
2069                 i40e_pf_config_irq0(hw, FALSE);
2070                 i40e_pf_enable_irq0(hw);
2071
2072                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2073                         PMD_INIT_LOG(INFO,
2074                                 "lsc won't enable because of no intr multiplex");
2075         } else {
2076                 ret = i40e_aq_set_phy_int_mask(hw,
2077                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2078                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2079                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2080                 if (ret != I40E_SUCCESS)
2081                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2082
2083                 /* Call get_link_info aq commond to enable/disable LSE */
2084                 i40e_dev_link_update(dev, 0);
2085         }
2086
2087         /* enable uio intr after callback register */
2088         rte_intr_enable(intr_handle);
2089
2090         i40e_filter_restore(pf);
2091
2092         if (pf->tm_conf.root && !pf->tm_conf.committed)
2093                 PMD_DRV_LOG(WARNING,
2094                             "please call hierarchy_commit() "
2095                             "before starting the port");
2096
2097         return I40E_SUCCESS;
2098
2099 err_up:
2100         i40e_dev_switch_queues(pf, FALSE);
2101         i40e_dev_clear_queues(dev);
2102
2103         return ret;
2104 }
2105
2106 static void
2107 i40e_dev_stop(struct rte_eth_dev *dev)
2108 {
2109         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2110         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2111         struct i40e_vsi *main_vsi = pf->main_vsi;
2112         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2113         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2114         int i;
2115
2116         if (hw->adapter_stopped == 1)
2117                 return;
2118         /* Disable all queues */
2119         i40e_dev_switch_queues(pf, FALSE);
2120
2121         /* un-map queues with interrupt registers */
2122         i40e_vsi_disable_queues_intr(main_vsi);
2123         i40e_vsi_queues_unbind_intr(main_vsi);
2124
2125         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2126                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2127                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2128         }
2129
2130         if (pf->fdir.fdir_vsi) {
2131                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2132                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2133         }
2134         /* Clear all queues and release memory */
2135         i40e_dev_clear_queues(dev);
2136
2137         /* Set link down */
2138         i40e_dev_set_link_down(dev);
2139
2140         if (!rte_intr_allow_others(intr_handle))
2141                 /* resume to the default handler */
2142                 rte_intr_callback_register(intr_handle,
2143                                            i40e_dev_interrupt_handler,
2144                                            (void *)dev);
2145
2146         /* Clean datapath event and queue/vec mapping */
2147         rte_intr_efd_disable(intr_handle);
2148         if (intr_handle->intr_vec) {
2149                 rte_free(intr_handle->intr_vec);
2150                 intr_handle->intr_vec = NULL;
2151         }
2152
2153         /* reset hierarchy commit */
2154         pf->tm_conf.committed = false;
2155
2156         /* Remove all the queue region configuration */
2157         i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
2158
2159         hw->adapter_stopped = 1;
2160 }
2161
2162 static void
2163 i40e_dev_close(struct rte_eth_dev *dev)
2164 {
2165         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2166         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2167         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2168         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2169         struct i40e_mirror_rule *p_mirror;
2170         uint32_t reg;
2171         int i;
2172         int ret;
2173
2174         PMD_INIT_FUNC_TRACE();
2175
2176         i40e_dev_stop(dev);
2177
2178         /* Remove all mirror rules */
2179         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2180                 ret = i40e_aq_del_mirror_rule(hw,
2181                                               pf->main_vsi->veb->seid,
2182                                               p_mirror->rule_type,
2183                                               p_mirror->entries,
2184                                               p_mirror->num_entries,
2185                                               p_mirror->id);
2186                 if (ret < 0)
2187                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2188                                     "status = %d, aq_err = %d.", ret,
2189                                     hw->aq.asq_last_status);
2190
2191                 /* remove mirror software resource anyway */
2192                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2193                 rte_free(p_mirror);
2194                 pf->nb_mirror_rule--;
2195         }
2196
2197         i40e_dev_free_queues(dev);
2198
2199         /* Disable interrupt */
2200         i40e_pf_disable_irq0(hw);
2201         rte_intr_disable(intr_handle);
2202
2203         /* shutdown and destroy the HMC */
2204         i40e_shutdown_lan_hmc(hw);
2205
2206         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2207                 i40e_vsi_release(pf->vmdq[i].vsi);
2208                 pf->vmdq[i].vsi = NULL;
2209         }
2210         rte_free(pf->vmdq);
2211         pf->vmdq = NULL;
2212
2213         /* release all the existing VSIs and VEBs */
2214         i40e_fdir_teardown(pf);
2215         i40e_vsi_release(pf->main_vsi);
2216
2217         /* shutdown the adminq */
2218         i40e_aq_queue_shutdown(hw, true);
2219         i40e_shutdown_adminq(hw);
2220
2221         i40e_res_pool_destroy(&pf->qp_pool);
2222         i40e_res_pool_destroy(&pf->msix_pool);
2223
2224         /* force a PF reset to clean anything leftover */
2225         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2226         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2227                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2228         I40E_WRITE_FLUSH(hw);
2229 }
2230
2231 /*
2232  * Reset PF device only to re-initialize resources in PMD layer
2233  */
2234 static int
2235 i40e_dev_reset(struct rte_eth_dev *dev)
2236 {
2237         int ret;
2238
2239         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2240          * its VF to make them align with it. The detailed notification
2241          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2242          * To avoid unexpected behavior in VF, currently reset of PF with
2243          * SR-IOV activation is not supported. It might be supported later.
2244          */
2245         if (dev->data->sriov.active)
2246                 return -ENOTSUP;
2247
2248         ret = eth_i40e_dev_uninit(dev);
2249         if (ret)
2250                 return ret;
2251
2252         ret = eth_i40e_dev_init(dev);
2253
2254         return ret;
2255 }
2256
2257 static void
2258 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2259 {
2260         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2261         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2262         struct i40e_vsi *vsi = pf->main_vsi;
2263         int status;
2264
2265         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2266                                                      true, NULL, true);
2267         if (status != I40E_SUCCESS)
2268                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2269
2270         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2271                                                         TRUE, NULL);
2272         if (status != I40E_SUCCESS)
2273                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2274
2275 }
2276
2277 static void
2278 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2279 {
2280         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2281         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2282         struct i40e_vsi *vsi = pf->main_vsi;
2283         int status;
2284
2285         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2286                                                      false, NULL, true);
2287         if (status != I40E_SUCCESS)
2288                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2289
2290         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2291                                                         false, NULL);
2292         if (status != I40E_SUCCESS)
2293                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2294 }
2295
2296 static void
2297 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2298 {
2299         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2300         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2301         struct i40e_vsi *vsi = pf->main_vsi;
2302         int ret;
2303
2304         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2305         if (ret != I40E_SUCCESS)
2306                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2307 }
2308
2309 static void
2310 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2311 {
2312         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2313         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2314         struct i40e_vsi *vsi = pf->main_vsi;
2315         int ret;
2316
2317         if (dev->data->promiscuous == 1)
2318                 return; /* must remain in all_multicast mode */
2319
2320         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2321                                 vsi->seid, FALSE, NULL);
2322         if (ret != I40E_SUCCESS)
2323                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2324 }
2325
2326 /*
2327  * Set device link up.
2328  */
2329 static int
2330 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2331 {
2332         /* re-apply link speed setting */
2333         return i40e_apply_link_speed(dev);
2334 }
2335
2336 /*
2337  * Set device link down.
2338  */
2339 static int
2340 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2341 {
2342         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2343         uint8_t abilities = 0;
2344         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2345
2346         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2347         return i40e_phy_conf_link(hw, abilities, speed, false);
2348 }
2349
2350 int
2351 i40e_dev_link_update(struct rte_eth_dev *dev,
2352                      int wait_to_complete)
2353 {
2354 #define CHECK_INTERVAL 100  /* 100ms */
2355 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2356         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2357         struct i40e_link_status link_status;
2358         struct rte_eth_link link, old;
2359         int status;
2360         unsigned rep_cnt = MAX_REPEAT_TIME;
2361         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2362
2363         memset(&link, 0, sizeof(link));
2364         memset(&old, 0, sizeof(old));
2365         memset(&link_status, 0, sizeof(link_status));
2366         rte_i40e_dev_atomic_read_link_status(dev, &old);
2367
2368         do {
2369                 /* Get link status information from hardware */
2370                 status = i40e_aq_get_link_info(hw, enable_lse,
2371                                                 &link_status, NULL);
2372                 if (status != I40E_SUCCESS) {
2373                         link.link_speed = ETH_SPEED_NUM_100M;
2374                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2375                         PMD_DRV_LOG(ERR, "Failed to get link info");
2376                         goto out;
2377                 }
2378
2379                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2380                 if (!wait_to_complete || link.link_status)
2381                         break;
2382
2383                 rte_delay_ms(CHECK_INTERVAL);
2384         } while (--rep_cnt);
2385
2386         if (!link.link_status)
2387                 goto out;
2388
2389         /* i40e uses full duplex only */
2390         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2391
2392         /* Parse the link status */
2393         switch (link_status.link_speed) {
2394         case I40E_LINK_SPEED_100MB:
2395                 link.link_speed = ETH_SPEED_NUM_100M;
2396                 break;
2397         case I40E_LINK_SPEED_1GB:
2398                 link.link_speed = ETH_SPEED_NUM_1G;
2399                 break;
2400         case I40E_LINK_SPEED_10GB:
2401                 link.link_speed = ETH_SPEED_NUM_10G;
2402                 break;
2403         case I40E_LINK_SPEED_20GB:
2404                 link.link_speed = ETH_SPEED_NUM_20G;
2405                 break;
2406         case I40E_LINK_SPEED_25GB:
2407                 link.link_speed = ETH_SPEED_NUM_25G;
2408                 break;
2409         case I40E_LINK_SPEED_40GB:
2410                 link.link_speed = ETH_SPEED_NUM_40G;
2411                 break;
2412         default:
2413                 link.link_speed = ETH_SPEED_NUM_100M;
2414                 break;
2415         }
2416
2417         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2418                         ETH_LINK_SPEED_FIXED);
2419
2420 out:
2421         rte_i40e_dev_atomic_write_link_status(dev, &link);
2422         if (link.link_status == old.link_status)
2423                 return -1;
2424
2425         i40e_notify_all_vfs_link_status(dev);
2426
2427         return 0;
2428 }
2429
2430 /* Get all the statistics of a VSI */
2431 void
2432 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2433 {
2434         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2435         struct i40e_eth_stats *nes = &vsi->eth_stats;
2436         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2437         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2438
2439         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2440                             vsi->offset_loaded, &oes->rx_bytes,
2441                             &nes->rx_bytes);
2442         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2443                             vsi->offset_loaded, &oes->rx_unicast,
2444                             &nes->rx_unicast);
2445         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2446                             vsi->offset_loaded, &oes->rx_multicast,
2447                             &nes->rx_multicast);
2448         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2449                             vsi->offset_loaded, &oes->rx_broadcast,
2450                             &nes->rx_broadcast);
2451         /* exclude CRC bytes */
2452         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2453                 nes->rx_broadcast) * ETHER_CRC_LEN;
2454
2455         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2456                             &oes->rx_discards, &nes->rx_discards);
2457         /* GLV_REPC not supported */
2458         /* GLV_RMPC not supported */
2459         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2460                             &oes->rx_unknown_protocol,
2461                             &nes->rx_unknown_protocol);
2462         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2463                             vsi->offset_loaded, &oes->tx_bytes,
2464                             &nes->tx_bytes);
2465         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2466                             vsi->offset_loaded, &oes->tx_unicast,
2467                             &nes->tx_unicast);
2468         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2469                             vsi->offset_loaded, &oes->tx_multicast,
2470                             &nes->tx_multicast);
2471         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2472                             vsi->offset_loaded,  &oes->tx_broadcast,
2473                             &nes->tx_broadcast);
2474         /* GLV_TDPC not supported */
2475         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2476                             &oes->tx_errors, &nes->tx_errors);
2477         vsi->offset_loaded = true;
2478
2479         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2480                     vsi->vsi_id);
2481         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2482         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2483         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2484         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2485         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2486         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2487                     nes->rx_unknown_protocol);
2488         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2489         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2490         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2491         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2492         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2493         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2494         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2495                     vsi->vsi_id);
2496 }
2497
2498 static void
2499 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2500 {
2501         unsigned int i;
2502         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2503         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2504
2505         /* Get rx/tx bytes of internal transfer packets */
2506         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2507                         I40E_GLV_GORCL(hw->port),
2508                         pf->offset_loaded,
2509                         &pf->internal_stats_offset.rx_bytes,
2510                         &pf->internal_stats.rx_bytes);
2511
2512         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2513                         I40E_GLV_GOTCL(hw->port),
2514                         pf->offset_loaded,
2515                         &pf->internal_stats_offset.tx_bytes,
2516                         &pf->internal_stats.tx_bytes);
2517         /* Get total internal rx packet count */
2518         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2519                             I40E_GLV_UPRCL(hw->port),
2520                             pf->offset_loaded,
2521                             &pf->internal_stats_offset.rx_unicast,
2522                             &pf->internal_stats.rx_unicast);
2523         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2524                             I40E_GLV_MPRCL(hw->port),
2525                             pf->offset_loaded,
2526                             &pf->internal_stats_offset.rx_multicast,
2527                             &pf->internal_stats.rx_multicast);
2528         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2529                             I40E_GLV_BPRCL(hw->port),
2530                             pf->offset_loaded,
2531                             &pf->internal_stats_offset.rx_broadcast,
2532                             &pf->internal_stats.rx_broadcast);
2533
2534         /* exclude CRC size */
2535         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2536                 pf->internal_stats.rx_multicast +
2537                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2538
2539         /* Get statistics of struct i40e_eth_stats */
2540         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2541                             I40E_GLPRT_GORCL(hw->port),
2542                             pf->offset_loaded, &os->eth.rx_bytes,
2543                             &ns->eth.rx_bytes);
2544         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2545                             I40E_GLPRT_UPRCL(hw->port),
2546                             pf->offset_loaded, &os->eth.rx_unicast,
2547                             &ns->eth.rx_unicast);
2548         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2549                             I40E_GLPRT_MPRCL(hw->port),
2550                             pf->offset_loaded, &os->eth.rx_multicast,
2551                             &ns->eth.rx_multicast);
2552         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2553                             I40E_GLPRT_BPRCL(hw->port),
2554                             pf->offset_loaded, &os->eth.rx_broadcast,
2555                             &ns->eth.rx_broadcast);
2556         /* Workaround: CRC size should not be included in byte statistics,
2557          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2558          */
2559         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2560                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2561
2562         /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2563          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2564          * value.
2565          */
2566         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2567                 ns->eth.rx_bytes = 0;
2568         /* exlude internal rx bytes */
2569         else
2570                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2571
2572         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2573                             pf->offset_loaded, &os->eth.rx_discards,
2574                             &ns->eth.rx_discards);
2575         /* GLPRT_REPC not supported */
2576         /* GLPRT_RMPC not supported */
2577         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2578                             pf->offset_loaded,
2579                             &os->eth.rx_unknown_protocol,
2580                             &ns->eth.rx_unknown_protocol);
2581         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2582                             I40E_GLPRT_GOTCL(hw->port),
2583                             pf->offset_loaded, &os->eth.tx_bytes,
2584                             &ns->eth.tx_bytes);
2585         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2586                             I40E_GLPRT_UPTCL(hw->port),
2587                             pf->offset_loaded, &os->eth.tx_unicast,
2588                             &ns->eth.tx_unicast);
2589         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2590                             I40E_GLPRT_MPTCL(hw->port),
2591                             pf->offset_loaded, &os->eth.tx_multicast,
2592                             &ns->eth.tx_multicast);
2593         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2594                             I40E_GLPRT_BPTCL(hw->port),
2595                             pf->offset_loaded, &os->eth.tx_broadcast,
2596                             &ns->eth.tx_broadcast);
2597         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2598                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2599
2600         /* exclude internal tx bytes */
2601         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2602                 ns->eth.tx_bytes = 0;
2603         else
2604                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2605
2606         /* GLPRT_TEPC not supported */
2607
2608         /* additional port specific stats */
2609         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2610                             pf->offset_loaded, &os->tx_dropped_link_down,
2611                             &ns->tx_dropped_link_down);
2612         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2613                             pf->offset_loaded, &os->crc_errors,
2614                             &ns->crc_errors);
2615         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2616                             pf->offset_loaded, &os->illegal_bytes,
2617                             &ns->illegal_bytes);
2618         /* GLPRT_ERRBC not supported */
2619         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2620                             pf->offset_loaded, &os->mac_local_faults,
2621                             &ns->mac_local_faults);
2622         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2623                             pf->offset_loaded, &os->mac_remote_faults,
2624                             &ns->mac_remote_faults);
2625         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2626                             pf->offset_loaded, &os->rx_length_errors,
2627                             &ns->rx_length_errors);
2628         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2629                             pf->offset_loaded, &os->link_xon_rx,
2630                             &ns->link_xon_rx);
2631         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2632                             pf->offset_loaded, &os->link_xoff_rx,
2633                             &ns->link_xoff_rx);
2634         for (i = 0; i < 8; i++) {
2635                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2636                                     pf->offset_loaded,
2637                                     &os->priority_xon_rx[i],
2638                                     &ns->priority_xon_rx[i]);
2639                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2640                                     pf->offset_loaded,
2641                                     &os->priority_xoff_rx[i],
2642                                     &ns->priority_xoff_rx[i]);
2643         }
2644         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2645                             pf->offset_loaded, &os->link_xon_tx,
2646                             &ns->link_xon_tx);
2647         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2648                             pf->offset_loaded, &os->link_xoff_tx,
2649                             &ns->link_xoff_tx);
2650         for (i = 0; i < 8; i++) {
2651                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2652                                     pf->offset_loaded,
2653                                     &os->priority_xon_tx[i],
2654                                     &ns->priority_xon_tx[i]);
2655                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2656                                     pf->offset_loaded,
2657                                     &os->priority_xoff_tx[i],
2658                                     &ns->priority_xoff_tx[i]);
2659                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2660                                     pf->offset_loaded,
2661                                     &os->priority_xon_2_xoff[i],
2662                                     &ns->priority_xon_2_xoff[i]);
2663         }
2664         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2665                             I40E_GLPRT_PRC64L(hw->port),
2666                             pf->offset_loaded, &os->rx_size_64,
2667                             &ns->rx_size_64);
2668         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2669                             I40E_GLPRT_PRC127L(hw->port),
2670                             pf->offset_loaded, &os->rx_size_127,
2671                             &ns->rx_size_127);
2672         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2673                             I40E_GLPRT_PRC255L(hw->port),
2674                             pf->offset_loaded, &os->rx_size_255,
2675                             &ns->rx_size_255);
2676         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2677                             I40E_GLPRT_PRC511L(hw->port),
2678                             pf->offset_loaded, &os->rx_size_511,
2679                             &ns->rx_size_511);
2680         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2681                             I40E_GLPRT_PRC1023L(hw->port),
2682                             pf->offset_loaded, &os->rx_size_1023,
2683                             &ns->rx_size_1023);
2684         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2685                             I40E_GLPRT_PRC1522L(hw->port),
2686                             pf->offset_loaded, &os->rx_size_1522,
2687                             &ns->rx_size_1522);
2688         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2689                             I40E_GLPRT_PRC9522L(hw->port),
2690                             pf->offset_loaded, &os->rx_size_big,
2691                             &ns->rx_size_big);
2692         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2693                             pf->offset_loaded, &os->rx_undersize,
2694                             &ns->rx_undersize);
2695         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2696                             pf->offset_loaded, &os->rx_fragments,
2697                             &ns->rx_fragments);
2698         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2699                             pf->offset_loaded, &os->rx_oversize,
2700                             &ns->rx_oversize);
2701         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2702                             pf->offset_loaded, &os->rx_jabber,
2703                             &ns->rx_jabber);
2704         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2705                             I40E_GLPRT_PTC64L(hw->port),
2706                             pf->offset_loaded, &os->tx_size_64,
2707                             &ns->tx_size_64);
2708         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2709                             I40E_GLPRT_PTC127L(hw->port),
2710                             pf->offset_loaded, &os->tx_size_127,
2711                             &ns->tx_size_127);
2712         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2713                             I40E_GLPRT_PTC255L(hw->port),
2714                             pf->offset_loaded, &os->tx_size_255,
2715                             &ns->tx_size_255);
2716         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2717                             I40E_GLPRT_PTC511L(hw->port),
2718                             pf->offset_loaded, &os->tx_size_511,
2719                             &ns->tx_size_511);
2720         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2721                             I40E_GLPRT_PTC1023L(hw->port),
2722                             pf->offset_loaded, &os->tx_size_1023,
2723                             &ns->tx_size_1023);
2724         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2725                             I40E_GLPRT_PTC1522L(hw->port),
2726                             pf->offset_loaded, &os->tx_size_1522,
2727                             &ns->tx_size_1522);
2728         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2729                             I40E_GLPRT_PTC9522L(hw->port),
2730                             pf->offset_loaded, &os->tx_size_big,
2731                             &ns->tx_size_big);
2732         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2733                            pf->offset_loaded,
2734                            &os->fd_sb_match, &ns->fd_sb_match);
2735         /* GLPRT_MSPDC not supported */
2736         /* GLPRT_XEC not supported */
2737
2738         pf->offset_loaded = true;
2739
2740         if (pf->main_vsi)
2741                 i40e_update_vsi_stats(pf->main_vsi);
2742 }
2743
2744 /* Get all statistics of a port */
2745 static int
2746 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2747 {
2748         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2749         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2750         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2751         unsigned i;
2752
2753         /* call read registers - updates values, now write them to struct */
2754         i40e_read_stats_registers(pf, hw);
2755
2756         stats->ipackets = ns->eth.rx_unicast +
2757                         ns->eth.rx_multicast +
2758                         ns->eth.rx_broadcast -
2759                         ns->eth.rx_discards -
2760                         pf->main_vsi->eth_stats.rx_discards;
2761         stats->opackets = ns->eth.tx_unicast +
2762                         ns->eth.tx_multicast +
2763                         ns->eth.tx_broadcast;
2764         stats->ibytes   = ns->eth.rx_bytes;
2765         stats->obytes   = ns->eth.tx_bytes;
2766         stats->oerrors  = ns->eth.tx_errors +
2767                         pf->main_vsi->eth_stats.tx_errors;
2768
2769         /* Rx Errors */
2770         stats->imissed  = ns->eth.rx_discards +
2771                         pf->main_vsi->eth_stats.rx_discards;
2772         stats->ierrors  = ns->crc_errors +
2773                         ns->rx_length_errors + ns->rx_undersize +
2774                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2775
2776         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2777         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2778         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2779         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2780         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2781         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2782         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2783                     ns->eth.rx_unknown_protocol);
2784         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2785         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2786         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2787         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2788         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2789         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2790
2791         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2792                     ns->tx_dropped_link_down);
2793         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2794         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2795                     ns->illegal_bytes);
2796         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2797         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2798                     ns->mac_local_faults);
2799         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2800                     ns->mac_remote_faults);
2801         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2802                     ns->rx_length_errors);
2803         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2804         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2805         for (i = 0; i < 8; i++) {
2806                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2807                                 i, ns->priority_xon_rx[i]);
2808                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2809                                 i, ns->priority_xoff_rx[i]);
2810         }
2811         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2812         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2813         for (i = 0; i < 8; i++) {
2814                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2815                                 i, ns->priority_xon_tx[i]);
2816                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2817                                 i, ns->priority_xoff_tx[i]);
2818                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2819                                 i, ns->priority_xon_2_xoff[i]);
2820         }
2821         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2822         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2823         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2824         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2825         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2826         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2827         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2828         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2829         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2830         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2831         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2832         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2833         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2834         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2835         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2836         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2837         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2838         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2839         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2840                         ns->mac_short_packet_dropped);
2841         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2842                     ns->checksum_error);
2843         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2844         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2845         return 0;
2846 }
2847
2848 /* Reset the statistics */
2849 static void
2850 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2851 {
2852         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2853         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2854
2855         /* Mark PF and VSI stats to update the offset, aka "reset" */
2856         pf->offset_loaded = false;
2857         if (pf->main_vsi)
2858                 pf->main_vsi->offset_loaded = false;
2859
2860         /* read the stats, reading current register values into offset */
2861         i40e_read_stats_registers(pf, hw);
2862 }
2863
2864 static uint32_t
2865 i40e_xstats_calc_num(void)
2866 {
2867         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2868                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2869                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2870 }
2871
2872 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2873                                      struct rte_eth_xstat_name *xstats_names,
2874                                      __rte_unused unsigned limit)
2875 {
2876         unsigned count = 0;
2877         unsigned i, prio;
2878
2879         if (xstats_names == NULL)
2880                 return i40e_xstats_calc_num();
2881
2882         /* Note: limit checked in rte_eth_xstats_names() */
2883
2884         /* Get stats from i40e_eth_stats struct */
2885         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2886                 snprintf(xstats_names[count].name,
2887                          sizeof(xstats_names[count].name),
2888                          "%s", rte_i40e_stats_strings[i].name);
2889                 count++;
2890         }
2891
2892         /* Get individiual stats from i40e_hw_port struct */
2893         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2894                 snprintf(xstats_names[count].name,
2895                         sizeof(xstats_names[count].name),
2896                          "%s", rte_i40e_hw_port_strings[i].name);
2897                 count++;
2898         }
2899
2900         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2901                 for (prio = 0; prio < 8; prio++) {
2902                         snprintf(xstats_names[count].name,
2903                                  sizeof(xstats_names[count].name),
2904                                  "rx_priority%u_%s", prio,
2905                                  rte_i40e_rxq_prio_strings[i].name);
2906                         count++;
2907                 }
2908         }
2909
2910         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2911                 for (prio = 0; prio < 8; prio++) {
2912                         snprintf(xstats_names[count].name,
2913                                  sizeof(xstats_names[count].name),
2914                                  "tx_priority%u_%s", prio,
2915                                  rte_i40e_txq_prio_strings[i].name);
2916                         count++;
2917                 }
2918         }
2919         return count;
2920 }
2921
2922 static int
2923 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2924                     unsigned n)
2925 {
2926         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2927         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2928         unsigned i, count, prio;
2929         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2930
2931         count = i40e_xstats_calc_num();
2932         if (n < count)
2933                 return count;
2934
2935         i40e_read_stats_registers(pf, hw);
2936
2937         if (xstats == NULL)
2938                 return 0;
2939
2940         count = 0;
2941
2942         /* Get stats from i40e_eth_stats struct */
2943         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2944                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2945                         rte_i40e_stats_strings[i].offset);
2946                 xstats[count].id = count;
2947                 count++;
2948         }
2949
2950         /* Get individiual stats from i40e_hw_port struct */
2951         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2952                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2953                         rte_i40e_hw_port_strings[i].offset);
2954                 xstats[count].id = count;
2955                 count++;
2956         }
2957
2958         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2959                 for (prio = 0; prio < 8; prio++) {
2960                         xstats[count].value =
2961                                 *(uint64_t *)(((char *)hw_stats) +
2962                                 rte_i40e_rxq_prio_strings[i].offset +
2963                                 (sizeof(uint64_t) * prio));
2964                         xstats[count].id = count;
2965                         count++;
2966                 }
2967         }
2968
2969         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2970                 for (prio = 0; prio < 8; prio++) {
2971                         xstats[count].value =
2972                                 *(uint64_t *)(((char *)hw_stats) +
2973                                 rte_i40e_txq_prio_strings[i].offset +
2974                                 (sizeof(uint64_t) * prio));
2975                         xstats[count].id = count;
2976                         count++;
2977                 }
2978         }
2979
2980         return count;
2981 }
2982
2983 static int
2984 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2985                                  __rte_unused uint16_t queue_id,
2986                                  __rte_unused uint8_t stat_idx,
2987                                  __rte_unused uint8_t is_rx)
2988 {
2989         PMD_INIT_FUNC_TRACE();
2990
2991         return -ENOSYS;
2992 }
2993
2994 static int
2995 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2996 {
2997         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2998         u32 full_ver;
2999         u8 ver, patch;
3000         u16 build;
3001         int ret;
3002
3003         full_ver = hw->nvm.oem_ver;
3004         ver = (u8)(full_ver >> 24);
3005         build = (u16)((full_ver >> 8) & 0xffff);
3006         patch = (u8)(full_ver & 0xff);
3007
3008         ret = snprintf(fw_version, fw_size,
3009                  "%d.%d%d 0x%08x %d.%d.%d",
3010                  ((hw->nvm.version >> 12) & 0xf),
3011                  ((hw->nvm.version >> 4) & 0xff),
3012                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3013                  ver, build, patch);
3014
3015         ret += 1; /* add the size of '\0' */
3016         if (fw_size < (u32)ret)
3017                 return ret;
3018         else
3019                 return 0;
3020 }
3021
3022 static void
3023 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3024 {
3025         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3026         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3027         struct i40e_vsi *vsi = pf->main_vsi;
3028         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3029
3030         dev_info->pci_dev = pci_dev;
3031         dev_info->max_rx_queues = vsi->nb_qps;
3032         dev_info->max_tx_queues = vsi->nb_qps;
3033         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3034         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3035         dev_info->max_mac_addrs = vsi->max_macaddrs;
3036         dev_info->max_vfs = pci_dev->max_vfs;
3037         dev_info->rx_offload_capa =
3038                 DEV_RX_OFFLOAD_VLAN_STRIP |
3039                 DEV_RX_OFFLOAD_QINQ_STRIP |
3040                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3041                 DEV_RX_OFFLOAD_UDP_CKSUM |
3042                 DEV_RX_OFFLOAD_TCP_CKSUM;
3043         dev_info->tx_offload_capa =
3044                 DEV_TX_OFFLOAD_VLAN_INSERT |
3045                 DEV_TX_OFFLOAD_QINQ_INSERT |
3046                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3047                 DEV_TX_OFFLOAD_UDP_CKSUM |
3048                 DEV_TX_OFFLOAD_TCP_CKSUM |
3049                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3050                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3051                 DEV_TX_OFFLOAD_TCP_TSO |
3052                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3053                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3054                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3055                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3056         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3057                                                 sizeof(uint32_t);
3058         dev_info->reta_size = pf->hash_lut_size;
3059         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3060
3061         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3062                 .rx_thresh = {
3063                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3064                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3065                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3066                 },
3067                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3068                 .rx_drop_en = 0,
3069         };
3070
3071         dev_info->default_txconf = (struct rte_eth_txconf) {
3072                 .tx_thresh = {
3073                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3074                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3075                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3076                 },
3077                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3078                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3079                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3080                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3081         };
3082
3083         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3084                 .nb_max = I40E_MAX_RING_DESC,
3085                 .nb_min = I40E_MIN_RING_DESC,
3086                 .nb_align = I40E_ALIGN_RING_DESC,
3087         };
3088
3089         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3090                 .nb_max = I40E_MAX_RING_DESC,
3091                 .nb_min = I40E_MIN_RING_DESC,
3092                 .nb_align = I40E_ALIGN_RING_DESC,
3093                 .nb_seg_max = I40E_TX_MAX_SEG,
3094                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3095         };
3096
3097         if (pf->flags & I40E_FLAG_VMDQ) {
3098                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3099                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3100                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3101                                                 pf->max_nb_vmdq_vsi;
3102                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3103                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3104                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3105         }
3106
3107         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3108                 /* For XL710 */
3109                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3110         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3111                 /* For XXV710 */
3112                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3113         else
3114                 /* For X710 */
3115                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3116 }
3117
3118 static int
3119 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3120 {
3121         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3122         struct i40e_vsi *vsi = pf->main_vsi;
3123         PMD_INIT_FUNC_TRACE();
3124
3125         if (on)
3126                 return i40e_vsi_add_vlan(vsi, vlan_id);
3127         else
3128                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3129 }
3130
3131 static int
3132 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3133                                 enum rte_vlan_type vlan_type,
3134                                 uint16_t tpid, int qinq)
3135 {
3136         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3137         uint64_t reg_r = 0;
3138         uint64_t reg_w = 0;
3139         uint16_t reg_id = 3;
3140         int ret;
3141
3142         if (qinq) {
3143                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3144                         reg_id = 2;
3145         }
3146
3147         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3148                                           &reg_r, NULL);
3149         if (ret != I40E_SUCCESS) {
3150                 PMD_DRV_LOG(ERR,
3151                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3152                            reg_id);
3153                 return -EIO;
3154         }
3155         PMD_DRV_LOG(DEBUG,
3156                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3157                     reg_id, reg_r);
3158
3159         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3160         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3161         if (reg_r == reg_w) {
3162                 PMD_DRV_LOG(DEBUG, "No need to write");
3163                 return 0;
3164         }
3165
3166         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3167                                            reg_w, NULL);
3168         if (ret != I40E_SUCCESS) {
3169                 PMD_DRV_LOG(ERR,
3170                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3171                             reg_id);
3172                 return -EIO;
3173         }
3174         PMD_DRV_LOG(DEBUG,
3175                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3176                     reg_w, reg_id);
3177
3178         return 0;
3179 }
3180
3181 static int
3182 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3183                    enum rte_vlan_type vlan_type,
3184                    uint16_t tpid)
3185 {
3186         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3187         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3188         int ret = 0;
3189
3190         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3191              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3192             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3193                 PMD_DRV_LOG(ERR,
3194                             "Unsupported vlan type.");
3195                 return -EINVAL;
3196         }
3197         /* 802.1ad frames ability is added in NVM API 1.7*/
3198         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3199                 if (qinq) {
3200                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3201                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3202                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3203                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3204                 } else {
3205                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3206                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3207                 }
3208                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3209                 if (ret != I40E_SUCCESS) {
3210                         PMD_DRV_LOG(ERR,
3211                                     "Set switch config failed aq_err: %d",
3212                                     hw->aq.asq_last_status);
3213                         ret = -EIO;
3214                 }
3215         } else
3216                 /* If NVM API < 1.7, keep the register setting */
3217                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3218                                                       tpid, qinq);
3219
3220         return ret;
3221 }
3222
3223 static int
3224 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3225 {
3226         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3227         struct i40e_vsi *vsi = pf->main_vsi;
3228
3229         if (mask & ETH_VLAN_FILTER_MASK) {
3230                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3231                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3232                 else
3233                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3234         }
3235
3236         if (mask & ETH_VLAN_STRIP_MASK) {
3237                 /* Enable or disable VLAN stripping */
3238                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3239                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3240                 else
3241                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3242         }
3243
3244         if (mask & ETH_VLAN_EXTEND_MASK) {
3245                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3246                         i40e_vsi_config_double_vlan(vsi, TRUE);
3247                         /* Set global registers with default ethertype. */
3248                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3249                                            ETHER_TYPE_VLAN);
3250                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3251                                            ETHER_TYPE_VLAN);
3252                 }
3253                 else
3254                         i40e_vsi_config_double_vlan(vsi, FALSE);
3255         }
3256
3257         return 0;
3258 }
3259
3260 static void
3261 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3262                           __rte_unused uint16_t queue,
3263                           __rte_unused int on)
3264 {
3265         PMD_INIT_FUNC_TRACE();
3266 }
3267
3268 static int
3269 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3270 {
3271         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3272         struct i40e_vsi *vsi = pf->main_vsi;
3273         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3274         struct i40e_vsi_vlan_pvid_info info;
3275
3276         memset(&info, 0, sizeof(info));
3277         info.on = on;
3278         if (info.on)
3279                 info.config.pvid = pvid;
3280         else {
3281                 info.config.reject.tagged =
3282                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3283                 info.config.reject.untagged =
3284                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3285         }
3286
3287         return i40e_vsi_vlan_pvid_set(vsi, &info);
3288 }
3289
3290 static int
3291 i40e_dev_led_on(struct rte_eth_dev *dev)
3292 {
3293         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3294         uint32_t mode = i40e_led_get(hw);
3295
3296         if (mode == 0)
3297                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3298
3299         return 0;
3300 }
3301
3302 static int
3303 i40e_dev_led_off(struct rte_eth_dev *dev)
3304 {
3305         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3306         uint32_t mode = i40e_led_get(hw);
3307
3308         if (mode != 0)
3309                 i40e_led_set(hw, 0, false);
3310
3311         return 0;
3312 }
3313
3314 static int
3315 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3316 {
3317         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3318         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3319
3320         fc_conf->pause_time = pf->fc_conf.pause_time;
3321
3322         /* read out from register, in case they are modified by other port */
3323         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3324                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3325         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3326                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3327
3328         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3329         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3330
3331          /* Return current mode according to actual setting*/
3332         switch (hw->fc.current_mode) {
3333         case I40E_FC_FULL:
3334                 fc_conf->mode = RTE_FC_FULL;
3335                 break;
3336         case I40E_FC_TX_PAUSE:
3337                 fc_conf->mode = RTE_FC_TX_PAUSE;
3338                 break;
3339         case I40E_FC_RX_PAUSE:
3340                 fc_conf->mode = RTE_FC_RX_PAUSE;
3341                 break;
3342         case I40E_FC_NONE:
3343         default:
3344                 fc_conf->mode = RTE_FC_NONE;
3345         };
3346
3347         return 0;
3348 }
3349
3350 static int
3351 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3352 {
3353         uint32_t mflcn_reg, fctrl_reg, reg;
3354         uint32_t max_high_water;
3355         uint8_t i, aq_failure;
3356         int err;
3357         struct i40e_hw *hw;
3358         struct i40e_pf *pf;
3359         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3360                 [RTE_FC_NONE] = I40E_FC_NONE,
3361                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3362                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3363                 [RTE_FC_FULL] = I40E_FC_FULL
3364         };
3365
3366         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3367
3368         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3369         if ((fc_conf->high_water > max_high_water) ||
3370                         (fc_conf->high_water < fc_conf->low_water)) {
3371                 PMD_INIT_LOG(ERR,
3372                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3373                         max_high_water);
3374                 return -EINVAL;
3375         }
3376
3377         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3378         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3379         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3380
3381         pf->fc_conf.pause_time = fc_conf->pause_time;
3382         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3383         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3384
3385         PMD_INIT_FUNC_TRACE();
3386
3387         /* All the link flow control related enable/disable register
3388          * configuration is handle by the F/W
3389          */
3390         err = i40e_set_fc(hw, &aq_failure, true);
3391         if (err < 0)
3392                 return -ENOSYS;
3393
3394         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3395                 /* Configure flow control refresh threshold,
3396                  * the value for stat_tx_pause_refresh_timer[8]
3397                  * is used for global pause operation.
3398                  */
3399
3400                 I40E_WRITE_REG(hw,
3401                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3402                                pf->fc_conf.pause_time);
3403
3404                 /* configure the timer value included in transmitted pause
3405                  * frame,
3406                  * the value for stat_tx_pause_quanta[8] is used for global
3407                  * pause operation
3408                  */
3409                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3410                                pf->fc_conf.pause_time);
3411
3412                 fctrl_reg = I40E_READ_REG(hw,
3413                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3414
3415                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3416                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3417                 else
3418                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3419
3420                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3421                                fctrl_reg);
3422         } else {
3423                 /* Configure pause time (2 TCs per register) */
3424                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3425                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3426                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3427
3428                 /* Configure flow control refresh threshold value */
3429                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3430                                pf->fc_conf.pause_time / 2);
3431
3432                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3433
3434                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3435                  *depending on configuration
3436                  */
3437                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3438                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3439                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3440                 } else {
3441                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3442                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3443                 }
3444
3445                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3446         }
3447
3448         /* config the water marker both based on the packets and bytes */
3449         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3450                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3451                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3452         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3453                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3454                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3455         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3456                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3457                        << I40E_KILOSHIFT);
3458         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3459                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3460                        << I40E_KILOSHIFT);
3461
3462         I40E_WRITE_FLUSH(hw);
3463
3464         return 0;
3465 }
3466
3467 static int
3468 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3469                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3470 {
3471         PMD_INIT_FUNC_TRACE();
3472
3473         return -ENOSYS;
3474 }
3475
3476 /* Add a MAC address, and update filters */
3477 static int
3478 i40e_macaddr_add(struct rte_eth_dev *dev,
3479                  struct ether_addr *mac_addr,
3480                  __rte_unused uint32_t index,
3481                  uint32_t pool)
3482 {
3483         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3484         struct i40e_mac_filter_info mac_filter;
3485         struct i40e_vsi *vsi;
3486         int ret;
3487
3488         /* If VMDQ not enabled or configured, return */
3489         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3490                           !pf->nb_cfg_vmdq_vsi)) {
3491                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3492                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3493                         pool);
3494                 return -ENOTSUP;
3495         }
3496
3497         if (pool > pf->nb_cfg_vmdq_vsi) {
3498                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3499                                 pool, pf->nb_cfg_vmdq_vsi);
3500                 return -EINVAL;
3501         }
3502
3503         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3504         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3505                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3506         else
3507                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3508
3509         if (pool == 0)
3510                 vsi = pf->main_vsi;
3511         else
3512                 vsi = pf->vmdq[pool - 1].vsi;
3513
3514         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3515         if (ret != I40E_SUCCESS) {
3516                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3517                 return -ENODEV;
3518         }
3519         return 0;
3520 }
3521
3522 /* Remove a MAC address, and update filters */
3523 static void
3524 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3525 {
3526         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3527         struct i40e_vsi *vsi;
3528         struct rte_eth_dev_data *data = dev->data;
3529         struct ether_addr *macaddr;
3530         int ret;
3531         uint32_t i;
3532         uint64_t pool_sel;
3533
3534         macaddr = &(data->mac_addrs[index]);
3535
3536         pool_sel = dev->data->mac_pool_sel[index];
3537
3538         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3539                 if (pool_sel & (1ULL << i)) {
3540                         if (i == 0)
3541                                 vsi = pf->main_vsi;
3542                         else {
3543                                 /* No VMDQ pool enabled or configured */
3544                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3545                                         (i > pf->nb_cfg_vmdq_vsi)) {
3546                                         PMD_DRV_LOG(ERR,
3547                                                 "No VMDQ pool enabled/configured");
3548                                         return;
3549                                 }
3550                                 vsi = pf->vmdq[i - 1].vsi;
3551                         }
3552                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3553
3554                         if (ret) {
3555                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3556                                 return;
3557                         }
3558                 }
3559         }
3560 }
3561
3562 /* Set perfect match or hash match of MAC and VLAN for a VF */
3563 static int
3564 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3565                  struct rte_eth_mac_filter *filter,
3566                  bool add)
3567 {
3568         struct i40e_hw *hw;
3569         struct i40e_mac_filter_info mac_filter;
3570         struct ether_addr old_mac;
3571         struct ether_addr *new_mac;
3572         struct i40e_pf_vf *vf = NULL;
3573         uint16_t vf_id;
3574         int ret;
3575
3576         if (pf == NULL) {
3577                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3578                 return -EINVAL;
3579         }
3580         hw = I40E_PF_TO_HW(pf);
3581
3582         if (filter == NULL) {
3583                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3584                 return -EINVAL;
3585         }
3586
3587         new_mac = &filter->mac_addr;
3588
3589         if (is_zero_ether_addr(new_mac)) {
3590                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3591                 return -EINVAL;
3592         }
3593
3594         vf_id = filter->dst_id;
3595
3596         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3597                 PMD_DRV_LOG(ERR, "Invalid argument.");
3598                 return -EINVAL;
3599         }
3600         vf = &pf->vfs[vf_id];
3601
3602         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3603                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3604                 return -EINVAL;
3605         }
3606
3607         if (add) {
3608                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3609                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3610                                 ETHER_ADDR_LEN);
3611                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3612                                  ETHER_ADDR_LEN);
3613
3614                 mac_filter.filter_type = filter->filter_type;
3615                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3616                 if (ret != I40E_SUCCESS) {
3617                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3618                         return -1;
3619                 }
3620                 ether_addr_copy(new_mac, &pf->dev_addr);
3621         } else {
3622                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3623                                 ETHER_ADDR_LEN);
3624                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3625                 if (ret != I40E_SUCCESS) {
3626                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3627                         return -1;
3628                 }
3629
3630                 /* Clear device address as it has been removed */
3631                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3632                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3633         }
3634
3635         return 0;
3636 }
3637
3638 /* MAC filter handle */
3639 static int
3640 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3641                 void *arg)
3642 {
3643         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3644         struct rte_eth_mac_filter *filter;
3645         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3646         int ret = I40E_NOT_SUPPORTED;
3647
3648         filter = (struct rte_eth_mac_filter *)(arg);
3649
3650         switch (filter_op) {
3651         case RTE_ETH_FILTER_NOP:
3652                 ret = I40E_SUCCESS;
3653                 break;
3654         case RTE_ETH_FILTER_ADD:
3655                 i40e_pf_disable_irq0(hw);
3656                 if (filter->is_vf)
3657                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3658                 i40e_pf_enable_irq0(hw);
3659                 break;
3660         case RTE_ETH_FILTER_DELETE:
3661                 i40e_pf_disable_irq0(hw);
3662                 if (filter->is_vf)
3663                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3664                 i40e_pf_enable_irq0(hw);
3665                 break;
3666         default:
3667                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3668                 ret = I40E_ERR_PARAM;
3669                 break;
3670         }
3671
3672         return ret;
3673 }
3674
3675 static int
3676 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3677 {
3678         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3679         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3680         int ret;
3681
3682         if (!lut)
3683                 return -EINVAL;
3684
3685         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3686                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3687                                           lut, lut_size);
3688                 if (ret) {
3689                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3690                         return ret;
3691                 }
3692         } else {
3693                 uint32_t *lut_dw = (uint32_t *)lut;
3694                 uint16_t i, lut_size_dw = lut_size / 4;
3695
3696                 for (i = 0; i < lut_size_dw; i++)
3697                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3698         }
3699
3700         return 0;
3701 }
3702
3703 static int
3704 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3705 {
3706         struct i40e_pf *pf;
3707         struct i40e_hw *hw;
3708         int ret;
3709
3710         if (!vsi || !lut)
3711                 return -EINVAL;
3712
3713         pf = I40E_VSI_TO_PF(vsi);
3714         hw = I40E_VSI_TO_HW(vsi);
3715
3716         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3717                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3718                                           lut, lut_size);
3719                 if (ret) {
3720                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3721                         return ret;
3722                 }
3723         } else {
3724                 uint32_t *lut_dw = (uint32_t *)lut;
3725                 uint16_t i, lut_size_dw = lut_size / 4;
3726
3727                 for (i = 0; i < lut_size_dw; i++)
3728                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3729                 I40E_WRITE_FLUSH(hw);
3730         }
3731
3732         return 0;
3733 }
3734
3735 static int
3736 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3737                          struct rte_eth_rss_reta_entry64 *reta_conf,
3738                          uint16_t reta_size)
3739 {
3740         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3741         uint16_t i, lut_size = pf->hash_lut_size;
3742         uint16_t idx, shift;
3743         uint8_t *lut;
3744         int ret;
3745
3746         if (reta_size != lut_size ||
3747                 reta_size > ETH_RSS_RETA_SIZE_512) {
3748                 PMD_DRV_LOG(ERR,
3749                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3750                         reta_size, lut_size);
3751                 return -EINVAL;
3752         }
3753
3754         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3755         if (!lut) {
3756                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3757                 return -ENOMEM;
3758         }
3759         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3760         if (ret)
3761                 goto out;
3762         for (i = 0; i < reta_size; i++) {
3763                 idx = i / RTE_RETA_GROUP_SIZE;
3764                 shift = i % RTE_RETA_GROUP_SIZE;
3765                 if (reta_conf[idx].mask & (1ULL << shift))
3766                         lut[i] = reta_conf[idx].reta[shift];
3767         }
3768         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3769
3770 out:
3771         rte_free(lut);
3772
3773         return ret;
3774 }
3775
3776 static int
3777 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3778                         struct rte_eth_rss_reta_entry64 *reta_conf,
3779                         uint16_t reta_size)
3780 {
3781         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3782         uint16_t i, lut_size = pf->hash_lut_size;
3783         uint16_t idx, shift;
3784         uint8_t *lut;
3785         int ret;
3786
3787         if (reta_size != lut_size ||
3788                 reta_size > ETH_RSS_RETA_SIZE_512) {
3789                 PMD_DRV_LOG(ERR,
3790                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3791                         reta_size, lut_size);
3792                 return -EINVAL;
3793         }
3794
3795         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3796         if (!lut) {
3797                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3798                 return -ENOMEM;
3799         }
3800
3801         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3802         if (ret)
3803                 goto out;
3804         for (i = 0; i < reta_size; i++) {
3805                 idx = i / RTE_RETA_GROUP_SIZE;
3806                 shift = i % RTE_RETA_GROUP_SIZE;
3807                 if (reta_conf[idx].mask & (1ULL << shift))
3808                         reta_conf[idx].reta[shift] = lut[i];
3809         }
3810
3811 out:
3812         rte_free(lut);
3813
3814         return ret;
3815 }
3816
3817 /**
3818  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3819  * @hw:   pointer to the HW structure
3820  * @mem:  pointer to mem struct to fill out
3821  * @size: size of memory requested
3822  * @alignment: what to align the allocation to
3823  **/
3824 enum i40e_status_code
3825 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3826                         struct i40e_dma_mem *mem,
3827                         u64 size,
3828                         u32 alignment)
3829 {
3830         const struct rte_memzone *mz = NULL;
3831         char z_name[RTE_MEMZONE_NAMESIZE];
3832
3833         if (!mem)
3834                 return I40E_ERR_PARAM;
3835
3836         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3837         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3838                                          alignment, RTE_PGSIZE_2M);
3839         if (!mz)
3840                 return I40E_ERR_NO_MEMORY;
3841
3842         mem->size = size;
3843         mem->va = mz->addr;
3844         mem->pa = mz->phys_addr;
3845         mem->zone = (const void *)mz;
3846         PMD_DRV_LOG(DEBUG,
3847                 "memzone %s allocated with physical address: %"PRIu64,
3848                 mz->name, mem->pa);
3849
3850         return I40E_SUCCESS;
3851 }
3852
3853 /**
3854  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3855  * @hw:   pointer to the HW structure
3856  * @mem:  ptr to mem struct to free
3857  **/
3858 enum i40e_status_code
3859 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3860                     struct i40e_dma_mem *mem)
3861 {
3862         if (!mem)
3863                 return I40E_ERR_PARAM;
3864
3865         PMD_DRV_LOG(DEBUG,
3866                 "memzone %s to be freed with physical address: %"PRIu64,
3867                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3868         rte_memzone_free((const struct rte_memzone *)mem->zone);
3869         mem->zone = NULL;
3870         mem->va = NULL;
3871         mem->pa = (u64)0;
3872
3873         return I40E_SUCCESS;
3874 }
3875
3876 /**
3877  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3878  * @hw:   pointer to the HW structure
3879  * @mem:  pointer to mem struct to fill out
3880  * @size: size of memory requested
3881  **/
3882 enum i40e_status_code
3883 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3884                          struct i40e_virt_mem *mem,
3885                          u32 size)
3886 {
3887         if (!mem)
3888                 return I40E_ERR_PARAM;
3889
3890         mem->size = size;
3891         mem->va = rte_zmalloc("i40e", size, 0);
3892
3893         if (mem->va)
3894                 return I40E_SUCCESS;
3895         else
3896                 return I40E_ERR_NO_MEMORY;
3897 }
3898
3899 /**
3900  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3901  * @hw:   pointer to the HW structure
3902  * @mem:  pointer to mem struct to free
3903  **/
3904 enum i40e_status_code
3905 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3906                      struct i40e_virt_mem *mem)
3907 {
3908         if (!mem)
3909                 return I40E_ERR_PARAM;
3910
3911         rte_free(mem->va);
3912         mem->va = NULL;
3913
3914         return I40E_SUCCESS;
3915 }
3916
3917 void
3918 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3919 {
3920         rte_spinlock_init(&sp->spinlock);
3921 }
3922
3923 void
3924 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3925 {
3926         rte_spinlock_lock(&sp->spinlock);
3927 }
3928
3929 void
3930 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3931 {
3932         rte_spinlock_unlock(&sp->spinlock);
3933 }
3934
3935 void
3936 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3937 {
3938         return;
3939 }
3940
3941 /**
3942  * Get the hardware capabilities, which will be parsed
3943  * and saved into struct i40e_hw.
3944  */
3945 static int
3946 i40e_get_cap(struct i40e_hw *hw)
3947 {
3948         struct i40e_aqc_list_capabilities_element_resp *buf;
3949         uint16_t len, size = 0;
3950         int ret;
3951
3952         /* Calculate a huge enough buff for saving response data temporarily */
3953         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3954                                                 I40E_MAX_CAP_ELE_NUM;
3955         buf = rte_zmalloc("i40e", len, 0);
3956         if (!buf) {
3957                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3958                 return I40E_ERR_NO_MEMORY;
3959         }
3960
3961         /* Get, parse the capabilities and save it to hw */
3962         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3963                         i40e_aqc_opc_list_func_capabilities, NULL);
3964         if (ret != I40E_SUCCESS)
3965                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3966
3967         /* Free the temporary buffer after being used */
3968         rte_free(buf);
3969
3970         return ret;
3971 }
3972
3973 static int
3974 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3975 {
3976         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3977         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3978         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3979         uint16_t qp_count = 0, vsi_count = 0;
3980
3981         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3982                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3983                 return -EINVAL;
3984         }
3985         /* Add the parameter init for LFC */
3986         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3987         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3988         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3989
3990         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3991         pf->max_num_vsi = hw->func_caps.num_vsis;
3992         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3993         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3994         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3995
3996         /* FDir queue/VSI allocation */
3997         pf->fdir_qp_offset = 0;
3998         if (hw->func_caps.fd) {
3999                 pf->flags |= I40E_FLAG_FDIR;
4000                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4001         } else {
4002                 pf->fdir_nb_qps = 0;
4003         }
4004         qp_count += pf->fdir_nb_qps;
4005         vsi_count += 1;
4006
4007         /* LAN queue/VSI allocation */
4008         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4009         if (!hw->func_caps.rss) {
4010                 pf->lan_nb_qps = 1;
4011         } else {
4012                 pf->flags |= I40E_FLAG_RSS;
4013                 if (hw->mac.type == I40E_MAC_X722)
4014                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4015                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4016         }
4017         qp_count += pf->lan_nb_qps;
4018         vsi_count += 1;
4019
4020         /* VF queue/VSI allocation */
4021         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4022         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4023                 pf->flags |= I40E_FLAG_SRIOV;
4024                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4025                 pf->vf_num = pci_dev->max_vfs;
4026                 PMD_DRV_LOG(DEBUG,
4027                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4028                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4029         } else {
4030                 pf->vf_nb_qps = 0;
4031                 pf->vf_num = 0;
4032         }
4033         qp_count += pf->vf_nb_qps * pf->vf_num;
4034         vsi_count += pf->vf_num;
4035
4036         /* VMDq queue/VSI allocation */
4037         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4038         pf->vmdq_nb_qps = 0;
4039         pf->max_nb_vmdq_vsi = 0;
4040         if (hw->func_caps.vmdq) {
4041                 if (qp_count < hw->func_caps.num_tx_qp &&
4042                         vsi_count < hw->func_caps.num_vsis) {
4043                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4044                                 qp_count) / pf->vmdq_nb_qp_max;
4045
4046                         /* Limit the maximum number of VMDq vsi to the maximum
4047                          * ethdev can support
4048                          */
4049                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4050                                 hw->func_caps.num_vsis - vsi_count);
4051                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4052                                 ETH_64_POOLS);
4053                         if (pf->max_nb_vmdq_vsi) {
4054                                 pf->flags |= I40E_FLAG_VMDQ;
4055                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4056                                 PMD_DRV_LOG(DEBUG,
4057                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4058                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4059                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4060                         } else {
4061                                 PMD_DRV_LOG(INFO,
4062                                         "No enough queues left for VMDq");
4063                         }
4064                 } else {
4065                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4066                 }
4067         }
4068         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4069         vsi_count += pf->max_nb_vmdq_vsi;
4070
4071         if (hw->func_caps.dcb)
4072                 pf->flags |= I40E_FLAG_DCB;
4073
4074         if (qp_count > hw->func_caps.num_tx_qp) {
4075                 PMD_DRV_LOG(ERR,
4076                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4077                         qp_count, hw->func_caps.num_tx_qp);
4078                 return -EINVAL;
4079         }
4080         if (vsi_count > hw->func_caps.num_vsis) {
4081                 PMD_DRV_LOG(ERR,
4082                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4083                         vsi_count, hw->func_caps.num_vsis);
4084                 return -EINVAL;
4085         }
4086
4087         return 0;
4088 }
4089
4090 static int
4091 i40e_pf_get_switch_config(struct i40e_pf *pf)
4092 {
4093         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4094         struct i40e_aqc_get_switch_config_resp *switch_config;
4095         struct i40e_aqc_switch_config_element_resp *element;
4096         uint16_t start_seid = 0, num_reported;
4097         int ret;
4098
4099         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4100                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4101         if (!switch_config) {
4102                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4103                 return -ENOMEM;
4104         }
4105
4106         /* Get the switch configurations */
4107         ret = i40e_aq_get_switch_config(hw, switch_config,
4108                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4109         if (ret != I40E_SUCCESS) {
4110                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4111                 goto fail;
4112         }
4113         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4114         if (num_reported != 1) { /* The number should be 1 */
4115                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4116                 goto fail;
4117         }
4118
4119         /* Parse the switch configuration elements */
4120         element = &(switch_config->element[0]);
4121         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4122                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4123                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4124         } else
4125                 PMD_DRV_LOG(INFO, "Unknown element type");
4126
4127 fail:
4128         rte_free(switch_config);
4129
4130         return ret;
4131 }
4132
4133 static int
4134 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4135                         uint32_t num)
4136 {
4137         struct pool_entry *entry;
4138
4139         if (pool == NULL || num == 0)
4140                 return -EINVAL;
4141
4142         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4143         if (entry == NULL) {
4144                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4145                 return -ENOMEM;
4146         }
4147
4148         /* queue heap initialize */
4149         pool->num_free = num;
4150         pool->num_alloc = 0;
4151         pool->base = base;
4152         LIST_INIT(&pool->alloc_list);
4153         LIST_INIT(&pool->free_list);
4154
4155         /* Initialize element  */
4156         entry->base = 0;
4157         entry->len = num;
4158
4159         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4160         return 0;
4161 }
4162
4163 static void
4164 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4165 {
4166         struct pool_entry *entry, *next_entry;
4167
4168         if (pool == NULL)
4169                 return;
4170
4171         for (entry = LIST_FIRST(&pool->alloc_list);
4172                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4173                         entry = next_entry) {
4174                 LIST_REMOVE(entry, next);
4175                 rte_free(entry);
4176         }
4177
4178         for (entry = LIST_FIRST(&pool->free_list);
4179                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4180                         entry = next_entry) {
4181                 LIST_REMOVE(entry, next);
4182                 rte_free(entry);
4183         }
4184
4185         pool->num_free = 0;
4186         pool->num_alloc = 0;
4187         pool->base = 0;
4188         LIST_INIT(&pool->alloc_list);
4189         LIST_INIT(&pool->free_list);
4190 }
4191
4192 static int
4193 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4194                        uint32_t base)
4195 {
4196         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4197         uint32_t pool_offset;
4198         int insert;
4199
4200         if (pool == NULL) {
4201                 PMD_DRV_LOG(ERR, "Invalid parameter");
4202                 return -EINVAL;
4203         }
4204
4205         pool_offset = base - pool->base;
4206         /* Lookup in alloc list */
4207         LIST_FOREACH(entry, &pool->alloc_list, next) {
4208                 if (entry->base == pool_offset) {
4209                         valid_entry = entry;
4210                         LIST_REMOVE(entry, next);
4211                         break;
4212                 }
4213         }
4214
4215         /* Not find, return */
4216         if (valid_entry == NULL) {
4217                 PMD_DRV_LOG(ERR, "Failed to find entry");
4218                 return -EINVAL;
4219         }
4220
4221         /**
4222          * Found it, move it to free list  and try to merge.
4223          * In order to make merge easier, always sort it by qbase.
4224          * Find adjacent prev and last entries.
4225          */
4226         prev = next = NULL;
4227         LIST_FOREACH(entry, &pool->free_list, next) {
4228                 if (entry->base > valid_entry->base) {
4229                         next = entry;
4230                         break;
4231                 }
4232                 prev = entry;
4233         }
4234
4235         insert = 0;
4236         /* Try to merge with next one*/
4237         if (next != NULL) {
4238                 /* Merge with next one */
4239                 if (valid_entry->base + valid_entry->len == next->base) {
4240                         next->base = valid_entry->base;
4241                         next->len += valid_entry->len;
4242                         rte_free(valid_entry);
4243                         valid_entry = next;
4244                         insert = 1;
4245                 }
4246         }
4247
4248         if (prev != NULL) {
4249                 /* Merge with previous one */
4250                 if (prev->base + prev->len == valid_entry->base) {
4251                         prev->len += valid_entry->len;
4252                         /* If it merge with next one, remove next node */
4253                         if (insert == 1) {
4254                                 LIST_REMOVE(valid_entry, next);
4255                                 rte_free(valid_entry);
4256                         } else {
4257                                 rte_free(valid_entry);
4258                                 insert = 1;
4259                         }
4260                 }
4261         }
4262
4263         /* Not find any entry to merge, insert */
4264         if (insert == 0) {
4265                 if (prev != NULL)
4266                         LIST_INSERT_AFTER(prev, valid_entry, next);
4267                 else if (next != NULL)
4268                         LIST_INSERT_BEFORE(next, valid_entry, next);
4269                 else /* It's empty list, insert to head */
4270                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4271         }
4272
4273         pool->num_free += valid_entry->len;
4274         pool->num_alloc -= valid_entry->len;
4275
4276         return 0;
4277 }
4278
4279 static int
4280 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4281                        uint16_t num)
4282 {
4283         struct pool_entry *entry, *valid_entry;
4284
4285         if (pool == NULL || num == 0) {
4286                 PMD_DRV_LOG(ERR, "Invalid parameter");
4287                 return -EINVAL;
4288         }
4289
4290         if (pool->num_free < num) {
4291                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4292                             num, pool->num_free);
4293                 return -ENOMEM;
4294         }
4295
4296         valid_entry = NULL;
4297         /* Lookup  in free list and find most fit one */
4298         LIST_FOREACH(entry, &pool->free_list, next) {
4299                 if (entry->len >= num) {
4300                         /* Find best one */
4301                         if (entry->len == num) {
4302                                 valid_entry = entry;
4303                                 break;
4304                         }
4305                         if (valid_entry == NULL || valid_entry->len > entry->len)
4306                                 valid_entry = entry;
4307                 }
4308         }
4309
4310         /* Not find one to satisfy the request, return */
4311         if (valid_entry == NULL) {
4312                 PMD_DRV_LOG(ERR, "No valid entry found");
4313                 return -ENOMEM;
4314         }
4315         /**
4316          * The entry have equal queue number as requested,
4317          * remove it from alloc_list.
4318          */
4319         if (valid_entry->len == num) {
4320                 LIST_REMOVE(valid_entry, next);
4321         } else {
4322                 /**
4323                  * The entry have more numbers than requested,
4324                  * create a new entry for alloc_list and minus its
4325                  * queue base and number in free_list.
4326                  */
4327                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4328                 if (entry == NULL) {
4329                         PMD_DRV_LOG(ERR,
4330                                 "Failed to allocate memory for resource pool");
4331                         return -ENOMEM;
4332                 }
4333                 entry->base = valid_entry->base;
4334                 entry->len = num;
4335                 valid_entry->base += num;
4336                 valid_entry->len -= num;
4337                 valid_entry = entry;
4338         }
4339
4340         /* Insert it into alloc list, not sorted */
4341         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4342
4343         pool->num_free -= valid_entry->len;
4344         pool->num_alloc += valid_entry->len;
4345
4346         return valid_entry->base + pool->base;
4347 }
4348
4349 /**
4350  * bitmap_is_subset - Check whether src2 is subset of src1
4351  **/
4352 static inline int
4353 bitmap_is_subset(uint8_t src1, uint8_t src2)
4354 {
4355         return !((src1 ^ src2) & src2);
4356 }
4357
4358 static enum i40e_status_code
4359 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4360 {
4361         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4362
4363         /* If DCB is not supported, only default TC is supported */
4364         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4365                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4366                 return I40E_NOT_SUPPORTED;
4367         }
4368
4369         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4370                 PMD_DRV_LOG(ERR,
4371                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4372                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4373                 return I40E_NOT_SUPPORTED;
4374         }
4375         return I40E_SUCCESS;
4376 }
4377
4378 int
4379 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4380                                 struct i40e_vsi_vlan_pvid_info *info)
4381 {
4382         struct i40e_hw *hw;
4383         struct i40e_vsi_context ctxt;
4384         uint8_t vlan_flags = 0;
4385         int ret;
4386
4387         if (vsi == NULL || info == NULL) {
4388                 PMD_DRV_LOG(ERR, "invalid parameters");
4389                 return I40E_ERR_PARAM;
4390         }
4391
4392         if (info->on) {
4393                 vsi->info.pvid = info->config.pvid;
4394                 /**
4395                  * If insert pvid is enabled, only tagged pkts are
4396                  * allowed to be sent out.
4397                  */
4398                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4399                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4400         } else {
4401                 vsi->info.pvid = 0;
4402                 if (info->config.reject.tagged == 0)
4403                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4404
4405                 if (info->config.reject.untagged == 0)
4406                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4407         }
4408         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4409                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4410         vsi->info.port_vlan_flags |= vlan_flags;
4411         vsi->info.valid_sections =
4412                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4413         memset(&ctxt, 0, sizeof(ctxt));
4414         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4415         ctxt.seid = vsi->seid;
4416
4417         hw = I40E_VSI_TO_HW(vsi);
4418         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4419         if (ret != I40E_SUCCESS)
4420                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4421
4422         return ret;
4423 }
4424
4425 static int
4426 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4427 {
4428         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4429         int i, ret;
4430         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4431
4432         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4433         if (ret != I40E_SUCCESS)
4434                 return ret;
4435
4436         if (!vsi->seid) {
4437                 PMD_DRV_LOG(ERR, "seid not valid");
4438                 return -EINVAL;
4439         }
4440
4441         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4442         tc_bw_data.tc_valid_bits = enabled_tcmap;
4443         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4444                 tc_bw_data.tc_bw_credits[i] =
4445                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4446
4447         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4448         if (ret != I40E_SUCCESS) {
4449                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4450                 return ret;
4451         }
4452
4453         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4454                                         sizeof(vsi->info.qs_handle));
4455         return I40E_SUCCESS;
4456 }
4457
4458 static enum i40e_status_code
4459 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4460                                  struct i40e_aqc_vsi_properties_data *info,
4461                                  uint8_t enabled_tcmap)
4462 {
4463         enum i40e_status_code ret;
4464         int i, total_tc = 0;
4465         uint16_t qpnum_per_tc, bsf, qp_idx;
4466
4467         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4468         if (ret != I40E_SUCCESS)
4469                 return ret;
4470
4471         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4472                 if (enabled_tcmap & (1 << i))
4473                         total_tc++;
4474         if (total_tc == 0)
4475                 total_tc = 1;
4476         vsi->enabled_tc = enabled_tcmap;
4477
4478         /* Number of queues per enabled TC */
4479         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4480         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4481         bsf = rte_bsf32(qpnum_per_tc);
4482
4483         /* Adjust the queue number to actual queues that can be applied */
4484         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4485                 vsi->nb_qps = qpnum_per_tc * total_tc;
4486
4487         /**
4488          * Configure TC and queue mapping parameters, for enabled TC,
4489          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4490          * default queue will serve it.
4491          */
4492         qp_idx = 0;
4493         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4494                 if (vsi->enabled_tc & (1 << i)) {
4495                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4496                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4497                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4498                         qp_idx += qpnum_per_tc;
4499                 } else
4500                         info->tc_mapping[i] = 0;
4501         }
4502
4503         /* Associate queue number with VSI */
4504         if (vsi->type == I40E_VSI_SRIOV) {
4505                 info->mapping_flags |=
4506                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4507                 for (i = 0; i < vsi->nb_qps; i++)
4508                         info->queue_mapping[i] =
4509                                 rte_cpu_to_le_16(vsi->base_queue + i);
4510         } else {
4511                 info->mapping_flags |=
4512                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4513                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4514         }
4515         info->valid_sections |=
4516                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4517
4518         return I40E_SUCCESS;
4519 }
4520
4521 static int
4522 i40e_veb_release(struct i40e_veb *veb)
4523 {
4524         struct i40e_vsi *vsi;
4525         struct i40e_hw *hw;
4526
4527         if (veb == NULL)
4528                 return -EINVAL;
4529
4530         if (!TAILQ_EMPTY(&veb->head)) {
4531                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4532                 return -EACCES;
4533         }
4534         /* associate_vsi field is NULL for floating VEB */
4535         if (veb->associate_vsi != NULL) {
4536                 vsi = veb->associate_vsi;
4537                 hw = I40E_VSI_TO_HW(vsi);
4538
4539                 vsi->uplink_seid = veb->uplink_seid;
4540                 vsi->veb = NULL;
4541         } else {
4542                 veb->associate_pf->main_vsi->floating_veb = NULL;
4543                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4544         }
4545
4546         i40e_aq_delete_element(hw, veb->seid, NULL);
4547         rte_free(veb);
4548         return I40E_SUCCESS;
4549 }
4550
4551 /* Setup a veb */
4552 static struct i40e_veb *
4553 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4554 {
4555         struct i40e_veb *veb;
4556         int ret;
4557         struct i40e_hw *hw;
4558
4559         if (pf == NULL) {
4560                 PMD_DRV_LOG(ERR,
4561                             "veb setup failed, associated PF shouldn't null");
4562                 return NULL;
4563         }
4564         hw = I40E_PF_TO_HW(pf);
4565
4566         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4567         if (!veb) {
4568                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4569                 goto fail;
4570         }
4571
4572         veb->associate_vsi = vsi;
4573         veb->associate_pf = pf;
4574         TAILQ_INIT(&veb->head);
4575         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4576
4577         /* create floating veb if vsi is NULL */
4578         if (vsi != NULL) {
4579                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4580                                       I40E_DEFAULT_TCMAP, false,
4581                                       &veb->seid, false, NULL);
4582         } else {
4583                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4584                                       true, &veb->seid, false, NULL);
4585         }
4586
4587         if (ret != I40E_SUCCESS) {
4588                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4589                             hw->aq.asq_last_status);
4590                 goto fail;
4591         }
4592         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4593
4594         /* get statistics index */
4595         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4596                                 &veb->stats_idx, NULL, NULL, NULL);
4597         if (ret != I40E_SUCCESS) {
4598                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4599                             hw->aq.asq_last_status);
4600                 goto fail;
4601         }
4602         /* Get VEB bandwidth, to be implemented */
4603         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4604         if (vsi)
4605                 vsi->uplink_seid = veb->seid;
4606
4607         return veb;
4608 fail:
4609         rte_free(veb);
4610         return NULL;
4611 }
4612
4613 int
4614 i40e_vsi_release(struct i40e_vsi *vsi)
4615 {
4616         struct i40e_pf *pf;
4617         struct i40e_hw *hw;
4618         struct i40e_vsi_list *vsi_list;
4619         void *temp;
4620         int ret;
4621         struct i40e_mac_filter *f;
4622         uint16_t user_param;
4623
4624         if (!vsi)
4625                 return I40E_SUCCESS;
4626
4627         if (!vsi->adapter)
4628                 return -EFAULT;
4629
4630         user_param = vsi->user_param;
4631
4632         pf = I40E_VSI_TO_PF(vsi);
4633         hw = I40E_VSI_TO_HW(vsi);
4634
4635         /* VSI has child to attach, release child first */
4636         if (vsi->veb) {
4637                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4638                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4639                                 return -1;
4640                 }
4641                 i40e_veb_release(vsi->veb);
4642         }
4643
4644         if (vsi->floating_veb) {
4645                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4646                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4647                                 return -1;
4648                 }
4649         }
4650
4651         /* Remove all macvlan filters of the VSI */
4652         i40e_vsi_remove_all_macvlan_filter(vsi);
4653         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4654                 rte_free(f);
4655
4656         if (vsi->type != I40E_VSI_MAIN &&
4657             ((vsi->type != I40E_VSI_SRIOV) ||
4658             !pf->floating_veb_list[user_param])) {
4659                 /* Remove vsi from parent's sibling list */
4660                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4661                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4662                         return I40E_ERR_PARAM;
4663                 }
4664                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4665                                 &vsi->sib_vsi_list, list);
4666
4667                 /* Remove all switch element of the VSI */
4668                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4669                 if (ret != I40E_SUCCESS)
4670                         PMD_DRV_LOG(ERR, "Failed to delete element");
4671         }
4672
4673         if ((vsi->type == I40E_VSI_SRIOV) &&
4674             pf->floating_veb_list[user_param]) {
4675                 /* Remove vsi from parent's sibling list */
4676                 if (vsi->parent_vsi == NULL ||
4677                     vsi->parent_vsi->floating_veb == NULL) {
4678                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4679                         return I40E_ERR_PARAM;
4680                 }
4681                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4682                              &vsi->sib_vsi_list, list);
4683
4684                 /* Remove all switch element of the VSI */
4685                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4686                 if (ret != I40E_SUCCESS)
4687                         PMD_DRV_LOG(ERR, "Failed to delete element");
4688         }
4689
4690         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4691
4692         if (vsi->type != I40E_VSI_SRIOV)
4693                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4694         rte_free(vsi);
4695
4696         return I40E_SUCCESS;
4697 }
4698
4699 static int
4700 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4701 {
4702         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4703         struct i40e_aqc_remove_macvlan_element_data def_filter;
4704         struct i40e_mac_filter_info filter;
4705         int ret;
4706
4707         if (vsi->type != I40E_VSI_MAIN)
4708                 return I40E_ERR_CONFIG;
4709         memset(&def_filter, 0, sizeof(def_filter));
4710         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4711                                         ETH_ADDR_LEN);
4712         def_filter.vlan_tag = 0;
4713         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4714                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4715         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4716         if (ret != I40E_SUCCESS) {
4717                 struct i40e_mac_filter *f;
4718                 struct ether_addr *mac;
4719
4720                 PMD_DRV_LOG(DEBUG,
4721                             "Cannot remove the default macvlan filter");
4722                 /* It needs to add the permanent mac into mac list */
4723                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4724                 if (f == NULL) {
4725                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4726                         return I40E_ERR_NO_MEMORY;
4727                 }
4728                 mac = &f->mac_info.mac_addr;
4729                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4730                                 ETH_ADDR_LEN);
4731                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4732                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4733                 vsi->mac_num++;
4734
4735                 return ret;
4736         }
4737         rte_memcpy(&filter.mac_addr,
4738                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4739         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4740         return i40e_vsi_add_mac(vsi, &filter);
4741 }
4742
4743 /*
4744  * i40e_vsi_get_bw_config - Query VSI BW Information
4745  * @vsi: the VSI to be queried
4746  *
4747  * Returns 0 on success, negative value on failure
4748  */
4749 static enum i40e_status_code
4750 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4751 {
4752         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4753         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4754         struct i40e_hw *hw = &vsi->adapter->hw;
4755         i40e_status ret;
4756         int i;
4757         uint32_t bw_max;
4758
4759         memset(&bw_config, 0, sizeof(bw_config));
4760         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4761         if (ret != I40E_SUCCESS) {
4762                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4763                             hw->aq.asq_last_status);
4764                 return ret;
4765         }
4766
4767         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4768         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4769                                         &ets_sla_config, NULL);
4770         if (ret != I40E_SUCCESS) {
4771                 PMD_DRV_LOG(ERR,
4772                         "VSI failed to get TC bandwdith configuration %u",
4773                         hw->aq.asq_last_status);
4774                 return ret;
4775         }
4776
4777         /* store and print out BW info */
4778         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4779         vsi->bw_info.bw_max = bw_config.max_bw;
4780         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4781         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4782         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4783                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4784                      I40E_16_BIT_WIDTH);
4785         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4786                 vsi->bw_info.bw_ets_share_credits[i] =
4787                                 ets_sla_config.share_credits[i];
4788                 vsi->bw_info.bw_ets_credits[i] =
4789                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4790                 /* 4 bits per TC, 4th bit is reserved */
4791                 vsi->bw_info.bw_ets_max[i] =
4792                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4793                                   RTE_LEN2MASK(3, uint8_t));
4794                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4795                             vsi->bw_info.bw_ets_share_credits[i]);
4796                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4797                             vsi->bw_info.bw_ets_credits[i]);
4798                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4799                             vsi->bw_info.bw_ets_max[i]);
4800         }
4801
4802         return I40E_SUCCESS;
4803 }
4804
4805 /* i40e_enable_pf_lb
4806  * @pf: pointer to the pf structure
4807  *
4808  * allow loopback on pf
4809  */
4810 static inline void
4811 i40e_enable_pf_lb(struct i40e_pf *pf)
4812 {
4813         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4814         struct i40e_vsi_context ctxt;
4815         int ret;
4816
4817         /* Use the FW API if FW >= v5.0 */
4818         if (hw->aq.fw_maj_ver < 5) {
4819                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4820                 return;
4821         }
4822
4823         memset(&ctxt, 0, sizeof(ctxt));
4824         ctxt.seid = pf->main_vsi_seid;
4825         ctxt.pf_num = hw->pf_id;
4826         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4827         if (ret) {
4828                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4829                             ret, hw->aq.asq_last_status);
4830                 return;
4831         }
4832         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4833         ctxt.info.valid_sections =
4834                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4835         ctxt.info.switch_id |=
4836                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4837
4838         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4839         if (ret)
4840                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4841                             hw->aq.asq_last_status);
4842 }
4843
4844 /* Setup a VSI */
4845 struct i40e_vsi *
4846 i40e_vsi_setup(struct i40e_pf *pf,
4847                enum i40e_vsi_type type,
4848                struct i40e_vsi *uplink_vsi,
4849                uint16_t user_param)
4850 {
4851         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4852         struct i40e_vsi *vsi;
4853         struct i40e_mac_filter_info filter;
4854         int ret;
4855         struct i40e_vsi_context ctxt;
4856         struct ether_addr broadcast =
4857                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4858
4859         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4860             uplink_vsi == NULL) {
4861                 PMD_DRV_LOG(ERR,
4862                         "VSI setup failed, VSI link shouldn't be NULL");
4863                 return NULL;
4864         }
4865
4866         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4867                 PMD_DRV_LOG(ERR,
4868                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4869                 return NULL;
4870         }
4871
4872         /* two situations
4873          * 1.type is not MAIN and uplink vsi is not NULL
4874          * If uplink vsi didn't setup VEB, create one first under veb field
4875          * 2.type is SRIOV and the uplink is NULL
4876          * If floating VEB is NULL, create one veb under floating veb field
4877          */
4878
4879         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4880             uplink_vsi->veb == NULL) {
4881                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4882
4883                 if (uplink_vsi->veb == NULL) {
4884                         PMD_DRV_LOG(ERR, "VEB setup failed");
4885                         return NULL;
4886                 }
4887                 /* set ALLOWLOOPBACk on pf, when veb is created */
4888                 i40e_enable_pf_lb(pf);
4889         }
4890
4891         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4892             pf->main_vsi->floating_veb == NULL) {
4893                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4894
4895                 if (pf->main_vsi->floating_veb == NULL) {
4896                         PMD_DRV_LOG(ERR, "VEB setup failed");
4897                         return NULL;
4898                 }
4899         }
4900
4901         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4902         if (!vsi) {
4903                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4904                 return NULL;
4905         }
4906         TAILQ_INIT(&vsi->mac_list);
4907         vsi->type = type;
4908         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4909         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4910         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4911         vsi->user_param = user_param;
4912         vsi->vlan_anti_spoof_on = 0;
4913         vsi->vlan_filter_on = 0;
4914         /* Allocate queues */
4915         switch (vsi->type) {
4916         case I40E_VSI_MAIN  :
4917                 vsi->nb_qps = pf->lan_nb_qps;
4918                 break;
4919         case I40E_VSI_SRIOV :
4920                 vsi->nb_qps = pf->vf_nb_qps;
4921                 break;
4922         case I40E_VSI_VMDQ2:
4923                 vsi->nb_qps = pf->vmdq_nb_qps;
4924                 break;
4925         case I40E_VSI_FDIR:
4926                 vsi->nb_qps = pf->fdir_nb_qps;
4927                 break;
4928         default:
4929                 goto fail_mem;
4930         }
4931         /*
4932          * The filter status descriptor is reported in rx queue 0,
4933          * while the tx queue for fdir filter programming has no
4934          * such constraints, can be non-zero queues.
4935          * To simplify it, choose FDIR vsi use queue 0 pair.
4936          * To make sure it will use queue 0 pair, queue allocation
4937          * need be done before this function is called
4938          */
4939         if (type != I40E_VSI_FDIR) {
4940                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4941                         if (ret < 0) {
4942                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4943                                                 vsi->seid, ret);
4944                                 goto fail_mem;
4945                         }
4946                         vsi->base_queue = ret;
4947         } else
4948                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4949
4950         /* VF has MSIX interrupt in VF range, don't allocate here */
4951         if (type == I40E_VSI_MAIN) {
4952                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4953                                           RTE_MIN(vsi->nb_qps,
4954                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4955                 if (ret < 0) {
4956                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4957                                     vsi->seid, ret);
4958                         goto fail_queue_alloc;
4959                 }
4960                 vsi->msix_intr = ret;
4961                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4962         } else if (type != I40E_VSI_SRIOV) {
4963                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4964                 if (ret < 0) {
4965                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4966                         goto fail_queue_alloc;
4967                 }
4968                 vsi->msix_intr = ret;
4969                 vsi->nb_msix = 1;
4970         } else {
4971                 vsi->msix_intr = 0;
4972                 vsi->nb_msix = 0;
4973         }
4974
4975         /* Add VSI */
4976         if (type == I40E_VSI_MAIN) {
4977                 /* For main VSI, no need to add since it's default one */
4978                 vsi->uplink_seid = pf->mac_seid;
4979                 vsi->seid = pf->main_vsi_seid;
4980                 /* Bind queues with specific MSIX interrupt */
4981                 /**
4982                  * Needs 2 interrupt at least, one for misc cause which will
4983                  * enabled from OS side, Another for queues binding the
4984                  * interrupt from device side only.
4985                  */
4986
4987                 /* Get default VSI parameters from hardware */
4988                 memset(&ctxt, 0, sizeof(ctxt));
4989                 ctxt.seid = vsi->seid;
4990                 ctxt.pf_num = hw->pf_id;
4991                 ctxt.uplink_seid = vsi->uplink_seid;
4992                 ctxt.vf_num = 0;
4993                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4994                 if (ret != I40E_SUCCESS) {
4995                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4996                         goto fail_msix_alloc;
4997                 }
4998                 rte_memcpy(&vsi->info, &ctxt.info,
4999                         sizeof(struct i40e_aqc_vsi_properties_data));
5000                 vsi->vsi_id = ctxt.vsi_number;
5001                 vsi->info.valid_sections = 0;
5002
5003                 /* Configure tc, enabled TC0 only */
5004                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5005                         I40E_SUCCESS) {
5006                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5007                         goto fail_msix_alloc;
5008                 }
5009
5010                 /* TC, queue mapping */
5011                 memset(&ctxt, 0, sizeof(ctxt));
5012                 vsi->info.valid_sections |=
5013                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5014                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5015                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5016                 rte_memcpy(&ctxt.info, &vsi->info,
5017                         sizeof(struct i40e_aqc_vsi_properties_data));
5018                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5019                                                 I40E_DEFAULT_TCMAP);
5020                 if (ret != I40E_SUCCESS) {
5021                         PMD_DRV_LOG(ERR,
5022                                 "Failed to configure TC queue mapping");
5023                         goto fail_msix_alloc;
5024                 }
5025                 ctxt.seid = vsi->seid;
5026                 ctxt.pf_num = hw->pf_id;
5027                 ctxt.uplink_seid = vsi->uplink_seid;
5028                 ctxt.vf_num = 0;
5029
5030                 /* Update VSI parameters */
5031                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5032                 if (ret != I40E_SUCCESS) {
5033                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5034                         goto fail_msix_alloc;
5035                 }
5036
5037                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5038                                                 sizeof(vsi->info.tc_mapping));
5039                 rte_memcpy(&vsi->info.queue_mapping,
5040                                 &ctxt.info.queue_mapping,
5041                         sizeof(vsi->info.queue_mapping));
5042                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5043                 vsi->info.valid_sections = 0;
5044
5045                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5046                                 ETH_ADDR_LEN);
5047
5048                 /**
5049                  * Updating default filter settings are necessary to prevent
5050                  * reception of tagged packets.
5051                  * Some old firmware configurations load a default macvlan
5052                  * filter which accepts both tagged and untagged packets.
5053                  * The updating is to use a normal filter instead if needed.
5054                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5055                  * The firmware with correct configurations load the default
5056                  * macvlan filter which is expected and cannot be removed.
5057                  */
5058                 i40e_update_default_filter_setting(vsi);
5059                 i40e_config_qinq(hw, vsi);
5060         } else if (type == I40E_VSI_SRIOV) {
5061                 memset(&ctxt, 0, sizeof(ctxt));
5062                 /**
5063                  * For other VSI, the uplink_seid equals to uplink VSI's
5064                  * uplink_seid since they share same VEB
5065                  */
5066                 if (uplink_vsi == NULL)
5067                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5068                 else
5069                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5070                 ctxt.pf_num = hw->pf_id;
5071                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5072                 ctxt.uplink_seid = vsi->uplink_seid;
5073                 ctxt.connection_type = 0x1;
5074                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5075
5076                 /* Use the VEB configuration if FW >= v5.0 */
5077                 if (hw->aq.fw_maj_ver >= 5) {
5078                         /* Configure switch ID */
5079                         ctxt.info.valid_sections |=
5080                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5081                         ctxt.info.switch_id =
5082                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5083                 }
5084
5085                 /* Configure port/vlan */
5086                 ctxt.info.valid_sections |=
5087                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5088                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5089                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5090                                                 hw->func_caps.enabled_tcmap);
5091                 if (ret != I40E_SUCCESS) {
5092                         PMD_DRV_LOG(ERR,
5093                                 "Failed to configure TC queue mapping");
5094                         goto fail_msix_alloc;
5095                 }
5096
5097                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5098                 ctxt.info.valid_sections |=
5099                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5100                 /**
5101                  * Since VSI is not created yet, only configure parameter,
5102                  * will add vsi below.
5103                  */
5104
5105                 i40e_config_qinq(hw, vsi);
5106         } else if (type == I40E_VSI_VMDQ2) {
5107                 memset(&ctxt, 0, sizeof(ctxt));
5108                 /*
5109                  * For other VSI, the uplink_seid equals to uplink VSI's
5110                  * uplink_seid since they share same VEB
5111                  */
5112                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5113                 ctxt.pf_num = hw->pf_id;
5114                 ctxt.vf_num = 0;
5115                 ctxt.uplink_seid = vsi->uplink_seid;
5116                 ctxt.connection_type = 0x1;
5117                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5118
5119                 ctxt.info.valid_sections |=
5120                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5121                 /* user_param carries flag to enable loop back */
5122                 if (user_param) {
5123                         ctxt.info.switch_id =
5124                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5125                         ctxt.info.switch_id |=
5126                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5127                 }
5128
5129                 /* Configure port/vlan */
5130                 ctxt.info.valid_sections |=
5131                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5132                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5133                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5134                                                 I40E_DEFAULT_TCMAP);
5135                 if (ret != I40E_SUCCESS) {
5136                         PMD_DRV_LOG(ERR,
5137                                 "Failed to configure TC queue mapping");
5138                         goto fail_msix_alloc;
5139                 }
5140                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5141                 ctxt.info.valid_sections |=
5142                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5143         } else if (type == I40E_VSI_FDIR) {
5144                 memset(&ctxt, 0, sizeof(ctxt));
5145                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5146                 ctxt.pf_num = hw->pf_id;
5147                 ctxt.vf_num = 0;
5148                 ctxt.uplink_seid = vsi->uplink_seid;
5149                 ctxt.connection_type = 0x1;     /* regular data port */
5150                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5151                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5152                                                 I40E_DEFAULT_TCMAP);
5153                 if (ret != I40E_SUCCESS) {
5154                         PMD_DRV_LOG(ERR,
5155                                 "Failed to configure TC queue mapping.");
5156                         goto fail_msix_alloc;
5157                 }
5158                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5159                 ctxt.info.valid_sections |=
5160                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5161         } else {
5162                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5163                 goto fail_msix_alloc;
5164         }
5165
5166         if (vsi->type != I40E_VSI_MAIN) {
5167                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5168                 if (ret != I40E_SUCCESS) {
5169                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5170                                     hw->aq.asq_last_status);
5171                         goto fail_msix_alloc;
5172                 }
5173                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5174                 vsi->info.valid_sections = 0;
5175                 vsi->seid = ctxt.seid;
5176                 vsi->vsi_id = ctxt.vsi_number;
5177                 vsi->sib_vsi_list.vsi = vsi;
5178                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5179                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5180                                           &vsi->sib_vsi_list, list);
5181                 } else {
5182                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5183                                           &vsi->sib_vsi_list, list);
5184                 }
5185         }
5186
5187         /* MAC/VLAN configuration */
5188         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5189         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5190
5191         ret = i40e_vsi_add_mac(vsi, &filter);
5192         if (ret != I40E_SUCCESS) {
5193                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5194                 goto fail_msix_alloc;
5195         }
5196
5197         /* Get VSI BW information */
5198         i40e_vsi_get_bw_config(vsi);
5199         return vsi;
5200 fail_msix_alloc:
5201         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5202 fail_queue_alloc:
5203         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5204 fail_mem:
5205         rte_free(vsi);
5206         return NULL;
5207 }
5208
5209 /* Configure vlan filter on or off */
5210 int
5211 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5212 {
5213         int i, num;
5214         struct i40e_mac_filter *f;
5215         void *temp;
5216         struct i40e_mac_filter_info *mac_filter;
5217         enum rte_mac_filter_type desired_filter;
5218         int ret = I40E_SUCCESS;
5219
5220         if (on) {
5221                 /* Filter to match MAC and VLAN */
5222                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5223         } else {
5224                 /* Filter to match only MAC */
5225                 desired_filter = RTE_MAC_PERFECT_MATCH;
5226         }
5227
5228         num = vsi->mac_num;
5229
5230         mac_filter = rte_zmalloc("mac_filter_info_data",
5231                                  num * sizeof(*mac_filter), 0);
5232         if (mac_filter == NULL) {
5233                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5234                 return I40E_ERR_NO_MEMORY;
5235         }
5236
5237         i = 0;
5238
5239         /* Remove all existing mac */
5240         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5241                 mac_filter[i] = f->mac_info;
5242                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5243                 if (ret) {
5244                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5245                                     on ? "enable" : "disable");
5246                         goto DONE;
5247                 }
5248                 i++;
5249         }
5250
5251         /* Override with new filter */
5252         for (i = 0; i < num; i++) {
5253                 mac_filter[i].filter_type = desired_filter;
5254                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5255                 if (ret) {
5256                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5257                                     on ? "enable" : "disable");
5258                         goto DONE;
5259                 }
5260         }
5261
5262 DONE:
5263         rte_free(mac_filter);
5264         return ret;
5265 }
5266
5267 /* Configure vlan stripping on or off */
5268 int
5269 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5270 {
5271         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5272         struct i40e_vsi_context ctxt;
5273         uint8_t vlan_flags;
5274         int ret = I40E_SUCCESS;
5275
5276         /* Check if it has been already on or off */
5277         if (vsi->info.valid_sections &
5278                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5279                 if (on) {
5280                         if ((vsi->info.port_vlan_flags &
5281                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5282                                 return 0; /* already on */
5283                 } else {
5284                         if ((vsi->info.port_vlan_flags &
5285                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5286                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5287                                 return 0; /* already off */
5288                 }
5289         }
5290
5291         if (on)
5292                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5293         else
5294                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5295         vsi->info.valid_sections =
5296                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5297         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5298         vsi->info.port_vlan_flags |= vlan_flags;
5299         ctxt.seid = vsi->seid;
5300         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5301         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5302         if (ret)
5303                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5304                             on ? "enable" : "disable");
5305
5306         return ret;
5307 }
5308
5309 static int
5310 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5311 {
5312         struct rte_eth_dev_data *data = dev->data;
5313         int ret;
5314         int mask = 0;
5315
5316         /* Apply vlan offload setting */
5317         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5318         ret = i40e_vlan_offload_set(dev, mask);
5319         if (ret) {
5320                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5321                 return ret;
5322         }
5323
5324         /* Apply double-vlan setting, not implemented yet */
5325
5326         /* Apply pvid setting */
5327         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5328                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5329         if (ret)
5330                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5331
5332         return ret;
5333 }
5334
5335 static int
5336 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5337 {
5338         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5339
5340         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5341 }
5342
5343 static int
5344 i40e_update_flow_control(struct i40e_hw *hw)
5345 {
5346 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5347         struct i40e_link_status link_status;
5348         uint32_t rxfc = 0, txfc = 0, reg;
5349         uint8_t an_info;
5350         int ret;
5351
5352         memset(&link_status, 0, sizeof(link_status));
5353         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5354         if (ret != I40E_SUCCESS) {
5355                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5356                 goto write_reg; /* Disable flow control */
5357         }
5358
5359         an_info = hw->phy.link_info.an_info;
5360         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5361                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5362                 ret = I40E_ERR_NOT_READY;
5363                 goto write_reg; /* Disable flow control */
5364         }
5365         /**
5366          * If link auto negotiation is enabled, flow control needs to
5367          * be configured according to it
5368          */
5369         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5370         case I40E_LINK_PAUSE_RXTX:
5371                 rxfc = 1;
5372                 txfc = 1;
5373                 hw->fc.current_mode = I40E_FC_FULL;
5374                 break;
5375         case I40E_AQ_LINK_PAUSE_RX:
5376                 rxfc = 1;
5377                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5378                 break;
5379         case I40E_AQ_LINK_PAUSE_TX:
5380                 txfc = 1;
5381                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5382                 break;
5383         default:
5384                 hw->fc.current_mode = I40E_FC_NONE;
5385                 break;
5386         }
5387
5388 write_reg:
5389         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5390                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5391         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5392         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5393         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5394         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5395
5396         return ret;
5397 }
5398
5399 /* PF setup */
5400 static int
5401 i40e_pf_setup(struct i40e_pf *pf)
5402 {
5403         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5404         struct i40e_filter_control_settings settings;
5405         struct i40e_vsi *vsi;
5406         int ret;
5407
5408         /* Clear all stats counters */
5409         pf->offset_loaded = FALSE;
5410         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5411         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5412         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5413         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5414
5415         ret = i40e_pf_get_switch_config(pf);
5416         if (ret != I40E_SUCCESS) {
5417                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5418                 return ret;
5419         }
5420         if (pf->flags & I40E_FLAG_FDIR) {
5421                 /* make queue allocated first, let FDIR use queue pair 0*/
5422                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5423                 if (ret != I40E_FDIR_QUEUE_ID) {
5424                         PMD_DRV_LOG(ERR,
5425                                 "queue allocation fails for FDIR: ret =%d",
5426                                 ret);
5427                         pf->flags &= ~I40E_FLAG_FDIR;
5428                 }
5429         }
5430         /*  main VSI setup */
5431         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5432         if (!vsi) {
5433                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5434                 return I40E_ERR_NOT_READY;
5435         }
5436         pf->main_vsi = vsi;
5437
5438         /* Configure filter control */
5439         memset(&settings, 0, sizeof(settings));
5440         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5441                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5442         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5443                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5444         else {
5445                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5446                         hw->func_caps.rss_table_size);
5447                 return I40E_ERR_PARAM;
5448         }
5449         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5450                 hw->func_caps.rss_table_size);
5451         pf->hash_lut_size = hw->func_caps.rss_table_size;
5452
5453         /* Enable ethtype and macvlan filters */
5454         settings.enable_ethtype = TRUE;
5455         settings.enable_macvlan = TRUE;
5456         ret = i40e_set_filter_control(hw, &settings);
5457         if (ret)
5458                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5459                                                                 ret);
5460
5461         /* Update flow control according to the auto negotiation */
5462         i40e_update_flow_control(hw);
5463
5464         return I40E_SUCCESS;
5465 }
5466
5467 int
5468 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5469 {
5470         uint32_t reg;
5471         uint16_t j;
5472
5473         /**
5474          * Set or clear TX Queue Disable flags,
5475          * which is required by hardware.
5476          */
5477         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5478         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5479
5480         /* Wait until the request is finished */
5481         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5482                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5483                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5484                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5485                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5486                                                         & 0x1))) {
5487                         break;
5488                 }
5489         }
5490         if (on) {
5491                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5492                         return I40E_SUCCESS; /* already on, skip next steps */
5493
5494                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5495                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5496         } else {
5497                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5498                         return I40E_SUCCESS; /* already off, skip next steps */
5499                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5500         }
5501         /* Write the register */
5502         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5503         /* Check the result */
5504         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5505                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5506                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5507                 if (on) {
5508                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5509                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5510                                 break;
5511                 } else {
5512                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5513                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5514                                 break;
5515                 }
5516         }
5517         /* Check if it is timeout */
5518         if (j >= I40E_CHK_Q_ENA_COUNT) {
5519                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5520                             (on ? "enable" : "disable"), q_idx);
5521                 return I40E_ERR_TIMEOUT;
5522         }
5523
5524         return I40E_SUCCESS;
5525 }
5526
5527 /* Swith on or off the tx queues */
5528 static int
5529 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5530 {
5531         struct rte_eth_dev_data *dev_data = pf->dev_data;
5532         struct i40e_tx_queue *txq;
5533         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5534         uint16_t i;
5535         int ret;
5536
5537         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5538                 txq = dev_data->tx_queues[i];
5539                 /* Don't operate the queue if not configured or
5540                  * if starting only per queue */
5541                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5542                         continue;
5543                 if (on)
5544                         ret = i40e_dev_tx_queue_start(dev, i);
5545                 else
5546                         ret = i40e_dev_tx_queue_stop(dev, i);
5547                 if ( ret != I40E_SUCCESS)
5548                         return ret;
5549         }
5550
5551         return I40E_SUCCESS;
5552 }
5553
5554 int
5555 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5556 {
5557         uint32_t reg;
5558         uint16_t j;
5559
5560         /* Wait until the request is finished */
5561         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5562                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5563                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5564                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5565                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5566                         break;
5567         }
5568
5569         if (on) {
5570                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5571                         return I40E_SUCCESS; /* Already on, skip next steps */
5572                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5573         } else {
5574                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5575                         return I40E_SUCCESS; /* Already off, skip next steps */
5576                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5577         }
5578
5579         /* Write the register */
5580         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5581         /* Check the result */
5582         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5583                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5584                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5585                 if (on) {
5586                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5587                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5588                                 break;
5589                 } else {
5590                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5591                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5592                                 break;
5593                 }
5594         }
5595
5596         /* Check if it is timeout */
5597         if (j >= I40E_CHK_Q_ENA_COUNT) {
5598                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5599                             (on ? "enable" : "disable"), q_idx);
5600                 return I40E_ERR_TIMEOUT;
5601         }
5602
5603         return I40E_SUCCESS;
5604 }
5605 /* Switch on or off the rx queues */
5606 static int
5607 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5608 {
5609         struct rte_eth_dev_data *dev_data = pf->dev_data;
5610         struct i40e_rx_queue *rxq;
5611         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5612         uint16_t i;
5613         int ret;
5614
5615         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5616                 rxq = dev_data->rx_queues[i];
5617                 /* Don't operate the queue if not configured or
5618                  * if starting only per queue */
5619                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5620                         continue;
5621                 if (on)
5622                         ret = i40e_dev_rx_queue_start(dev, i);
5623                 else
5624                         ret = i40e_dev_rx_queue_stop(dev, i);
5625                 if (ret != I40E_SUCCESS)
5626                         return ret;
5627         }
5628
5629         return I40E_SUCCESS;
5630 }
5631
5632 /* Switch on or off all the rx/tx queues */
5633 int
5634 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5635 {
5636         int ret;
5637
5638         if (on) {
5639                 /* enable rx queues before enabling tx queues */
5640                 ret = i40e_dev_switch_rx_queues(pf, on);
5641                 if (ret) {
5642                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5643                         return ret;
5644                 }
5645                 ret = i40e_dev_switch_tx_queues(pf, on);
5646         } else {
5647                 /* Stop tx queues before stopping rx queues */
5648                 ret = i40e_dev_switch_tx_queues(pf, on);
5649                 if (ret) {
5650                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5651                         return ret;
5652                 }
5653                 ret = i40e_dev_switch_rx_queues(pf, on);
5654         }
5655
5656         return ret;
5657 }
5658
5659 /* Initialize VSI for TX */
5660 static int
5661 i40e_dev_tx_init(struct i40e_pf *pf)
5662 {
5663         struct rte_eth_dev_data *data = pf->dev_data;
5664         uint16_t i;
5665         uint32_t ret = I40E_SUCCESS;
5666         struct i40e_tx_queue *txq;
5667
5668         for (i = 0; i < data->nb_tx_queues; i++) {
5669                 txq = data->tx_queues[i];
5670                 if (!txq || !txq->q_set)
5671                         continue;
5672                 ret = i40e_tx_queue_init(txq);
5673                 if (ret != I40E_SUCCESS)
5674                         break;
5675         }
5676         if (ret == I40E_SUCCESS)
5677                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5678                                      ->eth_dev);
5679
5680         return ret;
5681 }
5682
5683 /* Initialize VSI for RX */
5684 static int
5685 i40e_dev_rx_init(struct i40e_pf *pf)
5686 {
5687         struct rte_eth_dev_data *data = pf->dev_data;
5688         int ret = I40E_SUCCESS;
5689         uint16_t i;
5690         struct i40e_rx_queue *rxq;
5691
5692         i40e_pf_config_mq_rx(pf);
5693         for (i = 0; i < data->nb_rx_queues; i++) {
5694                 rxq = data->rx_queues[i];
5695                 if (!rxq || !rxq->q_set)
5696                         continue;
5697
5698                 ret = i40e_rx_queue_init(rxq);
5699                 if (ret != I40E_SUCCESS) {
5700                         PMD_DRV_LOG(ERR,
5701                                 "Failed to do RX queue initialization");
5702                         break;
5703                 }
5704         }
5705         if (ret == I40E_SUCCESS)
5706                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5707                                      ->eth_dev);
5708
5709         return ret;
5710 }
5711
5712 static int
5713 i40e_dev_rxtx_init(struct i40e_pf *pf)
5714 {
5715         int err;
5716
5717         err = i40e_dev_tx_init(pf);
5718         if (err) {
5719                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5720                 return err;
5721         }
5722         err = i40e_dev_rx_init(pf);
5723         if (err) {
5724                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5725                 return err;
5726         }
5727
5728         return err;
5729 }
5730
5731 static int
5732 i40e_vmdq_setup(struct rte_eth_dev *dev)
5733 {
5734         struct rte_eth_conf *conf = &dev->data->dev_conf;
5735         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5736         int i, err, conf_vsis, j, loop;
5737         struct i40e_vsi *vsi;
5738         struct i40e_vmdq_info *vmdq_info;
5739         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5740         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5741
5742         /*
5743          * Disable interrupt to avoid message from VF. Furthermore, it will
5744          * avoid race condition in VSI creation/destroy.
5745          */
5746         i40e_pf_disable_irq0(hw);
5747
5748         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5749                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5750                 return -ENOTSUP;
5751         }
5752
5753         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5754         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5755                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5756                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5757                         pf->max_nb_vmdq_vsi);
5758                 return -ENOTSUP;
5759         }
5760
5761         if (pf->vmdq != NULL) {
5762                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5763                 return 0;
5764         }
5765
5766         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5767                                 sizeof(*vmdq_info) * conf_vsis, 0);
5768
5769         if (pf->vmdq == NULL) {
5770                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5771                 return -ENOMEM;
5772         }
5773
5774         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5775
5776         /* Create VMDQ VSI */
5777         for (i = 0; i < conf_vsis; i++) {
5778                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5779                                 vmdq_conf->enable_loop_back);
5780                 if (vsi == NULL) {
5781                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5782                         err = -1;
5783                         goto err_vsi_setup;
5784                 }
5785                 vmdq_info = &pf->vmdq[i];
5786                 vmdq_info->pf = pf;
5787                 vmdq_info->vsi = vsi;
5788         }
5789         pf->nb_cfg_vmdq_vsi = conf_vsis;
5790
5791         /* Configure Vlan */
5792         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5793         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5794                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5795                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5796                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5797                                         vmdq_conf->pool_map[i].vlan_id, j);
5798
5799                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5800                                                 vmdq_conf->pool_map[i].vlan_id);
5801                                 if (err) {
5802                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5803                                         err = -1;
5804                                         goto err_vsi_setup;
5805                                 }
5806                         }
5807                 }
5808         }
5809
5810         i40e_pf_enable_irq0(hw);
5811
5812         return 0;
5813
5814 err_vsi_setup:
5815         for (i = 0; i < conf_vsis; i++)
5816                 if (pf->vmdq[i].vsi == NULL)
5817                         break;
5818                 else
5819                         i40e_vsi_release(pf->vmdq[i].vsi);
5820
5821         rte_free(pf->vmdq);
5822         pf->vmdq = NULL;
5823         i40e_pf_enable_irq0(hw);
5824         return err;
5825 }
5826
5827 static void
5828 i40e_stat_update_32(struct i40e_hw *hw,
5829                    uint32_t reg,
5830                    bool offset_loaded,
5831                    uint64_t *offset,
5832                    uint64_t *stat)
5833 {
5834         uint64_t new_data;
5835
5836         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5837         if (!offset_loaded)
5838                 *offset = new_data;
5839
5840         if (new_data >= *offset)
5841                 *stat = (uint64_t)(new_data - *offset);
5842         else
5843                 *stat = (uint64_t)((new_data +
5844                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5845 }
5846
5847 static void
5848 i40e_stat_update_48(struct i40e_hw *hw,
5849                    uint32_t hireg,
5850                    uint32_t loreg,
5851                    bool offset_loaded,
5852                    uint64_t *offset,
5853                    uint64_t *stat)
5854 {
5855         uint64_t new_data;
5856
5857         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5858         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5859                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5860
5861         if (!offset_loaded)
5862                 *offset = new_data;
5863
5864         if (new_data >= *offset)
5865                 *stat = new_data - *offset;
5866         else
5867                 *stat = (uint64_t)((new_data +
5868                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5869
5870         *stat &= I40E_48_BIT_MASK;
5871 }
5872
5873 /* Disable IRQ0 */
5874 void
5875 i40e_pf_disable_irq0(struct i40e_hw *hw)
5876 {
5877         /* Disable all interrupt types */
5878         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5879         I40E_WRITE_FLUSH(hw);
5880 }
5881
5882 /* Enable IRQ0 */
5883 void
5884 i40e_pf_enable_irq0(struct i40e_hw *hw)
5885 {
5886         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5887                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5888                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5889                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5890         I40E_WRITE_FLUSH(hw);
5891 }
5892
5893 static void
5894 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5895 {
5896         /* read pending request and disable first */
5897         i40e_pf_disable_irq0(hw);
5898         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5899         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5900                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5901
5902         if (no_queue)
5903                 /* Link no queues with irq0 */
5904                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5905                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5906 }
5907
5908 static void
5909 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5910 {
5911         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5912         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5913         int i;
5914         uint16_t abs_vf_id;
5915         uint32_t index, offset, val;
5916
5917         if (!pf->vfs)
5918                 return;
5919         /**
5920          * Try to find which VF trigger a reset, use absolute VF id to access
5921          * since the reg is global register.
5922          */
5923         for (i = 0; i < pf->vf_num; i++) {
5924                 abs_vf_id = hw->func_caps.vf_base_id + i;
5925                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5926                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5927                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5928                 /* VFR event occurred */
5929                 if (val & (0x1 << offset)) {
5930                         int ret;
5931
5932                         /* Clear the event first */
5933                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5934                                                         (0x1 << offset));
5935                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5936                         /**
5937                          * Only notify a VF reset event occurred,
5938                          * don't trigger another SW reset
5939                          */
5940                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5941                         if (ret != I40E_SUCCESS)
5942                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5943                 }
5944         }
5945 }
5946
5947 static void
5948 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5949 {
5950         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5951         int i;
5952
5953         for (i = 0; i < pf->vf_num; i++)
5954                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5955 }
5956
5957 static void
5958 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5959 {
5960         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5961         struct i40e_arq_event_info info;
5962         uint16_t pending, opcode;
5963         int ret;
5964
5965         info.buf_len = I40E_AQ_BUF_SZ;
5966         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5967         if (!info.msg_buf) {
5968                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5969                 return;
5970         }
5971
5972         pending = 1;
5973         while (pending) {
5974                 ret = i40e_clean_arq_element(hw, &info, &pending);
5975
5976                 if (ret != I40E_SUCCESS) {
5977                         PMD_DRV_LOG(INFO,
5978                                 "Failed to read msg from AdminQ, aq_err: %u",
5979                                 hw->aq.asq_last_status);
5980                         break;
5981                 }
5982                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5983
5984                 switch (opcode) {
5985                 case i40e_aqc_opc_send_msg_to_pf:
5986                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5987                         i40e_pf_host_handle_vf_msg(dev,
5988                                         rte_le_to_cpu_16(info.desc.retval),
5989                                         rte_le_to_cpu_32(info.desc.cookie_high),
5990                                         rte_le_to_cpu_32(info.desc.cookie_low),
5991                                         info.msg_buf,
5992                                         info.msg_len);
5993                         break;
5994                 case i40e_aqc_opc_get_link_status:
5995                         ret = i40e_dev_link_update(dev, 0);
5996                         if (!ret)
5997                                 _rte_eth_dev_callback_process(dev,
5998                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5999                         break;
6000                 default:
6001                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6002                                     opcode);
6003                         break;
6004                 }
6005         }
6006         rte_free(info.msg_buf);
6007 }
6008
6009 /**
6010  * Interrupt handler triggered by NIC  for handling
6011  * specific interrupt.
6012  *
6013  * @param handle
6014  *  Pointer to interrupt handle.
6015  * @param param
6016  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6017  *
6018  * @return
6019  *  void
6020  */
6021 static void
6022 i40e_dev_interrupt_handler(void *param)
6023 {
6024         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6025         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6026         uint32_t icr0;
6027
6028         /* Disable interrupt */
6029         i40e_pf_disable_irq0(hw);
6030
6031         /* read out interrupt causes */
6032         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6033
6034         /* No interrupt event indicated */
6035         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6036                 PMD_DRV_LOG(INFO, "No interrupt event");
6037                 goto done;
6038         }
6039         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6040                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6041         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6042                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6043         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6044                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6045         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6046                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6047         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6048                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6049         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6050                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6051         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6052                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6053
6054         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6055                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6056                 i40e_dev_handle_vfr_event(dev);
6057         }
6058         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6059                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6060                 i40e_dev_handle_aq_msg(dev);
6061         }
6062
6063 done:
6064         /* Enable interrupt */
6065         i40e_pf_enable_irq0(hw);
6066         rte_intr_enable(dev->intr_handle);
6067 }
6068
6069 int
6070 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6071                          struct i40e_macvlan_filter *filter,
6072                          int total)
6073 {
6074         int ele_num, ele_buff_size;
6075         int num, actual_num, i;
6076         uint16_t flags;
6077         int ret = I40E_SUCCESS;
6078         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6079         struct i40e_aqc_add_macvlan_element_data *req_list;
6080
6081         if (filter == NULL  || total == 0)
6082                 return I40E_ERR_PARAM;
6083         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6084         ele_buff_size = hw->aq.asq_buf_size;
6085
6086         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6087         if (req_list == NULL) {
6088                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6089                 return I40E_ERR_NO_MEMORY;
6090         }
6091
6092         num = 0;
6093         do {
6094                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6095                 memset(req_list, 0, ele_buff_size);
6096
6097                 for (i = 0; i < actual_num; i++) {
6098                         rte_memcpy(req_list[i].mac_addr,
6099                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6100                         req_list[i].vlan_tag =
6101                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6102
6103                         switch (filter[num + i].filter_type) {
6104                         case RTE_MAC_PERFECT_MATCH:
6105                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6106                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6107                                 break;
6108                         case RTE_MACVLAN_PERFECT_MATCH:
6109                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6110                                 break;
6111                         case RTE_MAC_HASH_MATCH:
6112                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6113                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6114                                 break;
6115                         case RTE_MACVLAN_HASH_MATCH:
6116                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6117                                 break;
6118                         default:
6119                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6120                                 ret = I40E_ERR_PARAM;
6121                                 goto DONE;
6122                         }
6123
6124                         req_list[i].queue_number = 0;
6125
6126                         req_list[i].flags = rte_cpu_to_le_16(flags);
6127                 }
6128
6129                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6130                                                 actual_num, NULL);
6131                 if (ret != I40E_SUCCESS) {
6132                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6133                         goto DONE;
6134                 }
6135                 num += actual_num;
6136         } while (num < total);
6137
6138 DONE:
6139         rte_free(req_list);
6140         return ret;
6141 }
6142
6143 int
6144 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6145                             struct i40e_macvlan_filter *filter,
6146                             int total)
6147 {
6148         int ele_num, ele_buff_size;
6149         int num, actual_num, i;
6150         uint16_t flags;
6151         int ret = I40E_SUCCESS;
6152         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6153         struct i40e_aqc_remove_macvlan_element_data *req_list;
6154
6155         if (filter == NULL  || total == 0)
6156                 return I40E_ERR_PARAM;
6157
6158         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6159         ele_buff_size = hw->aq.asq_buf_size;
6160
6161         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6162         if (req_list == NULL) {
6163                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6164                 return I40E_ERR_NO_MEMORY;
6165         }
6166
6167         num = 0;
6168         do {
6169                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6170                 memset(req_list, 0, ele_buff_size);
6171
6172                 for (i = 0; i < actual_num; i++) {
6173                         rte_memcpy(req_list[i].mac_addr,
6174                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6175                         req_list[i].vlan_tag =
6176                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6177
6178                         switch (filter[num + i].filter_type) {
6179                         case RTE_MAC_PERFECT_MATCH:
6180                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6181                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6182                                 break;
6183                         case RTE_MACVLAN_PERFECT_MATCH:
6184                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6185                                 break;
6186                         case RTE_MAC_HASH_MATCH:
6187                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6188                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6189                                 break;
6190                         case RTE_MACVLAN_HASH_MATCH:
6191                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6192                                 break;
6193                         default:
6194                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6195                                 ret = I40E_ERR_PARAM;
6196                                 goto DONE;
6197                         }
6198                         req_list[i].flags = rte_cpu_to_le_16(flags);
6199                 }
6200
6201                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6202                                                 actual_num, NULL);
6203                 if (ret != I40E_SUCCESS) {
6204                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6205                         goto DONE;
6206                 }
6207                 num += actual_num;
6208         } while (num < total);
6209
6210 DONE:
6211         rte_free(req_list);
6212         return ret;
6213 }
6214
6215 /* Find out specific MAC filter */
6216 static struct i40e_mac_filter *
6217 i40e_find_mac_filter(struct i40e_vsi *vsi,
6218                          struct ether_addr *macaddr)
6219 {
6220         struct i40e_mac_filter *f;
6221
6222         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6223                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6224                         return f;
6225         }
6226
6227         return NULL;
6228 }
6229
6230 static bool
6231 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6232                          uint16_t vlan_id)
6233 {
6234         uint32_t vid_idx, vid_bit;
6235
6236         if (vlan_id > ETH_VLAN_ID_MAX)
6237                 return 0;
6238
6239         vid_idx = I40E_VFTA_IDX(vlan_id);
6240         vid_bit = I40E_VFTA_BIT(vlan_id);
6241
6242         if (vsi->vfta[vid_idx] & vid_bit)
6243                 return 1;
6244         else
6245                 return 0;
6246 }
6247
6248 static void
6249 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6250                        uint16_t vlan_id, bool on)
6251 {
6252         uint32_t vid_idx, vid_bit;
6253
6254         vid_idx = I40E_VFTA_IDX(vlan_id);
6255         vid_bit = I40E_VFTA_BIT(vlan_id);
6256
6257         if (on)
6258                 vsi->vfta[vid_idx] |= vid_bit;
6259         else
6260                 vsi->vfta[vid_idx] &= ~vid_bit;
6261 }
6262
6263 void
6264 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6265                      uint16_t vlan_id, bool on)
6266 {
6267         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6268         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6269         int ret;
6270
6271         if (vlan_id > ETH_VLAN_ID_MAX)
6272                 return;
6273
6274         i40e_store_vlan_filter(vsi, vlan_id, on);
6275
6276         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6277                 return;
6278
6279         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6280
6281         if (on) {
6282                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6283                                        &vlan_data, 1, NULL);
6284                 if (ret != I40E_SUCCESS)
6285                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6286         } else {
6287                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6288                                           &vlan_data, 1, NULL);
6289                 if (ret != I40E_SUCCESS)
6290                         PMD_DRV_LOG(ERR,
6291                                     "Failed to remove vlan filter");
6292         }
6293 }
6294
6295 /**
6296  * Find all vlan options for specific mac addr,
6297  * return with actual vlan found.
6298  */
6299 int
6300 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6301                            struct i40e_macvlan_filter *mv_f,
6302                            int num, struct ether_addr *addr)
6303 {
6304         int i;
6305         uint32_t j, k;
6306
6307         /**
6308          * Not to use i40e_find_vlan_filter to decrease the loop time,
6309          * although the code looks complex.
6310           */
6311         if (num < vsi->vlan_num)
6312                 return I40E_ERR_PARAM;
6313
6314         i = 0;
6315         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6316                 if (vsi->vfta[j]) {
6317                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6318                                 if (vsi->vfta[j] & (1 << k)) {
6319                                         if (i > num - 1) {
6320                                                 PMD_DRV_LOG(ERR,
6321                                                         "vlan number doesn't match");
6322                                                 return I40E_ERR_PARAM;
6323                                         }
6324                                         rte_memcpy(&mv_f[i].macaddr,
6325                                                         addr, ETH_ADDR_LEN);
6326                                         mv_f[i].vlan_id =
6327                                                 j * I40E_UINT32_BIT_SIZE + k;
6328                                         i++;
6329                                 }
6330                         }
6331                 }
6332         }
6333         return I40E_SUCCESS;
6334 }
6335
6336 static inline int
6337 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6338                            struct i40e_macvlan_filter *mv_f,
6339                            int num,
6340                            uint16_t vlan)
6341 {
6342         int i = 0;
6343         struct i40e_mac_filter *f;
6344
6345         if (num < vsi->mac_num)
6346                 return I40E_ERR_PARAM;
6347
6348         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6349                 if (i > num - 1) {
6350                         PMD_DRV_LOG(ERR, "buffer number not match");
6351                         return I40E_ERR_PARAM;
6352                 }
6353                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6354                                 ETH_ADDR_LEN);
6355                 mv_f[i].vlan_id = vlan;
6356                 mv_f[i].filter_type = f->mac_info.filter_type;
6357                 i++;
6358         }
6359
6360         return I40E_SUCCESS;
6361 }
6362
6363 static int
6364 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6365 {
6366         int i, j, num;
6367         struct i40e_mac_filter *f;
6368         struct i40e_macvlan_filter *mv_f;
6369         int ret = I40E_SUCCESS;
6370
6371         if (vsi == NULL || vsi->mac_num == 0)
6372                 return I40E_ERR_PARAM;
6373
6374         /* Case that no vlan is set */
6375         if (vsi->vlan_num == 0)
6376                 num = vsi->mac_num;
6377         else
6378                 num = vsi->mac_num * vsi->vlan_num;
6379
6380         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6381         if (mv_f == NULL) {
6382                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6383                 return I40E_ERR_NO_MEMORY;
6384         }
6385
6386         i = 0;
6387         if (vsi->vlan_num == 0) {
6388                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6389                         rte_memcpy(&mv_f[i].macaddr,
6390                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6391                         mv_f[i].filter_type = f->mac_info.filter_type;
6392                         mv_f[i].vlan_id = 0;
6393                         i++;
6394                 }
6395         } else {
6396                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6397                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6398                                         vsi->vlan_num, &f->mac_info.mac_addr);
6399                         if (ret != I40E_SUCCESS)
6400                                 goto DONE;
6401                         for (j = i; j < i + vsi->vlan_num; j++)
6402                                 mv_f[j].filter_type = f->mac_info.filter_type;
6403                         i += vsi->vlan_num;
6404                 }
6405         }
6406
6407         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6408 DONE:
6409         rte_free(mv_f);
6410
6411         return ret;
6412 }
6413
6414 int
6415 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6416 {
6417         struct i40e_macvlan_filter *mv_f;
6418         int mac_num;
6419         int ret = I40E_SUCCESS;
6420
6421         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6422                 return I40E_ERR_PARAM;
6423
6424         /* If it's already set, just return */
6425         if (i40e_find_vlan_filter(vsi,vlan))
6426                 return I40E_SUCCESS;
6427
6428         mac_num = vsi->mac_num;
6429
6430         if (mac_num == 0) {
6431                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6432                 return I40E_ERR_PARAM;
6433         }
6434
6435         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6436
6437         if (mv_f == NULL) {
6438                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6439                 return I40E_ERR_NO_MEMORY;
6440         }
6441
6442         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6443
6444         if (ret != I40E_SUCCESS)
6445                 goto DONE;
6446
6447         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6448
6449         if (ret != I40E_SUCCESS)
6450                 goto DONE;
6451
6452         i40e_set_vlan_filter(vsi, vlan, 1);
6453
6454         vsi->vlan_num++;
6455         ret = I40E_SUCCESS;
6456 DONE:
6457         rte_free(mv_f);
6458         return ret;
6459 }
6460
6461 int
6462 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6463 {
6464         struct i40e_macvlan_filter *mv_f;
6465         int mac_num;
6466         int ret = I40E_SUCCESS;
6467
6468         /**
6469          * Vlan 0 is the generic filter for untagged packets
6470          * and can't be removed.
6471          */
6472         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6473                 return I40E_ERR_PARAM;
6474
6475         /* If can't find it, just return */
6476         if (!i40e_find_vlan_filter(vsi, vlan))
6477                 return I40E_ERR_PARAM;
6478
6479         mac_num = vsi->mac_num;
6480
6481         if (mac_num == 0) {
6482                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6483                 return I40E_ERR_PARAM;
6484         }
6485
6486         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6487
6488         if (mv_f == NULL) {
6489                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6490                 return I40E_ERR_NO_MEMORY;
6491         }
6492
6493         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6494
6495         if (ret != I40E_SUCCESS)
6496                 goto DONE;
6497
6498         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6499
6500         if (ret != I40E_SUCCESS)
6501                 goto DONE;
6502
6503         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6504         if (vsi->vlan_num == 1) {
6505                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6506                 if (ret != I40E_SUCCESS)
6507                         goto DONE;
6508
6509                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6510                 if (ret != I40E_SUCCESS)
6511                         goto DONE;
6512         }
6513
6514         i40e_set_vlan_filter(vsi, vlan, 0);
6515
6516         vsi->vlan_num--;
6517         ret = I40E_SUCCESS;
6518 DONE:
6519         rte_free(mv_f);
6520         return ret;
6521 }
6522
6523 int
6524 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6525 {
6526         struct i40e_mac_filter *f;
6527         struct i40e_macvlan_filter *mv_f;
6528         int i, vlan_num = 0;
6529         int ret = I40E_SUCCESS;
6530
6531         /* If it's add and we've config it, return */
6532         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6533         if (f != NULL)
6534                 return I40E_SUCCESS;
6535         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6536                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6537
6538                 /**
6539                  * If vlan_num is 0, that's the first time to add mac,
6540                  * set mask for vlan_id 0.
6541                  */
6542                 if (vsi->vlan_num == 0) {
6543                         i40e_set_vlan_filter(vsi, 0, 1);
6544                         vsi->vlan_num = 1;
6545                 }
6546                 vlan_num = vsi->vlan_num;
6547         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6548                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6549                 vlan_num = 1;
6550
6551         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6552         if (mv_f == NULL) {
6553                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6554                 return I40E_ERR_NO_MEMORY;
6555         }
6556
6557         for (i = 0; i < vlan_num; i++) {
6558                 mv_f[i].filter_type = mac_filter->filter_type;
6559                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6560                                 ETH_ADDR_LEN);
6561         }
6562
6563         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6564                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6565                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6566                                         &mac_filter->mac_addr);
6567                 if (ret != I40E_SUCCESS)
6568                         goto DONE;
6569         }
6570
6571         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6572         if (ret != I40E_SUCCESS)
6573                 goto DONE;
6574
6575         /* Add the mac addr into mac list */
6576         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6577         if (f == NULL) {
6578                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6579                 ret = I40E_ERR_NO_MEMORY;
6580                 goto DONE;
6581         }
6582         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6583                         ETH_ADDR_LEN);
6584         f->mac_info.filter_type = mac_filter->filter_type;
6585         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6586         vsi->mac_num++;
6587
6588         ret = I40E_SUCCESS;
6589 DONE:
6590         rte_free(mv_f);
6591
6592         return ret;
6593 }
6594
6595 int
6596 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6597 {
6598         struct i40e_mac_filter *f;
6599         struct i40e_macvlan_filter *mv_f;
6600         int i, vlan_num;
6601         enum rte_mac_filter_type filter_type;
6602         int ret = I40E_SUCCESS;
6603
6604         /* Can't find it, return an error */
6605         f = i40e_find_mac_filter(vsi, addr);
6606         if (f == NULL)
6607                 return I40E_ERR_PARAM;
6608
6609         vlan_num = vsi->vlan_num;
6610         filter_type = f->mac_info.filter_type;
6611         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6612                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6613                 if (vlan_num == 0) {
6614                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6615                         return I40E_ERR_PARAM;
6616                 }
6617         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6618                         filter_type == RTE_MAC_HASH_MATCH)
6619                 vlan_num = 1;
6620
6621         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6622         if (mv_f == NULL) {
6623                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6624                 return I40E_ERR_NO_MEMORY;
6625         }
6626
6627         for (i = 0; i < vlan_num; i++) {
6628                 mv_f[i].filter_type = filter_type;
6629                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6630                                 ETH_ADDR_LEN);
6631         }
6632         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6633                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6634                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6635                 if (ret != I40E_SUCCESS)
6636                         goto DONE;
6637         }
6638
6639         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6640         if (ret != I40E_SUCCESS)
6641                 goto DONE;
6642
6643         /* Remove the mac addr into mac list */
6644         TAILQ_REMOVE(&vsi->mac_list, f, next);
6645         rte_free(f);
6646         vsi->mac_num--;
6647
6648         ret = I40E_SUCCESS;
6649 DONE:
6650         rte_free(mv_f);
6651         return ret;
6652 }
6653
6654 /* Configure hash enable flags for RSS */
6655 uint64_t
6656 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6657 {
6658         uint64_t hena = 0;
6659         int i;
6660
6661         if (!flags)
6662                 return hena;
6663
6664         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6665                 if (flags & (1ULL << i))
6666                         hena |= adapter->pctypes_tbl[i];
6667         }
6668
6669         return hena;
6670 }
6671
6672 /* Parse the hash enable flags */
6673 uint64_t
6674 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6675 {
6676         uint64_t rss_hf = 0;
6677
6678         if (!flags)
6679                 return rss_hf;
6680         int i;
6681
6682         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6683                 if (flags & adapter->pctypes_tbl[i])
6684                         rss_hf |= (1ULL << i);
6685         }
6686         return rss_hf;
6687 }
6688
6689 /* Disable RSS */
6690 static void
6691 i40e_pf_disable_rss(struct i40e_pf *pf)
6692 {
6693         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6694
6695         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6696         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6697         I40E_WRITE_FLUSH(hw);
6698 }
6699
6700 static int
6701 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6702 {
6703         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6704         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6705         int ret = 0;
6706
6707         if (!key || key_len == 0) {
6708                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6709                 return 0;
6710         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6711                 sizeof(uint32_t)) {
6712                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6713                 return -EINVAL;
6714         }
6715
6716         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6717                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6718                         (struct i40e_aqc_get_set_rss_key_data *)key;
6719
6720                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6721                 if (ret)
6722                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6723         } else {
6724                 uint32_t *hash_key = (uint32_t *)key;
6725                 uint16_t i;
6726
6727                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6728                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6729                 I40E_WRITE_FLUSH(hw);
6730         }
6731
6732         return ret;
6733 }
6734
6735 static int
6736 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6737 {
6738         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6739         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6740         int ret;
6741
6742         if (!key || !key_len)
6743                 return -EINVAL;
6744
6745         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6746                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6747                         (struct i40e_aqc_get_set_rss_key_data *)key);
6748                 if (ret) {
6749                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6750                         return ret;
6751                 }
6752         } else {
6753                 uint32_t *key_dw = (uint32_t *)key;
6754                 uint16_t i;
6755
6756                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6757                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6758         }
6759         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6760
6761         return 0;
6762 }
6763
6764 static int
6765 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6766 {
6767         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6768         uint64_t hena;
6769         int ret;
6770
6771         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6772                                rss_conf->rss_key_len);
6773         if (ret)
6774                 return ret;
6775
6776         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6777         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6778         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6779         I40E_WRITE_FLUSH(hw);
6780
6781         return 0;
6782 }
6783
6784 static int
6785 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6786                          struct rte_eth_rss_conf *rss_conf)
6787 {
6788         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6789         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6790         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6791         uint64_t hena;
6792
6793         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6794         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6795
6796         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6797                 if (rss_hf != 0) /* Enable RSS */
6798                         return -EINVAL;
6799                 return 0; /* Nothing to do */
6800         }
6801         /* RSS enabled */
6802         if (rss_hf == 0) /* Disable RSS */
6803                 return -EINVAL;
6804
6805         return i40e_hw_rss_hash_set(pf, rss_conf);
6806 }
6807
6808 static int
6809 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6810                            struct rte_eth_rss_conf *rss_conf)
6811 {
6812         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6813         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6814         uint64_t hena;
6815
6816         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6817                          &rss_conf->rss_key_len);
6818
6819         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6820         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6821         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6822
6823         return 0;
6824 }
6825
6826 static int
6827 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6828 {
6829         switch (filter_type) {
6830         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6831                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6832                 break;
6833         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6834                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6835                 break;
6836         case RTE_TUNNEL_FILTER_IMAC_TENID:
6837                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6838                 break;
6839         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6840                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6841                 break;
6842         case ETH_TUNNEL_FILTER_IMAC:
6843                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6844                 break;
6845         case ETH_TUNNEL_FILTER_OIP:
6846                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6847                 break;
6848         case ETH_TUNNEL_FILTER_IIP:
6849                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6850                 break;
6851         default:
6852                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6853                 return -EINVAL;
6854         }
6855
6856         return 0;
6857 }
6858
6859 /* Convert tunnel filter structure */
6860 static int
6861 i40e_tunnel_filter_convert(
6862         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6863         struct i40e_tunnel_filter *tunnel_filter)
6864 {
6865         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6866                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6867         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6868                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6869         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6870         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6871              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6872             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6873                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6874         else
6875                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6876         tunnel_filter->input.flags = cld_filter->element.flags;
6877         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6878         tunnel_filter->queue = cld_filter->element.queue_number;
6879         rte_memcpy(tunnel_filter->input.general_fields,
6880                    cld_filter->general_fields,
6881                    sizeof(cld_filter->general_fields));
6882
6883         return 0;
6884 }
6885
6886 /* Check if there exists the tunnel filter */
6887 struct i40e_tunnel_filter *
6888 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6889                              const struct i40e_tunnel_filter_input *input)
6890 {
6891         int ret;
6892
6893         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6894         if (ret < 0)
6895                 return NULL;
6896
6897         return tunnel_rule->hash_map[ret];
6898 }
6899
6900 /* Add a tunnel filter into the SW list */
6901 static int
6902 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6903                              struct i40e_tunnel_filter *tunnel_filter)
6904 {
6905         struct i40e_tunnel_rule *rule = &pf->tunnel;
6906         int ret;
6907
6908         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6909         if (ret < 0) {
6910                 PMD_DRV_LOG(ERR,
6911                             "Failed to insert tunnel filter to hash table %d!",
6912                             ret);
6913                 return ret;
6914         }
6915         rule->hash_map[ret] = tunnel_filter;
6916
6917         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6918
6919         return 0;
6920 }
6921
6922 /* Delete a tunnel filter from the SW list */
6923 int
6924 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6925                           struct i40e_tunnel_filter_input *input)
6926 {
6927         struct i40e_tunnel_rule *rule = &pf->tunnel;
6928         struct i40e_tunnel_filter *tunnel_filter;
6929         int ret;
6930
6931         ret = rte_hash_del_key(rule->hash_table, input);
6932         if (ret < 0) {
6933                 PMD_DRV_LOG(ERR,
6934                             "Failed to delete tunnel filter to hash table %d!",
6935                             ret);
6936                 return ret;
6937         }
6938         tunnel_filter = rule->hash_map[ret];
6939         rule->hash_map[ret] = NULL;
6940
6941         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6942         rte_free(tunnel_filter);
6943
6944         return 0;
6945 }
6946
6947 int
6948 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6949                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6950                         uint8_t add)
6951 {
6952         uint16_t ip_type;
6953         uint32_t ipv4_addr;
6954         uint8_t i, tun_type = 0;
6955         /* internal varialbe to convert ipv6 byte order */
6956         uint32_t convert_ipv6[4];
6957         int val, ret = 0;
6958         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6959         struct i40e_vsi *vsi = pf->main_vsi;
6960         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6961         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6962         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6963         struct i40e_tunnel_filter *tunnel, *node;
6964         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6965
6966         cld_filter = rte_zmalloc("tunnel_filter",
6967                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6968         0);
6969
6970         if (NULL == cld_filter) {
6971                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6972                 return -ENOMEM;
6973         }
6974         pfilter = cld_filter;
6975
6976         ether_addr_copy(&tunnel_filter->outer_mac,
6977                         (struct ether_addr *)&pfilter->element.outer_mac);
6978         ether_addr_copy(&tunnel_filter->inner_mac,
6979                         (struct ether_addr *)&pfilter->element.inner_mac);
6980
6981         pfilter->element.inner_vlan =
6982                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6983         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6984                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6985                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6986                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6987                                 &rte_cpu_to_le_32(ipv4_addr),
6988                                 sizeof(pfilter->element.ipaddr.v4.data));
6989         } else {
6990                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6991                 for (i = 0; i < 4; i++) {
6992                         convert_ipv6[i] =
6993                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6994                 }
6995                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6996                            &convert_ipv6,
6997                            sizeof(pfilter->element.ipaddr.v6.data));
6998         }
6999
7000         /* check tunneled type */
7001         switch (tunnel_filter->tunnel_type) {
7002         case RTE_TUNNEL_TYPE_VXLAN:
7003                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7004                 break;
7005         case RTE_TUNNEL_TYPE_NVGRE:
7006                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7007                 break;
7008         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7009                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7010                 break;
7011         default:
7012                 /* Other tunnel types is not supported. */
7013                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7014                 rte_free(cld_filter);
7015                 return -EINVAL;
7016         }
7017
7018         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7019                                        &pfilter->element.flags);
7020         if (val < 0) {
7021                 rte_free(cld_filter);
7022                 return -EINVAL;
7023         }
7024
7025         pfilter->element.flags |= rte_cpu_to_le_16(
7026                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7027                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7028         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7029         pfilter->element.queue_number =
7030                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7031
7032         /* Check if there is the filter in SW list */
7033         memset(&check_filter, 0, sizeof(check_filter));
7034         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7035         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7036         if (add && node) {
7037                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7038                 return -EINVAL;
7039         }
7040
7041         if (!add && !node) {
7042                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7043                 return -EINVAL;
7044         }
7045
7046         if (add) {
7047                 ret = i40e_aq_add_cloud_filters(hw,
7048                                         vsi->seid, &cld_filter->element, 1);
7049                 if (ret < 0) {
7050                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7051                         return -ENOTSUP;
7052                 }
7053                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7054                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7055                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7056         } else {
7057                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7058                                                    &cld_filter->element, 1);
7059                 if (ret < 0) {
7060                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7061                         return -ENOTSUP;
7062                 }
7063                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7064         }
7065
7066         rte_free(cld_filter);
7067         return ret;
7068 }
7069
7070 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7071 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7072 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7073 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7074 #define I40E_TR_GRE_KEY_MASK                    0x400
7075 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7076 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7077
7078 static enum
7079 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7080 {
7081         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7082         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7083         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7084         enum i40e_status_code status = I40E_SUCCESS;
7085
7086         memset(&filter_replace, 0,
7087                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7088         memset(&filter_replace_buf, 0,
7089                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7090
7091         /* create L1 filter */
7092         filter_replace.old_filter_type =
7093                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7094         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7095         filter_replace.tr_bit = 0;
7096
7097         /* Prepare the buffer, 3 entries */
7098         filter_replace_buf.data[0] =
7099                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7100         filter_replace_buf.data[0] |=
7101                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7102         filter_replace_buf.data[2] = 0xFF;
7103         filter_replace_buf.data[3] = 0xFF;
7104         filter_replace_buf.data[4] =
7105                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7106         filter_replace_buf.data[4] |=
7107                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7108         filter_replace_buf.data[7] = 0xF0;
7109         filter_replace_buf.data[8]
7110                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7111         filter_replace_buf.data[8] |=
7112                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7113         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7114                 I40E_TR_GENEVE_KEY_MASK |
7115                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7116         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7117                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7118                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7119
7120         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7121                                                &filter_replace_buf);
7122         return status;
7123 }
7124
7125 static enum
7126 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7127 {
7128         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7129         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7130         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7131         enum i40e_status_code status = I40E_SUCCESS;
7132
7133         /* For MPLSoUDP */
7134         memset(&filter_replace, 0,
7135                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7136         memset(&filter_replace_buf, 0,
7137                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7138         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7139                 I40E_AQC_MIRROR_CLOUD_FILTER;
7140         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7141         filter_replace.new_filter_type =
7142                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7143         /* Prepare the buffer, 2 entries */
7144         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7145         filter_replace_buf.data[0] |=
7146                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7147         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7148         filter_replace_buf.data[4] |=
7149                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7150         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7151                                                &filter_replace_buf);
7152         if (status < 0)
7153                 return status;
7154
7155         /* For MPLSoGRE */
7156         memset(&filter_replace, 0,
7157                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7158         memset(&filter_replace_buf, 0,
7159                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7160
7161         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7162                 I40E_AQC_MIRROR_CLOUD_FILTER;
7163         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7164         filter_replace.new_filter_type =
7165                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7166         /* Prepare the buffer, 2 entries */
7167         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7168         filter_replace_buf.data[0] |=
7169                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7170         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7171         filter_replace_buf.data[4] |=
7172                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7173
7174         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7175                                                &filter_replace_buf);
7176         return status;
7177 }
7178
7179 static enum i40e_status_code
7180 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7181 {
7182         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7183         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7184         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7185         enum i40e_status_code status = I40E_SUCCESS;
7186
7187         /* For GTP-C */
7188         memset(&filter_replace, 0,
7189                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7190         memset(&filter_replace_buf, 0,
7191                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7192         /* create L1 filter */
7193         filter_replace.old_filter_type =
7194                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7195         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7196         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7197                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7198         /* Prepare the buffer, 2 entries */
7199         filter_replace_buf.data[0] =
7200                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7201         filter_replace_buf.data[0] |=
7202                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7203         filter_replace_buf.data[2] = 0xFF;
7204         filter_replace_buf.data[3] = 0xFF;
7205         filter_replace_buf.data[4] =
7206                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7207         filter_replace_buf.data[4] |=
7208                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7209         filter_replace_buf.data[6] = 0xFF;
7210         filter_replace_buf.data[7] = 0xFF;
7211         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7212                                                &filter_replace_buf);
7213         if (status < 0)
7214                 return status;
7215
7216         /* for GTP-U */
7217         memset(&filter_replace, 0,
7218                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7219         memset(&filter_replace_buf, 0,
7220                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7221         /* create L1 filter */
7222         filter_replace.old_filter_type =
7223                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7224         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7225         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7226                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7227         /* Prepare the buffer, 2 entries */
7228         filter_replace_buf.data[0] =
7229                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7230         filter_replace_buf.data[0] |=
7231                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7232         filter_replace_buf.data[2] = 0xFF;
7233         filter_replace_buf.data[3] = 0xFF;
7234         filter_replace_buf.data[4] =
7235                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7236         filter_replace_buf.data[4] |=
7237                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7238         filter_replace_buf.data[6] = 0xFF;
7239         filter_replace_buf.data[7] = 0xFF;
7240
7241         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7242                                                &filter_replace_buf);
7243         return status;
7244 }
7245
7246 static enum
7247 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7248 {
7249         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7250         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7251         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7252         enum i40e_status_code status = I40E_SUCCESS;
7253
7254         /* for GTP-C */
7255         memset(&filter_replace, 0,
7256                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7257         memset(&filter_replace_buf, 0,
7258                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7259         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7260         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7261         filter_replace.new_filter_type =
7262                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7263         /* Prepare the buffer, 2 entries */
7264         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7265         filter_replace_buf.data[0] |=
7266                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7267         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7268         filter_replace_buf.data[4] |=
7269                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7270         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7271                                                &filter_replace_buf);
7272         if (status < 0)
7273                 return status;
7274
7275         /* for GTP-U */
7276         memset(&filter_replace, 0,
7277                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7278         memset(&filter_replace_buf, 0,
7279                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7280         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7281         filter_replace.old_filter_type =
7282                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7283         filter_replace.new_filter_type =
7284                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7285         /* Prepare the buffer, 2 entries */
7286         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7287         filter_replace_buf.data[0] |=
7288                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7289         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7290         filter_replace_buf.data[4] |=
7291                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7292
7293         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7294                                                &filter_replace_buf);
7295         return status;
7296 }
7297
7298 int
7299 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7300                       struct i40e_tunnel_filter_conf *tunnel_filter,
7301                       uint8_t add)
7302 {
7303         uint16_t ip_type;
7304         uint32_t ipv4_addr;
7305         uint8_t i, tun_type = 0;
7306         /* internal variable to convert ipv6 byte order */
7307         uint32_t convert_ipv6[4];
7308         int val, ret = 0;
7309         struct i40e_pf_vf *vf = NULL;
7310         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7311         struct i40e_vsi *vsi;
7312         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7313         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7314         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7315         struct i40e_tunnel_filter *tunnel, *node;
7316         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7317         uint32_t teid_le;
7318         bool big_buffer = 0;
7319
7320         cld_filter = rte_zmalloc("tunnel_filter",
7321                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7322                          0);
7323
7324         if (cld_filter == NULL) {
7325                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7326                 return -ENOMEM;
7327         }
7328         pfilter = cld_filter;
7329
7330         ether_addr_copy(&tunnel_filter->outer_mac,
7331                         (struct ether_addr *)&pfilter->element.outer_mac);
7332         ether_addr_copy(&tunnel_filter->inner_mac,
7333                         (struct ether_addr *)&pfilter->element.inner_mac);
7334
7335         pfilter->element.inner_vlan =
7336                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7337         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7338                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7339                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7340                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7341                                 &rte_cpu_to_le_32(ipv4_addr),
7342                                 sizeof(pfilter->element.ipaddr.v4.data));
7343         } else {
7344                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7345                 for (i = 0; i < 4; i++) {
7346                         convert_ipv6[i] =
7347                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7348                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7349                 }
7350                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7351                            &convert_ipv6,
7352                            sizeof(pfilter->element.ipaddr.v6.data));
7353         }
7354
7355         /* check tunneled type */
7356         switch (tunnel_filter->tunnel_type) {
7357         case I40E_TUNNEL_TYPE_VXLAN:
7358                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7359                 break;
7360         case I40E_TUNNEL_TYPE_NVGRE:
7361                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7362                 break;
7363         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7364                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7365                 break;
7366         case I40E_TUNNEL_TYPE_MPLSoUDP:
7367                 if (!pf->mpls_replace_flag) {
7368                         i40e_replace_mpls_l1_filter(pf);
7369                         i40e_replace_mpls_cloud_filter(pf);
7370                         pf->mpls_replace_flag = 1;
7371                 }
7372                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7373                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7374                         teid_le >> 4;
7375                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7376                         (teid_le & 0xF) << 12;
7377                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7378                         0x40;
7379                 big_buffer = 1;
7380                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7381                 break;
7382         case I40E_TUNNEL_TYPE_MPLSoGRE:
7383                 if (!pf->mpls_replace_flag) {
7384                         i40e_replace_mpls_l1_filter(pf);
7385                         i40e_replace_mpls_cloud_filter(pf);
7386                         pf->mpls_replace_flag = 1;
7387                 }
7388                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7389                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7390                         teid_le >> 4;
7391                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7392                         (teid_le & 0xF) << 12;
7393                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7394                         0x0;
7395                 big_buffer = 1;
7396                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7397                 break;
7398         case I40E_TUNNEL_TYPE_GTPC:
7399                 if (!pf->gtp_replace_flag) {
7400                         i40e_replace_gtp_l1_filter(pf);
7401                         i40e_replace_gtp_cloud_filter(pf);
7402                         pf->gtp_replace_flag = 1;
7403                 }
7404                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7405                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7406                         (teid_le >> 16) & 0xFFFF;
7407                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7408                         teid_le & 0xFFFF;
7409                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7410                         0x0;
7411                 big_buffer = 1;
7412                 break;
7413         case I40E_TUNNEL_TYPE_GTPU:
7414                 if (!pf->gtp_replace_flag) {
7415                         i40e_replace_gtp_l1_filter(pf);
7416                         i40e_replace_gtp_cloud_filter(pf);
7417                         pf->gtp_replace_flag = 1;
7418                 }
7419                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7420                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7421                         (teid_le >> 16) & 0xFFFF;
7422                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7423                         teid_le & 0xFFFF;
7424                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7425                         0x0;
7426                 big_buffer = 1;
7427                 break;
7428         case I40E_TUNNEL_TYPE_QINQ:
7429                 if (!pf->qinq_replace_flag) {
7430                         ret = i40e_cloud_filter_qinq_create(pf);
7431                         if (ret < 0)
7432                                 PMD_DRV_LOG(DEBUG,
7433                                             "QinQ tunnel filter already created.");
7434                         pf->qinq_replace_flag = 1;
7435                 }
7436                 /*      Add in the General fields the values of
7437                  *      the Outer and Inner VLAN
7438                  *      Big Buffer should be set, see changes in
7439                  *      i40e_aq_add_cloud_filters
7440                  */
7441                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7442                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7443                 big_buffer = 1;
7444                 break;
7445         default:
7446                 /* Other tunnel types is not supported. */
7447                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7448                 rte_free(cld_filter);
7449                 return -EINVAL;
7450         }
7451
7452         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7453                 pfilter->element.flags =
7454                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7455         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7456                 pfilter->element.flags =
7457                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7458         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7459                 pfilter->element.flags =
7460                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7461         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7462                 pfilter->element.flags =
7463                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7464         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7465                 pfilter->element.flags |=
7466                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7467         else {
7468                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7469                                                 &pfilter->element.flags);
7470                 if (val < 0) {
7471                         rte_free(cld_filter);
7472                         return -EINVAL;
7473                 }
7474         }
7475
7476         pfilter->element.flags |= rte_cpu_to_le_16(
7477                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7478                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7479         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7480         pfilter->element.queue_number =
7481                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7482
7483         if (!tunnel_filter->is_to_vf)
7484                 vsi = pf->main_vsi;
7485         else {
7486                 if (tunnel_filter->vf_id >= pf->vf_num) {
7487                         PMD_DRV_LOG(ERR, "Invalid argument.");
7488                         return -EINVAL;
7489                 }
7490                 vf = &pf->vfs[tunnel_filter->vf_id];
7491                 vsi = vf->vsi;
7492         }
7493
7494         /* Check if there is the filter in SW list */
7495         memset(&check_filter, 0, sizeof(check_filter));
7496         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7497         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7498         check_filter.vf_id = tunnel_filter->vf_id;
7499         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7500         if (add && node) {
7501                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7502                 return -EINVAL;
7503         }
7504
7505         if (!add && !node) {
7506                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7507                 return -EINVAL;
7508         }
7509
7510         if (add) {
7511                 if (big_buffer)
7512                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7513                                                    vsi->seid, cld_filter, 1);
7514                 else
7515                         ret = i40e_aq_add_cloud_filters(hw,
7516                                         vsi->seid, &cld_filter->element, 1);
7517                 if (ret < 0) {
7518                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7519                         return -ENOTSUP;
7520                 }
7521                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7522                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7523                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7524         } else {
7525                 if (big_buffer)
7526                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7527                                 hw, vsi->seid, cld_filter, 1);
7528                 else
7529                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7530                                                    &cld_filter->element, 1);
7531                 if (ret < 0) {
7532                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7533                         return -ENOTSUP;
7534                 }
7535                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7536         }
7537
7538         rte_free(cld_filter);
7539         return ret;
7540 }
7541
7542 static int
7543 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7544 {
7545         uint8_t i;
7546
7547         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7548                 if (pf->vxlan_ports[i] == port)
7549                         return i;
7550         }
7551
7552         return -1;
7553 }
7554
7555 static int
7556 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7557 {
7558         int  idx, ret;
7559         uint8_t filter_idx;
7560         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7561
7562         idx = i40e_get_vxlan_port_idx(pf, port);
7563
7564         /* Check if port already exists */
7565         if (idx >= 0) {
7566                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7567                 return -EINVAL;
7568         }
7569
7570         /* Now check if there is space to add the new port */
7571         idx = i40e_get_vxlan_port_idx(pf, 0);
7572         if (idx < 0) {
7573                 PMD_DRV_LOG(ERR,
7574                         "Maximum number of UDP ports reached, not adding port %d",
7575                         port);
7576                 return -ENOSPC;
7577         }
7578
7579         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7580                                         &filter_idx, NULL);
7581         if (ret < 0) {
7582                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7583                 return -1;
7584         }
7585
7586         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7587                          port,  filter_idx);
7588
7589         /* New port: add it and mark its index in the bitmap */
7590         pf->vxlan_ports[idx] = port;
7591         pf->vxlan_bitmap |= (1 << idx);
7592
7593         if (!(pf->flags & I40E_FLAG_VXLAN))
7594                 pf->flags |= I40E_FLAG_VXLAN;
7595
7596         return 0;
7597 }
7598
7599 static int
7600 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7601 {
7602         int idx;
7603         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7604
7605         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7606                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7607                 return -EINVAL;
7608         }
7609
7610         idx = i40e_get_vxlan_port_idx(pf, port);
7611
7612         if (idx < 0) {
7613                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7614                 return -EINVAL;
7615         }
7616
7617         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7618                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7619                 return -1;
7620         }
7621
7622         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7623                         port, idx);
7624
7625         pf->vxlan_ports[idx] = 0;
7626         pf->vxlan_bitmap &= ~(1 << idx);
7627
7628         if (!pf->vxlan_bitmap)
7629                 pf->flags &= ~I40E_FLAG_VXLAN;
7630
7631         return 0;
7632 }
7633
7634 /* Add UDP tunneling port */
7635 static int
7636 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7637                              struct rte_eth_udp_tunnel *udp_tunnel)
7638 {
7639         int ret = 0;
7640         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7641
7642         if (udp_tunnel == NULL)
7643                 return -EINVAL;
7644
7645         switch (udp_tunnel->prot_type) {
7646         case RTE_TUNNEL_TYPE_VXLAN:
7647                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7648                 break;
7649
7650         case RTE_TUNNEL_TYPE_GENEVE:
7651         case RTE_TUNNEL_TYPE_TEREDO:
7652                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7653                 ret = -1;
7654                 break;
7655
7656         default:
7657                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7658                 ret = -1;
7659                 break;
7660         }
7661
7662         return ret;
7663 }
7664
7665 /* Remove UDP tunneling port */
7666 static int
7667 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7668                              struct rte_eth_udp_tunnel *udp_tunnel)
7669 {
7670         int ret = 0;
7671         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7672
7673         if (udp_tunnel == NULL)
7674                 return -EINVAL;
7675
7676         switch (udp_tunnel->prot_type) {
7677         case RTE_TUNNEL_TYPE_VXLAN:
7678                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7679                 break;
7680         case RTE_TUNNEL_TYPE_GENEVE:
7681         case RTE_TUNNEL_TYPE_TEREDO:
7682                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7683                 ret = -1;
7684                 break;
7685         default:
7686                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7687                 ret = -1;
7688                 break;
7689         }
7690
7691         return ret;
7692 }
7693
7694 /* Calculate the maximum number of contiguous PF queues that are configured */
7695 static int
7696 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7697 {
7698         struct rte_eth_dev_data *data = pf->dev_data;
7699         int i, num;
7700         struct i40e_rx_queue *rxq;
7701
7702         num = 0;
7703         for (i = 0; i < pf->lan_nb_qps; i++) {
7704                 rxq = data->rx_queues[i];
7705                 if (rxq && rxq->q_set)
7706                         num++;
7707                 else
7708                         break;
7709         }
7710
7711         return num;
7712 }
7713
7714 /* Configure RSS */
7715 static int
7716 i40e_pf_config_rss(struct i40e_pf *pf)
7717 {
7718         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7719         struct rte_eth_rss_conf rss_conf;
7720         uint32_t i, lut = 0;
7721         uint16_t j, num;
7722
7723         /*
7724          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7725          * It's necessary to calculate the actual PF queues that are configured.
7726          */
7727         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7728                 num = i40e_pf_calc_configured_queues_num(pf);
7729         else
7730                 num = pf->dev_data->nb_rx_queues;
7731
7732         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7733         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7734                         num);
7735
7736         if (num == 0) {
7737                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7738                 return -ENOTSUP;
7739         }
7740
7741         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7742                 if (j == num)
7743                         j = 0;
7744                 lut = (lut << 8) | (j & ((0x1 <<
7745                         hw->func_caps.rss_table_entry_width) - 1));
7746                 if ((i & 3) == 3)
7747                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7748         }
7749
7750         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7751         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7752                 i40e_pf_disable_rss(pf);
7753                 return 0;
7754         }
7755         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7756                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7757                 /* Random default keys */
7758                 static uint32_t rss_key_default[] = {0x6b793944,
7759                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7760                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7761                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7762
7763                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7764                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7765                                                         sizeof(uint32_t);
7766         }
7767
7768         return i40e_hw_rss_hash_set(pf, &rss_conf);
7769 }
7770
7771 static int
7772 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7773                                struct rte_eth_tunnel_filter_conf *filter)
7774 {
7775         if (pf == NULL || filter == NULL) {
7776                 PMD_DRV_LOG(ERR, "Invalid parameter");
7777                 return -EINVAL;
7778         }
7779
7780         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7781                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7782                 return -EINVAL;
7783         }
7784
7785         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7786                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7787                 return -EINVAL;
7788         }
7789
7790         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7791                 (is_zero_ether_addr(&filter->outer_mac))) {
7792                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7793                 return -EINVAL;
7794         }
7795
7796         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7797                 (is_zero_ether_addr(&filter->inner_mac))) {
7798                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7799                 return -EINVAL;
7800         }
7801
7802         return 0;
7803 }
7804
7805 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7806 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7807 static int
7808 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7809 {
7810         uint32_t val, reg;
7811         int ret = -EINVAL;
7812
7813         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7814         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7815
7816         if (len == 3) {
7817                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7818         } else if (len == 4) {
7819                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7820         } else {
7821                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7822                 return ret;
7823         }
7824
7825         if (reg != val) {
7826                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7827                                                    reg, NULL);
7828                 if (ret != 0)
7829                         return ret;
7830         } else {
7831                 ret = 0;
7832         }
7833         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7834                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7835
7836         return ret;
7837 }
7838
7839 static int
7840 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7841 {
7842         int ret = -EINVAL;
7843
7844         if (!hw || !cfg)
7845                 return -EINVAL;
7846
7847         switch (cfg->cfg_type) {
7848         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7849                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7850                 break;
7851         default:
7852                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7853                 break;
7854         }
7855
7856         return ret;
7857 }
7858
7859 static int
7860 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7861                                enum rte_filter_op filter_op,
7862                                void *arg)
7863 {
7864         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7865         int ret = I40E_ERR_PARAM;
7866
7867         switch (filter_op) {
7868         case RTE_ETH_FILTER_SET:
7869                 ret = i40e_dev_global_config_set(hw,
7870                         (struct rte_eth_global_cfg *)arg);
7871                 break;
7872         default:
7873                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7874                 break;
7875         }
7876
7877         return ret;
7878 }
7879
7880 static int
7881 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7882                           enum rte_filter_op filter_op,
7883                           void *arg)
7884 {
7885         struct rte_eth_tunnel_filter_conf *filter;
7886         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7887         int ret = I40E_SUCCESS;
7888
7889         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7890
7891         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7892                 return I40E_ERR_PARAM;
7893
7894         switch (filter_op) {
7895         case RTE_ETH_FILTER_NOP:
7896                 if (!(pf->flags & I40E_FLAG_VXLAN))
7897                         ret = I40E_NOT_SUPPORTED;
7898                 break;
7899         case RTE_ETH_FILTER_ADD:
7900                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7901                 break;
7902         case RTE_ETH_FILTER_DELETE:
7903                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7904                 break;
7905         default:
7906                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7907                 ret = I40E_ERR_PARAM;
7908                 break;
7909         }
7910
7911         return ret;
7912 }
7913
7914 static int
7915 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7916 {
7917         int ret = 0;
7918         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7919
7920         /* RSS setup */
7921         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7922                 ret = i40e_pf_config_rss(pf);
7923         else
7924                 i40e_pf_disable_rss(pf);
7925
7926         return ret;
7927 }
7928
7929 /* Get the symmetric hash enable configurations per port */
7930 static void
7931 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7932 {
7933         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7934
7935         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7936 }
7937
7938 /* Set the symmetric hash enable configurations per port */
7939 static void
7940 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7941 {
7942         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7943
7944         if (enable > 0) {
7945                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7946                         PMD_DRV_LOG(INFO,
7947                                 "Symmetric hash has already been enabled");
7948                         return;
7949                 }
7950                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7951         } else {
7952                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7953                         PMD_DRV_LOG(INFO,
7954                                 "Symmetric hash has already been disabled");
7955                         return;
7956                 }
7957                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7958         }
7959         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7960         I40E_WRITE_FLUSH(hw);
7961 }
7962
7963 /*
7964  * Get global configurations of hash function type and symmetric hash enable
7965  * per flow type (pctype). Note that global configuration means it affects all
7966  * the ports on the same NIC.
7967  */
7968 static int
7969 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7970                                    struct rte_eth_hash_global_conf *g_cfg)
7971 {
7972         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
7973         uint32_t reg;
7974         uint16_t i, j;
7975
7976         memset(g_cfg, 0, sizeof(*g_cfg));
7977         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7978         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7979                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7980         else
7981                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7982         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7983                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7984
7985         /*
7986          * We work only with lowest 32 bits which is not correct, but to work
7987          * properly the valid_bit_mask size should be increased up to 64 bits
7988          * and this will brake ABI. This modification will be done in next
7989          * release
7990          */
7991         g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
7992
7993         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
7994                 if (!adapter->pctypes_tbl[i])
7995                         continue;
7996                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
7997                      j < I40E_FILTER_PCTYPE_MAX; j++) {
7998                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
7999                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8000                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8001                                         g_cfg->sym_hash_enable_mask[0] |=
8002                                                                 (1UL << i);
8003                                 }
8004                         }
8005                 }
8006         }
8007
8008         return 0;
8009 }
8010
8011 static int
8012 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8013                               const struct rte_eth_hash_global_conf *g_cfg)
8014 {
8015         uint32_t i;
8016         uint32_t mask0, i40e_mask = adapter->flow_types_mask;
8017
8018         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8019                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8020                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8021                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8022                                                 g_cfg->hash_func);
8023                 return -EINVAL;
8024         }
8025
8026         /*
8027          * As i40e supports less than 32 flow types, only first 32 bits need to
8028          * be checked.
8029          */
8030         mask0 = g_cfg->valid_bit_mask[0];
8031         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8032                 if (i == 0) {
8033                         /* Check if any unsupported flow type configured */
8034                         if ((mask0 | i40e_mask) ^ i40e_mask)
8035                                 goto mask_err;
8036                 } else {
8037                         if (g_cfg->valid_bit_mask[i])
8038                                 goto mask_err;
8039                 }
8040         }
8041
8042         return 0;
8043
8044 mask_err:
8045         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8046
8047         return -EINVAL;
8048 }
8049
8050 /*
8051  * Set global configurations of hash function type and symmetric hash enable
8052  * per flow type (pctype). Note any modifying global configuration will affect
8053  * all the ports on the same NIC.
8054  */
8055 static int
8056 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8057                                    struct rte_eth_hash_global_conf *g_cfg)
8058 {
8059         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8060         int ret;
8061         uint16_t i, j;
8062         uint32_t reg;
8063         /*
8064          * We work only with lowest 32 bits which is not correct, but to work
8065          * properly the valid_bit_mask size should be increased up to 64 bits
8066          * and this will brake ABI. This modification will be done in next
8067          * release
8068          */
8069         uint32_t mask0 = g_cfg->valid_bit_mask[0] &
8070                                         (uint32_t)adapter->flow_types_mask;
8071
8072         /* Check the input parameters */
8073         ret = i40e_hash_global_config_check(adapter, g_cfg);
8074         if (ret < 0)
8075                 return ret;
8076
8077         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
8078                 if (mask0 & (1UL << i)) {
8079                         reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
8080                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8081
8082                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8083                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8084                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8085                                         i40e_write_rx_ctl(hw,
8086                                                           I40E_GLQF_HSYM(j),
8087                                                           reg);
8088                         }
8089                 }
8090         }
8091
8092         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8093         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8094                 /* Toeplitz */
8095                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8096                         PMD_DRV_LOG(DEBUG,
8097                                 "Hash function already set to Toeplitz");
8098                         goto out;
8099                 }
8100                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8101         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8102                 /* Simple XOR */
8103                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8104                         PMD_DRV_LOG(DEBUG,
8105                                 "Hash function already set to Simple XOR");
8106                         goto out;
8107                 }
8108                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8109         } else
8110                 /* Use the default, and keep it as it is */
8111                 goto out;
8112
8113         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8114
8115 out:
8116         I40E_WRITE_FLUSH(hw);
8117
8118         return 0;
8119 }
8120
8121 /**
8122  * Valid input sets for hash and flow director filters per PCTYPE
8123  */
8124 static uint64_t
8125 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8126                 enum rte_filter_type filter)
8127 {
8128         uint64_t valid;
8129
8130         static const uint64_t valid_hash_inset_table[] = {
8131                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8132                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8133                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8134                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8135                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8136                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8137                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8138                         I40E_INSET_FLEX_PAYLOAD,
8139                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8140                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8141                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8142                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8143                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8144                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8145                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8146                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8147                         I40E_INSET_FLEX_PAYLOAD,
8148                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8149                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8150                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8151                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8152                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8153                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8154                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8155                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8156                         I40E_INSET_FLEX_PAYLOAD,
8157                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8158                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8159                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8160                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8161                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8162                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8163                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8164                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8165                         I40E_INSET_FLEX_PAYLOAD,
8166                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8167                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8168                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8169                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8170                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8171                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8172                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8173                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8174                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8175                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8176                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8177                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8178                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8179                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8180                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8181                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8182                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8183                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8184                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8185                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8186                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8187                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8188                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8189                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8190                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8191                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8192                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8193                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8194                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8195                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8196                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8197                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8198                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8199                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8200                         I40E_INSET_FLEX_PAYLOAD,
8201                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8202                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8203                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8204                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8205                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8206                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8207                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8208                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8209                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8210                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8211                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8212                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8213                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8214                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8215                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8216                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8217                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8218                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8219                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8220                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8221                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8222                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8223                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8224                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8225                         I40E_INSET_FLEX_PAYLOAD,
8226                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8227                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8228                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8229                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8230                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8231                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8232                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8233                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8234                         I40E_INSET_FLEX_PAYLOAD,
8235                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8236                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8237                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8238                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8239                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8240                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8241                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8242                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8243                         I40E_INSET_FLEX_PAYLOAD,
8244                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8245                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8246                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8247                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8248                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8249                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8250                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8251                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8252                         I40E_INSET_FLEX_PAYLOAD,
8253                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8254                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8255                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8256                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8257                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8258                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8259                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8260                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8261                         I40E_INSET_FLEX_PAYLOAD,
8262                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8263                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8264                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8265                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8266                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8267                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8268                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8269                         I40E_INSET_FLEX_PAYLOAD,
8270                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8271                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8272                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8273                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8274                         I40E_INSET_FLEX_PAYLOAD,
8275         };
8276
8277         /**
8278          * Flow director supports only fields defined in
8279          * union rte_eth_fdir_flow.
8280          */
8281         static const uint64_t valid_fdir_inset_table[] = {
8282                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8283                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8284                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8285                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8286                 I40E_INSET_IPV4_TTL,
8287                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8288                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8289                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8290                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8291                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8292                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8293                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8294                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8295                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8296                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8297                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8298                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8299                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8300                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8301                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8302                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8303                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8304                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8305                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8306                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8307                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8308                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8309                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8310                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8311                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8312                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8313                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8314                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8315                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8316                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8317                 I40E_INSET_SCTP_VT,
8318                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8319                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8320                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8321                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8322                 I40E_INSET_IPV4_TTL,
8323                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8324                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8325                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8326                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8327                 I40E_INSET_IPV6_HOP_LIMIT,
8328                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8329                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8330                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8331                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8332                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8333                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8334                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8335                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8336                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8337                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8338                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8339                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8340                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8341                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8342                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8343                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8344                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8345                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8346                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8347                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8348                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8349                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8350                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8351                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8352                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8353                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8354                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8355                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8356                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8357                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8358                 I40E_INSET_SCTP_VT,
8359                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8360                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8361                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8362                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8363                 I40E_INSET_IPV6_HOP_LIMIT,
8364                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8365                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8366                 I40E_INSET_LAST_ETHER_TYPE,
8367         };
8368
8369         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8370                 return 0;
8371         if (filter == RTE_ETH_FILTER_HASH)
8372                 valid = valid_hash_inset_table[pctype];
8373         else
8374                 valid = valid_fdir_inset_table[pctype];
8375
8376         return valid;
8377 }
8378
8379 /**
8380  * Validate if the input set is allowed for a specific PCTYPE
8381  */
8382 int
8383 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8384                 enum rte_filter_type filter, uint64_t inset)
8385 {
8386         uint64_t valid;
8387
8388         valid = i40e_get_valid_input_set(pctype, filter);
8389         if (inset & (~valid))
8390                 return -EINVAL;
8391
8392         return 0;
8393 }
8394
8395 /* default input set fields combination per pctype */
8396 uint64_t
8397 i40e_get_default_input_set(uint16_t pctype)
8398 {
8399         static const uint64_t default_inset_table[] = {
8400                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8401                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8402                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8403                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8404                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8405                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8406                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8407                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8408                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8409                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8410                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8411                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8412                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8413                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8414                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8415                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8416                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8417                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8418                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8419                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8420                         I40E_INSET_SCTP_VT,
8421                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8422                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8423                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8424                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8425                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8426                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8427                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8428                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8429                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8430                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8431                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8432                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8433                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8434                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8435                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8436                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8437                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8438                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8439                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8440                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8441                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8442                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8443                         I40E_INSET_SCTP_VT,
8444                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8445                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8446                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8447                         I40E_INSET_LAST_ETHER_TYPE,
8448         };
8449
8450         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8451                 return 0;
8452
8453         return default_inset_table[pctype];
8454 }
8455
8456 /**
8457  * Parse the input set from index to logical bit masks
8458  */
8459 static int
8460 i40e_parse_input_set(uint64_t *inset,
8461                      enum i40e_filter_pctype pctype,
8462                      enum rte_eth_input_set_field *field,
8463                      uint16_t size)
8464 {
8465         uint16_t i, j;
8466         int ret = -EINVAL;
8467
8468         static const struct {
8469                 enum rte_eth_input_set_field field;
8470                 uint64_t inset;
8471         } inset_convert_table[] = {
8472                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8473                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8474                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8475                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8476                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8477                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8478                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8479                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8480                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8481                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8482                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8483                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8484                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8485                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8486                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8487                         I40E_INSET_IPV6_NEXT_HDR},
8488                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8489                         I40E_INSET_IPV6_HOP_LIMIT},
8490                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8491                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8492                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8493                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8494                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8495                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8496                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8497                         I40E_INSET_SCTP_VT},
8498                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8499                         I40E_INSET_TUNNEL_DMAC},
8500                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8501                         I40E_INSET_VLAN_TUNNEL},
8502                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8503                         I40E_INSET_TUNNEL_ID},
8504                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8505                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8506                         I40E_INSET_FLEX_PAYLOAD_W1},
8507                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8508                         I40E_INSET_FLEX_PAYLOAD_W2},
8509                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8510                         I40E_INSET_FLEX_PAYLOAD_W3},
8511                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8512                         I40E_INSET_FLEX_PAYLOAD_W4},
8513                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8514                         I40E_INSET_FLEX_PAYLOAD_W5},
8515                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8516                         I40E_INSET_FLEX_PAYLOAD_W6},
8517                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8518                         I40E_INSET_FLEX_PAYLOAD_W7},
8519                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8520                         I40E_INSET_FLEX_PAYLOAD_W8},
8521         };
8522
8523         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8524                 return ret;
8525
8526         /* Only one item allowed for default or all */
8527         if (size == 1) {
8528                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8529                         *inset = i40e_get_default_input_set(pctype);
8530                         return 0;
8531                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8532                         *inset = I40E_INSET_NONE;
8533                         return 0;
8534                 }
8535         }
8536
8537         for (i = 0, *inset = 0; i < size; i++) {
8538                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8539                         if (field[i] == inset_convert_table[j].field) {
8540                                 *inset |= inset_convert_table[j].inset;
8541                                 break;
8542                         }
8543                 }
8544
8545                 /* It contains unsupported input set, return immediately */
8546                 if (j == RTE_DIM(inset_convert_table))
8547                         return ret;
8548         }
8549
8550         return 0;
8551 }
8552
8553 /**
8554  * Translate the input set from bit masks to register aware bit masks
8555  * and vice versa
8556  */
8557 uint64_t
8558 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8559 {
8560         uint64_t val = 0;
8561         uint16_t i;
8562
8563         struct inset_map {
8564                 uint64_t inset;
8565                 uint64_t inset_reg;
8566         };
8567
8568         static const struct inset_map inset_map_common[] = {
8569                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8570                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8571                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8572                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8573                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8574                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8575                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8576                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8577                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8578                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8579                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8580                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8581                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8582                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8583                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8584                 {I40E_INSET_TUNNEL_DMAC,
8585                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8586                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8587                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8588                 {I40E_INSET_TUNNEL_SRC_PORT,
8589                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8590                 {I40E_INSET_TUNNEL_DST_PORT,
8591                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8592                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8593                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8594                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8595                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8596                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8597                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8598                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8599                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8600                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8601         };
8602
8603     /* some different registers map in x722*/
8604         static const struct inset_map inset_map_diff_x722[] = {
8605                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8606                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8607                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8608                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8609         };
8610
8611         static const struct inset_map inset_map_diff_not_x722[] = {
8612                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8613                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8614                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8615                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8616         };
8617
8618         if (input == 0)
8619                 return val;
8620
8621         /* Translate input set to register aware inset */
8622         if (type == I40E_MAC_X722) {
8623                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8624                         if (input & inset_map_diff_x722[i].inset)
8625                                 val |= inset_map_diff_x722[i].inset_reg;
8626                 }
8627         } else {
8628                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8629                         if (input & inset_map_diff_not_x722[i].inset)
8630                                 val |= inset_map_diff_not_x722[i].inset_reg;
8631                 }
8632         }
8633
8634         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8635                 if (input & inset_map_common[i].inset)
8636                         val |= inset_map_common[i].inset_reg;
8637         }
8638
8639         return val;
8640 }
8641
8642 int
8643 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8644 {
8645         uint8_t i, idx = 0;
8646         uint64_t inset_need_mask = inset;
8647
8648         static const struct {
8649                 uint64_t inset;
8650                 uint32_t mask;
8651         } inset_mask_map[] = {
8652                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8653                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8654                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8655                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8656                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8657                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8658                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8659                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8660         };
8661
8662         if (!inset || !mask || !nb_elem)
8663                 return 0;
8664
8665         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8666                 /* Clear the inset bit, if no MASK is required,
8667                  * for example proto + ttl
8668                  */
8669                 if ((inset & inset_mask_map[i].inset) ==
8670                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8671                         inset_need_mask &= ~inset_mask_map[i].inset;
8672                 if (!inset_need_mask)
8673                         return 0;
8674         }
8675         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8676                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8677                     inset_mask_map[i].inset) {
8678                         if (idx >= nb_elem) {
8679                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8680                                 return -EINVAL;
8681                         }
8682                         mask[idx] = inset_mask_map[i].mask;
8683                         idx++;
8684                 }
8685         }
8686
8687         return idx;
8688 }
8689
8690 void
8691 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8692 {
8693         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8694
8695         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8696         if (reg != val)
8697                 i40e_write_rx_ctl(hw, addr, val);
8698         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8699                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8700 }
8701
8702 static void
8703 i40e_filter_input_set_init(struct i40e_pf *pf)
8704 {
8705         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8706         enum i40e_filter_pctype pctype;
8707         uint64_t input_set, inset_reg;
8708         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8709         int num, i;
8710         uint16_t flow_type;
8711
8712         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8713              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8714                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8715
8716                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8717                         continue;
8718
8719                 input_set = i40e_get_default_input_set(pctype);
8720
8721                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8722                                                    I40E_INSET_MASK_NUM_REG);
8723                 if (num < 0)
8724                         return;
8725                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8726                                         input_set);
8727
8728                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8729                                       (uint32_t)(inset_reg & UINT32_MAX));
8730                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8731                                      (uint32_t)((inset_reg >>
8732                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8733                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8734                                       (uint32_t)(inset_reg & UINT32_MAX));
8735                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8736                                      (uint32_t)((inset_reg >>
8737                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8738
8739                 for (i = 0; i < num; i++) {
8740                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8741                                              mask_reg[i]);
8742                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8743                                              mask_reg[i]);
8744                 }
8745                 /*clear unused mask registers of the pctype */
8746                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8747                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8748                                              0);
8749                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8750                                              0);
8751                 }
8752                 I40E_WRITE_FLUSH(hw);
8753
8754                 /* store the default input set */
8755                 pf->hash_input_set[pctype] = input_set;
8756                 pf->fdir.input_set[pctype] = input_set;
8757         }
8758 }
8759
8760 int
8761 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8762                          struct rte_eth_input_set_conf *conf)
8763 {
8764         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8765         enum i40e_filter_pctype pctype;
8766         uint64_t input_set, inset_reg = 0;
8767         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8768         int ret, i, num;
8769
8770         if (!conf) {
8771                 PMD_DRV_LOG(ERR, "Invalid pointer");
8772                 return -EFAULT;
8773         }
8774         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8775             conf->op != RTE_ETH_INPUT_SET_ADD) {
8776                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8777                 return -EINVAL;
8778         }
8779
8780         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8781         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8782                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8783                 return -EINVAL;
8784         }
8785
8786         if (hw->mac.type == I40E_MAC_X722) {
8787                 /* get translated pctype value in fd pctype register */
8788                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8789                         I40E_GLQF_FD_PCTYPES((int)pctype));
8790         }
8791
8792         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8793                                    conf->inset_size);
8794         if (ret) {
8795                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8796                 return -EINVAL;
8797         }
8798
8799         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8800                 /* get inset value in register */
8801                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8802                 inset_reg <<= I40E_32_BIT_WIDTH;
8803                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8804                 input_set |= pf->hash_input_set[pctype];
8805         }
8806         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8807                                            I40E_INSET_MASK_NUM_REG);
8808         if (num < 0)
8809                 return -EINVAL;
8810
8811         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8812
8813         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8814                               (uint32_t)(inset_reg & UINT32_MAX));
8815         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8816                              (uint32_t)((inset_reg >>
8817                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8818
8819         for (i = 0; i < num; i++)
8820                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8821                                      mask_reg[i]);
8822         /*clear unused mask registers of the pctype */
8823         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8824                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8825                                      0);
8826         I40E_WRITE_FLUSH(hw);
8827
8828         pf->hash_input_set[pctype] = input_set;
8829         return 0;
8830 }
8831
8832 int
8833 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8834                          struct rte_eth_input_set_conf *conf)
8835 {
8836         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8837         enum i40e_filter_pctype pctype;
8838         uint64_t input_set, inset_reg = 0;
8839         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8840         int ret, i, num;
8841
8842         if (!hw || !conf) {
8843                 PMD_DRV_LOG(ERR, "Invalid pointer");
8844                 return -EFAULT;
8845         }
8846         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8847             conf->op != RTE_ETH_INPUT_SET_ADD) {
8848                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8849                 return -EINVAL;
8850         }
8851
8852         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8853
8854         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8855                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8856                 return -EINVAL;
8857         }
8858
8859         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8860                                    conf->inset_size);
8861         if (ret) {
8862                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8863                 return -EINVAL;
8864         }
8865
8866         /* get inset value in register */
8867         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8868         inset_reg <<= I40E_32_BIT_WIDTH;
8869         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8870
8871         /* Can not change the inset reg for flex payload for fdir,
8872          * it is done by writing I40E_PRTQF_FD_FLXINSET
8873          * in i40e_set_flex_mask_on_pctype.
8874          */
8875         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8876                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8877         else
8878                 input_set |= pf->fdir.input_set[pctype];
8879         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8880                                            I40E_INSET_MASK_NUM_REG);
8881         if (num < 0)
8882                 return -EINVAL;
8883
8884         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8885
8886         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8887                               (uint32_t)(inset_reg & UINT32_MAX));
8888         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8889                              (uint32_t)((inset_reg >>
8890                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8891
8892         for (i = 0; i < num; i++)
8893                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8894                                      mask_reg[i]);
8895         /*clear unused mask registers of the pctype */
8896         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8897                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8898                                      0);
8899         I40E_WRITE_FLUSH(hw);
8900
8901         pf->fdir.input_set[pctype] = input_set;
8902         return 0;
8903 }
8904
8905 static int
8906 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8907 {
8908         int ret = 0;
8909
8910         if (!hw || !info) {
8911                 PMD_DRV_LOG(ERR, "Invalid pointer");
8912                 return -EFAULT;
8913         }
8914
8915         switch (info->info_type) {
8916         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8917                 i40e_get_symmetric_hash_enable_per_port(hw,
8918                                         &(info->info.enable));
8919                 break;
8920         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8921                 ret = i40e_get_hash_filter_global_config(hw,
8922                                 &(info->info.global_conf));
8923                 break;
8924         default:
8925                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8926                                                         info->info_type);
8927                 ret = -EINVAL;
8928                 break;
8929         }
8930
8931         return ret;
8932 }
8933
8934 static int
8935 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8936 {
8937         int ret = 0;
8938
8939         if (!hw || !info) {
8940                 PMD_DRV_LOG(ERR, "Invalid pointer");
8941                 return -EFAULT;
8942         }
8943
8944         switch (info->info_type) {
8945         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8946                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8947                 break;
8948         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8949                 ret = i40e_set_hash_filter_global_config(hw,
8950                                 &(info->info.global_conf));
8951                 break;
8952         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8953                 ret = i40e_hash_filter_inset_select(hw,
8954                                                &(info->info.input_set_conf));
8955                 break;
8956
8957         default:
8958                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8959                                                         info->info_type);
8960                 ret = -EINVAL;
8961                 break;
8962         }
8963
8964         return ret;
8965 }
8966
8967 /* Operations for hash function */
8968 static int
8969 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8970                       enum rte_filter_op filter_op,
8971                       void *arg)
8972 {
8973         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8974         int ret = 0;
8975
8976         switch (filter_op) {
8977         case RTE_ETH_FILTER_NOP:
8978                 break;
8979         case RTE_ETH_FILTER_GET:
8980                 ret = i40e_hash_filter_get(hw,
8981                         (struct rte_eth_hash_filter_info *)arg);
8982                 break;
8983         case RTE_ETH_FILTER_SET:
8984                 ret = i40e_hash_filter_set(hw,
8985                         (struct rte_eth_hash_filter_info *)arg);
8986                 break;
8987         default:
8988                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8989                                                                 filter_op);
8990                 ret = -ENOTSUP;
8991                 break;
8992         }
8993
8994         return ret;
8995 }
8996
8997 /* Convert ethertype filter structure */
8998 static int
8999 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9000                               struct i40e_ethertype_filter *filter)
9001 {
9002         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9003         filter->input.ether_type = input->ether_type;
9004         filter->flags = input->flags;
9005         filter->queue = input->queue;
9006
9007         return 0;
9008 }
9009
9010 /* Check if there exists the ehtertype filter */
9011 struct i40e_ethertype_filter *
9012 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9013                                 const struct i40e_ethertype_filter_input *input)
9014 {
9015         int ret;
9016
9017         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9018         if (ret < 0)
9019                 return NULL;
9020
9021         return ethertype_rule->hash_map[ret];
9022 }
9023
9024 /* Add ethertype filter in SW list */
9025 static int
9026 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9027                                 struct i40e_ethertype_filter *filter)
9028 {
9029         struct i40e_ethertype_rule *rule = &pf->ethertype;
9030         int ret;
9031
9032         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9033         if (ret < 0) {
9034                 PMD_DRV_LOG(ERR,
9035                             "Failed to insert ethertype filter"
9036                             " to hash table %d!",
9037                             ret);
9038                 return ret;
9039         }
9040         rule->hash_map[ret] = filter;
9041
9042         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9043
9044         return 0;
9045 }
9046
9047 /* Delete ethertype filter in SW list */
9048 int
9049 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9050                              struct i40e_ethertype_filter_input *input)
9051 {
9052         struct i40e_ethertype_rule *rule = &pf->ethertype;
9053         struct i40e_ethertype_filter *filter;
9054         int ret;
9055
9056         ret = rte_hash_del_key(rule->hash_table, input);
9057         if (ret < 0) {
9058                 PMD_DRV_LOG(ERR,
9059                             "Failed to delete ethertype filter"
9060                             " to hash table %d!",
9061                             ret);
9062                 return ret;
9063         }
9064         filter = rule->hash_map[ret];
9065         rule->hash_map[ret] = NULL;
9066
9067         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9068         rte_free(filter);
9069
9070         return 0;
9071 }
9072
9073 /*
9074  * Configure ethertype filter, which can director packet by filtering
9075  * with mac address and ether_type or only ether_type
9076  */
9077 int
9078 i40e_ethertype_filter_set(struct i40e_pf *pf,
9079                         struct rte_eth_ethertype_filter *filter,
9080                         bool add)
9081 {
9082         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9083         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9084         struct i40e_ethertype_filter *ethertype_filter, *node;
9085         struct i40e_ethertype_filter check_filter;
9086         struct i40e_control_filter_stats stats;
9087         uint16_t flags = 0;
9088         int ret;
9089
9090         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9091                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9092                 return -EINVAL;
9093         }
9094         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9095                 filter->ether_type == ETHER_TYPE_IPv6) {
9096                 PMD_DRV_LOG(ERR,
9097                         "unsupported ether_type(0x%04x) in control packet filter.",
9098                         filter->ether_type);
9099                 return -EINVAL;
9100         }
9101         if (filter->ether_type == ETHER_TYPE_VLAN)
9102                 PMD_DRV_LOG(WARNING,
9103                         "filter vlan ether_type in first tag is not supported.");
9104
9105         /* Check if there is the filter in SW list */
9106         memset(&check_filter, 0, sizeof(check_filter));
9107         i40e_ethertype_filter_convert(filter, &check_filter);
9108         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9109                                                &check_filter.input);
9110         if (add && node) {
9111                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9112                 return -EINVAL;
9113         }
9114
9115         if (!add && !node) {
9116                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9117                 return -EINVAL;
9118         }
9119
9120         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9121                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9122         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9123                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9124         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9125
9126         memset(&stats, 0, sizeof(stats));
9127         ret = i40e_aq_add_rem_control_packet_filter(hw,
9128                         filter->mac_addr.addr_bytes,
9129                         filter->ether_type, flags,
9130                         pf->main_vsi->seid,
9131                         filter->queue, add, &stats, NULL);
9132
9133         PMD_DRV_LOG(INFO,
9134                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9135                 ret, stats.mac_etype_used, stats.etype_used,
9136                 stats.mac_etype_free, stats.etype_free);
9137         if (ret < 0)
9138                 return -ENOSYS;
9139
9140         /* Add or delete a filter in SW list */
9141         if (add) {
9142                 ethertype_filter = rte_zmalloc("ethertype_filter",
9143                                        sizeof(*ethertype_filter), 0);
9144                 rte_memcpy(ethertype_filter, &check_filter,
9145                            sizeof(check_filter));
9146                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9147         } else {
9148                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9149         }
9150
9151         return ret;
9152 }
9153
9154 /*
9155  * Handle operations for ethertype filter.
9156  */
9157 static int
9158 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9159                                 enum rte_filter_op filter_op,
9160                                 void *arg)
9161 {
9162         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9163         int ret = 0;
9164
9165         if (filter_op == RTE_ETH_FILTER_NOP)
9166                 return ret;
9167
9168         if (arg == NULL) {
9169                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9170                             filter_op);
9171                 return -EINVAL;
9172         }
9173
9174         switch (filter_op) {
9175         case RTE_ETH_FILTER_ADD:
9176                 ret = i40e_ethertype_filter_set(pf,
9177                         (struct rte_eth_ethertype_filter *)arg,
9178                         TRUE);
9179                 break;
9180         case RTE_ETH_FILTER_DELETE:
9181                 ret = i40e_ethertype_filter_set(pf,
9182                         (struct rte_eth_ethertype_filter *)arg,
9183                         FALSE);
9184                 break;
9185         default:
9186                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9187                 ret = -ENOSYS;
9188                 break;
9189         }
9190         return ret;
9191 }
9192
9193 static int
9194 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9195                      enum rte_filter_type filter_type,
9196                      enum rte_filter_op filter_op,
9197                      void *arg)
9198 {
9199         int ret = 0;
9200
9201         if (dev == NULL)
9202                 return -EINVAL;
9203
9204         switch (filter_type) {
9205         case RTE_ETH_FILTER_NONE:
9206                 /* For global configuration */
9207                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9208                 break;
9209         case RTE_ETH_FILTER_HASH:
9210                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9211                 break;
9212         case RTE_ETH_FILTER_MACVLAN:
9213                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9214                 break;
9215         case RTE_ETH_FILTER_ETHERTYPE:
9216                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9217                 break;
9218         case RTE_ETH_FILTER_TUNNEL:
9219                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9220                 break;
9221         case RTE_ETH_FILTER_FDIR:
9222                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9223                 break;
9224         case RTE_ETH_FILTER_GENERIC:
9225                 if (filter_op != RTE_ETH_FILTER_GET)
9226                         return -EINVAL;
9227                 *(const void **)arg = &i40e_flow_ops;
9228                 break;
9229         default:
9230                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9231                                                         filter_type);
9232                 ret = -EINVAL;
9233                 break;
9234         }
9235
9236         return ret;
9237 }
9238
9239 /*
9240  * Check and enable Extended Tag.
9241  * Enabling Extended Tag is important for 40G performance.
9242  */
9243 static void
9244 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9245 {
9246         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9247         uint32_t buf = 0;
9248         int ret;
9249
9250         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9251                                       PCI_DEV_CAP_REG);
9252         if (ret < 0) {
9253                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9254                             PCI_DEV_CAP_REG);
9255                 return;
9256         }
9257         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9258                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9259                 return;
9260         }
9261
9262         buf = 0;
9263         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9264                                       PCI_DEV_CTRL_REG);
9265         if (ret < 0) {
9266                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9267                             PCI_DEV_CTRL_REG);
9268                 return;
9269         }
9270         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9271                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9272                 return;
9273         }
9274         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9275         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9276                                        PCI_DEV_CTRL_REG);
9277         if (ret < 0) {
9278                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9279                             PCI_DEV_CTRL_REG);
9280                 return;
9281         }
9282 }
9283
9284 /*
9285  * As some registers wouldn't be reset unless a global hardware reset,
9286  * hardware initialization is needed to put those registers into an
9287  * expected initial state.
9288  */
9289 static void
9290 i40e_hw_init(struct rte_eth_dev *dev)
9291 {
9292         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9293
9294         i40e_enable_extended_tag(dev);
9295
9296         /* clear the PF Queue Filter control register */
9297         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9298
9299         /* Disable symmetric hash per port */
9300         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9301 }
9302
9303 /*
9304  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9305  * however this function will return only one highest pctype index,
9306  * which is not quite correct. This is known problem of i40e driver
9307  * and needs to be fixed later.
9308  */
9309 enum i40e_filter_pctype
9310 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9311 {
9312         int i;
9313         uint64_t pctype_mask;
9314
9315         if (flow_type < I40E_FLOW_TYPE_MAX) {
9316                 pctype_mask = adapter->pctypes_tbl[flow_type];
9317                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9318                         if (pctype_mask & (1ULL << i))
9319                                 return (enum i40e_filter_pctype)i;
9320                 }
9321         }
9322         return I40E_FILTER_PCTYPE_INVALID;
9323 }
9324
9325 uint16_t
9326 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9327                         enum i40e_filter_pctype pctype)
9328 {
9329         uint16_t flowtype;
9330         uint64_t pctype_mask = 1ULL << pctype;
9331
9332         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9333              flowtype++) {
9334                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9335                         return flowtype;
9336         }
9337
9338         return RTE_ETH_FLOW_UNKNOWN;
9339 }
9340
9341 /*
9342  * On X710, performance number is far from the expectation on recent firmware
9343  * versions; on XL710, performance number is also far from the expectation on
9344  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9345  * mode is enabled and port MAC address is equal to the packet destination MAC
9346  * address. The fix for this issue may not be integrated in the following
9347  * firmware version. So the workaround in software driver is needed. It needs
9348  * to modify the initial values of 3 internal only registers for both X710 and
9349  * XL710. Note that the values for X710 or XL710 could be different, and the
9350  * workaround can be removed when it is fixed in firmware in the future.
9351  */
9352
9353 /* For both X710 and XL710 */
9354 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9355 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x20000200
9356 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9357
9358 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9359 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9360
9361 /* For X722 */
9362 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9363 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9364
9365 /* For X710 */
9366 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9367 /* For XL710 */
9368 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9369 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9370
9371 static int
9372 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9373 {
9374         enum i40e_status_code status;
9375         struct i40e_aq_get_phy_abilities_resp phy_ab;
9376         int ret = -ENOTSUP;
9377         int retries = 0;
9378
9379         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9380                                               NULL);
9381
9382         while (status) {
9383                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9384                         status);
9385                 retries++;
9386                 rte_delay_us(100000);
9387                 if  (retries < 5)
9388                         status = i40e_aq_get_phy_capabilities(hw, false,
9389                                         true, &phy_ab, NULL);
9390                 else
9391                         return ret;
9392         }
9393         return 0;
9394 }
9395
9396 static void
9397 i40e_configure_registers(struct i40e_hw *hw)
9398 {
9399         static struct {
9400                 uint32_t addr;
9401                 uint64_t val;
9402         } reg_table[] = {
9403                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9404                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9405                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9406         };
9407         uint64_t reg;
9408         uint32_t i;
9409         int ret;
9410
9411         for (i = 0; i < RTE_DIM(reg_table); i++) {
9412                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9413                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9414                                 reg_table[i].val =
9415                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9416                         else /* For X710/XL710/XXV710 */
9417                                 if (hw->aq.fw_maj_ver < 6)
9418                                         reg_table[i].val =
9419                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9420                                 else
9421                                         reg_table[i].val =
9422                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9423                 }
9424
9425                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9426                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9427                                 reg_table[i].val =
9428                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9429                         else /* For X710/XL710/XXV710 */
9430                                 reg_table[i].val =
9431                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9432                 }
9433
9434                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9435                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9436                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9437                                 reg_table[i].val =
9438                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9439                         else /* For X710 */
9440                                 reg_table[i].val =
9441                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9442                 }
9443
9444                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9445                                                         &reg, NULL);
9446                 if (ret < 0) {
9447                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9448                                                         reg_table[i].addr);
9449                         break;
9450                 }
9451                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9452                                                 reg_table[i].addr, reg);
9453                 if (reg == reg_table[i].val)
9454                         continue;
9455
9456                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9457                                                 reg_table[i].val, NULL);
9458                 if (ret < 0) {
9459                         PMD_DRV_LOG(ERR,
9460                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9461                                 reg_table[i].val, reg_table[i].addr);
9462                         break;
9463                 }
9464                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9465                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9466         }
9467 }
9468
9469 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9470 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9471 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9472 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9473 static int
9474 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9475 {
9476         uint32_t reg;
9477         int ret;
9478
9479         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9480                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9481                 return -EINVAL;
9482         }
9483
9484         /* Configure for double VLAN RX stripping */
9485         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9486         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9487                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9488                 ret = i40e_aq_debug_write_register(hw,
9489                                                    I40E_VSI_TSR(vsi->vsi_id),
9490                                                    reg, NULL);
9491                 if (ret < 0) {
9492                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9493                                     vsi->vsi_id);
9494                         return I40E_ERR_CONFIG;
9495                 }
9496         }
9497
9498         /* Configure for double VLAN TX insertion */
9499         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9500         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9501                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9502                 ret = i40e_aq_debug_write_register(hw,
9503                                                    I40E_VSI_L2TAGSTXVALID(
9504                                                    vsi->vsi_id), reg, NULL);
9505                 if (ret < 0) {
9506                         PMD_DRV_LOG(ERR,
9507                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9508                                 vsi->vsi_id);
9509                         return I40E_ERR_CONFIG;
9510                 }
9511         }
9512
9513         return 0;
9514 }
9515
9516 /**
9517  * i40e_aq_add_mirror_rule
9518  * @hw: pointer to the hardware structure
9519  * @seid: VEB seid to add mirror rule to
9520  * @dst_id: destination vsi seid
9521  * @entries: Buffer which contains the entities to be mirrored
9522  * @count: number of entities contained in the buffer
9523  * @rule_id:the rule_id of the rule to be added
9524  *
9525  * Add a mirror rule for a given veb.
9526  *
9527  **/
9528 static enum i40e_status_code
9529 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9530                         uint16_t seid, uint16_t dst_id,
9531                         uint16_t rule_type, uint16_t *entries,
9532                         uint16_t count, uint16_t *rule_id)
9533 {
9534         struct i40e_aq_desc desc;
9535         struct i40e_aqc_add_delete_mirror_rule cmd;
9536         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9537                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9538                 &desc.params.raw;
9539         uint16_t buff_len;
9540         enum i40e_status_code status;
9541
9542         i40e_fill_default_direct_cmd_desc(&desc,
9543                                           i40e_aqc_opc_add_mirror_rule);
9544         memset(&cmd, 0, sizeof(cmd));
9545
9546         buff_len = sizeof(uint16_t) * count;
9547         desc.datalen = rte_cpu_to_le_16(buff_len);
9548         if (buff_len > 0)
9549                 desc.flags |= rte_cpu_to_le_16(
9550                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9551         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9552                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9553         cmd.num_entries = rte_cpu_to_le_16(count);
9554         cmd.seid = rte_cpu_to_le_16(seid);
9555         cmd.destination = rte_cpu_to_le_16(dst_id);
9556
9557         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9558         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9559         PMD_DRV_LOG(INFO,
9560                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9561                 hw->aq.asq_last_status, resp->rule_id,
9562                 resp->mirror_rules_used, resp->mirror_rules_free);
9563         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9564
9565         return status;
9566 }
9567
9568 /**
9569  * i40e_aq_del_mirror_rule
9570  * @hw: pointer to the hardware structure
9571  * @seid: VEB seid to add mirror rule to
9572  * @entries: Buffer which contains the entities to be mirrored
9573  * @count: number of entities contained in the buffer
9574  * @rule_id:the rule_id of the rule to be delete
9575  *
9576  * Delete a mirror rule for a given veb.
9577  *
9578  **/
9579 static enum i40e_status_code
9580 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9581                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9582                 uint16_t count, uint16_t rule_id)
9583 {
9584         struct i40e_aq_desc desc;
9585         struct i40e_aqc_add_delete_mirror_rule cmd;
9586         uint16_t buff_len = 0;
9587         enum i40e_status_code status;
9588         void *buff = NULL;
9589
9590         i40e_fill_default_direct_cmd_desc(&desc,
9591                                           i40e_aqc_opc_delete_mirror_rule);
9592         memset(&cmd, 0, sizeof(cmd));
9593         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9594                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9595                                                           I40E_AQ_FLAG_RD));
9596                 cmd.num_entries = count;
9597                 buff_len = sizeof(uint16_t) * count;
9598                 desc.datalen = rte_cpu_to_le_16(buff_len);
9599                 buff = (void *)entries;
9600         } else
9601                 /* rule id is filled in destination field for deleting mirror rule */
9602                 cmd.destination = rte_cpu_to_le_16(rule_id);
9603
9604         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9605                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9606         cmd.seid = rte_cpu_to_le_16(seid);
9607
9608         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9609         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9610
9611         return status;
9612 }
9613
9614 /**
9615  * i40e_mirror_rule_set
9616  * @dev: pointer to the hardware structure
9617  * @mirror_conf: mirror rule info
9618  * @sw_id: mirror rule's sw_id
9619  * @on: enable/disable
9620  *
9621  * set a mirror rule.
9622  *
9623  **/
9624 static int
9625 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9626                         struct rte_eth_mirror_conf *mirror_conf,
9627                         uint8_t sw_id, uint8_t on)
9628 {
9629         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9630         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9631         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9632         struct i40e_mirror_rule *parent = NULL;
9633         uint16_t seid, dst_seid, rule_id;
9634         uint16_t i, j = 0;
9635         int ret;
9636
9637         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9638
9639         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9640                 PMD_DRV_LOG(ERR,
9641                         "mirror rule can not be configured without veb or vfs.");
9642                 return -ENOSYS;
9643         }
9644         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9645                 PMD_DRV_LOG(ERR, "mirror table is full.");
9646                 return -ENOSPC;
9647         }
9648         if (mirror_conf->dst_pool > pf->vf_num) {
9649                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9650                                  mirror_conf->dst_pool);
9651                 return -EINVAL;
9652         }
9653
9654         seid = pf->main_vsi->veb->seid;
9655
9656         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9657                 if (sw_id <= it->index) {
9658                         mirr_rule = it;
9659                         break;
9660                 }
9661                 parent = it;
9662         }
9663         if (mirr_rule && sw_id == mirr_rule->index) {
9664                 if (on) {
9665                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9666                         return -EEXIST;
9667                 } else {
9668                         ret = i40e_aq_del_mirror_rule(hw, seid,
9669                                         mirr_rule->rule_type,
9670                                         mirr_rule->entries,
9671                                         mirr_rule->num_entries, mirr_rule->id);
9672                         if (ret < 0) {
9673                                 PMD_DRV_LOG(ERR,
9674                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9675                                         ret, hw->aq.asq_last_status);
9676                                 return -ENOSYS;
9677                         }
9678                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9679                         rte_free(mirr_rule);
9680                         pf->nb_mirror_rule--;
9681                         return 0;
9682                 }
9683         } else if (!on) {
9684                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9685                 return -ENOENT;
9686         }
9687
9688         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9689                                 sizeof(struct i40e_mirror_rule) , 0);
9690         if (!mirr_rule) {
9691                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9692                 return I40E_ERR_NO_MEMORY;
9693         }
9694         switch (mirror_conf->rule_type) {
9695         case ETH_MIRROR_VLAN:
9696                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9697                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9698                                 mirr_rule->entries[j] =
9699                                         mirror_conf->vlan.vlan_id[i];
9700                                 j++;
9701                         }
9702                 }
9703                 if (j == 0) {
9704                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9705                         rte_free(mirr_rule);
9706                         return -EINVAL;
9707                 }
9708                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9709                 break;
9710         case ETH_MIRROR_VIRTUAL_POOL_UP:
9711         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9712                 /* check if the specified pool bit is out of range */
9713                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9714                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9715                         rte_free(mirr_rule);
9716                         return -EINVAL;
9717                 }
9718                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9719                         if (mirror_conf->pool_mask & (1ULL << i)) {
9720                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9721                                 j++;
9722                         }
9723                 }
9724                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9725                         /* add pf vsi to entries */
9726                         mirr_rule->entries[j] = pf->main_vsi_seid;
9727                         j++;
9728                 }
9729                 if (j == 0) {
9730                         PMD_DRV_LOG(ERR, "pool is not specified.");
9731                         rte_free(mirr_rule);
9732                         return -EINVAL;
9733                 }
9734                 /* egress and ingress in aq commands means from switch but not port */
9735                 mirr_rule->rule_type =
9736                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9737                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9738                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9739                 break;
9740         case ETH_MIRROR_UPLINK_PORT:
9741                 /* egress and ingress in aq commands means from switch but not port*/
9742                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9743                 break;
9744         case ETH_MIRROR_DOWNLINK_PORT:
9745                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9746                 break;
9747         default:
9748                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9749                         mirror_conf->rule_type);
9750                 rte_free(mirr_rule);
9751                 return -EINVAL;
9752         }
9753
9754         /* If the dst_pool is equal to vf_num, consider it as PF */
9755         if (mirror_conf->dst_pool == pf->vf_num)
9756                 dst_seid = pf->main_vsi_seid;
9757         else
9758                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9759
9760         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9761                                       mirr_rule->rule_type, mirr_rule->entries,
9762                                       j, &rule_id);
9763         if (ret < 0) {
9764                 PMD_DRV_LOG(ERR,
9765                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9766                         ret, hw->aq.asq_last_status);
9767                 rte_free(mirr_rule);
9768                 return -ENOSYS;
9769         }
9770
9771         mirr_rule->index = sw_id;
9772         mirr_rule->num_entries = j;
9773         mirr_rule->id = rule_id;
9774         mirr_rule->dst_vsi_seid = dst_seid;
9775
9776         if (parent)
9777                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9778         else
9779                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9780
9781         pf->nb_mirror_rule++;
9782         return 0;
9783 }
9784
9785 /**
9786  * i40e_mirror_rule_reset
9787  * @dev: pointer to the device
9788  * @sw_id: mirror rule's sw_id
9789  *
9790  * reset a mirror rule.
9791  *
9792  **/
9793 static int
9794 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9795 {
9796         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9797         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9798         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9799         uint16_t seid;
9800         int ret;
9801
9802         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9803
9804         seid = pf->main_vsi->veb->seid;
9805
9806         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9807                 if (sw_id == it->index) {
9808                         mirr_rule = it;
9809                         break;
9810                 }
9811         }
9812         if (mirr_rule) {
9813                 ret = i40e_aq_del_mirror_rule(hw, seid,
9814                                 mirr_rule->rule_type,
9815                                 mirr_rule->entries,
9816                                 mirr_rule->num_entries, mirr_rule->id);
9817                 if (ret < 0) {
9818                         PMD_DRV_LOG(ERR,
9819                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9820                                 ret, hw->aq.asq_last_status);
9821                         return -ENOSYS;
9822                 }
9823                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9824                 rte_free(mirr_rule);
9825                 pf->nb_mirror_rule--;
9826         } else {
9827                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9828                 return -ENOENT;
9829         }
9830         return 0;
9831 }
9832
9833 static uint64_t
9834 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9835 {
9836         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9837         uint64_t systim_cycles;
9838
9839         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9840         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9841                         << 32;
9842
9843         return systim_cycles;
9844 }
9845
9846 static uint64_t
9847 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9848 {
9849         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9850         uint64_t rx_tstamp;
9851
9852         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9853         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9854                         << 32;
9855
9856         return rx_tstamp;
9857 }
9858
9859 static uint64_t
9860 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9861 {
9862         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9863         uint64_t tx_tstamp;
9864
9865         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9866         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9867                         << 32;
9868
9869         return tx_tstamp;
9870 }
9871
9872 static void
9873 i40e_start_timecounters(struct rte_eth_dev *dev)
9874 {
9875         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9876         struct i40e_adapter *adapter =
9877                         (struct i40e_adapter *)dev->data->dev_private;
9878         struct rte_eth_link link;
9879         uint32_t tsync_inc_l;
9880         uint32_t tsync_inc_h;
9881
9882         /* Get current link speed. */
9883         memset(&link, 0, sizeof(link));
9884         i40e_dev_link_update(dev, 1);
9885         rte_i40e_dev_atomic_read_link_status(dev, &link);
9886
9887         switch (link.link_speed) {
9888         case ETH_SPEED_NUM_40G:
9889                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9890                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9891                 break;
9892         case ETH_SPEED_NUM_10G:
9893                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9894                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9895                 break;
9896         case ETH_SPEED_NUM_1G:
9897                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9898                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9899                 break;
9900         default:
9901                 tsync_inc_l = 0x0;
9902                 tsync_inc_h = 0x0;
9903         }
9904
9905         /* Set the timesync increment value. */
9906         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9907         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9908
9909         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9910         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9911         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9912
9913         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9914         adapter->systime_tc.cc_shift = 0;
9915         adapter->systime_tc.nsec_mask = 0;
9916
9917         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9918         adapter->rx_tstamp_tc.cc_shift = 0;
9919         adapter->rx_tstamp_tc.nsec_mask = 0;
9920
9921         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9922         adapter->tx_tstamp_tc.cc_shift = 0;
9923         adapter->tx_tstamp_tc.nsec_mask = 0;
9924 }
9925
9926 static int
9927 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9928 {
9929         struct i40e_adapter *adapter =
9930                         (struct i40e_adapter *)dev->data->dev_private;
9931
9932         adapter->systime_tc.nsec += delta;
9933         adapter->rx_tstamp_tc.nsec += delta;
9934         adapter->tx_tstamp_tc.nsec += delta;
9935
9936         return 0;
9937 }
9938
9939 static int
9940 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9941 {
9942         uint64_t ns;
9943         struct i40e_adapter *adapter =
9944                         (struct i40e_adapter *)dev->data->dev_private;
9945
9946         ns = rte_timespec_to_ns(ts);
9947
9948         /* Set the timecounters to a new value. */
9949         adapter->systime_tc.nsec = ns;
9950         adapter->rx_tstamp_tc.nsec = ns;
9951         adapter->tx_tstamp_tc.nsec = ns;
9952
9953         return 0;
9954 }
9955
9956 static int
9957 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9958 {
9959         uint64_t ns, systime_cycles;
9960         struct i40e_adapter *adapter =
9961                         (struct i40e_adapter *)dev->data->dev_private;
9962
9963         systime_cycles = i40e_read_systime_cyclecounter(dev);
9964         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9965         *ts = rte_ns_to_timespec(ns);
9966
9967         return 0;
9968 }
9969
9970 static int
9971 i40e_timesync_enable(struct rte_eth_dev *dev)
9972 {
9973         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9974         uint32_t tsync_ctl_l;
9975         uint32_t tsync_ctl_h;
9976
9977         /* Stop the timesync system time. */
9978         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9979         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9980         /* Reset the timesync system time value. */
9981         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9982         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9983
9984         i40e_start_timecounters(dev);
9985
9986         /* Clear timesync registers. */
9987         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9988         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9989         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9990         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9991         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9992         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9993
9994         /* Enable timestamping of PTP packets. */
9995         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9996         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9997
9998         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9999         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10000         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10001
10002         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10003         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10004
10005         return 0;
10006 }
10007
10008 static int
10009 i40e_timesync_disable(struct rte_eth_dev *dev)
10010 {
10011         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10012         uint32_t tsync_ctl_l;
10013         uint32_t tsync_ctl_h;
10014
10015         /* Disable timestamping of transmitted PTP packets. */
10016         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10017         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10018
10019         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10020         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10021
10022         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10023         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10024
10025         /* Reset the timesync increment value. */
10026         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10027         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10028
10029         return 0;
10030 }
10031
10032 static int
10033 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10034                                 struct timespec *timestamp, uint32_t flags)
10035 {
10036         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10037         struct i40e_adapter *adapter =
10038                 (struct i40e_adapter *)dev->data->dev_private;
10039
10040         uint32_t sync_status;
10041         uint32_t index = flags & 0x03;
10042         uint64_t rx_tstamp_cycles;
10043         uint64_t ns;
10044
10045         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10046         if ((sync_status & (1 << index)) == 0)
10047                 return -EINVAL;
10048
10049         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10050         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10051         *timestamp = rte_ns_to_timespec(ns);
10052
10053         return 0;
10054 }
10055
10056 static int
10057 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10058                                 struct timespec *timestamp)
10059 {
10060         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10061         struct i40e_adapter *adapter =
10062                 (struct i40e_adapter *)dev->data->dev_private;
10063
10064         uint32_t sync_status;
10065         uint64_t tx_tstamp_cycles;
10066         uint64_t ns;
10067
10068         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10069         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10070                 return -EINVAL;
10071
10072         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10073         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10074         *timestamp = rte_ns_to_timespec(ns);
10075
10076         return 0;
10077 }
10078
10079 /*
10080  * i40e_parse_dcb_configure - parse dcb configure from user
10081  * @dev: the device being configured
10082  * @dcb_cfg: pointer of the result of parse
10083  * @*tc_map: bit map of enabled traffic classes
10084  *
10085  * Returns 0 on success, negative value on failure
10086  */
10087 static int
10088 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10089                          struct i40e_dcbx_config *dcb_cfg,
10090                          uint8_t *tc_map)
10091 {
10092         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10093         uint8_t i, tc_bw, bw_lf;
10094
10095         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10096
10097         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10098         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10099                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10100                 return -EINVAL;
10101         }
10102
10103         /* assume each tc has the same bw */
10104         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10105         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10106                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10107         /* to ensure the sum of tcbw is equal to 100 */
10108         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10109         for (i = 0; i < bw_lf; i++)
10110                 dcb_cfg->etscfg.tcbwtable[i]++;
10111
10112         /* assume each tc has the same Transmission Selection Algorithm */
10113         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10114                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10115
10116         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10117                 dcb_cfg->etscfg.prioritytable[i] =
10118                                 dcb_rx_conf->dcb_tc[i];
10119
10120         /* FW needs one App to configure HW */
10121         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10122         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10123         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10124         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10125
10126         if (dcb_rx_conf->nb_tcs == 0)
10127                 *tc_map = 1; /* tc0 only */
10128         else
10129                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10130
10131         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10132                 dcb_cfg->pfc.willing = 0;
10133                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10134                 dcb_cfg->pfc.pfcenable = *tc_map;
10135         }
10136         return 0;
10137 }
10138
10139
10140 static enum i40e_status_code
10141 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10142                               struct i40e_aqc_vsi_properties_data *info,
10143                               uint8_t enabled_tcmap)
10144 {
10145         enum i40e_status_code ret;
10146         int i, total_tc = 0;
10147         uint16_t qpnum_per_tc, bsf, qp_idx;
10148         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10149         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10150         uint16_t used_queues;
10151
10152         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10153         if (ret != I40E_SUCCESS)
10154                 return ret;
10155
10156         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10157                 if (enabled_tcmap & (1 << i))
10158                         total_tc++;
10159         }
10160         if (total_tc == 0)
10161                 total_tc = 1;
10162         vsi->enabled_tc = enabled_tcmap;
10163
10164         /* different VSI has different queues assigned */
10165         if (vsi->type == I40E_VSI_MAIN)
10166                 used_queues = dev_data->nb_rx_queues -
10167                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10168         else if (vsi->type == I40E_VSI_VMDQ2)
10169                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10170         else {
10171                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10172                 return I40E_ERR_NO_AVAILABLE_VSI;
10173         }
10174
10175         qpnum_per_tc = used_queues / total_tc;
10176         /* Number of queues per enabled TC */
10177         if (qpnum_per_tc == 0) {
10178                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10179                 return I40E_ERR_INVALID_QP_ID;
10180         }
10181         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10182                                 I40E_MAX_Q_PER_TC);
10183         bsf = rte_bsf32(qpnum_per_tc);
10184
10185         /**
10186          * Configure TC and queue mapping parameters, for enabled TC,
10187          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10188          * default queue will serve it.
10189          */
10190         qp_idx = 0;
10191         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10192                 if (vsi->enabled_tc & (1 << i)) {
10193                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10194                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10195                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10196                         qp_idx += qpnum_per_tc;
10197                 } else
10198                         info->tc_mapping[i] = 0;
10199         }
10200
10201         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10202         if (vsi->type == I40E_VSI_SRIOV) {
10203                 info->mapping_flags |=
10204                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10205                 for (i = 0; i < vsi->nb_qps; i++)
10206                         info->queue_mapping[i] =
10207                                 rte_cpu_to_le_16(vsi->base_queue + i);
10208         } else {
10209                 info->mapping_flags |=
10210                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10211                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10212         }
10213         info->valid_sections |=
10214                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10215
10216         return I40E_SUCCESS;
10217 }
10218
10219 /*
10220  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10221  * @veb: VEB to be configured
10222  * @tc_map: enabled TC bitmap
10223  *
10224  * Returns 0 on success, negative value on failure
10225  */
10226 static enum i40e_status_code
10227 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10228 {
10229         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10230         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10231         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10232         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10233         enum i40e_status_code ret = I40E_SUCCESS;
10234         int i;
10235         uint32_t bw_max;
10236
10237         /* Check if enabled_tc is same as existing or new TCs */
10238         if (veb->enabled_tc == tc_map)
10239                 return ret;
10240
10241         /* configure tc bandwidth */
10242         memset(&veb_bw, 0, sizeof(veb_bw));
10243         veb_bw.tc_valid_bits = tc_map;
10244         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10245         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10246                 if (tc_map & BIT_ULL(i))
10247                         veb_bw.tc_bw_share_credits[i] = 1;
10248         }
10249         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10250                                                    &veb_bw, NULL);
10251         if (ret) {
10252                 PMD_INIT_LOG(ERR,
10253                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10254                         hw->aq.asq_last_status);
10255                 return ret;
10256         }
10257
10258         memset(&ets_query, 0, sizeof(ets_query));
10259         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10260                                                    &ets_query, NULL);
10261         if (ret != I40E_SUCCESS) {
10262                 PMD_DRV_LOG(ERR,
10263                         "Failed to get switch_comp ETS configuration %u",
10264                         hw->aq.asq_last_status);
10265                 return ret;
10266         }
10267         memset(&bw_query, 0, sizeof(bw_query));
10268         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10269                                                   &bw_query, NULL);
10270         if (ret != I40E_SUCCESS) {
10271                 PMD_DRV_LOG(ERR,
10272                         "Failed to get switch_comp bandwidth configuration %u",
10273                         hw->aq.asq_last_status);
10274                 return ret;
10275         }
10276
10277         /* store and print out BW info */
10278         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10279         veb->bw_info.bw_max = ets_query.tc_bw_max;
10280         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10281         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10282         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10283                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10284                      I40E_16_BIT_WIDTH);
10285         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10286                 veb->bw_info.bw_ets_share_credits[i] =
10287                                 bw_query.tc_bw_share_credits[i];
10288                 veb->bw_info.bw_ets_credits[i] =
10289                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10290                 /* 4 bits per TC, 4th bit is reserved */
10291                 veb->bw_info.bw_ets_max[i] =
10292                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10293                                   RTE_LEN2MASK(3, uint8_t));
10294                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10295                             veb->bw_info.bw_ets_share_credits[i]);
10296                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10297                             veb->bw_info.bw_ets_credits[i]);
10298                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10299                             veb->bw_info.bw_ets_max[i]);
10300         }
10301
10302         veb->enabled_tc = tc_map;
10303
10304         return ret;
10305 }
10306
10307
10308 /*
10309  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10310  * @vsi: VSI to be configured
10311  * @tc_map: enabled TC bitmap
10312  *
10313  * Returns 0 on success, negative value on failure
10314  */
10315 static enum i40e_status_code
10316 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10317 {
10318         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10319         struct i40e_vsi_context ctxt;
10320         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10321         enum i40e_status_code ret = I40E_SUCCESS;
10322         int i;
10323
10324         /* Check if enabled_tc is same as existing or new TCs */
10325         if (vsi->enabled_tc == tc_map)
10326                 return ret;
10327
10328         /* configure tc bandwidth */
10329         memset(&bw_data, 0, sizeof(bw_data));
10330         bw_data.tc_valid_bits = tc_map;
10331         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10332         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10333                 if (tc_map & BIT_ULL(i))
10334                         bw_data.tc_bw_credits[i] = 1;
10335         }
10336         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10337         if (ret) {
10338                 PMD_INIT_LOG(ERR,
10339                         "AQ command Config VSI BW allocation per TC failed = %d",
10340                         hw->aq.asq_last_status);
10341                 goto out;
10342         }
10343         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10344                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10345
10346         /* Update Queue Pairs Mapping for currently enabled UPs */
10347         ctxt.seid = vsi->seid;
10348         ctxt.pf_num = hw->pf_id;
10349         ctxt.vf_num = 0;
10350         ctxt.uplink_seid = vsi->uplink_seid;
10351         ctxt.info = vsi->info;
10352         i40e_get_cap(hw);
10353         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10354         if (ret)
10355                 goto out;
10356
10357         /* Update the VSI after updating the VSI queue-mapping information */
10358         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10359         if (ret) {
10360                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10361                         hw->aq.asq_last_status);
10362                 goto out;
10363         }
10364         /* update the local VSI info with updated queue map */
10365         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10366                                         sizeof(vsi->info.tc_mapping));
10367         rte_memcpy(&vsi->info.queue_mapping,
10368                         &ctxt.info.queue_mapping,
10369                 sizeof(vsi->info.queue_mapping));
10370         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10371         vsi->info.valid_sections = 0;
10372
10373         /* query and update current VSI BW information */
10374         ret = i40e_vsi_get_bw_config(vsi);
10375         if (ret) {
10376                 PMD_INIT_LOG(ERR,
10377                          "Failed updating vsi bw info, err %s aq_err %s",
10378                          i40e_stat_str(hw, ret),
10379                          i40e_aq_str(hw, hw->aq.asq_last_status));
10380                 goto out;
10381         }
10382
10383         vsi->enabled_tc = tc_map;
10384
10385 out:
10386         return ret;
10387 }
10388
10389 /*
10390  * i40e_dcb_hw_configure - program the dcb setting to hw
10391  * @pf: pf the configuration is taken on
10392  * @new_cfg: new configuration
10393  * @tc_map: enabled TC bitmap
10394  *
10395  * Returns 0 on success, negative value on failure
10396  */
10397 static enum i40e_status_code
10398 i40e_dcb_hw_configure(struct i40e_pf *pf,
10399                       struct i40e_dcbx_config *new_cfg,
10400                       uint8_t tc_map)
10401 {
10402         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10403         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10404         struct i40e_vsi *main_vsi = pf->main_vsi;
10405         struct i40e_vsi_list *vsi_list;
10406         enum i40e_status_code ret;
10407         int i;
10408         uint32_t val;
10409
10410         /* Use the FW API if FW > v4.4*/
10411         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10412               (hw->aq.fw_maj_ver >= 5))) {
10413                 PMD_INIT_LOG(ERR,
10414                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10415                 return I40E_ERR_FIRMWARE_API_VERSION;
10416         }
10417
10418         /* Check if need reconfiguration */
10419         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10420                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10421                 return I40E_SUCCESS;
10422         }
10423
10424         /* Copy the new config to the current config */
10425         *old_cfg = *new_cfg;
10426         old_cfg->etsrec = old_cfg->etscfg;
10427         ret = i40e_set_dcb_config(hw);
10428         if (ret) {
10429                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10430                          i40e_stat_str(hw, ret),
10431                          i40e_aq_str(hw, hw->aq.asq_last_status));
10432                 return ret;
10433         }
10434         /* set receive Arbiter to RR mode and ETS scheme by default */
10435         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10436                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10437                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10438                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10439                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10440                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10441                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10442                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10443                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10444                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10445                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10446                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10447                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10448         }
10449         /* get local mib to check whether it is configured correctly */
10450         /* IEEE mode */
10451         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10452         /* Get Local DCB Config */
10453         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10454                                      &hw->local_dcbx_config);
10455
10456         /* if Veb is created, need to update TC of it at first */
10457         if (main_vsi->veb) {
10458                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10459                 if (ret)
10460                         PMD_INIT_LOG(WARNING,
10461                                  "Failed configuring TC for VEB seid=%d",
10462                                  main_vsi->veb->seid);
10463         }
10464         /* Update each VSI */
10465         i40e_vsi_config_tc(main_vsi, tc_map);
10466         if (main_vsi->veb) {
10467                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10468                         /* Beside main VSI and VMDQ VSIs, only enable default
10469                          * TC for other VSIs
10470                          */
10471                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10472                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10473                                                          tc_map);
10474                         else
10475                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10476                                                          I40E_DEFAULT_TCMAP);
10477                         if (ret)
10478                                 PMD_INIT_LOG(WARNING,
10479                                         "Failed configuring TC for VSI seid=%d",
10480                                         vsi_list->vsi->seid);
10481                         /* continue */
10482                 }
10483         }
10484         return I40E_SUCCESS;
10485 }
10486
10487 /*
10488  * i40e_dcb_init_configure - initial dcb config
10489  * @dev: device being configured
10490  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10491  *
10492  * Returns 0 on success, negative value on failure
10493  */
10494 int
10495 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10496 {
10497         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10498         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10499         int i, ret = 0;
10500
10501         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10502                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10503                 return -ENOTSUP;
10504         }
10505
10506         /* DCB initialization:
10507          * Update DCB configuration from the Firmware and configure
10508          * LLDP MIB change event.
10509          */
10510         if (sw_dcb == TRUE) {
10511                 ret = i40e_init_dcb(hw);
10512                 /* If lldp agent is stopped, the return value from
10513                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10514                  * adminq status. Otherwise, it should return success.
10515                  */
10516                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10517                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10518                         memset(&hw->local_dcbx_config, 0,
10519                                 sizeof(struct i40e_dcbx_config));
10520                         /* set dcb default configuration */
10521                         hw->local_dcbx_config.etscfg.willing = 0;
10522                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10523                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10524                         hw->local_dcbx_config.etscfg.tsatable[0] =
10525                                                 I40E_IEEE_TSA_ETS;
10526                         /* all UPs mapping to TC0 */
10527                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10528                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10529                         hw->local_dcbx_config.etsrec =
10530                                 hw->local_dcbx_config.etscfg;
10531                         hw->local_dcbx_config.pfc.willing = 0;
10532                         hw->local_dcbx_config.pfc.pfccap =
10533                                                 I40E_MAX_TRAFFIC_CLASS;
10534                         /* FW needs one App to configure HW */
10535                         hw->local_dcbx_config.numapps = 1;
10536                         hw->local_dcbx_config.app[0].selector =
10537                                                 I40E_APP_SEL_ETHTYPE;
10538                         hw->local_dcbx_config.app[0].priority = 3;
10539                         hw->local_dcbx_config.app[0].protocolid =
10540                                                 I40E_APP_PROTOID_FCOE;
10541                         ret = i40e_set_dcb_config(hw);
10542                         if (ret) {
10543                                 PMD_INIT_LOG(ERR,
10544                                         "default dcb config fails. err = %d, aq_err = %d.",
10545                                         ret, hw->aq.asq_last_status);
10546                                 return -ENOSYS;
10547                         }
10548                 } else {
10549                         PMD_INIT_LOG(ERR,
10550                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10551                                 ret, hw->aq.asq_last_status);
10552                         return -ENOTSUP;
10553                 }
10554         } else {
10555                 ret = i40e_aq_start_lldp(hw, NULL);
10556                 if (ret != I40E_SUCCESS)
10557                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10558
10559                 ret = i40e_init_dcb(hw);
10560                 if (!ret) {
10561                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10562                                 PMD_INIT_LOG(ERR,
10563                                         "HW doesn't support DCBX offload.");
10564                                 return -ENOTSUP;
10565                         }
10566                 } else {
10567                         PMD_INIT_LOG(ERR,
10568                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10569                                 ret, hw->aq.asq_last_status);
10570                         return -ENOTSUP;
10571                 }
10572         }
10573         return 0;
10574 }
10575
10576 /*
10577  * i40e_dcb_setup - setup dcb related config
10578  * @dev: device being configured
10579  *
10580  * Returns 0 on success, negative value on failure
10581  */
10582 static int
10583 i40e_dcb_setup(struct rte_eth_dev *dev)
10584 {
10585         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10586         struct i40e_dcbx_config dcb_cfg;
10587         uint8_t tc_map = 0;
10588         int ret = 0;
10589
10590         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10591                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10592                 return -ENOTSUP;
10593         }
10594
10595         if (pf->vf_num != 0)
10596                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10597
10598         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10599         if (ret) {
10600                 PMD_INIT_LOG(ERR, "invalid dcb config");
10601                 return -EINVAL;
10602         }
10603         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10604         if (ret) {
10605                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10606                 return -ENOSYS;
10607         }
10608
10609         return 0;
10610 }
10611
10612 static int
10613 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10614                       struct rte_eth_dcb_info *dcb_info)
10615 {
10616         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10617         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10618         struct i40e_vsi *vsi = pf->main_vsi;
10619         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10620         uint16_t bsf, tc_mapping;
10621         int i, j = 0;
10622
10623         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10624                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10625         else
10626                 dcb_info->nb_tcs = 1;
10627         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10628                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10629         for (i = 0; i < dcb_info->nb_tcs; i++)
10630                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10631
10632         /* get queue mapping if vmdq is disabled */
10633         if (!pf->nb_cfg_vmdq_vsi) {
10634                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10635                         if (!(vsi->enabled_tc & (1 << i)))
10636                                 continue;
10637                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10638                         dcb_info->tc_queue.tc_rxq[j][i].base =
10639                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10640                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10641                         dcb_info->tc_queue.tc_txq[j][i].base =
10642                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10643                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10644                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10645                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10646                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10647                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10648                 }
10649                 return 0;
10650         }
10651
10652         /* get queue mapping if vmdq is enabled */
10653         do {
10654                 vsi = pf->vmdq[j].vsi;
10655                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10656                         if (!(vsi->enabled_tc & (1 << i)))
10657                                 continue;
10658                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10659                         dcb_info->tc_queue.tc_rxq[j][i].base =
10660                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10661                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10662                         dcb_info->tc_queue.tc_txq[j][i].base =
10663                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10664                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10665                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10666                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10667                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10668                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10669                 }
10670                 j++;
10671         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10672         return 0;
10673 }
10674
10675 static int
10676 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10677 {
10678         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10679         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10680         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10681         uint16_t interval =
10682                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10683         uint16_t msix_intr;
10684
10685         msix_intr = intr_handle->intr_vec[queue_id];
10686         if (msix_intr == I40E_MISC_VEC_ID)
10687                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10688                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10689                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10690                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10691                                (interval <<
10692                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10693         else
10694                 I40E_WRITE_REG(hw,
10695                                I40E_PFINT_DYN_CTLN(msix_intr -
10696                                                    I40E_RX_VEC_START),
10697                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10698                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10699                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10700                                (interval <<
10701                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10702
10703         I40E_WRITE_FLUSH(hw);
10704         rte_intr_enable(&pci_dev->intr_handle);
10705
10706         return 0;
10707 }
10708
10709 static int
10710 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10711 {
10712         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10713         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10714         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10715         uint16_t msix_intr;
10716
10717         msix_intr = intr_handle->intr_vec[queue_id];
10718         if (msix_intr == I40E_MISC_VEC_ID)
10719                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10720         else
10721                 I40E_WRITE_REG(hw,
10722                                I40E_PFINT_DYN_CTLN(msix_intr -
10723                                                    I40E_RX_VEC_START),
10724                                0);
10725         I40E_WRITE_FLUSH(hw);
10726
10727         return 0;
10728 }
10729
10730 static int i40e_get_regs(struct rte_eth_dev *dev,
10731                          struct rte_dev_reg_info *regs)
10732 {
10733         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10734         uint32_t *ptr_data = regs->data;
10735         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10736         const struct i40e_reg_info *reg_info;
10737
10738         if (ptr_data == NULL) {
10739                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10740                 regs->width = sizeof(uint32_t);
10741                 return 0;
10742         }
10743
10744         /* The first few registers have to be read using AQ operations */
10745         reg_idx = 0;
10746         while (i40e_regs_adminq[reg_idx].name) {
10747                 reg_info = &i40e_regs_adminq[reg_idx++];
10748                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10749                         for (arr_idx2 = 0;
10750                                         arr_idx2 <= reg_info->count2;
10751                                         arr_idx2++) {
10752                                 reg_offset = arr_idx * reg_info->stride1 +
10753                                         arr_idx2 * reg_info->stride2;
10754                                 reg_offset += reg_info->base_addr;
10755                                 ptr_data[reg_offset >> 2] =
10756                                         i40e_read_rx_ctl(hw, reg_offset);
10757                         }
10758         }
10759
10760         /* The remaining registers can be read using primitives */
10761         reg_idx = 0;
10762         while (i40e_regs_others[reg_idx].name) {
10763                 reg_info = &i40e_regs_others[reg_idx++];
10764                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10765                         for (arr_idx2 = 0;
10766                                         arr_idx2 <= reg_info->count2;
10767                                         arr_idx2++) {
10768                                 reg_offset = arr_idx * reg_info->stride1 +
10769                                         arr_idx2 * reg_info->stride2;
10770                                 reg_offset += reg_info->base_addr;
10771                                 ptr_data[reg_offset >> 2] =
10772                                         I40E_READ_REG(hw, reg_offset);
10773                         }
10774         }
10775
10776         return 0;
10777 }
10778
10779 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10780 {
10781         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10782
10783         /* Convert word count to byte count */
10784         return hw->nvm.sr_size << 1;
10785 }
10786
10787 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10788                            struct rte_dev_eeprom_info *eeprom)
10789 {
10790         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10791         uint16_t *data = eeprom->data;
10792         uint16_t offset, length, cnt_words;
10793         int ret_code;
10794
10795         offset = eeprom->offset >> 1;
10796         length = eeprom->length >> 1;
10797         cnt_words = length;
10798
10799         if (offset > hw->nvm.sr_size ||
10800                 offset + length > hw->nvm.sr_size) {
10801                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10802                 return -EINVAL;
10803         }
10804
10805         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10806
10807         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10808         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10809                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10810                 return -EIO;
10811         }
10812
10813         return 0;
10814 }
10815
10816 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10817                                       struct ether_addr *mac_addr)
10818 {
10819         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10820
10821         if (!is_valid_assigned_ether_addr(mac_addr)) {
10822                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10823                 return;
10824         }
10825
10826         /* Flags: 0x3 updates port address */
10827         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10828 }
10829
10830 static int
10831 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10832 {
10833         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10834         struct rte_eth_dev_data *dev_data = pf->dev_data;
10835         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10836         int ret = 0;
10837
10838         /* check if mtu is within the allowed range */
10839         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10840                 return -EINVAL;
10841
10842         /* mtu setting is forbidden if port is start */
10843         if (dev_data->dev_started) {
10844                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10845                             dev_data->port_id);
10846                 return -EBUSY;
10847         }
10848
10849         if (frame_size > ETHER_MAX_LEN)
10850                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10851         else
10852                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10853
10854         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10855
10856         return ret;
10857 }
10858
10859 /* Restore ethertype filter */
10860 static void
10861 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10862 {
10863         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10864         struct i40e_ethertype_filter_list
10865                 *ethertype_list = &pf->ethertype.ethertype_list;
10866         struct i40e_ethertype_filter *f;
10867         struct i40e_control_filter_stats stats;
10868         uint16_t flags;
10869
10870         TAILQ_FOREACH(f, ethertype_list, rules) {
10871                 flags = 0;
10872                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10873                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10874                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10875                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10876                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10877
10878                 memset(&stats, 0, sizeof(stats));
10879                 i40e_aq_add_rem_control_packet_filter(hw,
10880                                             f->input.mac_addr.addr_bytes,
10881                                             f->input.ether_type,
10882                                             flags, pf->main_vsi->seid,
10883                                             f->queue, 1, &stats, NULL);
10884         }
10885         PMD_DRV_LOG(INFO, "Ethertype filter:"
10886                     " mac_etype_used = %u, etype_used = %u,"
10887                     " mac_etype_free = %u, etype_free = %u",
10888                     stats.mac_etype_used, stats.etype_used,
10889                     stats.mac_etype_free, stats.etype_free);
10890 }
10891
10892 /* Restore tunnel filter */
10893 static void
10894 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10895 {
10896         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10897         struct i40e_vsi *vsi;
10898         struct i40e_pf_vf *vf;
10899         struct i40e_tunnel_filter_list
10900                 *tunnel_list = &pf->tunnel.tunnel_list;
10901         struct i40e_tunnel_filter *f;
10902         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10903         bool big_buffer = 0;
10904
10905         TAILQ_FOREACH(f, tunnel_list, rules) {
10906                 if (!f->is_to_vf)
10907                         vsi = pf->main_vsi;
10908                 else {
10909                         vf = &pf->vfs[f->vf_id];
10910                         vsi = vf->vsi;
10911                 }
10912                 memset(&cld_filter, 0, sizeof(cld_filter));
10913                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10914                         (struct ether_addr *)&cld_filter.element.outer_mac);
10915                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10916                         (struct ether_addr *)&cld_filter.element.inner_mac);
10917                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10918                 cld_filter.element.flags = f->input.flags;
10919                 cld_filter.element.tenant_id = f->input.tenant_id;
10920                 cld_filter.element.queue_number = f->queue;
10921                 rte_memcpy(cld_filter.general_fields,
10922                            f->input.general_fields,
10923                            sizeof(f->input.general_fields));
10924
10925                 if (((f->input.flags &
10926                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
10927                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
10928                     ((f->input.flags &
10929                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
10930                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
10931                     ((f->input.flags &
10932                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
10933                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
10934                         big_buffer = 1;
10935
10936                 if (big_buffer)
10937                         i40e_aq_add_cloud_filters_big_buffer(hw,
10938                                              vsi->seid, &cld_filter, 1);
10939                 else
10940                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10941                                                   &cld_filter.element, 1);
10942         }
10943 }
10944
10945 static void
10946 i40e_filter_restore(struct i40e_pf *pf)
10947 {
10948         i40e_ethertype_filter_restore(pf);
10949         i40e_tunnel_filter_restore(pf);
10950         i40e_fdir_filter_restore(pf);
10951 }
10952
10953 static bool
10954 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10955 {
10956         if (strcmp(dev->device->driver->name, drv->driver.name))
10957                 return false;
10958
10959         return true;
10960 }
10961
10962 bool
10963 is_i40e_supported(struct rte_eth_dev *dev)
10964 {
10965         return is_device_supported(dev, &rte_i40e_pmd);
10966 }
10967
10968 struct i40e_customized_pctype*
10969 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
10970 {
10971         int i;
10972
10973         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
10974                 if (pf->customized_pctype[i].index == index)
10975                         return &pf->customized_pctype[i];
10976         }
10977         return NULL;
10978 }
10979
10980 static int
10981 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
10982                               uint32_t pkg_size, uint32_t proto_num,
10983                               struct rte_pmd_i40e_proto_info *proto)
10984 {
10985         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10986         uint32_t pctype_num;
10987         struct rte_pmd_i40e_ptype_info *pctype;
10988         uint32_t buff_size;
10989         struct i40e_customized_pctype *new_pctype = NULL;
10990         uint8_t proto_id;
10991         uint8_t pctype_value;
10992         char name[64];
10993         uint32_t i, j, n;
10994         int ret;
10995
10996         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
10997                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
10998                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
10999         if (ret) {
11000                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11001                 return -1;
11002         }
11003         if (!pctype_num) {
11004                 PMD_DRV_LOG(INFO, "No new pctype added");
11005                 return -1;
11006         }
11007
11008         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11009         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11010         if (!pctype) {
11011                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11012                 return -1;
11013         }
11014         /* get information about new pctype list */
11015         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11016                                         (uint8_t *)pctype, buff_size,
11017                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11018         if (ret) {
11019                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11020                 rte_free(pctype);
11021                 return -1;
11022         }
11023
11024         /* Update customized pctype. */
11025         for (i = 0; i < pctype_num; i++) {
11026                 pctype_value = pctype[i].ptype_id;
11027                 memset(name, 0, sizeof(name));
11028                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11029                         proto_id = pctype[i].protocols[j];
11030                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11031                                 continue;
11032                         for (n = 0; n < proto_num; n++) {
11033                                 if (proto[n].proto_id != proto_id)
11034                                         continue;
11035                                 strcat(name, proto[n].name);
11036                                 strcat(name, "_");
11037                                 break;
11038                         }
11039                 }
11040                 name[strlen(name) - 1] = '\0';
11041                 if (!strcmp(name, "GTPC"))
11042                         new_pctype =
11043                                 i40e_find_customized_pctype(pf,
11044                                                       I40E_CUSTOMIZED_GTPC);
11045                 else if (!strcmp(name, "GTPU_IPV4"))
11046                         new_pctype =
11047                                 i40e_find_customized_pctype(pf,
11048                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11049                 else if (!strcmp(name, "GTPU_IPV6"))
11050                         new_pctype =
11051                                 i40e_find_customized_pctype(pf,
11052                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11053                 else if (!strcmp(name, "GTPU"))
11054                         new_pctype =
11055                                 i40e_find_customized_pctype(pf,
11056                                                       I40E_CUSTOMIZED_GTPU);
11057                 if (new_pctype) {
11058                         new_pctype->pctype = pctype_value;
11059                         new_pctype->valid = true;
11060                 }
11061         }
11062
11063         rte_free(pctype);
11064         return 0;
11065 }
11066
11067 static int
11068 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11069                                uint32_t pkg_size, uint32_t proto_num,
11070                                struct rte_pmd_i40e_proto_info *proto)
11071 {
11072         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11073         uint16_t port_id = dev->data->port_id;
11074         uint32_t ptype_num;
11075         struct rte_pmd_i40e_ptype_info *ptype;
11076         uint32_t buff_size;
11077         uint8_t proto_id;
11078         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11079         uint32_t i, j, n;
11080         bool inner_ip;
11081         int ret;
11082
11083         /* get information about new ptype num */
11084         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11085                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11086                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11087         if (ret) {
11088                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11089                 return ret;
11090         }
11091         if (!ptype_num) {
11092                 PMD_DRV_LOG(INFO, "No new ptype added");
11093                 return -1;
11094         }
11095
11096         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11097         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11098         if (!ptype) {
11099                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11100                 return -1;
11101         }
11102
11103         /* get information about new ptype list */
11104         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11105                                         (uint8_t *)ptype, buff_size,
11106                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11107         if (ret) {
11108                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11109                 rte_free(ptype);
11110                 return ret;
11111         }
11112
11113         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11114         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11115         if (!ptype_mapping) {
11116                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11117                 rte_free(ptype);
11118                 return -1;
11119         }
11120
11121         /* Update ptype mapping table. */
11122         for (i = 0; i < ptype_num; i++) {
11123                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11124                 ptype_mapping[i].sw_ptype = 0;
11125                 inner_ip = false;
11126                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11127                         proto_id = ptype[i].protocols[j];
11128                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11129                                 continue;
11130                         for (n = 0; n < proto_num; n++) {
11131                                 if (proto[n].proto_id != proto_id)
11132                                         continue;
11133                                 memset(name, 0, sizeof(name));
11134                                 strcpy(name, proto[n].name);
11135                                 if (!strncmp(name, "IPV4", 4) && !inner_ip) {
11136                                         ptype_mapping[i].sw_ptype |=
11137                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11138                                         inner_ip = true;
11139                                 } else if (!strncmp(name, "IPV4FRAG", 8) &&
11140                                            inner_ip) {
11141                                         ptype_mapping[i].sw_ptype |=
11142                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11143                                         ptype_mapping[i].sw_ptype |=
11144                                                 RTE_PTYPE_INNER_L4_FRAG;
11145                                 } else if (!strncmp(name, "IPV4", 4) &&
11146                                            inner_ip)
11147                                         ptype_mapping[i].sw_ptype |=
11148                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11149                                 else if (!strncmp(name, "IPV6", 4) &&
11150                                          !inner_ip) {
11151                                         ptype_mapping[i].sw_ptype |=
11152                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11153                                         inner_ip = true;
11154                                 } else if (!strncmp(name, "IPV6FRAG", 8) &&
11155                                            inner_ip) {
11156                                         ptype_mapping[i].sw_ptype |=
11157                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11158                                         ptype_mapping[i].sw_ptype |=
11159                                                 RTE_PTYPE_INNER_L4_FRAG;
11160                                 } else if (!strncmp(name, "IPV6", 4) &&
11161                                            inner_ip)
11162                                         ptype_mapping[i].sw_ptype |=
11163                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11164                                 else if (!strncmp(name, "GTPC", 4))
11165                                         ptype_mapping[i].sw_ptype |=
11166                                                 RTE_PTYPE_TUNNEL_GTPC;
11167                                 else if (!strncmp(name, "GTPU", 4))
11168                                         ptype_mapping[i].sw_ptype |=
11169                                                 RTE_PTYPE_TUNNEL_GTPU;
11170                                 else if (!strncmp(name, "UDP", 3))
11171                                         ptype_mapping[i].sw_ptype |=
11172                                                 RTE_PTYPE_INNER_L4_UDP;
11173                                 else if (!strncmp(name, "TCP", 3))
11174                                         ptype_mapping[i].sw_ptype |=
11175                                                 RTE_PTYPE_INNER_L4_TCP;
11176                                 else if (!strncmp(name, "SCTP", 4))
11177                                         ptype_mapping[i].sw_ptype |=
11178                                                 RTE_PTYPE_INNER_L4_SCTP;
11179                                 else if (!strncmp(name, "ICMP", 4) ||
11180                                          !strncmp(name, "ICMPV6", 6))
11181                                         ptype_mapping[i].sw_ptype |=
11182                                                 RTE_PTYPE_INNER_L4_ICMP;
11183
11184                                 break;
11185                         }
11186                 }
11187         }
11188
11189         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11190                                                 ptype_num, 0);
11191         if (ret)
11192                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11193
11194         rte_free(ptype_mapping);
11195         rte_free(ptype);
11196         return ret;
11197 }
11198
11199 void
11200 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11201                               uint32_t pkg_size)
11202 {
11203         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11204         uint32_t proto_num;
11205         struct rte_pmd_i40e_proto_info *proto;
11206         uint32_t buff_size;
11207         uint32_t i;
11208         int ret;
11209
11210         /* get information about protocol number */
11211         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11212                                        (uint8_t *)&proto_num, sizeof(proto_num),
11213                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11214         if (ret) {
11215                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11216                 return;
11217         }
11218         if (!proto_num) {
11219                 PMD_DRV_LOG(INFO, "No new protocol added");
11220                 return;
11221         }
11222
11223         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11224         proto = rte_zmalloc("new_proto", buff_size, 0);
11225         if (!proto) {
11226                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11227                 return;
11228         }
11229
11230         /* get information about protocol list */
11231         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11232                                         (uint8_t *)proto, buff_size,
11233                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11234         if (ret) {
11235                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11236                 rte_free(proto);
11237                 return;
11238         }
11239
11240         /* Check if GTP is supported. */
11241         for (i = 0; i < proto_num; i++) {
11242                 if (!strncmp(proto[i].name, "GTP", 3)) {
11243                         pf->gtp_support = true;
11244                         break;
11245                 }
11246         }
11247
11248         /* Update customized pctype info */
11249         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11250                                             proto_num, proto);
11251         if (ret)
11252                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11253
11254         /* Update customized ptype info */
11255         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11256                                            proto_num, proto);
11257         if (ret)
11258                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11259
11260         rte_free(proto);
11261 }
11262
11263 /* Create a QinQ cloud filter
11264  *
11265  * The Fortville NIC has limited resources for tunnel filters,
11266  * so we can only reuse existing filters.
11267  *
11268  * In step 1 we define which Field Vector fields can be used for
11269  * filter types.
11270  * As we do not have the inner tag defined as a field,
11271  * we have to define it first, by reusing one of L1 entries.
11272  *
11273  * In step 2 we are replacing one of existing filter types with
11274  * a new one for QinQ.
11275  * As we reusing L1 and replacing L2, some of the default filter
11276  * types will disappear,which depends on L1 and L2 entries we reuse.
11277  *
11278  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11279  *
11280  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11281  *              later when we define the cloud filter.
11282  *      a.      Valid_flags.replace_cloud = 0
11283  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11284  *      c.      New_filter = 0x10
11285  *      d.      TR bit = 0xff (optional, not used here)
11286  *      e.      Buffer – 2 entries:
11287  *              i.      Byte 0 = 8 (outer vlan FV index).
11288  *                      Byte 1 = 0 (rsv)
11289  *                      Byte 2-3 = 0x0fff
11290  *              ii.     Byte 0 = 37 (inner vlan FV index).
11291  *                      Byte 1 =0 (rsv)
11292  *                      Byte 2-3 = 0x0fff
11293  *
11294  * Step 2:
11295  * 2.   Create cloud filter using two L1 filters entries: stag and
11296  *              new filter(outer vlan+ inner vlan)
11297  *      a.      Valid_flags.replace_cloud = 1
11298  *      b.      Old_filter = 1 (instead of outer IP)
11299  *      c.      New_filter = 0x10
11300  *      d.      Buffer – 2 entries:
11301  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11302  *                      Byte 1-3 = 0 (rsv)
11303  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11304  *                      Byte 9-11 = 0 (rsv)
11305  */
11306 static int
11307 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11308 {
11309         int ret = -ENOTSUP;
11310         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11311         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11312         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11313
11314         /* Init */
11315         memset(&filter_replace, 0,
11316                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11317         memset(&filter_replace_buf, 0,
11318                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11319
11320         /* create L1 filter */
11321         filter_replace.old_filter_type =
11322                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11323         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11324         filter_replace.tr_bit = 0;
11325
11326         /* Prepare the buffer, 2 entries */
11327         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11328         filter_replace_buf.data[0] |=
11329                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11330         /* Field Vector 12b mask */
11331         filter_replace_buf.data[2] = 0xff;
11332         filter_replace_buf.data[3] = 0x0f;
11333         filter_replace_buf.data[4] =
11334                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11335         filter_replace_buf.data[4] |=
11336                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11337         /* Field Vector 12b mask */
11338         filter_replace_buf.data[6] = 0xff;
11339         filter_replace_buf.data[7] = 0x0f;
11340         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11341                         &filter_replace_buf);
11342         if (ret != I40E_SUCCESS)
11343                 return ret;
11344
11345         /* Apply the second L2 cloud filter */
11346         memset(&filter_replace, 0,
11347                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11348         memset(&filter_replace_buf, 0,
11349                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11350
11351         /* create L2 filter, input for L2 filter will be L1 filter  */
11352         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11353         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11354         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11355
11356         /* Prepare the buffer, 2 entries */
11357         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11358         filter_replace_buf.data[0] |=
11359                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11360         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11361         filter_replace_buf.data[4] |=
11362                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11363         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11364                         &filter_replace_buf);
11365         return ret;
11366 }
11367
11368 RTE_INIT(i40e_init_log);
11369 static void
11370 i40e_init_log(void)
11371 {
11372         i40e_logtype_init = rte_log_register("pmd.i40e.init");
11373         if (i40e_logtype_init >= 0)
11374                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11375         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11376         if (i40e_logtype_driver >= 0)
11377                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
11378 }