drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68 #include "rte_pmd_i40e.h"
  69
  70 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  71 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  72
  73 #define I40E_CLEAR_PXE_WAIT_MS     200
  74
  75 /* Maximun number of capability elements */
  76 #define I40E_MAX_CAP_ELE_NUM       128
  77
  78 /* Wait count and interval */
  79 #define I40E_CHK_Q_ENA_COUNT       1000
  80 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  81
  82 /* Maximun number of VSI */
  83 #define I40E_MAX_NUM_VSIS          (384UL)
  84
  85 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  86
  87 /* Flow control default timer */
  88 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  89
  90 /* Flow control enable fwd bit */
  91 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  92
  93 /* Receive Packet Buffer size */
  94 #define I40E_RXPBSIZE (968 * 1024)
  95
  96 /* Kilobytes shift */
  97 #define I40E_KILOSHIFT 10
  98
  99 /* Flow control default high water */
 100 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
 101
 102 /* Flow control default low water */
 103 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
 104
 105 /* Receive Average Packet Size in Byte*/
 106 #define I40E_PACKET_AVERAGE_SIZE 128
 107
 108 /* Mask of PF interrupt causes */
 109 #define I40E_PFINT_ICR0_ENA_MASK ( \
 110                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 112                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 114                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 115                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 118                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 119
 120 #define I40E_FLOW_TYPES ( \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 130         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 131         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 132
 133 /* Additional timesync values. */
 134 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 135 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 136 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 137 #define I40E_PRTTSYN_TSYNENA     0x80000000
 138 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 139 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 /**
 142  * Below are values for writing un-exposed registers suggested
 143  * by silicon experts
 144  */
 145 /* Destination MAC address */
 146 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 147 /* Source MAC address */
 148 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 149 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 150 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 151 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 152 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 153 /* Single VLAN tag in the inner L2 header */
 154 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 155 /* Source IPv4 address */
 156 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 157 /* Destination IPv4 address */
 158 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 159 /* Source IPv4 address for X722 */
 160 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 161 /* Destination IPv4 address for X722 */
 162 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 163 /* IPv4 Protocol for X722 */
 164 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 165 /* IPv4 Time to Live for X722 */
 166 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 167 /* IPv4 Type of Service (TOS) */
 168 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 169 /* IPv4 Protocol */
 170 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 171 /* IPv4 Time to Live */
 172 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 173 /* Source IPv6 address */
 174 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 175 /* Destination IPv6 address */
 176 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 177 /* IPv6 Traffic Class (TC) */
 178 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 179 /* IPv6 Next Header */
 180 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 181 /* IPv6 Hop Limit */
 182 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 183 /* Source L4 port */
 184 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 185 /* Destination L4 port */
 186 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 187 /* SCTP verification tag */
 188 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 189 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 190 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 191 /* Source port of tunneling UDP */
 192 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 193 /* Destination port of tunneling UDP */
 194 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 195 /* UDP Tunneling ID, NVGRE/GRE key */
 196 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 197 /* Last ether type */
 198 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 199 /* Tunneling outer destination IPv4 address */
 200 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 201 /* Tunneling outer destination IPv6 address */
 202 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 203 /* 1st word of flex payload */
 204 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 205 /* 2nd word of flex payload */
 206 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 207 /* 3rd word of flex payload */
 208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 209 /* 4th word of flex payload */
 210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 211 /* 5th word of flex payload */
 212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 213 /* 6th word of flex payload */
 214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 215 /* 7th word of flex payload */
 216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 217 /* 8th word of flex payload */
 218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 219 /* all 8 words flex payload */
 220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 221 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 222
 223 #define I40E_TRANSLATE_INSET 0
 224 #define I40E_TRANSLATE_REG   1
 225
 226 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 227 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 228 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 229 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 230 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 231 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 232
 233 /* PCI offset for querying capability */
 234 #define PCI_DEV_CAP_REG            0xA4
 235 /* PCI offset for enabling/disabling Extended Tag */
 236 #define PCI_DEV_CTRL_REG           0xA8
 237 /* Bit mask of Extended Tag capability */
 238 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 239 /* Bit shift of Extended Tag enable/disable */
 240 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 241 /* Bit mask of Extended Tag enable/disable */
 242 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 243
 244 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 245 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 246 static int i40e_dev_configure(struct rte_eth_dev *dev);
 247 static int i40e_dev_start(struct rte_eth_dev *dev);
 248 static void i40e_dev_stop(struct rte_eth_dev *dev);
 249 static void i40e_dev_close(struct rte_eth_dev *dev);
 250 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 251 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 252 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 253 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 254 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 255 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 256 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 257 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 258                                struct rte_eth_stats *stats);
 259 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 260                                struct rte_eth_xstat *xstats, unsigned n);
 261 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 262                                      struct rte_eth_xstat_name *xstats_names,
 263                                      unsigned limit);
 264 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 265 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 266                                             uint16_t queue_id,
 267                                             uint8_t stat_idx,
 268                                             uint8_t is_rx);
 269 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 270                                 char *fw_version, size_t fw_size);
 271 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 272                               struct rte_eth_dev_info *dev_info);
 273 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 274                                 uint16_t vlan_id,
 275                                 int on);
 276 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 277                               enum rte_vlan_type vlan_type,
 278                               uint16_t tpid);
 279 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 280 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 281                                       uint16_t queue,
 282                                       int on);
 283 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 284 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 285 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 286 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 287                               struct rte_eth_fc_conf *fc_conf);
 288 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 289                               struct rte_eth_fc_conf *fc_conf);
 290 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 291                                        struct rte_eth_pfc_conf *pfc_conf);
 292 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 293                             struct ether_addr *mac_addr,
 294                             uint32_t index,
 295                             uint32_t pool);
 296 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 297 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 298                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 299                                     uint16_t reta_size);
 300 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 301                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 302                                    uint16_t reta_size);
 303
 304 static int i40e_get_cap(struct i40e_hw *hw);
 305 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 306 static int i40e_pf_setup(struct i40e_pf *pf);
 307 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 308 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 309 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 310 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 311                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 312 static void i40e_stat_update_48(struct i40e_hw *hw,
 313                                uint32_t hireg,
 314                                uint32_t loreg,
 315                                bool offset_loaded,
 316                                uint64_t *offset,
 317                                uint64_t *stat);
 318 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 319 static void i40e_dev_interrupt_handler(void *param);
 320 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 321                                 uint32_t base, uint32_t num);
 322 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 323 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 324                         uint32_t base);
 325 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 326                         uint16_t num);
 327 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 328 static int i40e_veb_release(struct i40e_veb *veb);
 329 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 330                                                 struct i40e_vsi *vsi);
 331 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 332 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 333 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 334                                              struct i40e_macvlan_filter *mv_f,
 335                                              int num,
 336                                              uint16_t vlan);
 337 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 338 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 339                                     struct rte_eth_rss_conf *rss_conf);
 340 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 341                                       struct rte_eth_rss_conf *rss_conf);
 342 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 343                                         struct rte_eth_udp_tunnel *udp_tunnel);
 344 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 345                                         struct rte_eth_udp_tunnel *udp_tunnel);
 346 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 347 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 348                                 enum rte_filter_op filter_op,
 349                                 void *arg);
 350 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 351                                 enum rte_filter_type filter_type,
 352                                 enum rte_filter_op filter_op,
 353                                 void *arg);
 354 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 355                                   struct rte_eth_dcb_info *dcb_info);
 356 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 357 static void i40e_configure_registers(struct i40e_hw *hw);
 358 static void i40e_hw_init(struct rte_eth_dev *dev);
 359 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 360 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 361                                                      uint16_t seid,
 362                                                      uint16_t rule_type,
 363                                                      uint16_t *entries,
 364                                                      uint16_t count,
 365                                                      uint16_t rule_id);
 366 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 367                         struct rte_eth_mirror_conf *mirror_conf,
 368                         uint8_t sw_id, uint8_t on);
 369 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 370
 371 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 372 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 373 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 374                                            struct timespec *timestamp,
 375                                            uint32_t flags);
 376 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 377                                            struct timespec *timestamp);
 378 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 379
 380 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 381
 382 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 383                                    struct timespec *timestamp);
 384 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 385                                     const struct timespec *timestamp);
 386
 387 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 388                                          uint16_t queue_id);
 389 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 390                                           uint16_t queue_id);
 391
 392 static int i40e_get_regs(struct rte_eth_dev *dev,
 393                          struct rte_dev_reg_info *regs);
 394
 395 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 396
 397 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 398                            struct rte_dev_eeprom_info *eeprom);
 399
 400 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 401                                       struct ether_addr *mac_addr);
 402
 403 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 404
 405 static int i40e_ethertype_filter_convert(
 406         const struct rte_eth_ethertype_filter *input,
 407         struct i40e_ethertype_filter *filter);
 408 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 409                                    struct i40e_ethertype_filter *filter);
 410
 411 static int i40e_tunnel_filter_convert(
 412         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 413         struct i40e_tunnel_filter *tunnel_filter);
 414 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 415                                 struct i40e_tunnel_filter *tunnel_filter);
 416 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 417
 418 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 419 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 420 static void i40e_filter_restore(struct i40e_pf *pf);
 421 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 422
 423 int i40e_logtype_init;
 424 int i40e_logtype_driver;
 425
 426 static const struct rte_pci_id pci_id_i40e_map[] = {
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 445         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 446         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 447         { .vendor_id = 0, /* sentinel */ },
 448 };
 449
 450 static const struct eth_dev_ops i40e_eth_dev_ops = {
 451         .dev_configure                = i40e_dev_configure,
 452         .dev_start                    = i40e_dev_start,
 453         .dev_stop                     = i40e_dev_stop,
 454         .dev_close                    = i40e_dev_close,
 455         .dev_reset                    = i40e_dev_reset,
 456         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 457         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 458         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 459         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 460         .dev_set_link_up              = i40e_dev_set_link_up,
 461         .dev_set_link_down            = i40e_dev_set_link_down,
 462         .link_update                  = i40e_dev_link_update,
 463         .stats_get                    = i40e_dev_stats_get,
 464         .xstats_get                   = i40e_dev_xstats_get,
 465         .xstats_get_names             = i40e_dev_xstats_get_names,
 466         .stats_reset                  = i40e_dev_stats_reset,
 467         .xstats_reset                 = i40e_dev_stats_reset,
 468         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 469         .fw_version_get               = i40e_fw_version_get,
 470         .dev_infos_get                = i40e_dev_info_get,
 471         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 472         .vlan_filter_set              = i40e_vlan_filter_set,
 473         .vlan_tpid_set                = i40e_vlan_tpid_set,
 474         .vlan_offload_set             = i40e_vlan_offload_set,
 475         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 476         .vlan_pvid_set                = i40e_vlan_pvid_set,
 477         .rx_queue_start               = i40e_dev_rx_queue_start,
 478         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 479         .tx_queue_start               = i40e_dev_tx_queue_start,
 480         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 481         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 482         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 483         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 484         .rx_queue_release             = i40e_dev_rx_queue_release,
 485         .rx_queue_count               = i40e_dev_rx_queue_count,
 486         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 487         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 488         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 489         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 490         .tx_queue_release             = i40e_dev_tx_queue_release,
 491         .dev_led_on                   = i40e_dev_led_on,
 492         .dev_led_off                  = i40e_dev_led_off,
 493         .flow_ctrl_get                = i40e_flow_ctrl_get,
 494         .flow_ctrl_set                = i40e_flow_ctrl_set,
 495         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 496         .mac_addr_add                 = i40e_macaddr_add,
 497         .mac_addr_remove              = i40e_macaddr_remove,
 498         .reta_update                  = i40e_dev_rss_reta_update,
 499         .reta_query                   = i40e_dev_rss_reta_query,
 500         .rss_hash_update              = i40e_dev_rss_hash_update,
 501         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 502         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 503         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 504         .filter_ctrl                  = i40e_dev_filter_ctrl,
 505         .rxq_info_get                 = i40e_rxq_info_get,
 506         .txq_info_get                 = i40e_txq_info_get,
 507         .mirror_rule_set              = i40e_mirror_rule_set,
 508         .mirror_rule_reset            = i40e_mirror_rule_reset,
 509         .timesync_enable              = i40e_timesync_enable,
 510         .timesync_disable             = i40e_timesync_disable,
 511         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 512         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 513         .get_dcb_info                 = i40e_dev_get_dcb_info,
 514         .timesync_adjust_time         = i40e_timesync_adjust_time,
 515         .timesync_read_time           = i40e_timesync_read_time,
 516         .timesync_write_time          = i40e_timesync_write_time,
 517         .get_reg                      = i40e_get_regs,
 518         .get_eeprom_length            = i40e_get_eeprom_length,
 519         .get_eeprom                   = i40e_get_eeprom,
 520         .mac_addr_set                 = i40e_set_default_mac_addr,
 521         .mtu_set                      = i40e_dev_mtu_set,
 522         .tm_ops_get                   = i40e_tm_ops_get,
 523 };
 524
 525 /* store statistics names and its offset in stats structure */
 526 struct rte_i40e_xstats_name_off {
 527         char name[RTE_ETH_XSTATS_NAME_SIZE];
 528         unsigned offset;
 529 };
 530
 531 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 532         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 533         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 534         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 535         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 536         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 537                 rx_unknown_protocol)},
 538         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 539         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 540         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 541         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 542 };
 543
 544 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 545                 sizeof(rte_i40e_stats_strings[0]))
 546
 547 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 548         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 549                 tx_dropped_link_down)},
 550         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 551         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 552                 illegal_bytes)},
 553         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 554         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 555                 mac_local_faults)},
 556         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 557                 mac_remote_faults)},
 558         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 559                 rx_length_errors)},
 560         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 561         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 562         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 563         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 564         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 565         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_127)},
 567         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_255)},
 569         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_511)},
 571         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_1023)},
 573         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 574                 rx_size_1522)},
 575         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 576                 rx_size_big)},
 577         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 578                 rx_undersize)},
 579         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 580                 rx_oversize)},
 581         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 582                 mac_short_packet_dropped)},
 583         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 584                 rx_fragments)},
 585         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 586         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 587         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_127)},
 589         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_255)},
 591         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_511)},
 593         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_1023)},
 595         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 596                 tx_size_1522)},
 597         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 598                 tx_size_big)},
 599         {"rx_flow_director_atr_match_packets",
 600                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 601         {"rx_flow_director_sb_match_packets",
 602                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 603         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 604                 tx_lpi_status)},
 605         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 606                 rx_lpi_status)},
 607         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 608                 tx_lpi_count)},
 609         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 610                 rx_lpi_count)},
 611 };
 612
 613 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 614                 sizeof(rte_i40e_hw_port_strings[0]))
 615
 616 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 617         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 618                 priority_xon_rx)},
 619         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 620                 priority_xoff_rx)},
 621 };
 622
 623 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 624                 sizeof(rte_i40e_rxq_prio_strings[0]))
 625
 626 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 627         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 628                 priority_xon_tx)},
 629         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 630                 priority_xoff_tx)},
 631         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 632                 priority_xon_2_xoff)},
 633 };
 634
 635 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 636                 sizeof(rte_i40e_txq_prio_strings[0]))
 637
 638 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 639         struct rte_pci_device *pci_dev)
 640 {
 641         return rte_eth_dev_pci_generic_probe(pci_dev,
 642                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 643 }
 644
 645 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 646 {
 647         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 648 }
 649
 650 static struct rte_pci_driver rte_i40e_pmd = {
 651         .id_table = pci_id_i40e_map,
 652         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 653                      RTE_PCI_DRV_IOVA_AS_VA,
 654         .probe = eth_i40e_pci_probe,
 655         .remove = eth_i40e_pci_remove,
 656 };
 657
 658 static inline int
 659 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 660                                      struct rte_eth_link *link)
 661 {
 662         struct rte_eth_link *dst = link;
 663         struct rte_eth_link *src = &(dev->data->dev_link);
 664
 665         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 666                                         *(uint64_t *)src) == 0)
 667                 return -1;
 668
 669         return 0;
 670 }
 671
 672 static inline int
 673 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 674                                       struct rte_eth_link *link)
 675 {
 676         struct rte_eth_link *dst = &(dev->data->dev_link);
 677         struct rte_eth_link *src = link;
 678
 679         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 680                                         *(uint64_t *)src) == 0)
 681                 return -1;
 682
 683         return 0;
 684 }
 685
 686 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 687 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 688 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 689
 690 #ifndef I40E_GLQF_ORT
 691 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 692 #endif
 693 #ifndef I40E_GLQF_PIT
 694 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 695 #endif
 696 #ifndef I40E_GLQF_L3_MAP
 697 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 698 #endif
 699
 700 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 701 {
 702         /*
 703          * Force global configuration for flexible payload
 704          * to the first 16 bytes of the corresponding L2/L3/L4 paylod.
 705          * This should be removed from code once proper
 706          * configuration API is added to avoid configuration conflicts
 707          * between ports of the same device.
 708          */
 709         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 710         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 711         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 712
 713         /*
 714          * Initialize registers for parsing packet type of QinQ
 715          * This should be removed from code once proper
 716          * configuration API is added to avoid configuration conflicts
 717          * between ports of the same device.
 718          */
 719         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 720         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 721 }
 722
 723 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 724
 725 /*
 726  * Add a ethertype filter to drop all flow control frames transmitted
 727  * from VSIs.
 728 */
 729 static void
 730 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 731 {
 732         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 733         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 734                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 735                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 736         int ret;
 737
 738         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 739                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 740                                 pf->main_vsi_seid, 0,
 741                                 TRUE, NULL, NULL);
 742         if (ret)
 743                 PMD_INIT_LOG(ERR,
 744                         "Failed to add filter to drop flow control frames from VSIs.");
 745 }
 746
 747 static int
 748 floating_veb_list_handler(__rte_unused const char *key,
 749                           const char *floating_veb_value,
 750                           void *opaque)
 751 {
 752         int idx = 0;
 753         unsigned int count = 0;
 754         char *end = NULL;
 755         int min, max;
 756         bool *vf_floating_veb = opaque;
 757
 758         while (isblank(*floating_veb_value))
 759                 floating_veb_value++;
 760
 761         /* Reset floating VEB configuration for VFs */
 762         for (idx = 0; idx < I40E_MAX_VF; idx++)
 763                 vf_floating_veb[idx] = false;
 764
 765         min = I40E_MAX_VF;
 766         do {
 767                 while (isblank(*floating_veb_value))
 768                         floating_veb_value++;
 769                 if (*floating_veb_value == '\0')
 770                         return -1;
 771                 errno = 0;
 772                 idx = strtoul(floating_veb_value, &end, 10);
 773                 if (errno || end == NULL)
 774                         return -1;
 775                 while (isblank(*end))
 776                         end++;
 777                 if (*end == '-') {
 778                         min = idx;
 779                 } else if ((*end == ';') || (*end == '\0')) {
 780                         max = idx;
 781                         if (min == I40E_MAX_VF)
 782                                 min = idx;
 783                         if (max >= I40E_MAX_VF)
 784                                 max = I40E_MAX_VF - 1;
 785                         for (idx = min; idx <= max; idx++) {
 786                                 vf_floating_veb[idx] = true;
 787                                 count++;
 788                         }
 789                         min = I40E_MAX_VF;
 790                 } else {
 791                         return -1;
 792                 }
 793                 floating_veb_value = end + 1;
 794         } while (*end != '\0');
 795
 796         if (count == 0)
 797                 return -1;
 798
 799         return 0;
 800 }
 801
 802 static void
 803 config_vf_floating_veb(struct rte_devargs *devargs,
 804                        uint16_t floating_veb,
 805                        bool *vf_floating_veb)
 806 {
 807         struct rte_kvargs *kvlist;
 808         int i;
 809         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 810
 811         if (!floating_veb)
 812                 return;
 813         /* All the VFs attach to the floating VEB by default
 814          * when the floating VEB is enabled.
 815          */
 816         for (i = 0; i < I40E_MAX_VF; i++)
 817                 vf_floating_veb[i] = true;
 818
 819         if (devargs == NULL)
 820                 return;
 821
 822         kvlist = rte_kvargs_parse(devargs->args, NULL);
 823         if (kvlist == NULL)
 824                 return;
 825
 826         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 827                 rte_kvargs_free(kvlist);
 828                 return;
 829         }
 830         /* When the floating_veb_list parameter exists, all the VFs
 831          * will attach to the legacy VEB firstly, then configure VFs
 832          * to the floating VEB according to the floating_veb_list.
 833          */
 834         if (rte_kvargs_process(kvlist, floating_veb_list,
 835                                floating_veb_list_handler,
 836                                vf_floating_veb) < 0) {
 837                 rte_kvargs_free(kvlist);
 838                 return;
 839         }
 840         rte_kvargs_free(kvlist);
 841 }
 842
 843 static int
 844 i40e_check_floating_handler(__rte_unused const char *key,
 845                             const char *value,
 846                             __rte_unused void *opaque)
 847 {
 848         if (strcmp(value, "1"))
 849                 return -1;
 850
 851         return 0;
 852 }
 853
 854 static int
 855 is_floating_veb_supported(struct rte_devargs *devargs)
 856 {
 857         struct rte_kvargs *kvlist;
 858         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 859
 860         if (devargs == NULL)
 861                 return 0;
 862
 863         kvlist = rte_kvargs_parse(devargs->args, NULL);
 864         if (kvlist == NULL)
 865                 return 0;
 866
 867         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 868                 rte_kvargs_free(kvlist);
 869                 return 0;
 870         }
 871         /* Floating VEB is enabled when there's key-value:
 872          * enable_floating_veb=1
 873          */
 874         if (rte_kvargs_process(kvlist, floating_veb_key,
 875                                i40e_check_floating_handler, NULL) < 0) {
 876                 rte_kvargs_free(kvlist);
 877                 return 0;
 878         }
 879         rte_kvargs_free(kvlist);
 880
 881         return 1;
 882 }
 883
 884 static void
 885 config_floating_veb(struct rte_eth_dev *dev)
 886 {
 887         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 888         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 889         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 890
 891         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 892
 893         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 894                 pf->floating_veb =
 895                         is_floating_veb_supported(pci_dev->device.devargs);
 896                 config_vf_floating_veb(pci_dev->device.devargs,
 897                                        pf->floating_veb,
 898                                        pf->floating_veb_list);
 899         } else {
 900                 pf->floating_veb = false;
 901         }
 902 }
 903
 904 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 905 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 906
 907 static int
 908 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 909 {
 910         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 911         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 912         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 913         int ret;
 914
 915         struct rte_hash_parameters ethertype_hash_params = {
 916                 .name = ethertype_hash_name,
 917                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 918                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 919                 .hash_func = rte_hash_crc,
 920                 .hash_func_init_val = 0,
 921                 .socket_id = rte_socket_id(),
 922         };
 923
 924         /* Initialize ethertype filter rule list and hash */
 925         TAILQ_INIT(&ethertype_rule->ethertype_list);
 926         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 927                  "ethertype_%s", dev->device->name);
 928         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 929         if (!ethertype_rule->hash_table) {
 930                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 931                 return -EINVAL;
 932         }
 933         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 934                                        sizeof(struct i40e_ethertype_filter *) *
 935                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 936                                        0);
 937         if (!ethertype_rule->hash_map) {
 938                 PMD_INIT_LOG(ERR,
 939                              "Failed to allocate memory for ethertype hash map!");
 940                 ret = -ENOMEM;
 941                 goto err_ethertype_hash_map_alloc;
 942         }
 943
 944         return 0;
 945
 946 err_ethertype_hash_map_alloc:
 947         rte_hash_free(ethertype_rule->hash_table);
 948
 949         return ret;
 950 }
 951
 952 static int
 953 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 954 {
 955         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 956         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 957         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 958         int ret;
 959
 960         struct rte_hash_parameters tunnel_hash_params = {
 961                 .name = tunnel_hash_name,
 962                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 963                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 964                 .hash_func = rte_hash_crc,
 965                 .hash_func_init_val = 0,
 966                 .socket_id = rte_socket_id(),
 967         };
 968
 969         /* Initialize tunnel filter rule list and hash */
 970         TAILQ_INIT(&tunnel_rule->tunnel_list);
 971         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 972                  "tunnel_%s", dev->device->name);
 973         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 974         if (!tunnel_rule->hash_table) {
 975                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 976                 return -EINVAL;
 977         }
 978         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 979                                     sizeof(struct i40e_tunnel_filter *) *
 980                                     I40E_MAX_TUNNEL_FILTER_NUM,
 981                                     0);
 982         if (!tunnel_rule->hash_map) {
 983                 PMD_INIT_LOG(ERR,
 984                              "Failed to allocate memory for tunnel hash map!");
 985                 ret = -ENOMEM;
 986                 goto err_tunnel_hash_map_alloc;
 987         }
 988
 989         return 0;
 990
 991 err_tunnel_hash_map_alloc:
 992         rte_hash_free(tunnel_rule->hash_table);
 993
 994         return ret;
 995 }
 996
 997 static int
 998 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 999 {
1000         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1001         struct i40e_fdir_info *fdir_info = &pf->fdir;
1002         char fdir_hash_name[RTE_HASH_NAMESIZE];
1003         int ret;
1004
1005         struct rte_hash_parameters fdir_hash_params = {
1006                 .name = fdir_hash_name,
1007                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1008                 .key_len = sizeof(struct rte_eth_fdir_input),
1009                 .hash_func = rte_hash_crc,
1010                 .hash_func_init_val = 0,
1011                 .socket_id = rte_socket_id(),
1012         };
1013
1014         /* Initialize flow director filter rule list and hash */
1015         TAILQ_INIT(&fdir_info->fdir_list);
1016         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1017                  "fdir_%s", dev->device->name);
1018         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1019         if (!fdir_info->hash_table) {
1020                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1021                 return -EINVAL;
1022         }
1023         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1024                                           sizeof(struct i40e_fdir_filter *) *
1025                                           I40E_MAX_FDIR_FILTER_NUM,
1026                                           0);
1027         if (!fdir_info->hash_map) {
1028                 PMD_INIT_LOG(ERR,
1029                              "Failed to allocate memory for fdir hash map!");
1030                 ret = -ENOMEM;
1031                 goto err_fdir_hash_map_alloc;
1032         }
1033         return 0;
1034
1035 err_fdir_hash_map_alloc:
1036         rte_hash_free(fdir_info->hash_table);
1037
1038         return ret;
1039 }
1040
1041 static void
1042 i40e_init_customized_info(struct i40e_pf *pf)
1043 {
1044         int i;
1045
1046         /* Initialize customized pctype */
1047         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1048                 pf->customized_pctype[i].index = i;
1049                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1050                 pf->customized_pctype[i].valid = false;
1051         }
1052
1053         pf->gtp_support = false;
1054 }
1055
1056 void
1057 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1058 {
1059         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1060         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1061         struct i40e_queue_regions *info = &pf->queue_region;
1062         uint16_t i;
1063
1064         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1065                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1066
1067         memset(info, 0, sizeof(struct i40e_queue_regions));
1068 }
1069
1070 static int
1071 eth_i40e_dev_init(struct rte_eth_dev *dev)
1072 {
1073         struct rte_pci_device *pci_dev;
1074         struct rte_intr_handle *intr_handle;
1075         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1076         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1077         struct i40e_vsi *vsi;
1078         int ret;
1079         uint32_t len;
1080         uint8_t aq_fail = 0;
1081
1082         PMD_INIT_FUNC_TRACE();
1083
1084         dev->dev_ops = &i40e_eth_dev_ops;
1085         dev->rx_pkt_burst = i40e_recv_pkts;
1086         dev->tx_pkt_burst = i40e_xmit_pkts;
1087         dev->tx_pkt_prepare = i40e_prep_pkts;
1088
1089         /* for secondary processes, we don't initialise any further as primary
1090          * has already done this work. Only check we don't need a different
1091          * RX function */
1092         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1093                 i40e_set_rx_function(dev);
1094                 i40e_set_tx_function(dev);
1095                 return 0;
1096         }
1097         i40e_set_default_ptype_table(dev);
1098         i40e_set_default_pctype_table(dev);
1099         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1100         intr_handle = &pci_dev->intr_handle;
1101
1102         rte_eth_copy_pci_info(dev, pci_dev);
1103         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1104
1105         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1106         pf->adapter->eth_dev = dev;
1107         pf->dev_data = dev->data;
1108
1109         hw->back = I40E_PF_TO_ADAPTER(pf);
1110         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1111         if (!hw->hw_addr) {
1112                 PMD_INIT_LOG(ERR,
1113                         "Hardware is not available, as address is NULL");
1114                 return -ENODEV;
1115         }
1116
1117         hw->vendor_id = pci_dev->id.vendor_id;
1118         hw->device_id = pci_dev->id.device_id;
1119         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1120         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1121         hw->bus.device = pci_dev->addr.devid;
1122         hw->bus.func = pci_dev->addr.function;
1123         hw->adapter_stopped = 0;
1124
1125         /* Make sure all is clean before doing PF reset */
1126         i40e_clear_hw(hw);
1127
1128         /* Initialize the hardware */
1129         i40e_hw_init(dev);
1130
1131         /* Reset here to make sure all is clean for each PF */
1132         ret = i40e_pf_reset(hw);
1133         if (ret) {
1134                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1135                 return ret;
1136         }
1137
1138         /* Initialize the shared code (base driver) */
1139         ret = i40e_init_shared_code(hw);
1140         if (ret) {
1141                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1142                 return ret;
1143         }
1144
1145         /*
1146          * To work around the NVM issue, initialize registers
1147          * for flexible payload and packet type of QinQ by
1148          * software. It should be removed once issues are fixed
1149          * in NVM.
1150          */
1151         i40e_GLQF_reg_init(hw);
1152
1153         /* Initialize the input set for filters (hash and fd) to default value */
1154         i40e_filter_input_set_init(pf);
1155
1156         /* Initialize the parameters for adminq */
1157         i40e_init_adminq_parameter(hw);
1158         ret = i40e_init_adminq(hw);
1159         if (ret != I40E_SUCCESS) {
1160                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1161                 return -EIO;
1162         }
1163         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1164                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1165                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1166                      ((hw->nvm.version >> 12) & 0xf),
1167                      ((hw->nvm.version >> 4) & 0xff),
1168                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1169
1170         /* initialise the L3_MAP register */
1171         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1172                                    0x00000028,  NULL);
1173         if (ret)
1174                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1175
1176         /* Need the special FW version to support floating VEB */
1177         config_floating_veb(dev);
1178         /* Clear PXE mode */
1179         i40e_clear_pxe_mode(hw);
1180         i40e_dev_sync_phy_type(hw);
1181
1182         /*
1183          * On X710, performance number is far from the expectation on recent
1184          * firmware versions. The fix for this issue may not be integrated in
1185          * the following firmware version. So the workaround in software driver
1186          * is needed. It needs to modify the initial values of 3 internal only
1187          * registers. Note that the workaround can be removed when it is fixed
1188          * in firmware in the future.
1189          */
1190         i40e_configure_registers(hw);
1191
1192         /* Get hw capabilities */
1193         ret = i40e_get_cap(hw);
1194         if (ret != I40E_SUCCESS) {
1195                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1196                 goto err_get_capabilities;
1197         }
1198
1199         /* Initialize parameters for PF */
1200         ret = i40e_pf_parameter_init(dev);
1201         if (ret != 0) {
1202                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1203                 goto err_parameter_init;
1204         }
1205
1206         /* Initialize the queue management */
1207         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1208         if (ret < 0) {
1209                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1210                 goto err_qp_pool_init;
1211         }
1212         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1213                                 hw->func_caps.num_msix_vectors - 1);
1214         if (ret < 0) {
1215                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1216                 goto err_msix_pool_init;
1217         }
1218
1219         /* Initialize lan hmc */
1220         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1221                                 hw->func_caps.num_rx_qp, 0, 0);
1222         if (ret != I40E_SUCCESS) {
1223                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1224                 goto err_init_lan_hmc;
1225         }
1226
1227         /* Configure lan hmc */
1228         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1229         if (ret != I40E_SUCCESS) {
1230                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1231                 goto err_configure_lan_hmc;
1232         }
1233
1234         /* Get and check the mac address */
1235         i40e_get_mac_addr(hw, hw->mac.addr);
1236         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1237                 PMD_INIT_LOG(ERR, "mac address is not valid");
1238                 ret = -EIO;
1239                 goto err_get_mac_addr;
1240         }
1241         /* Copy the permanent MAC address */
1242         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1243                         (struct ether_addr *) hw->mac.perm_addr);
1244
1245         /* Disable flow control */
1246         hw->fc.requested_mode = I40E_FC_NONE;
1247         i40e_set_fc(hw, &aq_fail, TRUE);
1248
1249         /* Set the global registers with default ether type value */
1250         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1251         if (ret != I40E_SUCCESS) {
1252                 PMD_INIT_LOG(ERR,
1253                         "Failed to set the default outer VLAN ether type");
1254                 goto err_setup_pf_switch;
1255         }
1256
1257         /* PF setup, which includes VSI setup */
1258         ret = i40e_pf_setup(pf);
1259         if (ret) {
1260                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1261                 goto err_setup_pf_switch;
1262         }
1263
1264         /* reset all stats of the device, including pf and main vsi */
1265         i40e_dev_stats_reset(dev);
1266
1267         vsi = pf->main_vsi;
1268
1269         /* Disable double vlan by default */
1270         i40e_vsi_config_double_vlan(vsi, FALSE);
1271
1272         /* Disable S-TAG identification when floating_veb is disabled */
1273         if (!pf->floating_veb) {
1274                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1275                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1276                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1277                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1278                 }
1279         }
1280
1281         if (!vsi->max_macaddrs)
1282                 len = ETHER_ADDR_LEN;
1283         else
1284                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1285
1286         /* Should be after VSI initialized */
1287         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1288         if (!dev->data->mac_addrs) {
1289                 PMD_INIT_LOG(ERR,
1290                         "Failed to allocated memory for storing mac address");
1291                 goto err_mac_alloc;
1292         }
1293         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1294                                         &dev->data->mac_addrs[0]);
1295
1296         /* Init dcb to sw mode by default */
1297         ret = i40e_dcb_init_configure(dev, TRUE);
1298         if (ret != I40E_SUCCESS) {
1299                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1300                 pf->flags &= ~I40E_FLAG_DCB;
1301         }
1302         /* Update HW struct after DCB configuration */
1303         i40e_get_cap(hw);
1304
1305         /* initialize pf host driver to setup SRIOV resource if applicable */
1306         i40e_pf_host_init(dev);
1307
1308         /* register callback func to eal lib */
1309         rte_intr_callback_register(intr_handle,
1310                                    i40e_dev_interrupt_handler, dev);
1311
1312         /* configure and enable device interrupt */
1313         i40e_pf_config_irq0(hw, TRUE);
1314         i40e_pf_enable_irq0(hw);
1315
1316         /* enable uio intr after callback register */
1317         rte_intr_enable(intr_handle);
1318         /*
1319          * Add an ethertype filter to drop all flow control frames transmitted
1320          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1321          * frames to wire.
1322          */
1323         i40e_add_tx_flow_control_drop_filter(pf);
1324
1325         /* Set the max frame size to 0x2600 by default,
1326          * in case other drivers changed the default value.
1327          */
1328         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1329
1330         /* initialize mirror rule list */
1331         TAILQ_INIT(&pf->mirror_list);
1332
1333         /* initialize Traffic Manager configuration */
1334         i40e_tm_conf_init(dev);
1335
1336         /* Initialize customized information */
1337         i40e_init_customized_info(pf);
1338
1339         ret = i40e_init_ethtype_filter_list(dev);
1340         if (ret < 0)
1341                 goto err_init_ethtype_filter_list;
1342         ret = i40e_init_tunnel_filter_list(dev);
1343         if (ret < 0)
1344                 goto err_init_tunnel_filter_list;
1345         ret = i40e_init_fdir_filter_list(dev);
1346         if (ret < 0)
1347                 goto err_init_fdir_filter_list;
1348
1349         /* initialize queue region configuration */
1350         i40e_init_queue_region_conf(dev);
1351
1352         return 0;
1353
1354 err_init_fdir_filter_list:
1355         rte_free(pf->tunnel.hash_table);
1356         rte_free(pf->tunnel.hash_map);
1357 err_init_tunnel_filter_list:
1358         rte_free(pf->ethertype.hash_table);
1359         rte_free(pf->ethertype.hash_map);
1360 err_init_ethtype_filter_list:
1361         rte_free(dev->data->mac_addrs);
1362 err_mac_alloc:
1363         i40e_vsi_release(pf->main_vsi);
1364 err_setup_pf_switch:
1365 err_get_mac_addr:
1366 err_configure_lan_hmc:
1367         (void)i40e_shutdown_lan_hmc(hw);
1368 err_init_lan_hmc:
1369         i40e_res_pool_destroy(&pf->msix_pool);
1370 err_msix_pool_init:
1371         i40e_res_pool_destroy(&pf->qp_pool);
1372 err_qp_pool_init:
1373 err_parameter_init:
1374 err_get_capabilities:
1375         (void)i40e_shutdown_adminq(hw);
1376
1377         return ret;
1378 }
1379
1380 static void
1381 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1382 {
1383         struct i40e_ethertype_filter *p_ethertype;
1384         struct i40e_ethertype_rule *ethertype_rule;
1385
1386         ethertype_rule = &pf->ethertype;
1387         /* Remove all ethertype filter rules and hash */
1388         if (ethertype_rule->hash_map)
1389                 rte_free(ethertype_rule->hash_map);
1390         if (ethertype_rule->hash_table)
1391                 rte_hash_free(ethertype_rule->hash_table);
1392
1393         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1394                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1395                              p_ethertype, rules);
1396                 rte_free(p_ethertype);
1397         }
1398 }
1399
1400 static void
1401 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1402 {
1403         struct i40e_tunnel_filter *p_tunnel;
1404         struct i40e_tunnel_rule *tunnel_rule;
1405
1406         tunnel_rule = &pf->tunnel;
1407         /* Remove all tunnel director rules and hash */
1408         if (tunnel_rule->hash_map)
1409                 rte_free(tunnel_rule->hash_map);
1410         if (tunnel_rule->hash_table)
1411                 rte_hash_free(tunnel_rule->hash_table);
1412
1413         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1414                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1415                 rte_free(p_tunnel);
1416         }
1417 }
1418
1419 static void
1420 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1421 {
1422         struct i40e_fdir_filter *p_fdir;
1423         struct i40e_fdir_info *fdir_info;
1424
1425         fdir_info = &pf->fdir;
1426         /* Remove all flow director rules and hash */
1427         if (fdir_info->hash_map)
1428                 rte_free(fdir_info->hash_map);
1429         if (fdir_info->hash_table)
1430                 rte_hash_free(fdir_info->hash_table);
1431
1432         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1433                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1434                 rte_free(p_fdir);
1435         }
1436 }
1437
1438 static int
1439 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1440 {
1441         struct i40e_pf *pf;
1442         struct rte_pci_device *pci_dev;
1443         struct rte_intr_handle *intr_handle;
1444         struct i40e_hw *hw;
1445         struct i40e_filter_control_settings settings;
1446         struct rte_flow *p_flow;
1447         int ret;
1448         uint8_t aq_fail = 0;
1449
1450         PMD_INIT_FUNC_TRACE();
1451
1452         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1453                 return 0;
1454
1455         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1456         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1457         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1458         intr_handle = &pci_dev->intr_handle;
1459
1460         if (hw->adapter_stopped == 0)
1461                 i40e_dev_close(dev);
1462
1463         dev->dev_ops = NULL;
1464         dev->rx_pkt_burst = NULL;
1465         dev->tx_pkt_burst = NULL;
1466
1467         /* Clear PXE mode */
1468         i40e_clear_pxe_mode(hw);
1469
1470         /* Unconfigure filter control */
1471         memset(&settings, 0, sizeof(settings));
1472         ret = i40e_set_filter_control(hw, &settings);
1473         if (ret)
1474                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1475                                         ret);
1476
1477         /* Disable flow control */
1478         hw->fc.requested_mode = I40E_FC_NONE;
1479         i40e_set_fc(hw, &aq_fail, TRUE);
1480
1481         /* uninitialize pf host driver */
1482         i40e_pf_host_uninit(dev);
1483
1484         rte_free(dev->data->mac_addrs);
1485         dev->data->mac_addrs = NULL;
1486
1487         /* disable uio intr before callback unregister */
1488         rte_intr_disable(intr_handle);
1489
1490         /* register callback func to eal lib */
1491         rte_intr_callback_unregister(intr_handle,
1492                                      i40e_dev_interrupt_handler, dev);
1493
1494         i40e_rm_ethtype_filter_list(pf);
1495         i40e_rm_tunnel_filter_list(pf);
1496         i40e_rm_fdir_filter_list(pf);
1497
1498         /* Remove all flows */
1499         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1500                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1501                 rte_free(p_flow);
1502         }
1503
1504         /* Remove all Traffic Manager configuration */
1505         i40e_tm_conf_uninit(dev);
1506
1507         return 0;
1508 }
1509
1510 static int
1511 i40e_dev_configure(struct rte_eth_dev *dev)
1512 {
1513         struct i40e_adapter *ad =
1514                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1515         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1516         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1517         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1518         int i, ret;
1519
1520         ret = i40e_dev_sync_phy_type(hw);
1521         if (ret)
1522                 return ret;
1523
1524         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1525          * bulk allocation or vector Rx preconditions we will reset it.
1526          */
1527         ad->rx_bulk_alloc_allowed = true;
1528         ad->rx_vec_allowed = true;
1529         ad->tx_simple_allowed = true;
1530         ad->tx_vec_allowed = true;
1531
1532         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1533                 ret = i40e_fdir_setup(pf);
1534                 if (ret != I40E_SUCCESS) {
1535                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1536                         return -ENOTSUP;
1537                 }
1538                 ret = i40e_fdir_configure(dev);
1539                 if (ret < 0) {
1540                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1541                         goto err;
1542                 }
1543         } else
1544                 i40e_fdir_teardown(pf);
1545
1546         ret = i40e_dev_init_vlan(dev);
1547         if (ret < 0)
1548                 goto err;
1549
1550         /* VMDQ setup.
1551          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1552          *  RSS setting have different requirements.
1553          *  General PMD driver call sequence are NIC init, configure,
1554          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1555          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1556          *  applicable. So, VMDQ setting has to be done before
1557          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1558          *  For RSS setting, it will try to calculate actual configured RX queue
1559          *  number, which will be available after rx_queue_setup(). dev_start()
1560          *  function is good to place RSS setup.
1561          */
1562         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1563                 ret = i40e_vmdq_setup(dev);
1564                 if (ret)
1565                         goto err;
1566         }
1567
1568         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1569                 ret = i40e_dcb_setup(dev);
1570                 if (ret) {
1571                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1572                         goto err_dcb;
1573                 }
1574         }
1575
1576         TAILQ_INIT(&pf->flow_list);
1577
1578         return 0;
1579
1580 err_dcb:
1581         /* need to release vmdq resource if exists */
1582         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1583                 i40e_vsi_release(pf->vmdq[i].vsi);
1584                 pf->vmdq[i].vsi = NULL;
1585         }
1586         rte_free(pf->vmdq);
1587         pf->vmdq = NULL;
1588 err:
1589         /* need to release fdir resource if exists */
1590         i40e_fdir_teardown(pf);
1591         return ret;
1592 }
1593
1594 void
1595 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1596 {
1597         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1598         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1599         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1600         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1601         uint16_t msix_vect = vsi->msix_intr;
1602         uint16_t i;
1603
1604         for (i = 0; i < vsi->nb_qps; i++) {
1605                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1606                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1607                 rte_wmb();
1608         }
1609
1610         if (vsi->type != I40E_VSI_SRIOV) {
1611                 if (!rte_intr_allow_others(intr_handle)) {
1612                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1613                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1614                         I40E_WRITE_REG(hw,
1615                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1616                                        0);
1617                 } else {
1618                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1619                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1620                         I40E_WRITE_REG(hw,
1621                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1622                                                        msix_vect - 1), 0);
1623                 }
1624         } else {
1625                 uint32_t reg;
1626                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1627                         vsi->user_param + (msix_vect - 1);
1628
1629                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1630                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1631         }
1632         I40E_WRITE_FLUSH(hw);
1633 }
1634
1635 static void
1636 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1637                        int base_queue, int nb_queue,
1638                        uint16_t itr_idx)
1639 {
1640         int i;
1641         uint32_t val;
1642         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1643
1644         /* Bind all RX queues to allocated MSIX interrupt */
1645         for (i = 0; i < nb_queue; i++) {
1646                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1647                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1648                         ((base_queue + i + 1) <<
1649                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1650                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1651                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1652
1653                 if (i == nb_queue - 1)
1654                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1655                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1656         }
1657
1658         /* Write first RX queue to Link list register as the head element */
1659         if (vsi->type != I40E_VSI_SRIOV) {
1660                 uint16_t interval =
1661                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1662
1663                 if (msix_vect == I40E_MISC_VEC_ID) {
1664                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1665                                        (base_queue <<
1666                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1667                                        (0x0 <<
1668                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1669                         I40E_WRITE_REG(hw,
1670                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1671                                        interval);
1672                 } else {
1673                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1674                                        (base_queue <<
1675                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1676                                        (0x0 <<
1677                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1678                         I40E_WRITE_REG(hw,
1679                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1680                                                        msix_vect - 1),
1681                                        interval);
1682                 }
1683         } else {
1684                 uint32_t reg;
1685
1686                 if (msix_vect == I40E_MISC_VEC_ID) {
1687                         I40E_WRITE_REG(hw,
1688                                        I40E_VPINT_LNKLST0(vsi->user_param),
1689                                        (base_queue <<
1690                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1691                                        (0x0 <<
1692                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1693                 } else {
1694                         /* num_msix_vectors_vf needs to minus irq0 */
1695                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1696                                 vsi->user_param + (msix_vect - 1);
1697
1698                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1699                                        (base_queue <<
1700                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1701                                        (0x0 <<
1702                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1703                 }
1704         }
1705
1706         I40E_WRITE_FLUSH(hw);
1707 }
1708
1709 void
1710 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1711 {
1712         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1713         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1714         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1715         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1716         uint16_t msix_vect = vsi->msix_intr;
1717         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1718         uint16_t queue_idx = 0;
1719         int record = 0;
1720         uint32_t val;
1721         int i;
1722
1723         for (i = 0; i < vsi->nb_qps; i++) {
1724                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1725                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1726         }
1727
1728         /* INTENA flag is not auto-cleared for interrupt */
1729         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1730         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1731                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1732                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1733         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1734
1735         /* VF bind interrupt */
1736         if (vsi->type == I40E_VSI_SRIOV) {
1737                 __vsi_queues_bind_intr(vsi, msix_vect,
1738                                        vsi->base_queue, vsi->nb_qps,
1739                                        itr_idx);
1740                 return;
1741         }
1742
1743         /* PF & VMDq bind interrupt */
1744         if (rte_intr_dp_is_en(intr_handle)) {
1745                 if (vsi->type == I40E_VSI_MAIN) {
1746                         queue_idx = 0;
1747                         record = 1;
1748                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1749                         struct i40e_vsi *main_vsi =
1750                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1751                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1752                         record = 1;
1753                 }
1754         }
1755
1756         for (i = 0; i < vsi->nb_used_qps; i++) {
1757                 if (nb_msix <= 1) {
1758                         if (!rte_intr_allow_others(intr_handle))
1759                                 /* allow to share MISC_VEC_ID */
1760                                 msix_vect = I40E_MISC_VEC_ID;
1761
1762                         /* no enough msix_vect, map all to one */
1763                         __vsi_queues_bind_intr(vsi, msix_vect,
1764                                                vsi->base_queue + i,
1765                                                vsi->nb_used_qps - i,
1766                                                itr_idx);
1767                         for (; !!record && i < vsi->nb_used_qps; i++)
1768                                 intr_handle->intr_vec[queue_idx + i] =
1769                                         msix_vect;
1770                         break;
1771                 }
1772                 /* 1:1 queue/msix_vect mapping */
1773                 __vsi_queues_bind_intr(vsi, msix_vect,
1774                                        vsi->base_queue + i, 1,
1775                                        itr_idx);
1776                 if (!!record)
1777                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1778
1779                 msix_vect++;
1780                 nb_msix--;
1781         }
1782 }
1783
1784 static void
1785 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1786 {
1787         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1788         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1789         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1790         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1791         uint16_t interval = i40e_calc_itr_interval(\
1792                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1793         uint16_t msix_intr, i;
1794
1795         if (rte_intr_allow_others(intr_handle))
1796                 for (i = 0; i < vsi->nb_msix; i++) {
1797                         msix_intr = vsi->msix_intr + i;
1798                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1799                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1800                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1801                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1802                                 (interval <<
1803                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1804                 }
1805         else
1806                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1807                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1808                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1809                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1810                                (interval <<
1811                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1812
1813         I40E_WRITE_FLUSH(hw);
1814 }
1815
1816 static void
1817 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1818 {
1819         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1820         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1821         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1822         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1823         uint16_t msix_intr, i;
1824
1825         if (rte_intr_allow_others(intr_handle))
1826                 for (i = 0; i < vsi->nb_msix; i++) {
1827                         msix_intr = vsi->msix_intr + i;
1828                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1829                                        0);
1830                 }
1831         else
1832                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1833
1834         I40E_WRITE_FLUSH(hw);
1835 }
1836
1837 static inline uint8_t
1838 i40e_parse_link_speeds(uint16_t link_speeds)
1839 {
1840         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1841
1842         if (link_speeds & ETH_LINK_SPEED_40G)
1843                 link_speed |= I40E_LINK_SPEED_40GB;
1844         if (link_speeds & ETH_LINK_SPEED_25G)
1845                 link_speed |= I40E_LINK_SPEED_25GB;
1846         if (link_speeds & ETH_LINK_SPEED_20G)
1847                 link_speed |= I40E_LINK_SPEED_20GB;
1848         if (link_speeds & ETH_LINK_SPEED_10G)
1849                 link_speed |= I40E_LINK_SPEED_10GB;
1850         if (link_speeds & ETH_LINK_SPEED_1G)
1851                 link_speed |= I40E_LINK_SPEED_1GB;
1852         if (link_speeds & ETH_LINK_SPEED_100M)
1853                 link_speed |= I40E_LINK_SPEED_100MB;
1854
1855         return link_speed;
1856 }
1857
1858 static int
1859 i40e_phy_conf_link(struct i40e_hw *hw,
1860                    uint8_t abilities,
1861                    uint8_t force_speed,
1862                    bool is_up)
1863 {
1864         enum i40e_status_code status;
1865         struct i40e_aq_get_phy_abilities_resp phy_ab;
1866         struct i40e_aq_set_phy_config phy_conf;
1867         enum i40e_aq_phy_type cnt;
1868         uint32_t phy_type_mask = 0;
1869
1870         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1871                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1872                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1873                         I40E_AQ_PHY_FLAG_LOW_POWER;
1874         const uint8_t advt = I40E_LINK_SPEED_40GB |
1875                         I40E_LINK_SPEED_25GB |
1876                         I40E_LINK_SPEED_10GB |
1877                         I40E_LINK_SPEED_1GB |
1878                         I40E_LINK_SPEED_100MB;
1879         int ret = -ENOTSUP;
1880
1881
1882         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1883                                               NULL);
1884         if (status)
1885                 return ret;
1886
1887         /* If link already up, no need to set up again */
1888         if (is_up && phy_ab.phy_type != 0)
1889                 return I40E_SUCCESS;
1890
1891         memset(&phy_conf, 0, sizeof(phy_conf));
1892
1893         /* bits 0-2 use the values from get_phy_abilities_resp */
1894         abilities &= ~mask;
1895         abilities |= phy_ab.abilities & mask;
1896
1897         /* update ablities and speed */
1898         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1899                 phy_conf.link_speed = advt;
1900         else
1901                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1902
1903         phy_conf.abilities = abilities;
1904
1905
1906
1907         /* To enable link, phy_type mask needs to include each type */
1908         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1909                 phy_type_mask |= 1 << cnt;
1910
1911         /* use get_phy_abilities_resp value for the rest */
1912         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1913         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1914                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1915                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1916         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1917         phy_conf.eee_capability = phy_ab.eee_capability;
1918         phy_conf.eeer = phy_ab.eeer_val;
1919         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1920
1921         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1922                     phy_ab.abilities, phy_ab.link_speed);
1923         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1924                     phy_conf.abilities, phy_conf.link_speed);
1925
1926         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1927         if (status)
1928                 return ret;
1929
1930         return I40E_SUCCESS;
1931 }
1932
1933 static int
1934 i40e_apply_link_speed(struct rte_eth_dev *dev)
1935 {
1936         uint8_t speed;
1937         uint8_t abilities = 0;
1938         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939         struct rte_eth_conf *conf = &dev->data->dev_conf;
1940
1941         speed = i40e_parse_link_speeds(conf->link_speeds);
1942         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1943         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1944                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1945         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1946
1947         return i40e_phy_conf_link(hw, abilities, speed, true);
1948 }
1949
1950 static int
1951 i40e_dev_start(struct rte_eth_dev *dev)
1952 {
1953         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1954         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1955         struct i40e_vsi *main_vsi = pf->main_vsi;
1956         int ret, i;
1957         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1958         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1959         uint32_t intr_vector = 0;
1960         struct i40e_vsi *vsi;
1961
1962         hw->adapter_stopped = 0;
1963
1964         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1965                 PMD_INIT_LOG(ERR,
1966                 "Invalid link_speeds for port %u, autonegotiation disabled",
1967                               dev->data->port_id);
1968                 return -EINVAL;
1969         }
1970
1971         rte_intr_disable(intr_handle);
1972
1973         if ((rte_intr_cap_multiple(intr_handle) ||
1974              !RTE_ETH_DEV_SRIOV(dev).active) &&
1975             dev->data->dev_conf.intr_conf.rxq != 0) {
1976                 intr_vector = dev->data->nb_rx_queues;
1977                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1978                 if (ret)
1979                         return ret;
1980         }
1981
1982         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1983                 intr_handle->intr_vec =
1984                         rte_zmalloc("intr_vec",
1985                                     dev->data->nb_rx_queues * sizeof(int),
1986                                     0);
1987                 if (!intr_handle->intr_vec) {
1988                         PMD_INIT_LOG(ERR,
1989                                 "Failed to allocate %d rx_queues intr_vec",
1990                                 dev->data->nb_rx_queues);
1991                         return -ENOMEM;
1992                 }
1993         }
1994
1995         /* Initialize VSI */
1996         ret = i40e_dev_rxtx_init(pf);
1997         if (ret != I40E_SUCCESS) {
1998                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1999                 goto err_up;
2000         }
2001
2002         /* Map queues with MSIX interrupt */
2003         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2004                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2005         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2006         i40e_vsi_enable_queues_intr(main_vsi);
2007
2008         /* Map VMDQ VSI queues with MSIX interrupt */
2009         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2010                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2011                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2012                                           I40E_ITR_INDEX_DEFAULT);
2013                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2014         }
2015
2016         /* enable FDIR MSIX interrupt */
2017         if (pf->fdir.fdir_vsi) {
2018                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2019                                           I40E_ITR_INDEX_NONE);
2020                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2021         }
2022
2023         /* Enable all queues which have been configured */
2024         ret = i40e_dev_switch_queues(pf, TRUE);
2025         if (ret != I40E_SUCCESS) {
2026                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2027                 goto err_up;
2028         }
2029
2030         /* Enable receiving broadcast packets */
2031         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2032         if (ret != I40E_SUCCESS)
2033                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2034
2035         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2036                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2037                                                 true, NULL);
2038                 if (ret != I40E_SUCCESS)
2039                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2040         }
2041
2042         /* Enable the VLAN promiscuous mode. */
2043         if (pf->vfs) {
2044                 for (i = 0; i < pf->vf_num; i++) {
2045                         vsi = pf->vfs[i].vsi;
2046                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2047                                                      true, NULL);
2048                 }
2049         }
2050
2051         /* Apply link configure */
2052         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2053                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2054                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2055                                 ETH_LINK_SPEED_40G)) {
2056                 PMD_DRV_LOG(ERR, "Invalid link setting");
2057                 goto err_up;
2058         }
2059         ret = i40e_apply_link_speed(dev);
2060         if (I40E_SUCCESS != ret) {
2061                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2062                 goto err_up;
2063         }
2064
2065         if (!rte_intr_allow_others(intr_handle)) {
2066                 rte_intr_callback_unregister(intr_handle,
2067                                              i40e_dev_interrupt_handler,
2068                                              (void *)dev);
2069                 /* configure and enable device interrupt */
2070                 i40e_pf_config_irq0(hw, FALSE);
2071                 i40e_pf_enable_irq0(hw);
2072
2073                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2074                         PMD_INIT_LOG(INFO,
2075                                 "lsc won't enable because of no intr multiplex");
2076         } else {
2077                 ret = i40e_aq_set_phy_int_mask(hw,
2078                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2079                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2080                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2081                 if (ret != I40E_SUCCESS)
2082                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2083
2084                 /* Call get_link_info aq commond to enable/disable LSE */
2085                 i40e_dev_link_update(dev, 0);
2086         }
2087
2088         /* enable uio intr after callback register */
2089         rte_intr_enable(intr_handle);
2090
2091         i40e_filter_restore(pf);
2092
2093         if (pf->tm_conf.root && !pf->tm_conf.committed)
2094                 PMD_DRV_LOG(WARNING,
2095                             "please call hierarchy_commit() "
2096                             "before starting the port");
2097
2098         return I40E_SUCCESS;
2099
2100 err_up:
2101         i40e_dev_switch_queues(pf, FALSE);
2102         i40e_dev_clear_queues(dev);
2103
2104         return ret;
2105 }
2106
2107 static void
2108 i40e_dev_stop(struct rte_eth_dev *dev)
2109 {
2110         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2111         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2112         struct i40e_vsi *main_vsi = pf->main_vsi;
2113         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2114         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2115         int i;
2116
2117         if (hw->adapter_stopped == 1)
2118                 return;
2119         /* Disable all queues */
2120         i40e_dev_switch_queues(pf, FALSE);
2121
2122         /* un-map queues with interrupt registers */
2123         i40e_vsi_disable_queues_intr(main_vsi);
2124         i40e_vsi_queues_unbind_intr(main_vsi);
2125
2126         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2127                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2128                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2129         }
2130
2131         if (pf->fdir.fdir_vsi) {
2132                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2133                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2134         }
2135         /* Clear all queues and release memory */
2136         i40e_dev_clear_queues(dev);
2137
2138         /* Set link down */
2139         i40e_dev_set_link_down(dev);
2140
2141         if (!rte_intr_allow_others(intr_handle))
2142                 /* resume to the default handler */
2143                 rte_intr_callback_register(intr_handle,
2144                                            i40e_dev_interrupt_handler,
2145                                            (void *)dev);
2146
2147         /* Clean datapath event and queue/vec mapping */
2148         rte_intr_efd_disable(intr_handle);
2149         if (intr_handle->intr_vec) {
2150                 rte_free(intr_handle->intr_vec);
2151                 intr_handle->intr_vec = NULL;
2152         }
2153
2154         /* reset hierarchy commit */
2155         pf->tm_conf.committed = false;
2156
2157         /* Remove all the queue region configuration */
2158         i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
2159
2160         hw->adapter_stopped = 1;
2161 }
2162
2163 static void
2164 i40e_dev_close(struct rte_eth_dev *dev)
2165 {
2166         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2167         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2168         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2169         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2170         struct i40e_mirror_rule *p_mirror;
2171         uint32_t reg;
2172         int i;
2173         int ret;
2174
2175         PMD_INIT_FUNC_TRACE();
2176
2177         i40e_dev_stop(dev);
2178
2179         /* Remove all mirror rules */
2180         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2181                 ret = i40e_aq_del_mirror_rule(hw,
2182                                               pf->main_vsi->veb->seid,
2183                                               p_mirror->rule_type,
2184                                               p_mirror->entries,
2185                                               p_mirror->num_entries,
2186                                               p_mirror->id);
2187                 if (ret < 0)
2188                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2189                                     "status = %d, aq_err = %d.", ret,
2190                                     hw->aq.asq_last_status);
2191
2192                 /* remove mirror software resource anyway */
2193                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2194                 rte_free(p_mirror);
2195                 pf->nb_mirror_rule--;
2196         }
2197
2198         i40e_dev_free_queues(dev);
2199
2200         /* Disable interrupt */
2201         i40e_pf_disable_irq0(hw);
2202         rte_intr_disable(intr_handle);
2203
2204         /* shutdown and destroy the HMC */
2205         i40e_shutdown_lan_hmc(hw);
2206
2207         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2208                 i40e_vsi_release(pf->vmdq[i].vsi);
2209                 pf->vmdq[i].vsi = NULL;
2210         }
2211         rte_free(pf->vmdq);
2212         pf->vmdq = NULL;
2213
2214         /* release all the existing VSIs and VEBs */
2215         i40e_fdir_teardown(pf);
2216         i40e_vsi_release(pf->main_vsi);
2217
2218         /* shutdown the adminq */
2219         i40e_aq_queue_shutdown(hw, true);
2220         i40e_shutdown_adminq(hw);
2221
2222         i40e_res_pool_destroy(&pf->qp_pool);
2223         i40e_res_pool_destroy(&pf->msix_pool);
2224
2225         /* force a PF reset to clean anything leftover */
2226         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2227         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2228                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2229         I40E_WRITE_FLUSH(hw);
2230 }
2231
2232 /*
2233  * Reset PF device only to re-initialize resources in PMD layer
2234  */
2235 static int
2236 i40e_dev_reset(struct rte_eth_dev *dev)
2237 {
2238         int ret;
2239
2240         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2241          * its VF to make them align with it. The detailed notification
2242          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2243          * To avoid unexpected behavior in VF, currently reset of PF with
2244          * SR-IOV activation is not supported. It might be supported later.
2245          */
2246         if (dev->data->sriov.active)
2247                 return -ENOTSUP;
2248
2249         ret = eth_i40e_dev_uninit(dev);
2250         if (ret)
2251                 return ret;
2252
2253         ret = eth_i40e_dev_init(dev);
2254
2255         return ret;
2256 }
2257
2258 static void
2259 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2260 {
2261         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2262         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2263         struct i40e_vsi *vsi = pf->main_vsi;
2264         int status;
2265
2266         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2267                                                      true, NULL, true);
2268         if (status != I40E_SUCCESS)
2269                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2270
2271         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2272                                                         TRUE, NULL);
2273         if (status != I40E_SUCCESS)
2274                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2275
2276 }
2277
2278 static void
2279 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2280 {
2281         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2282         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2283         struct i40e_vsi *vsi = pf->main_vsi;
2284         int status;
2285
2286         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2287                                                      false, NULL, true);
2288         if (status != I40E_SUCCESS)
2289                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2290
2291         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2292                                                         false, NULL);
2293         if (status != I40E_SUCCESS)
2294                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2295 }
2296
2297 static void
2298 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2299 {
2300         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2301         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2302         struct i40e_vsi *vsi = pf->main_vsi;
2303         int ret;
2304
2305         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2306         if (ret != I40E_SUCCESS)
2307                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2308 }
2309
2310 static void
2311 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2312 {
2313         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2314         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2315         struct i40e_vsi *vsi = pf->main_vsi;
2316         int ret;
2317
2318         if (dev->data->promiscuous == 1)
2319                 return; /* must remain in all_multicast mode */
2320
2321         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2322                                 vsi->seid, FALSE, NULL);
2323         if (ret != I40E_SUCCESS)
2324                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2325 }
2326
2327 /*
2328  * Set device link up.
2329  */
2330 static int
2331 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2332 {
2333         /* re-apply link speed setting */
2334         return i40e_apply_link_speed(dev);
2335 }
2336
2337 /*
2338  * Set device link down.
2339  */
2340 static int
2341 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2342 {
2343         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2344         uint8_t abilities = 0;
2345         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2346
2347         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2348         return i40e_phy_conf_link(hw, abilities, speed, false);
2349 }
2350
2351 int
2352 i40e_dev_link_update(struct rte_eth_dev *dev,
2353                      int wait_to_complete)
2354 {
2355 #define CHECK_INTERVAL 100  /* 100ms */
2356 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2357         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2358         struct i40e_link_status link_status;
2359         struct rte_eth_link link, old;
2360         int status;
2361         unsigned rep_cnt = MAX_REPEAT_TIME;
2362         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2363
2364         memset(&link, 0, sizeof(link));
2365         memset(&old, 0, sizeof(old));
2366         memset(&link_status, 0, sizeof(link_status));
2367         rte_i40e_dev_atomic_read_link_status(dev, &old);
2368
2369         do {
2370                 /* Get link status information from hardware */
2371                 status = i40e_aq_get_link_info(hw, enable_lse,
2372                                                 &link_status, NULL);
2373                 if (status != I40E_SUCCESS) {
2374                         link.link_speed = ETH_SPEED_NUM_100M;
2375                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2376                         PMD_DRV_LOG(ERR, "Failed to get link info");
2377                         goto out;
2378                 }
2379
2380                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2381                 if (!wait_to_complete || link.link_status)
2382                         break;
2383
2384                 rte_delay_ms(CHECK_INTERVAL);
2385         } while (--rep_cnt);
2386
2387         if (!link.link_status)
2388                 goto out;
2389
2390         /* i40e uses full duplex only */
2391         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2392
2393         /* Parse the link status */
2394         switch (link_status.link_speed) {
2395         case I40E_LINK_SPEED_100MB:
2396                 link.link_speed = ETH_SPEED_NUM_100M;
2397                 break;
2398         case I40E_LINK_SPEED_1GB:
2399                 link.link_speed = ETH_SPEED_NUM_1G;
2400                 break;
2401         case I40E_LINK_SPEED_10GB:
2402                 link.link_speed = ETH_SPEED_NUM_10G;
2403                 break;
2404         case I40E_LINK_SPEED_20GB:
2405                 link.link_speed = ETH_SPEED_NUM_20G;
2406                 break;
2407         case I40E_LINK_SPEED_25GB:
2408                 link.link_speed = ETH_SPEED_NUM_25G;
2409                 break;
2410         case I40E_LINK_SPEED_40GB:
2411                 link.link_speed = ETH_SPEED_NUM_40G;
2412                 break;
2413         default:
2414                 link.link_speed = ETH_SPEED_NUM_100M;
2415                 break;
2416         }
2417
2418         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2419                         ETH_LINK_SPEED_FIXED);
2420
2421 out:
2422         rte_i40e_dev_atomic_write_link_status(dev, &link);
2423         if (link.link_status == old.link_status)
2424                 return -1;
2425
2426         i40e_notify_all_vfs_link_status(dev);
2427
2428         return 0;
2429 }
2430
2431 /* Get all the statistics of a VSI */
2432 void
2433 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2434 {
2435         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2436         struct i40e_eth_stats *nes = &vsi->eth_stats;
2437         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2438         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2439
2440         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2441                             vsi->offset_loaded, &oes->rx_bytes,
2442                             &nes->rx_bytes);
2443         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2444                             vsi->offset_loaded, &oes->rx_unicast,
2445                             &nes->rx_unicast);
2446         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2447                             vsi->offset_loaded, &oes->rx_multicast,
2448                             &nes->rx_multicast);
2449         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2450                             vsi->offset_loaded, &oes->rx_broadcast,
2451                             &nes->rx_broadcast);
2452         /* exclude CRC bytes */
2453         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2454                 nes->rx_broadcast) * ETHER_CRC_LEN;
2455
2456         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2457                             &oes->rx_discards, &nes->rx_discards);
2458         /* GLV_REPC not supported */
2459         /* GLV_RMPC not supported */
2460         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2461                             &oes->rx_unknown_protocol,
2462                             &nes->rx_unknown_protocol);
2463         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2464                             vsi->offset_loaded, &oes->tx_bytes,
2465                             &nes->tx_bytes);
2466         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2467                             vsi->offset_loaded, &oes->tx_unicast,
2468                             &nes->tx_unicast);
2469         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2470                             vsi->offset_loaded, &oes->tx_multicast,
2471                             &nes->tx_multicast);
2472         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2473                             vsi->offset_loaded,  &oes->tx_broadcast,
2474                             &nes->tx_broadcast);
2475         /* GLV_TDPC not supported */
2476         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2477                             &oes->tx_errors, &nes->tx_errors);
2478         vsi->offset_loaded = true;
2479
2480         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2481                     vsi->vsi_id);
2482         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2483         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2484         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2485         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2486         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2487         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2488                     nes->rx_unknown_protocol);
2489         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2490         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2491         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2492         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2493         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2494         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2495         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2496                     vsi->vsi_id);
2497 }
2498
2499 static void
2500 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2501 {
2502         unsigned int i;
2503         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2504         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2505
2506         /* Get rx/tx bytes of internal transfer packets */
2507         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2508                         I40E_GLV_GORCL(hw->port),
2509                         pf->offset_loaded,
2510                         &pf->internal_stats_offset.rx_bytes,
2511                         &pf->internal_stats.rx_bytes);
2512
2513         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2514                         I40E_GLV_GOTCL(hw->port),
2515                         pf->offset_loaded,
2516                         &pf->internal_stats_offset.tx_bytes,
2517                         &pf->internal_stats.tx_bytes);
2518         /* Get total internal rx packet count */
2519         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2520                             I40E_GLV_UPRCL(hw->port),
2521                             pf->offset_loaded,
2522                             &pf->internal_stats_offset.rx_unicast,
2523                             &pf->internal_stats.rx_unicast);
2524         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2525                             I40E_GLV_MPRCL(hw->port),
2526                             pf->offset_loaded,
2527                             &pf->internal_stats_offset.rx_multicast,
2528                             &pf->internal_stats.rx_multicast);
2529         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2530                             I40E_GLV_BPRCL(hw->port),
2531                             pf->offset_loaded,
2532                             &pf->internal_stats_offset.rx_broadcast,
2533                             &pf->internal_stats.rx_broadcast);
2534
2535         /* exclude CRC size */
2536         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2537                 pf->internal_stats.rx_multicast +
2538                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2539
2540         /* Get statistics of struct i40e_eth_stats */
2541         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2542                             I40E_GLPRT_GORCL(hw->port),
2543                             pf->offset_loaded, &os->eth.rx_bytes,
2544                             &ns->eth.rx_bytes);
2545         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2546                             I40E_GLPRT_UPRCL(hw->port),
2547                             pf->offset_loaded, &os->eth.rx_unicast,
2548                             &ns->eth.rx_unicast);
2549         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2550                             I40E_GLPRT_MPRCL(hw->port),
2551                             pf->offset_loaded, &os->eth.rx_multicast,
2552                             &ns->eth.rx_multicast);
2553         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2554                             I40E_GLPRT_BPRCL(hw->port),
2555                             pf->offset_loaded, &os->eth.rx_broadcast,
2556                             &ns->eth.rx_broadcast);
2557         /* Workaround: CRC size should not be included in byte statistics,
2558          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2559          */
2560         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2561                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2562
2563         /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2564          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2565          * value.
2566          */
2567         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2568                 ns->eth.rx_bytes = 0;
2569         /* exlude internal rx bytes */
2570         else
2571                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2572
2573         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2574                             pf->offset_loaded, &os->eth.rx_discards,
2575                             &ns->eth.rx_discards);
2576         /* GLPRT_REPC not supported */
2577         /* GLPRT_RMPC not supported */
2578         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2579                             pf->offset_loaded,
2580                             &os->eth.rx_unknown_protocol,
2581                             &ns->eth.rx_unknown_protocol);
2582         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2583                             I40E_GLPRT_GOTCL(hw->port),
2584                             pf->offset_loaded, &os->eth.tx_bytes,
2585                             &ns->eth.tx_bytes);
2586         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2587                             I40E_GLPRT_UPTCL(hw->port),
2588                             pf->offset_loaded, &os->eth.tx_unicast,
2589                             &ns->eth.tx_unicast);
2590         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2591                             I40E_GLPRT_MPTCL(hw->port),
2592                             pf->offset_loaded, &os->eth.tx_multicast,
2593                             &ns->eth.tx_multicast);
2594         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2595                             I40E_GLPRT_BPTCL(hw->port),
2596                             pf->offset_loaded, &os->eth.tx_broadcast,
2597                             &ns->eth.tx_broadcast);
2598         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2599                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2600
2601         /* exclude internal tx bytes */
2602         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2603                 ns->eth.tx_bytes = 0;
2604         else
2605                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2606
2607         /* GLPRT_TEPC not supported */
2608
2609         /* additional port specific stats */
2610         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2611                             pf->offset_loaded, &os->tx_dropped_link_down,
2612                             &ns->tx_dropped_link_down);
2613         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2614                             pf->offset_loaded, &os->crc_errors,
2615                             &ns->crc_errors);
2616         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2617                             pf->offset_loaded, &os->illegal_bytes,
2618                             &ns->illegal_bytes);
2619         /* GLPRT_ERRBC not supported */
2620         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2621                             pf->offset_loaded, &os->mac_local_faults,
2622                             &ns->mac_local_faults);
2623         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2624                             pf->offset_loaded, &os->mac_remote_faults,
2625                             &ns->mac_remote_faults);
2626         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2627                             pf->offset_loaded, &os->rx_length_errors,
2628                             &ns->rx_length_errors);
2629         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2630                             pf->offset_loaded, &os->link_xon_rx,
2631                             &ns->link_xon_rx);
2632         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2633                             pf->offset_loaded, &os->link_xoff_rx,
2634                             &ns->link_xoff_rx);
2635         for (i = 0; i < 8; i++) {
2636                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2637                                     pf->offset_loaded,
2638                                     &os->priority_xon_rx[i],
2639                                     &ns->priority_xon_rx[i]);
2640                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2641                                     pf->offset_loaded,
2642                                     &os->priority_xoff_rx[i],
2643                                     &ns->priority_xoff_rx[i]);
2644         }
2645         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2646                             pf->offset_loaded, &os->link_xon_tx,
2647                             &ns->link_xon_tx);
2648         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2649                             pf->offset_loaded, &os->link_xoff_tx,
2650                             &ns->link_xoff_tx);
2651         for (i = 0; i < 8; i++) {
2652                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2653                                     pf->offset_loaded,
2654                                     &os->priority_xon_tx[i],
2655                                     &ns->priority_xon_tx[i]);
2656                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2657                                     pf->offset_loaded,
2658                                     &os->priority_xoff_tx[i],
2659                                     &ns->priority_xoff_tx[i]);
2660                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2661                                     pf->offset_loaded,
2662                                     &os->priority_xon_2_xoff[i],
2663                                     &ns->priority_xon_2_xoff[i]);
2664         }
2665         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2666                             I40E_GLPRT_PRC64L(hw->port),
2667                             pf->offset_loaded, &os->rx_size_64,
2668                             &ns->rx_size_64);
2669         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2670                             I40E_GLPRT_PRC127L(hw->port),
2671                             pf->offset_loaded, &os->rx_size_127,
2672                             &ns->rx_size_127);
2673         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2674                             I40E_GLPRT_PRC255L(hw->port),
2675                             pf->offset_loaded, &os->rx_size_255,
2676                             &ns->rx_size_255);
2677         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2678                             I40E_GLPRT_PRC511L(hw->port),
2679                             pf->offset_loaded, &os->rx_size_511,
2680                             &ns->rx_size_511);
2681         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2682                             I40E_GLPRT_PRC1023L(hw->port),
2683                             pf->offset_loaded, &os->rx_size_1023,
2684                             &ns->rx_size_1023);
2685         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2686                             I40E_GLPRT_PRC1522L(hw->port),
2687                             pf->offset_loaded, &os->rx_size_1522,
2688                             &ns->rx_size_1522);
2689         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2690                             I40E_GLPRT_PRC9522L(hw->port),
2691                             pf->offset_loaded, &os->rx_size_big,
2692                             &ns->rx_size_big);
2693         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2694                             pf->offset_loaded, &os->rx_undersize,
2695                             &ns->rx_undersize);
2696         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2697                             pf->offset_loaded, &os->rx_fragments,
2698                             &ns->rx_fragments);
2699         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2700                             pf->offset_loaded, &os->rx_oversize,
2701                             &ns->rx_oversize);
2702         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2703                             pf->offset_loaded, &os->rx_jabber,
2704                             &ns->rx_jabber);
2705         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2706                             I40E_GLPRT_PTC64L(hw->port),
2707                             pf->offset_loaded, &os->tx_size_64,
2708                             &ns->tx_size_64);
2709         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2710                             I40E_GLPRT_PTC127L(hw->port),
2711                             pf->offset_loaded, &os->tx_size_127,
2712                             &ns->tx_size_127);
2713         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2714                             I40E_GLPRT_PTC255L(hw->port),
2715                             pf->offset_loaded, &os->tx_size_255,
2716                             &ns->tx_size_255);
2717         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2718                             I40E_GLPRT_PTC511L(hw->port),
2719                             pf->offset_loaded, &os->tx_size_511,
2720                             &ns->tx_size_511);
2721         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2722                             I40E_GLPRT_PTC1023L(hw->port),
2723                             pf->offset_loaded, &os->tx_size_1023,
2724                             &ns->tx_size_1023);
2725         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2726                             I40E_GLPRT_PTC1522L(hw->port),
2727                             pf->offset_loaded, &os->tx_size_1522,
2728                             &ns->tx_size_1522);
2729         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2730                             I40E_GLPRT_PTC9522L(hw->port),
2731                             pf->offset_loaded, &os->tx_size_big,
2732                             &ns->tx_size_big);
2733         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2734                            pf->offset_loaded,
2735                            &os->fd_sb_match, &ns->fd_sb_match);
2736         /* GLPRT_MSPDC not supported */
2737         /* GLPRT_XEC not supported */
2738
2739         pf->offset_loaded = true;
2740
2741         if (pf->main_vsi)
2742                 i40e_update_vsi_stats(pf->main_vsi);
2743 }
2744
2745 /* Get all statistics of a port */
2746 static int
2747 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2748 {
2749         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2750         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2751         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2752         unsigned i;
2753
2754         /* call read registers - updates values, now write them to struct */
2755         i40e_read_stats_registers(pf, hw);
2756
2757         stats->ipackets = ns->eth.rx_unicast +
2758                         ns->eth.rx_multicast +
2759                         ns->eth.rx_broadcast -
2760                         ns->eth.rx_discards -
2761                         pf->main_vsi->eth_stats.rx_discards;
2762         stats->opackets = ns->eth.tx_unicast +
2763                         ns->eth.tx_multicast +
2764                         ns->eth.tx_broadcast;
2765         stats->ibytes   = ns->eth.rx_bytes;
2766         stats->obytes   = ns->eth.tx_bytes;
2767         stats->oerrors  = ns->eth.tx_errors +
2768                         pf->main_vsi->eth_stats.tx_errors;
2769
2770         /* Rx Errors */
2771         stats->imissed  = ns->eth.rx_discards +
2772                         pf->main_vsi->eth_stats.rx_discards;
2773         stats->ierrors  = ns->crc_errors +
2774                         ns->rx_length_errors + ns->rx_undersize +
2775                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2776
2777         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2778         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2779         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2780         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2781         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2782         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2783         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2784                     ns->eth.rx_unknown_protocol);
2785         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2786         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2787         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2788         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2789         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2790         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2791
2792         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2793                     ns->tx_dropped_link_down);
2794         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2795         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2796                     ns->illegal_bytes);
2797         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2798         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2799                     ns->mac_local_faults);
2800         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2801                     ns->mac_remote_faults);
2802         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2803                     ns->rx_length_errors);
2804         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2805         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2806         for (i = 0; i < 8; i++) {
2807                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2808                                 i, ns->priority_xon_rx[i]);
2809                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2810                                 i, ns->priority_xoff_rx[i]);
2811         }
2812         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2813         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2814         for (i = 0; i < 8; i++) {
2815                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2816                                 i, ns->priority_xon_tx[i]);
2817                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2818                                 i, ns->priority_xoff_tx[i]);
2819                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2820                                 i, ns->priority_xon_2_xoff[i]);
2821         }
2822         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2823         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2824         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2825         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2826         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2827         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2828         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2829         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2830         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2831         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2832         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2833         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2834         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2835         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2836         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2837         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2838         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2839         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2840         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2841                         ns->mac_short_packet_dropped);
2842         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2843                     ns->checksum_error);
2844         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2845         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2846         return 0;
2847 }
2848
2849 /* Reset the statistics */
2850 static void
2851 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2852 {
2853         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2854         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2855
2856         /* Mark PF and VSI stats to update the offset, aka "reset" */
2857         pf->offset_loaded = false;
2858         if (pf->main_vsi)
2859                 pf->main_vsi->offset_loaded = false;
2860
2861         /* read the stats, reading current register values into offset */
2862         i40e_read_stats_registers(pf, hw);
2863 }
2864
2865 static uint32_t
2866 i40e_xstats_calc_num(void)
2867 {
2868         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2869                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2870                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2871 }
2872
2873 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2874                                      struct rte_eth_xstat_name *xstats_names,
2875                                      __rte_unused unsigned limit)
2876 {
2877         unsigned count = 0;
2878         unsigned i, prio;
2879
2880         if (xstats_names == NULL)
2881                 return i40e_xstats_calc_num();
2882
2883         /* Note: limit checked in rte_eth_xstats_names() */
2884
2885         /* Get stats from i40e_eth_stats struct */
2886         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2887                 snprintf(xstats_names[count].name,
2888                          sizeof(xstats_names[count].name),
2889                          "%s", rte_i40e_stats_strings[i].name);
2890                 count++;
2891         }
2892
2893         /* Get individiual stats from i40e_hw_port struct */
2894         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2895                 snprintf(xstats_names[count].name,
2896                         sizeof(xstats_names[count].name),
2897                          "%s", rte_i40e_hw_port_strings[i].name);
2898                 count++;
2899         }
2900
2901         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2902                 for (prio = 0; prio < 8; prio++) {
2903                         snprintf(xstats_names[count].name,
2904                                  sizeof(xstats_names[count].name),
2905                                  "rx_priority%u_%s", prio,
2906                                  rte_i40e_rxq_prio_strings[i].name);
2907                         count++;
2908                 }
2909         }
2910
2911         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2912                 for (prio = 0; prio < 8; prio++) {
2913                         snprintf(xstats_names[count].name,
2914                                  sizeof(xstats_names[count].name),
2915                                  "tx_priority%u_%s", prio,
2916                                  rte_i40e_txq_prio_strings[i].name);
2917                         count++;
2918                 }
2919         }
2920         return count;
2921 }
2922
2923 static int
2924 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2925                     unsigned n)
2926 {
2927         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2928         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2929         unsigned i, count, prio;
2930         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2931
2932         count = i40e_xstats_calc_num();
2933         if (n < count)
2934                 return count;
2935
2936         i40e_read_stats_registers(pf, hw);
2937
2938         if (xstats == NULL)
2939                 return 0;
2940
2941         count = 0;
2942
2943         /* Get stats from i40e_eth_stats struct */
2944         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2945                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2946                         rte_i40e_stats_strings[i].offset);
2947                 xstats[count].id = count;
2948                 count++;
2949         }
2950
2951         /* Get individiual stats from i40e_hw_port struct */
2952         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2953                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2954                         rte_i40e_hw_port_strings[i].offset);
2955                 xstats[count].id = count;
2956                 count++;
2957         }
2958
2959         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2960                 for (prio = 0; prio < 8; prio++) {
2961                         xstats[count].value =
2962                                 *(uint64_t *)(((char *)hw_stats) +
2963                                 rte_i40e_rxq_prio_strings[i].offset +
2964                                 (sizeof(uint64_t) * prio));
2965                         xstats[count].id = count;
2966                         count++;
2967                 }
2968         }
2969
2970         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2971                 for (prio = 0; prio < 8; prio++) {
2972                         xstats[count].value =
2973                                 *(uint64_t *)(((char *)hw_stats) +
2974                                 rte_i40e_txq_prio_strings[i].offset +
2975                                 (sizeof(uint64_t) * prio));
2976                         xstats[count].id = count;
2977                         count++;
2978                 }
2979         }
2980
2981         return count;
2982 }
2983
2984 static int
2985 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2986                                  __rte_unused uint16_t queue_id,
2987                                  __rte_unused uint8_t stat_idx,
2988                                  __rte_unused uint8_t is_rx)
2989 {
2990         PMD_INIT_FUNC_TRACE();
2991
2992         return -ENOSYS;
2993 }
2994
2995 static int
2996 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2997 {
2998         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2999         u32 full_ver;
3000         u8 ver, patch;
3001         u16 build;
3002         int ret;
3003
3004         full_ver = hw->nvm.oem_ver;
3005         ver = (u8)(full_ver >> 24);
3006         build = (u16)((full_ver >> 8) & 0xffff);
3007         patch = (u8)(full_ver & 0xff);
3008
3009         ret = snprintf(fw_version, fw_size,
3010                  "%d.%d%d 0x%08x %d.%d.%d",
3011                  ((hw->nvm.version >> 12) & 0xf),
3012                  ((hw->nvm.version >> 4) & 0xff),
3013                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3014                  ver, build, patch);
3015
3016         ret += 1; /* add the size of '\0' */
3017         if (fw_size < (u32)ret)
3018                 return ret;
3019         else
3020                 return 0;
3021 }
3022
3023 static void
3024 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3025 {
3026         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3027         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3028         struct i40e_vsi *vsi = pf->main_vsi;
3029         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3030
3031         dev_info->pci_dev = pci_dev;
3032         dev_info->max_rx_queues = vsi->nb_qps;
3033         dev_info->max_tx_queues = vsi->nb_qps;
3034         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3035         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3036         dev_info->max_mac_addrs = vsi->max_macaddrs;
3037         dev_info->max_vfs = pci_dev->max_vfs;
3038         dev_info->rx_offload_capa =
3039                 DEV_RX_OFFLOAD_VLAN_STRIP |
3040                 DEV_RX_OFFLOAD_QINQ_STRIP |
3041                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3042                 DEV_RX_OFFLOAD_UDP_CKSUM |
3043                 DEV_RX_OFFLOAD_TCP_CKSUM;
3044         dev_info->tx_offload_capa =
3045                 DEV_TX_OFFLOAD_VLAN_INSERT |
3046                 DEV_TX_OFFLOAD_QINQ_INSERT |
3047                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3048                 DEV_TX_OFFLOAD_UDP_CKSUM |
3049                 DEV_TX_OFFLOAD_TCP_CKSUM |
3050                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3051                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3052                 DEV_TX_OFFLOAD_TCP_TSO |
3053                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3054                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3055                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3056                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3057         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3058                                                 sizeof(uint32_t);
3059         dev_info->reta_size = pf->hash_lut_size;
3060         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3061
3062         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3063                 .rx_thresh = {
3064                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3065                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3066                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3067                 },
3068                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3069                 .rx_drop_en = 0,
3070         };
3071
3072         dev_info->default_txconf = (struct rte_eth_txconf) {
3073                 .tx_thresh = {
3074                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3075                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3076                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3077                 },
3078                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3079                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3080                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3081                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3082         };
3083
3084         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3085                 .nb_max = I40E_MAX_RING_DESC,
3086                 .nb_min = I40E_MIN_RING_DESC,
3087                 .nb_align = I40E_ALIGN_RING_DESC,
3088         };
3089
3090         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3091                 .nb_max = I40E_MAX_RING_DESC,
3092                 .nb_min = I40E_MIN_RING_DESC,
3093                 .nb_align = I40E_ALIGN_RING_DESC,
3094                 .nb_seg_max = I40E_TX_MAX_SEG,
3095                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3096         };
3097
3098         if (pf->flags & I40E_FLAG_VMDQ) {
3099                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3100                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3101                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3102                                                 pf->max_nb_vmdq_vsi;
3103                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3104                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3105                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3106         }
3107
3108         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3109                 /* For XL710 */
3110                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3111         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3112                 /* For XXV710 */
3113                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3114         else
3115                 /* For X710 */
3116                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3117 }
3118
3119 static int
3120 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3121 {
3122         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3123         struct i40e_vsi *vsi = pf->main_vsi;
3124         PMD_INIT_FUNC_TRACE();
3125
3126         if (on)
3127                 return i40e_vsi_add_vlan(vsi, vlan_id);
3128         else
3129                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3130 }
3131
3132 static int
3133 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3134                                 enum rte_vlan_type vlan_type,
3135                                 uint16_t tpid, int qinq)
3136 {
3137         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3138         uint64_t reg_r = 0;
3139         uint64_t reg_w = 0;
3140         uint16_t reg_id = 3;
3141         int ret;
3142
3143         if (qinq) {
3144                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3145                         reg_id = 2;
3146         }
3147
3148         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3149                                           &reg_r, NULL);
3150         if (ret != I40E_SUCCESS) {
3151                 PMD_DRV_LOG(ERR,
3152                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3153                            reg_id);
3154                 return -EIO;
3155         }
3156         PMD_DRV_LOG(DEBUG,
3157                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3158                     reg_id, reg_r);
3159
3160         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3161         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3162         if (reg_r == reg_w) {
3163                 PMD_DRV_LOG(DEBUG, "No need to write");
3164                 return 0;
3165         }
3166
3167         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3168                                            reg_w, NULL);
3169         if (ret != I40E_SUCCESS) {
3170                 PMD_DRV_LOG(ERR,
3171                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3172                             reg_id);
3173                 return -EIO;
3174         }
3175         PMD_DRV_LOG(DEBUG,
3176                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3177                     reg_w, reg_id);
3178
3179         return 0;
3180 }
3181
3182 static int
3183 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3184                    enum rte_vlan_type vlan_type,
3185                    uint16_t tpid)
3186 {
3187         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3188         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3189         int ret = 0;
3190
3191         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3192              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3193             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3194                 PMD_DRV_LOG(ERR,
3195                             "Unsupported vlan type.");
3196                 return -EINVAL;
3197         }
3198         /* 802.1ad frames ability is added in NVM API 1.7*/
3199         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3200                 if (qinq) {
3201                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3202                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3203                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3204                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3205                 } else {
3206                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3207                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3208                 }
3209                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3210                 if (ret != I40E_SUCCESS) {
3211                         PMD_DRV_LOG(ERR,
3212                                     "Set switch config failed aq_err: %d",
3213                                     hw->aq.asq_last_status);
3214                         ret = -EIO;
3215                 }
3216         } else
3217                 /* If NVM API < 1.7, keep the register setting */
3218                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3219                                                       tpid, qinq);
3220
3221         return ret;
3222 }
3223
3224 static void
3225 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3226 {
3227         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3228         struct i40e_vsi *vsi = pf->main_vsi;
3229
3230         if (mask & ETH_VLAN_FILTER_MASK) {
3231                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3232                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3233                 else
3234                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3235         }
3236
3237         if (mask & ETH_VLAN_STRIP_MASK) {
3238                 /* Enable or disable VLAN stripping */
3239                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3240                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3241                 else
3242                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3243         }
3244
3245         if (mask & ETH_VLAN_EXTEND_MASK) {
3246                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3247                         i40e_vsi_config_double_vlan(vsi, TRUE);
3248                         /* Set global registers with default ethertype. */
3249                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3250                                            ETHER_TYPE_VLAN);
3251                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3252                                            ETHER_TYPE_VLAN);
3253                 }
3254                 else
3255                         i40e_vsi_config_double_vlan(vsi, FALSE);
3256         }
3257 }
3258
3259 static void
3260 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3261                           __rte_unused uint16_t queue,
3262                           __rte_unused int on)
3263 {
3264         PMD_INIT_FUNC_TRACE();
3265 }
3266
3267 static int
3268 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3269 {
3270         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3271         struct i40e_vsi *vsi = pf->main_vsi;
3272         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3273         struct i40e_vsi_vlan_pvid_info info;
3274
3275         memset(&info, 0, sizeof(info));
3276         info.on = on;
3277         if (info.on)
3278                 info.config.pvid = pvid;
3279         else {
3280                 info.config.reject.tagged =
3281                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3282                 info.config.reject.untagged =
3283                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3284         }
3285
3286         return i40e_vsi_vlan_pvid_set(vsi, &info);
3287 }
3288
3289 static int
3290 i40e_dev_led_on(struct rte_eth_dev *dev)
3291 {
3292         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3293         uint32_t mode = i40e_led_get(hw);
3294
3295         if (mode == 0)
3296                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3297
3298         return 0;
3299 }
3300
3301 static int
3302 i40e_dev_led_off(struct rte_eth_dev *dev)
3303 {
3304         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3305         uint32_t mode = i40e_led_get(hw);
3306
3307         if (mode != 0)
3308                 i40e_led_set(hw, 0, false);
3309
3310         return 0;
3311 }
3312
3313 static int
3314 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3315 {
3316         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3317         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3318
3319         fc_conf->pause_time = pf->fc_conf.pause_time;
3320
3321         /* read out from register, in case they are modified by other port */
3322         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3323                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3324         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3325                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3326
3327         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3328         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3329
3330          /* Return current mode according to actual setting*/
3331         switch (hw->fc.current_mode) {
3332         case I40E_FC_FULL:
3333                 fc_conf->mode = RTE_FC_FULL;
3334                 break;
3335         case I40E_FC_TX_PAUSE:
3336                 fc_conf->mode = RTE_FC_TX_PAUSE;
3337                 break;
3338         case I40E_FC_RX_PAUSE:
3339                 fc_conf->mode = RTE_FC_RX_PAUSE;
3340                 break;
3341         case I40E_FC_NONE:
3342         default:
3343                 fc_conf->mode = RTE_FC_NONE;
3344         };
3345
3346         return 0;
3347 }
3348
3349 static int
3350 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3351 {
3352         uint32_t mflcn_reg, fctrl_reg, reg;
3353         uint32_t max_high_water;
3354         uint8_t i, aq_failure;
3355         int err;
3356         struct i40e_hw *hw;
3357         struct i40e_pf *pf;
3358         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3359                 [RTE_FC_NONE] = I40E_FC_NONE,
3360                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3361                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3362                 [RTE_FC_FULL] = I40E_FC_FULL
3363         };
3364
3365         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3366
3367         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3368         if ((fc_conf->high_water > max_high_water) ||
3369                         (fc_conf->high_water < fc_conf->low_water)) {
3370                 PMD_INIT_LOG(ERR,
3371                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3372                         max_high_water);
3373                 return -EINVAL;
3374         }
3375
3376         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3377         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3378         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3379
3380         pf->fc_conf.pause_time = fc_conf->pause_time;
3381         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3382         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3383
3384         PMD_INIT_FUNC_TRACE();
3385
3386         /* All the link flow control related enable/disable register
3387          * configuration is handle by the F/W
3388          */
3389         err = i40e_set_fc(hw, &aq_failure, true);
3390         if (err < 0)
3391                 return -ENOSYS;
3392
3393         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3394                 /* Configure flow control refresh threshold,
3395                  * the value for stat_tx_pause_refresh_timer[8]
3396                  * is used for global pause operation.
3397                  */
3398
3399                 I40E_WRITE_REG(hw,
3400                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3401                                pf->fc_conf.pause_time);
3402
3403                 /* configure the timer value included in transmitted pause
3404                  * frame,
3405                  * the value for stat_tx_pause_quanta[8] is used for global
3406                  * pause operation
3407                  */
3408                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3409                                pf->fc_conf.pause_time);
3410
3411                 fctrl_reg = I40E_READ_REG(hw,
3412                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3413
3414                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3415                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3416                 else
3417                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3418
3419                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3420                                fctrl_reg);
3421         } else {
3422                 /* Configure pause time (2 TCs per register) */
3423                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3424                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3425                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3426
3427                 /* Configure flow control refresh threshold value */
3428                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3429                                pf->fc_conf.pause_time / 2);
3430
3431                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3432
3433                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3434                  *depending on configuration
3435                  */
3436                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3437                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3438                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3439                 } else {
3440                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3441                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3442                 }
3443
3444                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3445         }
3446
3447         /* config the water marker both based on the packets and bytes */
3448         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3449                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3450                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3451         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3452                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3453                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3454         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3455                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3456                        << I40E_KILOSHIFT);
3457         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3458                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3459                        << I40E_KILOSHIFT);
3460
3461         I40E_WRITE_FLUSH(hw);
3462
3463         return 0;
3464 }
3465
3466 static int
3467 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3468                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3469 {
3470         PMD_INIT_FUNC_TRACE();
3471
3472         return -ENOSYS;
3473 }
3474
3475 /* Add a MAC address, and update filters */
3476 static int
3477 i40e_macaddr_add(struct rte_eth_dev *dev,
3478                  struct ether_addr *mac_addr,
3479                  __rte_unused uint32_t index,
3480                  uint32_t pool)
3481 {
3482         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3483         struct i40e_mac_filter_info mac_filter;
3484         struct i40e_vsi *vsi;
3485         int ret;
3486
3487         /* If VMDQ not enabled or configured, return */
3488         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3489                           !pf->nb_cfg_vmdq_vsi)) {
3490                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3491                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3492                         pool);
3493                 return -ENOTSUP;
3494         }
3495
3496         if (pool > pf->nb_cfg_vmdq_vsi) {
3497                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3498                                 pool, pf->nb_cfg_vmdq_vsi);
3499                 return -EINVAL;
3500         }
3501
3502         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3503         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3504                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3505         else
3506                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3507
3508         if (pool == 0)
3509                 vsi = pf->main_vsi;
3510         else
3511                 vsi = pf->vmdq[pool - 1].vsi;
3512
3513         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3514         if (ret != I40E_SUCCESS) {
3515                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3516                 return -ENODEV;
3517         }
3518         return 0;
3519 }
3520
3521 /* Remove a MAC address, and update filters */
3522 static void
3523 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3524 {
3525         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3526         struct i40e_vsi *vsi;
3527         struct rte_eth_dev_data *data = dev->data;
3528         struct ether_addr *macaddr;
3529         int ret;
3530         uint32_t i;
3531         uint64_t pool_sel;
3532
3533         macaddr = &(data->mac_addrs[index]);
3534
3535         pool_sel = dev->data->mac_pool_sel[index];
3536
3537         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3538                 if (pool_sel & (1ULL << i)) {
3539                         if (i == 0)
3540                                 vsi = pf->main_vsi;
3541                         else {
3542                                 /* No VMDQ pool enabled or configured */
3543                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3544                                         (i > pf->nb_cfg_vmdq_vsi)) {
3545                                         PMD_DRV_LOG(ERR,
3546                                                 "No VMDQ pool enabled/configured");
3547                                         return;
3548                                 }
3549                                 vsi = pf->vmdq[i - 1].vsi;
3550                         }
3551                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3552
3553                         if (ret) {
3554                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3555                                 return;
3556                         }
3557                 }
3558         }
3559 }
3560
3561 /* Set perfect match or hash match of MAC and VLAN for a VF */
3562 static int
3563 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3564                  struct rte_eth_mac_filter *filter,
3565                  bool add)
3566 {
3567         struct i40e_hw *hw;
3568         struct i40e_mac_filter_info mac_filter;
3569         struct ether_addr old_mac;
3570         struct ether_addr *new_mac;
3571         struct i40e_pf_vf *vf = NULL;
3572         uint16_t vf_id;
3573         int ret;
3574
3575         if (pf == NULL) {
3576                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3577                 return -EINVAL;
3578         }
3579         hw = I40E_PF_TO_HW(pf);
3580
3581         if (filter == NULL) {
3582                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3583                 return -EINVAL;
3584         }
3585
3586         new_mac = &filter->mac_addr;
3587
3588         if (is_zero_ether_addr(new_mac)) {
3589                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3590                 return -EINVAL;
3591         }
3592
3593         vf_id = filter->dst_id;
3594
3595         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3596                 PMD_DRV_LOG(ERR, "Invalid argument.");
3597                 return -EINVAL;
3598         }
3599         vf = &pf->vfs[vf_id];
3600
3601         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3602                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3603                 return -EINVAL;
3604         }
3605
3606         if (add) {
3607                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3608                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3609                                 ETHER_ADDR_LEN);
3610                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3611                                  ETHER_ADDR_LEN);
3612
3613                 mac_filter.filter_type = filter->filter_type;
3614                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3615                 if (ret != I40E_SUCCESS) {
3616                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3617                         return -1;
3618                 }
3619                 ether_addr_copy(new_mac, &pf->dev_addr);
3620         } else {
3621                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3622                                 ETHER_ADDR_LEN);
3623                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3624                 if (ret != I40E_SUCCESS) {
3625                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3626                         return -1;
3627                 }
3628
3629                 /* Clear device address as it has been removed */
3630                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3631                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3632         }
3633
3634         return 0;
3635 }
3636
3637 /* MAC filter handle */
3638 static int
3639 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3640                 void *arg)
3641 {
3642         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3643         struct rte_eth_mac_filter *filter;
3644         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3645         int ret = I40E_NOT_SUPPORTED;
3646
3647         filter = (struct rte_eth_mac_filter *)(arg);
3648
3649         switch (filter_op) {
3650         case RTE_ETH_FILTER_NOP:
3651                 ret = I40E_SUCCESS;
3652                 break;
3653         case RTE_ETH_FILTER_ADD:
3654                 i40e_pf_disable_irq0(hw);
3655                 if (filter->is_vf)
3656                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3657                 i40e_pf_enable_irq0(hw);
3658                 break;
3659         case RTE_ETH_FILTER_DELETE:
3660                 i40e_pf_disable_irq0(hw);
3661                 if (filter->is_vf)
3662                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3663                 i40e_pf_enable_irq0(hw);
3664                 break;
3665         default:
3666                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3667                 ret = I40E_ERR_PARAM;
3668                 break;
3669         }
3670
3671         return ret;
3672 }
3673
3674 static int
3675 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3676 {
3677         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3678         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3679         int ret;
3680
3681         if (!lut)
3682                 return -EINVAL;
3683
3684         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3685                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3686                                           lut, lut_size);
3687                 if (ret) {
3688                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3689                         return ret;
3690                 }
3691         } else {
3692                 uint32_t *lut_dw = (uint32_t *)lut;
3693                 uint16_t i, lut_size_dw = lut_size / 4;
3694
3695                 for (i = 0; i < lut_size_dw; i++)
3696                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3697         }
3698
3699         return 0;
3700 }
3701
3702 static int
3703 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3704 {
3705         struct i40e_pf *pf;
3706         struct i40e_hw *hw;
3707         int ret;
3708
3709         if (!vsi || !lut)
3710                 return -EINVAL;
3711
3712         pf = I40E_VSI_TO_PF(vsi);
3713         hw = I40E_VSI_TO_HW(vsi);
3714
3715         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3716                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3717                                           lut, lut_size);
3718                 if (ret) {
3719                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3720                         return ret;
3721                 }
3722         } else {
3723                 uint32_t *lut_dw = (uint32_t *)lut;
3724                 uint16_t i, lut_size_dw = lut_size / 4;
3725
3726                 for (i = 0; i < lut_size_dw; i++)
3727                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3728                 I40E_WRITE_FLUSH(hw);
3729         }
3730
3731         return 0;
3732 }
3733
3734 static int
3735 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3736                          struct rte_eth_rss_reta_entry64 *reta_conf,
3737                          uint16_t reta_size)
3738 {
3739         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3740         uint16_t i, lut_size = pf->hash_lut_size;
3741         uint16_t idx, shift;
3742         uint8_t *lut;
3743         int ret;
3744
3745         if (reta_size != lut_size ||
3746                 reta_size > ETH_RSS_RETA_SIZE_512) {
3747                 PMD_DRV_LOG(ERR,
3748                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3749                         reta_size, lut_size);
3750                 return -EINVAL;
3751         }
3752
3753         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3754         if (!lut) {
3755                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3756                 return -ENOMEM;
3757         }
3758         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3759         if (ret)
3760                 goto out;
3761         for (i = 0; i < reta_size; i++) {
3762                 idx = i / RTE_RETA_GROUP_SIZE;
3763                 shift = i % RTE_RETA_GROUP_SIZE;
3764                 if (reta_conf[idx].mask & (1ULL << shift))
3765                         lut[i] = reta_conf[idx].reta[shift];
3766         }
3767         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3768
3769 out:
3770         rte_free(lut);
3771
3772         return ret;
3773 }
3774
3775 static int
3776 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3777                         struct rte_eth_rss_reta_entry64 *reta_conf,
3778                         uint16_t reta_size)
3779 {
3780         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3781         uint16_t i, lut_size = pf->hash_lut_size;
3782         uint16_t idx, shift;
3783         uint8_t *lut;
3784         int ret;
3785
3786         if (reta_size != lut_size ||
3787                 reta_size > ETH_RSS_RETA_SIZE_512) {
3788                 PMD_DRV_LOG(ERR,
3789                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3790                         reta_size, lut_size);
3791                 return -EINVAL;
3792         }
3793
3794         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3795         if (!lut) {
3796                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3797                 return -ENOMEM;
3798         }
3799
3800         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3801         if (ret)
3802                 goto out;
3803         for (i = 0; i < reta_size; i++) {
3804                 idx = i / RTE_RETA_GROUP_SIZE;
3805                 shift = i % RTE_RETA_GROUP_SIZE;
3806                 if (reta_conf[idx].mask & (1ULL << shift))
3807                         reta_conf[idx].reta[shift] = lut[i];
3808         }
3809
3810 out:
3811         rte_free(lut);
3812
3813         return ret;
3814 }
3815
3816 /**
3817  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3818  * @hw:   pointer to the HW structure
3819  * @mem:  pointer to mem struct to fill out
3820  * @size: size of memory requested
3821  * @alignment: what to align the allocation to
3822  **/
3823 enum i40e_status_code
3824 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3825                         struct i40e_dma_mem *mem,
3826                         u64 size,
3827                         u32 alignment)
3828 {
3829         const struct rte_memzone *mz = NULL;
3830         char z_name[RTE_MEMZONE_NAMESIZE];
3831
3832         if (!mem)
3833                 return I40E_ERR_PARAM;
3834
3835         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3836         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3837                                          alignment, RTE_PGSIZE_2M);
3838         if (!mz)
3839                 return I40E_ERR_NO_MEMORY;
3840
3841         mem->size = size;
3842         mem->va = mz->addr;
3843         mem->pa = mz->phys_addr;
3844         mem->zone = (const void *)mz;
3845         PMD_DRV_LOG(DEBUG,
3846                 "memzone %s allocated with physical address: %"PRIu64,
3847                 mz->name, mem->pa);
3848
3849         return I40E_SUCCESS;
3850 }
3851
3852 /**
3853  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3854  * @hw:   pointer to the HW structure
3855  * @mem:  ptr to mem struct to free
3856  **/
3857 enum i40e_status_code
3858 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3859                     struct i40e_dma_mem *mem)
3860 {
3861         if (!mem)
3862                 return I40E_ERR_PARAM;
3863
3864         PMD_DRV_LOG(DEBUG,
3865                 "memzone %s to be freed with physical address: %"PRIu64,
3866                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3867         rte_memzone_free((const struct rte_memzone *)mem->zone);
3868         mem->zone = NULL;
3869         mem->va = NULL;
3870         mem->pa = (u64)0;
3871
3872         return I40E_SUCCESS;
3873 }
3874
3875 /**
3876  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3877  * @hw:   pointer to the HW structure
3878  * @mem:  pointer to mem struct to fill out
3879  * @size: size of memory requested
3880  **/
3881 enum i40e_status_code
3882 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3883                          struct i40e_virt_mem *mem,
3884                          u32 size)
3885 {
3886         if (!mem)
3887                 return I40E_ERR_PARAM;
3888
3889         mem->size = size;
3890         mem->va = rte_zmalloc("i40e", size, 0);
3891
3892         if (mem->va)
3893                 return I40E_SUCCESS;
3894         else
3895                 return I40E_ERR_NO_MEMORY;
3896 }
3897
3898 /**
3899  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3900  * @hw:   pointer to the HW structure
3901  * @mem:  pointer to mem struct to free
3902  **/
3903 enum i40e_status_code
3904 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3905                      struct i40e_virt_mem *mem)
3906 {
3907         if (!mem)
3908                 return I40E_ERR_PARAM;
3909
3910         rte_free(mem->va);
3911         mem->va = NULL;
3912
3913         return I40E_SUCCESS;
3914 }
3915
3916 void
3917 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3918 {
3919         rte_spinlock_init(&sp->spinlock);
3920 }
3921
3922 void
3923 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3924 {
3925         rte_spinlock_lock(&sp->spinlock);
3926 }
3927
3928 void
3929 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3930 {
3931         rte_spinlock_unlock(&sp->spinlock);
3932 }
3933
3934 void
3935 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3936 {
3937         return;
3938 }
3939
3940 /**
3941  * Get the hardware capabilities, which will be parsed
3942  * and saved into struct i40e_hw.
3943  */
3944 static int
3945 i40e_get_cap(struct i40e_hw *hw)
3946 {
3947         struct i40e_aqc_list_capabilities_element_resp *buf;
3948         uint16_t len, size = 0;
3949         int ret;
3950
3951         /* Calculate a huge enough buff for saving response data temporarily */
3952         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3953                                                 I40E_MAX_CAP_ELE_NUM;
3954         buf = rte_zmalloc("i40e", len, 0);
3955         if (!buf) {
3956                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3957                 return I40E_ERR_NO_MEMORY;
3958         }
3959
3960         /* Get, parse the capabilities and save it to hw */
3961         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3962                         i40e_aqc_opc_list_func_capabilities, NULL);
3963         if (ret != I40E_SUCCESS)
3964                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3965
3966         /* Free the temporary buffer after being used */
3967         rte_free(buf);
3968
3969         return ret;
3970 }
3971
3972 static int
3973 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3974 {
3975         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3976         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3977         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3978         uint16_t qp_count = 0, vsi_count = 0;
3979
3980         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3981                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3982                 return -EINVAL;
3983         }
3984         /* Add the parameter init for LFC */
3985         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3986         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3987         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3988
3989         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3990         pf->max_num_vsi = hw->func_caps.num_vsis;
3991         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3992         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3993         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3994
3995         /* FDir queue/VSI allocation */
3996         pf->fdir_qp_offset = 0;
3997         if (hw->func_caps.fd) {
3998                 pf->flags |= I40E_FLAG_FDIR;
3999                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4000         } else {
4001                 pf->fdir_nb_qps = 0;
4002         }
4003         qp_count += pf->fdir_nb_qps;
4004         vsi_count += 1;
4005
4006         /* LAN queue/VSI allocation */
4007         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4008         if (!hw->func_caps.rss) {
4009                 pf->lan_nb_qps = 1;
4010         } else {
4011                 pf->flags |= I40E_FLAG_RSS;
4012                 if (hw->mac.type == I40E_MAC_X722)
4013                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4014                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4015         }
4016         qp_count += pf->lan_nb_qps;
4017         vsi_count += 1;
4018
4019         /* VF queue/VSI allocation */
4020         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4021         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4022                 pf->flags |= I40E_FLAG_SRIOV;
4023                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4024                 pf->vf_num = pci_dev->max_vfs;
4025                 PMD_DRV_LOG(DEBUG,
4026                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4027                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4028         } else {
4029                 pf->vf_nb_qps = 0;
4030                 pf->vf_num = 0;
4031         }
4032         qp_count += pf->vf_nb_qps * pf->vf_num;
4033         vsi_count += pf->vf_num;
4034
4035         /* VMDq queue/VSI allocation */
4036         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4037         pf->vmdq_nb_qps = 0;
4038         pf->max_nb_vmdq_vsi = 0;
4039         if (hw->func_caps.vmdq) {
4040                 if (qp_count < hw->func_caps.num_tx_qp &&
4041                         vsi_count < hw->func_caps.num_vsis) {
4042                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4043                                 qp_count) / pf->vmdq_nb_qp_max;
4044
4045                         /* Limit the maximum number of VMDq vsi to the maximum
4046                          * ethdev can support
4047                          */
4048                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4049                                 hw->func_caps.num_vsis - vsi_count);
4050                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4051                                 ETH_64_POOLS);
4052                         if (pf->max_nb_vmdq_vsi) {
4053                                 pf->flags |= I40E_FLAG_VMDQ;
4054                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4055                                 PMD_DRV_LOG(DEBUG,
4056                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4057                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4058                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4059                         } else {
4060                                 PMD_DRV_LOG(INFO,
4061                                         "No enough queues left for VMDq");
4062                         }
4063                 } else {
4064                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4065                 }
4066         }
4067         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4068         vsi_count += pf->max_nb_vmdq_vsi;
4069
4070         if (hw->func_caps.dcb)
4071                 pf->flags |= I40E_FLAG_DCB;
4072
4073         if (qp_count > hw->func_caps.num_tx_qp) {
4074                 PMD_DRV_LOG(ERR,
4075                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4076                         qp_count, hw->func_caps.num_tx_qp);
4077                 return -EINVAL;
4078         }
4079         if (vsi_count > hw->func_caps.num_vsis) {
4080                 PMD_DRV_LOG(ERR,
4081                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4082                         vsi_count, hw->func_caps.num_vsis);
4083                 return -EINVAL;
4084         }
4085
4086         return 0;
4087 }
4088
4089 static int
4090 i40e_pf_get_switch_config(struct i40e_pf *pf)
4091 {
4092         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4093         struct i40e_aqc_get_switch_config_resp *switch_config;
4094         struct i40e_aqc_switch_config_element_resp *element;
4095         uint16_t start_seid = 0, num_reported;
4096         int ret;
4097
4098         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4099                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4100         if (!switch_config) {
4101                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4102                 return -ENOMEM;
4103         }
4104
4105         /* Get the switch configurations */
4106         ret = i40e_aq_get_switch_config(hw, switch_config,
4107                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4108         if (ret != I40E_SUCCESS) {
4109                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4110                 goto fail;
4111         }
4112         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4113         if (num_reported != 1) { /* The number should be 1 */
4114                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4115                 goto fail;
4116         }
4117
4118         /* Parse the switch configuration elements */
4119         element = &(switch_config->element[0]);
4120         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4121                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4122                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4123         } else
4124                 PMD_DRV_LOG(INFO, "Unknown element type");
4125
4126 fail:
4127         rte_free(switch_config);
4128
4129         return ret;
4130 }
4131
4132 static int
4133 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4134                         uint32_t num)
4135 {
4136         struct pool_entry *entry;
4137
4138         if (pool == NULL || num == 0)
4139                 return -EINVAL;
4140
4141         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4142         if (entry == NULL) {
4143                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4144                 return -ENOMEM;
4145         }
4146
4147         /* queue heap initialize */
4148         pool->num_free = num;
4149         pool->num_alloc = 0;
4150         pool->base = base;
4151         LIST_INIT(&pool->alloc_list);
4152         LIST_INIT(&pool->free_list);
4153
4154         /* Initialize element  */
4155         entry->base = 0;
4156         entry->len = num;
4157
4158         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4159         return 0;
4160 }
4161
4162 static void
4163 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4164 {
4165         struct pool_entry *entry, *next_entry;
4166
4167         if (pool == NULL)
4168                 return;
4169
4170         for (entry = LIST_FIRST(&pool->alloc_list);
4171                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4172                         entry = next_entry) {
4173                 LIST_REMOVE(entry, next);
4174                 rte_free(entry);
4175         }
4176
4177         for (entry = LIST_FIRST(&pool->free_list);
4178                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4179                         entry = next_entry) {
4180                 LIST_REMOVE(entry, next);
4181                 rte_free(entry);
4182         }
4183
4184         pool->num_free = 0;
4185         pool->num_alloc = 0;
4186         pool->base = 0;
4187         LIST_INIT(&pool->alloc_list);
4188         LIST_INIT(&pool->free_list);
4189 }
4190
4191 static int
4192 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4193                        uint32_t base)
4194 {
4195         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4196         uint32_t pool_offset;
4197         int insert;
4198
4199         if (pool == NULL) {
4200                 PMD_DRV_LOG(ERR, "Invalid parameter");
4201                 return -EINVAL;
4202         }
4203
4204         pool_offset = base - pool->base;
4205         /* Lookup in alloc list */
4206         LIST_FOREACH(entry, &pool->alloc_list, next) {
4207                 if (entry->base == pool_offset) {
4208                         valid_entry = entry;
4209                         LIST_REMOVE(entry, next);
4210                         break;
4211                 }
4212         }
4213
4214         /* Not find, return */
4215         if (valid_entry == NULL) {
4216                 PMD_DRV_LOG(ERR, "Failed to find entry");
4217                 return -EINVAL;
4218         }
4219
4220         /**
4221          * Found it, move it to free list  and try to merge.
4222          * In order to make merge easier, always sort it by qbase.
4223          * Find adjacent prev and last entries.
4224          */
4225         prev = next = NULL;
4226         LIST_FOREACH(entry, &pool->free_list, next) {
4227                 if (entry->base > valid_entry->base) {
4228                         next = entry;
4229                         break;
4230                 }
4231                 prev = entry;
4232         }
4233
4234         insert = 0;
4235         /* Try to merge with next one*/
4236         if (next != NULL) {
4237                 /* Merge with next one */
4238                 if (valid_entry->base + valid_entry->len == next->base) {
4239                         next->base = valid_entry->base;
4240                         next->len += valid_entry->len;
4241                         rte_free(valid_entry);
4242                         valid_entry = next;
4243                         insert = 1;
4244                 }
4245         }
4246
4247         if (prev != NULL) {
4248                 /* Merge with previous one */
4249                 if (prev->base + prev->len == valid_entry->base) {
4250                         prev->len += valid_entry->len;
4251                         /* If it merge with next one, remove next node */
4252                         if (insert == 1) {
4253                                 LIST_REMOVE(valid_entry, next);
4254                                 rte_free(valid_entry);
4255                         } else {
4256                                 rte_free(valid_entry);
4257                                 insert = 1;
4258                         }
4259                 }
4260         }
4261
4262         /* Not find any entry to merge, insert */
4263         if (insert == 0) {
4264                 if (prev != NULL)
4265                         LIST_INSERT_AFTER(prev, valid_entry, next);
4266                 else if (next != NULL)
4267                         LIST_INSERT_BEFORE(next, valid_entry, next);
4268                 else /* It's empty list, insert to head */
4269                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4270         }
4271
4272         pool->num_free += valid_entry->len;
4273         pool->num_alloc -= valid_entry->len;
4274
4275         return 0;
4276 }
4277
4278 static int
4279 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4280                        uint16_t num)
4281 {
4282         struct pool_entry *entry, *valid_entry;
4283
4284         if (pool == NULL || num == 0) {
4285                 PMD_DRV_LOG(ERR, "Invalid parameter");
4286                 return -EINVAL;
4287         }
4288
4289         if (pool->num_free < num) {
4290                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4291                             num, pool->num_free);
4292                 return -ENOMEM;
4293         }
4294
4295         valid_entry = NULL;
4296         /* Lookup  in free list and find most fit one */
4297         LIST_FOREACH(entry, &pool->free_list, next) {
4298                 if (entry->len >= num) {
4299                         /* Find best one */
4300                         if (entry->len == num) {
4301                                 valid_entry = entry;
4302                                 break;
4303                         }
4304                         if (valid_entry == NULL || valid_entry->len > entry->len)
4305                                 valid_entry = entry;
4306                 }
4307         }
4308
4309         /* Not find one to satisfy the request, return */
4310         if (valid_entry == NULL) {
4311                 PMD_DRV_LOG(ERR, "No valid entry found");
4312                 return -ENOMEM;
4313         }
4314         /**
4315          * The entry have equal queue number as requested,
4316          * remove it from alloc_list.
4317          */
4318         if (valid_entry->len == num) {
4319                 LIST_REMOVE(valid_entry, next);
4320         } else {
4321                 /**
4322                  * The entry have more numbers than requested,
4323                  * create a new entry for alloc_list and minus its
4324                  * queue base and number in free_list.
4325                  */
4326                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4327                 if (entry == NULL) {
4328                         PMD_DRV_LOG(ERR,
4329                                 "Failed to allocate memory for resource pool");
4330                         return -ENOMEM;
4331                 }
4332                 entry->base = valid_entry->base;
4333                 entry->len = num;
4334                 valid_entry->base += num;
4335                 valid_entry->len -= num;
4336                 valid_entry = entry;
4337         }
4338
4339         /* Insert it into alloc list, not sorted */
4340         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4341
4342         pool->num_free -= valid_entry->len;
4343         pool->num_alloc += valid_entry->len;
4344
4345         return valid_entry->base + pool->base;
4346 }
4347
4348 /**
4349  * bitmap_is_subset - Check whether src2 is subset of src1
4350  **/
4351 static inline int
4352 bitmap_is_subset(uint8_t src1, uint8_t src2)
4353 {
4354         return !((src1 ^ src2) & src2);
4355 }
4356
4357 static enum i40e_status_code
4358 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4359 {
4360         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4361
4362         /* If DCB is not supported, only default TC is supported */
4363         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4364                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4365                 return I40E_NOT_SUPPORTED;
4366         }
4367
4368         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4369                 PMD_DRV_LOG(ERR,
4370                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4371                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4372                 return I40E_NOT_SUPPORTED;
4373         }
4374         return I40E_SUCCESS;
4375 }
4376
4377 int
4378 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4379                                 struct i40e_vsi_vlan_pvid_info *info)
4380 {
4381         struct i40e_hw *hw;
4382         struct i40e_vsi_context ctxt;
4383         uint8_t vlan_flags = 0;
4384         int ret;
4385
4386         if (vsi == NULL || info == NULL) {
4387                 PMD_DRV_LOG(ERR, "invalid parameters");
4388                 return I40E_ERR_PARAM;
4389         }
4390
4391         if (info->on) {
4392                 vsi->info.pvid = info->config.pvid;
4393                 /**
4394                  * If insert pvid is enabled, only tagged pkts are
4395                  * allowed to be sent out.
4396                  */
4397                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4398                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4399         } else {
4400                 vsi->info.pvid = 0;
4401                 if (info->config.reject.tagged == 0)
4402                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4403
4404                 if (info->config.reject.untagged == 0)
4405                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4406         }
4407         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4408                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4409         vsi->info.port_vlan_flags |= vlan_flags;
4410         vsi->info.valid_sections =
4411                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4412         memset(&ctxt, 0, sizeof(ctxt));
4413         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4414         ctxt.seid = vsi->seid;
4415
4416         hw = I40E_VSI_TO_HW(vsi);
4417         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4418         if (ret != I40E_SUCCESS)
4419                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4420
4421         return ret;
4422 }
4423
4424 static int
4425 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4426 {
4427         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4428         int i, ret;
4429         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4430
4431         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4432         if (ret != I40E_SUCCESS)
4433                 return ret;
4434
4435         if (!vsi->seid) {
4436                 PMD_DRV_LOG(ERR, "seid not valid");
4437                 return -EINVAL;
4438         }
4439
4440         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4441         tc_bw_data.tc_valid_bits = enabled_tcmap;
4442         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4443                 tc_bw_data.tc_bw_credits[i] =
4444                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4445
4446         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4447         if (ret != I40E_SUCCESS) {
4448                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4449                 return ret;
4450         }
4451
4452         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4453                                         sizeof(vsi->info.qs_handle));
4454         return I40E_SUCCESS;
4455 }
4456
4457 static enum i40e_status_code
4458 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4459                                  struct i40e_aqc_vsi_properties_data *info,
4460                                  uint8_t enabled_tcmap)
4461 {
4462         enum i40e_status_code ret;
4463         int i, total_tc = 0;
4464         uint16_t qpnum_per_tc, bsf, qp_idx;
4465
4466         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4467         if (ret != I40E_SUCCESS)
4468                 return ret;
4469
4470         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4471                 if (enabled_tcmap & (1 << i))
4472                         total_tc++;
4473         if (total_tc == 0)
4474                 total_tc = 1;
4475         vsi->enabled_tc = enabled_tcmap;
4476
4477         /* Number of queues per enabled TC */
4478         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4479         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4480         bsf = rte_bsf32(qpnum_per_tc);
4481
4482         /* Adjust the queue number to actual queues that can be applied */
4483         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4484                 vsi->nb_qps = qpnum_per_tc * total_tc;
4485
4486         /**
4487          * Configure TC and queue mapping parameters, for enabled TC,
4488          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4489          * default queue will serve it.
4490          */
4491         qp_idx = 0;
4492         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4493                 if (vsi->enabled_tc & (1 << i)) {
4494                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4495                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4496                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4497                         qp_idx += qpnum_per_tc;
4498                 } else
4499                         info->tc_mapping[i] = 0;
4500         }
4501
4502         /* Associate queue number with VSI */
4503         if (vsi->type == I40E_VSI_SRIOV) {
4504                 info->mapping_flags |=
4505                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4506                 for (i = 0; i < vsi->nb_qps; i++)
4507                         info->queue_mapping[i] =
4508                                 rte_cpu_to_le_16(vsi->base_queue + i);
4509         } else {
4510                 info->mapping_flags |=
4511                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4512                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4513         }
4514         info->valid_sections |=
4515                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4516
4517         return I40E_SUCCESS;
4518 }
4519
4520 static int
4521 i40e_veb_release(struct i40e_veb *veb)
4522 {
4523         struct i40e_vsi *vsi;
4524         struct i40e_hw *hw;
4525
4526         if (veb == NULL)
4527                 return -EINVAL;
4528
4529         if (!TAILQ_EMPTY(&veb->head)) {
4530                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4531                 return -EACCES;
4532         }
4533         /* associate_vsi field is NULL for floating VEB */
4534         if (veb->associate_vsi != NULL) {
4535                 vsi = veb->associate_vsi;
4536                 hw = I40E_VSI_TO_HW(vsi);
4537
4538                 vsi->uplink_seid = veb->uplink_seid;
4539                 vsi->veb = NULL;
4540         } else {
4541                 veb->associate_pf->main_vsi->floating_veb = NULL;
4542                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4543         }
4544
4545         i40e_aq_delete_element(hw, veb->seid, NULL);
4546         rte_free(veb);
4547         return I40E_SUCCESS;
4548 }
4549
4550 /* Setup a veb */
4551 static struct i40e_veb *
4552 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4553 {
4554         struct i40e_veb *veb;
4555         int ret;
4556         struct i40e_hw *hw;
4557
4558         if (pf == NULL) {
4559                 PMD_DRV_LOG(ERR,
4560                             "veb setup failed, associated PF shouldn't null");
4561                 return NULL;
4562         }
4563         hw = I40E_PF_TO_HW(pf);
4564
4565         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4566         if (!veb) {
4567                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4568                 goto fail;
4569         }
4570
4571         veb->associate_vsi = vsi;
4572         veb->associate_pf = pf;
4573         TAILQ_INIT(&veb->head);
4574         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4575
4576         /* create floating veb if vsi is NULL */
4577         if (vsi != NULL) {
4578                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4579                                       I40E_DEFAULT_TCMAP, false,
4580                                       &veb->seid, false, NULL);
4581         } else {
4582                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4583                                       true, &veb->seid, false, NULL);
4584         }
4585
4586         if (ret != I40E_SUCCESS) {
4587                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4588                             hw->aq.asq_last_status);
4589                 goto fail;
4590         }
4591         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4592
4593         /* get statistics index */
4594         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4595                                 &veb->stats_idx, NULL, NULL, NULL);
4596         if (ret != I40E_SUCCESS) {
4597                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4598                             hw->aq.asq_last_status);
4599                 goto fail;
4600         }
4601         /* Get VEB bandwidth, to be implemented */
4602         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4603         if (vsi)
4604                 vsi->uplink_seid = veb->seid;
4605
4606         return veb;
4607 fail:
4608         rte_free(veb);
4609         return NULL;
4610 }
4611
4612 int
4613 i40e_vsi_release(struct i40e_vsi *vsi)
4614 {
4615         struct i40e_pf *pf;
4616         struct i40e_hw *hw;
4617         struct i40e_vsi_list *vsi_list;
4618         void *temp;
4619         int ret;
4620         struct i40e_mac_filter *f;
4621         uint16_t user_param;
4622
4623         if (!vsi)
4624                 return I40E_SUCCESS;
4625
4626         if (!vsi->adapter)
4627                 return -EFAULT;
4628
4629         user_param = vsi->user_param;
4630
4631         pf = I40E_VSI_TO_PF(vsi);
4632         hw = I40E_VSI_TO_HW(vsi);
4633
4634         /* VSI has child to attach, release child first */
4635         if (vsi->veb) {
4636                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4637                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4638                                 return -1;
4639                 }
4640                 i40e_veb_release(vsi->veb);
4641         }
4642
4643         if (vsi->floating_veb) {
4644                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4645                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4646                                 return -1;
4647                 }
4648         }
4649
4650         /* Remove all macvlan filters of the VSI */
4651         i40e_vsi_remove_all_macvlan_filter(vsi);
4652         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4653                 rte_free(f);
4654
4655         if (vsi->type != I40E_VSI_MAIN &&
4656             ((vsi->type != I40E_VSI_SRIOV) ||
4657             !pf->floating_veb_list[user_param])) {
4658                 /* Remove vsi from parent's sibling list */
4659                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4660                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4661                         return I40E_ERR_PARAM;
4662                 }
4663                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4664                                 &vsi->sib_vsi_list, list);
4665
4666                 /* Remove all switch element of the VSI */
4667                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4668                 if (ret != I40E_SUCCESS)
4669                         PMD_DRV_LOG(ERR, "Failed to delete element");
4670         }
4671
4672         if ((vsi->type == I40E_VSI_SRIOV) &&
4673             pf->floating_veb_list[user_param]) {
4674                 /* Remove vsi from parent's sibling list */
4675                 if (vsi->parent_vsi == NULL ||
4676                     vsi->parent_vsi->floating_veb == NULL) {
4677                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4678                         return I40E_ERR_PARAM;
4679                 }
4680                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4681                              &vsi->sib_vsi_list, list);
4682
4683                 /* Remove all switch element of the VSI */
4684                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4685                 if (ret != I40E_SUCCESS)
4686                         PMD_DRV_LOG(ERR, "Failed to delete element");
4687         }
4688
4689         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4690
4691         if (vsi->type != I40E_VSI_SRIOV)
4692                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4693         rte_free(vsi);
4694
4695         return I40E_SUCCESS;
4696 }
4697
4698 static int
4699 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4700 {
4701         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4702         struct i40e_aqc_remove_macvlan_element_data def_filter;
4703         struct i40e_mac_filter_info filter;
4704         int ret;
4705
4706         if (vsi->type != I40E_VSI_MAIN)
4707                 return I40E_ERR_CONFIG;
4708         memset(&def_filter, 0, sizeof(def_filter));
4709         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4710                                         ETH_ADDR_LEN);
4711         def_filter.vlan_tag = 0;
4712         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4713                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4714         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4715         if (ret != I40E_SUCCESS) {
4716                 struct i40e_mac_filter *f;
4717                 struct ether_addr *mac;
4718
4719                 PMD_DRV_LOG(DEBUG,
4720                             "Cannot remove the default macvlan filter");
4721                 /* It needs to add the permanent mac into mac list */
4722                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4723                 if (f == NULL) {
4724                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4725                         return I40E_ERR_NO_MEMORY;
4726                 }
4727                 mac = &f->mac_info.mac_addr;
4728                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4729                                 ETH_ADDR_LEN);
4730                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4731                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4732                 vsi->mac_num++;
4733
4734                 return ret;
4735         }
4736         rte_memcpy(&filter.mac_addr,
4737                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4738         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4739         return i40e_vsi_add_mac(vsi, &filter);
4740 }
4741
4742 /*
4743  * i40e_vsi_get_bw_config - Query VSI BW Information
4744  * @vsi: the VSI to be queried
4745  *
4746  * Returns 0 on success, negative value on failure
4747  */
4748 static enum i40e_status_code
4749 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4750 {
4751         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4752         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4753         struct i40e_hw *hw = &vsi->adapter->hw;
4754         i40e_status ret;
4755         int i;
4756         uint32_t bw_max;
4757
4758         memset(&bw_config, 0, sizeof(bw_config));
4759         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4760         if (ret != I40E_SUCCESS) {
4761                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4762                             hw->aq.asq_last_status);
4763                 return ret;
4764         }
4765
4766         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4767         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4768                                         &ets_sla_config, NULL);
4769         if (ret != I40E_SUCCESS) {
4770                 PMD_DRV_LOG(ERR,
4771                         "VSI failed to get TC bandwdith configuration %u",
4772                         hw->aq.asq_last_status);
4773                 return ret;
4774         }
4775
4776         /* store and print out BW info */
4777         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4778         vsi->bw_info.bw_max = bw_config.max_bw;
4779         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4780         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4781         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4782                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4783                      I40E_16_BIT_WIDTH);
4784         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4785                 vsi->bw_info.bw_ets_share_credits[i] =
4786                                 ets_sla_config.share_credits[i];
4787                 vsi->bw_info.bw_ets_credits[i] =
4788                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4789                 /* 4 bits per TC, 4th bit is reserved */
4790                 vsi->bw_info.bw_ets_max[i] =
4791                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4792                                   RTE_LEN2MASK(3, uint8_t));
4793                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4794                             vsi->bw_info.bw_ets_share_credits[i]);
4795                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4796                             vsi->bw_info.bw_ets_credits[i]);
4797                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4798                             vsi->bw_info.bw_ets_max[i]);
4799         }
4800
4801         return I40E_SUCCESS;
4802 }
4803
4804 /* i40e_enable_pf_lb
4805  * @pf: pointer to the pf structure
4806  *
4807  * allow loopback on pf
4808  */
4809 static inline void
4810 i40e_enable_pf_lb(struct i40e_pf *pf)
4811 {
4812         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4813         struct i40e_vsi_context ctxt;
4814         int ret;
4815
4816         /* Use the FW API if FW >= v5.0 */
4817         if (hw->aq.fw_maj_ver < 5) {
4818                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4819                 return;
4820         }
4821
4822         memset(&ctxt, 0, sizeof(ctxt));
4823         ctxt.seid = pf->main_vsi_seid;
4824         ctxt.pf_num = hw->pf_id;
4825         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4826         if (ret) {
4827                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4828                             ret, hw->aq.asq_last_status);
4829                 return;
4830         }
4831         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4832         ctxt.info.valid_sections =
4833                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4834         ctxt.info.switch_id |=
4835                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4836
4837         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4838         if (ret)
4839                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4840                             hw->aq.asq_last_status);
4841 }
4842
4843 /* Setup a VSI */
4844 struct i40e_vsi *
4845 i40e_vsi_setup(struct i40e_pf *pf,
4846                enum i40e_vsi_type type,
4847                struct i40e_vsi *uplink_vsi,
4848                uint16_t user_param)
4849 {
4850         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4851         struct i40e_vsi *vsi;
4852         struct i40e_mac_filter_info filter;
4853         int ret;
4854         struct i40e_vsi_context ctxt;
4855         struct ether_addr broadcast =
4856                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4857
4858         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4859             uplink_vsi == NULL) {
4860                 PMD_DRV_LOG(ERR,
4861                         "VSI setup failed, VSI link shouldn't be NULL");
4862                 return NULL;
4863         }
4864
4865         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4866                 PMD_DRV_LOG(ERR,
4867                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4868                 return NULL;
4869         }
4870
4871         /* two situations
4872          * 1.type is not MAIN and uplink vsi is not NULL
4873          * If uplink vsi didn't setup VEB, create one first under veb field
4874          * 2.type is SRIOV and the uplink is NULL
4875          * If floating VEB is NULL, create one veb under floating veb field
4876          */
4877
4878         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4879             uplink_vsi->veb == NULL) {
4880                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4881
4882                 if (uplink_vsi->veb == NULL) {
4883                         PMD_DRV_LOG(ERR, "VEB setup failed");
4884                         return NULL;
4885                 }
4886                 /* set ALLOWLOOPBACk on pf, when veb is created */
4887                 i40e_enable_pf_lb(pf);
4888         }
4889
4890         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4891             pf->main_vsi->floating_veb == NULL) {
4892                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4893
4894                 if (pf->main_vsi->floating_veb == NULL) {
4895                         PMD_DRV_LOG(ERR, "VEB setup failed");
4896                         return NULL;
4897                 }
4898         }
4899
4900         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4901         if (!vsi) {
4902                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4903                 return NULL;
4904         }
4905         TAILQ_INIT(&vsi->mac_list);
4906         vsi->type = type;
4907         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4908         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4909         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4910         vsi->user_param = user_param;
4911         vsi->vlan_anti_spoof_on = 0;
4912         vsi->vlan_filter_on = 0;
4913         /* Allocate queues */
4914         switch (vsi->type) {
4915         case I40E_VSI_MAIN  :
4916                 vsi->nb_qps = pf->lan_nb_qps;
4917                 break;
4918         case I40E_VSI_SRIOV :
4919                 vsi->nb_qps = pf->vf_nb_qps;
4920                 break;
4921         case I40E_VSI_VMDQ2:
4922                 vsi->nb_qps = pf->vmdq_nb_qps;
4923                 break;
4924         case I40E_VSI_FDIR:
4925                 vsi->nb_qps = pf->fdir_nb_qps;
4926                 break;
4927         default:
4928                 goto fail_mem;
4929         }
4930         /*
4931          * The filter status descriptor is reported in rx queue 0,
4932          * while the tx queue for fdir filter programming has no
4933          * such constraints, can be non-zero queues.
4934          * To simplify it, choose FDIR vsi use queue 0 pair.
4935          * To make sure it will use queue 0 pair, queue allocation
4936          * need be done before this function is called
4937          */
4938         if (type != I40E_VSI_FDIR) {
4939                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4940                         if (ret < 0) {
4941                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4942                                                 vsi->seid, ret);
4943                                 goto fail_mem;
4944                         }
4945                         vsi->base_queue = ret;
4946         } else
4947                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4948
4949         /* VF has MSIX interrupt in VF range, don't allocate here */
4950         if (type == I40E_VSI_MAIN) {
4951                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4952                                           RTE_MIN(vsi->nb_qps,
4953                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4954                 if (ret < 0) {
4955                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4956                                     vsi->seid, ret);
4957                         goto fail_queue_alloc;
4958                 }
4959                 vsi->msix_intr = ret;
4960                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4961         } else if (type != I40E_VSI_SRIOV) {
4962                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4963                 if (ret < 0) {
4964                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4965                         goto fail_queue_alloc;
4966                 }
4967                 vsi->msix_intr = ret;
4968                 vsi->nb_msix = 1;
4969         } else {
4970                 vsi->msix_intr = 0;
4971                 vsi->nb_msix = 0;
4972         }
4973
4974         /* Add VSI */
4975         if (type == I40E_VSI_MAIN) {
4976                 /* For main VSI, no need to add since it's default one */
4977                 vsi->uplink_seid = pf->mac_seid;
4978                 vsi->seid = pf->main_vsi_seid;
4979                 /* Bind queues with specific MSIX interrupt */
4980                 /**
4981                  * Needs 2 interrupt at least, one for misc cause which will
4982                  * enabled from OS side, Another for queues binding the
4983                  * interrupt from device side only.
4984                  */
4985
4986                 /* Get default VSI parameters from hardware */
4987                 memset(&ctxt, 0, sizeof(ctxt));
4988                 ctxt.seid = vsi->seid;
4989                 ctxt.pf_num = hw->pf_id;
4990                 ctxt.uplink_seid = vsi->uplink_seid;
4991                 ctxt.vf_num = 0;
4992                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4993                 if (ret != I40E_SUCCESS) {
4994                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4995                         goto fail_msix_alloc;
4996                 }
4997                 rte_memcpy(&vsi->info, &ctxt.info,
4998                         sizeof(struct i40e_aqc_vsi_properties_data));
4999                 vsi->vsi_id = ctxt.vsi_number;
5000                 vsi->info.valid_sections = 0;
5001
5002                 /* Configure tc, enabled TC0 only */
5003                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5004                         I40E_SUCCESS) {
5005                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5006                         goto fail_msix_alloc;
5007                 }
5008
5009                 /* TC, queue mapping */
5010                 memset(&ctxt, 0, sizeof(ctxt));
5011                 vsi->info.valid_sections |=
5012                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5013                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5014                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5015                 rte_memcpy(&ctxt.info, &vsi->info,
5016                         sizeof(struct i40e_aqc_vsi_properties_data));
5017                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5018                                                 I40E_DEFAULT_TCMAP);
5019                 if (ret != I40E_SUCCESS) {
5020                         PMD_DRV_LOG(ERR,
5021                                 "Failed to configure TC queue mapping");
5022                         goto fail_msix_alloc;
5023                 }
5024                 ctxt.seid = vsi->seid;
5025                 ctxt.pf_num = hw->pf_id;
5026                 ctxt.uplink_seid = vsi->uplink_seid;
5027                 ctxt.vf_num = 0;
5028
5029                 /* Update VSI parameters */
5030                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5031                 if (ret != I40E_SUCCESS) {
5032                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5033                         goto fail_msix_alloc;
5034                 }
5035
5036                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5037                                                 sizeof(vsi->info.tc_mapping));
5038                 rte_memcpy(&vsi->info.queue_mapping,
5039                                 &ctxt.info.queue_mapping,
5040                         sizeof(vsi->info.queue_mapping));
5041                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5042                 vsi->info.valid_sections = 0;
5043
5044                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5045                                 ETH_ADDR_LEN);
5046
5047                 /**
5048                  * Updating default filter settings are necessary to prevent
5049                  * reception of tagged packets.
5050                  * Some old firmware configurations load a default macvlan
5051                  * filter which accepts both tagged and untagged packets.
5052                  * The updating is to use a normal filter instead if needed.
5053                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5054                  * The firmware with correct configurations load the default
5055                  * macvlan filter which is expected and cannot be removed.
5056                  */
5057                 i40e_update_default_filter_setting(vsi);
5058                 i40e_config_qinq(hw, vsi);
5059         } else if (type == I40E_VSI_SRIOV) {
5060                 memset(&ctxt, 0, sizeof(ctxt));
5061                 /**
5062                  * For other VSI, the uplink_seid equals to uplink VSI's
5063                  * uplink_seid since they share same VEB
5064                  */
5065                 if (uplink_vsi == NULL)
5066                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5067                 else
5068                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5069                 ctxt.pf_num = hw->pf_id;
5070                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5071                 ctxt.uplink_seid = vsi->uplink_seid;
5072                 ctxt.connection_type = 0x1;
5073                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5074
5075                 /* Use the VEB configuration if FW >= v5.0 */
5076                 if (hw->aq.fw_maj_ver >= 5) {
5077                         /* Configure switch ID */
5078                         ctxt.info.valid_sections |=
5079                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5080                         ctxt.info.switch_id =
5081                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5082                 }
5083
5084                 /* Configure port/vlan */
5085                 ctxt.info.valid_sections |=
5086                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5087                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5088                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5089                                                 hw->func_caps.enabled_tcmap);
5090                 if (ret != I40E_SUCCESS) {
5091                         PMD_DRV_LOG(ERR,
5092                                 "Failed to configure TC queue mapping");
5093                         goto fail_msix_alloc;
5094                 }
5095
5096                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5097                 ctxt.info.valid_sections |=
5098                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5099                 /**
5100                  * Since VSI is not created yet, only configure parameter,
5101                  * will add vsi below.
5102                  */
5103
5104                 i40e_config_qinq(hw, vsi);
5105         } else if (type == I40E_VSI_VMDQ2) {
5106                 memset(&ctxt, 0, sizeof(ctxt));
5107                 /*
5108                  * For other VSI, the uplink_seid equals to uplink VSI's
5109                  * uplink_seid since they share same VEB
5110                  */
5111                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5112                 ctxt.pf_num = hw->pf_id;
5113                 ctxt.vf_num = 0;
5114                 ctxt.uplink_seid = vsi->uplink_seid;
5115                 ctxt.connection_type = 0x1;
5116                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5117
5118                 ctxt.info.valid_sections |=
5119                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5120                 /* user_param carries flag to enable loop back */
5121                 if (user_param) {
5122                         ctxt.info.switch_id =
5123                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5124                         ctxt.info.switch_id |=
5125                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5126                 }
5127
5128                 /* Configure port/vlan */
5129                 ctxt.info.valid_sections |=
5130                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5131                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5132                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5133                                                 I40E_DEFAULT_TCMAP);
5134                 if (ret != I40E_SUCCESS) {
5135                         PMD_DRV_LOG(ERR,
5136                                 "Failed to configure TC queue mapping");
5137                         goto fail_msix_alloc;
5138                 }
5139                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5140                 ctxt.info.valid_sections |=
5141                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5142         } else if (type == I40E_VSI_FDIR) {
5143                 memset(&ctxt, 0, sizeof(ctxt));
5144                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5145                 ctxt.pf_num = hw->pf_id;
5146                 ctxt.vf_num = 0;
5147                 ctxt.uplink_seid = vsi->uplink_seid;
5148                 ctxt.connection_type = 0x1;     /* regular data port */
5149                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5150                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5151                                                 I40E_DEFAULT_TCMAP);
5152                 if (ret != I40E_SUCCESS) {
5153                         PMD_DRV_LOG(ERR,
5154                                 "Failed to configure TC queue mapping.");
5155                         goto fail_msix_alloc;
5156                 }
5157                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5158                 ctxt.info.valid_sections |=
5159                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5160         } else {
5161                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5162                 goto fail_msix_alloc;
5163         }
5164
5165         if (vsi->type != I40E_VSI_MAIN) {
5166                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5167                 if (ret != I40E_SUCCESS) {
5168                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5169                                     hw->aq.asq_last_status);
5170                         goto fail_msix_alloc;
5171                 }
5172                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5173                 vsi->info.valid_sections = 0;
5174                 vsi->seid = ctxt.seid;
5175                 vsi->vsi_id = ctxt.vsi_number;
5176                 vsi->sib_vsi_list.vsi = vsi;
5177                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5178                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5179                                           &vsi->sib_vsi_list, list);
5180                 } else {
5181                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5182                                           &vsi->sib_vsi_list, list);
5183                 }
5184         }
5185
5186         /* MAC/VLAN configuration */
5187         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5188         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5189
5190         ret = i40e_vsi_add_mac(vsi, &filter);
5191         if (ret != I40E_SUCCESS) {
5192                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5193                 goto fail_msix_alloc;
5194         }
5195
5196         /* Get VSI BW information */
5197         i40e_vsi_get_bw_config(vsi);
5198         return vsi;
5199 fail_msix_alloc:
5200         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5201 fail_queue_alloc:
5202         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5203 fail_mem:
5204         rte_free(vsi);
5205         return NULL;
5206 }
5207
5208 /* Configure vlan filter on or off */
5209 int
5210 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5211 {
5212         int i, num;
5213         struct i40e_mac_filter *f;
5214         void *temp;
5215         struct i40e_mac_filter_info *mac_filter;
5216         enum rte_mac_filter_type desired_filter;
5217         int ret = I40E_SUCCESS;
5218
5219         if (on) {
5220                 /* Filter to match MAC and VLAN */
5221                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5222         } else {
5223                 /* Filter to match only MAC */
5224                 desired_filter = RTE_MAC_PERFECT_MATCH;
5225         }
5226
5227         num = vsi->mac_num;
5228
5229         mac_filter = rte_zmalloc("mac_filter_info_data",
5230                                  num * sizeof(*mac_filter), 0);
5231         if (mac_filter == NULL) {
5232                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5233                 return I40E_ERR_NO_MEMORY;
5234         }
5235
5236         i = 0;
5237
5238         /* Remove all existing mac */
5239         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5240                 mac_filter[i] = f->mac_info;
5241                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5242                 if (ret) {
5243                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5244                                     on ? "enable" : "disable");
5245                         goto DONE;
5246                 }
5247                 i++;
5248         }
5249
5250         /* Override with new filter */
5251         for (i = 0; i < num; i++) {
5252                 mac_filter[i].filter_type = desired_filter;
5253                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5254                 if (ret) {
5255                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5256                                     on ? "enable" : "disable");
5257                         goto DONE;
5258                 }
5259         }
5260
5261 DONE:
5262         rte_free(mac_filter);
5263         return ret;
5264 }
5265
5266 /* Configure vlan stripping on or off */
5267 int
5268 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5269 {
5270         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5271         struct i40e_vsi_context ctxt;
5272         uint8_t vlan_flags;
5273         int ret = I40E_SUCCESS;
5274
5275         /* Check if it has been already on or off */
5276         if (vsi->info.valid_sections &
5277                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5278                 if (on) {
5279                         if ((vsi->info.port_vlan_flags &
5280                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5281                                 return 0; /* already on */
5282                 } else {
5283                         if ((vsi->info.port_vlan_flags &
5284                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5285                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5286                                 return 0; /* already off */
5287                 }
5288         }
5289
5290         if (on)
5291                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5292         else
5293                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5294         vsi->info.valid_sections =
5295                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5296         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5297         vsi->info.port_vlan_flags |= vlan_flags;
5298         ctxt.seid = vsi->seid;
5299         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5300         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5301         if (ret)
5302                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5303                             on ? "enable" : "disable");
5304
5305         return ret;
5306 }
5307
5308 static int
5309 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5310 {
5311         struct rte_eth_dev_data *data = dev->data;
5312         int ret;
5313         int mask = 0;
5314
5315         /* Apply vlan offload setting */
5316         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5317         i40e_vlan_offload_set(dev, mask);
5318
5319         /* Apply double-vlan setting, not implemented yet */
5320
5321         /* Apply pvid setting */
5322         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5323                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5324         if (ret)
5325                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5326
5327         return ret;
5328 }
5329
5330 static int
5331 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5332 {
5333         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5334
5335         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5336 }
5337
5338 static int
5339 i40e_update_flow_control(struct i40e_hw *hw)
5340 {
5341 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5342         struct i40e_link_status link_status;
5343         uint32_t rxfc = 0, txfc = 0, reg;
5344         uint8_t an_info;
5345         int ret;
5346
5347         memset(&link_status, 0, sizeof(link_status));
5348         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5349         if (ret != I40E_SUCCESS) {
5350                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5351                 goto write_reg; /* Disable flow control */
5352         }
5353
5354         an_info = hw->phy.link_info.an_info;
5355         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5356                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5357                 ret = I40E_ERR_NOT_READY;
5358                 goto write_reg; /* Disable flow control */
5359         }
5360         /**
5361          * If link auto negotiation is enabled, flow control needs to
5362          * be configured according to it
5363          */
5364         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5365         case I40E_LINK_PAUSE_RXTX:
5366                 rxfc = 1;
5367                 txfc = 1;
5368                 hw->fc.current_mode = I40E_FC_FULL;
5369                 break;
5370         case I40E_AQ_LINK_PAUSE_RX:
5371                 rxfc = 1;
5372                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5373                 break;
5374         case I40E_AQ_LINK_PAUSE_TX:
5375                 txfc = 1;
5376                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5377                 break;
5378         default:
5379                 hw->fc.current_mode = I40E_FC_NONE;
5380                 break;
5381         }
5382
5383 write_reg:
5384         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5385                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5386         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5387         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5388         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5389         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5390
5391         return ret;
5392 }
5393
5394 /* PF setup */
5395 static int
5396 i40e_pf_setup(struct i40e_pf *pf)
5397 {
5398         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5399         struct i40e_filter_control_settings settings;
5400         struct i40e_vsi *vsi;
5401         int ret;
5402
5403         /* Clear all stats counters */
5404         pf->offset_loaded = FALSE;
5405         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5406         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5407         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5408         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5409
5410         ret = i40e_pf_get_switch_config(pf);
5411         if (ret != I40E_SUCCESS) {
5412                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5413                 return ret;
5414         }
5415         if (pf->flags & I40E_FLAG_FDIR) {
5416                 /* make queue allocated first, let FDIR use queue pair 0*/
5417                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5418                 if (ret != I40E_FDIR_QUEUE_ID) {
5419                         PMD_DRV_LOG(ERR,
5420                                 "queue allocation fails for FDIR: ret =%d",
5421                                 ret);
5422                         pf->flags &= ~I40E_FLAG_FDIR;
5423                 }
5424         }
5425         /*  main VSI setup */
5426         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5427         if (!vsi) {
5428                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5429                 return I40E_ERR_NOT_READY;
5430         }
5431         pf->main_vsi = vsi;
5432
5433         /* Configure filter control */
5434         memset(&settings, 0, sizeof(settings));
5435         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5436                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5437         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5438                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5439         else {
5440                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5441                         hw->func_caps.rss_table_size);
5442                 return I40E_ERR_PARAM;
5443         }
5444         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5445                 hw->func_caps.rss_table_size);
5446         pf->hash_lut_size = hw->func_caps.rss_table_size;
5447
5448         /* Enable ethtype and macvlan filters */
5449         settings.enable_ethtype = TRUE;
5450         settings.enable_macvlan = TRUE;
5451         ret = i40e_set_filter_control(hw, &settings);
5452         if (ret)
5453                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5454                                                                 ret);
5455
5456         /* Update flow control according to the auto negotiation */
5457         i40e_update_flow_control(hw);
5458
5459         return I40E_SUCCESS;
5460 }
5461
5462 int
5463 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5464 {
5465         uint32_t reg;
5466         uint16_t j;
5467
5468         /**
5469          * Set or clear TX Queue Disable flags,
5470          * which is required by hardware.
5471          */
5472         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5473         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5474
5475         /* Wait until the request is finished */
5476         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5477                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5478                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5479                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5480                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5481                                                         & 0x1))) {
5482                         break;
5483                 }
5484         }
5485         if (on) {
5486                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5487                         return I40E_SUCCESS; /* already on, skip next steps */
5488
5489                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5490                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5491         } else {
5492                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5493                         return I40E_SUCCESS; /* already off, skip next steps */
5494                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5495         }
5496         /* Write the register */
5497         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5498         /* Check the result */
5499         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5500                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5501                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5502                 if (on) {
5503                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5504                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5505                                 break;
5506                 } else {
5507                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5508                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5509                                 break;
5510                 }
5511         }
5512         /* Check if it is timeout */
5513         if (j >= I40E_CHK_Q_ENA_COUNT) {
5514                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5515                             (on ? "enable" : "disable"), q_idx);
5516                 return I40E_ERR_TIMEOUT;
5517         }
5518
5519         return I40E_SUCCESS;
5520 }
5521
5522 /* Swith on or off the tx queues */
5523 static int
5524 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5525 {
5526         struct rte_eth_dev_data *dev_data = pf->dev_data;
5527         struct i40e_tx_queue *txq;
5528         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5529         uint16_t i;
5530         int ret;
5531
5532         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5533                 txq = dev_data->tx_queues[i];
5534                 /* Don't operate the queue if not configured or
5535                  * if starting only per queue */
5536                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5537                         continue;
5538                 if (on)
5539                         ret = i40e_dev_tx_queue_start(dev, i);
5540                 else
5541                         ret = i40e_dev_tx_queue_stop(dev, i);
5542                 if ( ret != I40E_SUCCESS)
5543                         return ret;
5544         }
5545
5546         return I40E_SUCCESS;
5547 }
5548
5549 int
5550 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5551 {
5552         uint32_t reg;
5553         uint16_t j;
5554
5555         /* Wait until the request is finished */
5556         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5557                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5558                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5559                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5560                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5561                         break;
5562         }
5563
5564         if (on) {
5565                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5566                         return I40E_SUCCESS; /* Already on, skip next steps */
5567                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5568         } else {
5569                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5570                         return I40E_SUCCESS; /* Already off, skip next steps */
5571                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5572         }
5573
5574         /* Write the register */
5575         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5576         /* Check the result */
5577         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5578                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5579                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5580                 if (on) {
5581                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5582                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5583                                 break;
5584                 } else {
5585                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5586                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5587                                 break;
5588                 }
5589         }
5590
5591         /* Check if it is timeout */
5592         if (j >= I40E_CHK_Q_ENA_COUNT) {
5593                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5594                             (on ? "enable" : "disable"), q_idx);
5595                 return I40E_ERR_TIMEOUT;
5596         }
5597
5598         return I40E_SUCCESS;
5599 }
5600 /* Switch on or off the rx queues */
5601 static int
5602 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5603 {
5604         struct rte_eth_dev_data *dev_data = pf->dev_data;
5605         struct i40e_rx_queue *rxq;
5606         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5607         uint16_t i;
5608         int ret;
5609
5610         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5611                 rxq = dev_data->rx_queues[i];
5612                 /* Don't operate the queue if not configured or
5613                  * if starting only per queue */
5614                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5615                         continue;
5616                 if (on)
5617                         ret = i40e_dev_rx_queue_start(dev, i);
5618                 else
5619                         ret = i40e_dev_rx_queue_stop(dev, i);
5620                 if (ret != I40E_SUCCESS)
5621                         return ret;
5622         }
5623
5624         return I40E_SUCCESS;
5625 }
5626
5627 /* Switch on or off all the rx/tx queues */
5628 int
5629 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5630 {
5631         int ret;
5632
5633         if (on) {
5634                 /* enable rx queues before enabling tx queues */
5635                 ret = i40e_dev_switch_rx_queues(pf, on);
5636                 if (ret) {
5637                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5638                         return ret;
5639                 }
5640                 ret = i40e_dev_switch_tx_queues(pf, on);
5641         } else {
5642                 /* Stop tx queues before stopping rx queues */
5643                 ret = i40e_dev_switch_tx_queues(pf, on);
5644                 if (ret) {
5645                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5646                         return ret;
5647                 }
5648                 ret = i40e_dev_switch_rx_queues(pf, on);
5649         }
5650
5651         return ret;
5652 }
5653
5654 /* Initialize VSI for TX */
5655 static int
5656 i40e_dev_tx_init(struct i40e_pf *pf)
5657 {
5658         struct rte_eth_dev_data *data = pf->dev_data;
5659         uint16_t i;
5660         uint32_t ret = I40E_SUCCESS;
5661         struct i40e_tx_queue *txq;
5662
5663         for (i = 0; i < data->nb_tx_queues; i++) {
5664                 txq = data->tx_queues[i];
5665                 if (!txq || !txq->q_set)
5666                         continue;
5667                 ret = i40e_tx_queue_init(txq);
5668                 if (ret != I40E_SUCCESS)
5669                         break;
5670         }
5671         if (ret == I40E_SUCCESS)
5672                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5673                                      ->eth_dev);
5674
5675         return ret;
5676 }
5677
5678 /* Initialize VSI for RX */
5679 static int
5680 i40e_dev_rx_init(struct i40e_pf *pf)
5681 {
5682         struct rte_eth_dev_data *data = pf->dev_data;
5683         int ret = I40E_SUCCESS;
5684         uint16_t i;
5685         struct i40e_rx_queue *rxq;
5686
5687         i40e_pf_config_mq_rx(pf);
5688         for (i = 0; i < data->nb_rx_queues; i++) {
5689                 rxq = data->rx_queues[i];
5690                 if (!rxq || !rxq->q_set)
5691                         continue;
5692
5693                 ret = i40e_rx_queue_init(rxq);
5694                 if (ret != I40E_SUCCESS) {
5695                         PMD_DRV_LOG(ERR,
5696                                 "Failed to do RX queue initialization");
5697                         break;
5698                 }
5699         }
5700         if (ret == I40E_SUCCESS)
5701                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5702                                      ->eth_dev);
5703
5704         return ret;
5705 }
5706
5707 static int
5708 i40e_dev_rxtx_init(struct i40e_pf *pf)
5709 {
5710         int err;
5711
5712         err = i40e_dev_tx_init(pf);
5713         if (err) {
5714                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5715                 return err;
5716         }
5717         err = i40e_dev_rx_init(pf);
5718         if (err) {
5719                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5720                 return err;
5721         }
5722
5723         return err;
5724 }
5725
5726 static int
5727 i40e_vmdq_setup(struct rte_eth_dev *dev)
5728 {
5729         struct rte_eth_conf *conf = &dev->data->dev_conf;
5730         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5731         int i, err, conf_vsis, j, loop;
5732         struct i40e_vsi *vsi;
5733         struct i40e_vmdq_info *vmdq_info;
5734         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5735         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5736
5737         /*
5738          * Disable interrupt to avoid message from VF. Furthermore, it will
5739          * avoid race condition in VSI creation/destroy.
5740          */
5741         i40e_pf_disable_irq0(hw);
5742
5743         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5744                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5745                 return -ENOTSUP;
5746         }
5747
5748         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5749         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5750                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5751                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5752                         pf->max_nb_vmdq_vsi);
5753                 return -ENOTSUP;
5754         }
5755
5756         if (pf->vmdq != NULL) {
5757                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5758                 return 0;
5759         }
5760
5761         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5762                                 sizeof(*vmdq_info) * conf_vsis, 0);
5763
5764         if (pf->vmdq == NULL) {
5765                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5766                 return -ENOMEM;
5767         }
5768
5769         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5770
5771         /* Create VMDQ VSI */
5772         for (i = 0; i < conf_vsis; i++) {
5773                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5774                                 vmdq_conf->enable_loop_back);
5775                 if (vsi == NULL) {
5776                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5777                         err = -1;
5778                         goto err_vsi_setup;
5779                 }
5780                 vmdq_info = &pf->vmdq[i];
5781                 vmdq_info->pf = pf;
5782                 vmdq_info->vsi = vsi;
5783         }
5784         pf->nb_cfg_vmdq_vsi = conf_vsis;
5785
5786         /* Configure Vlan */
5787         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5788         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5789                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5790                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5791                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5792                                         vmdq_conf->pool_map[i].vlan_id, j);
5793
5794                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5795                                                 vmdq_conf->pool_map[i].vlan_id);
5796                                 if (err) {
5797                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5798                                         err = -1;
5799                                         goto err_vsi_setup;
5800                                 }
5801                         }
5802                 }
5803         }
5804
5805         i40e_pf_enable_irq0(hw);
5806
5807         return 0;
5808
5809 err_vsi_setup:
5810         for (i = 0; i < conf_vsis; i++)
5811                 if (pf->vmdq[i].vsi == NULL)
5812                         break;
5813                 else
5814                         i40e_vsi_release(pf->vmdq[i].vsi);
5815
5816         rte_free(pf->vmdq);
5817         pf->vmdq = NULL;
5818         i40e_pf_enable_irq0(hw);
5819         return err;
5820 }
5821
5822 static void
5823 i40e_stat_update_32(struct i40e_hw *hw,
5824                    uint32_t reg,
5825                    bool offset_loaded,
5826                    uint64_t *offset,
5827                    uint64_t *stat)
5828 {
5829         uint64_t new_data;
5830
5831         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5832         if (!offset_loaded)
5833                 *offset = new_data;
5834
5835         if (new_data >= *offset)
5836                 *stat = (uint64_t)(new_data - *offset);
5837         else
5838                 *stat = (uint64_t)((new_data +
5839                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5840 }
5841
5842 static void
5843 i40e_stat_update_48(struct i40e_hw *hw,
5844                    uint32_t hireg,
5845                    uint32_t loreg,
5846                    bool offset_loaded,
5847                    uint64_t *offset,
5848                    uint64_t *stat)
5849 {
5850         uint64_t new_data;
5851
5852         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5853         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5854                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5855
5856         if (!offset_loaded)
5857                 *offset = new_data;
5858
5859         if (new_data >= *offset)
5860                 *stat = new_data - *offset;
5861         else
5862                 *stat = (uint64_t)((new_data +
5863                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5864
5865         *stat &= I40E_48_BIT_MASK;
5866 }
5867
5868 /* Disable IRQ0 */
5869 void
5870 i40e_pf_disable_irq0(struct i40e_hw *hw)
5871 {
5872         /* Disable all interrupt types */
5873         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5874         I40E_WRITE_FLUSH(hw);
5875 }
5876
5877 /* Enable IRQ0 */
5878 void
5879 i40e_pf_enable_irq0(struct i40e_hw *hw)
5880 {
5881         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5882                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5883                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5884                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5885         I40E_WRITE_FLUSH(hw);
5886 }
5887
5888 static void
5889 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5890 {
5891         /* read pending request and disable first */
5892         i40e_pf_disable_irq0(hw);
5893         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5894         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5895                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5896
5897         if (no_queue)
5898                 /* Link no queues with irq0 */
5899                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5900                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5901 }
5902
5903 static void
5904 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5905 {
5906         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5907         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5908         int i;
5909         uint16_t abs_vf_id;
5910         uint32_t index, offset, val;
5911
5912         if (!pf->vfs)
5913                 return;
5914         /**
5915          * Try to find which VF trigger a reset, use absolute VF id to access
5916          * since the reg is global register.
5917          */
5918         for (i = 0; i < pf->vf_num; i++) {
5919                 abs_vf_id = hw->func_caps.vf_base_id + i;
5920                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5921                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5922                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5923                 /* VFR event occurred */
5924                 if (val & (0x1 << offset)) {
5925                         int ret;
5926
5927                         /* Clear the event first */
5928                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5929                                                         (0x1 << offset));
5930                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5931                         /**
5932                          * Only notify a VF reset event occurred,
5933                          * don't trigger another SW reset
5934                          */
5935                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5936                         if (ret != I40E_SUCCESS)
5937                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5938                 }
5939         }
5940 }
5941
5942 static void
5943 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5944 {
5945         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5946         int i;
5947
5948         for (i = 0; i < pf->vf_num; i++)
5949                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5950 }
5951
5952 static void
5953 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5954 {
5955         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5956         struct i40e_arq_event_info info;
5957         uint16_t pending, opcode;
5958         int ret;
5959
5960         info.buf_len = I40E_AQ_BUF_SZ;
5961         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5962         if (!info.msg_buf) {
5963                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5964                 return;
5965         }
5966
5967         pending = 1;
5968         while (pending) {
5969                 ret = i40e_clean_arq_element(hw, &info, &pending);
5970
5971                 if (ret != I40E_SUCCESS) {
5972                         PMD_DRV_LOG(INFO,
5973                                 "Failed to read msg from AdminQ, aq_err: %u",
5974                                 hw->aq.asq_last_status);
5975                         break;
5976                 }
5977                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5978
5979                 switch (opcode) {
5980                 case i40e_aqc_opc_send_msg_to_pf:
5981                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5982                         i40e_pf_host_handle_vf_msg(dev,
5983                                         rte_le_to_cpu_16(info.desc.retval),
5984                                         rte_le_to_cpu_32(info.desc.cookie_high),
5985                                         rte_le_to_cpu_32(info.desc.cookie_low),
5986                                         info.msg_buf,
5987                                         info.msg_len);
5988                         break;
5989                 case i40e_aqc_opc_get_link_status:
5990                         ret = i40e_dev_link_update(dev, 0);
5991                         if (!ret)
5992                                 _rte_eth_dev_callback_process(dev,
5993                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5994                         break;
5995                 default:
5996                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5997                                     opcode);
5998                         break;
5999                 }
6000         }
6001         rte_free(info.msg_buf);
6002 }
6003
6004 /**
6005  * Interrupt handler triggered by NIC  for handling
6006  * specific interrupt.
6007  *
6008  * @param handle
6009  *  Pointer to interrupt handle.
6010  * @param param
6011  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6012  *
6013  * @return
6014  *  void
6015  */
6016 static void
6017 i40e_dev_interrupt_handler(void *param)
6018 {
6019         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6020         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6021         uint32_t icr0;
6022
6023         /* Disable interrupt */
6024         i40e_pf_disable_irq0(hw);
6025
6026         /* read out interrupt causes */
6027         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6028
6029         /* No interrupt event indicated */
6030         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6031                 PMD_DRV_LOG(INFO, "No interrupt event");
6032                 goto done;
6033         }
6034         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6035                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6036         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6037                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6038         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6039                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6040         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6041                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6042         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6043                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6044         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6045                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6046         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6047                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6048
6049         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6050                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6051                 i40e_dev_handle_vfr_event(dev);
6052         }
6053         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6054                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6055                 i40e_dev_handle_aq_msg(dev);
6056         }
6057
6058 done:
6059         /* Enable interrupt */
6060         i40e_pf_enable_irq0(hw);
6061         rte_intr_enable(dev->intr_handle);
6062 }
6063
6064 int
6065 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6066                          struct i40e_macvlan_filter *filter,
6067                          int total)
6068 {
6069         int ele_num, ele_buff_size;
6070         int num, actual_num, i;
6071         uint16_t flags;
6072         int ret = I40E_SUCCESS;
6073         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6074         struct i40e_aqc_add_macvlan_element_data *req_list;
6075
6076         if (filter == NULL  || total == 0)
6077                 return I40E_ERR_PARAM;
6078         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6079         ele_buff_size = hw->aq.asq_buf_size;
6080
6081         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6082         if (req_list == NULL) {
6083                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6084                 return I40E_ERR_NO_MEMORY;
6085         }
6086
6087         num = 0;
6088         do {
6089                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6090                 memset(req_list, 0, ele_buff_size);
6091
6092                 for (i = 0; i < actual_num; i++) {
6093                         rte_memcpy(req_list[i].mac_addr,
6094                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6095                         req_list[i].vlan_tag =
6096                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6097
6098                         switch (filter[num + i].filter_type) {
6099                         case RTE_MAC_PERFECT_MATCH:
6100                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6101                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6102                                 break;
6103                         case RTE_MACVLAN_PERFECT_MATCH:
6104                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6105                                 break;
6106                         case RTE_MAC_HASH_MATCH:
6107                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6108                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6109                                 break;
6110                         case RTE_MACVLAN_HASH_MATCH:
6111                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6112                                 break;
6113                         default:
6114                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6115                                 ret = I40E_ERR_PARAM;
6116                                 goto DONE;
6117                         }
6118
6119                         req_list[i].queue_number = 0;
6120
6121                         req_list[i].flags = rte_cpu_to_le_16(flags);
6122                 }
6123
6124                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6125                                                 actual_num, NULL);
6126                 if (ret != I40E_SUCCESS) {
6127                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6128                         goto DONE;
6129                 }
6130                 num += actual_num;
6131         } while (num < total);
6132
6133 DONE:
6134         rte_free(req_list);
6135         return ret;
6136 }
6137
6138 int
6139 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6140                             struct i40e_macvlan_filter *filter,
6141                             int total)
6142 {
6143         int ele_num, ele_buff_size;
6144         int num, actual_num, i;
6145         uint16_t flags;
6146         int ret = I40E_SUCCESS;
6147         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6148         struct i40e_aqc_remove_macvlan_element_data *req_list;
6149
6150         if (filter == NULL  || total == 0)
6151                 return I40E_ERR_PARAM;
6152
6153         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6154         ele_buff_size = hw->aq.asq_buf_size;
6155
6156         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6157         if (req_list == NULL) {
6158                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6159                 return I40E_ERR_NO_MEMORY;
6160         }
6161
6162         num = 0;
6163         do {
6164                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6165                 memset(req_list, 0, ele_buff_size);
6166
6167                 for (i = 0; i < actual_num; i++) {
6168                         rte_memcpy(req_list[i].mac_addr,
6169                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6170                         req_list[i].vlan_tag =
6171                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6172
6173                         switch (filter[num + i].filter_type) {
6174                         case RTE_MAC_PERFECT_MATCH:
6175                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6176                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6177                                 break;
6178                         case RTE_MACVLAN_PERFECT_MATCH:
6179                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6180                                 break;
6181                         case RTE_MAC_HASH_MATCH:
6182                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6183                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6184                                 break;
6185                         case RTE_MACVLAN_HASH_MATCH:
6186                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6187                                 break;
6188                         default:
6189                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6190                                 ret = I40E_ERR_PARAM;
6191                                 goto DONE;
6192                         }
6193                         req_list[i].flags = rte_cpu_to_le_16(flags);
6194                 }
6195
6196                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6197                                                 actual_num, NULL);
6198                 if (ret != I40E_SUCCESS) {
6199                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6200                         goto DONE;
6201                 }
6202                 num += actual_num;
6203         } while (num < total);
6204
6205 DONE:
6206         rte_free(req_list);
6207         return ret;
6208 }
6209
6210 /* Find out specific MAC filter */
6211 static struct i40e_mac_filter *
6212 i40e_find_mac_filter(struct i40e_vsi *vsi,
6213                          struct ether_addr *macaddr)
6214 {
6215         struct i40e_mac_filter *f;
6216
6217         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6218                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6219                         return f;
6220         }
6221
6222         return NULL;
6223 }
6224
6225 static bool
6226 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6227                          uint16_t vlan_id)
6228 {
6229         uint32_t vid_idx, vid_bit;
6230
6231         if (vlan_id > ETH_VLAN_ID_MAX)
6232                 return 0;
6233
6234         vid_idx = I40E_VFTA_IDX(vlan_id);
6235         vid_bit = I40E_VFTA_BIT(vlan_id);
6236
6237         if (vsi->vfta[vid_idx] & vid_bit)
6238                 return 1;
6239         else
6240                 return 0;
6241 }
6242
6243 static void
6244 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6245                        uint16_t vlan_id, bool on)
6246 {
6247         uint32_t vid_idx, vid_bit;
6248
6249         vid_idx = I40E_VFTA_IDX(vlan_id);
6250         vid_bit = I40E_VFTA_BIT(vlan_id);
6251
6252         if (on)
6253                 vsi->vfta[vid_idx] |= vid_bit;
6254         else
6255                 vsi->vfta[vid_idx] &= ~vid_bit;
6256 }
6257
6258 void
6259 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6260                      uint16_t vlan_id, bool on)
6261 {
6262         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6263         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6264         int ret;
6265
6266         if (vlan_id > ETH_VLAN_ID_MAX)
6267                 return;
6268
6269         i40e_store_vlan_filter(vsi, vlan_id, on);
6270
6271         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6272                 return;
6273
6274         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6275
6276         if (on) {
6277                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6278                                        &vlan_data, 1, NULL);
6279                 if (ret != I40E_SUCCESS)
6280                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6281         } else {
6282                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6283                                           &vlan_data, 1, NULL);
6284                 if (ret != I40E_SUCCESS)
6285                         PMD_DRV_LOG(ERR,
6286                                     "Failed to remove vlan filter");
6287         }
6288 }
6289
6290 /**
6291  * Find all vlan options for specific mac addr,
6292  * return with actual vlan found.
6293  */
6294 int
6295 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6296                            struct i40e_macvlan_filter *mv_f,
6297                            int num, struct ether_addr *addr)
6298 {
6299         int i;
6300         uint32_t j, k;
6301
6302         /**
6303          * Not to use i40e_find_vlan_filter to decrease the loop time,
6304          * although the code looks complex.
6305           */
6306         if (num < vsi->vlan_num)
6307                 return I40E_ERR_PARAM;
6308
6309         i = 0;
6310         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6311                 if (vsi->vfta[j]) {
6312                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6313                                 if (vsi->vfta[j] & (1 << k)) {
6314                                         if (i > num - 1) {
6315                                                 PMD_DRV_LOG(ERR,
6316                                                         "vlan number doesn't match");
6317                                                 return I40E_ERR_PARAM;
6318                                         }
6319                                         rte_memcpy(&mv_f[i].macaddr,
6320                                                         addr, ETH_ADDR_LEN);
6321                                         mv_f[i].vlan_id =
6322                                                 j * I40E_UINT32_BIT_SIZE + k;
6323                                         i++;
6324                                 }
6325                         }
6326                 }
6327         }
6328         return I40E_SUCCESS;
6329 }
6330
6331 static inline int
6332 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6333                            struct i40e_macvlan_filter *mv_f,
6334                            int num,
6335                            uint16_t vlan)
6336 {
6337         int i = 0;
6338         struct i40e_mac_filter *f;
6339
6340         if (num < vsi->mac_num)
6341                 return I40E_ERR_PARAM;
6342
6343         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6344                 if (i > num - 1) {
6345                         PMD_DRV_LOG(ERR, "buffer number not match");
6346                         return I40E_ERR_PARAM;
6347                 }
6348                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6349                                 ETH_ADDR_LEN);
6350                 mv_f[i].vlan_id = vlan;
6351                 mv_f[i].filter_type = f->mac_info.filter_type;
6352                 i++;
6353         }
6354
6355         return I40E_SUCCESS;
6356 }
6357
6358 static int
6359 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6360 {
6361         int i, j, num;
6362         struct i40e_mac_filter *f;
6363         struct i40e_macvlan_filter *mv_f;
6364         int ret = I40E_SUCCESS;
6365
6366         if (vsi == NULL || vsi->mac_num == 0)
6367                 return I40E_ERR_PARAM;
6368
6369         /* Case that no vlan is set */
6370         if (vsi->vlan_num == 0)
6371                 num = vsi->mac_num;
6372         else
6373                 num = vsi->mac_num * vsi->vlan_num;
6374
6375         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6376         if (mv_f == NULL) {
6377                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6378                 return I40E_ERR_NO_MEMORY;
6379         }
6380
6381         i = 0;
6382         if (vsi->vlan_num == 0) {
6383                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6384                         rte_memcpy(&mv_f[i].macaddr,
6385                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6386                         mv_f[i].filter_type = f->mac_info.filter_type;
6387                         mv_f[i].vlan_id = 0;
6388                         i++;
6389                 }
6390         } else {
6391                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6392                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6393                                         vsi->vlan_num, &f->mac_info.mac_addr);
6394                         if (ret != I40E_SUCCESS)
6395                                 goto DONE;
6396                         for (j = i; j < i + vsi->vlan_num; j++)
6397                                 mv_f[j].filter_type = f->mac_info.filter_type;
6398                         i += vsi->vlan_num;
6399                 }
6400         }
6401
6402         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6403 DONE:
6404         rte_free(mv_f);
6405
6406         return ret;
6407 }
6408
6409 int
6410 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6411 {
6412         struct i40e_macvlan_filter *mv_f;
6413         int mac_num;
6414         int ret = I40E_SUCCESS;
6415
6416         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6417                 return I40E_ERR_PARAM;
6418
6419         /* If it's already set, just return */
6420         if (i40e_find_vlan_filter(vsi,vlan))
6421                 return I40E_SUCCESS;
6422
6423         mac_num = vsi->mac_num;
6424
6425         if (mac_num == 0) {
6426                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6427                 return I40E_ERR_PARAM;
6428         }
6429
6430         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6431
6432         if (mv_f == NULL) {
6433                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6434                 return I40E_ERR_NO_MEMORY;
6435         }
6436
6437         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6438
6439         if (ret != I40E_SUCCESS)
6440                 goto DONE;
6441
6442         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6443
6444         if (ret != I40E_SUCCESS)
6445                 goto DONE;
6446
6447         i40e_set_vlan_filter(vsi, vlan, 1);
6448
6449         vsi->vlan_num++;
6450         ret = I40E_SUCCESS;
6451 DONE:
6452         rte_free(mv_f);
6453         return ret;
6454 }
6455
6456 int
6457 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6458 {
6459         struct i40e_macvlan_filter *mv_f;
6460         int mac_num;
6461         int ret = I40E_SUCCESS;
6462
6463         /**
6464          * Vlan 0 is the generic filter for untagged packets
6465          * and can't be removed.
6466          */
6467         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6468                 return I40E_ERR_PARAM;
6469
6470         /* If can't find it, just return */
6471         if (!i40e_find_vlan_filter(vsi, vlan))
6472                 return I40E_ERR_PARAM;
6473
6474         mac_num = vsi->mac_num;
6475
6476         if (mac_num == 0) {
6477                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6478                 return I40E_ERR_PARAM;
6479         }
6480
6481         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6482
6483         if (mv_f == NULL) {
6484                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6485                 return I40E_ERR_NO_MEMORY;
6486         }
6487
6488         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6489
6490         if (ret != I40E_SUCCESS)
6491                 goto DONE;
6492
6493         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6494
6495         if (ret != I40E_SUCCESS)
6496                 goto DONE;
6497
6498         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6499         if (vsi->vlan_num == 1) {
6500                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6501                 if (ret != I40E_SUCCESS)
6502                         goto DONE;
6503
6504                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6505                 if (ret != I40E_SUCCESS)
6506                         goto DONE;
6507         }
6508
6509         i40e_set_vlan_filter(vsi, vlan, 0);
6510
6511         vsi->vlan_num--;
6512         ret = I40E_SUCCESS;
6513 DONE:
6514         rte_free(mv_f);
6515         return ret;
6516 }
6517
6518 int
6519 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6520 {
6521         struct i40e_mac_filter *f;
6522         struct i40e_macvlan_filter *mv_f;
6523         int i, vlan_num = 0;
6524         int ret = I40E_SUCCESS;
6525
6526         /* If it's add and we've config it, return */
6527         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6528         if (f != NULL)
6529                 return I40E_SUCCESS;
6530         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6531                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6532
6533                 /**
6534                  * If vlan_num is 0, that's the first time to add mac,
6535                  * set mask for vlan_id 0.
6536                  */
6537                 if (vsi->vlan_num == 0) {
6538                         i40e_set_vlan_filter(vsi, 0, 1);
6539                         vsi->vlan_num = 1;
6540                 }
6541                 vlan_num = vsi->vlan_num;
6542         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6543                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6544                 vlan_num = 1;
6545
6546         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6547         if (mv_f == NULL) {
6548                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6549                 return I40E_ERR_NO_MEMORY;
6550         }
6551
6552         for (i = 0; i < vlan_num; i++) {
6553                 mv_f[i].filter_type = mac_filter->filter_type;
6554                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6555                                 ETH_ADDR_LEN);
6556         }
6557
6558         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6559                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6560                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6561                                         &mac_filter->mac_addr);
6562                 if (ret != I40E_SUCCESS)
6563                         goto DONE;
6564         }
6565
6566         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6567         if (ret != I40E_SUCCESS)
6568                 goto DONE;
6569
6570         /* Add the mac addr into mac list */
6571         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6572         if (f == NULL) {
6573                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6574                 ret = I40E_ERR_NO_MEMORY;
6575                 goto DONE;
6576         }
6577         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6578                         ETH_ADDR_LEN);
6579         f->mac_info.filter_type = mac_filter->filter_type;
6580         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6581         vsi->mac_num++;
6582
6583         ret = I40E_SUCCESS;
6584 DONE:
6585         rte_free(mv_f);
6586
6587         return ret;
6588 }
6589
6590 int
6591 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6592 {
6593         struct i40e_mac_filter *f;
6594         struct i40e_macvlan_filter *mv_f;
6595         int i, vlan_num;
6596         enum rte_mac_filter_type filter_type;
6597         int ret = I40E_SUCCESS;
6598
6599         /* Can't find it, return an error */
6600         f = i40e_find_mac_filter(vsi, addr);
6601         if (f == NULL)
6602                 return I40E_ERR_PARAM;
6603
6604         vlan_num = vsi->vlan_num;
6605         filter_type = f->mac_info.filter_type;
6606         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6607                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6608                 if (vlan_num == 0) {
6609                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6610                         return I40E_ERR_PARAM;
6611                 }
6612         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6613                         filter_type == RTE_MAC_HASH_MATCH)
6614                 vlan_num = 1;
6615
6616         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6617         if (mv_f == NULL) {
6618                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6619                 return I40E_ERR_NO_MEMORY;
6620         }
6621
6622         for (i = 0; i < vlan_num; i++) {
6623                 mv_f[i].filter_type = filter_type;
6624                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6625                                 ETH_ADDR_LEN);
6626         }
6627         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6628                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6629                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6630                 if (ret != I40E_SUCCESS)
6631                         goto DONE;
6632         }
6633
6634         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6635         if (ret != I40E_SUCCESS)
6636                 goto DONE;
6637
6638         /* Remove the mac addr into mac list */
6639         TAILQ_REMOVE(&vsi->mac_list, f, next);
6640         rte_free(f);
6641         vsi->mac_num--;
6642
6643         ret = I40E_SUCCESS;
6644 DONE:
6645         rte_free(mv_f);
6646         return ret;
6647 }
6648
6649 /* Configure hash enable flags for RSS */
6650 uint64_t
6651 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6652 {
6653         uint64_t hena = 0;
6654         int i;
6655
6656         if (!flags)
6657                 return hena;
6658
6659         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6660                 if (flags & (1ULL << i))
6661                         hena |= adapter->pctypes_tbl[i];
6662         }
6663
6664         return hena;
6665 }
6666
6667 /* Parse the hash enable flags */
6668 uint64_t
6669 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6670 {
6671         uint64_t rss_hf = 0;
6672
6673         if (!flags)
6674                 return rss_hf;
6675         int i;
6676
6677         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6678                 if (flags & adapter->pctypes_tbl[i])
6679                         rss_hf |= (1ULL << i);
6680         }
6681         return rss_hf;
6682 }
6683
6684 /* Disable RSS */
6685 static void
6686 i40e_pf_disable_rss(struct i40e_pf *pf)
6687 {
6688         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6689
6690         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6691         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6692         I40E_WRITE_FLUSH(hw);
6693 }
6694
6695 static int
6696 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6697 {
6698         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6699         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6700         int ret = 0;
6701
6702         if (!key || key_len == 0) {
6703                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6704                 return 0;
6705         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6706                 sizeof(uint32_t)) {
6707                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6708                 return -EINVAL;
6709         }
6710
6711         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6712                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6713                         (struct i40e_aqc_get_set_rss_key_data *)key;
6714
6715                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6716                 if (ret)
6717                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6718         } else {
6719                 uint32_t *hash_key = (uint32_t *)key;
6720                 uint16_t i;
6721
6722                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6723                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6724                 I40E_WRITE_FLUSH(hw);
6725         }
6726
6727         return ret;
6728 }
6729
6730 static int
6731 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6732 {
6733         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6734         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6735         int ret;
6736
6737         if (!key || !key_len)
6738                 return -EINVAL;
6739
6740         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6741                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6742                         (struct i40e_aqc_get_set_rss_key_data *)key);
6743                 if (ret) {
6744                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6745                         return ret;
6746                 }
6747         } else {
6748                 uint32_t *key_dw = (uint32_t *)key;
6749                 uint16_t i;
6750
6751                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6752                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6753         }
6754         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6755
6756         return 0;
6757 }
6758
6759 static int
6760 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6761 {
6762         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6763         uint64_t hena;
6764         int ret;
6765
6766         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6767                                rss_conf->rss_key_len);
6768         if (ret)
6769                 return ret;
6770
6771         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6772         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6773         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6774         I40E_WRITE_FLUSH(hw);
6775
6776         return 0;
6777 }
6778
6779 static int
6780 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6781                          struct rte_eth_rss_conf *rss_conf)
6782 {
6783         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6784         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6785         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6786         uint64_t hena;
6787
6788         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6789         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6790
6791         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6792                 if (rss_hf != 0) /* Enable RSS */
6793                         return -EINVAL;
6794                 return 0; /* Nothing to do */
6795         }
6796         /* RSS enabled */
6797         if (rss_hf == 0) /* Disable RSS */
6798                 return -EINVAL;
6799
6800         return i40e_hw_rss_hash_set(pf, rss_conf);
6801 }
6802
6803 static int
6804 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6805                            struct rte_eth_rss_conf *rss_conf)
6806 {
6807         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6808         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6809         uint64_t hena;
6810
6811         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6812                          &rss_conf->rss_key_len);
6813
6814         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6815         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6816         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6817
6818         return 0;
6819 }
6820
6821 static int
6822 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6823 {
6824         switch (filter_type) {
6825         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6826                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6827                 break;
6828         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6829                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6830                 break;
6831         case RTE_TUNNEL_FILTER_IMAC_TENID:
6832                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6833                 break;
6834         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6835                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6836                 break;
6837         case ETH_TUNNEL_FILTER_IMAC:
6838                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6839                 break;
6840         case ETH_TUNNEL_FILTER_OIP:
6841                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6842                 break;
6843         case ETH_TUNNEL_FILTER_IIP:
6844                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6845                 break;
6846         default:
6847                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6848                 return -EINVAL;
6849         }
6850
6851         return 0;
6852 }
6853
6854 /* Convert tunnel filter structure */
6855 static int
6856 i40e_tunnel_filter_convert(
6857         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6858         struct i40e_tunnel_filter *tunnel_filter)
6859 {
6860         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6861                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6862         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6863                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6864         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6865         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6866              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6867             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6868                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6869         else
6870                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6871         tunnel_filter->input.flags = cld_filter->element.flags;
6872         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6873         tunnel_filter->queue = cld_filter->element.queue_number;
6874         rte_memcpy(tunnel_filter->input.general_fields,
6875                    cld_filter->general_fields,
6876                    sizeof(cld_filter->general_fields));
6877
6878         return 0;
6879 }
6880
6881 /* Check if there exists the tunnel filter */
6882 struct i40e_tunnel_filter *
6883 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6884                              const struct i40e_tunnel_filter_input *input)
6885 {
6886         int ret;
6887
6888         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6889         if (ret < 0)
6890                 return NULL;
6891
6892         return tunnel_rule->hash_map[ret];
6893 }
6894
6895 /* Add a tunnel filter into the SW list */
6896 static int
6897 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6898                              struct i40e_tunnel_filter *tunnel_filter)
6899 {
6900         struct i40e_tunnel_rule *rule = &pf->tunnel;
6901         int ret;
6902
6903         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6904         if (ret < 0) {
6905                 PMD_DRV_LOG(ERR,
6906                             "Failed to insert tunnel filter to hash table %d!",
6907                             ret);
6908                 return ret;
6909         }
6910         rule->hash_map[ret] = tunnel_filter;
6911
6912         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6913
6914         return 0;
6915 }
6916
6917 /* Delete a tunnel filter from the SW list */
6918 int
6919 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6920                           struct i40e_tunnel_filter_input *input)
6921 {
6922         struct i40e_tunnel_rule *rule = &pf->tunnel;
6923         struct i40e_tunnel_filter *tunnel_filter;
6924         int ret;
6925
6926         ret = rte_hash_del_key(rule->hash_table, input);
6927         if (ret < 0) {
6928                 PMD_DRV_LOG(ERR,
6929                             "Failed to delete tunnel filter to hash table %d!",
6930                             ret);
6931                 return ret;
6932         }
6933         tunnel_filter = rule->hash_map[ret];
6934         rule->hash_map[ret] = NULL;
6935
6936         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6937         rte_free(tunnel_filter);
6938
6939         return 0;
6940 }
6941
6942 int
6943 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6944                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6945                         uint8_t add)
6946 {
6947         uint16_t ip_type;
6948         uint32_t ipv4_addr;
6949         uint8_t i, tun_type = 0;
6950         /* internal varialbe to convert ipv6 byte order */
6951         uint32_t convert_ipv6[4];
6952         int val, ret = 0;
6953         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6954         struct i40e_vsi *vsi = pf->main_vsi;
6955         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6956         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6957         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6958         struct i40e_tunnel_filter *tunnel, *node;
6959         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6960
6961         cld_filter = rte_zmalloc("tunnel_filter",
6962                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6963         0);
6964
6965         if (NULL == cld_filter) {
6966                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6967                 return -ENOMEM;
6968         }
6969         pfilter = cld_filter;
6970
6971         ether_addr_copy(&tunnel_filter->outer_mac,
6972                         (struct ether_addr *)&pfilter->element.outer_mac);
6973         ether_addr_copy(&tunnel_filter->inner_mac,
6974                         (struct ether_addr *)&pfilter->element.inner_mac);
6975
6976         pfilter->element.inner_vlan =
6977                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6978         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6979                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6980                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6981                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6982                                 &rte_cpu_to_le_32(ipv4_addr),
6983                                 sizeof(pfilter->element.ipaddr.v4.data));
6984         } else {
6985                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6986                 for (i = 0; i < 4; i++) {
6987                         convert_ipv6[i] =
6988                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6989                 }
6990                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6991                            &convert_ipv6,
6992                            sizeof(pfilter->element.ipaddr.v6.data));
6993         }
6994
6995         /* check tunneled type */
6996         switch (tunnel_filter->tunnel_type) {
6997         case RTE_TUNNEL_TYPE_VXLAN:
6998                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6999                 break;
7000         case RTE_TUNNEL_TYPE_NVGRE:
7001                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7002                 break;
7003         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7004                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7005                 break;
7006         default:
7007                 /* Other tunnel types is not supported. */
7008                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7009                 rte_free(cld_filter);
7010                 return -EINVAL;
7011         }
7012
7013         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7014                                        &pfilter->element.flags);
7015         if (val < 0) {
7016                 rte_free(cld_filter);
7017                 return -EINVAL;
7018         }
7019
7020         pfilter->element.flags |= rte_cpu_to_le_16(
7021                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7022                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7023         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7024         pfilter->element.queue_number =
7025                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7026
7027         /* Check if there is the filter in SW list */
7028         memset(&check_filter, 0, sizeof(check_filter));
7029         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7030         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7031         if (add && node) {
7032                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7033                 return -EINVAL;
7034         }
7035
7036         if (!add && !node) {
7037                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7038                 return -EINVAL;
7039         }
7040
7041         if (add) {
7042                 ret = i40e_aq_add_cloud_filters(hw,
7043                                         vsi->seid, &cld_filter->element, 1);
7044                 if (ret < 0) {
7045                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7046                         return -ENOTSUP;
7047                 }
7048                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7049                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7050                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7051         } else {
7052                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7053                                                    &cld_filter->element, 1);
7054                 if (ret < 0) {
7055                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7056                         return -ENOTSUP;
7057                 }
7058                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7059         }
7060
7061         rte_free(cld_filter);
7062         return ret;
7063 }
7064
7065 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7066 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7067 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7068 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7069 #define I40E_TR_GRE_KEY_MASK                    0x400
7070 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7071 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7072
7073 static enum
7074 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7075 {
7076         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7077         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7078         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7079         enum i40e_status_code status = I40E_SUCCESS;
7080
7081         memset(&filter_replace, 0,
7082                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7083         memset(&filter_replace_buf, 0,
7084                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7085
7086         /* create L1 filter */
7087         filter_replace.old_filter_type =
7088                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7089         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7090         filter_replace.tr_bit = 0;
7091
7092         /* Prepare the buffer, 3 entries */
7093         filter_replace_buf.data[0] =
7094                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7095         filter_replace_buf.data[0] |=
7096                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7097         filter_replace_buf.data[2] = 0xFF;
7098         filter_replace_buf.data[3] = 0xFF;
7099         filter_replace_buf.data[4] =
7100                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7101         filter_replace_buf.data[4] |=
7102                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7103         filter_replace_buf.data[7] = 0xF0;
7104         filter_replace_buf.data[8]
7105                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7106         filter_replace_buf.data[8] |=
7107                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7108         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7109                 I40E_TR_GENEVE_KEY_MASK |
7110                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7111         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7112                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7113                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7114
7115         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7116                                                &filter_replace_buf);
7117         return status;
7118 }
7119
7120 static enum
7121 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7122 {
7123         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7124         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7125         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7126         enum i40e_status_code status = I40E_SUCCESS;
7127
7128         /* For MPLSoUDP */
7129         memset(&filter_replace, 0,
7130                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7131         memset(&filter_replace_buf, 0,
7132                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7133         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7134                 I40E_AQC_MIRROR_CLOUD_FILTER;
7135         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7136         filter_replace.new_filter_type =
7137                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7138         /* Prepare the buffer, 2 entries */
7139         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7140         filter_replace_buf.data[0] |=
7141                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7142         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7143         filter_replace_buf.data[4] |=
7144                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7145         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7146                                                &filter_replace_buf);
7147         if (status < 0)
7148                 return status;
7149
7150         /* For MPLSoGRE */
7151         memset(&filter_replace, 0,
7152                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7153         memset(&filter_replace_buf, 0,
7154                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7155
7156         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7157                 I40E_AQC_MIRROR_CLOUD_FILTER;
7158         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7159         filter_replace.new_filter_type =
7160                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7161         /* Prepare the buffer, 2 entries */
7162         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7163         filter_replace_buf.data[0] |=
7164                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7165         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7166         filter_replace_buf.data[4] |=
7167                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7168
7169         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7170                                                &filter_replace_buf);
7171         return status;
7172 }
7173
7174 static enum i40e_status_code
7175 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7176 {
7177         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7178         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7179         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7180         enum i40e_status_code status = I40E_SUCCESS;
7181
7182         /* For GTP-C */
7183         memset(&filter_replace, 0,
7184                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7185         memset(&filter_replace_buf, 0,
7186                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7187         /* create L1 filter */
7188         filter_replace.old_filter_type =
7189                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7190         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7191         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7192                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7193         /* Prepare the buffer, 2 entries */
7194         filter_replace_buf.data[0] =
7195                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7196         filter_replace_buf.data[0] |=
7197                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7198         filter_replace_buf.data[2] = 0xFF;
7199         filter_replace_buf.data[3] = 0xFF;
7200         filter_replace_buf.data[4] =
7201                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7202         filter_replace_buf.data[4] |=
7203                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7204         filter_replace_buf.data[6] = 0xFF;
7205         filter_replace_buf.data[7] = 0xFF;
7206         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7207                                                &filter_replace_buf);
7208         if (status < 0)
7209                 return status;
7210
7211         /* for GTP-U */
7212         memset(&filter_replace, 0,
7213                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7214         memset(&filter_replace_buf, 0,
7215                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7216         /* create L1 filter */
7217         filter_replace.old_filter_type =
7218                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7219         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7220         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7221                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7222         /* Prepare the buffer, 2 entries */
7223         filter_replace_buf.data[0] =
7224                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7225         filter_replace_buf.data[0] |=
7226                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7227         filter_replace_buf.data[2] = 0xFF;
7228         filter_replace_buf.data[3] = 0xFF;
7229         filter_replace_buf.data[4] =
7230                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7231         filter_replace_buf.data[4] |=
7232                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7233         filter_replace_buf.data[6] = 0xFF;
7234         filter_replace_buf.data[7] = 0xFF;
7235
7236         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7237                                                &filter_replace_buf);
7238         return status;
7239 }
7240
7241 static enum
7242 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7243 {
7244         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7245         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7246         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7247         enum i40e_status_code status = I40E_SUCCESS;
7248
7249         /* for GTP-C */
7250         memset(&filter_replace, 0,
7251                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7252         memset(&filter_replace_buf, 0,
7253                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7254         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7255         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7256         filter_replace.new_filter_type =
7257                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7258         /* Prepare the buffer, 2 entries */
7259         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7260         filter_replace_buf.data[0] |=
7261                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7262         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7263         filter_replace_buf.data[4] |=
7264                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7265         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7266                                                &filter_replace_buf);
7267         if (status < 0)
7268                 return status;
7269
7270         /* for GTP-U */
7271         memset(&filter_replace, 0,
7272                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7273         memset(&filter_replace_buf, 0,
7274                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7275         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7276         filter_replace.old_filter_type =
7277                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7278         filter_replace.new_filter_type =
7279                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7280         /* Prepare the buffer, 2 entries */
7281         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7282         filter_replace_buf.data[0] |=
7283                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7284         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7285         filter_replace_buf.data[4] |=
7286                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7287
7288         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7289                                                &filter_replace_buf);
7290         return status;
7291 }
7292
7293 int
7294 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7295                       struct i40e_tunnel_filter_conf *tunnel_filter,
7296                       uint8_t add)
7297 {
7298         uint16_t ip_type;
7299         uint32_t ipv4_addr;
7300         uint8_t i, tun_type = 0;
7301         /* internal variable to convert ipv6 byte order */
7302         uint32_t convert_ipv6[4];
7303         int val, ret = 0;
7304         struct i40e_pf_vf *vf = NULL;
7305         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7306         struct i40e_vsi *vsi;
7307         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7308         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7309         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7310         struct i40e_tunnel_filter *tunnel, *node;
7311         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7312         uint32_t teid_le;
7313         bool big_buffer = 0;
7314
7315         cld_filter = rte_zmalloc("tunnel_filter",
7316                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7317                          0);
7318
7319         if (cld_filter == NULL) {
7320                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7321                 return -ENOMEM;
7322         }
7323         pfilter = cld_filter;
7324
7325         ether_addr_copy(&tunnel_filter->outer_mac,
7326                         (struct ether_addr *)&pfilter->element.outer_mac);
7327         ether_addr_copy(&tunnel_filter->inner_mac,
7328                         (struct ether_addr *)&pfilter->element.inner_mac);
7329
7330         pfilter->element.inner_vlan =
7331                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7332         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7333                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7334                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7335                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7336                                 &rte_cpu_to_le_32(ipv4_addr),
7337                                 sizeof(pfilter->element.ipaddr.v4.data));
7338         } else {
7339                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7340                 for (i = 0; i < 4; i++) {
7341                         convert_ipv6[i] =
7342                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7343                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7344                 }
7345                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7346                            &convert_ipv6,
7347                            sizeof(pfilter->element.ipaddr.v6.data));
7348         }
7349
7350         /* check tunneled type */
7351         switch (tunnel_filter->tunnel_type) {
7352         case I40E_TUNNEL_TYPE_VXLAN:
7353                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7354                 break;
7355         case I40E_TUNNEL_TYPE_NVGRE:
7356                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7357                 break;
7358         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7359                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7360                 break;
7361         case I40E_TUNNEL_TYPE_MPLSoUDP:
7362                 if (!pf->mpls_replace_flag) {
7363                         i40e_replace_mpls_l1_filter(pf);
7364                         i40e_replace_mpls_cloud_filter(pf);
7365                         pf->mpls_replace_flag = 1;
7366                 }
7367                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7368                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7369                         teid_le >> 4;
7370                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7371                         (teid_le & 0xF) << 12;
7372                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7373                         0x40;
7374                 big_buffer = 1;
7375                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7376                 break;
7377         case I40E_TUNNEL_TYPE_MPLSoGRE:
7378                 if (!pf->mpls_replace_flag) {
7379                         i40e_replace_mpls_l1_filter(pf);
7380                         i40e_replace_mpls_cloud_filter(pf);
7381                         pf->mpls_replace_flag = 1;
7382                 }
7383                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7384                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7385                         teid_le >> 4;
7386                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7387                         (teid_le & 0xF) << 12;
7388                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7389                         0x0;
7390                 big_buffer = 1;
7391                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7392                 break;
7393         case I40E_TUNNEL_TYPE_GTPC:
7394                 if (!pf->gtp_replace_flag) {
7395                         i40e_replace_gtp_l1_filter(pf);
7396                         i40e_replace_gtp_cloud_filter(pf);
7397                         pf->gtp_replace_flag = 1;
7398                 }
7399                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7400                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7401                         (teid_le >> 16) & 0xFFFF;
7402                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7403                         teid_le & 0xFFFF;
7404                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7405                         0x0;
7406                 big_buffer = 1;
7407                 break;
7408         case I40E_TUNNEL_TYPE_GTPU:
7409                 if (!pf->gtp_replace_flag) {
7410                         i40e_replace_gtp_l1_filter(pf);
7411                         i40e_replace_gtp_cloud_filter(pf);
7412                         pf->gtp_replace_flag = 1;
7413                 }
7414                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7415                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7416                         (teid_le >> 16) & 0xFFFF;
7417                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7418                         teid_le & 0xFFFF;
7419                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7420                         0x0;
7421                 big_buffer = 1;
7422                 break;
7423         case I40E_TUNNEL_TYPE_QINQ:
7424                 if (!pf->qinq_replace_flag) {
7425                         ret = i40e_cloud_filter_qinq_create(pf);
7426                         if (ret < 0)
7427                                 PMD_DRV_LOG(DEBUG,
7428                                             "QinQ tunnel filter already created.");
7429                         pf->qinq_replace_flag = 1;
7430                 }
7431                 /*      Add in the General fields the values of
7432                  *      the Outer and Inner VLAN
7433                  *      Big Buffer should be set, see changes in
7434                  *      i40e_aq_add_cloud_filters
7435                  */
7436                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7437                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7438                 big_buffer = 1;
7439                 break;
7440         default:
7441                 /* Other tunnel types is not supported. */
7442                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7443                 rte_free(cld_filter);
7444                 return -EINVAL;
7445         }
7446
7447         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7448                 pfilter->element.flags =
7449                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7450         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7451                 pfilter->element.flags =
7452                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7453         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7454                 pfilter->element.flags =
7455                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7456         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7457                 pfilter->element.flags =
7458                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7459         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7460                 pfilter->element.flags |=
7461                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7462         else {
7463                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7464                                                 &pfilter->element.flags);
7465                 if (val < 0) {
7466                         rte_free(cld_filter);
7467                         return -EINVAL;
7468                 }
7469         }
7470
7471         pfilter->element.flags |= rte_cpu_to_le_16(
7472                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7473                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7474         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7475         pfilter->element.queue_number =
7476                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7477
7478         if (!tunnel_filter->is_to_vf)
7479                 vsi = pf->main_vsi;
7480         else {
7481                 if (tunnel_filter->vf_id >= pf->vf_num) {
7482                         PMD_DRV_LOG(ERR, "Invalid argument.");
7483                         return -EINVAL;
7484                 }
7485                 vf = &pf->vfs[tunnel_filter->vf_id];
7486                 vsi = vf->vsi;
7487         }
7488
7489         /* Check if there is the filter in SW list */
7490         memset(&check_filter, 0, sizeof(check_filter));
7491         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7492         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7493         check_filter.vf_id = tunnel_filter->vf_id;
7494         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7495         if (add && node) {
7496                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7497                 return -EINVAL;
7498         }
7499
7500         if (!add && !node) {
7501                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7502                 return -EINVAL;
7503         }
7504
7505         if (add) {
7506                 if (big_buffer)
7507                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7508                                                    vsi->seid, cld_filter, 1);
7509                 else
7510                         ret = i40e_aq_add_cloud_filters(hw,
7511                                         vsi->seid, &cld_filter->element, 1);
7512                 if (ret < 0) {
7513                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7514                         return -ENOTSUP;
7515                 }
7516                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7517                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7518                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7519         } else {
7520                 if (big_buffer)
7521                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7522                                 hw, vsi->seid, cld_filter, 1);
7523                 else
7524                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7525                                                    &cld_filter->element, 1);
7526                 if (ret < 0) {
7527                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7528                         return -ENOTSUP;
7529                 }
7530                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7531         }
7532
7533         rte_free(cld_filter);
7534         return ret;
7535 }
7536
7537 static int
7538 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7539 {
7540         uint8_t i;
7541
7542         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7543                 if (pf->vxlan_ports[i] == port)
7544                         return i;
7545         }
7546
7547         return -1;
7548 }
7549
7550 static int
7551 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7552 {
7553         int  idx, ret;
7554         uint8_t filter_idx;
7555         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7556
7557         idx = i40e_get_vxlan_port_idx(pf, port);
7558
7559         /* Check if port already exists */
7560         if (idx >= 0) {
7561                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7562                 return -EINVAL;
7563         }
7564
7565         /* Now check if there is space to add the new port */
7566         idx = i40e_get_vxlan_port_idx(pf, 0);
7567         if (idx < 0) {
7568                 PMD_DRV_LOG(ERR,
7569                         "Maximum number of UDP ports reached, not adding port %d",
7570                         port);
7571                 return -ENOSPC;
7572         }
7573
7574         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7575                                         &filter_idx, NULL);
7576         if (ret < 0) {
7577                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7578                 return -1;
7579         }
7580
7581         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7582                          port,  filter_idx);
7583
7584         /* New port: add it and mark its index in the bitmap */
7585         pf->vxlan_ports[idx] = port;
7586         pf->vxlan_bitmap |= (1 << idx);
7587
7588         if (!(pf->flags & I40E_FLAG_VXLAN))
7589                 pf->flags |= I40E_FLAG_VXLAN;
7590
7591         return 0;
7592 }
7593
7594 static int
7595 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7596 {
7597         int idx;
7598         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7599
7600         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7601                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7602                 return -EINVAL;
7603         }
7604
7605         idx = i40e_get_vxlan_port_idx(pf, port);
7606
7607         if (idx < 0) {
7608                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7609                 return -EINVAL;
7610         }
7611
7612         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7613                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7614                 return -1;
7615         }
7616
7617         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7618                         port, idx);
7619
7620         pf->vxlan_ports[idx] = 0;
7621         pf->vxlan_bitmap &= ~(1 << idx);
7622
7623         if (!pf->vxlan_bitmap)
7624                 pf->flags &= ~I40E_FLAG_VXLAN;
7625
7626         return 0;
7627 }
7628
7629 /* Add UDP tunneling port */
7630 static int
7631 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7632                              struct rte_eth_udp_tunnel *udp_tunnel)
7633 {
7634         int ret = 0;
7635         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7636
7637         if (udp_tunnel == NULL)
7638                 return -EINVAL;
7639
7640         switch (udp_tunnel->prot_type) {
7641         case RTE_TUNNEL_TYPE_VXLAN:
7642                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7643                 break;
7644
7645         case RTE_TUNNEL_TYPE_GENEVE:
7646         case RTE_TUNNEL_TYPE_TEREDO:
7647                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7648                 ret = -1;
7649                 break;
7650
7651         default:
7652                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7653                 ret = -1;
7654                 break;
7655         }
7656
7657         return ret;
7658 }
7659
7660 /* Remove UDP tunneling port */
7661 static int
7662 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7663                              struct rte_eth_udp_tunnel *udp_tunnel)
7664 {
7665         int ret = 0;
7666         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7667
7668         if (udp_tunnel == NULL)
7669                 return -EINVAL;
7670
7671         switch (udp_tunnel->prot_type) {
7672         case RTE_TUNNEL_TYPE_VXLAN:
7673                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7674                 break;
7675         case RTE_TUNNEL_TYPE_GENEVE:
7676         case RTE_TUNNEL_TYPE_TEREDO:
7677                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7678                 ret = -1;
7679                 break;
7680         default:
7681                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7682                 ret = -1;
7683                 break;
7684         }
7685
7686         return ret;
7687 }
7688
7689 /* Calculate the maximum number of contiguous PF queues that are configured */
7690 static int
7691 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7692 {
7693         struct rte_eth_dev_data *data = pf->dev_data;
7694         int i, num;
7695         struct i40e_rx_queue *rxq;
7696
7697         num = 0;
7698         for (i = 0; i < pf->lan_nb_qps; i++) {
7699                 rxq = data->rx_queues[i];
7700                 if (rxq && rxq->q_set)
7701                         num++;
7702                 else
7703                         break;
7704         }
7705
7706         return num;
7707 }
7708
7709 /* Configure RSS */
7710 static int
7711 i40e_pf_config_rss(struct i40e_pf *pf)
7712 {
7713         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7714         struct rte_eth_rss_conf rss_conf;
7715         uint32_t i, lut = 0;
7716         uint16_t j, num;
7717
7718         /*
7719          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7720          * It's necessary to calculate the actual PF queues that are configured.
7721          */
7722         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7723                 num = i40e_pf_calc_configured_queues_num(pf);
7724         else
7725                 num = pf->dev_data->nb_rx_queues;
7726
7727         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7728         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7729                         num);
7730
7731         if (num == 0) {
7732                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7733                 return -ENOTSUP;
7734         }
7735
7736         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7737                 if (j == num)
7738                         j = 0;
7739                 lut = (lut << 8) | (j & ((0x1 <<
7740                         hw->func_caps.rss_table_entry_width) - 1));
7741                 if ((i & 3) == 3)
7742                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7743         }
7744
7745         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7746         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7747                 i40e_pf_disable_rss(pf);
7748                 return 0;
7749         }
7750         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7751                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7752                 /* Random default keys */
7753                 static uint32_t rss_key_default[] = {0x6b793944,
7754                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7755                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7756                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7757
7758                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7759                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7760                                                         sizeof(uint32_t);
7761         }
7762
7763         return i40e_hw_rss_hash_set(pf, &rss_conf);
7764 }
7765
7766 static int
7767 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7768                                struct rte_eth_tunnel_filter_conf *filter)
7769 {
7770         if (pf == NULL || filter == NULL) {
7771                 PMD_DRV_LOG(ERR, "Invalid parameter");
7772                 return -EINVAL;
7773         }
7774
7775         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7776                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7777                 return -EINVAL;
7778         }
7779
7780         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7781                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7782                 return -EINVAL;
7783         }
7784
7785         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7786                 (is_zero_ether_addr(&filter->outer_mac))) {
7787                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7788                 return -EINVAL;
7789         }
7790
7791         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7792                 (is_zero_ether_addr(&filter->inner_mac))) {
7793                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7794                 return -EINVAL;
7795         }
7796
7797         return 0;
7798 }
7799
7800 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7801 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7802 static int
7803 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7804 {
7805         uint32_t val, reg;
7806         int ret = -EINVAL;
7807
7808         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7809         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7810
7811         if (len == 3) {
7812                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7813         } else if (len == 4) {
7814                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7815         } else {
7816                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7817                 return ret;
7818         }
7819
7820         if (reg != val) {
7821                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7822                                                    reg, NULL);
7823                 if (ret != 0)
7824                         return ret;
7825         } else {
7826                 ret = 0;
7827         }
7828         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7829                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7830
7831         return ret;
7832 }
7833
7834 static int
7835 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7836 {
7837         int ret = -EINVAL;
7838
7839         if (!hw || !cfg)
7840                 return -EINVAL;
7841
7842         switch (cfg->cfg_type) {
7843         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7844                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7845                 break;
7846         default:
7847                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7848                 break;
7849         }
7850
7851         return ret;
7852 }
7853
7854 static int
7855 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7856                                enum rte_filter_op filter_op,
7857                                void *arg)
7858 {
7859         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7860         int ret = I40E_ERR_PARAM;
7861
7862         switch (filter_op) {
7863         case RTE_ETH_FILTER_SET:
7864                 ret = i40e_dev_global_config_set(hw,
7865                         (struct rte_eth_global_cfg *)arg);
7866                 break;
7867         default:
7868                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7869                 break;
7870         }
7871
7872         return ret;
7873 }
7874
7875 static int
7876 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7877                           enum rte_filter_op filter_op,
7878                           void *arg)
7879 {
7880         struct rte_eth_tunnel_filter_conf *filter;
7881         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7882         int ret = I40E_SUCCESS;
7883
7884         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7885
7886         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7887                 return I40E_ERR_PARAM;
7888
7889         switch (filter_op) {
7890         case RTE_ETH_FILTER_NOP:
7891                 if (!(pf->flags & I40E_FLAG_VXLAN))
7892                         ret = I40E_NOT_SUPPORTED;
7893                 break;
7894         case RTE_ETH_FILTER_ADD:
7895                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7896                 break;
7897         case RTE_ETH_FILTER_DELETE:
7898                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7899                 break;
7900         default:
7901                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7902                 ret = I40E_ERR_PARAM;
7903                 break;
7904         }
7905
7906         return ret;
7907 }
7908
7909 static int
7910 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7911 {
7912         int ret = 0;
7913         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7914
7915         /* RSS setup */
7916         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7917                 ret = i40e_pf_config_rss(pf);
7918         else
7919                 i40e_pf_disable_rss(pf);
7920
7921         return ret;
7922 }
7923
7924 /* Get the symmetric hash enable configurations per port */
7925 static void
7926 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7927 {
7928         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7929
7930         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7931 }
7932
7933 /* Set the symmetric hash enable configurations per port */
7934 static void
7935 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7936 {
7937         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7938
7939         if (enable > 0) {
7940                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7941                         PMD_DRV_LOG(INFO,
7942                                 "Symmetric hash has already been enabled");
7943                         return;
7944                 }
7945                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7946         } else {
7947                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7948                         PMD_DRV_LOG(INFO,
7949                                 "Symmetric hash has already been disabled");
7950                         return;
7951                 }
7952                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7953         }
7954         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7955         I40E_WRITE_FLUSH(hw);
7956 }
7957
7958 /*
7959  * Get global configurations of hash function type and symmetric hash enable
7960  * per flow type (pctype). Note that global configuration means it affects all
7961  * the ports on the same NIC.
7962  */
7963 static int
7964 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7965                                    struct rte_eth_hash_global_conf *g_cfg)
7966 {
7967         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
7968         uint32_t reg;
7969         uint16_t i, j;
7970
7971         memset(g_cfg, 0, sizeof(*g_cfg));
7972         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7973         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7974                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7975         else
7976                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7977         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7978                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7979
7980         /*
7981          * We work only with lowest 32 bits which is not correct, but to work
7982          * properly the valid_bit_mask size should be increased up to 64 bits
7983          * and this will brake ABI. This modification will be done in next
7984          * release
7985          */
7986         g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
7987
7988         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
7989                 if (!adapter->pctypes_tbl[i])
7990                         continue;
7991                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
7992                      j < I40E_FILTER_PCTYPE_MAX; j++) {
7993                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
7994                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
7995                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
7996                                         g_cfg->sym_hash_enable_mask[0] |=
7997                                                                 (1UL << i);
7998                                 }
7999                         }
8000                 }
8001         }
8002
8003         return 0;
8004 }
8005
8006 static int
8007 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8008                               const struct rte_eth_hash_global_conf *g_cfg)
8009 {
8010         uint32_t i;
8011         uint32_t mask0, i40e_mask = adapter->flow_types_mask;
8012
8013         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8014                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8015                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8016                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8017                                                 g_cfg->hash_func);
8018                 return -EINVAL;
8019         }
8020
8021         /*
8022          * As i40e supports less than 32 flow types, only first 32 bits need to
8023          * be checked.
8024          */
8025         mask0 = g_cfg->valid_bit_mask[0];
8026         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8027                 if (i == 0) {
8028                         /* Check if any unsupported flow type configured */
8029                         if ((mask0 | i40e_mask) ^ i40e_mask)
8030                                 goto mask_err;
8031                 } else {
8032                         if (g_cfg->valid_bit_mask[i])
8033                                 goto mask_err;
8034                 }
8035         }
8036
8037         return 0;
8038
8039 mask_err:
8040         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8041
8042         return -EINVAL;
8043 }
8044
8045 /*
8046  * Set global configurations of hash function type and symmetric hash enable
8047  * per flow type (pctype). Note any modifying global configuration will affect
8048  * all the ports on the same NIC.
8049  */
8050 static int
8051 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8052                                    struct rte_eth_hash_global_conf *g_cfg)
8053 {
8054         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8055         int ret;
8056         uint16_t i, j;
8057         uint32_t reg;
8058         /*
8059          * We work only with lowest 32 bits which is not correct, but to work
8060          * properly the valid_bit_mask size should be increased up to 64 bits
8061          * and this will brake ABI. This modification will be done in next
8062          * release
8063          */
8064         uint32_t mask0 = g_cfg->valid_bit_mask[0] &
8065                                         (uint32_t)adapter->flow_types_mask;
8066
8067         /* Check the input parameters */
8068         ret = i40e_hash_global_config_check(adapter, g_cfg);
8069         if (ret < 0)
8070                 return ret;
8071
8072         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
8073                 if (mask0 & (1UL << i)) {
8074                         reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
8075                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8076
8077                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8078                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8079                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8080                                         i40e_write_rx_ctl(hw,
8081                                                           I40E_GLQF_HSYM(j),
8082                                                           reg);
8083                         }
8084                 }
8085         }
8086
8087         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8088         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8089                 /* Toeplitz */
8090                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8091                         PMD_DRV_LOG(DEBUG,
8092                                 "Hash function already set to Toeplitz");
8093                         goto out;
8094                 }
8095                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8096         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8097                 /* Simple XOR */
8098                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8099                         PMD_DRV_LOG(DEBUG,
8100                                 "Hash function already set to Simple XOR");
8101                         goto out;
8102                 }
8103                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8104         } else
8105                 /* Use the default, and keep it as it is */
8106                 goto out;
8107
8108         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8109
8110 out:
8111         I40E_WRITE_FLUSH(hw);
8112
8113         return 0;
8114 }
8115
8116 /**
8117  * Valid input sets for hash and flow director filters per PCTYPE
8118  */
8119 static uint64_t
8120 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8121                 enum rte_filter_type filter)
8122 {
8123         uint64_t valid;
8124
8125         static const uint64_t valid_hash_inset_table[] = {
8126                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8127                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8128                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8129                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8130                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8131                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8132                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8133                         I40E_INSET_FLEX_PAYLOAD,
8134                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8135                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8136                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8137                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8138                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8139                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8140                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8141                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8142                         I40E_INSET_FLEX_PAYLOAD,
8143                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8144                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8145                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8146                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8147                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8148                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8149                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8150                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8151                         I40E_INSET_FLEX_PAYLOAD,
8152                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8153                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8154                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8155                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8156                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8157                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8158                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8159                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8160                         I40E_INSET_FLEX_PAYLOAD,
8161                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8162                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8163                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8164                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8165                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8166                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8167                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8168                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8169                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8170                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8171                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8172                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8173                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8174                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8175                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8176                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8177                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8178                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8179                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8180                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8181                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8182                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8183                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8184                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8185                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8186                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8187                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8188                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8189                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8190                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8191                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8192                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8193                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8194                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8195                         I40E_INSET_FLEX_PAYLOAD,
8196                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8197                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8198                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8199                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8200                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8201                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8202                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8203                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8204                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8205                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8206                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8207                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8208                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8209                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8210                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8211                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8212                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8213                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8214                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8215                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8216                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8217                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8218                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8219                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8220                         I40E_INSET_FLEX_PAYLOAD,
8221                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8222                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8223                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8224                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8225                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8226                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8227                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8228                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8229                         I40E_INSET_FLEX_PAYLOAD,
8230                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8231                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8232                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8233                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8234                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8235                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8236                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8237                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8238                         I40E_INSET_FLEX_PAYLOAD,
8239                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8240                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8241                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8242                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8243                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8244                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8245                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8246                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8247                         I40E_INSET_FLEX_PAYLOAD,
8248                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8249                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8250                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8251                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8252                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8253                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8254                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8255                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8256                         I40E_INSET_FLEX_PAYLOAD,
8257                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8258                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8259                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8260                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8261                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8262                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8263                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8264                         I40E_INSET_FLEX_PAYLOAD,
8265                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8266                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8267                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8268                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8269                         I40E_INSET_FLEX_PAYLOAD,
8270         };
8271
8272         /**
8273          * Flow director supports only fields defined in
8274          * union rte_eth_fdir_flow.
8275          */
8276         static const uint64_t valid_fdir_inset_table[] = {
8277                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8278                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8279                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8280                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8281                 I40E_INSET_IPV4_TTL,
8282                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8283                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8284                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8285                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8286                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8287                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8288                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8289                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8290                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8291                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8292                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8293                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8294                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8295                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8296                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8297                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8298                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8299                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8300                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8301                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8302                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8303                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8304                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8305                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8306                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8307                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8308                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8309                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8310                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8311                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8312                 I40E_INSET_SCTP_VT,
8313                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8314                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8315                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8316                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8317                 I40E_INSET_IPV4_TTL,
8318                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8319                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8320                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8321                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8322                 I40E_INSET_IPV6_HOP_LIMIT,
8323                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8324                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8325                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8326                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8327                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8328                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8329                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8330                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8331                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8332                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8333                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8334                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8335                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8336                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8337                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8338                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8339                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8340                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8341                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8342                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8343                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8344                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8345                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8346                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8347                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8348                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8349                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8350                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8351                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8352                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8353                 I40E_INSET_SCTP_VT,
8354                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8355                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8356                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8357                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8358                 I40E_INSET_IPV6_HOP_LIMIT,
8359                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8360                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8361                 I40E_INSET_LAST_ETHER_TYPE,
8362         };
8363
8364         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8365                 return 0;
8366         if (filter == RTE_ETH_FILTER_HASH)
8367                 valid = valid_hash_inset_table[pctype];
8368         else
8369                 valid = valid_fdir_inset_table[pctype];
8370
8371         return valid;
8372 }
8373
8374 /**
8375  * Validate if the input set is allowed for a specific PCTYPE
8376  */
8377 int
8378 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8379                 enum rte_filter_type filter, uint64_t inset)
8380 {
8381         uint64_t valid;
8382
8383         valid = i40e_get_valid_input_set(pctype, filter);
8384         if (inset & (~valid))
8385                 return -EINVAL;
8386
8387         return 0;
8388 }
8389
8390 /* default input set fields combination per pctype */
8391 uint64_t
8392 i40e_get_default_input_set(uint16_t pctype)
8393 {
8394         static const uint64_t default_inset_table[] = {
8395                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8396                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8397                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8398                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8399                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8400                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8401                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8402                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8403                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8404                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8405                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8406                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8407                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8408                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8409                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8410                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8411                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8412                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8413                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8414                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8415                         I40E_INSET_SCTP_VT,
8416                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8417                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8418                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8419                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8420                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8421                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8422                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8423                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8424                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8425                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8426                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8427                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8428                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8429                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8430                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8431                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8432                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8433                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8434                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8435                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8436                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8437                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8438                         I40E_INSET_SCTP_VT,
8439                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8440                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8441                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8442                         I40E_INSET_LAST_ETHER_TYPE,
8443         };
8444
8445         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8446                 return 0;
8447
8448         return default_inset_table[pctype];
8449 }
8450
8451 /**
8452  * Parse the input set from index to logical bit masks
8453  */
8454 static int
8455 i40e_parse_input_set(uint64_t *inset,
8456                      enum i40e_filter_pctype pctype,
8457                      enum rte_eth_input_set_field *field,
8458                      uint16_t size)
8459 {
8460         uint16_t i, j;
8461         int ret = -EINVAL;
8462
8463         static const struct {
8464                 enum rte_eth_input_set_field field;
8465                 uint64_t inset;
8466         } inset_convert_table[] = {
8467                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8468                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8469                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8470                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8471                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8472                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8473                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8474                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8475                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8476                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8477                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8478                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8479                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8480                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8481                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8482                         I40E_INSET_IPV6_NEXT_HDR},
8483                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8484                         I40E_INSET_IPV6_HOP_LIMIT},
8485                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8486                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8487                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8488                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8489                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8490                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8491                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8492                         I40E_INSET_SCTP_VT},
8493                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8494                         I40E_INSET_TUNNEL_DMAC},
8495                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8496                         I40E_INSET_VLAN_TUNNEL},
8497                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8498                         I40E_INSET_TUNNEL_ID},
8499                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8500                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8501                         I40E_INSET_FLEX_PAYLOAD_W1},
8502                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8503                         I40E_INSET_FLEX_PAYLOAD_W2},
8504                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8505                         I40E_INSET_FLEX_PAYLOAD_W3},
8506                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8507                         I40E_INSET_FLEX_PAYLOAD_W4},
8508                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8509                         I40E_INSET_FLEX_PAYLOAD_W5},
8510                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8511                         I40E_INSET_FLEX_PAYLOAD_W6},
8512                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8513                         I40E_INSET_FLEX_PAYLOAD_W7},
8514                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8515                         I40E_INSET_FLEX_PAYLOAD_W8},
8516         };
8517
8518         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8519                 return ret;
8520
8521         /* Only one item allowed for default or all */
8522         if (size == 1) {
8523                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8524                         *inset = i40e_get_default_input_set(pctype);
8525                         return 0;
8526                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8527                         *inset = I40E_INSET_NONE;
8528                         return 0;
8529                 }
8530         }
8531
8532         for (i = 0, *inset = 0; i < size; i++) {
8533                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8534                         if (field[i] == inset_convert_table[j].field) {
8535                                 *inset |= inset_convert_table[j].inset;
8536                                 break;
8537                         }
8538                 }
8539
8540                 /* It contains unsupported input set, return immediately */
8541                 if (j == RTE_DIM(inset_convert_table))
8542                         return ret;
8543         }
8544
8545         return 0;
8546 }
8547
8548 /**
8549  * Translate the input set from bit masks to register aware bit masks
8550  * and vice versa
8551  */
8552 uint64_t
8553 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8554 {
8555         uint64_t val = 0;
8556         uint16_t i;
8557
8558         struct inset_map {
8559                 uint64_t inset;
8560                 uint64_t inset_reg;
8561         };
8562
8563         static const struct inset_map inset_map_common[] = {
8564                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8565                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8566                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8567                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8568                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8569                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8570                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8571                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8572                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8573                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8574                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8575                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8576                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8577                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8578                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8579                 {I40E_INSET_TUNNEL_DMAC,
8580                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8581                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8582                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8583                 {I40E_INSET_TUNNEL_SRC_PORT,
8584                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8585                 {I40E_INSET_TUNNEL_DST_PORT,
8586                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8587                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8588                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8589                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8590                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8591                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8592                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8593                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8594                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8595                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8596         };
8597
8598     /* some different registers map in x722*/
8599         static const struct inset_map inset_map_diff_x722[] = {
8600                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8601                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8602                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8603                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8604         };
8605
8606         static const struct inset_map inset_map_diff_not_x722[] = {
8607                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8608                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8609                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8610                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8611         };
8612
8613         if (input == 0)
8614                 return val;
8615
8616         /* Translate input set to register aware inset */
8617         if (type == I40E_MAC_X722) {
8618                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8619                         if (input & inset_map_diff_x722[i].inset)
8620                                 val |= inset_map_diff_x722[i].inset_reg;
8621                 }
8622         } else {
8623                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8624                         if (input & inset_map_diff_not_x722[i].inset)
8625                                 val |= inset_map_diff_not_x722[i].inset_reg;
8626                 }
8627         }
8628
8629         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8630                 if (input & inset_map_common[i].inset)
8631                         val |= inset_map_common[i].inset_reg;
8632         }
8633
8634         return val;
8635 }
8636
8637 int
8638 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8639 {
8640         uint8_t i, idx = 0;
8641         uint64_t inset_need_mask = inset;
8642
8643         static const struct {
8644                 uint64_t inset;
8645                 uint32_t mask;
8646         } inset_mask_map[] = {
8647                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8648                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8649                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8650                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8651                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8652                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8653                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8654                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8655         };
8656
8657         if (!inset || !mask || !nb_elem)
8658                 return 0;
8659
8660         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8661                 /* Clear the inset bit, if no MASK is required,
8662                  * for example proto + ttl
8663                  */
8664                 if ((inset & inset_mask_map[i].inset) ==
8665                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8666                         inset_need_mask &= ~inset_mask_map[i].inset;
8667                 if (!inset_need_mask)
8668                         return 0;
8669         }
8670         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8671                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8672                     inset_mask_map[i].inset) {
8673                         if (idx >= nb_elem) {
8674                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8675                                 return -EINVAL;
8676                         }
8677                         mask[idx] = inset_mask_map[i].mask;
8678                         idx++;
8679                 }
8680         }
8681
8682         return idx;
8683 }
8684
8685 void
8686 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8687 {
8688         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8689
8690         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8691         if (reg != val)
8692                 i40e_write_rx_ctl(hw, addr, val);
8693         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8694                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8695 }
8696
8697 static void
8698 i40e_filter_input_set_init(struct i40e_pf *pf)
8699 {
8700         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8701         enum i40e_filter_pctype pctype;
8702         uint64_t input_set, inset_reg;
8703         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8704         int num, i;
8705         uint16_t flow_type;
8706
8707         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8708              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8709                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8710
8711                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8712                         continue;
8713
8714                 input_set = i40e_get_default_input_set(pctype);
8715
8716                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8717                                                    I40E_INSET_MASK_NUM_REG);
8718                 if (num < 0)
8719                         return;
8720                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8721                                         input_set);
8722
8723                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8724                                       (uint32_t)(inset_reg & UINT32_MAX));
8725                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8726                                      (uint32_t)((inset_reg >>
8727                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8728                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8729                                       (uint32_t)(inset_reg & UINT32_MAX));
8730                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8731                                      (uint32_t)((inset_reg >>
8732                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8733
8734                 for (i = 0; i < num; i++) {
8735                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8736                                              mask_reg[i]);
8737                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8738                                              mask_reg[i]);
8739                 }
8740                 /*clear unused mask registers of the pctype */
8741                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8742                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8743                                              0);
8744                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8745                                              0);
8746                 }
8747                 I40E_WRITE_FLUSH(hw);
8748
8749                 /* store the default input set */
8750                 pf->hash_input_set[pctype] = input_set;
8751                 pf->fdir.input_set[pctype] = input_set;
8752         }
8753 }
8754
8755 int
8756 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8757                          struct rte_eth_input_set_conf *conf)
8758 {
8759         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8760         enum i40e_filter_pctype pctype;
8761         uint64_t input_set, inset_reg = 0;
8762         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8763         int ret, i, num;
8764
8765         if (!conf) {
8766                 PMD_DRV_LOG(ERR, "Invalid pointer");
8767                 return -EFAULT;
8768         }
8769         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8770             conf->op != RTE_ETH_INPUT_SET_ADD) {
8771                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8772                 return -EINVAL;
8773         }
8774
8775         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8776         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8777                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8778                 return -EINVAL;
8779         }
8780
8781         if (hw->mac.type == I40E_MAC_X722) {
8782                 /* get translated pctype value in fd pctype register */
8783                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8784                         I40E_GLQF_FD_PCTYPES((int)pctype));
8785         }
8786
8787         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8788                                    conf->inset_size);
8789         if (ret) {
8790                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8791                 return -EINVAL;
8792         }
8793
8794         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8795                 /* get inset value in register */
8796                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8797                 inset_reg <<= I40E_32_BIT_WIDTH;
8798                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8799                 input_set |= pf->hash_input_set[pctype];
8800         }
8801         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8802                                            I40E_INSET_MASK_NUM_REG);
8803         if (num < 0)
8804                 return -EINVAL;
8805
8806         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8807
8808         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8809                               (uint32_t)(inset_reg & UINT32_MAX));
8810         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8811                              (uint32_t)((inset_reg >>
8812                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8813
8814         for (i = 0; i < num; i++)
8815                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8816                                      mask_reg[i]);
8817         /*clear unused mask registers of the pctype */
8818         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8819                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8820                                      0);
8821         I40E_WRITE_FLUSH(hw);
8822
8823         pf->hash_input_set[pctype] = input_set;
8824         return 0;
8825 }
8826
8827 int
8828 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8829                          struct rte_eth_input_set_conf *conf)
8830 {
8831         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8832         enum i40e_filter_pctype pctype;
8833         uint64_t input_set, inset_reg = 0;
8834         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8835         int ret, i, num;
8836
8837         if (!hw || !conf) {
8838                 PMD_DRV_LOG(ERR, "Invalid pointer");
8839                 return -EFAULT;
8840         }
8841         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8842             conf->op != RTE_ETH_INPUT_SET_ADD) {
8843                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8844                 return -EINVAL;
8845         }
8846
8847         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8848
8849         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8850                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8851                 return -EINVAL;
8852         }
8853
8854         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8855                                    conf->inset_size);
8856         if (ret) {
8857                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8858                 return -EINVAL;
8859         }
8860
8861         /* get inset value in register */
8862         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8863         inset_reg <<= I40E_32_BIT_WIDTH;
8864         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8865
8866         /* Can not change the inset reg for flex payload for fdir,
8867          * it is done by writing I40E_PRTQF_FD_FLXINSET
8868          * in i40e_set_flex_mask_on_pctype.
8869          */
8870         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8871                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8872         else
8873                 input_set |= pf->fdir.input_set[pctype];
8874         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8875                                            I40E_INSET_MASK_NUM_REG);
8876         if (num < 0)
8877                 return -EINVAL;
8878
8879         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8880
8881         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8882                               (uint32_t)(inset_reg & UINT32_MAX));
8883         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8884                              (uint32_t)((inset_reg >>
8885                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8886
8887         for (i = 0; i < num; i++)
8888                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8889                                      mask_reg[i]);
8890         /*clear unused mask registers of the pctype */
8891         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8892                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8893                                      0);
8894         I40E_WRITE_FLUSH(hw);
8895
8896         pf->fdir.input_set[pctype] = input_set;
8897         return 0;
8898 }
8899
8900 static int
8901 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8902 {
8903         int ret = 0;
8904
8905         if (!hw || !info) {
8906                 PMD_DRV_LOG(ERR, "Invalid pointer");
8907                 return -EFAULT;
8908         }
8909
8910         switch (info->info_type) {
8911         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8912                 i40e_get_symmetric_hash_enable_per_port(hw,
8913                                         &(info->info.enable));
8914                 break;
8915         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8916                 ret = i40e_get_hash_filter_global_config(hw,
8917                                 &(info->info.global_conf));
8918                 break;
8919         default:
8920                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8921                                                         info->info_type);
8922                 ret = -EINVAL;
8923                 break;
8924         }
8925
8926         return ret;
8927 }
8928
8929 static int
8930 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8931 {
8932         int ret = 0;
8933
8934         if (!hw || !info) {
8935                 PMD_DRV_LOG(ERR, "Invalid pointer");
8936                 return -EFAULT;
8937         }
8938
8939         switch (info->info_type) {
8940         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8941                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8942                 break;
8943         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8944                 ret = i40e_set_hash_filter_global_config(hw,
8945                                 &(info->info.global_conf));
8946                 break;
8947         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8948                 ret = i40e_hash_filter_inset_select(hw,
8949                                                &(info->info.input_set_conf));
8950                 break;
8951
8952         default:
8953                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8954                                                         info->info_type);
8955                 ret = -EINVAL;
8956                 break;
8957         }
8958
8959         return ret;
8960 }
8961
8962 /* Operations for hash function */
8963 static int
8964 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8965                       enum rte_filter_op filter_op,
8966                       void *arg)
8967 {
8968         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8969         int ret = 0;
8970
8971         switch (filter_op) {
8972         case RTE_ETH_FILTER_NOP:
8973                 break;
8974         case RTE_ETH_FILTER_GET:
8975                 ret = i40e_hash_filter_get(hw,
8976                         (struct rte_eth_hash_filter_info *)arg);
8977                 break;
8978         case RTE_ETH_FILTER_SET:
8979                 ret = i40e_hash_filter_set(hw,
8980                         (struct rte_eth_hash_filter_info *)arg);
8981                 break;
8982         default:
8983                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8984                                                                 filter_op);
8985                 ret = -ENOTSUP;
8986                 break;
8987         }
8988
8989         return ret;
8990 }
8991
8992 /* Convert ethertype filter structure */
8993 static int
8994 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8995                               struct i40e_ethertype_filter *filter)
8996 {
8997         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8998         filter->input.ether_type = input->ether_type;
8999         filter->flags = input->flags;
9000         filter->queue = input->queue;
9001
9002         return 0;
9003 }
9004
9005 /* Check if there exists the ehtertype filter */
9006 struct i40e_ethertype_filter *
9007 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9008                                 const struct i40e_ethertype_filter_input *input)
9009 {
9010         int ret;
9011
9012         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9013         if (ret < 0)
9014                 return NULL;
9015
9016         return ethertype_rule->hash_map[ret];
9017 }
9018
9019 /* Add ethertype filter in SW list */
9020 static int
9021 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9022                                 struct i40e_ethertype_filter *filter)
9023 {
9024         struct i40e_ethertype_rule *rule = &pf->ethertype;
9025         int ret;
9026
9027         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9028         if (ret < 0) {
9029                 PMD_DRV_LOG(ERR,
9030                             "Failed to insert ethertype filter"
9031                             " to hash table %d!",
9032                             ret);
9033                 return ret;
9034         }
9035         rule->hash_map[ret] = filter;
9036
9037         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9038
9039         return 0;
9040 }
9041
9042 /* Delete ethertype filter in SW list */
9043 int
9044 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9045                              struct i40e_ethertype_filter_input *input)
9046 {
9047         struct i40e_ethertype_rule *rule = &pf->ethertype;
9048         struct i40e_ethertype_filter *filter;
9049         int ret;
9050
9051         ret = rte_hash_del_key(rule->hash_table, input);
9052         if (ret < 0) {
9053                 PMD_DRV_LOG(ERR,
9054                             "Failed to delete ethertype filter"
9055                             " to hash table %d!",
9056                             ret);
9057                 return ret;
9058         }
9059         filter = rule->hash_map[ret];
9060         rule->hash_map[ret] = NULL;
9061
9062         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9063         rte_free(filter);
9064
9065         return 0;
9066 }
9067
9068 /*
9069  * Configure ethertype filter, which can director packet by filtering
9070  * with mac address and ether_type or only ether_type
9071  */
9072 int
9073 i40e_ethertype_filter_set(struct i40e_pf *pf,
9074                         struct rte_eth_ethertype_filter *filter,
9075                         bool add)
9076 {
9077         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9078         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9079         struct i40e_ethertype_filter *ethertype_filter, *node;
9080         struct i40e_ethertype_filter check_filter;
9081         struct i40e_control_filter_stats stats;
9082         uint16_t flags = 0;
9083         int ret;
9084
9085         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9086                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9087                 return -EINVAL;
9088         }
9089         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9090                 filter->ether_type == ETHER_TYPE_IPv6) {
9091                 PMD_DRV_LOG(ERR,
9092                         "unsupported ether_type(0x%04x) in control packet filter.",
9093                         filter->ether_type);
9094                 return -EINVAL;
9095         }
9096         if (filter->ether_type == ETHER_TYPE_VLAN)
9097                 PMD_DRV_LOG(WARNING,
9098                         "filter vlan ether_type in first tag is not supported.");
9099
9100         /* Check if there is the filter in SW list */
9101         memset(&check_filter, 0, sizeof(check_filter));
9102         i40e_ethertype_filter_convert(filter, &check_filter);
9103         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9104                                                &check_filter.input);
9105         if (add && node) {
9106                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9107                 return -EINVAL;
9108         }
9109
9110         if (!add && !node) {
9111                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9112                 return -EINVAL;
9113         }
9114
9115         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9116                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9117         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9118                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9119         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9120
9121         memset(&stats, 0, sizeof(stats));
9122         ret = i40e_aq_add_rem_control_packet_filter(hw,
9123                         filter->mac_addr.addr_bytes,
9124                         filter->ether_type, flags,
9125                         pf->main_vsi->seid,
9126                         filter->queue, add, &stats, NULL);
9127
9128         PMD_DRV_LOG(INFO,
9129                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9130                 ret, stats.mac_etype_used, stats.etype_used,
9131                 stats.mac_etype_free, stats.etype_free);
9132         if (ret < 0)
9133                 return -ENOSYS;
9134
9135         /* Add or delete a filter in SW list */
9136         if (add) {
9137                 ethertype_filter = rte_zmalloc("ethertype_filter",
9138                                        sizeof(*ethertype_filter), 0);
9139                 rte_memcpy(ethertype_filter, &check_filter,
9140                            sizeof(check_filter));
9141                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9142         } else {
9143                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9144         }
9145
9146         return ret;
9147 }
9148
9149 /*
9150  * Handle operations for ethertype filter.
9151  */
9152 static int
9153 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9154                                 enum rte_filter_op filter_op,
9155                                 void *arg)
9156 {
9157         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9158         int ret = 0;
9159
9160         if (filter_op == RTE_ETH_FILTER_NOP)
9161                 return ret;
9162
9163         if (arg == NULL) {
9164                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9165                             filter_op);
9166                 return -EINVAL;
9167         }
9168
9169         switch (filter_op) {
9170         case RTE_ETH_FILTER_ADD:
9171                 ret = i40e_ethertype_filter_set(pf,
9172                         (struct rte_eth_ethertype_filter *)arg,
9173                         TRUE);
9174                 break;
9175         case RTE_ETH_FILTER_DELETE:
9176                 ret = i40e_ethertype_filter_set(pf,
9177                         (struct rte_eth_ethertype_filter *)arg,
9178                         FALSE);
9179                 break;
9180         default:
9181                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9182                 ret = -ENOSYS;
9183                 break;
9184         }
9185         return ret;
9186 }
9187
9188 static int
9189 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9190                      enum rte_filter_type filter_type,
9191                      enum rte_filter_op filter_op,
9192                      void *arg)
9193 {
9194         int ret = 0;
9195
9196         if (dev == NULL)
9197                 return -EINVAL;
9198
9199         switch (filter_type) {
9200         case RTE_ETH_FILTER_NONE:
9201                 /* For global configuration */
9202                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9203                 break;
9204         case RTE_ETH_FILTER_HASH:
9205                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9206                 break;
9207         case RTE_ETH_FILTER_MACVLAN:
9208                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9209                 break;
9210         case RTE_ETH_FILTER_ETHERTYPE:
9211                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9212                 break;
9213         case RTE_ETH_FILTER_TUNNEL:
9214                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9215                 break;
9216         case RTE_ETH_FILTER_FDIR:
9217                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9218                 break;
9219         case RTE_ETH_FILTER_GENERIC:
9220                 if (filter_op != RTE_ETH_FILTER_GET)
9221                         return -EINVAL;
9222                 *(const void **)arg = &i40e_flow_ops;
9223                 break;
9224         default:
9225                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9226                                                         filter_type);
9227                 ret = -EINVAL;
9228                 break;
9229         }
9230
9231         return ret;
9232 }
9233
9234 /*
9235  * Check and enable Extended Tag.
9236  * Enabling Extended Tag is important for 40G performance.
9237  */
9238 static void
9239 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9240 {
9241         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9242         uint32_t buf = 0;
9243         int ret;
9244
9245         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9246                                       PCI_DEV_CAP_REG);
9247         if (ret < 0) {
9248                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9249                             PCI_DEV_CAP_REG);
9250                 return;
9251         }
9252         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9253                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9254                 return;
9255         }
9256
9257         buf = 0;
9258         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9259                                       PCI_DEV_CTRL_REG);
9260         if (ret < 0) {
9261                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9262                             PCI_DEV_CTRL_REG);
9263                 return;
9264         }
9265         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9266                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9267                 return;
9268         }
9269         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9270         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9271                                        PCI_DEV_CTRL_REG);
9272         if (ret < 0) {
9273                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9274                             PCI_DEV_CTRL_REG);
9275                 return;
9276         }
9277 }
9278
9279 /*
9280  * As some registers wouldn't be reset unless a global hardware reset,
9281  * hardware initialization is needed to put those registers into an
9282  * expected initial state.
9283  */
9284 static void
9285 i40e_hw_init(struct rte_eth_dev *dev)
9286 {
9287         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9288
9289         i40e_enable_extended_tag(dev);
9290
9291         /* clear the PF Queue Filter control register */
9292         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9293
9294         /* Disable symmetric hash per port */
9295         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9296 }
9297
9298 /*
9299  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9300  * however this function will return only one highest pctype index,
9301  * which is not quite correct. This is known problem of i40e driver
9302  * and needs to be fixed later.
9303  */
9304 enum i40e_filter_pctype
9305 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9306 {
9307         int i;
9308         uint64_t pctype_mask;
9309
9310         if (flow_type < I40E_FLOW_TYPE_MAX) {
9311                 pctype_mask = adapter->pctypes_tbl[flow_type];
9312                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9313                         if (pctype_mask & (1ULL << i))
9314                                 return (enum i40e_filter_pctype)i;
9315                 }
9316         }
9317         return I40E_FILTER_PCTYPE_INVALID;
9318 }
9319
9320 uint16_t
9321 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9322                         enum i40e_filter_pctype pctype)
9323 {
9324         uint16_t flowtype;
9325         uint64_t pctype_mask = 1ULL << pctype;
9326
9327         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9328              flowtype++) {
9329                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9330                         return flowtype;
9331         }
9332
9333         return RTE_ETH_FLOW_UNKNOWN;
9334 }
9335
9336 /*
9337  * On X710, performance number is far from the expectation on recent firmware
9338  * versions; on XL710, performance number is also far from the expectation on
9339  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9340  * mode is enabled and port MAC address is equal to the packet destination MAC
9341  * address. The fix for this issue may not be integrated in the following
9342  * firmware version. So the workaround in software driver is needed. It needs
9343  * to modify the initial values of 3 internal only registers for both X710 and
9344  * XL710. Note that the values for X710 or XL710 could be different, and the
9345  * workaround can be removed when it is fixed in firmware in the future.
9346  */
9347
9348 /* For both X710 and XL710 */
9349 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9350 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x20000200
9351 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9352
9353 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9354 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9355
9356 /* For X722 */
9357 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9358 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9359
9360 /* For X710 */
9361 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9362 /* For XL710 */
9363 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9364 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9365
9366 static int
9367 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9368 {
9369         enum i40e_status_code status;
9370         struct i40e_aq_get_phy_abilities_resp phy_ab;
9371         int ret = -ENOTSUP;
9372         int retries = 0;
9373
9374         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9375                                               NULL);
9376
9377         while (status) {
9378                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9379                         status);
9380                 retries++;
9381                 rte_delay_us(100000);
9382                 if  (retries < 5)
9383                         status = i40e_aq_get_phy_capabilities(hw, false,
9384                                         true, &phy_ab, NULL);
9385                 else
9386                         return ret;
9387         }
9388         return 0;
9389 }
9390
9391 static void
9392 i40e_configure_registers(struct i40e_hw *hw)
9393 {
9394         static struct {
9395                 uint32_t addr;
9396                 uint64_t val;
9397         } reg_table[] = {
9398                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9399                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9400                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9401         };
9402         uint64_t reg;
9403         uint32_t i;
9404         int ret;
9405
9406         for (i = 0; i < RTE_DIM(reg_table); i++) {
9407                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9408                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9409                                 reg_table[i].val =
9410                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9411                         else /* For X710/XL710/XXV710 */
9412                                 if (hw->aq.fw_maj_ver < 6)
9413                                         reg_table[i].val =
9414                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9415                                 else
9416                                         reg_table[i].val =
9417                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9418                 }
9419
9420                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9421                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9422                                 reg_table[i].val =
9423                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9424                         else /* For X710/XL710/XXV710 */
9425                                 reg_table[i].val =
9426                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9427                 }
9428
9429                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9430                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9431                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9432                                 reg_table[i].val =
9433                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9434                         else /* For X710 */
9435                                 reg_table[i].val =
9436                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9437                 }
9438
9439                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9440                                                         &reg, NULL);
9441                 if (ret < 0) {
9442                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9443                                                         reg_table[i].addr);
9444                         break;
9445                 }
9446                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9447                                                 reg_table[i].addr, reg);
9448                 if (reg == reg_table[i].val)
9449                         continue;
9450
9451                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9452                                                 reg_table[i].val, NULL);
9453                 if (ret < 0) {
9454                         PMD_DRV_LOG(ERR,
9455                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9456                                 reg_table[i].val, reg_table[i].addr);
9457                         break;
9458                 }
9459                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9460                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9461         }
9462 }
9463
9464 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9465 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9466 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9467 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9468 static int
9469 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9470 {
9471         uint32_t reg;
9472         int ret;
9473
9474         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9475                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9476                 return -EINVAL;
9477         }
9478
9479         /* Configure for double VLAN RX stripping */
9480         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9481         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9482                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9483                 ret = i40e_aq_debug_write_register(hw,
9484                                                    I40E_VSI_TSR(vsi->vsi_id),
9485                                                    reg, NULL);
9486                 if (ret < 0) {
9487                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9488                                     vsi->vsi_id);
9489                         return I40E_ERR_CONFIG;
9490                 }
9491         }
9492
9493         /* Configure for double VLAN TX insertion */
9494         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9495         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9496                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9497                 ret = i40e_aq_debug_write_register(hw,
9498                                                    I40E_VSI_L2TAGSTXVALID(
9499                                                    vsi->vsi_id), reg, NULL);
9500                 if (ret < 0) {
9501                         PMD_DRV_LOG(ERR,
9502                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9503                                 vsi->vsi_id);
9504                         return I40E_ERR_CONFIG;
9505                 }
9506         }
9507
9508         return 0;
9509 }
9510
9511 /**
9512  * i40e_aq_add_mirror_rule
9513  * @hw: pointer to the hardware structure
9514  * @seid: VEB seid to add mirror rule to
9515  * @dst_id: destination vsi seid
9516  * @entries: Buffer which contains the entities to be mirrored
9517  * @count: number of entities contained in the buffer
9518  * @rule_id:the rule_id of the rule to be added
9519  *
9520  * Add a mirror rule for a given veb.
9521  *
9522  **/
9523 static enum i40e_status_code
9524 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9525                         uint16_t seid, uint16_t dst_id,
9526                         uint16_t rule_type, uint16_t *entries,
9527                         uint16_t count, uint16_t *rule_id)
9528 {
9529         struct i40e_aq_desc desc;
9530         struct i40e_aqc_add_delete_mirror_rule cmd;
9531         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9532                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9533                 &desc.params.raw;
9534         uint16_t buff_len;
9535         enum i40e_status_code status;
9536
9537         i40e_fill_default_direct_cmd_desc(&desc,
9538                                           i40e_aqc_opc_add_mirror_rule);
9539         memset(&cmd, 0, sizeof(cmd));
9540
9541         buff_len = sizeof(uint16_t) * count;
9542         desc.datalen = rte_cpu_to_le_16(buff_len);
9543         if (buff_len > 0)
9544                 desc.flags |= rte_cpu_to_le_16(
9545                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9546         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9547                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9548         cmd.num_entries = rte_cpu_to_le_16(count);
9549         cmd.seid = rte_cpu_to_le_16(seid);
9550         cmd.destination = rte_cpu_to_le_16(dst_id);
9551
9552         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9553         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9554         PMD_DRV_LOG(INFO,
9555                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9556                 hw->aq.asq_last_status, resp->rule_id,
9557                 resp->mirror_rules_used, resp->mirror_rules_free);
9558         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9559
9560         return status;
9561 }
9562
9563 /**
9564  * i40e_aq_del_mirror_rule
9565  * @hw: pointer to the hardware structure
9566  * @seid: VEB seid to add mirror rule to
9567  * @entries: Buffer which contains the entities to be mirrored
9568  * @count: number of entities contained in the buffer
9569  * @rule_id:the rule_id of the rule to be delete
9570  *
9571  * Delete a mirror rule for a given veb.
9572  *
9573  **/
9574 static enum i40e_status_code
9575 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9576                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9577                 uint16_t count, uint16_t rule_id)
9578 {
9579         struct i40e_aq_desc desc;
9580         struct i40e_aqc_add_delete_mirror_rule cmd;
9581         uint16_t buff_len = 0;
9582         enum i40e_status_code status;
9583         void *buff = NULL;
9584
9585         i40e_fill_default_direct_cmd_desc(&desc,
9586                                           i40e_aqc_opc_delete_mirror_rule);
9587         memset(&cmd, 0, sizeof(cmd));
9588         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9589                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9590                                                           I40E_AQ_FLAG_RD));
9591                 cmd.num_entries = count;
9592                 buff_len = sizeof(uint16_t) * count;
9593                 desc.datalen = rte_cpu_to_le_16(buff_len);
9594                 buff = (void *)entries;
9595         } else
9596                 /* rule id is filled in destination field for deleting mirror rule */
9597                 cmd.destination = rte_cpu_to_le_16(rule_id);
9598
9599         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9600                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9601         cmd.seid = rte_cpu_to_le_16(seid);
9602
9603         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9604         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9605
9606         return status;
9607 }
9608
9609 /**
9610  * i40e_mirror_rule_set
9611  * @dev: pointer to the hardware structure
9612  * @mirror_conf: mirror rule info
9613  * @sw_id: mirror rule's sw_id
9614  * @on: enable/disable
9615  *
9616  * set a mirror rule.
9617  *
9618  **/
9619 static int
9620 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9621                         struct rte_eth_mirror_conf *mirror_conf,
9622                         uint8_t sw_id, uint8_t on)
9623 {
9624         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9625         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9626         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9627         struct i40e_mirror_rule *parent = NULL;
9628         uint16_t seid, dst_seid, rule_id;
9629         uint16_t i, j = 0;
9630         int ret;
9631
9632         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9633
9634         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9635                 PMD_DRV_LOG(ERR,
9636                         "mirror rule can not be configured without veb or vfs.");
9637                 return -ENOSYS;
9638         }
9639         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9640                 PMD_DRV_LOG(ERR, "mirror table is full.");
9641                 return -ENOSPC;
9642         }
9643         if (mirror_conf->dst_pool > pf->vf_num) {
9644                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9645                                  mirror_conf->dst_pool);
9646                 return -EINVAL;
9647         }
9648
9649         seid = pf->main_vsi->veb->seid;
9650
9651         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9652                 if (sw_id <= it->index) {
9653                         mirr_rule = it;
9654                         break;
9655                 }
9656                 parent = it;
9657         }
9658         if (mirr_rule && sw_id == mirr_rule->index) {
9659                 if (on) {
9660                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9661                         return -EEXIST;
9662                 } else {
9663                         ret = i40e_aq_del_mirror_rule(hw, seid,
9664                                         mirr_rule->rule_type,
9665                                         mirr_rule->entries,
9666                                         mirr_rule->num_entries, mirr_rule->id);
9667                         if (ret < 0) {
9668                                 PMD_DRV_LOG(ERR,
9669                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9670                                         ret, hw->aq.asq_last_status);
9671                                 return -ENOSYS;
9672                         }
9673                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9674                         rte_free(mirr_rule);
9675                         pf->nb_mirror_rule--;
9676                         return 0;
9677                 }
9678         } else if (!on) {
9679                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9680                 return -ENOENT;
9681         }
9682
9683         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9684                                 sizeof(struct i40e_mirror_rule) , 0);
9685         if (!mirr_rule) {
9686                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9687                 return I40E_ERR_NO_MEMORY;
9688         }
9689         switch (mirror_conf->rule_type) {
9690         case ETH_MIRROR_VLAN:
9691                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9692                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9693                                 mirr_rule->entries[j] =
9694                                         mirror_conf->vlan.vlan_id[i];
9695                                 j++;
9696                         }
9697                 }
9698                 if (j == 0) {
9699                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9700                         rte_free(mirr_rule);
9701                         return -EINVAL;
9702                 }
9703                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9704                 break;
9705         case ETH_MIRROR_VIRTUAL_POOL_UP:
9706         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9707                 /* check if the specified pool bit is out of range */
9708                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9709                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9710                         rte_free(mirr_rule);
9711                         return -EINVAL;
9712                 }
9713                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9714                         if (mirror_conf->pool_mask & (1ULL << i)) {
9715                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9716                                 j++;
9717                         }
9718                 }
9719                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9720                         /* add pf vsi to entries */
9721                         mirr_rule->entries[j] = pf->main_vsi_seid;
9722                         j++;
9723                 }
9724                 if (j == 0) {
9725                         PMD_DRV_LOG(ERR, "pool is not specified.");
9726                         rte_free(mirr_rule);
9727                         return -EINVAL;
9728                 }
9729                 /* egress and ingress in aq commands means from switch but not port */
9730                 mirr_rule->rule_type =
9731                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9732                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9733                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9734                 break;
9735         case ETH_MIRROR_UPLINK_PORT:
9736                 /* egress and ingress in aq commands means from switch but not port*/
9737                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9738                 break;
9739         case ETH_MIRROR_DOWNLINK_PORT:
9740                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9741                 break;
9742         default:
9743                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9744                         mirror_conf->rule_type);
9745                 rte_free(mirr_rule);
9746                 return -EINVAL;
9747         }
9748
9749         /* If the dst_pool is equal to vf_num, consider it as PF */
9750         if (mirror_conf->dst_pool == pf->vf_num)
9751                 dst_seid = pf->main_vsi_seid;
9752         else
9753                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9754
9755         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9756                                       mirr_rule->rule_type, mirr_rule->entries,
9757                                       j, &rule_id);
9758         if (ret < 0) {
9759                 PMD_DRV_LOG(ERR,
9760                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9761                         ret, hw->aq.asq_last_status);
9762                 rte_free(mirr_rule);
9763                 return -ENOSYS;
9764         }
9765
9766         mirr_rule->index = sw_id;
9767         mirr_rule->num_entries = j;
9768         mirr_rule->id = rule_id;
9769         mirr_rule->dst_vsi_seid = dst_seid;
9770
9771         if (parent)
9772                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9773         else
9774                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9775
9776         pf->nb_mirror_rule++;
9777         return 0;
9778 }
9779
9780 /**
9781  * i40e_mirror_rule_reset
9782  * @dev: pointer to the device
9783  * @sw_id: mirror rule's sw_id
9784  *
9785  * reset a mirror rule.
9786  *
9787  **/
9788 static int
9789 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9790 {
9791         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9792         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9793         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9794         uint16_t seid;
9795         int ret;
9796
9797         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9798
9799         seid = pf->main_vsi->veb->seid;
9800
9801         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9802                 if (sw_id == it->index) {
9803                         mirr_rule = it;
9804                         break;
9805                 }
9806         }
9807         if (mirr_rule) {
9808                 ret = i40e_aq_del_mirror_rule(hw, seid,
9809                                 mirr_rule->rule_type,
9810                                 mirr_rule->entries,
9811                                 mirr_rule->num_entries, mirr_rule->id);
9812                 if (ret < 0) {
9813                         PMD_DRV_LOG(ERR,
9814                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9815                                 ret, hw->aq.asq_last_status);
9816                         return -ENOSYS;
9817                 }
9818                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9819                 rte_free(mirr_rule);
9820                 pf->nb_mirror_rule--;
9821         } else {
9822                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9823                 return -ENOENT;
9824         }
9825         return 0;
9826 }
9827
9828 static uint64_t
9829 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9830 {
9831         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9832         uint64_t systim_cycles;
9833
9834         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9835         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9836                         << 32;
9837
9838         return systim_cycles;
9839 }
9840
9841 static uint64_t
9842 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9843 {
9844         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9845         uint64_t rx_tstamp;
9846
9847         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9848         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9849                         << 32;
9850
9851         return rx_tstamp;
9852 }
9853
9854 static uint64_t
9855 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9856 {
9857         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9858         uint64_t tx_tstamp;
9859
9860         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9861         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9862                         << 32;
9863
9864         return tx_tstamp;
9865 }
9866
9867 static void
9868 i40e_start_timecounters(struct rte_eth_dev *dev)
9869 {
9870         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9871         struct i40e_adapter *adapter =
9872                         (struct i40e_adapter *)dev->data->dev_private;
9873         struct rte_eth_link link;
9874         uint32_t tsync_inc_l;
9875         uint32_t tsync_inc_h;
9876
9877         /* Get current link speed. */
9878         memset(&link, 0, sizeof(link));
9879         i40e_dev_link_update(dev, 1);
9880         rte_i40e_dev_atomic_read_link_status(dev, &link);
9881
9882         switch (link.link_speed) {
9883         case ETH_SPEED_NUM_40G:
9884                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9885                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9886                 break;
9887         case ETH_SPEED_NUM_10G:
9888                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9889                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9890                 break;
9891         case ETH_SPEED_NUM_1G:
9892                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9893                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9894                 break;
9895         default:
9896                 tsync_inc_l = 0x0;
9897                 tsync_inc_h = 0x0;
9898         }
9899
9900         /* Set the timesync increment value. */
9901         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9902         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9903
9904         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9905         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9906         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9907
9908         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9909         adapter->systime_tc.cc_shift = 0;
9910         adapter->systime_tc.nsec_mask = 0;
9911
9912         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9913         adapter->rx_tstamp_tc.cc_shift = 0;
9914         adapter->rx_tstamp_tc.nsec_mask = 0;
9915
9916         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9917         adapter->tx_tstamp_tc.cc_shift = 0;
9918         adapter->tx_tstamp_tc.nsec_mask = 0;
9919 }
9920
9921 static int
9922 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9923 {
9924         struct i40e_adapter *adapter =
9925                         (struct i40e_adapter *)dev->data->dev_private;
9926
9927         adapter->systime_tc.nsec += delta;
9928         adapter->rx_tstamp_tc.nsec += delta;
9929         adapter->tx_tstamp_tc.nsec += delta;
9930
9931         return 0;
9932 }
9933
9934 static int
9935 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9936 {
9937         uint64_t ns;
9938         struct i40e_adapter *adapter =
9939                         (struct i40e_adapter *)dev->data->dev_private;
9940
9941         ns = rte_timespec_to_ns(ts);
9942
9943         /* Set the timecounters to a new value. */
9944         adapter->systime_tc.nsec = ns;
9945         adapter->rx_tstamp_tc.nsec = ns;
9946         adapter->tx_tstamp_tc.nsec = ns;
9947
9948         return 0;
9949 }
9950
9951 static int
9952 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9953 {
9954         uint64_t ns, systime_cycles;
9955         struct i40e_adapter *adapter =
9956                         (struct i40e_adapter *)dev->data->dev_private;
9957
9958         systime_cycles = i40e_read_systime_cyclecounter(dev);
9959         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9960         *ts = rte_ns_to_timespec(ns);
9961
9962         return 0;
9963 }
9964
9965 static int
9966 i40e_timesync_enable(struct rte_eth_dev *dev)
9967 {
9968         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9969         uint32_t tsync_ctl_l;
9970         uint32_t tsync_ctl_h;
9971
9972         /* Stop the timesync system time. */
9973         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9974         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9975         /* Reset the timesync system time value. */
9976         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9977         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9978
9979         i40e_start_timecounters(dev);
9980
9981         /* Clear timesync registers. */
9982         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9983         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9984         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9985         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9986         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9987         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9988
9989         /* Enable timestamping of PTP packets. */
9990         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9991         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9992
9993         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9994         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9995         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9996
9997         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9998         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9999
10000         return 0;
10001 }
10002
10003 static int
10004 i40e_timesync_disable(struct rte_eth_dev *dev)
10005 {
10006         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10007         uint32_t tsync_ctl_l;
10008         uint32_t tsync_ctl_h;
10009
10010         /* Disable timestamping of transmitted PTP packets. */
10011         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10012         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10013
10014         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10015         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10016
10017         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10018         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10019
10020         /* Reset the timesync increment value. */
10021         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10022         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10023
10024         return 0;
10025 }
10026
10027 static int
10028 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10029                                 struct timespec *timestamp, uint32_t flags)
10030 {
10031         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10032         struct i40e_adapter *adapter =
10033                 (struct i40e_adapter *)dev->data->dev_private;
10034
10035         uint32_t sync_status;
10036         uint32_t index = flags & 0x03;
10037         uint64_t rx_tstamp_cycles;
10038         uint64_t ns;
10039
10040         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10041         if ((sync_status & (1 << index)) == 0)
10042                 return -EINVAL;
10043
10044         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10045         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10046         *timestamp = rte_ns_to_timespec(ns);
10047
10048         return 0;
10049 }
10050
10051 static int
10052 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10053                                 struct timespec *timestamp)
10054 {
10055         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10056         struct i40e_adapter *adapter =
10057                 (struct i40e_adapter *)dev->data->dev_private;
10058
10059         uint32_t sync_status;
10060         uint64_t tx_tstamp_cycles;
10061         uint64_t ns;
10062
10063         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10064         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10065                 return -EINVAL;
10066
10067         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10068         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10069         *timestamp = rte_ns_to_timespec(ns);
10070
10071         return 0;
10072 }
10073
10074 /*
10075  * i40e_parse_dcb_configure - parse dcb configure from user
10076  * @dev: the device being configured
10077  * @dcb_cfg: pointer of the result of parse
10078  * @*tc_map: bit map of enabled traffic classes
10079  *
10080  * Returns 0 on success, negative value on failure
10081  */
10082 static int
10083 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10084                          struct i40e_dcbx_config *dcb_cfg,
10085                          uint8_t *tc_map)
10086 {
10087         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10088         uint8_t i, tc_bw, bw_lf;
10089
10090         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10091
10092         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10093         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10094                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10095                 return -EINVAL;
10096         }
10097
10098         /* assume each tc has the same bw */
10099         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10100         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10101                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10102         /* to ensure the sum of tcbw is equal to 100 */
10103         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10104         for (i = 0; i < bw_lf; i++)
10105                 dcb_cfg->etscfg.tcbwtable[i]++;
10106
10107         /* assume each tc has the same Transmission Selection Algorithm */
10108         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10109                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10110
10111         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10112                 dcb_cfg->etscfg.prioritytable[i] =
10113                                 dcb_rx_conf->dcb_tc[i];
10114
10115         /* FW needs one App to configure HW */
10116         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10117         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10118         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10119         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10120
10121         if (dcb_rx_conf->nb_tcs == 0)
10122                 *tc_map = 1; /* tc0 only */
10123         else
10124                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10125
10126         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10127                 dcb_cfg->pfc.willing = 0;
10128                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10129                 dcb_cfg->pfc.pfcenable = *tc_map;
10130         }
10131         return 0;
10132 }
10133
10134
10135 static enum i40e_status_code
10136 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10137                               struct i40e_aqc_vsi_properties_data *info,
10138                               uint8_t enabled_tcmap)
10139 {
10140         enum i40e_status_code ret;
10141         int i, total_tc = 0;
10142         uint16_t qpnum_per_tc, bsf, qp_idx;
10143         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10144         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10145         uint16_t used_queues;
10146
10147         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10148         if (ret != I40E_SUCCESS)
10149                 return ret;
10150
10151         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10152                 if (enabled_tcmap & (1 << i))
10153                         total_tc++;
10154         }
10155         if (total_tc == 0)
10156                 total_tc = 1;
10157         vsi->enabled_tc = enabled_tcmap;
10158
10159         /* different VSI has different queues assigned */
10160         if (vsi->type == I40E_VSI_MAIN)
10161                 used_queues = dev_data->nb_rx_queues -
10162                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10163         else if (vsi->type == I40E_VSI_VMDQ2)
10164                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10165         else {
10166                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10167                 return I40E_ERR_NO_AVAILABLE_VSI;
10168         }
10169
10170         qpnum_per_tc = used_queues / total_tc;
10171         /* Number of queues per enabled TC */
10172         if (qpnum_per_tc == 0) {
10173                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10174                 return I40E_ERR_INVALID_QP_ID;
10175         }
10176         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10177                                 I40E_MAX_Q_PER_TC);
10178         bsf = rte_bsf32(qpnum_per_tc);
10179
10180         /**
10181          * Configure TC and queue mapping parameters, for enabled TC,
10182          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10183          * default queue will serve it.
10184          */
10185         qp_idx = 0;
10186         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10187                 if (vsi->enabled_tc & (1 << i)) {
10188                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10189                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10190                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10191                         qp_idx += qpnum_per_tc;
10192                 } else
10193                         info->tc_mapping[i] = 0;
10194         }
10195
10196         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10197         if (vsi->type == I40E_VSI_SRIOV) {
10198                 info->mapping_flags |=
10199                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10200                 for (i = 0; i < vsi->nb_qps; i++)
10201                         info->queue_mapping[i] =
10202                                 rte_cpu_to_le_16(vsi->base_queue + i);
10203         } else {
10204                 info->mapping_flags |=
10205                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10206                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10207         }
10208         info->valid_sections |=
10209                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10210
10211         return I40E_SUCCESS;
10212 }
10213
10214 /*
10215  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10216  * @veb: VEB to be configured
10217  * @tc_map: enabled TC bitmap
10218  *
10219  * Returns 0 on success, negative value on failure
10220  */
10221 static enum i40e_status_code
10222 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10223 {
10224         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10225         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10226         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10227         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10228         enum i40e_status_code ret = I40E_SUCCESS;
10229         int i;
10230         uint32_t bw_max;
10231
10232         /* Check if enabled_tc is same as existing or new TCs */
10233         if (veb->enabled_tc == tc_map)
10234                 return ret;
10235
10236         /* configure tc bandwidth */
10237         memset(&veb_bw, 0, sizeof(veb_bw));
10238         veb_bw.tc_valid_bits = tc_map;
10239         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10240         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10241                 if (tc_map & BIT_ULL(i))
10242                         veb_bw.tc_bw_share_credits[i] = 1;
10243         }
10244         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10245                                                    &veb_bw, NULL);
10246         if (ret) {
10247                 PMD_INIT_LOG(ERR,
10248                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10249                         hw->aq.asq_last_status);
10250                 return ret;
10251         }
10252
10253         memset(&ets_query, 0, sizeof(ets_query));
10254         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10255                                                    &ets_query, NULL);
10256         if (ret != I40E_SUCCESS) {
10257                 PMD_DRV_LOG(ERR,
10258                         "Failed to get switch_comp ETS configuration %u",
10259                         hw->aq.asq_last_status);
10260                 return ret;
10261         }
10262         memset(&bw_query, 0, sizeof(bw_query));
10263         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10264                                                   &bw_query, NULL);
10265         if (ret != I40E_SUCCESS) {
10266                 PMD_DRV_LOG(ERR,
10267                         "Failed to get switch_comp bandwidth configuration %u",
10268                         hw->aq.asq_last_status);
10269                 return ret;
10270         }
10271
10272         /* store and print out BW info */
10273         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10274         veb->bw_info.bw_max = ets_query.tc_bw_max;
10275         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10276         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10277         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10278                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10279                      I40E_16_BIT_WIDTH);
10280         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10281                 veb->bw_info.bw_ets_share_credits[i] =
10282                                 bw_query.tc_bw_share_credits[i];
10283                 veb->bw_info.bw_ets_credits[i] =
10284                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10285                 /* 4 bits per TC, 4th bit is reserved */
10286                 veb->bw_info.bw_ets_max[i] =
10287                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10288                                   RTE_LEN2MASK(3, uint8_t));
10289                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10290                             veb->bw_info.bw_ets_share_credits[i]);
10291                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10292                             veb->bw_info.bw_ets_credits[i]);
10293                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10294                             veb->bw_info.bw_ets_max[i]);
10295         }
10296
10297         veb->enabled_tc = tc_map;
10298
10299         return ret;
10300 }
10301
10302
10303 /*
10304  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10305  * @vsi: VSI to be configured
10306  * @tc_map: enabled TC bitmap
10307  *
10308  * Returns 0 on success, negative value on failure
10309  */
10310 static enum i40e_status_code
10311 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10312 {
10313         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10314         struct i40e_vsi_context ctxt;
10315         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10316         enum i40e_status_code ret = I40E_SUCCESS;
10317         int i;
10318
10319         /* Check if enabled_tc is same as existing or new TCs */
10320         if (vsi->enabled_tc == tc_map)
10321                 return ret;
10322
10323         /* configure tc bandwidth */
10324         memset(&bw_data, 0, sizeof(bw_data));
10325         bw_data.tc_valid_bits = tc_map;
10326         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10327         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10328                 if (tc_map & BIT_ULL(i))
10329                         bw_data.tc_bw_credits[i] = 1;
10330         }
10331         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10332         if (ret) {
10333                 PMD_INIT_LOG(ERR,
10334                         "AQ command Config VSI BW allocation per TC failed = %d",
10335                         hw->aq.asq_last_status);
10336                 goto out;
10337         }
10338         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10339                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10340
10341         /* Update Queue Pairs Mapping for currently enabled UPs */
10342         ctxt.seid = vsi->seid;
10343         ctxt.pf_num = hw->pf_id;
10344         ctxt.vf_num = 0;
10345         ctxt.uplink_seid = vsi->uplink_seid;
10346         ctxt.info = vsi->info;
10347         i40e_get_cap(hw);
10348         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10349         if (ret)
10350                 goto out;
10351
10352         /* Update the VSI after updating the VSI queue-mapping information */
10353         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10354         if (ret) {
10355                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10356                         hw->aq.asq_last_status);
10357                 goto out;
10358         }
10359         /* update the local VSI info with updated queue map */
10360         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10361                                         sizeof(vsi->info.tc_mapping));
10362         rte_memcpy(&vsi->info.queue_mapping,
10363                         &ctxt.info.queue_mapping,
10364                 sizeof(vsi->info.queue_mapping));
10365         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10366         vsi->info.valid_sections = 0;
10367
10368         /* query and update current VSI BW information */
10369         ret = i40e_vsi_get_bw_config(vsi);
10370         if (ret) {
10371                 PMD_INIT_LOG(ERR,
10372                          "Failed updating vsi bw info, err %s aq_err %s",
10373                          i40e_stat_str(hw, ret),
10374                          i40e_aq_str(hw, hw->aq.asq_last_status));
10375                 goto out;
10376         }
10377
10378         vsi->enabled_tc = tc_map;
10379
10380 out:
10381         return ret;
10382 }
10383
10384 /*
10385  * i40e_dcb_hw_configure - program the dcb setting to hw
10386  * @pf: pf the configuration is taken on
10387  * @new_cfg: new configuration
10388  * @tc_map: enabled TC bitmap
10389  *
10390  * Returns 0 on success, negative value on failure
10391  */
10392 static enum i40e_status_code
10393 i40e_dcb_hw_configure(struct i40e_pf *pf,
10394                       struct i40e_dcbx_config *new_cfg,
10395                       uint8_t tc_map)
10396 {
10397         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10398         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10399         struct i40e_vsi *main_vsi = pf->main_vsi;
10400         struct i40e_vsi_list *vsi_list;
10401         enum i40e_status_code ret;
10402         int i;
10403         uint32_t val;
10404
10405         /* Use the FW API if FW > v4.4*/
10406         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10407               (hw->aq.fw_maj_ver >= 5))) {
10408                 PMD_INIT_LOG(ERR,
10409                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10410                 return I40E_ERR_FIRMWARE_API_VERSION;
10411         }
10412
10413         /* Check if need reconfiguration */
10414         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10415                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10416                 return I40E_SUCCESS;
10417         }
10418
10419         /* Copy the new config to the current config */
10420         *old_cfg = *new_cfg;
10421         old_cfg->etsrec = old_cfg->etscfg;
10422         ret = i40e_set_dcb_config(hw);
10423         if (ret) {
10424                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10425                          i40e_stat_str(hw, ret),
10426                          i40e_aq_str(hw, hw->aq.asq_last_status));
10427                 return ret;
10428         }
10429         /* set receive Arbiter to RR mode and ETS scheme by default */
10430         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10431                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10432                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10433                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10434                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10435                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10436                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10437                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10438                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10439                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10440                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10441                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10442                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10443         }
10444         /* get local mib to check whether it is configured correctly */
10445         /* IEEE mode */
10446         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10447         /* Get Local DCB Config */
10448         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10449                                      &hw->local_dcbx_config);
10450
10451         /* if Veb is created, need to update TC of it at first */
10452         if (main_vsi->veb) {
10453                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10454                 if (ret)
10455                         PMD_INIT_LOG(WARNING,
10456                                  "Failed configuring TC for VEB seid=%d",
10457                                  main_vsi->veb->seid);
10458         }
10459         /* Update each VSI */
10460         i40e_vsi_config_tc(main_vsi, tc_map);
10461         if (main_vsi->veb) {
10462                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10463                         /* Beside main VSI and VMDQ VSIs, only enable default
10464                          * TC for other VSIs
10465                          */
10466                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10467                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10468                                                          tc_map);
10469                         else
10470                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10471                                                          I40E_DEFAULT_TCMAP);
10472                         if (ret)
10473                                 PMD_INIT_LOG(WARNING,
10474                                         "Failed configuring TC for VSI seid=%d",
10475                                         vsi_list->vsi->seid);
10476                         /* continue */
10477                 }
10478         }
10479         return I40E_SUCCESS;
10480 }
10481
10482 /*
10483  * i40e_dcb_init_configure - initial dcb config
10484  * @dev: device being configured
10485  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10486  *
10487  * Returns 0 on success, negative value on failure
10488  */
10489 int
10490 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10491 {
10492         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10493         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10494         int i, ret = 0;
10495
10496         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10497                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10498                 return -ENOTSUP;
10499         }
10500
10501         /* DCB initialization:
10502          * Update DCB configuration from the Firmware and configure
10503          * LLDP MIB change event.
10504          */
10505         if (sw_dcb == TRUE) {
10506                 ret = i40e_init_dcb(hw);
10507                 /* If lldp agent is stopped, the return value from
10508                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10509                  * adminq status. Otherwise, it should return success.
10510                  */
10511                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10512                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10513                         memset(&hw->local_dcbx_config, 0,
10514                                 sizeof(struct i40e_dcbx_config));
10515                         /* set dcb default configuration */
10516                         hw->local_dcbx_config.etscfg.willing = 0;
10517                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10518                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10519                         hw->local_dcbx_config.etscfg.tsatable[0] =
10520                                                 I40E_IEEE_TSA_ETS;
10521                         /* all UPs mapping to TC0 */
10522                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10523                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10524                         hw->local_dcbx_config.etsrec =
10525                                 hw->local_dcbx_config.etscfg;
10526                         hw->local_dcbx_config.pfc.willing = 0;
10527                         hw->local_dcbx_config.pfc.pfccap =
10528                                                 I40E_MAX_TRAFFIC_CLASS;
10529                         /* FW needs one App to configure HW */
10530                         hw->local_dcbx_config.numapps = 1;
10531                         hw->local_dcbx_config.app[0].selector =
10532                                                 I40E_APP_SEL_ETHTYPE;
10533                         hw->local_dcbx_config.app[0].priority = 3;
10534                         hw->local_dcbx_config.app[0].protocolid =
10535                                                 I40E_APP_PROTOID_FCOE;
10536                         ret = i40e_set_dcb_config(hw);
10537                         if (ret) {
10538                                 PMD_INIT_LOG(ERR,
10539                                         "default dcb config fails. err = %d, aq_err = %d.",
10540                                         ret, hw->aq.asq_last_status);
10541                                 return -ENOSYS;
10542                         }
10543                 } else {
10544                         PMD_INIT_LOG(ERR,
10545                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10546                                 ret, hw->aq.asq_last_status);
10547                         return -ENOTSUP;
10548                 }
10549         } else {
10550                 ret = i40e_aq_start_lldp(hw, NULL);
10551                 if (ret != I40E_SUCCESS)
10552                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10553
10554                 ret = i40e_init_dcb(hw);
10555                 if (!ret) {
10556                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10557                                 PMD_INIT_LOG(ERR,
10558                                         "HW doesn't support DCBX offload.");
10559                                 return -ENOTSUP;
10560                         }
10561                 } else {
10562                         PMD_INIT_LOG(ERR,
10563                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10564                                 ret, hw->aq.asq_last_status);
10565                         return -ENOTSUP;
10566                 }
10567         }
10568         return 0;
10569 }
10570
10571 /*
10572  * i40e_dcb_setup - setup dcb related config
10573  * @dev: device being configured
10574  *
10575  * Returns 0 on success, negative value on failure
10576  */
10577 static int
10578 i40e_dcb_setup(struct rte_eth_dev *dev)
10579 {
10580         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10581         struct i40e_dcbx_config dcb_cfg;
10582         uint8_t tc_map = 0;
10583         int ret = 0;
10584
10585         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10586                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10587                 return -ENOTSUP;
10588         }
10589
10590         if (pf->vf_num != 0)
10591                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10592
10593         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10594         if (ret) {
10595                 PMD_INIT_LOG(ERR, "invalid dcb config");
10596                 return -EINVAL;
10597         }
10598         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10599         if (ret) {
10600                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10601                 return -ENOSYS;
10602         }
10603
10604         return 0;
10605 }
10606
10607 static int
10608 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10609                       struct rte_eth_dcb_info *dcb_info)
10610 {
10611         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10612         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10613         struct i40e_vsi *vsi = pf->main_vsi;
10614         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10615         uint16_t bsf, tc_mapping;
10616         int i, j = 0;
10617
10618         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10619                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10620         else
10621                 dcb_info->nb_tcs = 1;
10622         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10623                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10624         for (i = 0; i < dcb_info->nb_tcs; i++)
10625                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10626
10627         /* get queue mapping if vmdq is disabled */
10628         if (!pf->nb_cfg_vmdq_vsi) {
10629                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10630                         if (!(vsi->enabled_tc & (1 << i)))
10631                                 continue;
10632                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10633                         dcb_info->tc_queue.tc_rxq[j][i].base =
10634                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10635                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10636                         dcb_info->tc_queue.tc_txq[j][i].base =
10637                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10638                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10639                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10640                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10641                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10642                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10643                 }
10644                 return 0;
10645         }
10646
10647         /* get queue mapping if vmdq is enabled */
10648         do {
10649                 vsi = pf->vmdq[j].vsi;
10650                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10651                         if (!(vsi->enabled_tc & (1 << i)))
10652                                 continue;
10653                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10654                         dcb_info->tc_queue.tc_rxq[j][i].base =
10655                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10656                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10657                         dcb_info->tc_queue.tc_txq[j][i].base =
10658                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10659                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10660                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10661                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10662                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10663                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10664                 }
10665                 j++;
10666         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10667         return 0;
10668 }
10669
10670 static int
10671 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10672 {
10673         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10674         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10675         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10676         uint16_t interval =
10677                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10678         uint16_t msix_intr;
10679
10680         msix_intr = intr_handle->intr_vec[queue_id];
10681         if (msix_intr == I40E_MISC_VEC_ID)
10682                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10683                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10684                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10685                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10686                                (interval <<
10687                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10688         else
10689                 I40E_WRITE_REG(hw,
10690                                I40E_PFINT_DYN_CTLN(msix_intr -
10691                                                    I40E_RX_VEC_START),
10692                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10693                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10694                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10695                                (interval <<
10696                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10697
10698         I40E_WRITE_FLUSH(hw);
10699         rte_intr_enable(&pci_dev->intr_handle);
10700
10701         return 0;
10702 }
10703
10704 static int
10705 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10706 {
10707         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10708         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10709         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10710         uint16_t msix_intr;
10711
10712         msix_intr = intr_handle->intr_vec[queue_id];
10713         if (msix_intr == I40E_MISC_VEC_ID)
10714                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10715         else
10716                 I40E_WRITE_REG(hw,
10717                                I40E_PFINT_DYN_CTLN(msix_intr -
10718                                                    I40E_RX_VEC_START),
10719                                0);
10720         I40E_WRITE_FLUSH(hw);
10721
10722         return 0;
10723 }
10724
10725 static int i40e_get_regs(struct rte_eth_dev *dev,
10726                          struct rte_dev_reg_info *regs)
10727 {
10728         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10729         uint32_t *ptr_data = regs->data;
10730         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10731         const struct i40e_reg_info *reg_info;
10732
10733         if (ptr_data == NULL) {
10734                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10735                 regs->width = sizeof(uint32_t);
10736                 return 0;
10737         }
10738
10739         /* The first few registers have to be read using AQ operations */
10740         reg_idx = 0;
10741         while (i40e_regs_adminq[reg_idx].name) {
10742                 reg_info = &i40e_regs_adminq[reg_idx++];
10743                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10744                         for (arr_idx2 = 0;
10745                                         arr_idx2 <= reg_info->count2;
10746                                         arr_idx2++) {
10747                                 reg_offset = arr_idx * reg_info->stride1 +
10748                                         arr_idx2 * reg_info->stride2;
10749                                 reg_offset += reg_info->base_addr;
10750                                 ptr_data[reg_offset >> 2] =
10751                                         i40e_read_rx_ctl(hw, reg_offset);
10752                         }
10753         }
10754
10755         /* The remaining registers can be read using primitives */
10756         reg_idx = 0;
10757         while (i40e_regs_others[reg_idx].name) {
10758                 reg_info = &i40e_regs_others[reg_idx++];
10759                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10760                         for (arr_idx2 = 0;
10761                                         arr_idx2 <= reg_info->count2;
10762                                         arr_idx2++) {
10763                                 reg_offset = arr_idx * reg_info->stride1 +
10764                                         arr_idx2 * reg_info->stride2;
10765                                 reg_offset += reg_info->base_addr;
10766                                 ptr_data[reg_offset >> 2] =
10767                                         I40E_READ_REG(hw, reg_offset);
10768                         }
10769         }
10770
10771         return 0;
10772 }
10773
10774 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10775 {
10776         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10777
10778         /* Convert word count to byte count */
10779         return hw->nvm.sr_size << 1;
10780 }
10781
10782 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10783                            struct rte_dev_eeprom_info *eeprom)
10784 {
10785         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10786         uint16_t *data = eeprom->data;
10787         uint16_t offset, length, cnt_words;
10788         int ret_code;
10789
10790         offset = eeprom->offset >> 1;
10791         length = eeprom->length >> 1;
10792         cnt_words = length;
10793
10794         if (offset > hw->nvm.sr_size ||
10795                 offset + length > hw->nvm.sr_size) {
10796                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10797                 return -EINVAL;
10798         }
10799
10800         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10801
10802         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10803         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10804                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10805                 return -EIO;
10806         }
10807
10808         return 0;
10809 }
10810
10811 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10812                                       struct ether_addr *mac_addr)
10813 {
10814         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10815
10816         if (!is_valid_assigned_ether_addr(mac_addr)) {
10817                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10818                 return;
10819         }
10820
10821         /* Flags: 0x3 updates port address */
10822         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10823 }
10824
10825 static int
10826 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10827 {
10828         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10829         struct rte_eth_dev_data *dev_data = pf->dev_data;
10830         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10831         int ret = 0;
10832
10833         /* check if mtu is within the allowed range */
10834         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10835                 return -EINVAL;
10836
10837         /* mtu setting is forbidden if port is start */
10838         if (dev_data->dev_started) {
10839                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10840                             dev_data->port_id);
10841                 return -EBUSY;
10842         }
10843
10844         if (frame_size > ETHER_MAX_LEN)
10845                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10846         else
10847                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10848
10849         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10850
10851         return ret;
10852 }
10853
10854 /* Restore ethertype filter */
10855 static void
10856 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10857 {
10858         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10859         struct i40e_ethertype_filter_list
10860                 *ethertype_list = &pf->ethertype.ethertype_list;
10861         struct i40e_ethertype_filter *f;
10862         struct i40e_control_filter_stats stats;
10863         uint16_t flags;
10864
10865         TAILQ_FOREACH(f, ethertype_list, rules) {
10866                 flags = 0;
10867                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10868                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10869                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10870                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10871                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10872
10873                 memset(&stats, 0, sizeof(stats));
10874                 i40e_aq_add_rem_control_packet_filter(hw,
10875                                             f->input.mac_addr.addr_bytes,
10876                                             f->input.ether_type,
10877                                             flags, pf->main_vsi->seid,
10878                                             f->queue, 1, &stats, NULL);
10879         }
10880         PMD_DRV_LOG(INFO, "Ethertype filter:"
10881                     " mac_etype_used = %u, etype_used = %u,"
10882                     " mac_etype_free = %u, etype_free = %u",
10883                     stats.mac_etype_used, stats.etype_used,
10884                     stats.mac_etype_free, stats.etype_free);
10885 }
10886
10887 /* Restore tunnel filter */
10888 static void
10889 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10890 {
10891         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10892         struct i40e_vsi *vsi;
10893         struct i40e_pf_vf *vf;
10894         struct i40e_tunnel_filter_list
10895                 *tunnel_list = &pf->tunnel.tunnel_list;
10896         struct i40e_tunnel_filter *f;
10897         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10898         bool big_buffer = 0;
10899
10900         TAILQ_FOREACH(f, tunnel_list, rules) {
10901                 if (!f->is_to_vf)
10902                         vsi = pf->main_vsi;
10903                 else {
10904                         vf = &pf->vfs[f->vf_id];
10905                         vsi = vf->vsi;
10906                 }
10907                 memset(&cld_filter, 0, sizeof(cld_filter));
10908                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10909                         (struct ether_addr *)&cld_filter.element.outer_mac);
10910                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10911                         (struct ether_addr *)&cld_filter.element.inner_mac);
10912                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10913                 cld_filter.element.flags = f->input.flags;
10914                 cld_filter.element.tenant_id = f->input.tenant_id;
10915                 cld_filter.element.queue_number = f->queue;
10916                 rte_memcpy(cld_filter.general_fields,
10917                            f->input.general_fields,
10918                            sizeof(f->input.general_fields));
10919
10920                 if (((f->input.flags &
10921                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
10922                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
10923                     ((f->input.flags &
10924                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
10925                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
10926                     ((f->input.flags &
10927                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
10928                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
10929                         big_buffer = 1;
10930
10931                 if (big_buffer)
10932                         i40e_aq_add_cloud_filters_big_buffer(hw,
10933                                              vsi->seid, &cld_filter, 1);
10934                 else
10935                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10936                                                   &cld_filter.element, 1);
10937         }
10938 }
10939
10940 static void
10941 i40e_filter_restore(struct i40e_pf *pf)
10942 {
10943         i40e_ethertype_filter_restore(pf);
10944         i40e_tunnel_filter_restore(pf);
10945         i40e_fdir_filter_restore(pf);
10946 }
10947
10948 static bool
10949 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10950 {
10951         if (strcmp(dev->device->driver->name, drv->driver.name))
10952                 return false;
10953
10954         return true;
10955 }
10956
10957 bool
10958 is_i40e_supported(struct rte_eth_dev *dev)
10959 {
10960         return is_device_supported(dev, &rte_i40e_pmd);
10961 }
10962
10963 struct i40e_customized_pctype*
10964 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
10965 {
10966         int i;
10967
10968         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
10969                 if (pf->customized_pctype[i].index == index)
10970                         return &pf->customized_pctype[i];
10971         }
10972         return NULL;
10973 }
10974
10975 static int
10976 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
10977                               uint32_t pkg_size, uint32_t proto_num,
10978                               struct rte_pmd_i40e_proto_info *proto)
10979 {
10980         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10981         uint32_t pctype_num;
10982         struct rte_pmd_i40e_ptype_info *pctype;
10983         uint32_t buff_size;
10984         struct i40e_customized_pctype *new_pctype = NULL;
10985         uint8_t proto_id;
10986         uint8_t pctype_value;
10987         char name[64];
10988         uint32_t i, j, n;
10989         int ret;
10990
10991         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
10992                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
10993                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
10994         if (ret) {
10995                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
10996                 return -1;
10997         }
10998         if (!pctype_num) {
10999                 PMD_DRV_LOG(INFO, "No new pctype added");
11000                 return -1;
11001         }
11002
11003         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11004         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11005         if (!pctype) {
11006                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11007                 return -1;
11008         }
11009         /* get information about new pctype list */
11010         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11011                                         (uint8_t *)pctype, buff_size,
11012                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11013         if (ret) {
11014                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11015                 rte_free(pctype);
11016                 return -1;
11017         }
11018
11019         /* Update customized pctype. */
11020         for (i = 0; i < pctype_num; i++) {
11021                 pctype_value = pctype[i].ptype_id;
11022                 memset(name, 0, sizeof(name));
11023                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11024                         proto_id = pctype[i].protocols[j];
11025                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11026                                 continue;
11027                         for (n = 0; n < proto_num; n++) {
11028                                 if (proto[n].proto_id != proto_id)
11029                                         continue;
11030                                 strcat(name, proto[n].name);
11031                                 strcat(name, "_");
11032                                 break;
11033                         }
11034                 }
11035                 name[strlen(name) - 1] = '\0';
11036                 if (!strcmp(name, "GTPC"))
11037                         new_pctype =
11038                                 i40e_find_customized_pctype(pf,
11039                                                       I40E_CUSTOMIZED_GTPC);
11040                 else if (!strcmp(name, "GTPU_IPV4"))
11041                         new_pctype =
11042                                 i40e_find_customized_pctype(pf,
11043                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11044                 else if (!strcmp(name, "GTPU_IPV6"))
11045                         new_pctype =
11046                                 i40e_find_customized_pctype(pf,
11047                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11048                 else if (!strcmp(name, "GTPU"))
11049                         new_pctype =
11050                                 i40e_find_customized_pctype(pf,
11051                                                       I40E_CUSTOMIZED_GTPU);
11052                 if (new_pctype) {
11053                         new_pctype->pctype = pctype_value;
11054                         new_pctype->valid = true;
11055                 }
11056         }
11057
11058         rte_free(pctype);
11059         return 0;
11060 }
11061
11062 static int
11063 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11064                                uint32_t pkg_size, uint32_t proto_num,
11065                                struct rte_pmd_i40e_proto_info *proto)
11066 {
11067         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11068         uint16_t port_id = dev->data->port_id;
11069         uint32_t ptype_num;
11070         struct rte_pmd_i40e_ptype_info *ptype;
11071         uint32_t buff_size;
11072         uint8_t proto_id;
11073         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11074         uint32_t i, j, n;
11075         bool inner_ip;
11076         int ret;
11077
11078         /* get information about new ptype num */
11079         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11080                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11081                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11082         if (ret) {
11083                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11084                 return ret;
11085         }
11086         if (!ptype_num) {
11087                 PMD_DRV_LOG(INFO, "No new ptype added");
11088                 return -1;
11089         }
11090
11091         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11092         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11093         if (!ptype) {
11094                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11095                 return -1;
11096         }
11097
11098         /* get information about new ptype list */
11099         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11100                                         (uint8_t *)ptype, buff_size,
11101                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11102         if (ret) {
11103                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11104                 rte_free(ptype);
11105                 return ret;
11106         }
11107
11108         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11109         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11110         if (!ptype_mapping) {
11111                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11112                 rte_free(ptype);
11113                 return -1;
11114         }
11115
11116         /* Update ptype mapping table. */
11117         for (i = 0; i < ptype_num; i++) {
11118                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11119                 ptype_mapping[i].sw_ptype = 0;
11120                 inner_ip = false;
11121                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11122                         proto_id = ptype[i].protocols[j];
11123                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11124                                 continue;
11125                         for (n = 0; n < proto_num; n++) {
11126                                 if (proto[n].proto_id != proto_id)
11127                                         continue;
11128                                 memset(name, 0, sizeof(name));
11129                                 strcpy(name, proto[n].name);
11130                                 if (!strncmp(name, "IPV4", 4) && !inner_ip) {
11131                                         ptype_mapping[i].sw_ptype |=
11132                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11133                                         inner_ip = true;
11134                                 } else if (!strncmp(name, "IPV4FRAG", 8) &&
11135                                            inner_ip) {
11136                                         ptype_mapping[i].sw_ptype |=
11137                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11138                                         ptype_mapping[i].sw_ptype |=
11139                                                 RTE_PTYPE_INNER_L4_FRAG;
11140                                 } else if (!strncmp(name, "IPV4", 4) &&
11141                                            inner_ip)
11142                                         ptype_mapping[i].sw_ptype |=
11143                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11144                                 else if (!strncmp(name, "IPV6", 4) &&
11145                                          !inner_ip) {
11146                                         ptype_mapping[i].sw_ptype |=
11147                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11148                                         inner_ip = true;
11149                                 } else if (!strncmp(name, "IPV6FRAG", 8) &&
11150                                            inner_ip) {
11151                                         ptype_mapping[i].sw_ptype |=
11152                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11153                                         ptype_mapping[i].sw_ptype |=
11154                                                 RTE_PTYPE_INNER_L4_FRAG;
11155                                 } else if (!strncmp(name, "IPV6", 4) &&
11156                                            inner_ip)
11157                                         ptype_mapping[i].sw_ptype |=
11158                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11159                                 else if (!strncmp(name, "GTPC", 4))
11160                                         ptype_mapping[i].sw_ptype |=
11161                                                 RTE_PTYPE_TUNNEL_GTPC;
11162                                 else if (!strncmp(name, "GTPU", 4))
11163                                         ptype_mapping[i].sw_ptype |=
11164                                                 RTE_PTYPE_TUNNEL_GTPU;
11165                                 else if (!strncmp(name, "UDP", 3))
11166                                         ptype_mapping[i].sw_ptype |=
11167                                                 RTE_PTYPE_INNER_L4_UDP;
11168                                 else if (!strncmp(name, "TCP", 3))
11169                                         ptype_mapping[i].sw_ptype |=
11170                                                 RTE_PTYPE_INNER_L4_TCP;
11171                                 else if (!strncmp(name, "SCTP", 4))
11172                                         ptype_mapping[i].sw_ptype |=
11173                                                 RTE_PTYPE_INNER_L4_SCTP;
11174                                 else if (!strncmp(name, "ICMP", 4) ||
11175                                          !strncmp(name, "ICMPV6", 6))
11176                                         ptype_mapping[i].sw_ptype |=
11177                                                 RTE_PTYPE_INNER_L4_ICMP;
11178
11179                                 break;
11180                         }
11181                 }
11182         }
11183
11184         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11185                                                 ptype_num, 0);
11186         if (ret)
11187                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11188
11189         rte_free(ptype_mapping);
11190         rte_free(ptype);
11191         return ret;
11192 }
11193
11194 void
11195 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11196                               uint32_t pkg_size)
11197 {
11198         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11199         uint32_t proto_num;
11200         struct rte_pmd_i40e_proto_info *proto;
11201         uint32_t buff_size;
11202         uint32_t i;
11203         int ret;
11204
11205         /* get information about protocol number */
11206         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11207                                        (uint8_t *)&proto_num, sizeof(proto_num),
11208                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11209         if (ret) {
11210                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11211                 return;
11212         }
11213         if (!proto_num) {
11214                 PMD_DRV_LOG(INFO, "No new protocol added");
11215                 return;
11216         }
11217
11218         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11219         proto = rte_zmalloc("new_proto", buff_size, 0);
11220         if (!proto) {
11221                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11222                 return;
11223         }
11224
11225         /* get information about protocol list */
11226         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11227                                         (uint8_t *)proto, buff_size,
11228                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11229         if (ret) {
11230                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11231                 rte_free(proto);
11232                 return;
11233         }
11234
11235         /* Check if GTP is supported. */
11236         for (i = 0; i < proto_num; i++) {
11237                 if (!strncmp(proto[i].name, "GTP", 3)) {
11238                         pf->gtp_support = true;
11239                         break;
11240                 }
11241         }
11242
11243         /* Update customized pctype info */
11244         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11245                                             proto_num, proto);
11246         if (ret)
11247                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11248
11249         /* Update customized ptype info */
11250         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11251                                            proto_num, proto);
11252         if (ret)
11253                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11254
11255         rte_free(proto);
11256 }
11257
11258 /* Create a QinQ cloud filter
11259  *
11260  * The Fortville NIC has limited resources for tunnel filters,
11261  * so we can only reuse existing filters.
11262  *
11263  * In step 1 we define which Field Vector fields can be used for
11264  * filter types.
11265  * As we do not have the inner tag defined as a field,
11266  * we have to define it first, by reusing one of L1 entries.
11267  *
11268  * In step 2 we are replacing one of existing filter types with
11269  * a new one for QinQ.
11270  * As we reusing L1 and replacing L2, some of the default filter
11271  * types will disappear,which depends on L1 and L2 entries we reuse.
11272  *
11273  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11274  *
11275  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11276  *              later when we define the cloud filter.
11277  *      a.      Valid_flags.replace_cloud = 0
11278  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11279  *      c.      New_filter = 0x10
11280  *      d.      TR bit = 0xff (optional, not used here)
11281  *      e.      Buffer – 2 entries:
11282  *              i.      Byte 0 = 8 (outer vlan FV index).
11283  *                      Byte 1 = 0 (rsv)
11284  *                      Byte 2-3 = 0x0fff
11285  *              ii.     Byte 0 = 37 (inner vlan FV index).
11286  *                      Byte 1 =0 (rsv)
11287  *                      Byte 2-3 = 0x0fff
11288  *
11289  * Step 2:
11290  * 2.   Create cloud filter using two L1 filters entries: stag and
11291  *              new filter(outer vlan+ inner vlan)
11292  *      a.      Valid_flags.replace_cloud = 1
11293  *      b.      Old_filter = 1 (instead of outer IP)
11294  *      c.      New_filter = 0x10
11295  *      d.      Buffer – 2 entries:
11296  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11297  *                      Byte 1-3 = 0 (rsv)
11298  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11299  *                      Byte 9-11 = 0 (rsv)
11300  */
11301 static int
11302 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11303 {
11304         int ret = -ENOTSUP;
11305         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11306         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11307         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11308
11309         /* Init */
11310         memset(&filter_replace, 0,
11311                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11312         memset(&filter_replace_buf, 0,
11313                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11314
11315         /* create L1 filter */
11316         filter_replace.old_filter_type =
11317                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11318         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11319         filter_replace.tr_bit = 0;
11320
11321         /* Prepare the buffer, 2 entries */
11322         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11323         filter_replace_buf.data[0] |=
11324                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11325         /* Field Vector 12b mask */
11326         filter_replace_buf.data[2] = 0xff;
11327         filter_replace_buf.data[3] = 0x0f;
11328         filter_replace_buf.data[4] =
11329                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11330         filter_replace_buf.data[4] |=
11331                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11332         /* Field Vector 12b mask */
11333         filter_replace_buf.data[6] = 0xff;
11334         filter_replace_buf.data[7] = 0x0f;
11335         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11336                         &filter_replace_buf);
11337         if (ret != I40E_SUCCESS)
11338                 return ret;
11339
11340         /* Apply the second L2 cloud filter */
11341         memset(&filter_replace, 0,
11342                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11343         memset(&filter_replace_buf, 0,
11344                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11345
11346         /* create L2 filter, input for L2 filter will be L1 filter  */
11347         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11348         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11349         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11350
11351         /* Prepare the buffer, 2 entries */
11352         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11353         filter_replace_buf.data[0] |=
11354                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11355         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11356         filter_replace_buf.data[4] |=
11357                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11358         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11359                         &filter_replace_buf);
11360         return ret;
11361 }
11362
11363 RTE_INIT(i40e_init_log);
11364 static void
11365 i40e_init_log(void)
11366 {
11367         i40e_logtype_init = rte_log_register("pmd.i40e.init");
11368         if (i40e_logtype_init >= 0)
11369                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11370         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11371         if (i40e_logtype_driver >= 0)
11372                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
11373 }