drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68 #include "rte_pmd_i40e.h"
  69
  70 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  71 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  72
  73 #define I40E_CLEAR_PXE_WAIT_MS     200
  74
  75 /* Maximun number of capability elements */
  76 #define I40E_MAX_CAP_ELE_NUM       128
  77
  78 /* Wait count and interval */
  79 #define I40E_CHK_Q_ENA_COUNT       1000
  80 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  81
  82 /* Maximun number of VSI */
  83 #define I40E_MAX_NUM_VSIS          (384UL)
  84
  85 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  86
  87 /* Flow control default timer */
  88 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  89
  90 /* Flow control enable fwd bit */
  91 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  92
  93 /* Receive Packet Buffer size */
  94 #define I40E_RXPBSIZE (968 * 1024)
  95
  96 /* Kilobytes shift */
  97 #define I40E_KILOSHIFT 10
  98
  99 /* Flow control default high water */
 100 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
 101
 102 /* Flow control default low water */
 103 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
 104
 105 /* Receive Average Packet Size in Byte*/
 106 #define I40E_PACKET_AVERAGE_SIZE 128
 107
 108 /* Mask of PF interrupt causes */
 109 #define I40E_PFINT_ICR0_ENA_MASK ( \
 110                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 112                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 114                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 115                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 118                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 119
 120 #define I40E_FLOW_TYPES ( \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 130         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 131         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 132
 133 /* Additional timesync values. */
 134 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 135 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 136 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 137 #define I40E_PRTTSYN_TSYNENA     0x80000000
 138 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 139 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define I40E_MAX_PERCENT            100
 142 #define I40E_DEFAULT_DCB_APP_NUM    1
 143 #define I40E_DEFAULT_DCB_APP_PRIO   3
 144
 145 /**
 146  * Below are values for writing un-exposed registers suggested
 147  * by silicon experts
 148  */
 149 /* Destination MAC address */
 150 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 151 /* Source MAC address */
 152 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 153 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 154 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 155 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 156 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 157 /* Single VLAN tag in the inner L2 header */
 158 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 159 /* Source IPv4 address */
 160 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 161 /* Destination IPv4 address */
 162 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 163 /* Source IPv4 address for X722 */
 164 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 165 /* Destination IPv4 address for X722 */
 166 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 167 /* IPv4 Protocol for X722 */
 168 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 169 /* IPv4 Time to Live for X722 */
 170 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 171 /* IPv4 Type of Service (TOS) */
 172 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 173 /* IPv4 Protocol */
 174 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 175 /* IPv4 Time to Live */
 176 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 177 /* Source IPv6 address */
 178 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 179 /* Destination IPv6 address */
 180 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 181 /* IPv6 Traffic Class (TC) */
 182 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 183 /* IPv6 Next Header */
 184 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 185 /* IPv6 Hop Limit */
 186 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 187 /* Source L4 port */
 188 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 189 /* Destination L4 port */
 190 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 191 /* SCTP verification tag */
 192 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 193 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 194 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 195 /* Source port of tunneling UDP */
 196 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 197 /* Destination port of tunneling UDP */
 198 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 199 /* UDP Tunneling ID, NVGRE/GRE key */
 200 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 201 /* Last ether type */
 202 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 203 /* Tunneling outer destination IPv4 address */
 204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 205 /* Tunneling outer destination IPv6 address */
 206 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 207 /* 1st word of flex payload */
 208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 209 /* 2nd word of flex payload */
 210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 211 /* 3rd word of flex payload */
 212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 213 /* 4th word of flex payload */
 214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 215 /* 5th word of flex payload */
 216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 217 /* 6th word of flex payload */
 218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 219 /* 7th word of flex payload */
 220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 221 /* 8th word of flex payload */
 222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 223 /* all 8 words flex payload */
 224 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 225 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 226
 227 #define I40E_TRANSLATE_INSET 0
 228 #define I40E_TRANSLATE_REG   1
 229
 230 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 231 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 232 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 233 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 234 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 235 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 236
 237 /* PCI offset for querying capability */
 238 #define PCI_DEV_CAP_REG            0xA4
 239 /* PCI offset for enabling/disabling Extended Tag */
 240 #define PCI_DEV_CTRL_REG           0xA8
 241 /* Bit mask of Extended Tag capability */
 242 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 243 /* Bit shift of Extended Tag enable/disable */
 244 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 245 /* Bit mask of Extended Tag enable/disable */
 246 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 247
 248 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 249 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 250 static int i40e_dev_configure(struct rte_eth_dev *dev);
 251 static int i40e_dev_start(struct rte_eth_dev *dev);
 252 static void i40e_dev_stop(struct rte_eth_dev *dev);
 253 static void i40e_dev_close(struct rte_eth_dev *dev);
 254 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 255 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 256 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 257 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 258 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 259 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 260 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 261 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 262                                struct rte_eth_stats *stats);
 263 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 264                                struct rte_eth_xstat *xstats, unsigned n);
 265 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 266                                      struct rte_eth_xstat_name *xstats_names,
 267                                      unsigned limit);
 268 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 269 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 270                                             uint16_t queue_id,
 271                                             uint8_t stat_idx,
 272                                             uint8_t is_rx);
 273 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 274                                 char *fw_version, size_t fw_size);
 275 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 276                               struct rte_eth_dev_info *dev_info);
 277 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 278                                 uint16_t vlan_id,
 279                                 int on);
 280 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 281                               enum rte_vlan_type vlan_type,
 282                               uint16_t tpid);
 283 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 284 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 285                                       uint16_t queue,
 286                                       int on);
 287 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 288 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 289 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 290 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 291                               struct rte_eth_fc_conf *fc_conf);
 292 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 293                               struct rte_eth_fc_conf *fc_conf);
 294 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 295                                        struct rte_eth_pfc_conf *pfc_conf);
 296 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 297                             struct ether_addr *mac_addr,
 298                             uint32_t index,
 299                             uint32_t pool);
 300 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 301 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 302                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 303                                     uint16_t reta_size);
 304 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 305                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 306                                    uint16_t reta_size);
 307
 308 static int i40e_get_cap(struct i40e_hw *hw);
 309 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 310 static int i40e_pf_setup(struct i40e_pf *pf);
 311 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 312 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 313 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 314 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 315 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 316                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 317 static void i40e_stat_update_48(struct i40e_hw *hw,
 318                                uint32_t hireg,
 319                                uint32_t loreg,
 320                                bool offset_loaded,
 321                                uint64_t *offset,
 322                                uint64_t *stat);
 323 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 324 static void i40e_dev_interrupt_handler(void *param);
 325 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 326                                 uint32_t base, uint32_t num);
 327 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 328 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 329                         uint32_t base);
 330 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 331                         uint16_t num);
 332 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 333 static int i40e_veb_release(struct i40e_veb *veb);
 334 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 335                                                 struct i40e_vsi *vsi);
 336 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 337 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 338 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 339                                              struct i40e_macvlan_filter *mv_f,
 340                                              int num,
 341                                              uint16_t vlan);
 342 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 343 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 344                                     struct rte_eth_rss_conf *rss_conf);
 345 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 346                                       struct rte_eth_rss_conf *rss_conf);
 347 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 348                                         struct rte_eth_udp_tunnel *udp_tunnel);
 349 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 350                                         struct rte_eth_udp_tunnel *udp_tunnel);
 351 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 352 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 353                                 enum rte_filter_op filter_op,
 354                                 void *arg);
 355 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 356                                 enum rte_filter_type filter_type,
 357                                 enum rte_filter_op filter_op,
 358                                 void *arg);
 359 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 360                                   struct rte_eth_dcb_info *dcb_info);
 361 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 362 static void i40e_configure_registers(struct i40e_hw *hw);
 363 static void i40e_hw_init(struct rte_eth_dev *dev);
 364 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 365 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 366                                                      uint16_t seid,
 367                                                      uint16_t rule_type,
 368                                                      uint16_t *entries,
 369                                                      uint16_t count,
 370                                                      uint16_t rule_id);
 371 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 372                         struct rte_eth_mirror_conf *mirror_conf,
 373                         uint8_t sw_id, uint8_t on);
 374 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 375
 376 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 377 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 378 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 379                                            struct timespec *timestamp,
 380                                            uint32_t flags);
 381 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 382                                            struct timespec *timestamp);
 383 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 384
 385 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 386
 387 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 388                                    struct timespec *timestamp);
 389 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 390                                     const struct timespec *timestamp);
 391
 392 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 393                                          uint16_t queue_id);
 394 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 395                                           uint16_t queue_id);
 396
 397 static int i40e_get_regs(struct rte_eth_dev *dev,
 398                          struct rte_dev_reg_info *regs);
 399
 400 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 401
 402 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 403                            struct rte_dev_eeprom_info *eeprom);
 404
 405 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 406                                       struct ether_addr *mac_addr);
 407
 408 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 409
 410 static int i40e_ethertype_filter_convert(
 411         const struct rte_eth_ethertype_filter *input,
 412         struct i40e_ethertype_filter *filter);
 413 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 414                                    struct i40e_ethertype_filter *filter);
 415
 416 static int i40e_tunnel_filter_convert(
 417         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 418         struct i40e_tunnel_filter *tunnel_filter);
 419 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 420                                 struct i40e_tunnel_filter *tunnel_filter);
 421 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 422
 423 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 424 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 425 static void i40e_filter_restore(struct i40e_pf *pf);
 426 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 427
 428 int i40e_logtype_init;
 429 int i40e_logtype_driver;
 430
 431 static const struct rte_pci_id pci_id_i40e_map[] = {
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 445         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 446         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 447         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 448         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 449         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 450         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 451         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 452         { .vendor_id = 0, /* sentinel */ },
 453 };
 454
 455 static const struct eth_dev_ops i40e_eth_dev_ops = {
 456         .dev_configure                = i40e_dev_configure,
 457         .dev_start                    = i40e_dev_start,
 458         .dev_stop                     = i40e_dev_stop,
 459         .dev_close                    = i40e_dev_close,
 460         .dev_reset                    = i40e_dev_reset,
 461         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 462         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 463         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 464         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 465         .dev_set_link_up              = i40e_dev_set_link_up,
 466         .dev_set_link_down            = i40e_dev_set_link_down,
 467         .link_update                  = i40e_dev_link_update,
 468         .stats_get                    = i40e_dev_stats_get,
 469         .xstats_get                   = i40e_dev_xstats_get,
 470         .xstats_get_names             = i40e_dev_xstats_get_names,
 471         .stats_reset                  = i40e_dev_stats_reset,
 472         .xstats_reset                 = i40e_dev_stats_reset,
 473         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 474         .fw_version_get               = i40e_fw_version_get,
 475         .dev_infos_get                = i40e_dev_info_get,
 476         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 477         .vlan_filter_set              = i40e_vlan_filter_set,
 478         .vlan_tpid_set                = i40e_vlan_tpid_set,
 479         .vlan_offload_set             = i40e_vlan_offload_set,
 480         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 481         .vlan_pvid_set                = i40e_vlan_pvid_set,
 482         .rx_queue_start               = i40e_dev_rx_queue_start,
 483         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 484         .tx_queue_start               = i40e_dev_tx_queue_start,
 485         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 486         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 487         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 488         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 489         .rx_queue_release             = i40e_dev_rx_queue_release,
 490         .rx_queue_count               = i40e_dev_rx_queue_count,
 491         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 492         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 493         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 494         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 495         .tx_queue_release             = i40e_dev_tx_queue_release,
 496         .dev_led_on                   = i40e_dev_led_on,
 497         .dev_led_off                  = i40e_dev_led_off,
 498         .flow_ctrl_get                = i40e_flow_ctrl_get,
 499         .flow_ctrl_set                = i40e_flow_ctrl_set,
 500         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 501         .mac_addr_add                 = i40e_macaddr_add,
 502         .mac_addr_remove              = i40e_macaddr_remove,
 503         .reta_update                  = i40e_dev_rss_reta_update,
 504         .reta_query                   = i40e_dev_rss_reta_query,
 505         .rss_hash_update              = i40e_dev_rss_hash_update,
 506         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 507         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 508         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 509         .filter_ctrl                  = i40e_dev_filter_ctrl,
 510         .rxq_info_get                 = i40e_rxq_info_get,
 511         .txq_info_get                 = i40e_txq_info_get,
 512         .mirror_rule_set              = i40e_mirror_rule_set,
 513         .mirror_rule_reset            = i40e_mirror_rule_reset,
 514         .timesync_enable              = i40e_timesync_enable,
 515         .timesync_disable             = i40e_timesync_disable,
 516         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 517         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 518         .get_dcb_info                 = i40e_dev_get_dcb_info,
 519         .timesync_adjust_time         = i40e_timesync_adjust_time,
 520         .timesync_read_time           = i40e_timesync_read_time,
 521         .timesync_write_time          = i40e_timesync_write_time,
 522         .get_reg                      = i40e_get_regs,
 523         .get_eeprom_length            = i40e_get_eeprom_length,
 524         .get_eeprom                   = i40e_get_eeprom,
 525         .mac_addr_set                 = i40e_set_default_mac_addr,
 526         .mtu_set                      = i40e_dev_mtu_set,
 527         .tm_ops_get                   = i40e_tm_ops_get,
 528 };
 529
 530 /* store statistics names and its offset in stats structure */
 531 struct rte_i40e_xstats_name_off {
 532         char name[RTE_ETH_XSTATS_NAME_SIZE];
 533         unsigned offset;
 534 };
 535
 536 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 537         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 538         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 539         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 540         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 541         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 542                 rx_unknown_protocol)},
 543         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 544         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 545         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 546         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 547 };
 548
 549 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 550                 sizeof(rte_i40e_stats_strings[0]))
 551
 552 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 553         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 554                 tx_dropped_link_down)},
 555         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 556         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 557                 illegal_bytes)},
 558         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 559         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 560                 mac_local_faults)},
 561         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 562                 mac_remote_faults)},
 563         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 564                 rx_length_errors)},
 565         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 566         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 567         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 568         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 569         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 570         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 571                 rx_size_127)},
 572         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 573                 rx_size_255)},
 574         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 575                 rx_size_511)},
 576         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 577                 rx_size_1023)},
 578         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 579                 rx_size_1522)},
 580         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 581                 rx_size_big)},
 582         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 583                 rx_undersize)},
 584         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 585                 rx_oversize)},
 586         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 587                 mac_short_packet_dropped)},
 588         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 589                 rx_fragments)},
 590         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 591         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 592         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 593                 tx_size_127)},
 594         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 595                 tx_size_255)},
 596         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 597                 tx_size_511)},
 598         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 599                 tx_size_1023)},
 600         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 601                 tx_size_1522)},
 602         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 603                 tx_size_big)},
 604         {"rx_flow_director_atr_match_packets",
 605                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 606         {"rx_flow_director_sb_match_packets",
 607                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 608         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 609                 tx_lpi_status)},
 610         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 611                 rx_lpi_status)},
 612         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 613                 tx_lpi_count)},
 614         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 615                 rx_lpi_count)},
 616 };
 617
 618 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 619                 sizeof(rte_i40e_hw_port_strings[0]))
 620
 621 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 622         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 623                 priority_xon_rx)},
 624         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 625                 priority_xoff_rx)},
 626 };
 627
 628 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 629                 sizeof(rte_i40e_rxq_prio_strings[0]))
 630
 631 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 632         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 633                 priority_xon_tx)},
 634         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 635                 priority_xoff_tx)},
 636         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 637                 priority_xon_2_xoff)},
 638 };
 639
 640 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 641                 sizeof(rte_i40e_txq_prio_strings[0]))
 642
 643 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 644         struct rte_pci_device *pci_dev)
 645 {
 646         return rte_eth_dev_pci_generic_probe(pci_dev,
 647                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 648 }
 649
 650 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 651 {
 652         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 653 }
 654
 655 static struct rte_pci_driver rte_i40e_pmd = {
 656         .id_table = pci_id_i40e_map,
 657         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 658         .probe = eth_i40e_pci_probe,
 659         .remove = eth_i40e_pci_remove,
 660 };
 661
 662 static inline int
 663 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 664                                      struct rte_eth_link *link)
 665 {
 666         struct rte_eth_link *dst = link;
 667         struct rte_eth_link *src = &(dev->data->dev_link);
 668
 669         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 670                                         *(uint64_t *)src) == 0)
 671                 return -1;
 672
 673         return 0;
 674 }
 675
 676 static inline int
 677 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 678                                       struct rte_eth_link *link)
 679 {
 680         struct rte_eth_link *dst = &(dev->data->dev_link);
 681         struct rte_eth_link *src = link;
 682
 683         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 684                                         *(uint64_t *)src) == 0)
 685                 return -1;
 686
 687         return 0;
 688 }
 689
 690 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 691 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 692 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 693
 694 #ifndef I40E_GLQF_ORT
 695 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 696 #endif
 697 #ifndef I40E_GLQF_PIT
 698 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 699 #endif
 700 #ifndef I40E_GLQF_L3_MAP
 701 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 702 #endif
 703
 704 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 705 {
 706         /*
 707          * Initialize registers for flexible payload, which should be set by NVM.
 708          * This should be removed from code once it is fixed in NVM.
 709          */
 710         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 711         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 712         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 713         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 714         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 715         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 716         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 717         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 718         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 719         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 720         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 721         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 722
 723         /* Initialize registers for parsing packet type of QinQ */
 724         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 725         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 726 }
 727
 728 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 729
 730 /*
 731  * Add a ethertype filter to drop all flow control frames transmitted
 732  * from VSIs.
 733 */
 734 static void
 735 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 736 {
 737         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 738         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 739                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 740                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 741         int ret;
 742
 743         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 744                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 745                                 pf->main_vsi_seid, 0,
 746                                 TRUE, NULL, NULL);
 747         if (ret)
 748                 PMD_INIT_LOG(ERR,
 749                         "Failed to add filter to drop flow control frames from VSIs.");
 750 }
 751
 752 static int
 753 floating_veb_list_handler(__rte_unused const char *key,
 754                           const char *floating_veb_value,
 755                           void *opaque)
 756 {
 757         int idx = 0;
 758         unsigned int count = 0;
 759         char *end = NULL;
 760         int min, max;
 761         bool *vf_floating_veb = opaque;
 762
 763         while (isblank(*floating_veb_value))
 764                 floating_veb_value++;
 765
 766         /* Reset floating VEB configuration for VFs */
 767         for (idx = 0; idx < I40E_MAX_VF; idx++)
 768                 vf_floating_veb[idx] = false;
 769
 770         min = I40E_MAX_VF;
 771         do {
 772                 while (isblank(*floating_veb_value))
 773                         floating_veb_value++;
 774                 if (*floating_veb_value == '\0')
 775                         return -1;
 776                 errno = 0;
 777                 idx = strtoul(floating_veb_value, &end, 10);
 778                 if (errno || end == NULL)
 779                         return -1;
 780                 while (isblank(*end))
 781                         end++;
 782                 if (*end == '-') {
 783                         min = idx;
 784                 } else if ((*end == ';') || (*end == '\0')) {
 785                         max = idx;
 786                         if (min == I40E_MAX_VF)
 787                                 min = idx;
 788                         if (max >= I40E_MAX_VF)
 789                                 max = I40E_MAX_VF - 1;
 790                         for (idx = min; idx <= max; idx++) {
 791                                 vf_floating_veb[idx] = true;
 792                                 count++;
 793                         }
 794                         min = I40E_MAX_VF;
 795                 } else {
 796                         return -1;
 797                 }
 798                 floating_veb_value = end + 1;
 799         } while (*end != '\0');
 800
 801         if (count == 0)
 802                 return -1;
 803
 804         return 0;
 805 }
 806
 807 static void
 808 config_vf_floating_veb(struct rte_devargs *devargs,
 809                        uint16_t floating_veb,
 810                        bool *vf_floating_veb)
 811 {
 812         struct rte_kvargs *kvlist;
 813         int i;
 814         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 815
 816         if (!floating_veb)
 817                 return;
 818         /* All the VFs attach to the floating VEB by default
 819          * when the floating VEB is enabled.
 820          */
 821         for (i = 0; i < I40E_MAX_VF; i++)
 822                 vf_floating_veb[i] = true;
 823
 824         if (devargs == NULL)
 825                 return;
 826
 827         kvlist = rte_kvargs_parse(devargs->args, NULL);
 828         if (kvlist == NULL)
 829                 return;
 830
 831         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 832                 rte_kvargs_free(kvlist);
 833                 return;
 834         }
 835         /* When the floating_veb_list parameter exists, all the VFs
 836          * will attach to the legacy VEB firstly, then configure VFs
 837          * to the floating VEB according to the floating_veb_list.
 838          */
 839         if (rte_kvargs_process(kvlist, floating_veb_list,
 840                                floating_veb_list_handler,
 841                                vf_floating_veb) < 0) {
 842                 rte_kvargs_free(kvlist);
 843                 return;
 844         }
 845         rte_kvargs_free(kvlist);
 846 }
 847
 848 static int
 849 i40e_check_floating_handler(__rte_unused const char *key,
 850                             const char *value,
 851                             __rte_unused void *opaque)
 852 {
 853         if (strcmp(value, "1"))
 854                 return -1;
 855
 856         return 0;
 857 }
 858
 859 static int
 860 is_floating_veb_supported(struct rte_devargs *devargs)
 861 {
 862         struct rte_kvargs *kvlist;
 863         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 864
 865         if (devargs == NULL)
 866                 return 0;
 867
 868         kvlist = rte_kvargs_parse(devargs->args, NULL);
 869         if (kvlist == NULL)
 870                 return 0;
 871
 872         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 873                 rte_kvargs_free(kvlist);
 874                 return 0;
 875         }
 876         /* Floating VEB is enabled when there's key-value:
 877          * enable_floating_veb=1
 878          */
 879         if (rte_kvargs_process(kvlist, floating_veb_key,
 880                                i40e_check_floating_handler, NULL) < 0) {
 881                 rte_kvargs_free(kvlist);
 882                 return 0;
 883         }
 884         rte_kvargs_free(kvlist);
 885
 886         return 1;
 887 }
 888
 889 static void
 890 config_floating_veb(struct rte_eth_dev *dev)
 891 {
 892         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 893         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 894         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 895
 896         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 897
 898         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 899                 pf->floating_veb =
 900                         is_floating_veb_supported(pci_dev->device.devargs);
 901                 config_vf_floating_veb(pci_dev->device.devargs,
 902                                        pf->floating_veb,
 903                                        pf->floating_veb_list);
 904         } else {
 905                 pf->floating_veb = false;
 906         }
 907 }
 908
 909 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 910 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 911
 912 static int
 913 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 914 {
 915         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 916         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 917         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 918         int ret;
 919
 920         struct rte_hash_parameters ethertype_hash_params = {
 921                 .name = ethertype_hash_name,
 922                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 923                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 924                 .hash_func = rte_hash_crc,
 925                 .hash_func_init_val = 0,
 926                 .socket_id = rte_socket_id(),
 927         };
 928
 929         /* Initialize ethertype filter rule list and hash */
 930         TAILQ_INIT(&ethertype_rule->ethertype_list);
 931         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 932                  "ethertype_%s", dev->device->name);
 933         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 934         if (!ethertype_rule->hash_table) {
 935                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 936                 return -EINVAL;
 937         }
 938         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 939                                        sizeof(struct i40e_ethertype_filter *) *
 940                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 941                                        0);
 942         if (!ethertype_rule->hash_map) {
 943                 PMD_INIT_LOG(ERR,
 944                              "Failed to allocate memory for ethertype hash map!");
 945                 ret = -ENOMEM;
 946                 goto err_ethertype_hash_map_alloc;
 947         }
 948
 949         return 0;
 950
 951 err_ethertype_hash_map_alloc:
 952         rte_hash_free(ethertype_rule->hash_table);
 953
 954         return ret;
 955 }
 956
 957 static int
 958 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 959 {
 960         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 961         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 962         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 963         int ret;
 964
 965         struct rte_hash_parameters tunnel_hash_params = {
 966                 .name = tunnel_hash_name,
 967                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 968                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 969                 .hash_func = rte_hash_crc,
 970                 .hash_func_init_val = 0,
 971                 .socket_id = rte_socket_id(),
 972         };
 973
 974         /* Initialize tunnel filter rule list and hash */
 975         TAILQ_INIT(&tunnel_rule->tunnel_list);
 976         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 977                  "tunnel_%s", dev->device->name);
 978         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 979         if (!tunnel_rule->hash_table) {
 980                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 981                 return -EINVAL;
 982         }
 983         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 984                                     sizeof(struct i40e_tunnel_filter *) *
 985                                     I40E_MAX_TUNNEL_FILTER_NUM,
 986                                     0);
 987         if (!tunnel_rule->hash_map) {
 988                 PMD_INIT_LOG(ERR,
 989                              "Failed to allocate memory for tunnel hash map!");
 990                 ret = -ENOMEM;
 991                 goto err_tunnel_hash_map_alloc;
 992         }
 993
 994         return 0;
 995
 996 err_tunnel_hash_map_alloc:
 997         rte_hash_free(tunnel_rule->hash_table);
 998
 999         return ret;
1000 }
1001
1002 static int
1003 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1004 {
1005         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1006         struct i40e_fdir_info *fdir_info = &pf->fdir;
1007         char fdir_hash_name[RTE_HASH_NAMESIZE];
1008         int ret;
1009
1010         struct rte_hash_parameters fdir_hash_params = {
1011                 .name = fdir_hash_name,
1012                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1013                 .key_len = sizeof(struct rte_eth_fdir_input),
1014                 .hash_func = rte_hash_crc,
1015                 .hash_func_init_val = 0,
1016                 .socket_id = rte_socket_id(),
1017         };
1018
1019         /* Initialize flow director filter rule list and hash */
1020         TAILQ_INIT(&fdir_info->fdir_list);
1021         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1022                  "fdir_%s", dev->device->name);
1023         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1024         if (!fdir_info->hash_table) {
1025                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1026                 return -EINVAL;
1027         }
1028         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1029                                           sizeof(struct i40e_fdir_filter *) *
1030                                           I40E_MAX_FDIR_FILTER_NUM,
1031                                           0);
1032         if (!fdir_info->hash_map) {
1033                 PMD_INIT_LOG(ERR,
1034                              "Failed to allocate memory for fdir hash map!");
1035                 ret = -ENOMEM;
1036                 goto err_fdir_hash_map_alloc;
1037         }
1038         return 0;
1039
1040 err_fdir_hash_map_alloc:
1041         rte_hash_free(fdir_info->hash_table);
1042
1043         return ret;
1044 }
1045
1046 static void
1047 i40e_init_customized_info(struct i40e_pf *pf)
1048 {
1049         int i;
1050
1051         /* Initialize customized pctype */
1052         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1053                 pf->customized_pctype[i].index = i;
1054                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1055                 pf->customized_pctype[i].valid = false;
1056         }
1057
1058         pf->gtp_support = false;
1059 }
1060
1061 static int
1062 eth_i40e_dev_init(struct rte_eth_dev *dev)
1063 {
1064         struct rte_pci_device *pci_dev;
1065         struct rte_intr_handle *intr_handle;
1066         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1067         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1068         struct i40e_vsi *vsi;
1069         int ret;
1070         uint32_t len;
1071         uint8_t aq_fail = 0;
1072
1073         PMD_INIT_FUNC_TRACE();
1074
1075         dev->dev_ops = &i40e_eth_dev_ops;
1076         dev->rx_pkt_burst = i40e_recv_pkts;
1077         dev->tx_pkt_burst = i40e_xmit_pkts;
1078         dev->tx_pkt_prepare = i40e_prep_pkts;
1079
1080         /* for secondary processes, we don't initialise any further as primary
1081          * has already done this work. Only check we don't need a different
1082          * RX function */
1083         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1084                 i40e_set_rx_function(dev);
1085                 i40e_set_tx_function(dev);
1086                 return 0;
1087         }
1088         i40e_set_default_ptype_table(dev);
1089         i40e_set_default_pctype_table(dev);
1090         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1091         intr_handle = &pci_dev->intr_handle;
1092
1093         rte_eth_copy_pci_info(dev, pci_dev);
1094         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1095
1096         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1097         pf->adapter->eth_dev = dev;
1098         pf->dev_data = dev->data;
1099
1100         hw->back = I40E_PF_TO_ADAPTER(pf);
1101         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1102         if (!hw->hw_addr) {
1103                 PMD_INIT_LOG(ERR,
1104                         "Hardware is not available, as address is NULL");
1105                 return -ENODEV;
1106         }
1107
1108         hw->vendor_id = pci_dev->id.vendor_id;
1109         hw->device_id = pci_dev->id.device_id;
1110         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1111         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1112         hw->bus.device = pci_dev->addr.devid;
1113         hw->bus.func = pci_dev->addr.function;
1114         hw->adapter_stopped = 0;
1115
1116         /* Make sure all is clean before doing PF reset */
1117         i40e_clear_hw(hw);
1118
1119         /* Initialize the hardware */
1120         i40e_hw_init(dev);
1121
1122         /* Reset here to make sure all is clean for each PF */
1123         ret = i40e_pf_reset(hw);
1124         if (ret) {
1125                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1126                 return ret;
1127         }
1128
1129         /* Initialize the shared code (base driver) */
1130         ret = i40e_init_shared_code(hw);
1131         if (ret) {
1132                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1133                 return ret;
1134         }
1135
1136         /*
1137          * To work around the NVM issue, initialize registers
1138          * for flexible payload and packet type of QinQ by
1139          * software. It should be removed once issues are fixed
1140          * in NVM.
1141          */
1142         i40e_GLQF_reg_init(hw);
1143
1144         /* Initialize the input set for filters (hash and fd) to default value */
1145         i40e_filter_input_set_init(pf);
1146
1147         /* Initialize the parameters for adminq */
1148         i40e_init_adminq_parameter(hw);
1149         ret = i40e_init_adminq(hw);
1150         if (ret != I40E_SUCCESS) {
1151                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1152                 return -EIO;
1153         }
1154         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1155                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1156                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1157                      ((hw->nvm.version >> 12) & 0xf),
1158                      ((hw->nvm.version >> 4) & 0xff),
1159                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1160
1161         /* initialise the L3_MAP register */
1162         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1163                                    0x00000028,  NULL);
1164         if (ret)
1165                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1166
1167         /* Need the special FW version to support floating VEB */
1168         config_floating_veb(dev);
1169         /* Clear PXE mode */
1170         i40e_clear_pxe_mode(hw);
1171         i40e_dev_sync_phy_type(hw);
1172
1173         /*
1174          * On X710, performance number is far from the expectation on recent
1175          * firmware versions. The fix for this issue may not be integrated in
1176          * the following firmware version. So the workaround in software driver
1177          * is needed. It needs to modify the initial values of 3 internal only
1178          * registers. Note that the workaround can be removed when it is fixed
1179          * in firmware in the future.
1180          */
1181         i40e_configure_registers(hw);
1182
1183         /* Get hw capabilities */
1184         ret = i40e_get_cap(hw);
1185         if (ret != I40E_SUCCESS) {
1186                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1187                 goto err_get_capabilities;
1188         }
1189
1190         /* Initialize parameters for PF */
1191         ret = i40e_pf_parameter_init(dev);
1192         if (ret != 0) {
1193                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1194                 goto err_parameter_init;
1195         }
1196
1197         /* Initialize the queue management */
1198         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1199         if (ret < 0) {
1200                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1201                 goto err_qp_pool_init;
1202         }
1203         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1204                                 hw->func_caps.num_msix_vectors - 1);
1205         if (ret < 0) {
1206                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1207                 goto err_msix_pool_init;
1208         }
1209
1210         /* Initialize lan hmc */
1211         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1212                                 hw->func_caps.num_rx_qp, 0, 0);
1213         if (ret != I40E_SUCCESS) {
1214                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1215                 goto err_init_lan_hmc;
1216         }
1217
1218         /* Configure lan hmc */
1219         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1220         if (ret != I40E_SUCCESS) {
1221                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1222                 goto err_configure_lan_hmc;
1223         }
1224
1225         /* Get and check the mac address */
1226         i40e_get_mac_addr(hw, hw->mac.addr);
1227         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1228                 PMD_INIT_LOG(ERR, "mac address is not valid");
1229                 ret = -EIO;
1230                 goto err_get_mac_addr;
1231         }
1232         /* Copy the permanent MAC address */
1233         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1234                         (struct ether_addr *) hw->mac.perm_addr);
1235
1236         /* Disable flow control */
1237         hw->fc.requested_mode = I40E_FC_NONE;
1238         i40e_set_fc(hw, &aq_fail, TRUE);
1239
1240         /* Set the global registers with default ether type value */
1241         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1242         if (ret != I40E_SUCCESS) {
1243                 PMD_INIT_LOG(ERR,
1244                         "Failed to set the default outer VLAN ether type");
1245                 goto err_setup_pf_switch;
1246         }
1247
1248         /* PF setup, which includes VSI setup */
1249         ret = i40e_pf_setup(pf);
1250         if (ret) {
1251                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1252                 goto err_setup_pf_switch;
1253         }
1254
1255         /* reset all stats of the device, including pf and main vsi */
1256         i40e_dev_stats_reset(dev);
1257
1258         vsi = pf->main_vsi;
1259
1260         /* Disable double vlan by default */
1261         i40e_vsi_config_double_vlan(vsi, FALSE);
1262
1263         /* Disable S-TAG identification when floating_veb is disabled */
1264         if (!pf->floating_veb) {
1265                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1266                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1267                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1268                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1269                 }
1270         }
1271
1272         if (!vsi->max_macaddrs)
1273                 len = ETHER_ADDR_LEN;
1274         else
1275                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1276
1277         /* Should be after VSI initialized */
1278         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1279         if (!dev->data->mac_addrs) {
1280                 PMD_INIT_LOG(ERR,
1281                         "Failed to allocated memory for storing mac address");
1282                 goto err_mac_alloc;
1283         }
1284         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1285                                         &dev->data->mac_addrs[0]);
1286
1287         /* Init dcb to sw mode by default */
1288         ret = i40e_dcb_init_configure(dev, TRUE);
1289         if (ret != I40E_SUCCESS) {
1290                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1291                 pf->flags &= ~I40E_FLAG_DCB;
1292         }
1293         /* Update HW struct after DCB configuration */
1294         i40e_get_cap(hw);
1295
1296         /* initialize pf host driver to setup SRIOV resource if applicable */
1297         i40e_pf_host_init(dev);
1298
1299         /* register callback func to eal lib */
1300         rte_intr_callback_register(intr_handle,
1301                                    i40e_dev_interrupt_handler, dev);
1302
1303         /* configure and enable device interrupt */
1304         i40e_pf_config_irq0(hw, TRUE);
1305         i40e_pf_enable_irq0(hw);
1306
1307         /* enable uio intr after callback register */
1308         rte_intr_enable(intr_handle);
1309         /*
1310          * Add an ethertype filter to drop all flow control frames transmitted
1311          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1312          * frames to wire.
1313          */
1314         i40e_add_tx_flow_control_drop_filter(pf);
1315
1316         /* Set the max frame size to 0x2600 by default,
1317          * in case other drivers changed the default value.
1318          */
1319         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1320
1321         /* initialize mirror rule list */
1322         TAILQ_INIT(&pf->mirror_list);
1323
1324         /* initialize Traffic Manager configuration */
1325         i40e_tm_conf_init(dev);
1326
1327         /* Initialize customized information */
1328         i40e_init_customized_info(pf);
1329
1330         ret = i40e_init_ethtype_filter_list(dev);
1331         if (ret < 0)
1332                 goto err_init_ethtype_filter_list;
1333         ret = i40e_init_tunnel_filter_list(dev);
1334         if (ret < 0)
1335                 goto err_init_tunnel_filter_list;
1336         ret = i40e_init_fdir_filter_list(dev);
1337         if (ret < 0)
1338                 goto err_init_fdir_filter_list;
1339
1340         return 0;
1341
1342 err_init_fdir_filter_list:
1343         rte_free(pf->tunnel.hash_table);
1344         rte_free(pf->tunnel.hash_map);
1345 err_init_tunnel_filter_list:
1346         rte_free(pf->ethertype.hash_table);
1347         rte_free(pf->ethertype.hash_map);
1348 err_init_ethtype_filter_list:
1349         rte_free(dev->data->mac_addrs);
1350 err_mac_alloc:
1351         i40e_vsi_release(pf->main_vsi);
1352 err_setup_pf_switch:
1353 err_get_mac_addr:
1354 err_configure_lan_hmc:
1355         (void)i40e_shutdown_lan_hmc(hw);
1356 err_init_lan_hmc:
1357         i40e_res_pool_destroy(&pf->msix_pool);
1358 err_msix_pool_init:
1359         i40e_res_pool_destroy(&pf->qp_pool);
1360 err_qp_pool_init:
1361 err_parameter_init:
1362 err_get_capabilities:
1363         (void)i40e_shutdown_adminq(hw);
1364
1365         return ret;
1366 }
1367
1368 static void
1369 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1370 {
1371         struct i40e_ethertype_filter *p_ethertype;
1372         struct i40e_ethertype_rule *ethertype_rule;
1373
1374         ethertype_rule = &pf->ethertype;
1375         /* Remove all ethertype filter rules and hash */
1376         if (ethertype_rule->hash_map)
1377                 rte_free(ethertype_rule->hash_map);
1378         if (ethertype_rule->hash_table)
1379                 rte_hash_free(ethertype_rule->hash_table);
1380
1381         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1382                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1383                              p_ethertype, rules);
1384                 rte_free(p_ethertype);
1385         }
1386 }
1387
1388 static void
1389 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1390 {
1391         struct i40e_tunnel_filter *p_tunnel;
1392         struct i40e_tunnel_rule *tunnel_rule;
1393
1394         tunnel_rule = &pf->tunnel;
1395         /* Remove all tunnel director rules and hash */
1396         if (tunnel_rule->hash_map)
1397                 rte_free(tunnel_rule->hash_map);
1398         if (tunnel_rule->hash_table)
1399                 rte_hash_free(tunnel_rule->hash_table);
1400
1401         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1402                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1403                 rte_free(p_tunnel);
1404         }
1405 }
1406
1407 static void
1408 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1409 {
1410         struct i40e_fdir_filter *p_fdir;
1411         struct i40e_fdir_info *fdir_info;
1412
1413         fdir_info = &pf->fdir;
1414         /* Remove all flow director rules and hash */
1415         if (fdir_info->hash_map)
1416                 rte_free(fdir_info->hash_map);
1417         if (fdir_info->hash_table)
1418                 rte_hash_free(fdir_info->hash_table);
1419
1420         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1421                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1422                 rte_free(p_fdir);
1423         }
1424 }
1425
1426 static int
1427 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1428 {
1429         struct i40e_pf *pf;
1430         struct rte_pci_device *pci_dev;
1431         struct rte_intr_handle *intr_handle;
1432         struct i40e_hw *hw;
1433         struct i40e_filter_control_settings settings;
1434         struct rte_flow *p_flow;
1435         int ret;
1436         uint8_t aq_fail = 0;
1437
1438         PMD_INIT_FUNC_TRACE();
1439
1440         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1441                 return 0;
1442
1443         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1444         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1445         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1446         intr_handle = &pci_dev->intr_handle;
1447
1448         if (hw->adapter_stopped == 0)
1449                 i40e_dev_close(dev);
1450
1451         dev->dev_ops = NULL;
1452         dev->rx_pkt_burst = NULL;
1453         dev->tx_pkt_burst = NULL;
1454
1455         /* Clear PXE mode */
1456         i40e_clear_pxe_mode(hw);
1457
1458         /* Unconfigure filter control */
1459         memset(&settings, 0, sizeof(settings));
1460         ret = i40e_set_filter_control(hw, &settings);
1461         if (ret)
1462                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1463                                         ret);
1464
1465         /* Disable flow control */
1466         hw->fc.requested_mode = I40E_FC_NONE;
1467         i40e_set_fc(hw, &aq_fail, TRUE);
1468
1469         /* uninitialize pf host driver */
1470         i40e_pf_host_uninit(dev);
1471
1472         rte_free(dev->data->mac_addrs);
1473         dev->data->mac_addrs = NULL;
1474
1475         /* disable uio intr before callback unregister */
1476         rte_intr_disable(intr_handle);
1477
1478         /* register callback func to eal lib */
1479         rte_intr_callback_unregister(intr_handle,
1480                                      i40e_dev_interrupt_handler, dev);
1481
1482         i40e_rm_ethtype_filter_list(pf);
1483         i40e_rm_tunnel_filter_list(pf);
1484         i40e_rm_fdir_filter_list(pf);
1485
1486         /* Remove all flows */
1487         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1488                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1489                 rte_free(p_flow);
1490         }
1491
1492         /* Remove all Traffic Manager configuration */
1493         i40e_tm_conf_uninit(dev);
1494
1495         return 0;
1496 }
1497
1498 static int
1499 i40e_dev_configure(struct rte_eth_dev *dev)
1500 {
1501         struct i40e_adapter *ad =
1502                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1503         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1504         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1505         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1506         int i, ret;
1507
1508         ret = i40e_dev_sync_phy_type(hw);
1509         if (ret)
1510                 return ret;
1511
1512         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1513          * bulk allocation or vector Rx preconditions we will reset it.
1514          */
1515         ad->rx_bulk_alloc_allowed = true;
1516         ad->rx_vec_allowed = true;
1517         ad->tx_simple_allowed = true;
1518         ad->tx_vec_allowed = true;
1519
1520         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1521                 ret = i40e_fdir_setup(pf);
1522                 if (ret != I40E_SUCCESS) {
1523                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1524                         return -ENOTSUP;
1525                 }
1526                 ret = i40e_fdir_configure(dev);
1527                 if (ret < 0) {
1528                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1529                         goto err;
1530                 }
1531         } else
1532                 i40e_fdir_teardown(pf);
1533
1534         ret = i40e_dev_init_vlan(dev);
1535         if (ret < 0)
1536                 goto err;
1537
1538         /* VMDQ setup.
1539          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1540          *  RSS setting have different requirements.
1541          *  General PMD driver call sequence are NIC init, configure,
1542          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1543          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1544          *  applicable. So, VMDQ setting has to be done before
1545          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1546          *  For RSS setting, it will try to calculate actual configured RX queue
1547          *  number, which will be available after rx_queue_setup(). dev_start()
1548          *  function is good to place RSS setup.
1549          */
1550         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1551                 ret = i40e_vmdq_setup(dev);
1552                 if (ret)
1553                         goto err;
1554         }
1555
1556         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1557                 ret = i40e_dcb_setup(dev);
1558                 if (ret) {
1559                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1560                         goto err_dcb;
1561                 }
1562         }
1563
1564         TAILQ_INIT(&pf->flow_list);
1565
1566         return 0;
1567
1568 err_dcb:
1569         /* need to release vmdq resource if exists */
1570         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1571                 i40e_vsi_release(pf->vmdq[i].vsi);
1572                 pf->vmdq[i].vsi = NULL;
1573         }
1574         rte_free(pf->vmdq);
1575         pf->vmdq = NULL;
1576 err:
1577         /* need to release fdir resource if exists */
1578         i40e_fdir_teardown(pf);
1579         return ret;
1580 }
1581
1582 void
1583 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1584 {
1585         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1586         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1587         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1588         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1589         uint16_t msix_vect = vsi->msix_intr;
1590         uint16_t i;
1591
1592         for (i = 0; i < vsi->nb_qps; i++) {
1593                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1594                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1595                 rte_wmb();
1596         }
1597
1598         if (vsi->type != I40E_VSI_SRIOV) {
1599                 if (!rte_intr_allow_others(intr_handle)) {
1600                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1601                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1602                         I40E_WRITE_REG(hw,
1603                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1604                                        0);
1605                 } else {
1606                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1607                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1608                         I40E_WRITE_REG(hw,
1609                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1610                                                        msix_vect - 1), 0);
1611                 }
1612         } else {
1613                 uint32_t reg;
1614                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1615                         vsi->user_param + (msix_vect - 1);
1616
1617                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1618                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1619         }
1620         I40E_WRITE_FLUSH(hw);
1621 }
1622
1623 static void
1624 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1625                        int base_queue, int nb_queue,
1626                        uint16_t itr_idx)
1627 {
1628         int i;
1629         uint32_t val;
1630         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1631
1632         /* Bind all RX queues to allocated MSIX interrupt */
1633         for (i = 0; i < nb_queue; i++) {
1634                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1635                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1636                         ((base_queue + i + 1) <<
1637                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1638                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1639                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1640
1641                 if (i == nb_queue - 1)
1642                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1643                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1644         }
1645
1646         /* Write first RX queue to Link list register as the head element */
1647         if (vsi->type != I40E_VSI_SRIOV) {
1648                 uint16_t interval =
1649                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1650
1651                 if (msix_vect == I40E_MISC_VEC_ID) {
1652                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1653                                        (base_queue <<
1654                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1655                                        (0x0 <<
1656                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1657                         I40E_WRITE_REG(hw,
1658                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1659                                        interval);
1660                 } else {
1661                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1662                                        (base_queue <<
1663                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1664                                        (0x0 <<
1665                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1666                         I40E_WRITE_REG(hw,
1667                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1668                                                        msix_vect - 1),
1669                                        interval);
1670                 }
1671         } else {
1672                 uint32_t reg;
1673
1674                 if (msix_vect == I40E_MISC_VEC_ID) {
1675                         I40E_WRITE_REG(hw,
1676                                        I40E_VPINT_LNKLST0(vsi->user_param),
1677                                        (base_queue <<
1678                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1679                                        (0x0 <<
1680                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1681                 } else {
1682                         /* num_msix_vectors_vf needs to minus irq0 */
1683                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1684                                 vsi->user_param + (msix_vect - 1);
1685
1686                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1687                                        (base_queue <<
1688                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1689                                        (0x0 <<
1690                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1691                 }
1692         }
1693
1694         I40E_WRITE_FLUSH(hw);
1695 }
1696
1697 void
1698 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1699 {
1700         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1701         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1702         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1703         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1704         uint16_t msix_vect = vsi->msix_intr;
1705         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1706         uint16_t queue_idx = 0;
1707         int record = 0;
1708         uint32_t val;
1709         int i;
1710
1711         for (i = 0; i < vsi->nb_qps; i++) {
1712                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1713                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1714         }
1715
1716         /* INTENA flag is not auto-cleared for interrupt */
1717         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1718         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1719                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1720                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1721         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1722
1723         /* VF bind interrupt */
1724         if (vsi->type == I40E_VSI_SRIOV) {
1725                 __vsi_queues_bind_intr(vsi, msix_vect,
1726                                        vsi->base_queue, vsi->nb_qps,
1727                                        itr_idx);
1728                 return;
1729         }
1730
1731         /* PF & VMDq bind interrupt */
1732         if (rte_intr_dp_is_en(intr_handle)) {
1733                 if (vsi->type == I40E_VSI_MAIN) {
1734                         queue_idx = 0;
1735                         record = 1;
1736                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1737                         struct i40e_vsi *main_vsi =
1738                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1739                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1740                         record = 1;
1741                 }
1742         }
1743
1744         for (i = 0; i < vsi->nb_used_qps; i++) {
1745                 if (nb_msix <= 1) {
1746                         if (!rte_intr_allow_others(intr_handle))
1747                                 /* allow to share MISC_VEC_ID */
1748                                 msix_vect = I40E_MISC_VEC_ID;
1749
1750                         /* no enough msix_vect, map all to one */
1751                         __vsi_queues_bind_intr(vsi, msix_vect,
1752                                                vsi->base_queue + i,
1753                                                vsi->nb_used_qps - i,
1754                                                itr_idx);
1755                         for (; !!record && i < vsi->nb_used_qps; i++)
1756                                 intr_handle->intr_vec[queue_idx + i] =
1757                                         msix_vect;
1758                         break;
1759                 }
1760                 /* 1:1 queue/msix_vect mapping */
1761                 __vsi_queues_bind_intr(vsi, msix_vect,
1762                                        vsi->base_queue + i, 1,
1763                                        itr_idx);
1764                 if (!!record)
1765                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1766
1767                 msix_vect++;
1768                 nb_msix--;
1769         }
1770 }
1771
1772 static void
1773 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1774 {
1775         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1776         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1777         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1778         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1779         uint16_t interval = i40e_calc_itr_interval(\
1780                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1781         uint16_t msix_intr, i;
1782
1783         if (rte_intr_allow_others(intr_handle))
1784                 for (i = 0; i < vsi->nb_msix; i++) {
1785                         msix_intr = vsi->msix_intr + i;
1786                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1787                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1788                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1789                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1790                                 (interval <<
1791                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1792                 }
1793         else
1794                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1795                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1796                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1797                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1798                                (interval <<
1799                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1800
1801         I40E_WRITE_FLUSH(hw);
1802 }
1803
1804 static void
1805 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1806 {
1807         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1808         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1809         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1810         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1811         uint16_t msix_intr, i;
1812
1813         if (rte_intr_allow_others(intr_handle))
1814                 for (i = 0; i < vsi->nb_msix; i++) {
1815                         msix_intr = vsi->msix_intr + i;
1816                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1817                                        0);
1818                 }
1819         else
1820                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1821
1822         I40E_WRITE_FLUSH(hw);
1823 }
1824
1825 static inline uint8_t
1826 i40e_parse_link_speeds(uint16_t link_speeds)
1827 {
1828         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1829
1830         if (link_speeds & ETH_LINK_SPEED_40G)
1831                 link_speed |= I40E_LINK_SPEED_40GB;
1832         if (link_speeds & ETH_LINK_SPEED_25G)
1833                 link_speed |= I40E_LINK_SPEED_25GB;
1834         if (link_speeds & ETH_LINK_SPEED_20G)
1835                 link_speed |= I40E_LINK_SPEED_20GB;
1836         if (link_speeds & ETH_LINK_SPEED_10G)
1837                 link_speed |= I40E_LINK_SPEED_10GB;
1838         if (link_speeds & ETH_LINK_SPEED_1G)
1839                 link_speed |= I40E_LINK_SPEED_1GB;
1840         if (link_speeds & ETH_LINK_SPEED_100M)
1841                 link_speed |= I40E_LINK_SPEED_100MB;
1842
1843         return link_speed;
1844 }
1845
1846 static int
1847 i40e_phy_conf_link(struct i40e_hw *hw,
1848                    uint8_t abilities,
1849                    uint8_t force_speed,
1850                    bool is_up)
1851 {
1852         enum i40e_status_code status;
1853         struct i40e_aq_get_phy_abilities_resp phy_ab;
1854         struct i40e_aq_set_phy_config phy_conf;
1855         enum i40e_aq_phy_type cnt;
1856         uint32_t phy_type_mask = 0;
1857
1858         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1859                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1860                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1861                         I40E_AQ_PHY_FLAG_LOW_POWER;
1862         const uint8_t advt = I40E_LINK_SPEED_40GB |
1863                         I40E_LINK_SPEED_25GB |
1864                         I40E_LINK_SPEED_10GB |
1865                         I40E_LINK_SPEED_1GB |
1866                         I40E_LINK_SPEED_100MB;
1867         int ret = -ENOTSUP;
1868
1869
1870         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1871                                               NULL);
1872         if (status)
1873                 return ret;
1874
1875         /* If link already up, no need to set up again */
1876         if (is_up && phy_ab.phy_type != 0)
1877                 return I40E_SUCCESS;
1878
1879         memset(&phy_conf, 0, sizeof(phy_conf));
1880
1881         /* bits 0-2 use the values from get_phy_abilities_resp */
1882         abilities &= ~mask;
1883         abilities |= phy_ab.abilities & mask;
1884
1885         /* update ablities and speed */
1886         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1887                 phy_conf.link_speed = advt;
1888         else
1889                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1890
1891         phy_conf.abilities = abilities;
1892
1893
1894
1895         /* To enable link, phy_type mask needs to include each type */
1896         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1897                 phy_type_mask |= 1 << cnt;
1898
1899         /* use get_phy_abilities_resp value for the rest */
1900         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1901         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1902                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1903                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1904         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1905         phy_conf.eee_capability = phy_ab.eee_capability;
1906         phy_conf.eeer = phy_ab.eeer_val;
1907         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1908
1909         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1910                     phy_ab.abilities, phy_ab.link_speed);
1911         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1912                     phy_conf.abilities, phy_conf.link_speed);
1913
1914         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1915         if (status)
1916                 return ret;
1917
1918         return I40E_SUCCESS;
1919 }
1920
1921 static int
1922 i40e_apply_link_speed(struct rte_eth_dev *dev)
1923 {
1924         uint8_t speed;
1925         uint8_t abilities = 0;
1926         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1927         struct rte_eth_conf *conf = &dev->data->dev_conf;
1928
1929         speed = i40e_parse_link_speeds(conf->link_speeds);
1930         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1931         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1932                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1933         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1934
1935         return i40e_phy_conf_link(hw, abilities, speed, true);
1936 }
1937
1938 static int
1939 i40e_dev_start(struct rte_eth_dev *dev)
1940 {
1941         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1942         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1943         struct i40e_vsi *main_vsi = pf->main_vsi;
1944         int ret, i;
1945         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1946         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1947         uint32_t intr_vector = 0;
1948         struct i40e_vsi *vsi;
1949
1950         hw->adapter_stopped = 0;
1951
1952         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1953                 PMD_INIT_LOG(ERR,
1954                 "Invalid link_speeds for port %u, autonegotiation disabled",
1955                               dev->data->port_id);
1956                 return -EINVAL;
1957         }
1958
1959         rte_intr_disable(intr_handle);
1960
1961         if ((rte_intr_cap_multiple(intr_handle) ||
1962              !RTE_ETH_DEV_SRIOV(dev).active) &&
1963             dev->data->dev_conf.intr_conf.rxq != 0) {
1964                 intr_vector = dev->data->nb_rx_queues;
1965                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1966                 if (ret)
1967                         return ret;
1968         }
1969
1970         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1971                 intr_handle->intr_vec =
1972                         rte_zmalloc("intr_vec",
1973                                     dev->data->nb_rx_queues * sizeof(int),
1974                                     0);
1975                 if (!intr_handle->intr_vec) {
1976                         PMD_INIT_LOG(ERR,
1977                                 "Failed to allocate %d rx_queues intr_vec",
1978                                 dev->data->nb_rx_queues);
1979                         return -ENOMEM;
1980                 }
1981         }
1982
1983         /* Initialize VSI */
1984         ret = i40e_dev_rxtx_init(pf);
1985         if (ret != I40E_SUCCESS) {
1986                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1987                 goto err_up;
1988         }
1989
1990         /* Map queues with MSIX interrupt */
1991         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1992                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1993         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1994         i40e_vsi_enable_queues_intr(main_vsi);
1995
1996         /* Map VMDQ VSI queues with MSIX interrupt */
1997         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1998                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1999                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2000                                           I40E_ITR_INDEX_DEFAULT);
2001                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2002         }
2003
2004         /* enable FDIR MSIX interrupt */
2005         if (pf->fdir.fdir_vsi) {
2006                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2007                                           I40E_ITR_INDEX_NONE);
2008                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2009         }
2010
2011         /* Enable all queues which have been configured */
2012         ret = i40e_dev_switch_queues(pf, TRUE);
2013         if (ret != I40E_SUCCESS) {
2014                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2015                 goto err_up;
2016         }
2017
2018         /* Enable receiving broadcast packets */
2019         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2020         if (ret != I40E_SUCCESS)
2021                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2022
2023         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2024                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2025                                                 true, NULL);
2026                 if (ret != I40E_SUCCESS)
2027                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2028         }
2029
2030         /* Enable the VLAN promiscuous mode. */
2031         if (pf->vfs) {
2032                 for (i = 0; i < pf->vf_num; i++) {
2033                         vsi = pf->vfs[i].vsi;
2034                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2035                                                      true, NULL);
2036                 }
2037         }
2038
2039         /* Apply link configure */
2040         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2041                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2042                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2043                                 ETH_LINK_SPEED_40G)) {
2044                 PMD_DRV_LOG(ERR, "Invalid link setting");
2045                 goto err_up;
2046         }
2047         ret = i40e_apply_link_speed(dev);
2048         if (I40E_SUCCESS != ret) {
2049                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2050                 goto err_up;
2051         }
2052
2053         if (!rte_intr_allow_others(intr_handle)) {
2054                 rte_intr_callback_unregister(intr_handle,
2055                                              i40e_dev_interrupt_handler,
2056                                              (void *)dev);
2057                 /* configure and enable device interrupt */
2058                 i40e_pf_config_irq0(hw, FALSE);
2059                 i40e_pf_enable_irq0(hw);
2060
2061                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2062                         PMD_INIT_LOG(INFO,
2063                                 "lsc won't enable because of no intr multiplex");
2064         } else {
2065                 ret = i40e_aq_set_phy_int_mask(hw,
2066                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2067                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2068                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2069                 if (ret != I40E_SUCCESS)
2070                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2071
2072                 /* Call get_link_info aq commond to enable/disable LSE */
2073                 i40e_dev_link_update(dev, 0);
2074         }
2075
2076         /* enable uio intr after callback register */
2077         rte_intr_enable(intr_handle);
2078
2079         i40e_filter_restore(pf);
2080
2081         if (pf->tm_conf.root && !pf->tm_conf.committed)
2082                 PMD_DRV_LOG(WARNING,
2083                             "please call hierarchy_commit() "
2084                             "before starting the port");
2085
2086         return I40E_SUCCESS;
2087
2088 err_up:
2089         i40e_dev_switch_queues(pf, FALSE);
2090         i40e_dev_clear_queues(dev);
2091
2092         return ret;
2093 }
2094
2095 static void
2096 i40e_dev_stop(struct rte_eth_dev *dev)
2097 {
2098         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2099         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100         struct i40e_vsi *main_vsi = pf->main_vsi;
2101         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2102         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2103         int i;
2104
2105         if (hw->adapter_stopped == 1)
2106                 return;
2107         /* Disable all queues */
2108         i40e_dev_switch_queues(pf, FALSE);
2109
2110         /* un-map queues with interrupt registers */
2111         i40e_vsi_disable_queues_intr(main_vsi);
2112         i40e_vsi_queues_unbind_intr(main_vsi);
2113
2114         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2115                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2116                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2117         }
2118
2119         if (pf->fdir.fdir_vsi) {
2120                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2121                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2122         }
2123         /* Clear all queues and release memory */
2124         i40e_dev_clear_queues(dev);
2125
2126         /* Set link down */
2127         i40e_dev_set_link_down(dev);
2128
2129         if (!rte_intr_allow_others(intr_handle))
2130                 /* resume to the default handler */
2131                 rte_intr_callback_register(intr_handle,
2132                                            i40e_dev_interrupt_handler,
2133                                            (void *)dev);
2134
2135         /* Clean datapath event and queue/vec mapping */
2136         rte_intr_efd_disable(intr_handle);
2137         if (intr_handle->intr_vec) {
2138                 rte_free(intr_handle->intr_vec);
2139                 intr_handle->intr_vec = NULL;
2140         }
2141
2142         /* reset hierarchy commit */
2143         pf->tm_conf.committed = false;
2144
2145         hw->adapter_stopped = 1;
2146 }
2147
2148 static void
2149 i40e_dev_close(struct rte_eth_dev *dev)
2150 {
2151         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2152         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2153         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2154         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2155         struct i40e_mirror_rule *p_mirror;
2156         uint32_t reg;
2157         int i;
2158         int ret;
2159
2160         PMD_INIT_FUNC_TRACE();
2161
2162         i40e_dev_stop(dev);
2163
2164         /* Remove all mirror rules */
2165         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2166                 ret = i40e_aq_del_mirror_rule(hw,
2167                                               pf->main_vsi->veb->seid,
2168                                               p_mirror->rule_type,
2169                                               p_mirror->entries,
2170                                               p_mirror->num_entries,
2171                                               p_mirror->id);
2172                 if (ret < 0)
2173                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2174                                     "status = %d, aq_err = %d.", ret,
2175                                     hw->aq.asq_last_status);
2176
2177                 /* remove mirror software resource anyway */
2178                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2179                 rte_free(p_mirror);
2180                 pf->nb_mirror_rule--;
2181         }
2182
2183         i40e_dev_free_queues(dev);
2184
2185         /* Disable interrupt */
2186         i40e_pf_disable_irq0(hw);
2187         rte_intr_disable(intr_handle);
2188
2189         /* shutdown and destroy the HMC */
2190         i40e_shutdown_lan_hmc(hw);
2191
2192         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2193                 i40e_vsi_release(pf->vmdq[i].vsi);
2194                 pf->vmdq[i].vsi = NULL;
2195         }
2196         rte_free(pf->vmdq);
2197         pf->vmdq = NULL;
2198
2199         /* release all the existing VSIs and VEBs */
2200         i40e_fdir_teardown(pf);
2201         i40e_vsi_release(pf->main_vsi);
2202
2203         /* shutdown the adminq */
2204         i40e_aq_queue_shutdown(hw, true);
2205         i40e_shutdown_adminq(hw);
2206
2207         i40e_res_pool_destroy(&pf->qp_pool);
2208         i40e_res_pool_destroy(&pf->msix_pool);
2209
2210         /* force a PF reset to clean anything leftover */
2211         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2212         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2213                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2214         I40E_WRITE_FLUSH(hw);
2215 }
2216
2217 /*
2218  * Reset PF device only to re-initialize resources in PMD layer
2219  */
2220 static int
2221 i40e_dev_reset(struct rte_eth_dev *dev)
2222 {
2223         int ret;
2224
2225         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2226          * its VF to make them align with it. The detailed notification
2227          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2228          * To avoid unexpected behavior in VF, currently reset of PF with
2229          * SR-IOV activation is not supported. It might be supported later.
2230          */
2231         if (dev->data->sriov.active)
2232                 return -ENOTSUP;
2233
2234         ret = eth_i40e_dev_uninit(dev);
2235         if (ret)
2236                 return ret;
2237
2238         ret = eth_i40e_dev_init(dev);
2239
2240         return ret;
2241 }
2242
2243 static void
2244 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2245 {
2246         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2247         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2248         struct i40e_vsi *vsi = pf->main_vsi;
2249         int status;
2250
2251         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2252                                                      true, NULL, true);
2253         if (status != I40E_SUCCESS)
2254                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2255
2256         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2257                                                         TRUE, NULL);
2258         if (status != I40E_SUCCESS)
2259                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2260
2261 }
2262
2263 static void
2264 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2265 {
2266         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2267         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2268         struct i40e_vsi *vsi = pf->main_vsi;
2269         int status;
2270
2271         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2272                                                      false, NULL, true);
2273         if (status != I40E_SUCCESS)
2274                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2275
2276         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2277                                                         false, NULL);
2278         if (status != I40E_SUCCESS)
2279                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2280 }
2281
2282 static void
2283 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2284 {
2285         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2286         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2287         struct i40e_vsi *vsi = pf->main_vsi;
2288         int ret;
2289
2290         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2291         if (ret != I40E_SUCCESS)
2292                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2293 }
2294
2295 static void
2296 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2297 {
2298         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2299         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2300         struct i40e_vsi *vsi = pf->main_vsi;
2301         int ret;
2302
2303         if (dev->data->promiscuous == 1)
2304                 return; /* must remain in all_multicast mode */
2305
2306         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2307                                 vsi->seid, FALSE, NULL);
2308         if (ret != I40E_SUCCESS)
2309                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2310 }
2311
2312 /*
2313  * Set device link up.
2314  */
2315 static int
2316 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2317 {
2318         /* re-apply link speed setting */
2319         return i40e_apply_link_speed(dev);
2320 }
2321
2322 /*
2323  * Set device link down.
2324  */
2325 static int
2326 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2327 {
2328         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2329         uint8_t abilities = 0;
2330         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2331
2332         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2333         return i40e_phy_conf_link(hw, abilities, speed, false);
2334 }
2335
2336 int
2337 i40e_dev_link_update(struct rte_eth_dev *dev,
2338                      int wait_to_complete)
2339 {
2340 #define CHECK_INTERVAL 100  /* 100ms */
2341 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2342         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2343         struct i40e_link_status link_status;
2344         struct rte_eth_link link, old;
2345         int status;
2346         unsigned rep_cnt = MAX_REPEAT_TIME;
2347         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2348
2349         memset(&link, 0, sizeof(link));
2350         memset(&old, 0, sizeof(old));
2351         memset(&link_status, 0, sizeof(link_status));
2352         rte_i40e_dev_atomic_read_link_status(dev, &old);
2353
2354         do {
2355                 /* Get link status information from hardware */
2356                 status = i40e_aq_get_link_info(hw, enable_lse,
2357                                                 &link_status, NULL);
2358                 if (status != I40E_SUCCESS) {
2359                         link.link_speed = ETH_SPEED_NUM_100M;
2360                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2361                         PMD_DRV_LOG(ERR, "Failed to get link info");
2362                         goto out;
2363                 }
2364
2365                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2366                 if (!wait_to_complete || link.link_status)
2367                         break;
2368
2369                 rte_delay_ms(CHECK_INTERVAL);
2370         } while (--rep_cnt);
2371
2372         if (!link.link_status)
2373                 goto out;
2374
2375         /* i40e uses full duplex only */
2376         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2377
2378         /* Parse the link status */
2379         switch (link_status.link_speed) {
2380         case I40E_LINK_SPEED_100MB:
2381                 link.link_speed = ETH_SPEED_NUM_100M;
2382                 break;
2383         case I40E_LINK_SPEED_1GB:
2384                 link.link_speed = ETH_SPEED_NUM_1G;
2385                 break;
2386         case I40E_LINK_SPEED_10GB:
2387                 link.link_speed = ETH_SPEED_NUM_10G;
2388                 break;
2389         case I40E_LINK_SPEED_20GB:
2390                 link.link_speed = ETH_SPEED_NUM_20G;
2391                 break;
2392         case I40E_LINK_SPEED_25GB:
2393                 link.link_speed = ETH_SPEED_NUM_25G;
2394                 break;
2395         case I40E_LINK_SPEED_40GB:
2396                 link.link_speed = ETH_SPEED_NUM_40G;
2397                 break;
2398         default:
2399                 link.link_speed = ETH_SPEED_NUM_100M;
2400                 break;
2401         }
2402
2403         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2404                         ETH_LINK_SPEED_FIXED);
2405
2406 out:
2407         rte_i40e_dev_atomic_write_link_status(dev, &link);
2408         if (link.link_status == old.link_status)
2409                 return -1;
2410
2411         i40e_notify_all_vfs_link_status(dev);
2412
2413         return 0;
2414 }
2415
2416 /* Get all the statistics of a VSI */
2417 void
2418 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2419 {
2420         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2421         struct i40e_eth_stats *nes = &vsi->eth_stats;
2422         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2423         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2424
2425         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2426                             vsi->offset_loaded, &oes->rx_bytes,
2427                             &nes->rx_bytes);
2428         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2429                             vsi->offset_loaded, &oes->rx_unicast,
2430                             &nes->rx_unicast);
2431         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2432                             vsi->offset_loaded, &oes->rx_multicast,
2433                             &nes->rx_multicast);
2434         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2435                             vsi->offset_loaded, &oes->rx_broadcast,
2436                             &nes->rx_broadcast);
2437         /* exclude CRC bytes */
2438         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2439                 nes->rx_broadcast) * ETHER_CRC_LEN;
2440
2441         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2442                             &oes->rx_discards, &nes->rx_discards);
2443         /* GLV_REPC not supported */
2444         /* GLV_RMPC not supported */
2445         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2446                             &oes->rx_unknown_protocol,
2447                             &nes->rx_unknown_protocol);
2448         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2449                             vsi->offset_loaded, &oes->tx_bytes,
2450                             &nes->tx_bytes);
2451         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2452                             vsi->offset_loaded, &oes->tx_unicast,
2453                             &nes->tx_unicast);
2454         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2455                             vsi->offset_loaded, &oes->tx_multicast,
2456                             &nes->tx_multicast);
2457         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2458                             vsi->offset_loaded,  &oes->tx_broadcast,
2459                             &nes->tx_broadcast);
2460         /* GLV_TDPC not supported */
2461         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2462                             &oes->tx_errors, &nes->tx_errors);
2463         vsi->offset_loaded = true;
2464
2465         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2466                     vsi->vsi_id);
2467         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2468         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2469         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2470         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2471         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2472         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2473                     nes->rx_unknown_protocol);
2474         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2475         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2476         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2477         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2478         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2479         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2480         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2481                     vsi->vsi_id);
2482 }
2483
2484 static void
2485 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2486 {
2487         unsigned int i;
2488         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2489         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2490
2491         /* Get rx/tx bytes of internal transfer packets */
2492         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2493                         I40E_GLV_GORCL(hw->port),
2494                         pf->offset_loaded,
2495                         &pf->internal_stats_offset.rx_bytes,
2496                         &pf->internal_stats.rx_bytes);
2497
2498         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2499                         I40E_GLV_GOTCL(hw->port),
2500                         pf->offset_loaded,
2501                         &pf->internal_stats_offset.tx_bytes,
2502                         &pf->internal_stats.tx_bytes);
2503         /* Get total internal rx packet count */
2504         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2505                             I40E_GLV_UPRCL(hw->port),
2506                             pf->offset_loaded,
2507                             &pf->internal_stats_offset.rx_unicast,
2508                             &pf->internal_stats.rx_unicast);
2509         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2510                             I40E_GLV_MPRCL(hw->port),
2511                             pf->offset_loaded,
2512                             &pf->internal_stats_offset.rx_multicast,
2513                             &pf->internal_stats.rx_multicast);
2514         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2515                             I40E_GLV_BPRCL(hw->port),
2516                             pf->offset_loaded,
2517                             &pf->internal_stats_offset.rx_broadcast,
2518                             &pf->internal_stats.rx_broadcast);
2519
2520         /* exclude CRC size */
2521         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2522                 pf->internal_stats.rx_multicast +
2523                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2524
2525         /* Get statistics of struct i40e_eth_stats */
2526         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2527                             I40E_GLPRT_GORCL(hw->port),
2528                             pf->offset_loaded, &os->eth.rx_bytes,
2529                             &ns->eth.rx_bytes);
2530         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2531                             I40E_GLPRT_UPRCL(hw->port),
2532                             pf->offset_loaded, &os->eth.rx_unicast,
2533                             &ns->eth.rx_unicast);
2534         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2535                             I40E_GLPRT_MPRCL(hw->port),
2536                             pf->offset_loaded, &os->eth.rx_multicast,
2537                             &ns->eth.rx_multicast);
2538         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2539                             I40E_GLPRT_BPRCL(hw->port),
2540                             pf->offset_loaded, &os->eth.rx_broadcast,
2541                             &ns->eth.rx_broadcast);
2542         /* Workaround: CRC size should not be included in byte statistics,
2543          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2544          */
2545         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2546                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2547
2548         /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2549          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2550          * value.
2551          */
2552         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2553                 ns->eth.rx_bytes = 0;
2554         /* exlude internal rx bytes */
2555         else
2556                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2557
2558         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2559                             pf->offset_loaded, &os->eth.rx_discards,
2560                             &ns->eth.rx_discards);
2561         /* GLPRT_REPC not supported */
2562         /* GLPRT_RMPC not supported */
2563         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2564                             pf->offset_loaded,
2565                             &os->eth.rx_unknown_protocol,
2566                             &ns->eth.rx_unknown_protocol);
2567         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2568                             I40E_GLPRT_GOTCL(hw->port),
2569                             pf->offset_loaded, &os->eth.tx_bytes,
2570                             &ns->eth.tx_bytes);
2571         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2572                             I40E_GLPRT_UPTCL(hw->port),
2573                             pf->offset_loaded, &os->eth.tx_unicast,
2574                             &ns->eth.tx_unicast);
2575         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2576                             I40E_GLPRT_MPTCL(hw->port),
2577                             pf->offset_loaded, &os->eth.tx_multicast,
2578                             &ns->eth.tx_multicast);
2579         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2580                             I40E_GLPRT_BPTCL(hw->port),
2581                             pf->offset_loaded, &os->eth.tx_broadcast,
2582                             &ns->eth.tx_broadcast);
2583         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2584                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2585
2586         /* exclude internal tx bytes */
2587         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2588                 ns->eth.tx_bytes = 0;
2589         else
2590                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2591
2592         /* GLPRT_TEPC not supported */
2593
2594         /* additional port specific stats */
2595         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2596                             pf->offset_loaded, &os->tx_dropped_link_down,
2597                             &ns->tx_dropped_link_down);
2598         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2599                             pf->offset_loaded, &os->crc_errors,
2600                             &ns->crc_errors);
2601         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2602                             pf->offset_loaded, &os->illegal_bytes,
2603                             &ns->illegal_bytes);
2604         /* GLPRT_ERRBC not supported */
2605         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2606                             pf->offset_loaded, &os->mac_local_faults,
2607                             &ns->mac_local_faults);
2608         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2609                             pf->offset_loaded, &os->mac_remote_faults,
2610                             &ns->mac_remote_faults);
2611         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2612                             pf->offset_loaded, &os->rx_length_errors,
2613                             &ns->rx_length_errors);
2614         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2615                             pf->offset_loaded, &os->link_xon_rx,
2616                             &ns->link_xon_rx);
2617         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2618                             pf->offset_loaded, &os->link_xoff_rx,
2619                             &ns->link_xoff_rx);
2620         for (i = 0; i < 8; i++) {
2621                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2622                                     pf->offset_loaded,
2623                                     &os->priority_xon_rx[i],
2624                                     &ns->priority_xon_rx[i]);
2625                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2626                                     pf->offset_loaded,
2627                                     &os->priority_xoff_rx[i],
2628                                     &ns->priority_xoff_rx[i]);
2629         }
2630         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2631                             pf->offset_loaded, &os->link_xon_tx,
2632                             &ns->link_xon_tx);
2633         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2634                             pf->offset_loaded, &os->link_xoff_tx,
2635                             &ns->link_xoff_tx);
2636         for (i = 0; i < 8; i++) {
2637                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2638                                     pf->offset_loaded,
2639                                     &os->priority_xon_tx[i],
2640                                     &ns->priority_xon_tx[i]);
2641                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2642                                     pf->offset_loaded,
2643                                     &os->priority_xoff_tx[i],
2644                                     &ns->priority_xoff_tx[i]);
2645                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2646                                     pf->offset_loaded,
2647                                     &os->priority_xon_2_xoff[i],
2648                                     &ns->priority_xon_2_xoff[i]);
2649         }
2650         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2651                             I40E_GLPRT_PRC64L(hw->port),
2652                             pf->offset_loaded, &os->rx_size_64,
2653                             &ns->rx_size_64);
2654         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2655                             I40E_GLPRT_PRC127L(hw->port),
2656                             pf->offset_loaded, &os->rx_size_127,
2657                             &ns->rx_size_127);
2658         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2659                             I40E_GLPRT_PRC255L(hw->port),
2660                             pf->offset_loaded, &os->rx_size_255,
2661                             &ns->rx_size_255);
2662         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2663                             I40E_GLPRT_PRC511L(hw->port),
2664                             pf->offset_loaded, &os->rx_size_511,
2665                             &ns->rx_size_511);
2666         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2667                             I40E_GLPRT_PRC1023L(hw->port),
2668                             pf->offset_loaded, &os->rx_size_1023,
2669                             &ns->rx_size_1023);
2670         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2671                             I40E_GLPRT_PRC1522L(hw->port),
2672                             pf->offset_loaded, &os->rx_size_1522,
2673                             &ns->rx_size_1522);
2674         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2675                             I40E_GLPRT_PRC9522L(hw->port),
2676                             pf->offset_loaded, &os->rx_size_big,
2677                             &ns->rx_size_big);
2678         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2679                             pf->offset_loaded, &os->rx_undersize,
2680                             &ns->rx_undersize);
2681         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2682                             pf->offset_loaded, &os->rx_fragments,
2683                             &ns->rx_fragments);
2684         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2685                             pf->offset_loaded, &os->rx_oversize,
2686                             &ns->rx_oversize);
2687         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2688                             pf->offset_loaded, &os->rx_jabber,
2689                             &ns->rx_jabber);
2690         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2691                             I40E_GLPRT_PTC64L(hw->port),
2692                             pf->offset_loaded, &os->tx_size_64,
2693                             &ns->tx_size_64);
2694         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2695                             I40E_GLPRT_PTC127L(hw->port),
2696                             pf->offset_loaded, &os->tx_size_127,
2697                             &ns->tx_size_127);
2698         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2699                             I40E_GLPRT_PTC255L(hw->port),
2700                             pf->offset_loaded, &os->tx_size_255,
2701                             &ns->tx_size_255);
2702         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2703                             I40E_GLPRT_PTC511L(hw->port),
2704                             pf->offset_loaded, &os->tx_size_511,
2705                             &ns->tx_size_511);
2706         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2707                             I40E_GLPRT_PTC1023L(hw->port),
2708                             pf->offset_loaded, &os->tx_size_1023,
2709                             &ns->tx_size_1023);
2710         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2711                             I40E_GLPRT_PTC1522L(hw->port),
2712                             pf->offset_loaded, &os->tx_size_1522,
2713                             &ns->tx_size_1522);
2714         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2715                             I40E_GLPRT_PTC9522L(hw->port),
2716                             pf->offset_loaded, &os->tx_size_big,
2717                             &ns->tx_size_big);
2718         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2719                            pf->offset_loaded,
2720                            &os->fd_sb_match, &ns->fd_sb_match);
2721         /* GLPRT_MSPDC not supported */
2722         /* GLPRT_XEC not supported */
2723
2724         pf->offset_loaded = true;
2725
2726         if (pf->main_vsi)
2727                 i40e_update_vsi_stats(pf->main_vsi);
2728 }
2729
2730 /* Get all statistics of a port */
2731 static void
2732 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2733 {
2734         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2735         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2736         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2737         unsigned i;
2738
2739         /* call read registers - updates values, now write them to struct */
2740         i40e_read_stats_registers(pf, hw);
2741
2742         stats->ipackets = ns->eth.rx_unicast +
2743                         ns->eth.rx_multicast +
2744                         ns->eth.rx_broadcast -
2745                         ns->eth.rx_discards -
2746                         pf->main_vsi->eth_stats.rx_discards;
2747         stats->opackets = ns->eth.tx_unicast +
2748                         ns->eth.tx_multicast +
2749                         ns->eth.tx_broadcast;
2750         stats->ibytes   = ns->eth.rx_bytes;
2751         stats->obytes   = ns->eth.tx_bytes;
2752         stats->oerrors  = ns->eth.tx_errors +
2753                         pf->main_vsi->eth_stats.tx_errors;
2754
2755         /* Rx Errors */
2756         stats->imissed  = ns->eth.rx_discards +
2757                         pf->main_vsi->eth_stats.rx_discards;
2758         stats->ierrors  = ns->crc_errors +
2759                         ns->rx_length_errors + ns->rx_undersize +
2760                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2761
2762         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2763         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2764         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2765         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2766         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2767         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2768         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2769                     ns->eth.rx_unknown_protocol);
2770         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2771         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2772         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2773         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2774         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2775         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2776
2777         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2778                     ns->tx_dropped_link_down);
2779         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2780         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2781                     ns->illegal_bytes);
2782         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2783         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2784                     ns->mac_local_faults);
2785         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2786                     ns->mac_remote_faults);
2787         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2788                     ns->rx_length_errors);
2789         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2790         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2791         for (i = 0; i < 8; i++) {
2792                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2793                                 i, ns->priority_xon_rx[i]);
2794                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2795                                 i, ns->priority_xoff_rx[i]);
2796         }
2797         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2798         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2799         for (i = 0; i < 8; i++) {
2800                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2801                                 i, ns->priority_xon_tx[i]);
2802                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2803                                 i, ns->priority_xoff_tx[i]);
2804                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2805                                 i, ns->priority_xon_2_xoff[i]);
2806         }
2807         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2808         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2809         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2810         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2811         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2812         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2813         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2814         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2815         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2816         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2817         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2818         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2819         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2820         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2821         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2822         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2823         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2824         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2825         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2826                         ns->mac_short_packet_dropped);
2827         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2828                     ns->checksum_error);
2829         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2830         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2831 }
2832
2833 /* Reset the statistics */
2834 static void
2835 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2836 {
2837         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2838         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2839
2840         /* Mark PF and VSI stats to update the offset, aka "reset" */
2841         pf->offset_loaded = false;
2842         if (pf->main_vsi)
2843                 pf->main_vsi->offset_loaded = false;
2844
2845         /* read the stats, reading current register values into offset */
2846         i40e_read_stats_registers(pf, hw);
2847 }
2848
2849 static uint32_t
2850 i40e_xstats_calc_num(void)
2851 {
2852         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2853                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2854                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2855 }
2856
2857 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2858                                      struct rte_eth_xstat_name *xstats_names,
2859                                      __rte_unused unsigned limit)
2860 {
2861         unsigned count = 0;
2862         unsigned i, prio;
2863
2864         if (xstats_names == NULL)
2865                 return i40e_xstats_calc_num();
2866
2867         /* Note: limit checked in rte_eth_xstats_names() */
2868
2869         /* Get stats from i40e_eth_stats struct */
2870         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2871                 snprintf(xstats_names[count].name,
2872                          sizeof(xstats_names[count].name),
2873                          "%s", rte_i40e_stats_strings[i].name);
2874                 count++;
2875         }
2876
2877         /* Get individiual stats from i40e_hw_port struct */
2878         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2879                 snprintf(xstats_names[count].name,
2880                         sizeof(xstats_names[count].name),
2881                          "%s", rte_i40e_hw_port_strings[i].name);
2882                 count++;
2883         }
2884
2885         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2886                 for (prio = 0; prio < 8; prio++) {
2887                         snprintf(xstats_names[count].name,
2888                                  sizeof(xstats_names[count].name),
2889                                  "rx_priority%u_%s", prio,
2890                                  rte_i40e_rxq_prio_strings[i].name);
2891                         count++;
2892                 }
2893         }
2894
2895         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2896                 for (prio = 0; prio < 8; prio++) {
2897                         snprintf(xstats_names[count].name,
2898                                  sizeof(xstats_names[count].name),
2899                                  "tx_priority%u_%s", prio,
2900                                  rte_i40e_txq_prio_strings[i].name);
2901                         count++;
2902                 }
2903         }
2904         return count;
2905 }
2906
2907 static int
2908 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2909                     unsigned n)
2910 {
2911         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2912         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2913         unsigned i, count, prio;
2914         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2915
2916         count = i40e_xstats_calc_num();
2917         if (n < count)
2918                 return count;
2919
2920         i40e_read_stats_registers(pf, hw);
2921
2922         if (xstats == NULL)
2923                 return 0;
2924
2925         count = 0;
2926
2927         /* Get stats from i40e_eth_stats struct */
2928         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2929                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2930                         rte_i40e_stats_strings[i].offset);
2931                 xstats[count].id = count;
2932                 count++;
2933         }
2934
2935         /* Get individiual stats from i40e_hw_port struct */
2936         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2937                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2938                         rte_i40e_hw_port_strings[i].offset);
2939                 xstats[count].id = count;
2940                 count++;
2941         }
2942
2943         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2944                 for (prio = 0; prio < 8; prio++) {
2945                         xstats[count].value =
2946                                 *(uint64_t *)(((char *)hw_stats) +
2947                                 rte_i40e_rxq_prio_strings[i].offset +
2948                                 (sizeof(uint64_t) * prio));
2949                         xstats[count].id = count;
2950                         count++;
2951                 }
2952         }
2953
2954         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2955                 for (prio = 0; prio < 8; prio++) {
2956                         xstats[count].value =
2957                                 *(uint64_t *)(((char *)hw_stats) +
2958                                 rte_i40e_txq_prio_strings[i].offset +
2959                                 (sizeof(uint64_t) * prio));
2960                         xstats[count].id = count;
2961                         count++;
2962                 }
2963         }
2964
2965         return count;
2966 }
2967
2968 static int
2969 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2970                                  __rte_unused uint16_t queue_id,
2971                                  __rte_unused uint8_t stat_idx,
2972                                  __rte_unused uint8_t is_rx)
2973 {
2974         PMD_INIT_FUNC_TRACE();
2975
2976         return -ENOSYS;
2977 }
2978
2979 static int
2980 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2981 {
2982         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2983         u32 full_ver;
2984         u8 ver, patch;
2985         u16 build;
2986         int ret;
2987
2988         full_ver = hw->nvm.oem_ver;
2989         ver = (u8)(full_ver >> 24);
2990         build = (u16)((full_ver >> 8) & 0xffff);
2991         patch = (u8)(full_ver & 0xff);
2992
2993         ret = snprintf(fw_version, fw_size,
2994                  "%d.%d%d 0x%08x %d.%d.%d",
2995                  ((hw->nvm.version >> 12) & 0xf),
2996                  ((hw->nvm.version >> 4) & 0xff),
2997                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2998                  ver, build, patch);
2999
3000         ret += 1; /* add the size of '\0' */
3001         if (fw_size < (u32)ret)
3002                 return ret;
3003         else
3004                 return 0;
3005 }
3006
3007 static void
3008 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3009 {
3010         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3011         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3012         struct i40e_vsi *vsi = pf->main_vsi;
3013         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3014
3015         dev_info->pci_dev = pci_dev;
3016         dev_info->max_rx_queues = vsi->nb_qps;
3017         dev_info->max_tx_queues = vsi->nb_qps;
3018         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3019         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3020         dev_info->max_mac_addrs = vsi->max_macaddrs;
3021         dev_info->max_vfs = pci_dev->max_vfs;
3022         dev_info->rx_offload_capa =
3023                 DEV_RX_OFFLOAD_VLAN_STRIP |
3024                 DEV_RX_OFFLOAD_QINQ_STRIP |
3025                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3026                 DEV_RX_OFFLOAD_UDP_CKSUM |
3027                 DEV_RX_OFFLOAD_TCP_CKSUM;
3028         dev_info->tx_offload_capa =
3029                 DEV_TX_OFFLOAD_VLAN_INSERT |
3030                 DEV_TX_OFFLOAD_QINQ_INSERT |
3031                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3032                 DEV_TX_OFFLOAD_UDP_CKSUM |
3033                 DEV_TX_OFFLOAD_TCP_CKSUM |
3034                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3035                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3036                 DEV_TX_OFFLOAD_TCP_TSO |
3037                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3038                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3039                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3040                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3041         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3042                                                 sizeof(uint32_t);
3043         dev_info->reta_size = pf->hash_lut_size;
3044         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3045
3046         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3047                 .rx_thresh = {
3048                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3049                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3050                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3051                 },
3052                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3053                 .rx_drop_en = 0,
3054         };
3055
3056         dev_info->default_txconf = (struct rte_eth_txconf) {
3057                 .tx_thresh = {
3058                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3059                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3060                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3061                 },
3062                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3063                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3064                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3065                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3066         };
3067
3068         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3069                 .nb_max = I40E_MAX_RING_DESC,
3070                 .nb_min = I40E_MIN_RING_DESC,
3071                 .nb_align = I40E_ALIGN_RING_DESC,
3072         };
3073
3074         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3075                 .nb_max = I40E_MAX_RING_DESC,
3076                 .nb_min = I40E_MIN_RING_DESC,
3077                 .nb_align = I40E_ALIGN_RING_DESC,
3078                 .nb_seg_max = I40E_TX_MAX_SEG,
3079                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3080         };
3081
3082         if (pf->flags & I40E_FLAG_VMDQ) {
3083                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3084                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3085                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3086                                                 pf->max_nb_vmdq_vsi;
3087                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3088                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3089                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3090         }
3091
3092         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3093                 /* For XL710 */
3094                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3095         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3096                 /* For XXV710 */
3097                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3098         else
3099                 /* For X710 */
3100                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3101 }
3102
3103 static int
3104 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3105 {
3106         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3107         struct i40e_vsi *vsi = pf->main_vsi;
3108         PMD_INIT_FUNC_TRACE();
3109
3110         if (on)
3111                 return i40e_vsi_add_vlan(vsi, vlan_id);
3112         else
3113                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3114 }
3115
3116 static int
3117 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3118                                 enum rte_vlan_type vlan_type,
3119                                 uint16_t tpid, int qinq)
3120 {
3121         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3122         uint64_t reg_r = 0;
3123         uint64_t reg_w = 0;
3124         uint16_t reg_id = 3;
3125         int ret;
3126
3127         if (qinq) {
3128                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3129                         reg_id = 2;
3130         }
3131
3132         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3133                                           &reg_r, NULL);
3134         if (ret != I40E_SUCCESS) {
3135                 PMD_DRV_LOG(ERR,
3136                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3137                            reg_id);
3138                 return -EIO;
3139         }
3140         PMD_DRV_LOG(DEBUG,
3141                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3142                     reg_id, reg_r);
3143
3144         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3145         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3146         if (reg_r == reg_w) {
3147                 PMD_DRV_LOG(DEBUG, "No need to write");
3148                 return 0;
3149         }
3150
3151         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3152                                            reg_w, NULL);
3153         if (ret != I40E_SUCCESS) {
3154                 PMD_DRV_LOG(ERR,
3155                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3156                             reg_id);
3157                 return -EIO;
3158         }
3159         PMD_DRV_LOG(DEBUG,
3160                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3161                     reg_w, reg_id);
3162
3163         return 0;
3164 }
3165
3166 static int
3167 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3168                    enum rte_vlan_type vlan_type,
3169                    uint16_t tpid)
3170 {
3171         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3172         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3173         int ret = 0;
3174
3175         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3176              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3177             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3178                 PMD_DRV_LOG(ERR,
3179                             "Unsupported vlan type.");
3180                 return -EINVAL;
3181         }
3182         /* 802.1ad frames ability is added in NVM API 1.7*/
3183         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3184                 if (qinq) {
3185                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3186                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3187                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3188                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3189                 } else {
3190                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3191                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3192                 }
3193                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3194                 if (ret != I40E_SUCCESS) {
3195                         PMD_DRV_LOG(ERR,
3196                                     "Set switch config failed aq_err: %d",
3197                                     hw->aq.asq_last_status);
3198                         ret = -EIO;
3199                 }
3200         } else
3201                 /* If NVM API < 1.7, keep the register setting */
3202                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3203                                                       tpid, qinq);
3204
3205         return ret;
3206 }
3207
3208 static void
3209 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3210 {
3211         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3212         struct i40e_vsi *vsi = pf->main_vsi;
3213
3214         if (mask & ETH_VLAN_FILTER_MASK) {
3215                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3216                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3217                 else
3218                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3219         }
3220
3221         if (mask & ETH_VLAN_STRIP_MASK) {
3222                 /* Enable or disable VLAN stripping */
3223                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3224                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3225                 else
3226                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3227         }
3228
3229         if (mask & ETH_VLAN_EXTEND_MASK) {
3230                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3231                         i40e_vsi_config_double_vlan(vsi, TRUE);
3232                         /* Set global registers with default ethertype. */
3233                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3234                                            ETHER_TYPE_VLAN);
3235                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3236                                            ETHER_TYPE_VLAN);
3237                 }
3238                 else
3239                         i40e_vsi_config_double_vlan(vsi, FALSE);
3240         }
3241 }
3242
3243 static void
3244 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3245                           __rte_unused uint16_t queue,
3246                           __rte_unused int on)
3247 {
3248         PMD_INIT_FUNC_TRACE();
3249 }
3250
3251 static int
3252 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3253 {
3254         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3255         struct i40e_vsi *vsi = pf->main_vsi;
3256         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3257         struct i40e_vsi_vlan_pvid_info info;
3258
3259         memset(&info, 0, sizeof(info));
3260         info.on = on;
3261         if (info.on)
3262                 info.config.pvid = pvid;
3263         else {
3264                 info.config.reject.tagged =
3265                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3266                 info.config.reject.untagged =
3267                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3268         }
3269
3270         return i40e_vsi_vlan_pvid_set(vsi, &info);
3271 }
3272
3273 static int
3274 i40e_dev_led_on(struct rte_eth_dev *dev)
3275 {
3276         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3277         uint32_t mode = i40e_led_get(hw);
3278
3279         if (mode == 0)
3280                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3281
3282         return 0;
3283 }
3284
3285 static int
3286 i40e_dev_led_off(struct rte_eth_dev *dev)
3287 {
3288         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3289         uint32_t mode = i40e_led_get(hw);
3290
3291         if (mode != 0)
3292                 i40e_led_set(hw, 0, false);
3293
3294         return 0;
3295 }
3296
3297 static int
3298 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3299 {
3300         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3301         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3302
3303         fc_conf->pause_time = pf->fc_conf.pause_time;
3304
3305         /* read out from register, in case they are modified by other port */
3306         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3307                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3308         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3309                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3310
3311         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3312         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3313
3314          /* Return current mode according to actual setting*/
3315         switch (hw->fc.current_mode) {
3316         case I40E_FC_FULL:
3317                 fc_conf->mode = RTE_FC_FULL;
3318                 break;
3319         case I40E_FC_TX_PAUSE:
3320                 fc_conf->mode = RTE_FC_TX_PAUSE;
3321                 break;
3322         case I40E_FC_RX_PAUSE:
3323                 fc_conf->mode = RTE_FC_RX_PAUSE;
3324                 break;
3325         case I40E_FC_NONE:
3326         default:
3327                 fc_conf->mode = RTE_FC_NONE;
3328         };
3329
3330         return 0;
3331 }
3332
3333 static int
3334 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3335 {
3336         uint32_t mflcn_reg, fctrl_reg, reg;
3337         uint32_t max_high_water;
3338         uint8_t i, aq_failure;
3339         int err;
3340         struct i40e_hw *hw;
3341         struct i40e_pf *pf;
3342         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3343                 [RTE_FC_NONE] = I40E_FC_NONE,
3344                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3345                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3346                 [RTE_FC_FULL] = I40E_FC_FULL
3347         };
3348
3349         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3350
3351         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3352         if ((fc_conf->high_water > max_high_water) ||
3353                         (fc_conf->high_water < fc_conf->low_water)) {
3354                 PMD_INIT_LOG(ERR,
3355                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3356                         max_high_water);
3357                 return -EINVAL;
3358         }
3359
3360         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3361         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3362         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3363
3364         pf->fc_conf.pause_time = fc_conf->pause_time;
3365         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3366         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3367
3368         PMD_INIT_FUNC_TRACE();
3369
3370         /* All the link flow control related enable/disable register
3371          * configuration is handle by the F/W
3372          */
3373         err = i40e_set_fc(hw, &aq_failure, true);
3374         if (err < 0)
3375                 return -ENOSYS;
3376
3377         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3378                 /* Configure flow control refresh threshold,
3379                  * the value for stat_tx_pause_refresh_timer[8]
3380                  * is used for global pause operation.
3381                  */
3382
3383                 I40E_WRITE_REG(hw,
3384                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3385                                pf->fc_conf.pause_time);
3386
3387                 /* configure the timer value included in transmitted pause
3388                  * frame,
3389                  * the value for stat_tx_pause_quanta[8] is used for global
3390                  * pause operation
3391                  */
3392                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3393                                pf->fc_conf.pause_time);
3394
3395                 fctrl_reg = I40E_READ_REG(hw,
3396                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3397
3398                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3399                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3400                 else
3401                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3402
3403                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3404                                fctrl_reg);
3405         } else {
3406                 /* Configure pause time (2 TCs per register) */
3407                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3408                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3409                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3410
3411                 /* Configure flow control refresh threshold value */
3412                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3413                                pf->fc_conf.pause_time / 2);
3414
3415                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3416
3417                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3418                  *depending on configuration
3419                  */
3420                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3421                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3422                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3423                 } else {
3424                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3425                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3426                 }
3427
3428                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3429         }
3430
3431         /* config the water marker both based on the packets and bytes */
3432         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3433                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3434                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3435         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3436                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3437                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3438         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3439                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3440                        << I40E_KILOSHIFT);
3441         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3442                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3443                        << I40E_KILOSHIFT);
3444
3445         I40E_WRITE_FLUSH(hw);
3446
3447         return 0;
3448 }
3449
3450 static int
3451 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3452                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3453 {
3454         PMD_INIT_FUNC_TRACE();
3455
3456         return -ENOSYS;
3457 }
3458
3459 /* Add a MAC address, and update filters */
3460 static int
3461 i40e_macaddr_add(struct rte_eth_dev *dev,
3462                  struct ether_addr *mac_addr,
3463                  __rte_unused uint32_t index,
3464                  uint32_t pool)
3465 {
3466         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3467         struct i40e_mac_filter_info mac_filter;
3468         struct i40e_vsi *vsi;
3469         int ret;
3470
3471         /* If VMDQ not enabled or configured, return */
3472         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3473                           !pf->nb_cfg_vmdq_vsi)) {
3474                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3475                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3476                         pool);
3477                 return -ENOTSUP;
3478         }
3479
3480         if (pool > pf->nb_cfg_vmdq_vsi) {
3481                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3482                                 pool, pf->nb_cfg_vmdq_vsi);
3483                 return -EINVAL;
3484         }
3485
3486         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3487         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3488                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3489         else
3490                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3491
3492         if (pool == 0)
3493                 vsi = pf->main_vsi;
3494         else
3495                 vsi = pf->vmdq[pool - 1].vsi;
3496
3497         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3498         if (ret != I40E_SUCCESS) {
3499                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3500                 return -ENODEV;
3501         }
3502         return 0;
3503 }
3504
3505 /* Remove a MAC address, and update filters */
3506 static void
3507 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3508 {
3509         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3510         struct i40e_vsi *vsi;
3511         struct rte_eth_dev_data *data = dev->data;
3512         struct ether_addr *macaddr;
3513         int ret;
3514         uint32_t i;
3515         uint64_t pool_sel;
3516
3517         macaddr = &(data->mac_addrs[index]);
3518
3519         pool_sel = dev->data->mac_pool_sel[index];
3520
3521         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3522                 if (pool_sel & (1ULL << i)) {
3523                         if (i == 0)
3524                                 vsi = pf->main_vsi;
3525                         else {
3526                                 /* No VMDQ pool enabled or configured */
3527                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3528                                         (i > pf->nb_cfg_vmdq_vsi)) {
3529                                         PMD_DRV_LOG(ERR,
3530                                                 "No VMDQ pool enabled/configured");
3531                                         return;
3532                                 }
3533                                 vsi = pf->vmdq[i - 1].vsi;
3534                         }
3535                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3536
3537                         if (ret) {
3538                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3539                                 return;
3540                         }
3541                 }
3542         }
3543 }
3544
3545 /* Set perfect match or hash match of MAC and VLAN for a VF */
3546 static int
3547 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3548                  struct rte_eth_mac_filter *filter,
3549                  bool add)
3550 {
3551         struct i40e_hw *hw;
3552         struct i40e_mac_filter_info mac_filter;
3553         struct ether_addr old_mac;
3554         struct ether_addr *new_mac;
3555         struct i40e_pf_vf *vf = NULL;
3556         uint16_t vf_id;
3557         int ret;
3558
3559         if (pf == NULL) {
3560                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3561                 return -EINVAL;
3562         }
3563         hw = I40E_PF_TO_HW(pf);
3564
3565         if (filter == NULL) {
3566                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3567                 return -EINVAL;
3568         }
3569
3570         new_mac = &filter->mac_addr;
3571
3572         if (is_zero_ether_addr(new_mac)) {
3573                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3574                 return -EINVAL;
3575         }
3576
3577         vf_id = filter->dst_id;
3578
3579         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3580                 PMD_DRV_LOG(ERR, "Invalid argument.");
3581                 return -EINVAL;
3582         }
3583         vf = &pf->vfs[vf_id];
3584
3585         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3586                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3587                 return -EINVAL;
3588         }
3589
3590         if (add) {
3591                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3592                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3593                                 ETHER_ADDR_LEN);
3594                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3595                                  ETHER_ADDR_LEN);
3596
3597                 mac_filter.filter_type = filter->filter_type;
3598                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3599                 if (ret != I40E_SUCCESS) {
3600                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3601                         return -1;
3602                 }
3603                 ether_addr_copy(new_mac, &pf->dev_addr);
3604         } else {
3605                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3606                                 ETHER_ADDR_LEN);
3607                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3608                 if (ret != I40E_SUCCESS) {
3609                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3610                         return -1;
3611                 }
3612
3613                 /* Clear device address as it has been removed */
3614                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3615                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3616         }
3617
3618         return 0;
3619 }
3620
3621 /* MAC filter handle */
3622 static int
3623 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3624                 void *arg)
3625 {
3626         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3627         struct rte_eth_mac_filter *filter;
3628         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3629         int ret = I40E_NOT_SUPPORTED;
3630
3631         filter = (struct rte_eth_mac_filter *)(arg);
3632
3633         switch (filter_op) {
3634         case RTE_ETH_FILTER_NOP:
3635                 ret = I40E_SUCCESS;
3636                 break;
3637         case RTE_ETH_FILTER_ADD:
3638                 i40e_pf_disable_irq0(hw);
3639                 if (filter->is_vf)
3640                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3641                 i40e_pf_enable_irq0(hw);
3642                 break;
3643         case RTE_ETH_FILTER_DELETE:
3644                 i40e_pf_disable_irq0(hw);
3645                 if (filter->is_vf)
3646                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3647                 i40e_pf_enable_irq0(hw);
3648                 break;
3649         default:
3650                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3651                 ret = I40E_ERR_PARAM;
3652                 break;
3653         }
3654
3655         return ret;
3656 }
3657
3658 static int
3659 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3660 {
3661         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3662         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3663         int ret;
3664
3665         if (!lut)
3666                 return -EINVAL;
3667
3668         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3669                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3670                                           lut, lut_size);
3671                 if (ret) {
3672                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3673                         return ret;
3674                 }
3675         } else {
3676                 uint32_t *lut_dw = (uint32_t *)lut;
3677                 uint16_t i, lut_size_dw = lut_size / 4;
3678
3679                 for (i = 0; i < lut_size_dw; i++)
3680                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3681         }
3682
3683         return 0;
3684 }
3685
3686 static int
3687 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3688 {
3689         struct i40e_pf *pf;
3690         struct i40e_hw *hw;
3691         int ret;
3692
3693         if (!vsi || !lut)
3694                 return -EINVAL;
3695
3696         pf = I40E_VSI_TO_PF(vsi);
3697         hw = I40E_VSI_TO_HW(vsi);
3698
3699         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3700                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3701                                           lut, lut_size);
3702                 if (ret) {
3703                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3704                         return ret;
3705                 }
3706         } else {
3707                 uint32_t *lut_dw = (uint32_t *)lut;
3708                 uint16_t i, lut_size_dw = lut_size / 4;
3709
3710                 for (i = 0; i < lut_size_dw; i++)
3711                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3712                 I40E_WRITE_FLUSH(hw);
3713         }
3714
3715         return 0;
3716 }
3717
3718 static int
3719 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3720                          struct rte_eth_rss_reta_entry64 *reta_conf,
3721                          uint16_t reta_size)
3722 {
3723         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3724         uint16_t i, lut_size = pf->hash_lut_size;
3725         uint16_t idx, shift;
3726         uint8_t *lut;
3727         int ret;
3728
3729         if (reta_size != lut_size ||
3730                 reta_size > ETH_RSS_RETA_SIZE_512) {
3731                 PMD_DRV_LOG(ERR,
3732                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3733                         reta_size, lut_size);
3734                 return -EINVAL;
3735         }
3736
3737         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3738         if (!lut) {
3739                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3740                 return -ENOMEM;
3741         }
3742         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3743         if (ret)
3744                 goto out;
3745         for (i = 0; i < reta_size; i++) {
3746                 idx = i / RTE_RETA_GROUP_SIZE;
3747                 shift = i % RTE_RETA_GROUP_SIZE;
3748                 if (reta_conf[idx].mask & (1ULL << shift))
3749                         lut[i] = reta_conf[idx].reta[shift];
3750         }
3751         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3752
3753 out:
3754         rte_free(lut);
3755
3756         return ret;
3757 }
3758
3759 static int
3760 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3761                         struct rte_eth_rss_reta_entry64 *reta_conf,
3762                         uint16_t reta_size)
3763 {
3764         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3765         uint16_t i, lut_size = pf->hash_lut_size;
3766         uint16_t idx, shift;
3767         uint8_t *lut;
3768         int ret;
3769
3770         if (reta_size != lut_size ||
3771                 reta_size > ETH_RSS_RETA_SIZE_512) {
3772                 PMD_DRV_LOG(ERR,
3773                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3774                         reta_size, lut_size);
3775                 return -EINVAL;
3776         }
3777
3778         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3779         if (!lut) {
3780                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3781                 return -ENOMEM;
3782         }
3783
3784         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3785         if (ret)
3786                 goto out;
3787         for (i = 0; i < reta_size; i++) {
3788                 idx = i / RTE_RETA_GROUP_SIZE;
3789                 shift = i % RTE_RETA_GROUP_SIZE;
3790                 if (reta_conf[idx].mask & (1ULL << shift))
3791                         reta_conf[idx].reta[shift] = lut[i];
3792         }
3793
3794 out:
3795         rte_free(lut);
3796
3797         return ret;
3798 }
3799
3800 /**
3801  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3802  * @hw:   pointer to the HW structure
3803  * @mem:  pointer to mem struct to fill out
3804  * @size: size of memory requested
3805  * @alignment: what to align the allocation to
3806  **/
3807 enum i40e_status_code
3808 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3809                         struct i40e_dma_mem *mem,
3810                         u64 size,
3811                         u32 alignment)
3812 {
3813         const struct rte_memzone *mz = NULL;
3814         char z_name[RTE_MEMZONE_NAMESIZE];
3815
3816         if (!mem)
3817                 return I40E_ERR_PARAM;
3818
3819         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3820         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3821                                          alignment, RTE_PGSIZE_2M);
3822         if (!mz)
3823                 return I40E_ERR_NO_MEMORY;
3824
3825         mem->size = size;
3826         mem->va = mz->addr;
3827         mem->pa = mz->phys_addr;
3828         mem->zone = (const void *)mz;
3829         PMD_DRV_LOG(DEBUG,
3830                 "memzone %s allocated with physical address: %"PRIu64,
3831                 mz->name, mem->pa);
3832
3833         return I40E_SUCCESS;
3834 }
3835
3836 /**
3837  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3838  * @hw:   pointer to the HW structure
3839  * @mem:  ptr to mem struct to free
3840  **/
3841 enum i40e_status_code
3842 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3843                     struct i40e_dma_mem *mem)
3844 {
3845         if (!mem)
3846                 return I40E_ERR_PARAM;
3847
3848         PMD_DRV_LOG(DEBUG,
3849                 "memzone %s to be freed with physical address: %"PRIu64,
3850                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3851         rte_memzone_free((const struct rte_memzone *)mem->zone);
3852         mem->zone = NULL;
3853         mem->va = NULL;
3854         mem->pa = (u64)0;
3855
3856         return I40E_SUCCESS;
3857 }
3858
3859 /**
3860  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3861  * @hw:   pointer to the HW structure
3862  * @mem:  pointer to mem struct to fill out
3863  * @size: size of memory requested
3864  **/
3865 enum i40e_status_code
3866 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3867                          struct i40e_virt_mem *mem,
3868                          u32 size)
3869 {
3870         if (!mem)
3871                 return I40E_ERR_PARAM;
3872
3873         mem->size = size;
3874         mem->va = rte_zmalloc("i40e", size, 0);
3875
3876         if (mem->va)
3877                 return I40E_SUCCESS;
3878         else
3879                 return I40E_ERR_NO_MEMORY;
3880 }
3881
3882 /**
3883  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3884  * @hw:   pointer to the HW structure
3885  * @mem:  pointer to mem struct to free
3886  **/
3887 enum i40e_status_code
3888 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3889                      struct i40e_virt_mem *mem)
3890 {
3891         if (!mem)
3892                 return I40E_ERR_PARAM;
3893
3894         rte_free(mem->va);
3895         mem->va = NULL;
3896
3897         return I40E_SUCCESS;
3898 }
3899
3900 void
3901 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3902 {
3903         rte_spinlock_init(&sp->spinlock);
3904 }
3905
3906 void
3907 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3908 {
3909         rte_spinlock_lock(&sp->spinlock);
3910 }
3911
3912 void
3913 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3914 {
3915         rte_spinlock_unlock(&sp->spinlock);
3916 }
3917
3918 void
3919 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3920 {
3921         return;
3922 }
3923
3924 /**
3925  * Get the hardware capabilities, which will be parsed
3926  * and saved into struct i40e_hw.
3927  */
3928 static int
3929 i40e_get_cap(struct i40e_hw *hw)
3930 {
3931         struct i40e_aqc_list_capabilities_element_resp *buf;
3932         uint16_t len, size = 0;
3933         int ret;
3934
3935         /* Calculate a huge enough buff for saving response data temporarily */
3936         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3937                                                 I40E_MAX_CAP_ELE_NUM;
3938         buf = rte_zmalloc("i40e", len, 0);
3939         if (!buf) {
3940                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3941                 return I40E_ERR_NO_MEMORY;
3942         }
3943
3944         /* Get, parse the capabilities and save it to hw */
3945         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3946                         i40e_aqc_opc_list_func_capabilities, NULL);
3947         if (ret != I40E_SUCCESS)
3948                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3949
3950         /* Free the temporary buffer after being used */
3951         rte_free(buf);
3952
3953         return ret;
3954 }
3955
3956 static int
3957 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3958 {
3959         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3960         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3961         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3962         uint16_t qp_count = 0, vsi_count = 0;
3963
3964         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3965                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3966                 return -EINVAL;
3967         }
3968         /* Add the parameter init for LFC */
3969         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3970         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3971         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3972
3973         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3974         pf->max_num_vsi = hw->func_caps.num_vsis;
3975         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3976         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3977         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3978
3979         /* FDir queue/VSI allocation */
3980         pf->fdir_qp_offset = 0;
3981         if (hw->func_caps.fd) {
3982                 pf->flags |= I40E_FLAG_FDIR;
3983                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3984         } else {
3985                 pf->fdir_nb_qps = 0;
3986         }
3987         qp_count += pf->fdir_nb_qps;
3988         vsi_count += 1;
3989
3990         /* LAN queue/VSI allocation */
3991         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3992         if (!hw->func_caps.rss) {
3993                 pf->lan_nb_qps = 1;
3994         } else {
3995                 pf->flags |= I40E_FLAG_RSS;
3996                 if (hw->mac.type == I40E_MAC_X722)
3997                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3998                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3999         }
4000         qp_count += pf->lan_nb_qps;
4001         vsi_count += 1;
4002
4003         /* VF queue/VSI allocation */
4004         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4005         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4006                 pf->flags |= I40E_FLAG_SRIOV;
4007                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4008                 pf->vf_num = pci_dev->max_vfs;
4009                 PMD_DRV_LOG(DEBUG,
4010                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4011                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4012         } else {
4013                 pf->vf_nb_qps = 0;
4014                 pf->vf_num = 0;
4015         }
4016         qp_count += pf->vf_nb_qps * pf->vf_num;
4017         vsi_count += pf->vf_num;
4018
4019         /* VMDq queue/VSI allocation */
4020         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4021         pf->vmdq_nb_qps = 0;
4022         pf->max_nb_vmdq_vsi = 0;
4023         if (hw->func_caps.vmdq) {
4024                 if (qp_count < hw->func_caps.num_tx_qp &&
4025                         vsi_count < hw->func_caps.num_vsis) {
4026                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4027                                 qp_count) / pf->vmdq_nb_qp_max;
4028
4029                         /* Limit the maximum number of VMDq vsi to the maximum
4030                          * ethdev can support
4031                          */
4032                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4033                                 hw->func_caps.num_vsis - vsi_count);
4034                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4035                                 ETH_64_POOLS);
4036                         if (pf->max_nb_vmdq_vsi) {
4037                                 pf->flags |= I40E_FLAG_VMDQ;
4038                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4039                                 PMD_DRV_LOG(DEBUG,
4040                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4041                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4042                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4043                         } else {
4044                                 PMD_DRV_LOG(INFO,
4045                                         "No enough queues left for VMDq");
4046                         }
4047                 } else {
4048                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4049                 }
4050         }
4051         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4052         vsi_count += pf->max_nb_vmdq_vsi;
4053
4054         if (hw->func_caps.dcb)
4055                 pf->flags |= I40E_FLAG_DCB;
4056
4057         if (qp_count > hw->func_caps.num_tx_qp) {
4058                 PMD_DRV_LOG(ERR,
4059                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4060                         qp_count, hw->func_caps.num_tx_qp);
4061                 return -EINVAL;
4062         }
4063         if (vsi_count > hw->func_caps.num_vsis) {
4064                 PMD_DRV_LOG(ERR,
4065                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4066                         vsi_count, hw->func_caps.num_vsis);
4067                 return -EINVAL;
4068         }
4069
4070         return 0;
4071 }
4072
4073 static int
4074 i40e_pf_get_switch_config(struct i40e_pf *pf)
4075 {
4076         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4077         struct i40e_aqc_get_switch_config_resp *switch_config;
4078         struct i40e_aqc_switch_config_element_resp *element;
4079         uint16_t start_seid = 0, num_reported;
4080         int ret;
4081
4082         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4083                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4084         if (!switch_config) {
4085                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4086                 return -ENOMEM;
4087         }
4088
4089         /* Get the switch configurations */
4090         ret = i40e_aq_get_switch_config(hw, switch_config,
4091                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4092         if (ret != I40E_SUCCESS) {
4093                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4094                 goto fail;
4095         }
4096         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4097         if (num_reported != 1) { /* The number should be 1 */
4098                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4099                 goto fail;
4100         }
4101
4102         /* Parse the switch configuration elements */
4103         element = &(switch_config->element[0]);
4104         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4105                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4106                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4107         } else
4108                 PMD_DRV_LOG(INFO, "Unknown element type");
4109
4110 fail:
4111         rte_free(switch_config);
4112
4113         return ret;
4114 }
4115
4116 static int
4117 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4118                         uint32_t num)
4119 {
4120         struct pool_entry *entry;
4121
4122         if (pool == NULL || num == 0)
4123                 return -EINVAL;
4124
4125         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4126         if (entry == NULL) {
4127                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4128                 return -ENOMEM;
4129         }
4130
4131         /* queue heap initialize */
4132         pool->num_free = num;
4133         pool->num_alloc = 0;
4134         pool->base = base;
4135         LIST_INIT(&pool->alloc_list);
4136         LIST_INIT(&pool->free_list);
4137
4138         /* Initialize element  */
4139         entry->base = 0;
4140         entry->len = num;
4141
4142         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4143         return 0;
4144 }
4145
4146 static void
4147 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4148 {
4149         struct pool_entry *entry, *next_entry;
4150
4151         if (pool == NULL)
4152                 return;
4153
4154         for (entry = LIST_FIRST(&pool->alloc_list);
4155                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4156                         entry = next_entry) {
4157                 LIST_REMOVE(entry, next);
4158                 rte_free(entry);
4159         }
4160
4161         for (entry = LIST_FIRST(&pool->free_list);
4162                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4163                         entry = next_entry) {
4164                 LIST_REMOVE(entry, next);
4165                 rte_free(entry);
4166         }
4167
4168         pool->num_free = 0;
4169         pool->num_alloc = 0;
4170         pool->base = 0;
4171         LIST_INIT(&pool->alloc_list);
4172         LIST_INIT(&pool->free_list);
4173 }
4174
4175 static int
4176 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4177                        uint32_t base)
4178 {
4179         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4180         uint32_t pool_offset;
4181         int insert;
4182
4183         if (pool == NULL) {
4184                 PMD_DRV_LOG(ERR, "Invalid parameter");
4185                 return -EINVAL;
4186         }
4187
4188         pool_offset = base - pool->base;
4189         /* Lookup in alloc list */
4190         LIST_FOREACH(entry, &pool->alloc_list, next) {
4191                 if (entry->base == pool_offset) {
4192                         valid_entry = entry;
4193                         LIST_REMOVE(entry, next);
4194                         break;
4195                 }
4196         }
4197
4198         /* Not find, return */
4199         if (valid_entry == NULL) {
4200                 PMD_DRV_LOG(ERR, "Failed to find entry");
4201                 return -EINVAL;
4202         }
4203
4204         /**
4205          * Found it, move it to free list  and try to merge.
4206          * In order to make merge easier, always sort it by qbase.
4207          * Find adjacent prev and last entries.
4208          */
4209         prev = next = NULL;
4210         LIST_FOREACH(entry, &pool->free_list, next) {
4211                 if (entry->base > valid_entry->base) {
4212                         next = entry;
4213                         break;
4214                 }
4215                 prev = entry;
4216         }
4217
4218         insert = 0;
4219         /* Try to merge with next one*/
4220         if (next != NULL) {
4221                 /* Merge with next one */
4222                 if (valid_entry->base + valid_entry->len == next->base) {
4223                         next->base = valid_entry->base;
4224                         next->len += valid_entry->len;
4225                         rte_free(valid_entry);
4226                         valid_entry = next;
4227                         insert = 1;
4228                 }
4229         }
4230
4231         if (prev != NULL) {
4232                 /* Merge with previous one */
4233                 if (prev->base + prev->len == valid_entry->base) {
4234                         prev->len += valid_entry->len;
4235                         /* If it merge with next one, remove next node */
4236                         if (insert == 1) {
4237                                 LIST_REMOVE(valid_entry, next);
4238                                 rte_free(valid_entry);
4239                         } else {
4240                                 rte_free(valid_entry);
4241                                 insert = 1;
4242                         }
4243                 }
4244         }
4245
4246         /* Not find any entry to merge, insert */
4247         if (insert == 0) {
4248                 if (prev != NULL)
4249                         LIST_INSERT_AFTER(prev, valid_entry, next);
4250                 else if (next != NULL)
4251                         LIST_INSERT_BEFORE(next, valid_entry, next);
4252                 else /* It's empty list, insert to head */
4253                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4254         }
4255
4256         pool->num_free += valid_entry->len;
4257         pool->num_alloc -= valid_entry->len;
4258
4259         return 0;
4260 }
4261
4262 static int
4263 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4264                        uint16_t num)
4265 {
4266         struct pool_entry *entry, *valid_entry;
4267
4268         if (pool == NULL || num == 0) {
4269                 PMD_DRV_LOG(ERR, "Invalid parameter");
4270                 return -EINVAL;
4271         }
4272
4273         if (pool->num_free < num) {
4274                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4275                             num, pool->num_free);
4276                 return -ENOMEM;
4277         }
4278
4279         valid_entry = NULL;
4280         /* Lookup  in free list and find most fit one */
4281         LIST_FOREACH(entry, &pool->free_list, next) {
4282                 if (entry->len >= num) {
4283                         /* Find best one */
4284                         if (entry->len == num) {
4285                                 valid_entry = entry;
4286                                 break;
4287                         }
4288                         if (valid_entry == NULL || valid_entry->len > entry->len)
4289                                 valid_entry = entry;
4290                 }
4291         }
4292
4293         /* Not find one to satisfy the request, return */
4294         if (valid_entry == NULL) {
4295                 PMD_DRV_LOG(ERR, "No valid entry found");
4296                 return -ENOMEM;
4297         }
4298         /**
4299          * The entry have equal queue number as requested,
4300          * remove it from alloc_list.
4301          */
4302         if (valid_entry->len == num) {
4303                 LIST_REMOVE(valid_entry, next);
4304         } else {
4305                 /**
4306                  * The entry have more numbers than requested,
4307                  * create a new entry for alloc_list and minus its
4308                  * queue base and number in free_list.
4309                  */
4310                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4311                 if (entry == NULL) {
4312                         PMD_DRV_LOG(ERR,
4313                                 "Failed to allocate memory for resource pool");
4314                         return -ENOMEM;
4315                 }
4316                 entry->base = valid_entry->base;
4317                 entry->len = num;
4318                 valid_entry->base += num;
4319                 valid_entry->len -= num;
4320                 valid_entry = entry;
4321         }
4322
4323         /* Insert it into alloc list, not sorted */
4324         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4325
4326         pool->num_free -= valid_entry->len;
4327         pool->num_alloc += valid_entry->len;
4328
4329         return valid_entry->base + pool->base;
4330 }
4331
4332 /**
4333  * bitmap_is_subset - Check whether src2 is subset of src1
4334  **/
4335 static inline int
4336 bitmap_is_subset(uint8_t src1, uint8_t src2)
4337 {
4338         return !((src1 ^ src2) & src2);
4339 }
4340
4341 static enum i40e_status_code
4342 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4343 {
4344         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4345
4346         /* If DCB is not supported, only default TC is supported */
4347         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4348                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4349                 return I40E_NOT_SUPPORTED;
4350         }
4351
4352         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4353                 PMD_DRV_LOG(ERR,
4354                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4355                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4356                 return I40E_NOT_SUPPORTED;
4357         }
4358         return I40E_SUCCESS;
4359 }
4360
4361 int
4362 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4363                                 struct i40e_vsi_vlan_pvid_info *info)
4364 {
4365         struct i40e_hw *hw;
4366         struct i40e_vsi_context ctxt;
4367         uint8_t vlan_flags = 0;
4368         int ret;
4369
4370         if (vsi == NULL || info == NULL) {
4371                 PMD_DRV_LOG(ERR, "invalid parameters");
4372                 return I40E_ERR_PARAM;
4373         }
4374
4375         if (info->on) {
4376                 vsi->info.pvid = info->config.pvid;
4377                 /**
4378                  * If insert pvid is enabled, only tagged pkts are
4379                  * allowed to be sent out.
4380                  */
4381                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4382                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4383         } else {
4384                 vsi->info.pvid = 0;
4385                 if (info->config.reject.tagged == 0)
4386                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4387
4388                 if (info->config.reject.untagged == 0)
4389                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4390         }
4391         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4392                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4393         vsi->info.port_vlan_flags |= vlan_flags;
4394         vsi->info.valid_sections =
4395                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4396         memset(&ctxt, 0, sizeof(ctxt));
4397         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4398         ctxt.seid = vsi->seid;
4399
4400         hw = I40E_VSI_TO_HW(vsi);
4401         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4402         if (ret != I40E_SUCCESS)
4403                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4404
4405         return ret;
4406 }
4407
4408 static int
4409 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4410 {
4411         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4412         int i, ret;
4413         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4414
4415         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4416         if (ret != I40E_SUCCESS)
4417                 return ret;
4418
4419         if (!vsi->seid) {
4420                 PMD_DRV_LOG(ERR, "seid not valid");
4421                 return -EINVAL;
4422         }
4423
4424         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4425         tc_bw_data.tc_valid_bits = enabled_tcmap;
4426         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4427                 tc_bw_data.tc_bw_credits[i] =
4428                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4429
4430         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4431         if (ret != I40E_SUCCESS) {
4432                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4433                 return ret;
4434         }
4435
4436         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4437                                         sizeof(vsi->info.qs_handle));
4438         return I40E_SUCCESS;
4439 }
4440
4441 static enum i40e_status_code
4442 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4443                                  struct i40e_aqc_vsi_properties_data *info,
4444                                  uint8_t enabled_tcmap)
4445 {
4446         enum i40e_status_code ret;
4447         int i, total_tc = 0;
4448         uint16_t qpnum_per_tc, bsf, qp_idx;
4449
4450         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4451         if (ret != I40E_SUCCESS)
4452                 return ret;
4453
4454         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4455                 if (enabled_tcmap & (1 << i))
4456                         total_tc++;
4457         if (total_tc == 0)
4458                 total_tc = 1;
4459         vsi->enabled_tc = enabled_tcmap;
4460
4461         /* Number of queues per enabled TC */
4462         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4463         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4464         bsf = rte_bsf32(qpnum_per_tc);
4465
4466         /* Adjust the queue number to actual queues that can be applied */
4467         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4468                 vsi->nb_qps = qpnum_per_tc * total_tc;
4469
4470         /**
4471          * Configure TC and queue mapping parameters, for enabled TC,
4472          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4473          * default queue will serve it.
4474          */
4475         qp_idx = 0;
4476         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4477                 if (vsi->enabled_tc & (1 << i)) {
4478                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4479                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4480                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4481                         qp_idx += qpnum_per_tc;
4482                 } else
4483                         info->tc_mapping[i] = 0;
4484         }
4485
4486         /* Associate queue number with VSI */
4487         if (vsi->type == I40E_VSI_SRIOV) {
4488                 info->mapping_flags |=
4489                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4490                 for (i = 0; i < vsi->nb_qps; i++)
4491                         info->queue_mapping[i] =
4492                                 rte_cpu_to_le_16(vsi->base_queue + i);
4493         } else {
4494                 info->mapping_flags |=
4495                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4496                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4497         }
4498         info->valid_sections |=
4499                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4500
4501         return I40E_SUCCESS;
4502 }
4503
4504 static int
4505 i40e_veb_release(struct i40e_veb *veb)
4506 {
4507         struct i40e_vsi *vsi;
4508         struct i40e_hw *hw;
4509
4510         if (veb == NULL)
4511                 return -EINVAL;
4512
4513         if (!TAILQ_EMPTY(&veb->head)) {
4514                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4515                 return -EACCES;
4516         }
4517         /* associate_vsi field is NULL for floating VEB */
4518         if (veb->associate_vsi != NULL) {
4519                 vsi = veb->associate_vsi;
4520                 hw = I40E_VSI_TO_HW(vsi);
4521
4522                 vsi->uplink_seid = veb->uplink_seid;
4523                 vsi->veb = NULL;
4524         } else {
4525                 veb->associate_pf->main_vsi->floating_veb = NULL;
4526                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4527         }
4528
4529         i40e_aq_delete_element(hw, veb->seid, NULL);
4530         rte_free(veb);
4531         return I40E_SUCCESS;
4532 }
4533
4534 /* Setup a veb */
4535 static struct i40e_veb *
4536 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4537 {
4538         struct i40e_veb *veb;
4539         int ret;
4540         struct i40e_hw *hw;
4541
4542         if (pf == NULL) {
4543                 PMD_DRV_LOG(ERR,
4544                             "veb setup failed, associated PF shouldn't null");
4545                 return NULL;
4546         }
4547         hw = I40E_PF_TO_HW(pf);
4548
4549         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4550         if (!veb) {
4551                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4552                 goto fail;
4553         }
4554
4555         veb->associate_vsi = vsi;
4556         veb->associate_pf = pf;
4557         TAILQ_INIT(&veb->head);
4558         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4559
4560         /* create floating veb if vsi is NULL */
4561         if (vsi != NULL) {
4562                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4563                                       I40E_DEFAULT_TCMAP, false,
4564                                       &veb->seid, false, NULL);
4565         } else {
4566                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4567                                       true, &veb->seid, false, NULL);
4568         }
4569
4570         if (ret != I40E_SUCCESS) {
4571                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4572                             hw->aq.asq_last_status);
4573                 goto fail;
4574         }
4575         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4576
4577         /* get statistics index */
4578         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4579                                 &veb->stats_idx, NULL, NULL, NULL);
4580         if (ret != I40E_SUCCESS) {
4581                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4582                             hw->aq.asq_last_status);
4583                 goto fail;
4584         }
4585         /* Get VEB bandwidth, to be implemented */
4586         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4587         if (vsi)
4588                 vsi->uplink_seid = veb->seid;
4589
4590         return veb;
4591 fail:
4592         rte_free(veb);
4593         return NULL;
4594 }
4595
4596 int
4597 i40e_vsi_release(struct i40e_vsi *vsi)
4598 {
4599         struct i40e_pf *pf;
4600         struct i40e_hw *hw;
4601         struct i40e_vsi_list *vsi_list;
4602         void *temp;
4603         int ret;
4604         struct i40e_mac_filter *f;
4605         uint16_t user_param;
4606
4607         if (!vsi)
4608                 return I40E_SUCCESS;
4609
4610         if (!vsi->adapter)
4611                 return -EFAULT;
4612
4613         user_param = vsi->user_param;
4614
4615         pf = I40E_VSI_TO_PF(vsi);
4616         hw = I40E_VSI_TO_HW(vsi);
4617
4618         /* VSI has child to attach, release child first */
4619         if (vsi->veb) {
4620                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4621                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4622                                 return -1;
4623                 }
4624                 i40e_veb_release(vsi->veb);
4625         }
4626
4627         if (vsi->floating_veb) {
4628                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4629                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4630                                 return -1;
4631                 }
4632         }
4633
4634         /* Remove all macvlan filters of the VSI */
4635         i40e_vsi_remove_all_macvlan_filter(vsi);
4636         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4637                 rte_free(f);
4638
4639         if (vsi->type != I40E_VSI_MAIN &&
4640             ((vsi->type != I40E_VSI_SRIOV) ||
4641             !pf->floating_veb_list[user_param])) {
4642                 /* Remove vsi from parent's sibling list */
4643                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4644                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4645                         return I40E_ERR_PARAM;
4646                 }
4647                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4648                                 &vsi->sib_vsi_list, list);
4649
4650                 /* Remove all switch element of the VSI */
4651                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4652                 if (ret != I40E_SUCCESS)
4653                         PMD_DRV_LOG(ERR, "Failed to delete element");
4654         }
4655
4656         if ((vsi->type == I40E_VSI_SRIOV) &&
4657             pf->floating_veb_list[user_param]) {
4658                 /* Remove vsi from parent's sibling list */
4659                 if (vsi->parent_vsi == NULL ||
4660                     vsi->parent_vsi->floating_veb == NULL) {
4661                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4662                         return I40E_ERR_PARAM;
4663                 }
4664                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4665                              &vsi->sib_vsi_list, list);
4666
4667                 /* Remove all switch element of the VSI */
4668                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4669                 if (ret != I40E_SUCCESS)
4670                         PMD_DRV_LOG(ERR, "Failed to delete element");
4671         }
4672
4673         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4674
4675         if (vsi->type != I40E_VSI_SRIOV)
4676                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4677         rte_free(vsi);
4678
4679         return I40E_SUCCESS;
4680 }
4681
4682 static int
4683 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4684 {
4685         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4686         struct i40e_aqc_remove_macvlan_element_data def_filter;
4687         struct i40e_mac_filter_info filter;
4688         int ret;
4689
4690         if (vsi->type != I40E_VSI_MAIN)
4691                 return I40E_ERR_CONFIG;
4692         memset(&def_filter, 0, sizeof(def_filter));
4693         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4694                                         ETH_ADDR_LEN);
4695         def_filter.vlan_tag = 0;
4696         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4697                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4698         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4699         if (ret != I40E_SUCCESS) {
4700                 struct i40e_mac_filter *f;
4701                 struct ether_addr *mac;
4702
4703                 PMD_DRV_LOG(DEBUG,
4704                             "Cannot remove the default macvlan filter");
4705                 /* It needs to add the permanent mac into mac list */
4706                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4707                 if (f == NULL) {
4708                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4709                         return I40E_ERR_NO_MEMORY;
4710                 }
4711                 mac = &f->mac_info.mac_addr;
4712                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4713                                 ETH_ADDR_LEN);
4714                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4715                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4716                 vsi->mac_num++;
4717
4718                 return ret;
4719         }
4720         rte_memcpy(&filter.mac_addr,
4721                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4722         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4723         return i40e_vsi_add_mac(vsi, &filter);
4724 }
4725
4726 /*
4727  * i40e_vsi_get_bw_config - Query VSI BW Information
4728  * @vsi: the VSI to be queried
4729  *
4730  * Returns 0 on success, negative value on failure
4731  */
4732 static enum i40e_status_code
4733 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4734 {
4735         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4736         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4737         struct i40e_hw *hw = &vsi->adapter->hw;
4738         i40e_status ret;
4739         int i;
4740         uint32_t bw_max;
4741
4742         memset(&bw_config, 0, sizeof(bw_config));
4743         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4744         if (ret != I40E_SUCCESS) {
4745                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4746                             hw->aq.asq_last_status);
4747                 return ret;
4748         }
4749
4750         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4751         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4752                                         &ets_sla_config, NULL);
4753         if (ret != I40E_SUCCESS) {
4754                 PMD_DRV_LOG(ERR,
4755                         "VSI failed to get TC bandwdith configuration %u",
4756                         hw->aq.asq_last_status);
4757                 return ret;
4758         }
4759
4760         /* store and print out BW info */
4761         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4762         vsi->bw_info.bw_max = bw_config.max_bw;
4763         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4764         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4765         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4766                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4767                      I40E_16_BIT_WIDTH);
4768         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4769                 vsi->bw_info.bw_ets_share_credits[i] =
4770                                 ets_sla_config.share_credits[i];
4771                 vsi->bw_info.bw_ets_credits[i] =
4772                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4773                 /* 4 bits per TC, 4th bit is reserved */
4774                 vsi->bw_info.bw_ets_max[i] =
4775                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4776                                   RTE_LEN2MASK(3, uint8_t));
4777                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4778                             vsi->bw_info.bw_ets_share_credits[i]);
4779                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4780                             vsi->bw_info.bw_ets_credits[i]);
4781                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4782                             vsi->bw_info.bw_ets_max[i]);
4783         }
4784
4785         return I40E_SUCCESS;
4786 }
4787
4788 /* i40e_enable_pf_lb
4789  * @pf: pointer to the pf structure
4790  *
4791  * allow loopback on pf
4792  */
4793 static inline void
4794 i40e_enable_pf_lb(struct i40e_pf *pf)
4795 {
4796         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4797         struct i40e_vsi_context ctxt;
4798         int ret;
4799
4800         /* Use the FW API if FW >= v5.0 */
4801         if (hw->aq.fw_maj_ver < 5) {
4802                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4803                 return;
4804         }
4805
4806         memset(&ctxt, 0, sizeof(ctxt));
4807         ctxt.seid = pf->main_vsi_seid;
4808         ctxt.pf_num = hw->pf_id;
4809         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4810         if (ret) {
4811                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4812                             ret, hw->aq.asq_last_status);
4813                 return;
4814         }
4815         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4816         ctxt.info.valid_sections =
4817                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4818         ctxt.info.switch_id |=
4819                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4820
4821         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4822         if (ret)
4823                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4824                             hw->aq.asq_last_status);
4825 }
4826
4827 /* Setup a VSI */
4828 struct i40e_vsi *
4829 i40e_vsi_setup(struct i40e_pf *pf,
4830                enum i40e_vsi_type type,
4831                struct i40e_vsi *uplink_vsi,
4832                uint16_t user_param)
4833 {
4834         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4835         struct i40e_vsi *vsi;
4836         struct i40e_mac_filter_info filter;
4837         int ret;
4838         struct i40e_vsi_context ctxt;
4839         struct ether_addr broadcast =
4840                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4841
4842         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4843             uplink_vsi == NULL) {
4844                 PMD_DRV_LOG(ERR,
4845                         "VSI setup failed, VSI link shouldn't be NULL");
4846                 return NULL;
4847         }
4848
4849         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4850                 PMD_DRV_LOG(ERR,
4851                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4852                 return NULL;
4853         }
4854
4855         /* two situations
4856          * 1.type is not MAIN and uplink vsi is not NULL
4857          * If uplink vsi didn't setup VEB, create one first under veb field
4858          * 2.type is SRIOV and the uplink is NULL
4859          * If floating VEB is NULL, create one veb under floating veb field
4860          */
4861
4862         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4863             uplink_vsi->veb == NULL) {
4864                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4865
4866                 if (uplink_vsi->veb == NULL) {
4867                         PMD_DRV_LOG(ERR, "VEB setup failed");
4868                         return NULL;
4869                 }
4870                 /* set ALLOWLOOPBACk on pf, when veb is created */
4871                 i40e_enable_pf_lb(pf);
4872         }
4873
4874         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4875             pf->main_vsi->floating_veb == NULL) {
4876                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4877
4878                 if (pf->main_vsi->floating_veb == NULL) {
4879                         PMD_DRV_LOG(ERR, "VEB setup failed");
4880                         return NULL;
4881                 }
4882         }
4883
4884         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4885         if (!vsi) {
4886                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4887                 return NULL;
4888         }
4889         TAILQ_INIT(&vsi->mac_list);
4890         vsi->type = type;
4891         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4892         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4893         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4894         vsi->user_param = user_param;
4895         vsi->vlan_anti_spoof_on = 0;
4896         vsi->vlan_filter_on = 0;
4897         /* Allocate queues */
4898         switch (vsi->type) {
4899         case I40E_VSI_MAIN  :
4900                 vsi->nb_qps = pf->lan_nb_qps;
4901                 break;
4902         case I40E_VSI_SRIOV :
4903                 vsi->nb_qps = pf->vf_nb_qps;
4904                 break;
4905         case I40E_VSI_VMDQ2:
4906                 vsi->nb_qps = pf->vmdq_nb_qps;
4907                 break;
4908         case I40E_VSI_FDIR:
4909                 vsi->nb_qps = pf->fdir_nb_qps;
4910                 break;
4911         default:
4912                 goto fail_mem;
4913         }
4914         /*
4915          * The filter status descriptor is reported in rx queue 0,
4916          * while the tx queue for fdir filter programming has no
4917          * such constraints, can be non-zero queues.
4918          * To simplify it, choose FDIR vsi use queue 0 pair.
4919          * To make sure it will use queue 0 pair, queue allocation
4920          * need be done before this function is called
4921          */
4922         if (type != I40E_VSI_FDIR) {
4923                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4924                         if (ret < 0) {
4925                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4926                                                 vsi->seid, ret);
4927                                 goto fail_mem;
4928                         }
4929                         vsi->base_queue = ret;
4930         } else
4931                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4932
4933         /* VF has MSIX interrupt in VF range, don't allocate here */
4934         if (type == I40E_VSI_MAIN) {
4935                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4936                                           RTE_MIN(vsi->nb_qps,
4937                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4938                 if (ret < 0) {
4939                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4940                                     vsi->seid, ret);
4941                         goto fail_queue_alloc;
4942                 }
4943                 vsi->msix_intr = ret;
4944                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4945         } else if (type != I40E_VSI_SRIOV) {
4946                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4947                 if (ret < 0) {
4948                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4949                         goto fail_queue_alloc;
4950                 }
4951                 vsi->msix_intr = ret;
4952                 vsi->nb_msix = 1;
4953         } else {
4954                 vsi->msix_intr = 0;
4955                 vsi->nb_msix = 0;
4956         }
4957
4958         /* Add VSI */
4959         if (type == I40E_VSI_MAIN) {
4960                 /* For main VSI, no need to add since it's default one */
4961                 vsi->uplink_seid = pf->mac_seid;
4962                 vsi->seid = pf->main_vsi_seid;
4963                 /* Bind queues with specific MSIX interrupt */
4964                 /**
4965                  * Needs 2 interrupt at least, one for misc cause which will
4966                  * enabled from OS side, Another for queues binding the
4967                  * interrupt from device side only.
4968                  */
4969
4970                 /* Get default VSI parameters from hardware */
4971                 memset(&ctxt, 0, sizeof(ctxt));
4972                 ctxt.seid = vsi->seid;
4973                 ctxt.pf_num = hw->pf_id;
4974                 ctxt.uplink_seid = vsi->uplink_seid;
4975                 ctxt.vf_num = 0;
4976                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4977                 if (ret != I40E_SUCCESS) {
4978                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4979                         goto fail_msix_alloc;
4980                 }
4981                 rte_memcpy(&vsi->info, &ctxt.info,
4982                         sizeof(struct i40e_aqc_vsi_properties_data));
4983                 vsi->vsi_id = ctxt.vsi_number;
4984                 vsi->info.valid_sections = 0;
4985
4986                 /* Configure tc, enabled TC0 only */
4987                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4988                         I40E_SUCCESS) {
4989                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4990                         goto fail_msix_alloc;
4991                 }
4992
4993                 /* TC, queue mapping */
4994                 memset(&ctxt, 0, sizeof(ctxt));
4995                 vsi->info.valid_sections |=
4996                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4997                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4998                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4999                 rte_memcpy(&ctxt.info, &vsi->info,
5000                         sizeof(struct i40e_aqc_vsi_properties_data));
5001                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5002                                                 I40E_DEFAULT_TCMAP);
5003                 if (ret != I40E_SUCCESS) {
5004                         PMD_DRV_LOG(ERR,
5005                                 "Failed to configure TC queue mapping");
5006                         goto fail_msix_alloc;
5007                 }
5008                 ctxt.seid = vsi->seid;
5009                 ctxt.pf_num = hw->pf_id;
5010                 ctxt.uplink_seid = vsi->uplink_seid;
5011                 ctxt.vf_num = 0;
5012
5013                 /* Update VSI parameters */
5014                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5015                 if (ret != I40E_SUCCESS) {
5016                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5017                         goto fail_msix_alloc;
5018                 }
5019
5020                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5021                                                 sizeof(vsi->info.tc_mapping));
5022                 rte_memcpy(&vsi->info.queue_mapping,
5023                                 &ctxt.info.queue_mapping,
5024                         sizeof(vsi->info.queue_mapping));
5025                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5026                 vsi->info.valid_sections = 0;
5027
5028                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5029                                 ETH_ADDR_LEN);
5030
5031                 /**
5032                  * Updating default filter settings are necessary to prevent
5033                  * reception of tagged packets.
5034                  * Some old firmware configurations load a default macvlan
5035                  * filter which accepts both tagged and untagged packets.
5036                  * The updating is to use a normal filter instead if needed.
5037                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5038                  * The firmware with correct configurations load the default
5039                  * macvlan filter which is expected and cannot be removed.
5040                  */
5041                 i40e_update_default_filter_setting(vsi);
5042                 i40e_config_qinq(hw, vsi);
5043         } else if (type == I40E_VSI_SRIOV) {
5044                 memset(&ctxt, 0, sizeof(ctxt));
5045                 /**
5046                  * For other VSI, the uplink_seid equals to uplink VSI's
5047                  * uplink_seid since they share same VEB
5048                  */
5049                 if (uplink_vsi == NULL)
5050                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5051                 else
5052                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5053                 ctxt.pf_num = hw->pf_id;
5054                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5055                 ctxt.uplink_seid = vsi->uplink_seid;
5056                 ctxt.connection_type = 0x1;
5057                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5058
5059                 /* Use the VEB configuration if FW >= v5.0 */
5060                 if (hw->aq.fw_maj_ver >= 5) {
5061                         /* Configure switch ID */
5062                         ctxt.info.valid_sections |=
5063                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5064                         ctxt.info.switch_id =
5065                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5066                 }
5067
5068                 /* Configure port/vlan */
5069                 ctxt.info.valid_sections |=
5070                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5071                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5072                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5073                                                 hw->func_caps.enabled_tcmap);
5074                 if (ret != I40E_SUCCESS) {
5075                         PMD_DRV_LOG(ERR,
5076                                 "Failed to configure TC queue mapping");
5077                         goto fail_msix_alloc;
5078                 }
5079
5080                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5081                 ctxt.info.valid_sections |=
5082                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5083                 /**
5084                  * Since VSI is not created yet, only configure parameter,
5085                  * will add vsi below.
5086                  */
5087
5088                 i40e_config_qinq(hw, vsi);
5089         } else if (type == I40E_VSI_VMDQ2) {
5090                 memset(&ctxt, 0, sizeof(ctxt));
5091                 /*
5092                  * For other VSI, the uplink_seid equals to uplink VSI's
5093                  * uplink_seid since they share same VEB
5094                  */
5095                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5096                 ctxt.pf_num = hw->pf_id;
5097                 ctxt.vf_num = 0;
5098                 ctxt.uplink_seid = vsi->uplink_seid;
5099                 ctxt.connection_type = 0x1;
5100                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5101
5102                 ctxt.info.valid_sections |=
5103                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5104                 /* user_param carries flag to enable loop back */
5105                 if (user_param) {
5106                         ctxt.info.switch_id =
5107                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5108                         ctxt.info.switch_id |=
5109                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5110                 }
5111
5112                 /* Configure port/vlan */
5113                 ctxt.info.valid_sections |=
5114                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5115                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5116                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5117                                                 I40E_DEFAULT_TCMAP);
5118                 if (ret != I40E_SUCCESS) {
5119                         PMD_DRV_LOG(ERR,
5120                                 "Failed to configure TC queue mapping");
5121                         goto fail_msix_alloc;
5122                 }
5123                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5124                 ctxt.info.valid_sections |=
5125                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5126         } else if (type == I40E_VSI_FDIR) {
5127                 memset(&ctxt, 0, sizeof(ctxt));
5128                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5129                 ctxt.pf_num = hw->pf_id;
5130                 ctxt.vf_num = 0;
5131                 ctxt.uplink_seid = vsi->uplink_seid;
5132                 ctxt.connection_type = 0x1;     /* regular data port */
5133                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5134                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5135                                                 I40E_DEFAULT_TCMAP);
5136                 if (ret != I40E_SUCCESS) {
5137                         PMD_DRV_LOG(ERR,
5138                                 "Failed to configure TC queue mapping.");
5139                         goto fail_msix_alloc;
5140                 }
5141                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5142                 ctxt.info.valid_sections |=
5143                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5144         } else {
5145                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5146                 goto fail_msix_alloc;
5147         }
5148
5149         if (vsi->type != I40E_VSI_MAIN) {
5150                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5151                 if (ret != I40E_SUCCESS) {
5152                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5153                                     hw->aq.asq_last_status);
5154                         goto fail_msix_alloc;
5155                 }
5156                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5157                 vsi->info.valid_sections = 0;
5158                 vsi->seid = ctxt.seid;
5159                 vsi->vsi_id = ctxt.vsi_number;
5160                 vsi->sib_vsi_list.vsi = vsi;
5161                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5162                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5163                                           &vsi->sib_vsi_list, list);
5164                 } else {
5165                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5166                                           &vsi->sib_vsi_list, list);
5167                 }
5168         }
5169
5170         /* MAC/VLAN configuration */
5171         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5172         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5173
5174         ret = i40e_vsi_add_mac(vsi, &filter);
5175         if (ret != I40E_SUCCESS) {
5176                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5177                 goto fail_msix_alloc;
5178         }
5179
5180         /* Get VSI BW information */
5181         i40e_vsi_get_bw_config(vsi);
5182         return vsi;
5183 fail_msix_alloc:
5184         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5185 fail_queue_alloc:
5186         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5187 fail_mem:
5188         rte_free(vsi);
5189         return NULL;
5190 }
5191
5192 /* Configure vlan filter on or off */
5193 int
5194 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5195 {
5196         int i, num;
5197         struct i40e_mac_filter *f;
5198         void *temp;
5199         struct i40e_mac_filter_info *mac_filter;
5200         enum rte_mac_filter_type desired_filter;
5201         int ret = I40E_SUCCESS;
5202
5203         if (on) {
5204                 /* Filter to match MAC and VLAN */
5205                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5206         } else {
5207                 /* Filter to match only MAC */
5208                 desired_filter = RTE_MAC_PERFECT_MATCH;
5209         }
5210
5211         num = vsi->mac_num;
5212
5213         mac_filter = rte_zmalloc("mac_filter_info_data",
5214                                  num * sizeof(*mac_filter), 0);
5215         if (mac_filter == NULL) {
5216                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5217                 return I40E_ERR_NO_MEMORY;
5218         }
5219
5220         i = 0;
5221
5222         /* Remove all existing mac */
5223         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5224                 mac_filter[i] = f->mac_info;
5225                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5226                 if (ret) {
5227                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5228                                     on ? "enable" : "disable");
5229                         goto DONE;
5230                 }
5231                 i++;
5232         }
5233
5234         /* Override with new filter */
5235         for (i = 0; i < num; i++) {
5236                 mac_filter[i].filter_type = desired_filter;
5237                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5238                 if (ret) {
5239                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5240                                     on ? "enable" : "disable");
5241                         goto DONE;
5242                 }
5243         }
5244
5245 DONE:
5246         rte_free(mac_filter);
5247         return ret;
5248 }
5249
5250 /* Configure vlan stripping on or off */
5251 int
5252 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5253 {
5254         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5255         struct i40e_vsi_context ctxt;
5256         uint8_t vlan_flags;
5257         int ret = I40E_SUCCESS;
5258
5259         /* Check if it has been already on or off */
5260         if (vsi->info.valid_sections &
5261                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5262                 if (on) {
5263                         if ((vsi->info.port_vlan_flags &
5264                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5265                                 return 0; /* already on */
5266                 } else {
5267                         if ((vsi->info.port_vlan_flags &
5268                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5269                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5270                                 return 0; /* already off */
5271                 }
5272         }
5273
5274         if (on)
5275                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5276         else
5277                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5278         vsi->info.valid_sections =
5279                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5280         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5281         vsi->info.port_vlan_flags |= vlan_flags;
5282         ctxt.seid = vsi->seid;
5283         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5284         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5285         if (ret)
5286                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5287                             on ? "enable" : "disable");
5288
5289         return ret;
5290 }
5291
5292 static int
5293 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5294 {
5295         struct rte_eth_dev_data *data = dev->data;
5296         int ret;
5297         int mask = 0;
5298
5299         /* Apply vlan offload setting */
5300         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5301         i40e_vlan_offload_set(dev, mask);
5302
5303         /* Apply double-vlan setting, not implemented yet */
5304
5305         /* Apply pvid setting */
5306         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5307                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5308         if (ret)
5309                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5310
5311         return ret;
5312 }
5313
5314 static int
5315 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5316 {
5317         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5318
5319         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5320 }
5321
5322 static int
5323 i40e_update_flow_control(struct i40e_hw *hw)
5324 {
5325 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5326         struct i40e_link_status link_status;
5327         uint32_t rxfc = 0, txfc = 0, reg;
5328         uint8_t an_info;
5329         int ret;
5330
5331         memset(&link_status, 0, sizeof(link_status));
5332         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5333         if (ret != I40E_SUCCESS) {
5334                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5335                 goto write_reg; /* Disable flow control */
5336         }
5337
5338         an_info = hw->phy.link_info.an_info;
5339         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5340                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5341                 ret = I40E_ERR_NOT_READY;
5342                 goto write_reg; /* Disable flow control */
5343         }
5344         /**
5345          * If link auto negotiation is enabled, flow control needs to
5346          * be configured according to it
5347          */
5348         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5349         case I40E_LINK_PAUSE_RXTX:
5350                 rxfc = 1;
5351                 txfc = 1;
5352                 hw->fc.current_mode = I40E_FC_FULL;
5353                 break;
5354         case I40E_AQ_LINK_PAUSE_RX:
5355                 rxfc = 1;
5356                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5357                 break;
5358         case I40E_AQ_LINK_PAUSE_TX:
5359                 txfc = 1;
5360                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5361                 break;
5362         default:
5363                 hw->fc.current_mode = I40E_FC_NONE;
5364                 break;
5365         }
5366
5367 write_reg:
5368         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5369                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5370         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5371         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5372         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5373         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5374
5375         return ret;
5376 }
5377
5378 /* PF setup */
5379 static int
5380 i40e_pf_setup(struct i40e_pf *pf)
5381 {
5382         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5383         struct i40e_filter_control_settings settings;
5384         struct i40e_vsi *vsi;
5385         int ret;
5386
5387         /* Clear all stats counters */
5388         pf->offset_loaded = FALSE;
5389         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5390         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5391         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5392         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5393
5394         ret = i40e_pf_get_switch_config(pf);
5395         if (ret != I40E_SUCCESS) {
5396                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5397                 return ret;
5398         }
5399         if (pf->flags & I40E_FLAG_FDIR) {
5400                 /* make queue allocated first, let FDIR use queue pair 0*/
5401                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5402                 if (ret != I40E_FDIR_QUEUE_ID) {
5403                         PMD_DRV_LOG(ERR,
5404                                 "queue allocation fails for FDIR: ret =%d",
5405                                 ret);
5406                         pf->flags &= ~I40E_FLAG_FDIR;
5407                 }
5408         }
5409         /*  main VSI setup */
5410         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5411         if (!vsi) {
5412                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5413                 return I40E_ERR_NOT_READY;
5414         }
5415         pf->main_vsi = vsi;
5416
5417         /* Configure filter control */
5418         memset(&settings, 0, sizeof(settings));
5419         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5420                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5421         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5422                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5423         else {
5424                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5425                         hw->func_caps.rss_table_size);
5426                 return I40E_ERR_PARAM;
5427         }
5428         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5429                 hw->func_caps.rss_table_size);
5430         pf->hash_lut_size = hw->func_caps.rss_table_size;
5431
5432         /* Enable ethtype and macvlan filters */
5433         settings.enable_ethtype = TRUE;
5434         settings.enable_macvlan = TRUE;
5435         ret = i40e_set_filter_control(hw, &settings);
5436         if (ret)
5437                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5438                                                                 ret);
5439
5440         /* Update flow control according to the auto negotiation */
5441         i40e_update_flow_control(hw);
5442
5443         return I40E_SUCCESS;
5444 }
5445
5446 int
5447 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5448 {
5449         uint32_t reg;
5450         uint16_t j;
5451
5452         /**
5453          * Set or clear TX Queue Disable flags,
5454          * which is required by hardware.
5455          */
5456         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5457         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5458
5459         /* Wait until the request is finished */
5460         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5461                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5462                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5463                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5464                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5465                                                         & 0x1))) {
5466                         break;
5467                 }
5468         }
5469         if (on) {
5470                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5471                         return I40E_SUCCESS; /* already on, skip next steps */
5472
5473                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5474                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5475         } else {
5476                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5477                         return I40E_SUCCESS; /* already off, skip next steps */
5478                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5479         }
5480         /* Write the register */
5481         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5482         /* Check the result */
5483         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5484                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5485                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5486                 if (on) {
5487                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5488                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5489                                 break;
5490                 } else {
5491                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5492                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5493                                 break;
5494                 }
5495         }
5496         /* Check if it is timeout */
5497         if (j >= I40E_CHK_Q_ENA_COUNT) {
5498                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5499                             (on ? "enable" : "disable"), q_idx);
5500                 return I40E_ERR_TIMEOUT;
5501         }
5502
5503         return I40E_SUCCESS;
5504 }
5505
5506 /* Swith on or off the tx queues */
5507 static int
5508 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5509 {
5510         struct rte_eth_dev_data *dev_data = pf->dev_data;
5511         struct i40e_tx_queue *txq;
5512         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5513         uint16_t i;
5514         int ret;
5515
5516         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5517                 txq = dev_data->tx_queues[i];
5518                 /* Don't operate the queue if not configured or
5519                  * if starting only per queue */
5520                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5521                         continue;
5522                 if (on)
5523                         ret = i40e_dev_tx_queue_start(dev, i);
5524                 else
5525                         ret = i40e_dev_tx_queue_stop(dev, i);
5526                 if ( ret != I40E_SUCCESS)
5527                         return ret;
5528         }
5529
5530         return I40E_SUCCESS;
5531 }
5532
5533 int
5534 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5535 {
5536         uint32_t reg;
5537         uint16_t j;
5538
5539         /* Wait until the request is finished */
5540         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5541                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5542                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5543                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5544                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5545                         break;
5546         }
5547
5548         if (on) {
5549                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5550                         return I40E_SUCCESS; /* Already on, skip next steps */
5551                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5552         } else {
5553                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5554                         return I40E_SUCCESS; /* Already off, skip next steps */
5555                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5556         }
5557
5558         /* Write the register */
5559         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5560         /* Check the result */
5561         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5562                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5563                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5564                 if (on) {
5565                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5566                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5567                                 break;
5568                 } else {
5569                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5570                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5571                                 break;
5572                 }
5573         }
5574
5575         /* Check if it is timeout */
5576         if (j >= I40E_CHK_Q_ENA_COUNT) {
5577                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5578                             (on ? "enable" : "disable"), q_idx);
5579                 return I40E_ERR_TIMEOUT;
5580         }
5581
5582         return I40E_SUCCESS;
5583 }
5584 /* Switch on or off the rx queues */
5585 static int
5586 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5587 {
5588         struct rte_eth_dev_data *dev_data = pf->dev_data;
5589         struct i40e_rx_queue *rxq;
5590         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5591         uint16_t i;
5592         int ret;
5593
5594         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5595                 rxq = dev_data->rx_queues[i];
5596                 /* Don't operate the queue if not configured or
5597                  * if starting only per queue */
5598                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5599                         continue;
5600                 if (on)
5601                         ret = i40e_dev_rx_queue_start(dev, i);
5602                 else
5603                         ret = i40e_dev_rx_queue_stop(dev, i);
5604                 if (ret != I40E_SUCCESS)
5605                         return ret;
5606         }
5607
5608         return I40E_SUCCESS;
5609 }
5610
5611 /* Switch on or off all the rx/tx queues */
5612 int
5613 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5614 {
5615         int ret;
5616
5617         if (on) {
5618                 /* enable rx queues before enabling tx queues */
5619                 ret = i40e_dev_switch_rx_queues(pf, on);
5620                 if (ret) {
5621                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5622                         return ret;
5623                 }
5624                 ret = i40e_dev_switch_tx_queues(pf, on);
5625         } else {
5626                 /* Stop tx queues before stopping rx queues */
5627                 ret = i40e_dev_switch_tx_queues(pf, on);
5628                 if (ret) {
5629                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5630                         return ret;
5631                 }
5632                 ret = i40e_dev_switch_rx_queues(pf, on);
5633         }
5634
5635         return ret;
5636 }
5637
5638 /* Initialize VSI for TX */
5639 static int
5640 i40e_dev_tx_init(struct i40e_pf *pf)
5641 {
5642         struct rte_eth_dev_data *data = pf->dev_data;
5643         uint16_t i;
5644         uint32_t ret = I40E_SUCCESS;
5645         struct i40e_tx_queue *txq;
5646
5647         for (i = 0; i < data->nb_tx_queues; i++) {
5648                 txq = data->tx_queues[i];
5649                 if (!txq || !txq->q_set)
5650                         continue;
5651                 ret = i40e_tx_queue_init(txq);
5652                 if (ret != I40E_SUCCESS)
5653                         break;
5654         }
5655         if (ret == I40E_SUCCESS)
5656                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5657                                      ->eth_dev);
5658
5659         return ret;
5660 }
5661
5662 /* Initialize VSI for RX */
5663 static int
5664 i40e_dev_rx_init(struct i40e_pf *pf)
5665 {
5666         struct rte_eth_dev_data *data = pf->dev_data;
5667         int ret = I40E_SUCCESS;
5668         uint16_t i;
5669         struct i40e_rx_queue *rxq;
5670
5671         i40e_pf_config_mq_rx(pf);
5672         for (i = 0; i < data->nb_rx_queues; i++) {
5673                 rxq = data->rx_queues[i];
5674                 if (!rxq || !rxq->q_set)
5675                         continue;
5676
5677                 ret = i40e_rx_queue_init(rxq);
5678                 if (ret != I40E_SUCCESS) {
5679                         PMD_DRV_LOG(ERR,
5680                                 "Failed to do RX queue initialization");
5681                         break;
5682                 }
5683         }
5684         if (ret == I40E_SUCCESS)
5685                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5686                                      ->eth_dev);
5687
5688         return ret;
5689 }
5690
5691 static int
5692 i40e_dev_rxtx_init(struct i40e_pf *pf)
5693 {
5694         int err;
5695
5696         err = i40e_dev_tx_init(pf);
5697         if (err) {
5698                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5699                 return err;
5700         }
5701         err = i40e_dev_rx_init(pf);
5702         if (err) {
5703                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5704                 return err;
5705         }
5706
5707         return err;
5708 }
5709
5710 static int
5711 i40e_vmdq_setup(struct rte_eth_dev *dev)
5712 {
5713         struct rte_eth_conf *conf = &dev->data->dev_conf;
5714         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5715         int i, err, conf_vsis, j, loop;
5716         struct i40e_vsi *vsi;
5717         struct i40e_vmdq_info *vmdq_info;
5718         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5719         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5720
5721         /*
5722          * Disable interrupt to avoid message from VF. Furthermore, it will
5723          * avoid race condition in VSI creation/destroy.
5724          */
5725         i40e_pf_disable_irq0(hw);
5726
5727         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5728                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5729                 return -ENOTSUP;
5730         }
5731
5732         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5733         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5734                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5735                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5736                         pf->max_nb_vmdq_vsi);
5737                 return -ENOTSUP;
5738         }
5739
5740         if (pf->vmdq != NULL) {
5741                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5742                 return 0;
5743         }
5744
5745         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5746                                 sizeof(*vmdq_info) * conf_vsis, 0);
5747
5748         if (pf->vmdq == NULL) {
5749                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5750                 return -ENOMEM;
5751         }
5752
5753         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5754
5755         /* Create VMDQ VSI */
5756         for (i = 0; i < conf_vsis; i++) {
5757                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5758                                 vmdq_conf->enable_loop_back);
5759                 if (vsi == NULL) {
5760                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5761                         err = -1;
5762                         goto err_vsi_setup;
5763                 }
5764                 vmdq_info = &pf->vmdq[i];
5765                 vmdq_info->pf = pf;
5766                 vmdq_info->vsi = vsi;
5767         }
5768         pf->nb_cfg_vmdq_vsi = conf_vsis;
5769
5770         /* Configure Vlan */
5771         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5772         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5773                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5774                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5775                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5776                                         vmdq_conf->pool_map[i].vlan_id, j);
5777
5778                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5779                                                 vmdq_conf->pool_map[i].vlan_id);
5780                                 if (err) {
5781                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5782                                         err = -1;
5783                                         goto err_vsi_setup;
5784                                 }
5785                         }
5786                 }
5787         }
5788
5789         i40e_pf_enable_irq0(hw);
5790
5791         return 0;
5792
5793 err_vsi_setup:
5794         for (i = 0; i < conf_vsis; i++)
5795                 if (pf->vmdq[i].vsi == NULL)
5796                         break;
5797                 else
5798                         i40e_vsi_release(pf->vmdq[i].vsi);
5799
5800         rte_free(pf->vmdq);
5801         pf->vmdq = NULL;
5802         i40e_pf_enable_irq0(hw);
5803         return err;
5804 }
5805
5806 static void
5807 i40e_stat_update_32(struct i40e_hw *hw,
5808                    uint32_t reg,
5809                    bool offset_loaded,
5810                    uint64_t *offset,
5811                    uint64_t *stat)
5812 {
5813         uint64_t new_data;
5814
5815         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5816         if (!offset_loaded)
5817                 *offset = new_data;
5818
5819         if (new_data >= *offset)
5820                 *stat = (uint64_t)(new_data - *offset);
5821         else
5822                 *stat = (uint64_t)((new_data +
5823                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5824 }
5825
5826 static void
5827 i40e_stat_update_48(struct i40e_hw *hw,
5828                    uint32_t hireg,
5829                    uint32_t loreg,
5830                    bool offset_loaded,
5831                    uint64_t *offset,
5832                    uint64_t *stat)
5833 {
5834         uint64_t new_data;
5835
5836         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5837         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5838                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5839
5840         if (!offset_loaded)
5841                 *offset = new_data;
5842
5843         if (new_data >= *offset)
5844                 *stat = new_data - *offset;
5845         else
5846                 *stat = (uint64_t)((new_data +
5847                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5848
5849         *stat &= I40E_48_BIT_MASK;
5850 }
5851
5852 /* Disable IRQ0 */
5853 void
5854 i40e_pf_disable_irq0(struct i40e_hw *hw)
5855 {
5856         /* Disable all interrupt types */
5857         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5858         I40E_WRITE_FLUSH(hw);
5859 }
5860
5861 /* Enable IRQ0 */
5862 void
5863 i40e_pf_enable_irq0(struct i40e_hw *hw)
5864 {
5865         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5866                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5867                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5868                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5869         I40E_WRITE_FLUSH(hw);
5870 }
5871
5872 static void
5873 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5874 {
5875         /* read pending request and disable first */
5876         i40e_pf_disable_irq0(hw);
5877         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5878         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5879                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5880
5881         if (no_queue)
5882                 /* Link no queues with irq0 */
5883                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5884                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5885 }
5886
5887 static void
5888 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5889 {
5890         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5891         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5892         int i;
5893         uint16_t abs_vf_id;
5894         uint32_t index, offset, val;
5895
5896         if (!pf->vfs)
5897                 return;
5898         /**
5899          * Try to find which VF trigger a reset, use absolute VF id to access
5900          * since the reg is global register.
5901          */
5902         for (i = 0; i < pf->vf_num; i++) {
5903                 abs_vf_id = hw->func_caps.vf_base_id + i;
5904                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5905                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5906                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5907                 /* VFR event occurred */
5908                 if (val & (0x1 << offset)) {
5909                         int ret;
5910
5911                         /* Clear the event first */
5912                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5913                                                         (0x1 << offset));
5914                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5915                         /**
5916                          * Only notify a VF reset event occurred,
5917                          * don't trigger another SW reset
5918                          */
5919                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5920                         if (ret != I40E_SUCCESS)
5921                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5922                 }
5923         }
5924 }
5925
5926 static void
5927 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5928 {
5929         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5930         int i;
5931
5932         for (i = 0; i < pf->vf_num; i++)
5933                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5934 }
5935
5936 static void
5937 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5938 {
5939         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5940         struct i40e_arq_event_info info;
5941         uint16_t pending, opcode;
5942         int ret;
5943
5944         info.buf_len = I40E_AQ_BUF_SZ;
5945         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5946         if (!info.msg_buf) {
5947                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5948                 return;
5949         }
5950
5951         pending = 1;
5952         while (pending) {
5953                 ret = i40e_clean_arq_element(hw, &info, &pending);
5954
5955                 if (ret != I40E_SUCCESS) {
5956                         PMD_DRV_LOG(INFO,
5957                                 "Failed to read msg from AdminQ, aq_err: %u",
5958                                 hw->aq.asq_last_status);
5959                         break;
5960                 }
5961                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5962
5963                 switch (opcode) {
5964                 case i40e_aqc_opc_send_msg_to_pf:
5965                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5966                         i40e_pf_host_handle_vf_msg(dev,
5967                                         rte_le_to_cpu_16(info.desc.retval),
5968                                         rte_le_to_cpu_32(info.desc.cookie_high),
5969                                         rte_le_to_cpu_32(info.desc.cookie_low),
5970                                         info.msg_buf,
5971                                         info.msg_len);
5972                         break;
5973                 case i40e_aqc_opc_get_link_status:
5974                         ret = i40e_dev_link_update(dev, 0);
5975                         if (!ret)
5976                                 _rte_eth_dev_callback_process(dev,
5977                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5978                         break;
5979                 default:
5980                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5981                                     opcode);
5982                         break;
5983                 }
5984         }
5985         rte_free(info.msg_buf);
5986 }
5987
5988 /**
5989  * Interrupt handler triggered by NIC  for handling
5990  * specific interrupt.
5991  *
5992  * @param handle
5993  *  Pointer to interrupt handle.
5994  * @param param
5995  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5996  *
5997  * @return
5998  *  void
5999  */
6000 static void
6001 i40e_dev_interrupt_handler(void *param)
6002 {
6003         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6004         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6005         uint32_t icr0;
6006
6007         /* Disable interrupt */
6008         i40e_pf_disable_irq0(hw);
6009
6010         /* read out interrupt causes */
6011         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6012
6013         /* No interrupt event indicated */
6014         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6015                 PMD_DRV_LOG(INFO, "No interrupt event");
6016                 goto done;
6017         }
6018         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6019                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6020         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6021                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6022         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6023                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6024         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6025                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6026         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6027                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6028         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6029                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6030         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6031                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6032
6033         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6034                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6035                 i40e_dev_handle_vfr_event(dev);
6036         }
6037         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6038                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6039                 i40e_dev_handle_aq_msg(dev);
6040         }
6041
6042 done:
6043         /* Enable interrupt */
6044         i40e_pf_enable_irq0(hw);
6045         rte_intr_enable(dev->intr_handle);
6046 }
6047
6048 int
6049 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6050                          struct i40e_macvlan_filter *filter,
6051                          int total)
6052 {
6053         int ele_num, ele_buff_size;
6054         int num, actual_num, i;
6055         uint16_t flags;
6056         int ret = I40E_SUCCESS;
6057         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6058         struct i40e_aqc_add_macvlan_element_data *req_list;
6059
6060         if (filter == NULL  || total == 0)
6061                 return I40E_ERR_PARAM;
6062         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6063         ele_buff_size = hw->aq.asq_buf_size;
6064
6065         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6066         if (req_list == NULL) {
6067                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6068                 return I40E_ERR_NO_MEMORY;
6069         }
6070
6071         num = 0;
6072         do {
6073                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6074                 memset(req_list, 0, ele_buff_size);
6075
6076                 for (i = 0; i < actual_num; i++) {
6077                         rte_memcpy(req_list[i].mac_addr,
6078                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6079                         req_list[i].vlan_tag =
6080                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6081
6082                         switch (filter[num + i].filter_type) {
6083                         case RTE_MAC_PERFECT_MATCH:
6084                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6085                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6086                                 break;
6087                         case RTE_MACVLAN_PERFECT_MATCH:
6088                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6089                                 break;
6090                         case RTE_MAC_HASH_MATCH:
6091                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6092                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6093                                 break;
6094                         case RTE_MACVLAN_HASH_MATCH:
6095                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6096                                 break;
6097                         default:
6098                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6099                                 ret = I40E_ERR_PARAM;
6100                                 goto DONE;
6101                         }
6102
6103                         req_list[i].queue_number = 0;
6104
6105                         req_list[i].flags = rte_cpu_to_le_16(flags);
6106                 }
6107
6108                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6109                                                 actual_num, NULL);
6110                 if (ret != I40E_SUCCESS) {
6111                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6112                         goto DONE;
6113                 }
6114                 num += actual_num;
6115         } while (num < total);
6116
6117 DONE:
6118         rte_free(req_list);
6119         return ret;
6120 }
6121
6122 int
6123 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6124                             struct i40e_macvlan_filter *filter,
6125                             int total)
6126 {
6127         int ele_num, ele_buff_size;
6128         int num, actual_num, i;
6129         uint16_t flags;
6130         int ret = I40E_SUCCESS;
6131         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6132         struct i40e_aqc_remove_macvlan_element_data *req_list;
6133
6134         if (filter == NULL  || total == 0)
6135                 return I40E_ERR_PARAM;
6136
6137         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6138         ele_buff_size = hw->aq.asq_buf_size;
6139
6140         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6141         if (req_list == NULL) {
6142                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6143                 return I40E_ERR_NO_MEMORY;
6144         }
6145
6146         num = 0;
6147         do {
6148                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6149                 memset(req_list, 0, ele_buff_size);
6150
6151                 for (i = 0; i < actual_num; i++) {
6152                         rte_memcpy(req_list[i].mac_addr,
6153                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6154                         req_list[i].vlan_tag =
6155                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6156
6157                         switch (filter[num + i].filter_type) {
6158                         case RTE_MAC_PERFECT_MATCH:
6159                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6160                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6161                                 break;
6162                         case RTE_MACVLAN_PERFECT_MATCH:
6163                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6164                                 break;
6165                         case RTE_MAC_HASH_MATCH:
6166                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6167                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6168                                 break;
6169                         case RTE_MACVLAN_HASH_MATCH:
6170                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6171                                 break;
6172                         default:
6173                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6174                                 ret = I40E_ERR_PARAM;
6175                                 goto DONE;
6176                         }
6177                         req_list[i].flags = rte_cpu_to_le_16(flags);
6178                 }
6179
6180                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6181                                                 actual_num, NULL);
6182                 if (ret != I40E_SUCCESS) {
6183                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6184                         goto DONE;
6185                 }
6186                 num += actual_num;
6187         } while (num < total);
6188
6189 DONE:
6190         rte_free(req_list);
6191         return ret;
6192 }
6193
6194 /* Find out specific MAC filter */
6195 static struct i40e_mac_filter *
6196 i40e_find_mac_filter(struct i40e_vsi *vsi,
6197                          struct ether_addr *macaddr)
6198 {
6199         struct i40e_mac_filter *f;
6200
6201         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6202                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6203                         return f;
6204         }
6205
6206         return NULL;
6207 }
6208
6209 static bool
6210 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6211                          uint16_t vlan_id)
6212 {
6213         uint32_t vid_idx, vid_bit;
6214
6215         if (vlan_id > ETH_VLAN_ID_MAX)
6216                 return 0;
6217
6218         vid_idx = I40E_VFTA_IDX(vlan_id);
6219         vid_bit = I40E_VFTA_BIT(vlan_id);
6220
6221         if (vsi->vfta[vid_idx] & vid_bit)
6222                 return 1;
6223         else
6224                 return 0;
6225 }
6226
6227 static void
6228 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6229                        uint16_t vlan_id, bool on)
6230 {
6231         uint32_t vid_idx, vid_bit;
6232
6233         vid_idx = I40E_VFTA_IDX(vlan_id);
6234         vid_bit = I40E_VFTA_BIT(vlan_id);
6235
6236         if (on)
6237                 vsi->vfta[vid_idx] |= vid_bit;
6238         else
6239                 vsi->vfta[vid_idx] &= ~vid_bit;
6240 }
6241
6242 void
6243 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6244                      uint16_t vlan_id, bool on)
6245 {
6246         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6247         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6248         int ret;
6249
6250         if (vlan_id > ETH_VLAN_ID_MAX)
6251                 return;
6252
6253         i40e_store_vlan_filter(vsi, vlan_id, on);
6254
6255         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6256                 return;
6257
6258         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6259
6260         if (on) {
6261                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6262                                        &vlan_data, 1, NULL);
6263                 if (ret != I40E_SUCCESS)
6264                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6265         } else {
6266                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6267                                           &vlan_data, 1, NULL);
6268                 if (ret != I40E_SUCCESS)
6269                         PMD_DRV_LOG(ERR,
6270                                     "Failed to remove vlan filter");
6271         }
6272 }
6273
6274 /**
6275  * Find all vlan options for specific mac addr,
6276  * return with actual vlan found.
6277  */
6278 int
6279 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6280                            struct i40e_macvlan_filter *mv_f,
6281                            int num, struct ether_addr *addr)
6282 {
6283         int i;
6284         uint32_t j, k;
6285
6286         /**
6287          * Not to use i40e_find_vlan_filter to decrease the loop time,
6288          * although the code looks complex.
6289           */
6290         if (num < vsi->vlan_num)
6291                 return I40E_ERR_PARAM;
6292
6293         i = 0;
6294         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6295                 if (vsi->vfta[j]) {
6296                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6297                                 if (vsi->vfta[j] & (1 << k)) {
6298                                         if (i > num - 1) {
6299                                                 PMD_DRV_LOG(ERR,
6300                                                         "vlan number doesn't match");
6301                                                 return I40E_ERR_PARAM;
6302                                         }
6303                                         rte_memcpy(&mv_f[i].macaddr,
6304                                                         addr, ETH_ADDR_LEN);
6305                                         mv_f[i].vlan_id =
6306                                                 j * I40E_UINT32_BIT_SIZE + k;
6307                                         i++;
6308                                 }
6309                         }
6310                 }
6311         }
6312         return I40E_SUCCESS;
6313 }
6314
6315 static inline int
6316 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6317                            struct i40e_macvlan_filter *mv_f,
6318                            int num,
6319                            uint16_t vlan)
6320 {
6321         int i = 0;
6322         struct i40e_mac_filter *f;
6323
6324         if (num < vsi->mac_num)
6325                 return I40E_ERR_PARAM;
6326
6327         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6328                 if (i > num - 1) {
6329                         PMD_DRV_LOG(ERR, "buffer number not match");
6330                         return I40E_ERR_PARAM;
6331                 }
6332                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6333                                 ETH_ADDR_LEN);
6334                 mv_f[i].vlan_id = vlan;
6335                 mv_f[i].filter_type = f->mac_info.filter_type;
6336                 i++;
6337         }
6338
6339         return I40E_SUCCESS;
6340 }
6341
6342 static int
6343 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6344 {
6345         int i, j, num;
6346         struct i40e_mac_filter *f;
6347         struct i40e_macvlan_filter *mv_f;
6348         int ret = I40E_SUCCESS;
6349
6350         if (vsi == NULL || vsi->mac_num == 0)
6351                 return I40E_ERR_PARAM;
6352
6353         /* Case that no vlan is set */
6354         if (vsi->vlan_num == 0)
6355                 num = vsi->mac_num;
6356         else
6357                 num = vsi->mac_num * vsi->vlan_num;
6358
6359         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6360         if (mv_f == NULL) {
6361                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6362                 return I40E_ERR_NO_MEMORY;
6363         }
6364
6365         i = 0;
6366         if (vsi->vlan_num == 0) {
6367                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6368                         rte_memcpy(&mv_f[i].macaddr,
6369                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6370                         mv_f[i].filter_type = f->mac_info.filter_type;
6371                         mv_f[i].vlan_id = 0;
6372                         i++;
6373                 }
6374         } else {
6375                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6376                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6377                                         vsi->vlan_num, &f->mac_info.mac_addr);
6378                         if (ret != I40E_SUCCESS)
6379                                 goto DONE;
6380                         for (j = i; j < i + vsi->vlan_num; j++)
6381                                 mv_f[j].filter_type = f->mac_info.filter_type;
6382                         i += vsi->vlan_num;
6383                 }
6384         }
6385
6386         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6387 DONE:
6388         rte_free(mv_f);
6389
6390         return ret;
6391 }
6392
6393 int
6394 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6395 {
6396         struct i40e_macvlan_filter *mv_f;
6397         int mac_num;
6398         int ret = I40E_SUCCESS;
6399
6400         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6401                 return I40E_ERR_PARAM;
6402
6403         /* If it's already set, just return */
6404         if (i40e_find_vlan_filter(vsi,vlan))
6405                 return I40E_SUCCESS;
6406
6407         mac_num = vsi->mac_num;
6408
6409         if (mac_num == 0) {
6410                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6411                 return I40E_ERR_PARAM;
6412         }
6413
6414         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6415
6416         if (mv_f == NULL) {
6417                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6418                 return I40E_ERR_NO_MEMORY;
6419         }
6420
6421         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6422
6423         if (ret != I40E_SUCCESS)
6424                 goto DONE;
6425
6426         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6427
6428         if (ret != I40E_SUCCESS)
6429                 goto DONE;
6430
6431         i40e_set_vlan_filter(vsi, vlan, 1);
6432
6433         vsi->vlan_num++;
6434         ret = I40E_SUCCESS;
6435 DONE:
6436         rte_free(mv_f);
6437         return ret;
6438 }
6439
6440 int
6441 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6442 {
6443         struct i40e_macvlan_filter *mv_f;
6444         int mac_num;
6445         int ret = I40E_SUCCESS;
6446
6447         /**
6448          * Vlan 0 is the generic filter for untagged packets
6449          * and can't be removed.
6450          */
6451         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6452                 return I40E_ERR_PARAM;
6453
6454         /* If can't find it, just return */
6455         if (!i40e_find_vlan_filter(vsi, vlan))
6456                 return I40E_ERR_PARAM;
6457
6458         mac_num = vsi->mac_num;
6459
6460         if (mac_num == 0) {
6461                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6462                 return I40E_ERR_PARAM;
6463         }
6464
6465         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6466
6467         if (mv_f == NULL) {
6468                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6469                 return I40E_ERR_NO_MEMORY;
6470         }
6471
6472         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6473
6474         if (ret != I40E_SUCCESS)
6475                 goto DONE;
6476
6477         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6478
6479         if (ret != I40E_SUCCESS)
6480                 goto DONE;
6481
6482         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6483         if (vsi->vlan_num == 1) {
6484                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6485                 if (ret != I40E_SUCCESS)
6486                         goto DONE;
6487
6488                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6489                 if (ret != I40E_SUCCESS)
6490                         goto DONE;
6491         }
6492
6493         i40e_set_vlan_filter(vsi, vlan, 0);
6494
6495         vsi->vlan_num--;
6496         ret = I40E_SUCCESS;
6497 DONE:
6498         rte_free(mv_f);
6499         return ret;
6500 }
6501
6502 int
6503 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6504 {
6505         struct i40e_mac_filter *f;
6506         struct i40e_macvlan_filter *mv_f;
6507         int i, vlan_num = 0;
6508         int ret = I40E_SUCCESS;
6509
6510         /* If it's add and we've config it, return */
6511         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6512         if (f != NULL)
6513                 return I40E_SUCCESS;
6514         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6515                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6516
6517                 /**
6518                  * If vlan_num is 0, that's the first time to add mac,
6519                  * set mask for vlan_id 0.
6520                  */
6521                 if (vsi->vlan_num == 0) {
6522                         i40e_set_vlan_filter(vsi, 0, 1);
6523                         vsi->vlan_num = 1;
6524                 }
6525                 vlan_num = vsi->vlan_num;
6526         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6527                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6528                 vlan_num = 1;
6529
6530         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6531         if (mv_f == NULL) {
6532                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6533                 return I40E_ERR_NO_MEMORY;
6534         }
6535
6536         for (i = 0; i < vlan_num; i++) {
6537                 mv_f[i].filter_type = mac_filter->filter_type;
6538                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6539                                 ETH_ADDR_LEN);
6540         }
6541
6542         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6543                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6544                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6545                                         &mac_filter->mac_addr);
6546                 if (ret != I40E_SUCCESS)
6547                         goto DONE;
6548         }
6549
6550         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6551         if (ret != I40E_SUCCESS)
6552                 goto DONE;
6553
6554         /* Add the mac addr into mac list */
6555         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6556         if (f == NULL) {
6557                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6558                 ret = I40E_ERR_NO_MEMORY;
6559                 goto DONE;
6560         }
6561         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6562                         ETH_ADDR_LEN);
6563         f->mac_info.filter_type = mac_filter->filter_type;
6564         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6565         vsi->mac_num++;
6566
6567         ret = I40E_SUCCESS;
6568 DONE:
6569         rte_free(mv_f);
6570
6571         return ret;
6572 }
6573
6574 int
6575 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6576 {
6577         struct i40e_mac_filter *f;
6578         struct i40e_macvlan_filter *mv_f;
6579         int i, vlan_num;
6580         enum rte_mac_filter_type filter_type;
6581         int ret = I40E_SUCCESS;
6582
6583         /* Can't find it, return an error */
6584         f = i40e_find_mac_filter(vsi, addr);
6585         if (f == NULL)
6586                 return I40E_ERR_PARAM;
6587
6588         vlan_num = vsi->vlan_num;
6589         filter_type = f->mac_info.filter_type;
6590         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6591                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6592                 if (vlan_num == 0) {
6593                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6594                         return I40E_ERR_PARAM;
6595                 }
6596         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6597                         filter_type == RTE_MAC_HASH_MATCH)
6598                 vlan_num = 1;
6599
6600         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6601         if (mv_f == NULL) {
6602                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6603                 return I40E_ERR_NO_MEMORY;
6604         }
6605
6606         for (i = 0; i < vlan_num; i++) {
6607                 mv_f[i].filter_type = filter_type;
6608                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6609                                 ETH_ADDR_LEN);
6610         }
6611         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6612                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6613                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6614                 if (ret != I40E_SUCCESS)
6615                         goto DONE;
6616         }
6617
6618         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6619         if (ret != I40E_SUCCESS)
6620                 goto DONE;
6621
6622         /* Remove the mac addr into mac list */
6623         TAILQ_REMOVE(&vsi->mac_list, f, next);
6624         rte_free(f);
6625         vsi->mac_num--;
6626
6627         ret = I40E_SUCCESS;
6628 DONE:
6629         rte_free(mv_f);
6630         return ret;
6631 }
6632
6633 /* Configure hash enable flags for RSS */
6634 uint64_t
6635 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6636 {
6637         uint64_t hena = 0;
6638         int i;
6639
6640         if (!flags)
6641                 return hena;
6642
6643         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6644                 if (flags & (1ULL << i))
6645                         hena |= adapter->pctypes_tbl[i];
6646         }
6647
6648         return hena;
6649 }
6650
6651 /* Parse the hash enable flags */
6652 uint64_t
6653 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6654 {
6655         uint64_t rss_hf = 0;
6656
6657         if (!flags)
6658                 return rss_hf;
6659         int i;
6660
6661         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6662                 if (flags & adapter->pctypes_tbl[i])
6663                         rss_hf |= (1ULL << i);
6664         }
6665         return rss_hf;
6666 }
6667
6668 /* Disable RSS */
6669 static void
6670 i40e_pf_disable_rss(struct i40e_pf *pf)
6671 {
6672         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6673
6674         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6675         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6676         I40E_WRITE_FLUSH(hw);
6677 }
6678
6679 static int
6680 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6681 {
6682         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6683         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6684         int ret = 0;
6685
6686         if (!key || key_len == 0) {
6687                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6688                 return 0;
6689         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6690                 sizeof(uint32_t)) {
6691                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6692                 return -EINVAL;
6693         }
6694
6695         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6696                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6697                         (struct i40e_aqc_get_set_rss_key_data *)key;
6698
6699                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6700                 if (ret)
6701                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6702         } else {
6703                 uint32_t *hash_key = (uint32_t *)key;
6704                 uint16_t i;
6705
6706                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6707                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6708                 I40E_WRITE_FLUSH(hw);
6709         }
6710
6711         return ret;
6712 }
6713
6714 static int
6715 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6716 {
6717         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6718         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6719         int ret;
6720
6721         if (!key || !key_len)
6722                 return -EINVAL;
6723
6724         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6725                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6726                         (struct i40e_aqc_get_set_rss_key_data *)key);
6727                 if (ret) {
6728                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6729                         return ret;
6730                 }
6731         } else {
6732                 uint32_t *key_dw = (uint32_t *)key;
6733                 uint16_t i;
6734
6735                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6736                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6737         }
6738         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6739
6740         return 0;
6741 }
6742
6743 static int
6744 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6745 {
6746         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6747         uint64_t hena;
6748         int ret;
6749
6750         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6751                                rss_conf->rss_key_len);
6752         if (ret)
6753                 return ret;
6754
6755         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6756         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6757         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6758         I40E_WRITE_FLUSH(hw);
6759
6760         return 0;
6761 }
6762
6763 static int
6764 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6765                          struct rte_eth_rss_conf *rss_conf)
6766 {
6767         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6768         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6769         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6770         uint64_t hena;
6771
6772         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6773         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6774
6775         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6776                 if (rss_hf != 0) /* Enable RSS */
6777                         return -EINVAL;
6778                 return 0; /* Nothing to do */
6779         }
6780         /* RSS enabled */
6781         if (rss_hf == 0) /* Disable RSS */
6782                 return -EINVAL;
6783
6784         return i40e_hw_rss_hash_set(pf, rss_conf);
6785 }
6786
6787 static int
6788 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6789                            struct rte_eth_rss_conf *rss_conf)
6790 {
6791         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6792         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6793         uint64_t hena;
6794
6795         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6796                          &rss_conf->rss_key_len);
6797
6798         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6799         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6800         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6801
6802         return 0;
6803 }
6804
6805 static int
6806 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6807 {
6808         switch (filter_type) {
6809         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6810                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6811                 break;
6812         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6813                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6814                 break;
6815         case RTE_TUNNEL_FILTER_IMAC_TENID:
6816                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6817                 break;
6818         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6819                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6820                 break;
6821         case ETH_TUNNEL_FILTER_IMAC:
6822                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6823                 break;
6824         case ETH_TUNNEL_FILTER_OIP:
6825                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6826                 break;
6827         case ETH_TUNNEL_FILTER_IIP:
6828                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6829                 break;
6830         default:
6831                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6832                 return -EINVAL;
6833         }
6834
6835         return 0;
6836 }
6837
6838 /* Convert tunnel filter structure */
6839 static int
6840 i40e_tunnel_filter_convert(
6841         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6842         struct i40e_tunnel_filter *tunnel_filter)
6843 {
6844         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6845                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6846         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6847                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6848         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6849         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6850              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6851             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6852                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6853         else
6854                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6855         tunnel_filter->input.flags = cld_filter->element.flags;
6856         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6857         tunnel_filter->queue = cld_filter->element.queue_number;
6858         rte_memcpy(tunnel_filter->input.general_fields,
6859                    cld_filter->general_fields,
6860                    sizeof(cld_filter->general_fields));
6861
6862         return 0;
6863 }
6864
6865 /* Check if there exists the tunnel filter */
6866 struct i40e_tunnel_filter *
6867 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6868                              const struct i40e_tunnel_filter_input *input)
6869 {
6870         int ret;
6871
6872         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6873         if (ret < 0)
6874                 return NULL;
6875
6876         return tunnel_rule->hash_map[ret];
6877 }
6878
6879 /* Add a tunnel filter into the SW list */
6880 static int
6881 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6882                              struct i40e_tunnel_filter *tunnel_filter)
6883 {
6884         struct i40e_tunnel_rule *rule = &pf->tunnel;
6885         int ret;
6886
6887         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6888         if (ret < 0) {
6889                 PMD_DRV_LOG(ERR,
6890                             "Failed to insert tunnel filter to hash table %d!",
6891                             ret);
6892                 return ret;
6893         }
6894         rule->hash_map[ret] = tunnel_filter;
6895
6896         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6897
6898         return 0;
6899 }
6900
6901 /* Delete a tunnel filter from the SW list */
6902 int
6903 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6904                           struct i40e_tunnel_filter_input *input)
6905 {
6906         struct i40e_tunnel_rule *rule = &pf->tunnel;
6907         struct i40e_tunnel_filter *tunnel_filter;
6908         int ret;
6909
6910         ret = rte_hash_del_key(rule->hash_table, input);
6911         if (ret < 0) {
6912                 PMD_DRV_LOG(ERR,
6913                             "Failed to delete tunnel filter to hash table %d!",
6914                             ret);
6915                 return ret;
6916         }
6917         tunnel_filter = rule->hash_map[ret];
6918         rule->hash_map[ret] = NULL;
6919
6920         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6921         rte_free(tunnel_filter);
6922
6923         return 0;
6924 }
6925
6926 int
6927 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6928                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6929                         uint8_t add)
6930 {
6931         uint16_t ip_type;
6932         uint32_t ipv4_addr;
6933         uint8_t i, tun_type = 0;
6934         /* internal varialbe to convert ipv6 byte order */
6935         uint32_t convert_ipv6[4];
6936         int val, ret = 0;
6937         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6938         struct i40e_vsi *vsi = pf->main_vsi;
6939         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6940         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6941         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6942         struct i40e_tunnel_filter *tunnel, *node;
6943         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6944
6945         cld_filter = rte_zmalloc("tunnel_filter",
6946                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6947         0);
6948
6949         if (NULL == cld_filter) {
6950                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6951                 return -ENOMEM;
6952         }
6953         pfilter = cld_filter;
6954
6955         ether_addr_copy(&tunnel_filter->outer_mac,
6956                         (struct ether_addr *)&pfilter->element.outer_mac);
6957         ether_addr_copy(&tunnel_filter->inner_mac,
6958                         (struct ether_addr *)&pfilter->element.inner_mac);
6959
6960         pfilter->element.inner_vlan =
6961                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6962         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6963                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6964                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6965                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6966                                 &rte_cpu_to_le_32(ipv4_addr),
6967                                 sizeof(pfilter->element.ipaddr.v4.data));
6968         } else {
6969                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6970                 for (i = 0; i < 4; i++) {
6971                         convert_ipv6[i] =
6972                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6973                 }
6974                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6975                            &convert_ipv6,
6976                            sizeof(pfilter->element.ipaddr.v6.data));
6977         }
6978
6979         /* check tunneled type */
6980         switch (tunnel_filter->tunnel_type) {
6981         case RTE_TUNNEL_TYPE_VXLAN:
6982                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6983                 break;
6984         case RTE_TUNNEL_TYPE_NVGRE:
6985                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6986                 break;
6987         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6988                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6989                 break;
6990         default:
6991                 /* Other tunnel types is not supported. */
6992                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6993                 rte_free(cld_filter);
6994                 return -EINVAL;
6995         }
6996
6997         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6998                                        &pfilter->element.flags);
6999         if (val < 0) {
7000                 rte_free(cld_filter);
7001                 return -EINVAL;
7002         }
7003
7004         pfilter->element.flags |= rte_cpu_to_le_16(
7005                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7006                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7007         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7008         pfilter->element.queue_number =
7009                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7010
7011         /* Check if there is the filter in SW list */
7012         memset(&check_filter, 0, sizeof(check_filter));
7013         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7014         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7015         if (add && node) {
7016                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7017                 return -EINVAL;
7018         }
7019
7020         if (!add && !node) {
7021                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7022                 return -EINVAL;
7023         }
7024
7025         if (add) {
7026                 ret = i40e_aq_add_cloud_filters(hw,
7027                                         vsi->seid, &cld_filter->element, 1);
7028                 if (ret < 0) {
7029                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7030                         return -ENOTSUP;
7031                 }
7032                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7033                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7034                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7035         } else {
7036                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7037                                                    &cld_filter->element, 1);
7038                 if (ret < 0) {
7039                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7040                         return -ENOTSUP;
7041                 }
7042                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7043         }
7044
7045         rte_free(cld_filter);
7046         return ret;
7047 }
7048
7049 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7050 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7051 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7052 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7053 #define I40E_TR_GRE_KEY_MASK                    0x400
7054 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7055 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7056
7057 static enum
7058 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7059 {
7060         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7061         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7062         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7063         enum i40e_status_code status = I40E_SUCCESS;
7064
7065         memset(&filter_replace, 0,
7066                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7067         memset(&filter_replace_buf, 0,
7068                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7069
7070         /* create L1 filter */
7071         filter_replace.old_filter_type =
7072                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7073         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7074         filter_replace.tr_bit = 0;
7075
7076         /* Prepare the buffer, 3 entries */
7077         filter_replace_buf.data[0] =
7078                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7079         filter_replace_buf.data[0] |=
7080                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7081         filter_replace_buf.data[2] = 0xFF;
7082         filter_replace_buf.data[3] = 0xFF;
7083         filter_replace_buf.data[4] =
7084                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7085         filter_replace_buf.data[4] |=
7086                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7087         filter_replace_buf.data[7] = 0xF0;
7088         filter_replace_buf.data[8]
7089                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7090         filter_replace_buf.data[8] |=
7091                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7092         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7093                 I40E_TR_GENEVE_KEY_MASK |
7094                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7095         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7096                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7097                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7098
7099         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7100                                                &filter_replace_buf);
7101         return status;
7102 }
7103
7104 static enum
7105 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7106 {
7107         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7108         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7109         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7110         enum i40e_status_code status = I40E_SUCCESS;
7111
7112         /* For MPLSoUDP */
7113         memset(&filter_replace, 0,
7114                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7115         memset(&filter_replace_buf, 0,
7116                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7117         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7118                 I40E_AQC_MIRROR_CLOUD_FILTER;
7119         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7120         filter_replace.new_filter_type =
7121                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7122         /* Prepare the buffer, 2 entries */
7123         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7124         filter_replace_buf.data[0] |=
7125                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7126         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7127         filter_replace_buf.data[4] |=
7128                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7129         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7130                                                &filter_replace_buf);
7131         if (status < 0)
7132                 return status;
7133
7134         /* For MPLSoGRE */
7135         memset(&filter_replace, 0,
7136                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7137         memset(&filter_replace_buf, 0,
7138                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7139
7140         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7141                 I40E_AQC_MIRROR_CLOUD_FILTER;
7142         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7143         filter_replace.new_filter_type =
7144                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7145         /* Prepare the buffer, 2 entries */
7146         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7147         filter_replace_buf.data[0] |=
7148                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7149         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7150         filter_replace_buf.data[4] |=
7151                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7152
7153         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7154                                                &filter_replace_buf);
7155         return status;
7156 }
7157
7158 static enum i40e_status_code
7159 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7160 {
7161         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7162         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7163         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7164         enum i40e_status_code status = I40E_SUCCESS;
7165
7166         /* For GTP-C */
7167         memset(&filter_replace, 0,
7168                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7169         memset(&filter_replace_buf, 0,
7170                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7171         /* create L1 filter */
7172         filter_replace.old_filter_type =
7173                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7174         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7175         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7176                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7177         /* Prepare the buffer, 2 entries */
7178         filter_replace_buf.data[0] =
7179                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7180         filter_replace_buf.data[0] |=
7181                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7182         filter_replace_buf.data[2] = 0xFF;
7183         filter_replace_buf.data[3] = 0xFF;
7184         filter_replace_buf.data[4] =
7185                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7186         filter_replace_buf.data[4] |=
7187                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7188         filter_replace_buf.data[6] = 0xFF;
7189         filter_replace_buf.data[7] = 0xFF;
7190         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7191                                                &filter_replace_buf);
7192         if (status < 0)
7193                 return status;
7194
7195         /* for GTP-U */
7196         memset(&filter_replace, 0,
7197                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7198         memset(&filter_replace_buf, 0,
7199                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7200         /* create L1 filter */
7201         filter_replace.old_filter_type =
7202                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7203         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7204         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7205                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7206         /* Prepare the buffer, 2 entries */
7207         filter_replace_buf.data[0] =
7208                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7209         filter_replace_buf.data[0] |=
7210                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7211         filter_replace_buf.data[2] = 0xFF;
7212         filter_replace_buf.data[3] = 0xFF;
7213         filter_replace_buf.data[4] =
7214                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7215         filter_replace_buf.data[4] |=
7216                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7217         filter_replace_buf.data[6] = 0xFF;
7218         filter_replace_buf.data[7] = 0xFF;
7219
7220         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7221                                                &filter_replace_buf);
7222         return status;
7223 }
7224
7225 static enum
7226 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7227 {
7228         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7229         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7230         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7231         enum i40e_status_code status = I40E_SUCCESS;
7232
7233         /* for GTP-C */
7234         memset(&filter_replace, 0,
7235                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7236         memset(&filter_replace_buf, 0,
7237                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7238         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7239         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7240         filter_replace.new_filter_type =
7241                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7242         /* Prepare the buffer, 2 entries */
7243         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7244         filter_replace_buf.data[0] |=
7245                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7246         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7247         filter_replace_buf.data[4] |=
7248                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7249         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7250                                                &filter_replace_buf);
7251         if (status < 0)
7252                 return status;
7253
7254         /* for GTP-U */
7255         memset(&filter_replace, 0,
7256                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7257         memset(&filter_replace_buf, 0,
7258                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7259         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7260         filter_replace.old_filter_type =
7261                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7262         filter_replace.new_filter_type =
7263                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7264         /* Prepare the buffer, 2 entries */
7265         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7266         filter_replace_buf.data[0] |=
7267                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7268         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7269         filter_replace_buf.data[4] |=
7270                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7271
7272         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7273                                                &filter_replace_buf);
7274         return status;
7275 }
7276
7277 int
7278 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7279                       struct i40e_tunnel_filter_conf *tunnel_filter,
7280                       uint8_t add)
7281 {
7282         uint16_t ip_type;
7283         uint32_t ipv4_addr;
7284         uint8_t i, tun_type = 0;
7285         /* internal variable to convert ipv6 byte order */
7286         uint32_t convert_ipv6[4];
7287         int val, ret = 0;
7288         struct i40e_pf_vf *vf = NULL;
7289         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7290         struct i40e_vsi *vsi;
7291         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7292         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7293         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7294         struct i40e_tunnel_filter *tunnel, *node;
7295         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7296         uint32_t teid_le;
7297         bool big_buffer = 0;
7298
7299         cld_filter = rte_zmalloc("tunnel_filter",
7300                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7301                          0);
7302
7303         if (cld_filter == NULL) {
7304                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7305                 return -ENOMEM;
7306         }
7307         pfilter = cld_filter;
7308
7309         ether_addr_copy(&tunnel_filter->outer_mac,
7310                         (struct ether_addr *)&pfilter->element.outer_mac);
7311         ether_addr_copy(&tunnel_filter->inner_mac,
7312                         (struct ether_addr *)&pfilter->element.inner_mac);
7313
7314         pfilter->element.inner_vlan =
7315                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7316         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7317                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7318                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7319                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7320                                 &rte_cpu_to_le_32(ipv4_addr),
7321                                 sizeof(pfilter->element.ipaddr.v4.data));
7322         } else {
7323                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7324                 for (i = 0; i < 4; i++) {
7325                         convert_ipv6[i] =
7326                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7327                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7328                 }
7329                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7330                            &convert_ipv6,
7331                            sizeof(pfilter->element.ipaddr.v6.data));
7332         }
7333
7334         /* check tunneled type */
7335         switch (tunnel_filter->tunnel_type) {
7336         case I40E_TUNNEL_TYPE_VXLAN:
7337                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7338                 break;
7339         case I40E_TUNNEL_TYPE_NVGRE:
7340                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7341                 break;
7342         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7343                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7344                 break;
7345         case I40E_TUNNEL_TYPE_MPLSoUDP:
7346                 if (!pf->mpls_replace_flag) {
7347                         i40e_replace_mpls_l1_filter(pf);
7348                         i40e_replace_mpls_cloud_filter(pf);
7349                         pf->mpls_replace_flag = 1;
7350                 }
7351                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7352                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7353                         teid_le >> 4;
7354                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7355                         (teid_le & 0xF) << 12;
7356                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7357                         0x40;
7358                 big_buffer = 1;
7359                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7360                 break;
7361         case I40E_TUNNEL_TYPE_MPLSoGRE:
7362                 if (!pf->mpls_replace_flag) {
7363                         i40e_replace_mpls_l1_filter(pf);
7364                         i40e_replace_mpls_cloud_filter(pf);
7365                         pf->mpls_replace_flag = 1;
7366                 }
7367                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7368                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7369                         teid_le >> 4;
7370                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7371                         (teid_le & 0xF) << 12;
7372                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7373                         0x0;
7374                 big_buffer = 1;
7375                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7376                 break;
7377         case I40E_TUNNEL_TYPE_GTPC:
7378                 if (!pf->gtp_replace_flag) {
7379                         i40e_replace_gtp_l1_filter(pf);
7380                         i40e_replace_gtp_cloud_filter(pf);
7381                         pf->gtp_replace_flag = 1;
7382                 }
7383                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7384                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7385                         (teid_le >> 16) & 0xFFFF;
7386                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7387                         teid_le & 0xFFFF;
7388                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7389                         0x0;
7390                 big_buffer = 1;
7391                 break;
7392         case I40E_TUNNEL_TYPE_GTPU:
7393                 if (!pf->gtp_replace_flag) {
7394                         i40e_replace_gtp_l1_filter(pf);
7395                         i40e_replace_gtp_cloud_filter(pf);
7396                         pf->gtp_replace_flag = 1;
7397                 }
7398                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7399                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7400                         (teid_le >> 16) & 0xFFFF;
7401                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7402                         teid_le & 0xFFFF;
7403                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7404                         0x0;
7405                 big_buffer = 1;
7406                 break;
7407         case I40E_TUNNEL_TYPE_QINQ:
7408                 if (!pf->qinq_replace_flag) {
7409                         ret = i40e_cloud_filter_qinq_create(pf);
7410                         if (ret < 0)
7411                                 PMD_DRV_LOG(DEBUG,
7412                                             "QinQ tunnel filter already created.");
7413                         pf->qinq_replace_flag = 1;
7414                 }
7415                 /*      Add in the General fields the values of
7416                  *      the Outer and Inner VLAN
7417                  *      Big Buffer should be set, see changes in
7418                  *      i40e_aq_add_cloud_filters
7419                  */
7420                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7421                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7422                 big_buffer = 1;
7423                 break;
7424         default:
7425                 /* Other tunnel types is not supported. */
7426                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7427                 rte_free(cld_filter);
7428                 return -EINVAL;
7429         }
7430
7431         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7432                 pfilter->element.flags =
7433                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7434         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7435                 pfilter->element.flags =
7436                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7437         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7438                 pfilter->element.flags =
7439                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7440         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7441                 pfilter->element.flags =
7442                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7443         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7444                 pfilter->element.flags |=
7445                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7446         else {
7447                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7448                                                 &pfilter->element.flags);
7449                 if (val < 0) {
7450                         rte_free(cld_filter);
7451                         return -EINVAL;
7452                 }
7453         }
7454
7455         pfilter->element.flags |= rte_cpu_to_le_16(
7456                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7457                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7458         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7459         pfilter->element.queue_number =
7460                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7461
7462         if (!tunnel_filter->is_to_vf)
7463                 vsi = pf->main_vsi;
7464         else {
7465                 if (tunnel_filter->vf_id >= pf->vf_num) {
7466                         PMD_DRV_LOG(ERR, "Invalid argument.");
7467                         return -EINVAL;
7468                 }
7469                 vf = &pf->vfs[tunnel_filter->vf_id];
7470                 vsi = vf->vsi;
7471         }
7472
7473         /* Check if there is the filter in SW list */
7474         memset(&check_filter, 0, sizeof(check_filter));
7475         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7476         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7477         check_filter.vf_id = tunnel_filter->vf_id;
7478         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7479         if (add && node) {
7480                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7481                 return -EINVAL;
7482         }
7483
7484         if (!add && !node) {
7485                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7486                 return -EINVAL;
7487         }
7488
7489         if (add) {
7490                 if (big_buffer)
7491                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7492                                                    vsi->seid, cld_filter, 1);
7493                 else
7494                         ret = i40e_aq_add_cloud_filters(hw,
7495                                         vsi->seid, &cld_filter->element, 1);
7496                 if (ret < 0) {
7497                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7498                         return -ENOTSUP;
7499                 }
7500                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7501                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7502                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7503         } else {
7504                 if (big_buffer)
7505                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7506                                 hw, vsi->seid, cld_filter, 1);
7507                 else
7508                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7509                                                    &cld_filter->element, 1);
7510                 if (ret < 0) {
7511                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7512                         return -ENOTSUP;
7513                 }
7514                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7515         }
7516
7517         rte_free(cld_filter);
7518         return ret;
7519 }
7520
7521 static int
7522 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7523 {
7524         uint8_t i;
7525
7526         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7527                 if (pf->vxlan_ports[i] == port)
7528                         return i;
7529         }
7530
7531         return -1;
7532 }
7533
7534 static int
7535 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7536 {
7537         int  idx, ret;
7538         uint8_t filter_idx;
7539         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7540
7541         idx = i40e_get_vxlan_port_idx(pf, port);
7542
7543         /* Check if port already exists */
7544         if (idx >= 0) {
7545                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7546                 return -EINVAL;
7547         }
7548
7549         /* Now check if there is space to add the new port */
7550         idx = i40e_get_vxlan_port_idx(pf, 0);
7551         if (idx < 0) {
7552                 PMD_DRV_LOG(ERR,
7553                         "Maximum number of UDP ports reached, not adding port %d",
7554                         port);
7555                 return -ENOSPC;
7556         }
7557
7558         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7559                                         &filter_idx, NULL);
7560         if (ret < 0) {
7561                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7562                 return -1;
7563         }
7564
7565         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7566                          port,  filter_idx);
7567
7568         /* New port: add it and mark its index in the bitmap */
7569         pf->vxlan_ports[idx] = port;
7570         pf->vxlan_bitmap |= (1 << idx);
7571
7572         if (!(pf->flags & I40E_FLAG_VXLAN))
7573                 pf->flags |= I40E_FLAG_VXLAN;
7574
7575         return 0;
7576 }
7577
7578 static int
7579 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7580 {
7581         int idx;
7582         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7583
7584         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7585                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7586                 return -EINVAL;
7587         }
7588
7589         idx = i40e_get_vxlan_port_idx(pf, port);
7590
7591         if (idx < 0) {
7592                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7593                 return -EINVAL;
7594         }
7595
7596         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7597                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7598                 return -1;
7599         }
7600
7601         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7602                         port, idx);
7603
7604         pf->vxlan_ports[idx] = 0;
7605         pf->vxlan_bitmap &= ~(1 << idx);
7606
7607         if (!pf->vxlan_bitmap)
7608                 pf->flags &= ~I40E_FLAG_VXLAN;
7609
7610         return 0;
7611 }
7612
7613 /* Add UDP tunneling port */
7614 static int
7615 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7616                              struct rte_eth_udp_tunnel *udp_tunnel)
7617 {
7618         int ret = 0;
7619         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7620
7621         if (udp_tunnel == NULL)
7622                 return -EINVAL;
7623
7624         switch (udp_tunnel->prot_type) {
7625         case RTE_TUNNEL_TYPE_VXLAN:
7626                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7627                 break;
7628
7629         case RTE_TUNNEL_TYPE_GENEVE:
7630         case RTE_TUNNEL_TYPE_TEREDO:
7631                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7632                 ret = -1;
7633                 break;
7634
7635         default:
7636                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7637                 ret = -1;
7638                 break;
7639         }
7640
7641         return ret;
7642 }
7643
7644 /* Remove UDP tunneling port */
7645 static int
7646 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7647                              struct rte_eth_udp_tunnel *udp_tunnel)
7648 {
7649         int ret = 0;
7650         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7651
7652         if (udp_tunnel == NULL)
7653                 return -EINVAL;
7654
7655         switch (udp_tunnel->prot_type) {
7656         case RTE_TUNNEL_TYPE_VXLAN:
7657                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7658                 break;
7659         case RTE_TUNNEL_TYPE_GENEVE:
7660         case RTE_TUNNEL_TYPE_TEREDO:
7661                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7662                 ret = -1;
7663                 break;
7664         default:
7665                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7666                 ret = -1;
7667                 break;
7668         }
7669
7670         return ret;
7671 }
7672
7673 /* Calculate the maximum number of contiguous PF queues that are configured */
7674 static int
7675 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7676 {
7677         struct rte_eth_dev_data *data = pf->dev_data;
7678         int i, num;
7679         struct i40e_rx_queue *rxq;
7680
7681         num = 0;
7682         for (i = 0; i < pf->lan_nb_qps; i++) {
7683                 rxq = data->rx_queues[i];
7684                 if (rxq && rxq->q_set)
7685                         num++;
7686                 else
7687                         break;
7688         }
7689
7690         return num;
7691 }
7692
7693 /* Configure RSS */
7694 static int
7695 i40e_pf_config_rss(struct i40e_pf *pf)
7696 {
7697         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7698         struct rte_eth_rss_conf rss_conf;
7699         uint32_t i, lut = 0;
7700         uint16_t j, num;
7701
7702         /*
7703          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7704          * It's necessary to calculate the actual PF queues that are configured.
7705          */
7706         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7707                 num = i40e_pf_calc_configured_queues_num(pf);
7708         else
7709                 num = pf->dev_data->nb_rx_queues;
7710
7711         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7712         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7713                         num);
7714
7715         if (num == 0) {
7716                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7717                 return -ENOTSUP;
7718         }
7719
7720         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7721                 if (j == num)
7722                         j = 0;
7723                 lut = (lut << 8) | (j & ((0x1 <<
7724                         hw->func_caps.rss_table_entry_width) - 1));
7725                 if ((i & 3) == 3)
7726                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7727         }
7728
7729         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7730         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7731                 i40e_pf_disable_rss(pf);
7732                 return 0;
7733         }
7734         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7735                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7736                 /* Random default keys */
7737                 static uint32_t rss_key_default[] = {0x6b793944,
7738                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7739                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7740                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7741
7742                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7743                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7744                                                         sizeof(uint32_t);
7745         }
7746
7747         return i40e_hw_rss_hash_set(pf, &rss_conf);
7748 }
7749
7750 static int
7751 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7752                                struct rte_eth_tunnel_filter_conf *filter)
7753 {
7754         if (pf == NULL || filter == NULL) {
7755                 PMD_DRV_LOG(ERR, "Invalid parameter");
7756                 return -EINVAL;
7757         }
7758
7759         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7760                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7761                 return -EINVAL;
7762         }
7763
7764         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7765                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7766                 return -EINVAL;
7767         }
7768
7769         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7770                 (is_zero_ether_addr(&filter->outer_mac))) {
7771                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7772                 return -EINVAL;
7773         }
7774
7775         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7776                 (is_zero_ether_addr(&filter->inner_mac))) {
7777                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7778                 return -EINVAL;
7779         }
7780
7781         return 0;
7782 }
7783
7784 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7785 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7786 static int
7787 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7788 {
7789         uint32_t val, reg;
7790         int ret = -EINVAL;
7791
7792         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7793         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7794
7795         if (len == 3) {
7796                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7797         } else if (len == 4) {
7798                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7799         } else {
7800                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7801                 return ret;
7802         }
7803
7804         if (reg != val) {
7805                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7806                                                    reg, NULL);
7807                 if (ret != 0)
7808                         return ret;
7809         } else {
7810                 ret = 0;
7811         }
7812         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7813                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7814
7815         return ret;
7816 }
7817
7818 static int
7819 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7820 {
7821         int ret = -EINVAL;
7822
7823         if (!hw || !cfg)
7824                 return -EINVAL;
7825
7826         switch (cfg->cfg_type) {
7827         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7828                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7829                 break;
7830         default:
7831                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7832                 break;
7833         }
7834
7835         return ret;
7836 }
7837
7838 static int
7839 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7840                                enum rte_filter_op filter_op,
7841                                void *arg)
7842 {
7843         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7844         int ret = I40E_ERR_PARAM;
7845
7846         switch (filter_op) {
7847         case RTE_ETH_FILTER_SET:
7848                 ret = i40e_dev_global_config_set(hw,
7849                         (struct rte_eth_global_cfg *)arg);
7850                 break;
7851         default:
7852                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7853                 break;
7854         }
7855
7856         return ret;
7857 }
7858
7859 static int
7860 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7861                           enum rte_filter_op filter_op,
7862                           void *arg)
7863 {
7864         struct rte_eth_tunnel_filter_conf *filter;
7865         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7866         int ret = I40E_SUCCESS;
7867
7868         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7869
7870         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7871                 return I40E_ERR_PARAM;
7872
7873         switch (filter_op) {
7874         case RTE_ETH_FILTER_NOP:
7875                 if (!(pf->flags & I40E_FLAG_VXLAN))
7876                         ret = I40E_NOT_SUPPORTED;
7877                 break;
7878         case RTE_ETH_FILTER_ADD:
7879                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7880                 break;
7881         case RTE_ETH_FILTER_DELETE:
7882                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7883                 break;
7884         default:
7885                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7886                 ret = I40E_ERR_PARAM;
7887                 break;
7888         }
7889
7890         return ret;
7891 }
7892
7893 static int
7894 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7895 {
7896         int ret = 0;
7897         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7898
7899         /* RSS setup */
7900         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7901                 ret = i40e_pf_config_rss(pf);
7902         else
7903                 i40e_pf_disable_rss(pf);
7904
7905         return ret;
7906 }
7907
7908 /* Get the symmetric hash enable configurations per port */
7909 static void
7910 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7911 {
7912         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7913
7914         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7915 }
7916
7917 /* Set the symmetric hash enable configurations per port */
7918 static void
7919 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7920 {
7921         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7922
7923         if (enable > 0) {
7924                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7925                         PMD_DRV_LOG(INFO,
7926                                 "Symmetric hash has already been enabled");
7927                         return;
7928                 }
7929                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7930         } else {
7931                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7932                         PMD_DRV_LOG(INFO,
7933                                 "Symmetric hash has already been disabled");
7934                         return;
7935                 }
7936                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7937         }
7938         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7939         I40E_WRITE_FLUSH(hw);
7940 }
7941
7942 /*
7943  * Get global configurations of hash function type and symmetric hash enable
7944  * per flow type (pctype). Note that global configuration means it affects all
7945  * the ports on the same NIC.
7946  */
7947 static int
7948 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7949                                    struct rte_eth_hash_global_conf *g_cfg)
7950 {
7951         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
7952         uint32_t reg;
7953         uint16_t i, j;
7954
7955         memset(g_cfg, 0, sizeof(*g_cfg));
7956         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7957         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7958                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7959         else
7960                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7961         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7962                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7963
7964         /*
7965          * We work only with lowest 32 bits which is not correct, but to work
7966          * properly the valid_bit_mask size should be increased up to 64 bits
7967          * and this will brake ABI. This modification will be done in next
7968          * release
7969          */
7970         g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
7971
7972         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
7973                 if (!adapter->pctypes_tbl[i])
7974                         continue;
7975                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
7976                      j < I40E_FILTER_PCTYPE_MAX; j++) {
7977                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
7978                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
7979                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
7980                                         g_cfg->sym_hash_enable_mask[0] |=
7981                                                                 (1UL << i);
7982                                 }
7983                         }
7984                 }
7985         }
7986
7987         return 0;
7988 }
7989
7990 static int
7991 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
7992                               const struct rte_eth_hash_global_conf *g_cfg)
7993 {
7994         uint32_t i;
7995         uint32_t mask0, i40e_mask = adapter->flow_types_mask;
7996
7997         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7998                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7999                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8000                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8001                                                 g_cfg->hash_func);
8002                 return -EINVAL;
8003         }
8004
8005         /*
8006          * As i40e supports less than 32 flow types, only first 32 bits need to
8007          * be checked.
8008          */
8009         mask0 = g_cfg->valid_bit_mask[0];
8010         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8011                 if (i == 0) {
8012                         /* Check if any unsupported flow type configured */
8013                         if ((mask0 | i40e_mask) ^ i40e_mask)
8014                                 goto mask_err;
8015                 } else {
8016                         if (g_cfg->valid_bit_mask[i])
8017                                 goto mask_err;
8018                 }
8019         }
8020
8021         return 0;
8022
8023 mask_err:
8024         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8025
8026         return -EINVAL;
8027 }
8028
8029 /*
8030  * Set global configurations of hash function type and symmetric hash enable
8031  * per flow type (pctype). Note any modifying global configuration will affect
8032  * all the ports on the same NIC.
8033  */
8034 static int
8035 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8036                                    struct rte_eth_hash_global_conf *g_cfg)
8037 {
8038         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8039         int ret;
8040         uint16_t i, j;
8041         uint32_t reg;
8042         /*
8043          * We work only with lowest 32 bits which is not correct, but to work
8044          * properly the valid_bit_mask size should be increased up to 64 bits
8045          * and this will brake ABI. This modification will be done in next
8046          * release
8047          */
8048         uint32_t mask0 = g_cfg->valid_bit_mask[0] &
8049                                         (uint32_t)adapter->flow_types_mask;
8050
8051         /* Check the input parameters */
8052         ret = i40e_hash_global_config_check(adapter, g_cfg);
8053         if (ret < 0)
8054                 return ret;
8055
8056         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
8057                 if (mask0 & (1UL << i)) {
8058                         reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
8059                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8060
8061                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8062                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8063                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8064                                         i40e_write_rx_ctl(hw,
8065                                                           I40E_GLQF_HSYM(j),
8066                                                           reg);
8067                         }
8068                 }
8069         }
8070
8071         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8072         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8073                 /* Toeplitz */
8074                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8075                         PMD_DRV_LOG(DEBUG,
8076                                 "Hash function already set to Toeplitz");
8077                         goto out;
8078                 }
8079                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8080         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8081                 /* Simple XOR */
8082                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8083                         PMD_DRV_LOG(DEBUG,
8084                                 "Hash function already set to Simple XOR");
8085                         goto out;
8086                 }
8087                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8088         } else
8089                 /* Use the default, and keep it as it is */
8090                 goto out;
8091
8092         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8093
8094 out:
8095         I40E_WRITE_FLUSH(hw);
8096
8097         return 0;
8098 }
8099
8100 /**
8101  * Valid input sets for hash and flow director filters per PCTYPE
8102  */
8103 static uint64_t
8104 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8105                 enum rte_filter_type filter)
8106 {
8107         uint64_t valid;
8108
8109         static const uint64_t valid_hash_inset_table[] = {
8110                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8111                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8112                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8113                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8114                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8115                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8116                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8117                         I40E_INSET_FLEX_PAYLOAD,
8118                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8119                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8120                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8121                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8122                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8123                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8124                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8125                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8126                         I40E_INSET_FLEX_PAYLOAD,
8127                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8128                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8129                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8130                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8131                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8132                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8133                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8134                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8135                         I40E_INSET_FLEX_PAYLOAD,
8136                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8137                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8138                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8139                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8140                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8141                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8142                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8143                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8144                         I40E_INSET_FLEX_PAYLOAD,
8145                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8146                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8147                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8148                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8149                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8150                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8151                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8152                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8153                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8154                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8155                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8156                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8157                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8158                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8159                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8160                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8161                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8162                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8163                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8164                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8165                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8166                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8167                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8168                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8169                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8170                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8171                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8172                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8173                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8174                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8175                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8176                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8177                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8178                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8179                         I40E_INSET_FLEX_PAYLOAD,
8180                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8181                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8182                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8183                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8184                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8185                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8186                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8187                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8188                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8189                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8190                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8191                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8192                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8193                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8194                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8195                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8196                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8197                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8198                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8199                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8200                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8201                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8202                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8203                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8204                         I40E_INSET_FLEX_PAYLOAD,
8205                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8206                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8207                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8208                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8209                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8210                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8211                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8212                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8213                         I40E_INSET_FLEX_PAYLOAD,
8214                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8215                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8216                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8217                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8218                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8219                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8220                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8221                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8222                         I40E_INSET_FLEX_PAYLOAD,
8223                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8224                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8225                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8226                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8227                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8228                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8229                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8230                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8231                         I40E_INSET_FLEX_PAYLOAD,
8232                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8233                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8234                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8235                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8236                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8237                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8238                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8239                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8240                         I40E_INSET_FLEX_PAYLOAD,
8241                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8242                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8243                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8244                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8245                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8246                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8247                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8248                         I40E_INSET_FLEX_PAYLOAD,
8249                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8250                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8251                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8252                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8253                         I40E_INSET_FLEX_PAYLOAD,
8254         };
8255
8256         /**
8257          * Flow director supports only fields defined in
8258          * union rte_eth_fdir_flow.
8259          */
8260         static const uint64_t valid_fdir_inset_table[] = {
8261                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8262                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8263                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8264                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8265                 I40E_INSET_IPV4_TTL,
8266                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8267                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8268                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8269                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8270                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8271                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8272                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8273                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8274                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8275                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8276                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8277                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8278                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8279                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8280                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8281                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8282                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8283                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8284                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8285                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8286                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8287                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8288                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8289                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8290                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8291                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8292                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8293                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8294                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8295                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8296                 I40E_INSET_SCTP_VT,
8297                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8298                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8299                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8300                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8301                 I40E_INSET_IPV4_TTL,
8302                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8303                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8304                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8305                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8306                 I40E_INSET_IPV6_HOP_LIMIT,
8307                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8308                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8309                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8310                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8311                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8312                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8313                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8314                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8315                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8316                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8317                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8318                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8319                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8320                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8321                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8322                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8323                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8324                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8325                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8326                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8327                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8328                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8329                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8330                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8331                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8332                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8333                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8334                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8335                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8336                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8337                 I40E_INSET_SCTP_VT,
8338                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8339                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8340                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8341                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8342                 I40E_INSET_IPV6_HOP_LIMIT,
8343                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8344                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8345                 I40E_INSET_LAST_ETHER_TYPE,
8346         };
8347
8348         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8349                 return 0;
8350         if (filter == RTE_ETH_FILTER_HASH)
8351                 valid = valid_hash_inset_table[pctype];
8352         else
8353                 valid = valid_fdir_inset_table[pctype];
8354
8355         return valid;
8356 }
8357
8358 /**
8359  * Validate if the input set is allowed for a specific PCTYPE
8360  */
8361 int
8362 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8363                 enum rte_filter_type filter, uint64_t inset)
8364 {
8365         uint64_t valid;
8366
8367         valid = i40e_get_valid_input_set(pctype, filter);
8368         if (inset & (~valid))
8369                 return -EINVAL;
8370
8371         return 0;
8372 }
8373
8374 /* default input set fields combination per pctype */
8375 uint64_t
8376 i40e_get_default_input_set(uint16_t pctype)
8377 {
8378         static const uint64_t default_inset_table[] = {
8379                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8380                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8381                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8382                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8383                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8384                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8385                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8386                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8387                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8388                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8389                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8390                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8391                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8392                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8393                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8394                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8395                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8396                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8397                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8398                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8399                         I40E_INSET_SCTP_VT,
8400                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8401                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8402                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8403                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8404                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8405                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8406                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8407                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8408                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8409                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8410                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8411                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8412                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8413                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8414                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8415                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8416                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8417                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8418                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8419                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8420                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8421                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8422                         I40E_INSET_SCTP_VT,
8423                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8424                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8425                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8426                         I40E_INSET_LAST_ETHER_TYPE,
8427         };
8428
8429         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8430                 return 0;
8431
8432         return default_inset_table[pctype];
8433 }
8434
8435 /**
8436  * Parse the input set from index to logical bit masks
8437  */
8438 static int
8439 i40e_parse_input_set(uint64_t *inset,
8440                      enum i40e_filter_pctype pctype,
8441                      enum rte_eth_input_set_field *field,
8442                      uint16_t size)
8443 {
8444         uint16_t i, j;
8445         int ret = -EINVAL;
8446
8447         static const struct {
8448                 enum rte_eth_input_set_field field;
8449                 uint64_t inset;
8450         } inset_convert_table[] = {
8451                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8452                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8453                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8454                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8455                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8456                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8457                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8458                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8459                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8460                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8461                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8462                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8463                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8464                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8465                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8466                         I40E_INSET_IPV6_NEXT_HDR},
8467                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8468                         I40E_INSET_IPV6_HOP_LIMIT},
8469                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8470                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8471                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8472                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8473                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8474                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8475                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8476                         I40E_INSET_SCTP_VT},
8477                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8478                         I40E_INSET_TUNNEL_DMAC},
8479                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8480                         I40E_INSET_VLAN_TUNNEL},
8481                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8482                         I40E_INSET_TUNNEL_ID},
8483                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8484                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8485                         I40E_INSET_FLEX_PAYLOAD_W1},
8486                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8487                         I40E_INSET_FLEX_PAYLOAD_W2},
8488                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8489                         I40E_INSET_FLEX_PAYLOAD_W3},
8490                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8491                         I40E_INSET_FLEX_PAYLOAD_W4},
8492                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8493                         I40E_INSET_FLEX_PAYLOAD_W5},
8494                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8495                         I40E_INSET_FLEX_PAYLOAD_W6},
8496                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8497                         I40E_INSET_FLEX_PAYLOAD_W7},
8498                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8499                         I40E_INSET_FLEX_PAYLOAD_W8},
8500         };
8501
8502         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8503                 return ret;
8504
8505         /* Only one item allowed for default or all */
8506         if (size == 1) {
8507                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8508                         *inset = i40e_get_default_input_set(pctype);
8509                         return 0;
8510                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8511                         *inset = I40E_INSET_NONE;
8512                         return 0;
8513                 }
8514         }
8515
8516         for (i = 0, *inset = 0; i < size; i++) {
8517                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8518                         if (field[i] == inset_convert_table[j].field) {
8519                                 *inset |= inset_convert_table[j].inset;
8520                                 break;
8521                         }
8522                 }
8523
8524                 /* It contains unsupported input set, return immediately */
8525                 if (j == RTE_DIM(inset_convert_table))
8526                         return ret;
8527         }
8528
8529         return 0;
8530 }
8531
8532 /**
8533  * Translate the input set from bit masks to register aware bit masks
8534  * and vice versa
8535  */
8536 uint64_t
8537 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8538 {
8539         uint64_t val = 0;
8540         uint16_t i;
8541
8542         struct inset_map {
8543                 uint64_t inset;
8544                 uint64_t inset_reg;
8545         };
8546
8547         static const struct inset_map inset_map_common[] = {
8548                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8549                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8550                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8551                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8552                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8553                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8554                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8555                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8556                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8557                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8558                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8559                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8560                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8561                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8562                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8563                 {I40E_INSET_TUNNEL_DMAC,
8564                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8565                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8566                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8567                 {I40E_INSET_TUNNEL_SRC_PORT,
8568                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8569                 {I40E_INSET_TUNNEL_DST_PORT,
8570                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8571                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8572                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8573                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8574                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8575                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8576                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8577                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8578                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8579                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8580         };
8581
8582     /* some different registers map in x722*/
8583         static const struct inset_map inset_map_diff_x722[] = {
8584                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8585                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8586                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8587                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8588         };
8589
8590         static const struct inset_map inset_map_diff_not_x722[] = {
8591                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8592                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8593                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8594                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8595         };
8596
8597         if (input == 0)
8598                 return val;
8599
8600         /* Translate input set to register aware inset */
8601         if (type == I40E_MAC_X722) {
8602                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8603                         if (input & inset_map_diff_x722[i].inset)
8604                                 val |= inset_map_diff_x722[i].inset_reg;
8605                 }
8606         } else {
8607                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8608                         if (input & inset_map_diff_not_x722[i].inset)
8609                                 val |= inset_map_diff_not_x722[i].inset_reg;
8610                 }
8611         }
8612
8613         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8614                 if (input & inset_map_common[i].inset)
8615                         val |= inset_map_common[i].inset_reg;
8616         }
8617
8618         return val;
8619 }
8620
8621 int
8622 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8623 {
8624         uint8_t i, idx = 0;
8625         uint64_t inset_need_mask = inset;
8626
8627         static const struct {
8628                 uint64_t inset;
8629                 uint32_t mask;
8630         } inset_mask_map[] = {
8631                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8632                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8633                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8634                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8635                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8636                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8637                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8638                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8639         };
8640
8641         if (!inset || !mask || !nb_elem)
8642                 return 0;
8643
8644         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8645                 /* Clear the inset bit, if no MASK is required,
8646                  * for example proto + ttl
8647                  */
8648                 if ((inset & inset_mask_map[i].inset) ==
8649                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8650                         inset_need_mask &= ~inset_mask_map[i].inset;
8651                 if (!inset_need_mask)
8652                         return 0;
8653         }
8654         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8655                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8656                     inset_mask_map[i].inset) {
8657                         if (idx >= nb_elem) {
8658                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8659                                 return -EINVAL;
8660                         }
8661                         mask[idx] = inset_mask_map[i].mask;
8662                         idx++;
8663                 }
8664         }
8665
8666         return idx;
8667 }
8668
8669 void
8670 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8671 {
8672         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8673
8674         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8675         if (reg != val)
8676                 i40e_write_rx_ctl(hw, addr, val);
8677         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8678                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8679 }
8680
8681 static void
8682 i40e_filter_input_set_init(struct i40e_pf *pf)
8683 {
8684         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8685         enum i40e_filter_pctype pctype;
8686         uint64_t input_set, inset_reg;
8687         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8688         int num, i;
8689         uint16_t flow_type;
8690
8691         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8692              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8693                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8694
8695                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8696                         continue;
8697
8698                 input_set = i40e_get_default_input_set(pctype);
8699
8700                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8701                                                    I40E_INSET_MASK_NUM_REG);
8702                 if (num < 0)
8703                         return;
8704                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8705                                         input_set);
8706
8707                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8708                                       (uint32_t)(inset_reg & UINT32_MAX));
8709                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8710                                      (uint32_t)((inset_reg >>
8711                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8712                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8713                                       (uint32_t)(inset_reg & UINT32_MAX));
8714                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8715                                      (uint32_t)((inset_reg >>
8716                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8717
8718                 for (i = 0; i < num; i++) {
8719                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8720                                              mask_reg[i]);
8721                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8722                                              mask_reg[i]);
8723                 }
8724                 /*clear unused mask registers of the pctype */
8725                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8726                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8727                                              0);
8728                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8729                                              0);
8730                 }
8731                 I40E_WRITE_FLUSH(hw);
8732
8733                 /* store the default input set */
8734                 pf->hash_input_set[pctype] = input_set;
8735                 pf->fdir.input_set[pctype] = input_set;
8736         }
8737 }
8738
8739 int
8740 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8741                          struct rte_eth_input_set_conf *conf)
8742 {
8743         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8744         enum i40e_filter_pctype pctype;
8745         uint64_t input_set, inset_reg = 0;
8746         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8747         int ret, i, num;
8748
8749         if (!conf) {
8750                 PMD_DRV_LOG(ERR, "Invalid pointer");
8751                 return -EFAULT;
8752         }
8753         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8754             conf->op != RTE_ETH_INPUT_SET_ADD) {
8755                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8756                 return -EINVAL;
8757         }
8758
8759         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8760         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8761                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8762                 return -EINVAL;
8763         }
8764
8765         if (hw->mac.type == I40E_MAC_X722) {
8766                 /* get translated pctype value in fd pctype register */
8767                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8768                         I40E_GLQF_FD_PCTYPES((int)pctype));
8769         }
8770
8771         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8772                                    conf->inset_size);
8773         if (ret) {
8774                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8775                 return -EINVAL;
8776         }
8777
8778         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8779                 /* get inset value in register */
8780                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8781                 inset_reg <<= I40E_32_BIT_WIDTH;
8782                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8783                 input_set |= pf->hash_input_set[pctype];
8784         }
8785         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8786                                            I40E_INSET_MASK_NUM_REG);
8787         if (num < 0)
8788                 return -EINVAL;
8789
8790         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8791
8792         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8793                               (uint32_t)(inset_reg & UINT32_MAX));
8794         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8795                              (uint32_t)((inset_reg >>
8796                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8797
8798         for (i = 0; i < num; i++)
8799                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8800                                      mask_reg[i]);
8801         /*clear unused mask registers of the pctype */
8802         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8803                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8804                                      0);
8805         I40E_WRITE_FLUSH(hw);
8806
8807         pf->hash_input_set[pctype] = input_set;
8808         return 0;
8809 }
8810
8811 int
8812 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8813                          struct rte_eth_input_set_conf *conf)
8814 {
8815         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8816         enum i40e_filter_pctype pctype;
8817         uint64_t input_set, inset_reg = 0;
8818         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8819         int ret, i, num;
8820
8821         if (!hw || !conf) {
8822                 PMD_DRV_LOG(ERR, "Invalid pointer");
8823                 return -EFAULT;
8824         }
8825         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8826             conf->op != RTE_ETH_INPUT_SET_ADD) {
8827                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8828                 return -EINVAL;
8829         }
8830
8831         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8832
8833         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8834                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8835                 return -EINVAL;
8836         }
8837
8838         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8839                                    conf->inset_size);
8840         if (ret) {
8841                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8842                 return -EINVAL;
8843         }
8844
8845         /* get inset value in register */
8846         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8847         inset_reg <<= I40E_32_BIT_WIDTH;
8848         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8849
8850         /* Can not change the inset reg for flex payload for fdir,
8851          * it is done by writing I40E_PRTQF_FD_FLXINSET
8852          * in i40e_set_flex_mask_on_pctype.
8853          */
8854         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8855                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8856         else
8857                 input_set |= pf->fdir.input_set[pctype];
8858         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8859                                            I40E_INSET_MASK_NUM_REG);
8860         if (num < 0)
8861                 return -EINVAL;
8862
8863         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8864
8865         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8866                               (uint32_t)(inset_reg & UINT32_MAX));
8867         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8868                              (uint32_t)((inset_reg >>
8869                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8870
8871         for (i = 0; i < num; i++)
8872                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8873                                      mask_reg[i]);
8874         /*clear unused mask registers of the pctype */
8875         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8876                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8877                                      0);
8878         I40E_WRITE_FLUSH(hw);
8879
8880         pf->fdir.input_set[pctype] = input_set;
8881         return 0;
8882 }
8883
8884 static int
8885 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8886 {
8887         int ret = 0;
8888
8889         if (!hw || !info) {
8890                 PMD_DRV_LOG(ERR, "Invalid pointer");
8891                 return -EFAULT;
8892         }
8893
8894         switch (info->info_type) {
8895         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8896                 i40e_get_symmetric_hash_enable_per_port(hw,
8897                                         &(info->info.enable));
8898                 break;
8899         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8900                 ret = i40e_get_hash_filter_global_config(hw,
8901                                 &(info->info.global_conf));
8902                 break;
8903         default:
8904                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8905                                                         info->info_type);
8906                 ret = -EINVAL;
8907                 break;
8908         }
8909
8910         return ret;
8911 }
8912
8913 static int
8914 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8915 {
8916         int ret = 0;
8917
8918         if (!hw || !info) {
8919                 PMD_DRV_LOG(ERR, "Invalid pointer");
8920                 return -EFAULT;
8921         }
8922
8923         switch (info->info_type) {
8924         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8925                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8926                 break;
8927         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8928                 ret = i40e_set_hash_filter_global_config(hw,
8929                                 &(info->info.global_conf));
8930                 break;
8931         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8932                 ret = i40e_hash_filter_inset_select(hw,
8933                                                &(info->info.input_set_conf));
8934                 break;
8935
8936         default:
8937                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8938                                                         info->info_type);
8939                 ret = -EINVAL;
8940                 break;
8941         }
8942
8943         return ret;
8944 }
8945
8946 /* Operations for hash function */
8947 static int
8948 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8949                       enum rte_filter_op filter_op,
8950                       void *arg)
8951 {
8952         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8953         int ret = 0;
8954
8955         switch (filter_op) {
8956         case RTE_ETH_FILTER_NOP:
8957                 break;
8958         case RTE_ETH_FILTER_GET:
8959                 ret = i40e_hash_filter_get(hw,
8960                         (struct rte_eth_hash_filter_info *)arg);
8961                 break;
8962         case RTE_ETH_FILTER_SET:
8963                 ret = i40e_hash_filter_set(hw,
8964                         (struct rte_eth_hash_filter_info *)arg);
8965                 break;
8966         default:
8967                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8968                                                                 filter_op);
8969                 ret = -ENOTSUP;
8970                 break;
8971         }
8972
8973         return ret;
8974 }
8975
8976 /* Convert ethertype filter structure */
8977 static int
8978 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8979                               struct i40e_ethertype_filter *filter)
8980 {
8981         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8982         filter->input.ether_type = input->ether_type;
8983         filter->flags = input->flags;
8984         filter->queue = input->queue;
8985
8986         return 0;
8987 }
8988
8989 /* Check if there exists the ehtertype filter */
8990 struct i40e_ethertype_filter *
8991 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8992                                 const struct i40e_ethertype_filter_input *input)
8993 {
8994         int ret;
8995
8996         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8997         if (ret < 0)
8998                 return NULL;
8999
9000         return ethertype_rule->hash_map[ret];
9001 }
9002
9003 /* Add ethertype filter in SW list */
9004 static int
9005 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9006                                 struct i40e_ethertype_filter *filter)
9007 {
9008         struct i40e_ethertype_rule *rule = &pf->ethertype;
9009         int ret;
9010
9011         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9012         if (ret < 0) {
9013                 PMD_DRV_LOG(ERR,
9014                             "Failed to insert ethertype filter"
9015                             " to hash table %d!",
9016                             ret);
9017                 return ret;
9018         }
9019         rule->hash_map[ret] = filter;
9020
9021         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9022
9023         return 0;
9024 }
9025
9026 /* Delete ethertype filter in SW list */
9027 int
9028 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9029                              struct i40e_ethertype_filter_input *input)
9030 {
9031         struct i40e_ethertype_rule *rule = &pf->ethertype;
9032         struct i40e_ethertype_filter *filter;
9033         int ret;
9034
9035         ret = rte_hash_del_key(rule->hash_table, input);
9036         if (ret < 0) {
9037                 PMD_DRV_LOG(ERR,
9038                             "Failed to delete ethertype filter"
9039                             " to hash table %d!",
9040                             ret);
9041                 return ret;
9042         }
9043         filter = rule->hash_map[ret];
9044         rule->hash_map[ret] = NULL;
9045
9046         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9047         rte_free(filter);
9048
9049         return 0;
9050 }
9051
9052 /*
9053  * Configure ethertype filter, which can director packet by filtering
9054  * with mac address and ether_type or only ether_type
9055  */
9056 int
9057 i40e_ethertype_filter_set(struct i40e_pf *pf,
9058                         struct rte_eth_ethertype_filter *filter,
9059                         bool add)
9060 {
9061         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9062         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9063         struct i40e_ethertype_filter *ethertype_filter, *node;
9064         struct i40e_ethertype_filter check_filter;
9065         struct i40e_control_filter_stats stats;
9066         uint16_t flags = 0;
9067         int ret;
9068
9069         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9070                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9071                 return -EINVAL;
9072         }
9073         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9074                 filter->ether_type == ETHER_TYPE_IPv6) {
9075                 PMD_DRV_LOG(ERR,
9076                         "unsupported ether_type(0x%04x) in control packet filter.",
9077                         filter->ether_type);
9078                 return -EINVAL;
9079         }
9080         if (filter->ether_type == ETHER_TYPE_VLAN)
9081                 PMD_DRV_LOG(WARNING,
9082                         "filter vlan ether_type in first tag is not supported.");
9083
9084         /* Check if there is the filter in SW list */
9085         memset(&check_filter, 0, sizeof(check_filter));
9086         i40e_ethertype_filter_convert(filter, &check_filter);
9087         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9088                                                &check_filter.input);
9089         if (add && node) {
9090                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9091                 return -EINVAL;
9092         }
9093
9094         if (!add && !node) {
9095                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9096                 return -EINVAL;
9097         }
9098
9099         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9100                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9101         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9102                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9103         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9104
9105         memset(&stats, 0, sizeof(stats));
9106         ret = i40e_aq_add_rem_control_packet_filter(hw,
9107                         filter->mac_addr.addr_bytes,
9108                         filter->ether_type, flags,
9109                         pf->main_vsi->seid,
9110                         filter->queue, add, &stats, NULL);
9111
9112         PMD_DRV_LOG(INFO,
9113                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9114                 ret, stats.mac_etype_used, stats.etype_used,
9115                 stats.mac_etype_free, stats.etype_free);
9116         if (ret < 0)
9117                 return -ENOSYS;
9118
9119         /* Add or delete a filter in SW list */
9120         if (add) {
9121                 ethertype_filter = rte_zmalloc("ethertype_filter",
9122                                        sizeof(*ethertype_filter), 0);
9123                 rte_memcpy(ethertype_filter, &check_filter,
9124                            sizeof(check_filter));
9125                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9126         } else {
9127                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9128         }
9129
9130         return ret;
9131 }
9132
9133 /*
9134  * Handle operations for ethertype filter.
9135  */
9136 static int
9137 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9138                                 enum rte_filter_op filter_op,
9139                                 void *arg)
9140 {
9141         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9142         int ret = 0;
9143
9144         if (filter_op == RTE_ETH_FILTER_NOP)
9145                 return ret;
9146
9147         if (arg == NULL) {
9148                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9149                             filter_op);
9150                 return -EINVAL;
9151         }
9152
9153         switch (filter_op) {
9154         case RTE_ETH_FILTER_ADD:
9155                 ret = i40e_ethertype_filter_set(pf,
9156                         (struct rte_eth_ethertype_filter *)arg,
9157                         TRUE);
9158                 break;
9159         case RTE_ETH_FILTER_DELETE:
9160                 ret = i40e_ethertype_filter_set(pf,
9161                         (struct rte_eth_ethertype_filter *)arg,
9162                         FALSE);
9163                 break;
9164         default:
9165                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9166                 ret = -ENOSYS;
9167                 break;
9168         }
9169         return ret;
9170 }
9171
9172 static int
9173 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9174                      enum rte_filter_type filter_type,
9175                      enum rte_filter_op filter_op,
9176                      void *arg)
9177 {
9178         int ret = 0;
9179
9180         if (dev == NULL)
9181                 return -EINVAL;
9182
9183         switch (filter_type) {
9184         case RTE_ETH_FILTER_NONE:
9185                 /* For global configuration */
9186                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9187                 break;
9188         case RTE_ETH_FILTER_HASH:
9189                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9190                 break;
9191         case RTE_ETH_FILTER_MACVLAN:
9192                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9193                 break;
9194         case RTE_ETH_FILTER_ETHERTYPE:
9195                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9196                 break;
9197         case RTE_ETH_FILTER_TUNNEL:
9198                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9199                 break;
9200         case RTE_ETH_FILTER_FDIR:
9201                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9202                 break;
9203         case RTE_ETH_FILTER_GENERIC:
9204                 if (filter_op != RTE_ETH_FILTER_GET)
9205                         return -EINVAL;
9206                 *(const void **)arg = &i40e_flow_ops;
9207                 break;
9208         default:
9209                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9210                                                         filter_type);
9211                 ret = -EINVAL;
9212                 break;
9213         }
9214
9215         return ret;
9216 }
9217
9218 /*
9219  * Check and enable Extended Tag.
9220  * Enabling Extended Tag is important for 40G performance.
9221  */
9222 static void
9223 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9224 {
9225         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9226         uint32_t buf = 0;
9227         int ret;
9228
9229         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9230                                       PCI_DEV_CAP_REG);
9231         if (ret < 0) {
9232                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9233                             PCI_DEV_CAP_REG);
9234                 return;
9235         }
9236         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9237                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9238                 return;
9239         }
9240
9241         buf = 0;
9242         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9243                                       PCI_DEV_CTRL_REG);
9244         if (ret < 0) {
9245                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9246                             PCI_DEV_CTRL_REG);
9247                 return;
9248         }
9249         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9250                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9251                 return;
9252         }
9253         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9254         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9255                                        PCI_DEV_CTRL_REG);
9256         if (ret < 0) {
9257                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9258                             PCI_DEV_CTRL_REG);
9259                 return;
9260         }
9261 }
9262
9263 /*
9264  * As some registers wouldn't be reset unless a global hardware reset,
9265  * hardware initialization is needed to put those registers into an
9266  * expected initial state.
9267  */
9268 static void
9269 i40e_hw_init(struct rte_eth_dev *dev)
9270 {
9271         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9272
9273         i40e_enable_extended_tag(dev);
9274
9275         /* clear the PF Queue Filter control register */
9276         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9277
9278         /* Disable symmetric hash per port */
9279         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9280 }
9281
9282 /*
9283  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9284  * however this function will return only one highest pctype index,
9285  * which is not quite correct. This is known problem of i40e driver
9286  * and needs to be fixed later.
9287  */
9288 enum i40e_filter_pctype
9289 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9290 {
9291         int i;
9292         uint64_t pctype_mask;
9293
9294         if (flow_type < I40E_FLOW_TYPE_MAX) {
9295                 pctype_mask = adapter->pctypes_tbl[flow_type];
9296                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9297                         if (pctype_mask & (1ULL << i))
9298                                 return (enum i40e_filter_pctype)i;
9299                 }
9300         }
9301         return I40E_FILTER_PCTYPE_INVALID;
9302 }
9303
9304 uint16_t
9305 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9306                         enum i40e_filter_pctype pctype)
9307 {
9308         uint16_t flowtype;
9309         uint64_t pctype_mask = 1ULL << pctype;
9310
9311         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9312              flowtype++) {
9313                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9314                         return flowtype;
9315         }
9316
9317         return RTE_ETH_FLOW_UNKNOWN;
9318 }
9319
9320 /*
9321  * On X710, performance number is far from the expectation on recent firmware
9322  * versions; on XL710, performance number is also far from the expectation on
9323  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9324  * mode is enabled and port MAC address is equal to the packet destination MAC
9325  * address. The fix for this issue may not be integrated in the following
9326  * firmware version. So the workaround in software driver is needed. It needs
9327  * to modify the initial values of 3 internal only registers for both X710 and
9328  * XL710. Note that the values for X710 or XL710 could be different, and the
9329  * workaround can be removed when it is fixed in firmware in the future.
9330  */
9331
9332 /* For both X710 and XL710 */
9333 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9334 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x20000200
9335 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9336
9337 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9338 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9339
9340 /* For X722 */
9341 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9342 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9343
9344 /* For X710 */
9345 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9346 /* For XL710 */
9347 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9348 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9349
9350 static int
9351 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9352 {
9353         enum i40e_status_code status;
9354         struct i40e_aq_get_phy_abilities_resp phy_ab;
9355         int ret = -ENOTSUP;
9356         int retries = 0;
9357
9358         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9359                                               NULL);
9360
9361         while (status) {
9362                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9363                         status);
9364                 retries++;
9365                 rte_delay_us(100000);
9366                 if  (retries < 5)
9367                         status = i40e_aq_get_phy_capabilities(hw, false,
9368                                         true, &phy_ab, NULL);
9369                 else
9370                         return ret;
9371         }
9372         return 0;
9373 }
9374
9375 static void
9376 i40e_configure_registers(struct i40e_hw *hw)
9377 {
9378         static struct {
9379                 uint32_t addr;
9380                 uint64_t val;
9381         } reg_table[] = {
9382                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9383                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9384                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9385         };
9386         uint64_t reg;
9387         uint32_t i;
9388         int ret;
9389
9390         for (i = 0; i < RTE_DIM(reg_table); i++) {
9391                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9392                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9393                                 reg_table[i].val =
9394                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9395                         else /* For X710/XL710/XXV710 */
9396                                 if (hw->aq.fw_maj_ver < 6)
9397                                         reg_table[i].val =
9398                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9399                                 else
9400                                         reg_table[i].val =
9401                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9402                 }
9403
9404                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9405                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9406                                 reg_table[i].val =
9407                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9408                         else /* For X710/XL710/XXV710 */
9409                                 reg_table[i].val =
9410                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9411                 }
9412
9413                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9414                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9415                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9416                                 reg_table[i].val =
9417                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9418                         else /* For X710 */
9419                                 reg_table[i].val =
9420                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9421                 }
9422
9423                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9424                                                         &reg, NULL);
9425                 if (ret < 0) {
9426                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9427                                                         reg_table[i].addr);
9428                         break;
9429                 }
9430                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9431                                                 reg_table[i].addr, reg);
9432                 if (reg == reg_table[i].val)
9433                         continue;
9434
9435                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9436                                                 reg_table[i].val, NULL);
9437                 if (ret < 0) {
9438                         PMD_DRV_LOG(ERR,
9439                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9440                                 reg_table[i].val, reg_table[i].addr);
9441                         break;
9442                 }
9443                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9444                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9445         }
9446 }
9447
9448 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9449 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9450 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9451 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9452 static int
9453 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9454 {
9455         uint32_t reg;
9456         int ret;
9457
9458         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9459                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9460                 return -EINVAL;
9461         }
9462
9463         /* Configure for double VLAN RX stripping */
9464         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9465         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9466                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9467                 ret = i40e_aq_debug_write_register(hw,
9468                                                    I40E_VSI_TSR(vsi->vsi_id),
9469                                                    reg, NULL);
9470                 if (ret < 0) {
9471                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9472                                     vsi->vsi_id);
9473                         return I40E_ERR_CONFIG;
9474                 }
9475         }
9476
9477         /* Configure for double VLAN TX insertion */
9478         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9479         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9480                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9481                 ret = i40e_aq_debug_write_register(hw,
9482                                                    I40E_VSI_L2TAGSTXVALID(
9483                                                    vsi->vsi_id), reg, NULL);
9484                 if (ret < 0) {
9485                         PMD_DRV_LOG(ERR,
9486                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9487                                 vsi->vsi_id);
9488                         return I40E_ERR_CONFIG;
9489                 }
9490         }
9491
9492         return 0;
9493 }
9494
9495 /**
9496  * i40e_aq_add_mirror_rule
9497  * @hw: pointer to the hardware structure
9498  * @seid: VEB seid to add mirror rule to
9499  * @dst_id: destination vsi seid
9500  * @entries: Buffer which contains the entities to be mirrored
9501  * @count: number of entities contained in the buffer
9502  * @rule_id:the rule_id of the rule to be added
9503  *
9504  * Add a mirror rule for a given veb.
9505  *
9506  **/
9507 static enum i40e_status_code
9508 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9509                         uint16_t seid, uint16_t dst_id,
9510                         uint16_t rule_type, uint16_t *entries,
9511                         uint16_t count, uint16_t *rule_id)
9512 {
9513         struct i40e_aq_desc desc;
9514         struct i40e_aqc_add_delete_mirror_rule cmd;
9515         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9516                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9517                 &desc.params.raw;
9518         uint16_t buff_len;
9519         enum i40e_status_code status;
9520
9521         i40e_fill_default_direct_cmd_desc(&desc,
9522                                           i40e_aqc_opc_add_mirror_rule);
9523         memset(&cmd, 0, sizeof(cmd));
9524
9525         buff_len = sizeof(uint16_t) * count;
9526         desc.datalen = rte_cpu_to_le_16(buff_len);
9527         if (buff_len > 0)
9528                 desc.flags |= rte_cpu_to_le_16(
9529                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9530         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9531                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9532         cmd.num_entries = rte_cpu_to_le_16(count);
9533         cmd.seid = rte_cpu_to_le_16(seid);
9534         cmd.destination = rte_cpu_to_le_16(dst_id);
9535
9536         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9537         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9538         PMD_DRV_LOG(INFO,
9539                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9540                 hw->aq.asq_last_status, resp->rule_id,
9541                 resp->mirror_rules_used, resp->mirror_rules_free);
9542         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9543
9544         return status;
9545 }
9546
9547 /**
9548  * i40e_aq_del_mirror_rule
9549  * @hw: pointer to the hardware structure
9550  * @seid: VEB seid to add mirror rule to
9551  * @entries: Buffer which contains the entities to be mirrored
9552  * @count: number of entities contained in the buffer
9553  * @rule_id:the rule_id of the rule to be delete
9554  *
9555  * Delete a mirror rule for a given veb.
9556  *
9557  **/
9558 static enum i40e_status_code
9559 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9560                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9561                 uint16_t count, uint16_t rule_id)
9562 {
9563         struct i40e_aq_desc desc;
9564         struct i40e_aqc_add_delete_mirror_rule cmd;
9565         uint16_t buff_len = 0;
9566         enum i40e_status_code status;
9567         void *buff = NULL;
9568
9569         i40e_fill_default_direct_cmd_desc(&desc,
9570                                           i40e_aqc_opc_delete_mirror_rule);
9571         memset(&cmd, 0, sizeof(cmd));
9572         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9573                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9574                                                           I40E_AQ_FLAG_RD));
9575                 cmd.num_entries = count;
9576                 buff_len = sizeof(uint16_t) * count;
9577                 desc.datalen = rte_cpu_to_le_16(buff_len);
9578                 buff = (void *)entries;
9579         } else
9580                 /* rule id is filled in destination field for deleting mirror rule */
9581                 cmd.destination = rte_cpu_to_le_16(rule_id);
9582
9583         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9584                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9585         cmd.seid = rte_cpu_to_le_16(seid);
9586
9587         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9588         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9589
9590         return status;
9591 }
9592
9593 /**
9594  * i40e_mirror_rule_set
9595  * @dev: pointer to the hardware structure
9596  * @mirror_conf: mirror rule info
9597  * @sw_id: mirror rule's sw_id
9598  * @on: enable/disable
9599  *
9600  * set a mirror rule.
9601  *
9602  **/
9603 static int
9604 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9605                         struct rte_eth_mirror_conf *mirror_conf,
9606                         uint8_t sw_id, uint8_t on)
9607 {
9608         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9609         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9610         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9611         struct i40e_mirror_rule *parent = NULL;
9612         uint16_t seid, dst_seid, rule_id;
9613         uint16_t i, j = 0;
9614         int ret;
9615
9616         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9617
9618         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9619                 PMD_DRV_LOG(ERR,
9620                         "mirror rule can not be configured without veb or vfs.");
9621                 return -ENOSYS;
9622         }
9623         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9624                 PMD_DRV_LOG(ERR, "mirror table is full.");
9625                 return -ENOSPC;
9626         }
9627         if (mirror_conf->dst_pool > pf->vf_num) {
9628                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9629                                  mirror_conf->dst_pool);
9630                 return -EINVAL;
9631         }
9632
9633         seid = pf->main_vsi->veb->seid;
9634
9635         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9636                 if (sw_id <= it->index) {
9637                         mirr_rule = it;
9638                         break;
9639                 }
9640                 parent = it;
9641         }
9642         if (mirr_rule && sw_id == mirr_rule->index) {
9643                 if (on) {
9644                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9645                         return -EEXIST;
9646                 } else {
9647                         ret = i40e_aq_del_mirror_rule(hw, seid,
9648                                         mirr_rule->rule_type,
9649                                         mirr_rule->entries,
9650                                         mirr_rule->num_entries, mirr_rule->id);
9651                         if (ret < 0) {
9652                                 PMD_DRV_LOG(ERR,
9653                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9654                                         ret, hw->aq.asq_last_status);
9655                                 return -ENOSYS;
9656                         }
9657                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9658                         rte_free(mirr_rule);
9659                         pf->nb_mirror_rule--;
9660                         return 0;
9661                 }
9662         } else if (!on) {
9663                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9664                 return -ENOENT;
9665         }
9666
9667         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9668                                 sizeof(struct i40e_mirror_rule) , 0);
9669         if (!mirr_rule) {
9670                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9671                 return I40E_ERR_NO_MEMORY;
9672         }
9673         switch (mirror_conf->rule_type) {
9674         case ETH_MIRROR_VLAN:
9675                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9676                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9677                                 mirr_rule->entries[j] =
9678                                         mirror_conf->vlan.vlan_id[i];
9679                                 j++;
9680                         }
9681                 }
9682                 if (j == 0) {
9683                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9684                         rte_free(mirr_rule);
9685                         return -EINVAL;
9686                 }
9687                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9688                 break;
9689         case ETH_MIRROR_VIRTUAL_POOL_UP:
9690         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9691                 /* check if the specified pool bit is out of range */
9692                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9693                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9694                         rte_free(mirr_rule);
9695                         return -EINVAL;
9696                 }
9697                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9698                         if (mirror_conf->pool_mask & (1ULL << i)) {
9699                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9700                                 j++;
9701                         }
9702                 }
9703                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9704                         /* add pf vsi to entries */
9705                         mirr_rule->entries[j] = pf->main_vsi_seid;
9706                         j++;
9707                 }
9708                 if (j == 0) {
9709                         PMD_DRV_LOG(ERR, "pool is not specified.");
9710                         rte_free(mirr_rule);
9711                         return -EINVAL;
9712                 }
9713                 /* egress and ingress in aq commands means from switch but not port */
9714                 mirr_rule->rule_type =
9715                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9716                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9717                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9718                 break;
9719         case ETH_MIRROR_UPLINK_PORT:
9720                 /* egress and ingress in aq commands means from switch but not port*/
9721                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9722                 break;
9723         case ETH_MIRROR_DOWNLINK_PORT:
9724                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9725                 break;
9726         default:
9727                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9728                         mirror_conf->rule_type);
9729                 rte_free(mirr_rule);
9730                 return -EINVAL;
9731         }
9732
9733         /* If the dst_pool is equal to vf_num, consider it as PF */
9734         if (mirror_conf->dst_pool == pf->vf_num)
9735                 dst_seid = pf->main_vsi_seid;
9736         else
9737                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9738
9739         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9740                                       mirr_rule->rule_type, mirr_rule->entries,
9741                                       j, &rule_id);
9742         if (ret < 0) {
9743                 PMD_DRV_LOG(ERR,
9744                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9745                         ret, hw->aq.asq_last_status);
9746                 rte_free(mirr_rule);
9747                 return -ENOSYS;
9748         }
9749
9750         mirr_rule->index = sw_id;
9751         mirr_rule->num_entries = j;
9752         mirr_rule->id = rule_id;
9753         mirr_rule->dst_vsi_seid = dst_seid;
9754
9755         if (parent)
9756                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9757         else
9758                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9759
9760         pf->nb_mirror_rule++;
9761         return 0;
9762 }
9763
9764 /**
9765  * i40e_mirror_rule_reset
9766  * @dev: pointer to the device
9767  * @sw_id: mirror rule's sw_id
9768  *
9769  * reset a mirror rule.
9770  *
9771  **/
9772 static int
9773 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9774 {
9775         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9776         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9777         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9778         uint16_t seid;
9779         int ret;
9780
9781         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9782
9783         seid = pf->main_vsi->veb->seid;
9784
9785         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9786                 if (sw_id == it->index) {
9787                         mirr_rule = it;
9788                         break;
9789                 }
9790         }
9791         if (mirr_rule) {
9792                 ret = i40e_aq_del_mirror_rule(hw, seid,
9793                                 mirr_rule->rule_type,
9794                                 mirr_rule->entries,
9795                                 mirr_rule->num_entries, mirr_rule->id);
9796                 if (ret < 0) {
9797                         PMD_DRV_LOG(ERR,
9798                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9799                                 ret, hw->aq.asq_last_status);
9800                         return -ENOSYS;
9801                 }
9802                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9803                 rte_free(mirr_rule);
9804                 pf->nb_mirror_rule--;
9805         } else {
9806                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9807                 return -ENOENT;
9808         }
9809         return 0;
9810 }
9811
9812 static uint64_t
9813 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9814 {
9815         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9816         uint64_t systim_cycles;
9817
9818         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9819         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9820                         << 32;
9821
9822         return systim_cycles;
9823 }
9824
9825 static uint64_t
9826 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9827 {
9828         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9829         uint64_t rx_tstamp;
9830
9831         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9832         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9833                         << 32;
9834
9835         return rx_tstamp;
9836 }
9837
9838 static uint64_t
9839 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9840 {
9841         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9842         uint64_t tx_tstamp;
9843
9844         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9845         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9846                         << 32;
9847
9848         return tx_tstamp;
9849 }
9850
9851 static void
9852 i40e_start_timecounters(struct rte_eth_dev *dev)
9853 {
9854         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9855         struct i40e_adapter *adapter =
9856                         (struct i40e_adapter *)dev->data->dev_private;
9857         struct rte_eth_link link;
9858         uint32_t tsync_inc_l;
9859         uint32_t tsync_inc_h;
9860
9861         /* Get current link speed. */
9862         memset(&link, 0, sizeof(link));
9863         i40e_dev_link_update(dev, 1);
9864         rte_i40e_dev_atomic_read_link_status(dev, &link);
9865
9866         switch (link.link_speed) {
9867         case ETH_SPEED_NUM_40G:
9868                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9869                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9870                 break;
9871         case ETH_SPEED_NUM_10G:
9872                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9873                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9874                 break;
9875         case ETH_SPEED_NUM_1G:
9876                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9877                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9878                 break;
9879         default:
9880                 tsync_inc_l = 0x0;
9881                 tsync_inc_h = 0x0;
9882         }
9883
9884         /* Set the timesync increment value. */
9885         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9886         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9887
9888         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9889         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9890         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9891
9892         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9893         adapter->systime_tc.cc_shift = 0;
9894         adapter->systime_tc.nsec_mask = 0;
9895
9896         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9897         adapter->rx_tstamp_tc.cc_shift = 0;
9898         adapter->rx_tstamp_tc.nsec_mask = 0;
9899
9900         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9901         adapter->tx_tstamp_tc.cc_shift = 0;
9902         adapter->tx_tstamp_tc.nsec_mask = 0;
9903 }
9904
9905 static int
9906 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9907 {
9908         struct i40e_adapter *adapter =
9909                         (struct i40e_adapter *)dev->data->dev_private;
9910
9911         adapter->systime_tc.nsec += delta;
9912         adapter->rx_tstamp_tc.nsec += delta;
9913         adapter->tx_tstamp_tc.nsec += delta;
9914
9915         return 0;
9916 }
9917
9918 static int
9919 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9920 {
9921         uint64_t ns;
9922         struct i40e_adapter *adapter =
9923                         (struct i40e_adapter *)dev->data->dev_private;
9924
9925         ns = rte_timespec_to_ns(ts);
9926
9927         /* Set the timecounters to a new value. */
9928         adapter->systime_tc.nsec = ns;
9929         adapter->rx_tstamp_tc.nsec = ns;
9930         adapter->tx_tstamp_tc.nsec = ns;
9931
9932         return 0;
9933 }
9934
9935 static int
9936 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9937 {
9938         uint64_t ns, systime_cycles;
9939         struct i40e_adapter *adapter =
9940                         (struct i40e_adapter *)dev->data->dev_private;
9941
9942         systime_cycles = i40e_read_systime_cyclecounter(dev);
9943         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9944         *ts = rte_ns_to_timespec(ns);
9945
9946         return 0;
9947 }
9948
9949 static int
9950 i40e_timesync_enable(struct rte_eth_dev *dev)
9951 {
9952         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9953         uint32_t tsync_ctl_l;
9954         uint32_t tsync_ctl_h;
9955
9956         /* Stop the timesync system time. */
9957         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9958         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9959         /* Reset the timesync system time value. */
9960         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9961         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9962
9963         i40e_start_timecounters(dev);
9964
9965         /* Clear timesync registers. */
9966         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9967         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9968         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9969         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9970         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9971         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9972
9973         /* Enable timestamping of PTP packets. */
9974         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9975         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9976
9977         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9978         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9979         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9980
9981         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9982         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9983
9984         return 0;
9985 }
9986
9987 static int
9988 i40e_timesync_disable(struct rte_eth_dev *dev)
9989 {
9990         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9991         uint32_t tsync_ctl_l;
9992         uint32_t tsync_ctl_h;
9993
9994         /* Disable timestamping of transmitted PTP packets. */
9995         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9996         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9997
9998         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9999         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10000
10001         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10002         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10003
10004         /* Reset the timesync increment value. */
10005         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10006         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10007
10008         return 0;
10009 }
10010
10011 static int
10012 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10013                                 struct timespec *timestamp, uint32_t flags)
10014 {
10015         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10016         struct i40e_adapter *adapter =
10017                 (struct i40e_adapter *)dev->data->dev_private;
10018
10019         uint32_t sync_status;
10020         uint32_t index = flags & 0x03;
10021         uint64_t rx_tstamp_cycles;
10022         uint64_t ns;
10023
10024         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10025         if ((sync_status & (1 << index)) == 0)
10026                 return -EINVAL;
10027
10028         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10029         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10030         *timestamp = rte_ns_to_timespec(ns);
10031
10032         return 0;
10033 }
10034
10035 static int
10036 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10037                                 struct timespec *timestamp)
10038 {
10039         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10040         struct i40e_adapter *adapter =
10041                 (struct i40e_adapter *)dev->data->dev_private;
10042
10043         uint32_t sync_status;
10044         uint64_t tx_tstamp_cycles;
10045         uint64_t ns;
10046
10047         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10048         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10049                 return -EINVAL;
10050
10051         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10052         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10053         *timestamp = rte_ns_to_timespec(ns);
10054
10055         return 0;
10056 }
10057
10058 /*
10059  * i40e_parse_dcb_configure - parse dcb configure from user
10060  * @dev: the device being configured
10061  * @dcb_cfg: pointer of the result of parse
10062  * @*tc_map: bit map of enabled traffic classes
10063  *
10064  * Returns 0 on success, negative value on failure
10065  */
10066 static int
10067 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10068                          struct i40e_dcbx_config *dcb_cfg,
10069                          uint8_t *tc_map)
10070 {
10071         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10072         uint8_t i, tc_bw, bw_lf;
10073
10074         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10075
10076         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10077         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10078                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10079                 return -EINVAL;
10080         }
10081
10082         /* assume each tc has the same bw */
10083         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10084         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10085                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10086         /* to ensure the sum of tcbw is equal to 100 */
10087         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10088         for (i = 0; i < bw_lf; i++)
10089                 dcb_cfg->etscfg.tcbwtable[i]++;
10090
10091         /* assume each tc has the same Transmission Selection Algorithm */
10092         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10093                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10094
10095         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10096                 dcb_cfg->etscfg.prioritytable[i] =
10097                                 dcb_rx_conf->dcb_tc[i];
10098
10099         /* FW needs one App to configure HW */
10100         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10101         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10102         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10103         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10104
10105         if (dcb_rx_conf->nb_tcs == 0)
10106                 *tc_map = 1; /* tc0 only */
10107         else
10108                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10109
10110         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10111                 dcb_cfg->pfc.willing = 0;
10112                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10113                 dcb_cfg->pfc.pfcenable = *tc_map;
10114         }
10115         return 0;
10116 }
10117
10118
10119 static enum i40e_status_code
10120 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10121                               struct i40e_aqc_vsi_properties_data *info,
10122                               uint8_t enabled_tcmap)
10123 {
10124         enum i40e_status_code ret;
10125         int i, total_tc = 0;
10126         uint16_t qpnum_per_tc, bsf, qp_idx;
10127         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10128         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10129         uint16_t used_queues;
10130
10131         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10132         if (ret != I40E_SUCCESS)
10133                 return ret;
10134
10135         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10136                 if (enabled_tcmap & (1 << i))
10137                         total_tc++;
10138         }
10139         if (total_tc == 0)
10140                 total_tc = 1;
10141         vsi->enabled_tc = enabled_tcmap;
10142
10143         /* different VSI has different queues assigned */
10144         if (vsi->type == I40E_VSI_MAIN)
10145                 used_queues = dev_data->nb_rx_queues -
10146                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10147         else if (vsi->type == I40E_VSI_VMDQ2)
10148                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10149         else {
10150                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10151                 return I40E_ERR_NO_AVAILABLE_VSI;
10152         }
10153
10154         qpnum_per_tc = used_queues / total_tc;
10155         /* Number of queues per enabled TC */
10156         if (qpnum_per_tc == 0) {
10157                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10158                 return I40E_ERR_INVALID_QP_ID;
10159         }
10160         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10161                                 I40E_MAX_Q_PER_TC);
10162         bsf = rte_bsf32(qpnum_per_tc);
10163
10164         /**
10165          * Configure TC and queue mapping parameters, for enabled TC,
10166          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10167          * default queue will serve it.
10168          */
10169         qp_idx = 0;
10170         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10171                 if (vsi->enabled_tc & (1 << i)) {
10172                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10173                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10174                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10175                         qp_idx += qpnum_per_tc;
10176                 } else
10177                         info->tc_mapping[i] = 0;
10178         }
10179
10180         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10181         if (vsi->type == I40E_VSI_SRIOV) {
10182                 info->mapping_flags |=
10183                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10184                 for (i = 0; i < vsi->nb_qps; i++)
10185                         info->queue_mapping[i] =
10186                                 rte_cpu_to_le_16(vsi->base_queue + i);
10187         } else {
10188                 info->mapping_flags |=
10189                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10190                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10191         }
10192         info->valid_sections |=
10193                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10194
10195         return I40E_SUCCESS;
10196 }
10197
10198 /*
10199  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10200  * @veb: VEB to be configured
10201  * @tc_map: enabled TC bitmap
10202  *
10203  * Returns 0 on success, negative value on failure
10204  */
10205 static enum i40e_status_code
10206 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10207 {
10208         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10209         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10210         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10211         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10212         enum i40e_status_code ret = I40E_SUCCESS;
10213         int i;
10214         uint32_t bw_max;
10215
10216         /* Check if enabled_tc is same as existing or new TCs */
10217         if (veb->enabled_tc == tc_map)
10218                 return ret;
10219
10220         /* configure tc bandwidth */
10221         memset(&veb_bw, 0, sizeof(veb_bw));
10222         veb_bw.tc_valid_bits = tc_map;
10223         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10224         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10225                 if (tc_map & BIT_ULL(i))
10226                         veb_bw.tc_bw_share_credits[i] = 1;
10227         }
10228         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10229                                                    &veb_bw, NULL);
10230         if (ret) {
10231                 PMD_INIT_LOG(ERR,
10232                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10233                         hw->aq.asq_last_status);
10234                 return ret;
10235         }
10236
10237         memset(&ets_query, 0, sizeof(ets_query));
10238         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10239                                                    &ets_query, NULL);
10240         if (ret != I40E_SUCCESS) {
10241                 PMD_DRV_LOG(ERR,
10242                         "Failed to get switch_comp ETS configuration %u",
10243                         hw->aq.asq_last_status);
10244                 return ret;
10245         }
10246         memset(&bw_query, 0, sizeof(bw_query));
10247         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10248                                                   &bw_query, NULL);
10249         if (ret != I40E_SUCCESS) {
10250                 PMD_DRV_LOG(ERR,
10251                         "Failed to get switch_comp bandwidth configuration %u",
10252                         hw->aq.asq_last_status);
10253                 return ret;
10254         }
10255
10256         /* store and print out BW info */
10257         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10258         veb->bw_info.bw_max = ets_query.tc_bw_max;
10259         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10260         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10261         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10262                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10263                      I40E_16_BIT_WIDTH);
10264         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10265                 veb->bw_info.bw_ets_share_credits[i] =
10266                                 bw_query.tc_bw_share_credits[i];
10267                 veb->bw_info.bw_ets_credits[i] =
10268                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10269                 /* 4 bits per TC, 4th bit is reserved */
10270                 veb->bw_info.bw_ets_max[i] =
10271                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10272                                   RTE_LEN2MASK(3, uint8_t));
10273                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10274                             veb->bw_info.bw_ets_share_credits[i]);
10275                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10276                             veb->bw_info.bw_ets_credits[i]);
10277                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10278                             veb->bw_info.bw_ets_max[i]);
10279         }
10280
10281         veb->enabled_tc = tc_map;
10282
10283         return ret;
10284 }
10285
10286
10287 /*
10288  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10289  * @vsi: VSI to be configured
10290  * @tc_map: enabled TC bitmap
10291  *
10292  * Returns 0 on success, negative value on failure
10293  */
10294 static enum i40e_status_code
10295 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10296 {
10297         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10298         struct i40e_vsi_context ctxt;
10299         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10300         enum i40e_status_code ret = I40E_SUCCESS;
10301         int i;
10302
10303         /* Check if enabled_tc is same as existing or new TCs */
10304         if (vsi->enabled_tc == tc_map)
10305                 return ret;
10306
10307         /* configure tc bandwidth */
10308         memset(&bw_data, 0, sizeof(bw_data));
10309         bw_data.tc_valid_bits = tc_map;
10310         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10311         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10312                 if (tc_map & BIT_ULL(i))
10313                         bw_data.tc_bw_credits[i] = 1;
10314         }
10315         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10316         if (ret) {
10317                 PMD_INIT_LOG(ERR,
10318                         "AQ command Config VSI BW allocation per TC failed = %d",
10319                         hw->aq.asq_last_status);
10320                 goto out;
10321         }
10322         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10323                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10324
10325         /* Update Queue Pairs Mapping for currently enabled UPs */
10326         ctxt.seid = vsi->seid;
10327         ctxt.pf_num = hw->pf_id;
10328         ctxt.vf_num = 0;
10329         ctxt.uplink_seid = vsi->uplink_seid;
10330         ctxt.info = vsi->info;
10331         i40e_get_cap(hw);
10332         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10333         if (ret)
10334                 goto out;
10335
10336         /* Update the VSI after updating the VSI queue-mapping information */
10337         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10338         if (ret) {
10339                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10340                         hw->aq.asq_last_status);
10341                 goto out;
10342         }
10343         /* update the local VSI info with updated queue map */
10344         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10345                                         sizeof(vsi->info.tc_mapping));
10346         rte_memcpy(&vsi->info.queue_mapping,
10347                         &ctxt.info.queue_mapping,
10348                 sizeof(vsi->info.queue_mapping));
10349         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10350         vsi->info.valid_sections = 0;
10351
10352         /* query and update current VSI BW information */
10353         ret = i40e_vsi_get_bw_config(vsi);
10354         if (ret) {
10355                 PMD_INIT_LOG(ERR,
10356                          "Failed updating vsi bw info, err %s aq_err %s",
10357                          i40e_stat_str(hw, ret),
10358                          i40e_aq_str(hw, hw->aq.asq_last_status));
10359                 goto out;
10360         }
10361
10362         vsi->enabled_tc = tc_map;
10363
10364 out:
10365         return ret;
10366 }
10367
10368 /*
10369  * i40e_dcb_hw_configure - program the dcb setting to hw
10370  * @pf: pf the configuration is taken on
10371  * @new_cfg: new configuration
10372  * @tc_map: enabled TC bitmap
10373  *
10374  * Returns 0 on success, negative value on failure
10375  */
10376 static enum i40e_status_code
10377 i40e_dcb_hw_configure(struct i40e_pf *pf,
10378                       struct i40e_dcbx_config *new_cfg,
10379                       uint8_t tc_map)
10380 {
10381         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10382         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10383         struct i40e_vsi *main_vsi = pf->main_vsi;
10384         struct i40e_vsi_list *vsi_list;
10385         enum i40e_status_code ret;
10386         int i;
10387         uint32_t val;
10388
10389         /* Use the FW API if FW > v4.4*/
10390         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10391               (hw->aq.fw_maj_ver >= 5))) {
10392                 PMD_INIT_LOG(ERR,
10393                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10394                 return I40E_ERR_FIRMWARE_API_VERSION;
10395         }
10396
10397         /* Check if need reconfiguration */
10398         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10399                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10400                 return I40E_SUCCESS;
10401         }
10402
10403         /* Copy the new config to the current config */
10404         *old_cfg = *new_cfg;
10405         old_cfg->etsrec = old_cfg->etscfg;
10406         ret = i40e_set_dcb_config(hw);
10407         if (ret) {
10408                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10409                          i40e_stat_str(hw, ret),
10410                          i40e_aq_str(hw, hw->aq.asq_last_status));
10411                 return ret;
10412         }
10413         /* set receive Arbiter to RR mode and ETS scheme by default */
10414         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10415                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10416                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10417                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10418                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10419                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10420                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10421                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10422                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10423                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10424                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10425                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10426                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10427         }
10428         /* get local mib to check whether it is configured correctly */
10429         /* IEEE mode */
10430         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10431         /* Get Local DCB Config */
10432         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10433                                      &hw->local_dcbx_config);
10434
10435         /* if Veb is created, need to update TC of it at first */
10436         if (main_vsi->veb) {
10437                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10438                 if (ret)
10439                         PMD_INIT_LOG(WARNING,
10440                                  "Failed configuring TC for VEB seid=%d",
10441                                  main_vsi->veb->seid);
10442         }
10443         /* Update each VSI */
10444         i40e_vsi_config_tc(main_vsi, tc_map);
10445         if (main_vsi->veb) {
10446                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10447                         /* Beside main VSI and VMDQ VSIs, only enable default
10448                          * TC for other VSIs
10449                          */
10450                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10451                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10452                                                          tc_map);
10453                         else
10454                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10455                                                          I40E_DEFAULT_TCMAP);
10456                         if (ret)
10457                                 PMD_INIT_LOG(WARNING,
10458                                         "Failed configuring TC for VSI seid=%d",
10459                                         vsi_list->vsi->seid);
10460                         /* continue */
10461                 }
10462         }
10463         return I40E_SUCCESS;
10464 }
10465
10466 /*
10467  * i40e_dcb_init_configure - initial dcb config
10468  * @dev: device being configured
10469  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10470  *
10471  * Returns 0 on success, negative value on failure
10472  */
10473 static int
10474 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10475 {
10476         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10477         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10478         int i, ret = 0;
10479
10480         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10481                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10482                 return -ENOTSUP;
10483         }
10484
10485         /* DCB initialization:
10486          * Update DCB configuration from the Firmware and configure
10487          * LLDP MIB change event.
10488          */
10489         if (sw_dcb == TRUE) {
10490                 ret = i40e_init_dcb(hw);
10491                 /* If lldp agent is stopped, the return value from
10492                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10493                  * adminq status. Otherwise, it should return success.
10494                  */
10495                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10496                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10497                         memset(&hw->local_dcbx_config, 0,
10498                                 sizeof(struct i40e_dcbx_config));
10499                         /* set dcb default configuration */
10500                         hw->local_dcbx_config.etscfg.willing = 0;
10501                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10502                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10503                         hw->local_dcbx_config.etscfg.tsatable[0] =
10504                                                 I40E_IEEE_TSA_ETS;
10505                         /* all UPs mapping to TC0 */
10506                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10507                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10508                         hw->local_dcbx_config.etsrec =
10509                                 hw->local_dcbx_config.etscfg;
10510                         hw->local_dcbx_config.pfc.willing = 0;
10511                         hw->local_dcbx_config.pfc.pfccap =
10512                                                 I40E_MAX_TRAFFIC_CLASS;
10513                         /* FW needs one App to configure HW */
10514                         hw->local_dcbx_config.numapps = 1;
10515                         hw->local_dcbx_config.app[0].selector =
10516                                                 I40E_APP_SEL_ETHTYPE;
10517                         hw->local_dcbx_config.app[0].priority = 3;
10518                         hw->local_dcbx_config.app[0].protocolid =
10519                                                 I40E_APP_PROTOID_FCOE;
10520                         ret = i40e_set_dcb_config(hw);
10521                         if (ret) {
10522                                 PMD_INIT_LOG(ERR,
10523                                         "default dcb config fails. err = %d, aq_err = %d.",
10524                                         ret, hw->aq.asq_last_status);
10525                                 return -ENOSYS;
10526                         }
10527                 } else {
10528                         PMD_INIT_LOG(ERR,
10529                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10530                                 ret, hw->aq.asq_last_status);
10531                         return -ENOTSUP;
10532                 }
10533         } else {
10534                 ret = i40e_aq_start_lldp(hw, NULL);
10535                 if (ret != I40E_SUCCESS)
10536                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10537
10538                 ret = i40e_init_dcb(hw);
10539                 if (!ret) {
10540                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10541                                 PMD_INIT_LOG(ERR,
10542                                         "HW doesn't support DCBX offload.");
10543                                 return -ENOTSUP;
10544                         }
10545                 } else {
10546                         PMD_INIT_LOG(ERR,
10547                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10548                                 ret, hw->aq.asq_last_status);
10549                         return -ENOTSUP;
10550                 }
10551         }
10552         return 0;
10553 }
10554
10555 /*
10556  * i40e_dcb_setup - setup dcb related config
10557  * @dev: device being configured
10558  *
10559  * Returns 0 on success, negative value on failure
10560  */
10561 static int
10562 i40e_dcb_setup(struct rte_eth_dev *dev)
10563 {
10564         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10565         struct i40e_dcbx_config dcb_cfg;
10566         uint8_t tc_map = 0;
10567         int ret = 0;
10568
10569         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10570                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10571                 return -ENOTSUP;
10572         }
10573
10574         if (pf->vf_num != 0)
10575                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10576
10577         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10578         if (ret) {
10579                 PMD_INIT_LOG(ERR, "invalid dcb config");
10580                 return -EINVAL;
10581         }
10582         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10583         if (ret) {
10584                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10585                 return -ENOSYS;
10586         }
10587
10588         return 0;
10589 }
10590
10591 static int
10592 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10593                       struct rte_eth_dcb_info *dcb_info)
10594 {
10595         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10596         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10597         struct i40e_vsi *vsi = pf->main_vsi;
10598         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10599         uint16_t bsf, tc_mapping;
10600         int i, j = 0;
10601
10602         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10603                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10604         else
10605                 dcb_info->nb_tcs = 1;
10606         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10607                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10608         for (i = 0; i < dcb_info->nb_tcs; i++)
10609                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10610
10611         /* get queue mapping if vmdq is disabled */
10612         if (!pf->nb_cfg_vmdq_vsi) {
10613                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10614                         if (!(vsi->enabled_tc & (1 << i)))
10615                                 continue;
10616                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10617                         dcb_info->tc_queue.tc_rxq[j][i].base =
10618                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10619                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10620                         dcb_info->tc_queue.tc_txq[j][i].base =
10621                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10622                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10623                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10624                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10625                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10626                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10627                 }
10628                 return 0;
10629         }
10630
10631         /* get queue mapping if vmdq is enabled */
10632         do {
10633                 vsi = pf->vmdq[j].vsi;
10634                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10635                         if (!(vsi->enabled_tc & (1 << i)))
10636                                 continue;
10637                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10638                         dcb_info->tc_queue.tc_rxq[j][i].base =
10639                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10640                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10641                         dcb_info->tc_queue.tc_txq[j][i].base =
10642                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10643                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10644                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10645                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10646                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10647                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10648                 }
10649                 j++;
10650         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10651         return 0;
10652 }
10653
10654 static int
10655 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10656 {
10657         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10658         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10659         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10660         uint16_t interval =
10661                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10662         uint16_t msix_intr;
10663
10664         msix_intr = intr_handle->intr_vec[queue_id];
10665         if (msix_intr == I40E_MISC_VEC_ID)
10666                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10667                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10668                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10669                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10670                                (interval <<
10671                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10672         else
10673                 I40E_WRITE_REG(hw,
10674                                I40E_PFINT_DYN_CTLN(msix_intr -
10675                                                    I40E_RX_VEC_START),
10676                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10677                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10678                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10679                                (interval <<
10680                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10681
10682         I40E_WRITE_FLUSH(hw);
10683         rte_intr_enable(&pci_dev->intr_handle);
10684
10685         return 0;
10686 }
10687
10688 static int
10689 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10690 {
10691         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10692         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10693         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10694         uint16_t msix_intr;
10695
10696         msix_intr = intr_handle->intr_vec[queue_id];
10697         if (msix_intr == I40E_MISC_VEC_ID)
10698                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10699         else
10700                 I40E_WRITE_REG(hw,
10701                                I40E_PFINT_DYN_CTLN(msix_intr -
10702                                                    I40E_RX_VEC_START),
10703                                0);
10704         I40E_WRITE_FLUSH(hw);
10705
10706         return 0;
10707 }
10708
10709 static int i40e_get_regs(struct rte_eth_dev *dev,
10710                          struct rte_dev_reg_info *regs)
10711 {
10712         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10713         uint32_t *ptr_data = regs->data;
10714         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10715         const struct i40e_reg_info *reg_info;
10716
10717         if (ptr_data == NULL) {
10718                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10719                 regs->width = sizeof(uint32_t);
10720                 return 0;
10721         }
10722
10723         /* The first few registers have to be read using AQ operations */
10724         reg_idx = 0;
10725         while (i40e_regs_adminq[reg_idx].name) {
10726                 reg_info = &i40e_regs_adminq[reg_idx++];
10727                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10728                         for (arr_idx2 = 0;
10729                                         arr_idx2 <= reg_info->count2;
10730                                         arr_idx2++) {
10731                                 reg_offset = arr_idx * reg_info->stride1 +
10732                                         arr_idx2 * reg_info->stride2;
10733                                 reg_offset += reg_info->base_addr;
10734                                 ptr_data[reg_offset >> 2] =
10735                                         i40e_read_rx_ctl(hw, reg_offset);
10736                         }
10737         }
10738
10739         /* The remaining registers can be read using primitives */
10740         reg_idx = 0;
10741         while (i40e_regs_others[reg_idx].name) {
10742                 reg_info = &i40e_regs_others[reg_idx++];
10743                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10744                         for (arr_idx2 = 0;
10745                                         arr_idx2 <= reg_info->count2;
10746                                         arr_idx2++) {
10747                                 reg_offset = arr_idx * reg_info->stride1 +
10748                                         arr_idx2 * reg_info->stride2;
10749                                 reg_offset += reg_info->base_addr;
10750                                 ptr_data[reg_offset >> 2] =
10751                                         I40E_READ_REG(hw, reg_offset);
10752                         }
10753         }
10754
10755         return 0;
10756 }
10757
10758 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10759 {
10760         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10761
10762         /* Convert word count to byte count */
10763         return hw->nvm.sr_size << 1;
10764 }
10765
10766 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10767                            struct rte_dev_eeprom_info *eeprom)
10768 {
10769         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10770         uint16_t *data = eeprom->data;
10771         uint16_t offset, length, cnt_words;
10772         int ret_code;
10773
10774         offset = eeprom->offset >> 1;
10775         length = eeprom->length >> 1;
10776         cnt_words = length;
10777
10778         if (offset > hw->nvm.sr_size ||
10779                 offset + length > hw->nvm.sr_size) {
10780                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10781                 return -EINVAL;
10782         }
10783
10784         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10785
10786         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10787         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10788                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10789                 return -EIO;
10790         }
10791
10792         return 0;
10793 }
10794
10795 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10796                                       struct ether_addr *mac_addr)
10797 {
10798         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10799
10800         if (!is_valid_assigned_ether_addr(mac_addr)) {
10801                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10802                 return;
10803         }
10804
10805         /* Flags: 0x3 updates port address */
10806         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10807 }
10808
10809 static int
10810 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10811 {
10812         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10813         struct rte_eth_dev_data *dev_data = pf->dev_data;
10814         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10815         int ret = 0;
10816
10817         /* check if mtu is within the allowed range */
10818         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10819                 return -EINVAL;
10820
10821         /* mtu setting is forbidden if port is start */
10822         if (dev_data->dev_started) {
10823                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10824                             dev_data->port_id);
10825                 return -EBUSY;
10826         }
10827
10828         if (frame_size > ETHER_MAX_LEN)
10829                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10830         else
10831                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10832
10833         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10834
10835         return ret;
10836 }
10837
10838 /* Restore ethertype filter */
10839 static void
10840 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10841 {
10842         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10843         struct i40e_ethertype_filter_list
10844                 *ethertype_list = &pf->ethertype.ethertype_list;
10845         struct i40e_ethertype_filter *f;
10846         struct i40e_control_filter_stats stats;
10847         uint16_t flags;
10848
10849         TAILQ_FOREACH(f, ethertype_list, rules) {
10850                 flags = 0;
10851                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10852                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10853                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10854                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10855                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10856
10857                 memset(&stats, 0, sizeof(stats));
10858                 i40e_aq_add_rem_control_packet_filter(hw,
10859                                             f->input.mac_addr.addr_bytes,
10860                                             f->input.ether_type,
10861                                             flags, pf->main_vsi->seid,
10862                                             f->queue, 1, &stats, NULL);
10863         }
10864         PMD_DRV_LOG(INFO, "Ethertype filter:"
10865                     " mac_etype_used = %u, etype_used = %u,"
10866                     " mac_etype_free = %u, etype_free = %u",
10867                     stats.mac_etype_used, stats.etype_used,
10868                     stats.mac_etype_free, stats.etype_free);
10869 }
10870
10871 /* Restore tunnel filter */
10872 static void
10873 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10874 {
10875         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10876         struct i40e_vsi *vsi;
10877         struct i40e_pf_vf *vf;
10878         struct i40e_tunnel_filter_list
10879                 *tunnel_list = &pf->tunnel.tunnel_list;
10880         struct i40e_tunnel_filter *f;
10881         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10882         bool big_buffer = 0;
10883
10884         TAILQ_FOREACH(f, tunnel_list, rules) {
10885                 if (!f->is_to_vf)
10886                         vsi = pf->main_vsi;
10887                 else {
10888                         vf = &pf->vfs[f->vf_id];
10889                         vsi = vf->vsi;
10890                 }
10891                 memset(&cld_filter, 0, sizeof(cld_filter));
10892                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10893                         (struct ether_addr *)&cld_filter.element.outer_mac);
10894                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10895                         (struct ether_addr *)&cld_filter.element.inner_mac);
10896                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10897                 cld_filter.element.flags = f->input.flags;
10898                 cld_filter.element.tenant_id = f->input.tenant_id;
10899                 cld_filter.element.queue_number = f->queue;
10900                 rte_memcpy(cld_filter.general_fields,
10901                            f->input.general_fields,
10902                            sizeof(f->input.general_fields));
10903
10904                 if (((f->input.flags &
10905                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
10906                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
10907                     ((f->input.flags &
10908                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
10909                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
10910                     ((f->input.flags &
10911                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
10912                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
10913                         big_buffer = 1;
10914
10915                 if (big_buffer)
10916                         i40e_aq_add_cloud_filters_big_buffer(hw,
10917                                              vsi->seid, &cld_filter, 1);
10918                 else
10919                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10920                                                   &cld_filter.element, 1);
10921         }
10922 }
10923
10924 static void
10925 i40e_filter_restore(struct i40e_pf *pf)
10926 {
10927         i40e_ethertype_filter_restore(pf);
10928         i40e_tunnel_filter_restore(pf);
10929         i40e_fdir_filter_restore(pf);
10930 }
10931
10932 static bool
10933 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10934 {
10935         if (strcmp(dev->device->driver->name, drv->driver.name))
10936                 return false;
10937
10938         return true;
10939 }
10940
10941 bool
10942 is_i40e_supported(struct rte_eth_dev *dev)
10943 {
10944         return is_device_supported(dev, &rte_i40e_pmd);
10945 }
10946
10947 struct i40e_customized_pctype*
10948 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
10949 {
10950         int i;
10951
10952         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
10953                 if (pf->customized_pctype[i].index == index)
10954                         return &pf->customized_pctype[i];
10955         }
10956         return NULL;
10957 }
10958
10959 static int
10960 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
10961                               uint32_t pkg_size, uint32_t proto_num,
10962                               struct rte_pmd_i40e_proto_info *proto)
10963 {
10964         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10965         uint32_t pctype_num;
10966         struct rte_pmd_i40e_ptype_info *pctype;
10967         uint32_t buff_size;
10968         struct i40e_customized_pctype *new_pctype = NULL;
10969         uint8_t proto_id;
10970         uint8_t pctype_value;
10971         char name[64];
10972         uint32_t i, j, n;
10973         int ret;
10974
10975         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
10976                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
10977                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
10978         if (ret) {
10979                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
10980                 return -1;
10981         }
10982         if (!pctype_num) {
10983                 PMD_DRV_LOG(INFO, "No new pctype added");
10984                 return -1;
10985         }
10986
10987         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
10988         pctype = rte_zmalloc("new_pctype", buff_size, 0);
10989         if (!pctype) {
10990                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
10991                 return -1;
10992         }
10993         /* get information about new pctype list */
10994         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
10995                                         (uint8_t *)pctype, buff_size,
10996                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
10997         if (ret) {
10998                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
10999                 rte_free(pctype);
11000                 return -1;
11001         }
11002
11003         /* Update customized pctype. */
11004         for (i = 0; i < pctype_num; i++) {
11005                 pctype_value = pctype[i].ptype_id;
11006                 memset(name, 0, sizeof(name));
11007                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11008                         proto_id = pctype[i].protocols[j];
11009                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11010                                 continue;
11011                         for (n = 0; n < proto_num; n++) {
11012                                 if (proto[n].proto_id != proto_id)
11013                                         continue;
11014                                 strcat(name, proto[n].name);
11015                                 strcat(name, "_");
11016                                 break;
11017                         }
11018                 }
11019                 name[strlen(name) - 1] = '\0';
11020                 if (!strcmp(name, "GTPC"))
11021                         new_pctype =
11022                                 i40e_find_customized_pctype(pf,
11023                                                       I40E_CUSTOMIZED_GTPC);
11024                 else if (!strcmp(name, "GTPU_IPV4"))
11025                         new_pctype =
11026                                 i40e_find_customized_pctype(pf,
11027                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11028                 else if (!strcmp(name, "GTPU_IPV6"))
11029                         new_pctype =
11030                                 i40e_find_customized_pctype(pf,
11031                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11032                 else if (!strcmp(name, "GTPU"))
11033                         new_pctype =
11034                                 i40e_find_customized_pctype(pf,
11035                                                       I40E_CUSTOMIZED_GTPU);
11036                 if (new_pctype) {
11037                         new_pctype->pctype = pctype_value;
11038                         new_pctype->valid = true;
11039                 }
11040         }
11041
11042         rte_free(pctype);
11043         return 0;
11044 }
11045
11046 static int
11047 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11048                                uint32_t pkg_size, uint32_t proto_num,
11049                                struct rte_pmd_i40e_proto_info *proto)
11050 {
11051         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11052         uint8_t port_id = dev->data->port_id;
11053         uint32_t ptype_num;
11054         struct rte_pmd_i40e_ptype_info *ptype;
11055         uint32_t buff_size;
11056         uint8_t proto_id;
11057         char name[16];
11058         uint32_t i, j, n;
11059         bool inner_ip;
11060         int ret;
11061
11062         /* get information about new ptype num */
11063         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11064                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11065                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11066         if (ret) {
11067                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11068                 return ret;
11069         }
11070         if (!ptype_num) {
11071                 PMD_DRV_LOG(INFO, "No new ptype added");
11072                 return -1;
11073         }
11074
11075         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11076         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11077         if (!ptype) {
11078                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11079                 return -1;
11080         }
11081
11082         /* get information about new ptype list */
11083         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11084                                         (uint8_t *)ptype, buff_size,
11085                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11086         if (ret) {
11087                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11088                 rte_free(ptype);
11089                 return ret;
11090         }
11091
11092         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11093         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11094         if (!ptype_mapping) {
11095                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11096                 rte_free(ptype);
11097                 return -1;
11098         }
11099
11100         /* Update ptype mapping table. */
11101         for (i = 0; i < ptype_num; i++) {
11102                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11103                 ptype_mapping[i].sw_ptype = 0;
11104                 inner_ip = false;
11105                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11106                         proto_id = ptype[i].protocols[j];
11107                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11108                                 continue;
11109                         for (n = 0; n < proto_num; n++) {
11110                                 if (proto[n].proto_id != proto_id)
11111                                         continue;
11112                                 memset(name, 0, sizeof(name));
11113                                 strcpy(name, proto[n].name);
11114                                 if (!strncmp(name, "IPV4", 4) && !inner_ip) {
11115                                         ptype_mapping[i].sw_ptype |=
11116                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11117                                         inner_ip = true;
11118                                 } else if (!strncmp(name, "IPV4", 4) &&
11119                                            inner_ip) {
11120                                         ptype_mapping[i].sw_ptype |=
11121                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11122                                 } else if (!strncmp(name, "IPV6", 4) &&
11123                                            !inner_ip) {
11124                                         ptype_mapping[i].sw_ptype |=
11125                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11126                                         inner_ip = true;
11127                                 } else if (!strncmp(name, "IPV6", 4) &&
11128                                            inner_ip) {
11129                                         ptype_mapping[i].sw_ptype |=
11130                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11131                                 } else if (!strncmp(name, "IPV4FRAG", 8)) {
11132                                         ptype_mapping[i].sw_ptype |=
11133                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11134                                         ptype_mapping[i].sw_ptype |=
11135                                                 RTE_PTYPE_INNER_L4_FRAG;
11136                                 } else if (!strncmp(name, "IPV6FRAG", 8)) {
11137                                         ptype_mapping[i].sw_ptype |=
11138                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11139                                         ptype_mapping[i].sw_ptype |=
11140                                                 RTE_PTYPE_INNER_L4_FRAG;
11141                                 } else if (!strncmp(name, "GTPC", 4))
11142                                         ptype_mapping[i].sw_ptype |=
11143                                                 RTE_PTYPE_TUNNEL_GTPC;
11144                                 else if (!strncmp(name, "GTPU", 4))
11145                                         ptype_mapping[i].sw_ptype |=
11146                                                 RTE_PTYPE_TUNNEL_GTPU;
11147                                 else if (!strncmp(name, "UDP", 3))
11148                                         ptype_mapping[i].sw_ptype |=
11149                                                 RTE_PTYPE_INNER_L4_UDP;
11150                                 else if (!strncmp(name, "TCP", 3))
11151                                         ptype_mapping[i].sw_ptype |=
11152                                                 RTE_PTYPE_INNER_L4_TCP;
11153                                 else if (!strncmp(name, "SCTP", 4))
11154                                         ptype_mapping[i].sw_ptype |=
11155                                                 RTE_PTYPE_INNER_L4_SCTP;
11156                                 else if (!strncmp(name, "ICMP", 4) ||
11157                                          !strncmp(name, "ICMPV6", 6))
11158                                         ptype_mapping[i].sw_ptype |=
11159                                                 RTE_PTYPE_INNER_L4_ICMP;
11160
11161                                 break;
11162                         }
11163                 }
11164         }
11165
11166         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11167                                                 ptype_num, 0);
11168         if (ret)
11169                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11170
11171         rte_free(ptype_mapping);
11172         rte_free(ptype);
11173         return ret;
11174 }
11175
11176 void
11177 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11178                               uint32_t pkg_size)
11179 {
11180         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11181         uint32_t proto_num;
11182         struct rte_pmd_i40e_proto_info *proto;
11183         uint32_t buff_size;
11184         uint32_t i;
11185         int ret;
11186
11187         /* get information about protocol number */
11188         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11189                                        (uint8_t *)&proto_num, sizeof(proto_num),
11190                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11191         if (ret) {
11192                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11193                 return;
11194         }
11195         if (!proto_num) {
11196                 PMD_DRV_LOG(INFO, "No new protocol added");
11197                 return;
11198         }
11199
11200         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11201         proto = rte_zmalloc("new_proto", buff_size, 0);
11202         if (!proto) {
11203                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11204                 return;
11205         }
11206
11207         /* get information about protocol list */
11208         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11209                                         (uint8_t *)proto, buff_size,
11210                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11211         if (ret) {
11212                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11213                 rte_free(proto);
11214                 return;
11215         }
11216
11217         /* Check if GTP is supported. */
11218         for (i = 0; i < proto_num; i++) {
11219                 if (!strncmp(proto[i].name, "GTP", 3)) {
11220                         pf->gtp_support = true;
11221                         break;
11222                 }
11223         }
11224
11225         /* Update customized pctype info */
11226         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11227                                             proto_num, proto);
11228         if (ret)
11229                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11230
11231         /* Update customized ptype info */
11232         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11233                                            proto_num, proto);
11234         if (ret)
11235                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11236
11237         rte_free(proto);
11238 }
11239
11240 /* Create a QinQ cloud filter
11241  *
11242  * The Fortville NIC has limited resources for tunnel filters,
11243  * so we can only reuse existing filters.
11244  *
11245  * In step 1 we define which Field Vector fields can be used for
11246  * filter types.
11247  * As we do not have the inner tag defined as a field,
11248  * we have to define it first, by reusing one of L1 entries.
11249  *
11250  * In step 2 we are replacing one of existing filter types with
11251  * a new one for QinQ.
11252  * As we reusing L1 and replacing L2, some of the default filter
11253  * types will disappear,which depends on L1 and L2 entries we reuse.
11254  *
11255  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11256  *
11257  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11258  *              later when we define the cloud filter.
11259  *      a.      Valid_flags.replace_cloud = 0
11260  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11261  *      c.      New_filter = 0x10
11262  *      d.      TR bit = 0xff (optional, not used here)
11263  *      e.      Buffer – 2 entries:
11264  *              i.      Byte 0 = 8 (outer vlan FV index).
11265  *                      Byte 1 = 0 (rsv)
11266  *                      Byte 2-3 = 0x0fff
11267  *              ii.     Byte 0 = 37 (inner vlan FV index).
11268  *                      Byte 1 =0 (rsv)
11269  *                      Byte 2-3 = 0x0fff
11270  *
11271  * Step 2:
11272  * 2.   Create cloud filter using two L1 filters entries: stag and
11273  *              new filter(outer vlan+ inner vlan)
11274  *      a.      Valid_flags.replace_cloud = 1
11275  *      b.      Old_filter = 1 (instead of outer IP)
11276  *      c.      New_filter = 0x10
11277  *      d.      Buffer – 2 entries:
11278  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11279  *                      Byte 1-3 = 0 (rsv)
11280  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11281  *                      Byte 9-11 = 0 (rsv)
11282  */
11283 static int
11284 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11285 {
11286         int ret = -ENOTSUP;
11287         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11288         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11289         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11290
11291         /* Init */
11292         memset(&filter_replace, 0,
11293                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11294         memset(&filter_replace_buf, 0,
11295                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11296
11297         /* create L1 filter */
11298         filter_replace.old_filter_type =
11299                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11300         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11301         filter_replace.tr_bit = 0;
11302
11303         /* Prepare the buffer, 2 entries */
11304         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11305         filter_replace_buf.data[0] |=
11306                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11307         /* Field Vector 12b mask */
11308         filter_replace_buf.data[2] = 0xff;
11309         filter_replace_buf.data[3] = 0x0f;
11310         filter_replace_buf.data[4] =
11311                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11312         filter_replace_buf.data[4] |=
11313                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11314         /* Field Vector 12b mask */
11315         filter_replace_buf.data[6] = 0xff;
11316         filter_replace_buf.data[7] = 0x0f;
11317         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11318                         &filter_replace_buf);
11319         if (ret != I40E_SUCCESS)
11320                 return ret;
11321
11322         /* Apply the second L2 cloud filter */
11323         memset(&filter_replace, 0,
11324                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11325         memset(&filter_replace_buf, 0,
11326                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11327
11328         /* create L2 filter, input for L2 filter will be L1 filter  */
11329         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11330         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11331         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11332
11333         /* Prepare the buffer, 2 entries */
11334         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11335         filter_replace_buf.data[0] |=
11336                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11337         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11338         filter_replace_buf.data[4] |=
11339                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11340         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11341                         &filter_replace_buf);
11342         return ret;
11343 }
11344
11345 RTE_INIT(i40e_init_log);
11346 static void
11347 i40e_init_log(void)
11348 {
11349         i40e_logtype_init = rte_log_register("pmd.i40e.init");
11350         if (i40e_logtype_init >= 0)
11351                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11352         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11353         if (i40e_logtype_driver >= 0)
11354                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
11355 }