drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 112                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 116
 117 #define I40E_FLOW_TYPES ( \
 118         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 123         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 128         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 129
 130 /* Additional timesync values. */
 131 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA     0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 136 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 #define I40E_INSET_NONE            0x00000000000000000ULL
 143
 144 /* bit0 ~ bit 7 */
 145 #define I40E_INSET_DMAC            0x0000000000000001ULL
 146 #define I40E_INSET_SMAC            0x0000000000000002ULL
 147 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 148 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 149 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 150
 151 /* bit 8 ~ bit 15 */
 152 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 153 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 154 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 155 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 156 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 157 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 158 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 159
 160 /* bit 16 ~ bit 31 */
 161 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 162 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 163 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 164 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 165 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 166 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 167 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 168 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 169
 170 /* bit 32 ~ bit 47, tunnel fields */
 171 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 172 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 173 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 174 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 175 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 176 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 177
 178 /* bit 48 ~ bit 55 */
 179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 180
 181 /* bit 56 ~ bit 63, Flex Payload */
 182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD \
 191         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 192         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 193         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 194         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 195
 196 /**
 197  * Below are values for writing un-exposed registers suggested
 198  * by silicon experts
 199  */
 200 /* Destination MAC address */
 201 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 202 /* Source MAC address */
 203 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 205 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0200000000000000ULL
 206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 207 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 208 /* Single VLAN tag in the inner L2 header */
 209 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 210 /* Source IPv4 address */
 211 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 212 /* Destination IPv4 address */
 213 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 214 /* IPv4 Type of Service (TOS) */
 215 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 216 /* IPv4 Protocol */
 217 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 218 /* IPv4 Time to Live */
 219 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 220 /* Source IPv6 address */
 221 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 222 /* Destination IPv6 address */
 223 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 224 /* IPv6 Traffic Class (TC) */
 225 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 226 /* IPv6 Next Header */
 227 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 228 /* IPv6 Hop Limit */
 229 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 230 /* Source L4 port */
 231 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 232 /* Destination L4 port */
 233 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 234 /* SCTP verification tag */
 235 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 236 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 237 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 238 /* Source port of tunneling UDP */
 239 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 240 /* Destination port of tunneling UDP */
 241 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 242 /* UDP Tunneling ID, NVGRE/GRE key */
 243 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 244 /* Last ether type */
 245 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 246 /* Tunneling outer destination IPv4 address */
 247 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 248 /* Tunneling outer destination IPv6 address */
 249 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 250 /* 1st word of flex payload */
 251 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 252 /* 2nd word of flex payload */
 253 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 254 /* 3rd word of flex payload */
 255 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 256 /* 4th word of flex payload */
 257 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 258 /* 5th word of flex payload */
 259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 260 /* 6th word of flex payload */
 261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 262 /* 7th word of flex payload */
 263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 264 /* 8th word of flex payload */
 265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 266 /* all 8 words flex payload */
 267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 268 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 269
 270 #define I40E_TRANSLATE_INSET 0
 271 #define I40E_TRANSLATE_REG   1
 272
 273 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 274 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 275 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 276 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 277 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 278 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 279
 280 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 281 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 282 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 283         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 284
 285 /* PCI offset for querying capability */
 286 #define PCI_DEV_CAP_REG            0xA4
 287 /* PCI offset for enabling/disabling Extended Tag */
 288 #define PCI_DEV_CTRL_REG           0xA8
 289 /* Bit mask of Extended Tag capability */
 290 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 291 /* Bit shift of Extended Tag enable/disable */
 292 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 293 /* Bit mask of Extended Tag enable/disable */
 294 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 295
 296 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 297 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 298 static int i40e_dev_configure(struct rte_eth_dev *dev);
 299 static int i40e_dev_start(struct rte_eth_dev *dev);
 300 static void i40e_dev_stop(struct rte_eth_dev *dev);
 301 static void i40e_dev_close(struct rte_eth_dev *dev);
 302 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 303 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 304 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 305 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 306 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 307 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 308 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 309                                struct rte_eth_stats *stats);
 310 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 311                                struct rte_eth_xstat *xstats, unsigned n);
 312 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 313                                      struct rte_eth_xstat_name *xstats_names,
 314                                      unsigned limit);
 315 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 316 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 317                                             uint16_t queue_id,
 318                                             uint8_t stat_idx,
 319                                             uint8_t is_rx);
 320 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 321                               struct rte_eth_dev_info *dev_info);
 322 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 323                                 uint16_t vlan_id,
 324                                 int on);
 325 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 326                               enum rte_vlan_type vlan_type,
 327                               uint16_t tpid);
 328 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 329 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 330                                       uint16_t queue,
 331                                       int on);
 332 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 333 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 334 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 335 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 336                               struct rte_eth_fc_conf *fc_conf);
 337 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 338                               struct rte_eth_fc_conf *fc_conf);
 339 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 340                                        struct rte_eth_pfc_conf *pfc_conf);
 341 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 342                           struct ether_addr *mac_addr,
 343                           uint32_t index,
 344                           uint32_t pool);
 345 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 346 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 347                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 348                                     uint16_t reta_size);
 349 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 350                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 351                                    uint16_t reta_size);
 352
 353 static int i40e_get_cap(struct i40e_hw *hw);
 354 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 355 static int i40e_pf_setup(struct i40e_pf *pf);
 356 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 357 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 358 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 359 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 360 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 361                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 362 static void i40e_stat_update_48(struct i40e_hw *hw,
 363                                uint32_t hireg,
 364                                uint32_t loreg,
 365                                bool offset_loaded,
 366                                uint64_t *offset,
 367                                uint64_t *stat);
 368 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 369 static void i40e_dev_interrupt_handler(
 370                 __rte_unused struct rte_intr_handle *handle, void *param);
 371 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 372                                 uint32_t base, uint32_t num);
 373 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 374 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 375                         uint32_t base);
 376 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 377                         uint16_t num);
 378 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 379 static int i40e_veb_release(struct i40e_veb *veb);
 380 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 381                                                 struct i40e_vsi *vsi);
 382 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 383 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 384 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 385                                              struct i40e_macvlan_filter *mv_f,
 386                                              int num,
 387                                              struct ether_addr *addr);
 388 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 389                                              struct i40e_macvlan_filter *mv_f,
 390                                              int num,
 391                                              uint16_t vlan);
 392 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 393 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 394                                     struct rte_eth_rss_conf *rss_conf);
 395 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 396                                       struct rte_eth_rss_conf *rss_conf);
 397 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 398                                         struct rte_eth_udp_tunnel *udp_tunnel);
 399 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 400                                         struct rte_eth_udp_tunnel *udp_tunnel);
 401 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 402 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 403                         struct rte_eth_ethertype_filter *filter,
 404                         bool add);
 405 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 406                                 enum rte_filter_op filter_op,
 407                                 void *arg);
 408 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 409                                 enum rte_filter_type filter_type,
 410                                 enum rte_filter_op filter_op,
 411                                 void *arg);
 412 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 413                                   struct rte_eth_dcb_info *dcb_info);
 414 static void i40e_configure_registers(struct i40e_hw *hw);
 415 static void i40e_hw_init(struct rte_eth_dev *dev);
 416 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 417 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 418                         struct rte_eth_mirror_conf *mirror_conf,
 419                         uint8_t sw_id, uint8_t on);
 420 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 421
 422 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 423 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 424 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 425                                            struct timespec *timestamp,
 426                                            uint32_t flags);
 427 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 428                                            struct timespec *timestamp);
 429 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 430
 431 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 432
 433 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 434                                    struct timespec *timestamp);
 435 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 436                                     const struct timespec *timestamp);
 437
 438 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 439                                          uint16_t queue_id);
 440 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 441                                           uint16_t queue_id);
 442
 443 static int i40e_get_regs(struct rte_eth_dev *dev,
 444                          struct rte_dev_reg_info *regs);
 445
 446 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 447
 448 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 449                            struct rte_dev_eeprom_info *eeprom);
 450
 451 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 452                                       struct ether_addr *mac_addr);
 453
 454 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 455
 456 static const struct rte_pci_id pci_id_i40e_map[] = {
 457         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 458         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 459         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 460         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 461         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 462         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 463         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 464         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 465         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 466         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 467         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 468         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 469         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 470         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 471         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_I_X722) },
 478         { .vendor_id = 0, /* sentinel */ },
 479 };
 480
 481 static const struct eth_dev_ops i40e_eth_dev_ops = {
 482         .dev_configure                = i40e_dev_configure,
 483         .dev_start                    = i40e_dev_start,
 484         .dev_stop                     = i40e_dev_stop,
 485         .dev_close                    = i40e_dev_close,
 486         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 487         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 488         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 489         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 490         .dev_set_link_up              = i40e_dev_set_link_up,
 491         .dev_set_link_down            = i40e_dev_set_link_down,
 492         .link_update                  = i40e_dev_link_update,
 493         .stats_get                    = i40e_dev_stats_get,
 494         .xstats_get                   = i40e_dev_xstats_get,
 495         .xstats_get_names             = i40e_dev_xstats_get_names,
 496         .stats_reset                  = i40e_dev_stats_reset,
 497         .xstats_reset                 = i40e_dev_stats_reset,
 498         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 499         .dev_infos_get                = i40e_dev_info_get,
 500         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 501         .vlan_filter_set              = i40e_vlan_filter_set,
 502         .vlan_tpid_set                = i40e_vlan_tpid_set,
 503         .vlan_offload_set             = i40e_vlan_offload_set,
 504         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 505         .vlan_pvid_set                = i40e_vlan_pvid_set,
 506         .rx_queue_start               = i40e_dev_rx_queue_start,
 507         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 508         .tx_queue_start               = i40e_dev_tx_queue_start,
 509         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 510         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 511         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 512         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 513         .rx_queue_release             = i40e_dev_rx_queue_release,
 514         .rx_queue_count               = i40e_dev_rx_queue_count,
 515         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 516         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 517         .tx_queue_release             = i40e_dev_tx_queue_release,
 518         .dev_led_on                   = i40e_dev_led_on,
 519         .dev_led_off                  = i40e_dev_led_off,
 520         .flow_ctrl_get                = i40e_flow_ctrl_get,
 521         .flow_ctrl_set                = i40e_flow_ctrl_set,
 522         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 523         .mac_addr_add                 = i40e_macaddr_add,
 524         .mac_addr_remove              = i40e_macaddr_remove,
 525         .reta_update                  = i40e_dev_rss_reta_update,
 526         .reta_query                   = i40e_dev_rss_reta_query,
 527         .rss_hash_update              = i40e_dev_rss_hash_update,
 528         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 529         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 530         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 531         .filter_ctrl                  = i40e_dev_filter_ctrl,
 532         .rxq_info_get                 = i40e_rxq_info_get,
 533         .txq_info_get                 = i40e_txq_info_get,
 534         .mirror_rule_set              = i40e_mirror_rule_set,
 535         .mirror_rule_reset            = i40e_mirror_rule_reset,
 536         .timesync_enable              = i40e_timesync_enable,
 537         .timesync_disable             = i40e_timesync_disable,
 538         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 539         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 540         .get_dcb_info                 = i40e_dev_get_dcb_info,
 541         .timesync_adjust_time         = i40e_timesync_adjust_time,
 542         .timesync_read_time           = i40e_timesync_read_time,
 543         .timesync_write_time          = i40e_timesync_write_time,
 544         .get_reg                      = i40e_get_regs,
 545         .get_eeprom_length            = i40e_get_eeprom_length,
 546         .get_eeprom                   = i40e_get_eeprom,
 547         .mac_addr_set                 = i40e_set_default_mac_addr,
 548         .mtu_set                      = i40e_dev_mtu_set,
 549 };
 550
 551 /* store statistics names and its offset in stats structure */
 552 struct rte_i40e_xstats_name_off {
 553         char name[RTE_ETH_XSTATS_NAME_SIZE];
 554         unsigned offset;
 555 };
 556
 557 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 558         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 559         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 560         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 561         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 562         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 563                 rx_unknown_protocol)},
 564         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 565         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 566         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 567         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 568 };
 569
 570 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 571                 sizeof(rte_i40e_stats_strings[0]))
 572
 573 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 574         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 575                 tx_dropped_link_down)},
 576         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 577         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 578                 illegal_bytes)},
 579         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 580         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 581                 mac_local_faults)},
 582         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 583                 mac_remote_faults)},
 584         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 585                 rx_length_errors)},
 586         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 587         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 588         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 589         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 590         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 591         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 592                 rx_size_127)},
 593         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 594                 rx_size_255)},
 595         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 596                 rx_size_511)},
 597         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 598                 rx_size_1023)},
 599         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 600                 rx_size_1522)},
 601         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 602                 rx_size_big)},
 603         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 604                 rx_undersize)},
 605         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 606                 rx_oversize)},
 607         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 608                 mac_short_packet_dropped)},
 609         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 610                 rx_fragments)},
 611         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 612         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 613         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 614                 tx_size_127)},
 615         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 616                 tx_size_255)},
 617         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 618                 tx_size_511)},
 619         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 620                 tx_size_1023)},
 621         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 622                 tx_size_1522)},
 623         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 624                 tx_size_big)},
 625         {"rx_flow_director_atr_match_packets",
 626                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 627         {"rx_flow_director_sb_match_packets",
 628                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 629         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 630                 tx_lpi_status)},
 631         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 632                 rx_lpi_status)},
 633         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 634                 tx_lpi_count)},
 635         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 636                 rx_lpi_count)},
 637 };
 638
 639 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 640                 sizeof(rte_i40e_hw_port_strings[0]))
 641
 642 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 643         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 644                 priority_xon_rx)},
 645         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 646                 priority_xoff_rx)},
 647 };
 648
 649 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 650                 sizeof(rte_i40e_rxq_prio_strings[0]))
 651
 652 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 653         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 654                 priority_xon_tx)},
 655         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 656                 priority_xoff_tx)},
 657         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 658                 priority_xon_2_xoff)},
 659 };
 660
 661 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 662                 sizeof(rte_i40e_txq_prio_strings[0]))
 663
 664 static struct eth_driver rte_i40e_pmd = {
 665         .pci_drv = {
 666                 .id_table = pci_id_i40e_map,
 667                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 668                         RTE_PCI_DRV_DETACHABLE,
 669                 .probe = rte_eth_dev_pci_probe,
 670                 .remove = rte_eth_dev_pci_remove,
 671         },
 672         .eth_dev_init = eth_i40e_dev_init,
 673         .eth_dev_uninit = eth_i40e_dev_uninit,
 674         .dev_private_size = sizeof(struct i40e_adapter),
 675 };
 676
 677 static inline int
 678 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 679                                      struct rte_eth_link *link)
 680 {
 681         struct rte_eth_link *dst = link;
 682         struct rte_eth_link *src = &(dev->data->dev_link);
 683
 684         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 685                                         *(uint64_t *)src) == 0)
 686                 return -1;
 687
 688         return 0;
 689 }
 690
 691 static inline int
 692 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 693                                       struct rte_eth_link *link)
 694 {
 695         struct rte_eth_link *dst = &(dev->data->dev_link);
 696         struct rte_eth_link *src = link;
 697
 698         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 699                                         *(uint64_t *)src) == 0)
 700                 return -1;
 701
 702         return 0;
 703 }
 704
 705 DRIVER_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 706 DRIVER_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 707
 708 /*
 709  * Initialize registers for flexible payload, which should be set by NVM.
 710  * This should be removed from code once it is fixed in NVM.
 711  */
 712 #ifndef I40E_GLQF_ORT
 713 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 714 #endif
 715 #ifndef I40E_GLQF_PIT
 716 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 717 #endif
 718
 719 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 720 {
 721         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 722         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 723         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 724         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 725         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 726         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 727         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 728         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 729         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 730         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 731
 732         /* GLQF_PIT Registers */
 733         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 734         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 735 }
 736
 737 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 738
 739 /*
 740  * Add a ethertype filter to drop all flow control frames transmitted
 741  * from VSIs.
 742 */
 743 static void
 744 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 745 {
 746         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 747         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 748                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 749                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 750         int ret;
 751
 752         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 753                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 754                                 pf->main_vsi_seid, 0,
 755                                 TRUE, NULL, NULL);
 756         if (ret)
 757                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 758                                   " frames from VSIs.");
 759 }
 760
 761 static int
 762 floating_veb_list_handler(__rte_unused const char *key,
 763                           const char *floating_veb_value,
 764                           void *opaque)
 765 {
 766         int idx = 0;
 767         unsigned int count = 0;
 768         char *end = NULL;
 769         int min, max;
 770         bool *vf_floating_veb = opaque;
 771
 772         while (isblank(*floating_veb_value))
 773                 floating_veb_value++;
 774
 775         /* Reset floating VEB configuration for VFs */
 776         for (idx = 0; idx < I40E_MAX_VF; idx++)
 777                 vf_floating_veb[idx] = false;
 778
 779         min = I40E_MAX_VF;
 780         do {
 781                 while (isblank(*floating_veb_value))
 782                         floating_veb_value++;
 783                 if (*floating_veb_value == '\0')
 784                         return -1;
 785                 errno = 0;
 786                 idx = strtoul(floating_veb_value, &end, 10);
 787                 if (errno || end == NULL)
 788                         return -1;
 789                 while (isblank(*end))
 790                         end++;
 791                 if (*end == '-') {
 792                         min = idx;
 793                 } else if ((*end == ';') || (*end == '\0')) {
 794                         max = idx;
 795                         if (min == I40E_MAX_VF)
 796                                 min = idx;
 797                         if (max >= I40E_MAX_VF)
 798                                 max = I40E_MAX_VF - 1;
 799                         for (idx = min; idx <= max; idx++) {
 800                                 vf_floating_veb[idx] = true;
 801                                 count++;
 802                         }
 803                         min = I40E_MAX_VF;
 804                 } else {
 805                         return -1;
 806                 }
 807                 floating_veb_value = end + 1;
 808         } while (*end != '\0');
 809
 810         if (count == 0)
 811                 return -1;
 812
 813         return 0;
 814 }
 815
 816 static void
 817 config_vf_floating_veb(struct rte_devargs *devargs,
 818                        uint16_t floating_veb,
 819                        bool *vf_floating_veb)
 820 {
 821         struct rte_kvargs *kvlist;
 822         int i;
 823         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 824
 825         if (!floating_veb)
 826                 return;
 827         /* All the VFs attach to the floating VEB by default
 828          * when the floating VEB is enabled.
 829          */
 830         for (i = 0; i < I40E_MAX_VF; i++)
 831                 vf_floating_veb[i] = true;
 832
 833         if (devargs == NULL)
 834                 return;
 835
 836         kvlist = rte_kvargs_parse(devargs->args, NULL);
 837         if (kvlist == NULL)
 838                 return;
 839
 840         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 841                 rte_kvargs_free(kvlist);
 842                 return;
 843         }
 844         /* When the floating_veb_list parameter exists, all the VFs
 845          * will attach to the legacy VEB firstly, then configure VFs
 846          * to the floating VEB according to the floating_veb_list.
 847          */
 848         if (rte_kvargs_process(kvlist, floating_veb_list,
 849                                floating_veb_list_handler,
 850                                vf_floating_veb) < 0) {
 851                 rte_kvargs_free(kvlist);
 852                 return;
 853         }
 854         rte_kvargs_free(kvlist);
 855 }
 856
 857 static int
 858 i40e_check_floating_handler(__rte_unused const char *key,
 859                             const char *value,
 860                             __rte_unused void *opaque)
 861 {
 862         if (strcmp(value, "1"))
 863                 return -1;
 864
 865         return 0;
 866 }
 867
 868 static int
 869 is_floating_veb_supported(struct rte_devargs *devargs)
 870 {
 871         struct rte_kvargs *kvlist;
 872         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 873
 874         if (devargs == NULL)
 875                 return 0;
 876
 877         kvlist = rte_kvargs_parse(devargs->args, NULL);
 878         if (kvlist == NULL)
 879                 return 0;
 880
 881         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 882                 rte_kvargs_free(kvlist);
 883                 return 0;
 884         }
 885         /* Floating VEB is enabled when there's key-value:
 886          * enable_floating_veb=1
 887          */
 888         if (rte_kvargs_process(kvlist, floating_veb_key,
 889                                i40e_check_floating_handler, NULL) < 0) {
 890                 rte_kvargs_free(kvlist);
 891                 return 0;
 892         }
 893         rte_kvargs_free(kvlist);
 894
 895         return 1;
 896 }
 897
 898 static void
 899 config_floating_veb(struct rte_eth_dev *dev)
 900 {
 901         struct rte_pci_device *pci_dev = dev->pci_dev;
 902         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 903         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 904
 905         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 906
 907         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 908                 pf->floating_veb = is_floating_veb_supported(pci_dev->devargs);
 909                 config_vf_floating_veb(pci_dev->devargs, pf->floating_veb,
 910                                        pf->floating_veb_list);
 911         } else {
 912                 pf->floating_veb = false;
 913         }
 914 }
 915
 916 static int
 917 eth_i40e_dev_init(struct rte_eth_dev *dev)
 918 {
 919         struct rte_pci_device *pci_dev;
 920         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 921         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 922         struct i40e_vsi *vsi;
 923         int ret;
 924         uint32_t len;
 925         uint8_t aq_fail = 0;
 926
 927         PMD_INIT_FUNC_TRACE();
 928
 929         dev->dev_ops = &i40e_eth_dev_ops;
 930         dev->rx_pkt_burst = i40e_recv_pkts;
 931         dev->tx_pkt_burst = i40e_xmit_pkts;
 932
 933         /* for secondary processes, we don't initialise any further as primary
 934          * has already done this work. Only check we don't need a different
 935          * RX function */
 936         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 937                 i40e_set_rx_function(dev);
 938                 i40e_set_tx_function(dev);
 939                 return 0;
 940         }
 941         pci_dev = dev->pci_dev;
 942
 943         rte_eth_copy_pci_info(dev, pci_dev);
 944
 945         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 946         pf->adapter->eth_dev = dev;
 947         pf->dev_data = dev->data;
 948
 949         hw->back = I40E_PF_TO_ADAPTER(pf);
 950         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 951         if (!hw->hw_addr) {
 952                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 953                              "as address is NULL");
 954                 return -ENODEV;
 955         }
 956
 957         hw->vendor_id = pci_dev->id.vendor_id;
 958         hw->device_id = pci_dev->id.device_id;
 959         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 960         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 961         hw->bus.device = pci_dev->addr.devid;
 962         hw->bus.func = pci_dev->addr.function;
 963         hw->adapter_stopped = 0;
 964
 965         /* Make sure all is clean before doing PF reset */
 966         i40e_clear_hw(hw);
 967
 968         /* Initialize the hardware */
 969         i40e_hw_init(dev);
 970
 971         /* Reset here to make sure all is clean for each PF */
 972         ret = i40e_pf_reset(hw);
 973         if (ret) {
 974                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 975                 return ret;
 976         }
 977
 978         /* Initialize the shared code (base driver) */
 979         ret = i40e_init_shared_code(hw);
 980         if (ret) {
 981                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 982                 return ret;
 983         }
 984
 985         /*
 986          * To work around the NVM issue,initialize registers
 987          * for flexible payload by software.
 988          * It should be removed once issues are fixed in NVM.
 989          */
 990         i40e_flex_payload_reg_init(hw);
 991
 992         /* Initialize the input set for filters (hash and fd) to default value */
 993         i40e_filter_input_set_init(pf);
 994
 995         /* Initialize the parameters for adminq */
 996         i40e_init_adminq_parameter(hw);
 997         ret = i40e_init_adminq(hw);
 998         if (ret != I40E_SUCCESS) {
 999                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1000                 return -EIO;
1001         }
1002         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1003                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1004                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1005                      ((hw->nvm.version >> 12) & 0xf),
1006                      ((hw->nvm.version >> 4) & 0xff),
1007                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1008
1009         /* Need the special FW version to support floating VEB */
1010         config_floating_veb(dev);
1011         /* Clear PXE mode */
1012         i40e_clear_pxe_mode(hw);
1013
1014         /*
1015          * On X710, performance number is far from the expectation on recent
1016          * firmware versions. The fix for this issue may not be integrated in
1017          * the following firmware version. So the workaround in software driver
1018          * is needed. It needs to modify the initial values of 3 internal only
1019          * registers. Note that the workaround can be removed when it is fixed
1020          * in firmware in the future.
1021          */
1022         i40e_configure_registers(hw);
1023
1024         /* Get hw capabilities */
1025         ret = i40e_get_cap(hw);
1026         if (ret != I40E_SUCCESS) {
1027                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1028                 goto err_get_capabilities;
1029         }
1030
1031         /* Initialize parameters for PF */
1032         ret = i40e_pf_parameter_init(dev);
1033         if (ret != 0) {
1034                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1035                 goto err_parameter_init;
1036         }
1037
1038         /* Initialize the queue management */
1039         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1040         if (ret < 0) {
1041                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1042                 goto err_qp_pool_init;
1043         }
1044         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1045                                 hw->func_caps.num_msix_vectors - 1);
1046         if (ret < 0) {
1047                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1048                 goto err_msix_pool_init;
1049         }
1050
1051         /* Initialize lan hmc */
1052         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1053                                 hw->func_caps.num_rx_qp, 0, 0);
1054         if (ret != I40E_SUCCESS) {
1055                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1056                 goto err_init_lan_hmc;
1057         }
1058
1059         /* Configure lan hmc */
1060         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1061         if (ret != I40E_SUCCESS) {
1062                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1063                 goto err_configure_lan_hmc;
1064         }
1065
1066         /* Get and check the mac address */
1067         i40e_get_mac_addr(hw, hw->mac.addr);
1068         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1069                 PMD_INIT_LOG(ERR, "mac address is not valid");
1070                 ret = -EIO;
1071                 goto err_get_mac_addr;
1072         }
1073         /* Copy the permanent MAC address */
1074         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1075                         (struct ether_addr *) hw->mac.perm_addr);
1076
1077         /* Disable flow control */
1078         hw->fc.requested_mode = I40E_FC_NONE;
1079         i40e_set_fc(hw, &aq_fail, TRUE);
1080
1081         /* Set the global registers with default ether type value */
1082         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1083         if (ret != I40E_SUCCESS) {
1084                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1085                              "VLAN ether type");
1086                 goto err_setup_pf_switch;
1087         }
1088
1089         /* PF setup, which includes VSI setup */
1090         ret = i40e_pf_setup(pf);
1091         if (ret) {
1092                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1093                 goto err_setup_pf_switch;
1094         }
1095
1096         /* reset all stats of the device, including pf and main vsi */
1097         i40e_dev_stats_reset(dev);
1098
1099         vsi = pf->main_vsi;
1100
1101         /* Disable double vlan by default */
1102         i40e_vsi_config_double_vlan(vsi, FALSE);
1103
1104         if (!vsi->max_macaddrs)
1105                 len = ETHER_ADDR_LEN;
1106         else
1107                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1108
1109         /* Should be after VSI initialized */
1110         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1111         if (!dev->data->mac_addrs) {
1112                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1113                                         "for storing mac address");
1114                 goto err_mac_alloc;
1115         }
1116         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1117                                         &dev->data->mac_addrs[0]);
1118
1119         /* initialize pf host driver to setup SRIOV resource if applicable */
1120         i40e_pf_host_init(dev);
1121
1122         /* register callback func to eal lib */
1123         rte_intr_callback_register(&(pci_dev->intr_handle),
1124                 i40e_dev_interrupt_handler, (void *)dev);
1125
1126         /* configure and enable device interrupt */
1127         i40e_pf_config_irq0(hw, TRUE);
1128         i40e_pf_enable_irq0(hw);
1129
1130         /* enable uio intr after callback register */
1131         rte_intr_enable(&(pci_dev->intr_handle));
1132         /*
1133          * Add an ethertype filter to drop all flow control frames transmitted
1134          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1135          * frames to wire.
1136          */
1137         i40e_add_tx_flow_control_drop_filter(pf);
1138
1139         /* Set the max frame size to 0x2600 by default,
1140          * in case other drivers changed the default value.
1141          */
1142         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1143
1144         /* initialize mirror rule list */
1145         TAILQ_INIT(&pf->mirror_list);
1146
1147         /* Init dcb to sw mode by default */
1148         ret = i40e_dcb_init_configure(dev, TRUE);
1149         if (ret != I40E_SUCCESS) {
1150                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1151                 pf->flags &= ~I40E_FLAG_DCB;
1152         }
1153
1154         return 0;
1155
1156 err_mac_alloc:
1157         i40e_vsi_release(pf->main_vsi);
1158 err_setup_pf_switch:
1159 err_get_mac_addr:
1160 err_configure_lan_hmc:
1161         (void)i40e_shutdown_lan_hmc(hw);
1162 err_init_lan_hmc:
1163         i40e_res_pool_destroy(&pf->msix_pool);
1164 err_msix_pool_init:
1165         i40e_res_pool_destroy(&pf->qp_pool);
1166 err_qp_pool_init:
1167 err_parameter_init:
1168 err_get_capabilities:
1169         (void)i40e_shutdown_adminq(hw);
1170
1171         return ret;
1172 }
1173
1174 static int
1175 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1176 {
1177         struct rte_pci_device *pci_dev;
1178         struct i40e_hw *hw;
1179         struct i40e_filter_control_settings settings;
1180         int ret;
1181         uint8_t aq_fail = 0;
1182
1183         PMD_INIT_FUNC_TRACE();
1184
1185         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1186                 return 0;
1187
1188         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1189         pci_dev = dev->pci_dev;
1190
1191         if (hw->adapter_stopped == 0)
1192                 i40e_dev_close(dev);
1193
1194         dev->dev_ops = NULL;
1195         dev->rx_pkt_burst = NULL;
1196         dev->tx_pkt_burst = NULL;
1197
1198         /* Disable LLDP */
1199         ret = i40e_aq_stop_lldp(hw, true, NULL);
1200         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1201                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1202
1203         /* Clear PXE mode */
1204         i40e_clear_pxe_mode(hw);
1205
1206         /* Unconfigure filter control */
1207         memset(&settings, 0, sizeof(settings));
1208         ret = i40e_set_filter_control(hw, &settings);
1209         if (ret)
1210                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1211                                         ret);
1212
1213         /* Disable flow control */
1214         hw->fc.requested_mode = I40E_FC_NONE;
1215         i40e_set_fc(hw, &aq_fail, TRUE);
1216
1217         /* uninitialize pf host driver */
1218         i40e_pf_host_uninit(dev);
1219
1220         rte_free(dev->data->mac_addrs);
1221         dev->data->mac_addrs = NULL;
1222
1223         /* disable uio intr before callback unregister */
1224         rte_intr_disable(&(pci_dev->intr_handle));
1225
1226         /* register callback func to eal lib */
1227         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1228                 i40e_dev_interrupt_handler, (void *)dev);
1229
1230         return 0;
1231 }
1232
1233 static int
1234 i40e_dev_configure(struct rte_eth_dev *dev)
1235 {
1236         struct i40e_adapter *ad =
1237                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1238         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1239         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1240         int i, ret;
1241
1242         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1243          * bulk allocation or vector Rx preconditions we will reset it.
1244          */
1245         ad->rx_bulk_alloc_allowed = true;
1246         ad->rx_vec_allowed = true;
1247         ad->tx_simple_allowed = true;
1248         ad->tx_vec_allowed = true;
1249
1250         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1251                 ret = i40e_fdir_setup(pf);
1252                 if (ret != I40E_SUCCESS) {
1253                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1254                         return -ENOTSUP;
1255                 }
1256                 ret = i40e_fdir_configure(dev);
1257                 if (ret < 0) {
1258                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1259                         goto err;
1260                 }
1261         } else
1262                 i40e_fdir_teardown(pf);
1263
1264         ret = i40e_dev_init_vlan(dev);
1265         if (ret < 0)
1266                 goto err;
1267
1268         /* VMDQ setup.
1269          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1270          *  RSS setting have different requirements.
1271          *  General PMD driver call sequence are NIC init, configure,
1272          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1273          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1274          *  applicable. So, VMDQ setting has to be done before
1275          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1276          *  For RSS setting, it will try to calculate actual configured RX queue
1277          *  number, which will be available after rx_queue_setup(). dev_start()
1278          *  function is good to place RSS setup.
1279          */
1280         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1281                 ret = i40e_vmdq_setup(dev);
1282                 if (ret)
1283                         goto err;
1284         }
1285
1286         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1287                 ret = i40e_dcb_setup(dev);
1288                 if (ret) {
1289                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1290                         goto err_dcb;
1291                 }
1292         }
1293
1294         return 0;
1295
1296 err_dcb:
1297         /* need to release vmdq resource if exists */
1298         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1299                 i40e_vsi_release(pf->vmdq[i].vsi);
1300                 pf->vmdq[i].vsi = NULL;
1301         }
1302         rte_free(pf->vmdq);
1303         pf->vmdq = NULL;
1304 err:
1305         /* need to release fdir resource if exists */
1306         i40e_fdir_teardown(pf);
1307         return ret;
1308 }
1309
1310 void
1311 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1312 {
1313         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1314         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1315         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1316         uint16_t msix_vect = vsi->msix_intr;
1317         uint16_t i;
1318
1319         for (i = 0; i < vsi->nb_qps; i++) {
1320                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1321                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1322                 rte_wmb();
1323         }
1324
1325         if (vsi->type != I40E_VSI_SRIOV) {
1326                 if (!rte_intr_allow_others(intr_handle)) {
1327                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1328                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1329                         I40E_WRITE_REG(hw,
1330                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1331                                        0);
1332                 } else {
1333                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1334                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1335                         I40E_WRITE_REG(hw,
1336                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1337                                                        msix_vect - 1), 0);
1338                 }
1339         } else {
1340                 uint32_t reg;
1341                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1342                         vsi->user_param + (msix_vect - 1);
1343
1344                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1345                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1346         }
1347         I40E_WRITE_FLUSH(hw);
1348 }
1349
1350 static void
1351 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1352                        int base_queue, int nb_queue)
1353 {
1354         int i;
1355         uint32_t val;
1356         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1357
1358         /* Bind all RX queues to allocated MSIX interrupt */
1359         for (i = 0; i < nb_queue; i++) {
1360                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1361                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1362                         ((base_queue + i + 1) <<
1363                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1364                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1365                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1366
1367                 if (i == nb_queue - 1)
1368                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1369                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1370         }
1371
1372         /* Write first RX queue to Link list register as the head element */
1373         if (vsi->type != I40E_VSI_SRIOV) {
1374                 uint16_t interval =
1375                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1376
1377                 if (msix_vect == I40E_MISC_VEC_ID) {
1378                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1379                                        (base_queue <<
1380                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1381                                        (0x0 <<
1382                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1383                         I40E_WRITE_REG(hw,
1384                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1385                                        interval);
1386                 } else {
1387                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1388                                        (base_queue <<
1389                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1390                                        (0x0 <<
1391                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1392                         I40E_WRITE_REG(hw,
1393                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1394                                                        msix_vect - 1),
1395                                        interval);
1396                 }
1397         } else {
1398                 uint32_t reg;
1399
1400                 if (msix_vect == I40E_MISC_VEC_ID) {
1401                         I40E_WRITE_REG(hw,
1402                                        I40E_VPINT_LNKLST0(vsi->user_param),
1403                                        (base_queue <<
1404                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1405                                        (0x0 <<
1406                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1407                 } else {
1408                         /* num_msix_vectors_vf needs to minus irq0 */
1409                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1410                                 vsi->user_param + (msix_vect - 1);
1411
1412                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1413                                        (base_queue <<
1414                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1415                                        (0x0 <<
1416                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1417                 }
1418         }
1419
1420         I40E_WRITE_FLUSH(hw);
1421 }
1422
1423 void
1424 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1425 {
1426         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1427         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1428         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1429         uint16_t msix_vect = vsi->msix_intr;
1430         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1431         uint16_t queue_idx = 0;
1432         int record = 0;
1433         uint32_t val;
1434         int i;
1435
1436         for (i = 0; i < vsi->nb_qps; i++) {
1437                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1438                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1439         }
1440
1441         /* INTENA flag is not auto-cleared for interrupt */
1442         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1443         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1444                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1445                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1446         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1447
1448         /* VF bind interrupt */
1449         if (vsi->type == I40E_VSI_SRIOV) {
1450                 __vsi_queues_bind_intr(vsi, msix_vect,
1451                                        vsi->base_queue, vsi->nb_qps);
1452                 return;
1453         }
1454
1455         /* PF & VMDq bind interrupt */
1456         if (rte_intr_dp_is_en(intr_handle)) {
1457                 if (vsi->type == I40E_VSI_MAIN) {
1458                         queue_idx = 0;
1459                         record = 1;
1460                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1461                         struct i40e_vsi *main_vsi =
1462                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1463                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1464                         record = 1;
1465                 }
1466         }
1467
1468         for (i = 0; i < vsi->nb_used_qps; i++) {
1469                 if (nb_msix <= 1) {
1470                         if (!rte_intr_allow_others(intr_handle))
1471                                 /* allow to share MISC_VEC_ID */
1472                                 msix_vect = I40E_MISC_VEC_ID;
1473
1474                         /* no enough msix_vect, map all to one */
1475                         __vsi_queues_bind_intr(vsi, msix_vect,
1476                                                vsi->base_queue + i,
1477                                                vsi->nb_used_qps - i);
1478                         for (; !!record && i < vsi->nb_used_qps; i++)
1479                                 intr_handle->intr_vec[queue_idx + i] =
1480                                         msix_vect;
1481                         break;
1482                 }
1483                 /* 1:1 queue/msix_vect mapping */
1484                 __vsi_queues_bind_intr(vsi, msix_vect,
1485                                        vsi->base_queue + i, 1);
1486                 if (!!record)
1487                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1488
1489                 msix_vect++;
1490                 nb_msix--;
1491         }
1492 }
1493
1494 static void
1495 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1496 {
1497         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1498         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1499         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1500         uint16_t interval = i40e_calc_itr_interval(\
1501                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1502         uint16_t msix_intr, i;
1503
1504         if (rte_intr_allow_others(intr_handle))
1505                 for (i = 0; i < vsi->nb_msix; i++) {
1506                         msix_intr = vsi->msix_intr + i;
1507                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1508                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1509                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1510                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1511                                 (interval <<
1512                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1513                 }
1514         else
1515                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1516                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1517                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1518                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1519                                (interval <<
1520                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1521
1522         I40E_WRITE_FLUSH(hw);
1523 }
1524
1525 static void
1526 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1527 {
1528         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1529         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1530         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1531         uint16_t msix_intr, i;
1532
1533         if (rte_intr_allow_others(intr_handle))
1534                 for (i = 0; i < vsi->nb_msix; i++) {
1535                         msix_intr = vsi->msix_intr + i;
1536                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1537                                        0);
1538                 }
1539         else
1540                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1541
1542         I40E_WRITE_FLUSH(hw);
1543 }
1544
1545 static inline uint8_t
1546 i40e_parse_link_speeds(uint16_t link_speeds)
1547 {
1548         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1549
1550         if (link_speeds & ETH_LINK_SPEED_40G)
1551                 link_speed |= I40E_LINK_SPEED_40GB;
1552         if (link_speeds & ETH_LINK_SPEED_20G)
1553                 link_speed |= I40E_LINK_SPEED_20GB;
1554         if (link_speeds & ETH_LINK_SPEED_10G)
1555                 link_speed |= I40E_LINK_SPEED_10GB;
1556         if (link_speeds & ETH_LINK_SPEED_1G)
1557                 link_speed |= I40E_LINK_SPEED_1GB;
1558         if (link_speeds & ETH_LINK_SPEED_100M)
1559                 link_speed |= I40E_LINK_SPEED_100MB;
1560
1561         return link_speed;
1562 }
1563
1564 static int
1565 i40e_phy_conf_link(struct i40e_hw *hw,
1566                    uint8_t abilities,
1567                    uint8_t force_speed)
1568 {
1569         enum i40e_status_code status;
1570         struct i40e_aq_get_phy_abilities_resp phy_ab;
1571         struct i40e_aq_set_phy_config phy_conf;
1572         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1573                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1574                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1575                         I40E_AQ_PHY_FLAG_LOW_POWER;
1576         const uint8_t advt = I40E_LINK_SPEED_40GB |
1577                         I40E_LINK_SPEED_10GB |
1578                         I40E_LINK_SPEED_1GB |
1579                         I40E_LINK_SPEED_100MB;
1580         int ret = -ENOTSUP;
1581
1582
1583         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1584                                               NULL);
1585         if (status)
1586                 return ret;
1587
1588         memset(&phy_conf, 0, sizeof(phy_conf));
1589
1590         /* bits 0-2 use the values from get_phy_abilities_resp */
1591         abilities &= ~mask;
1592         abilities |= phy_ab.abilities & mask;
1593
1594         /* update ablities and speed */
1595         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1596                 phy_conf.link_speed = advt;
1597         else
1598                 phy_conf.link_speed = force_speed;
1599
1600         phy_conf.abilities = abilities;
1601
1602         /* use get_phy_abilities_resp value for the rest */
1603         phy_conf.phy_type = phy_ab.phy_type;
1604         phy_conf.eee_capability = phy_ab.eee_capability;
1605         phy_conf.eeer = phy_ab.eeer_val;
1606         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1607
1608         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1609                     phy_ab.abilities, phy_ab.link_speed);
1610         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1611                     phy_conf.abilities, phy_conf.link_speed);
1612
1613         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1614         if (status)
1615                 return ret;
1616
1617         return I40E_SUCCESS;
1618 }
1619
1620 static int
1621 i40e_apply_link_speed(struct rte_eth_dev *dev)
1622 {
1623         uint8_t speed;
1624         uint8_t abilities = 0;
1625         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1626         struct rte_eth_conf *conf = &dev->data->dev_conf;
1627
1628         speed = i40e_parse_link_speeds(conf->link_speeds);
1629         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1630         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1631                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1632         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1633
1634         /* Skip changing speed on 40G interfaces, FW does not support */
1635         if (i40e_is_40G_device(hw->device_id)) {
1636                 speed =  I40E_LINK_SPEED_UNKNOWN;
1637                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1638         }
1639
1640         return i40e_phy_conf_link(hw, abilities, speed);
1641 }
1642
1643 static int
1644 i40e_dev_start(struct rte_eth_dev *dev)
1645 {
1646         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1647         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1648         struct i40e_vsi *main_vsi = pf->main_vsi;
1649         int ret, i;
1650         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1651         uint32_t intr_vector = 0;
1652
1653         hw->adapter_stopped = 0;
1654
1655         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1656                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1657                              dev->data->port_id);
1658                 return -EINVAL;
1659         }
1660
1661         rte_intr_disable(intr_handle);
1662
1663         if ((rte_intr_cap_multiple(intr_handle) ||
1664              !RTE_ETH_DEV_SRIOV(dev).active) &&
1665             dev->data->dev_conf.intr_conf.rxq != 0) {
1666                 intr_vector = dev->data->nb_rx_queues;
1667                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1668                         return -1;
1669         }
1670
1671         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1672                 intr_handle->intr_vec =
1673                         rte_zmalloc("intr_vec",
1674                                     dev->data->nb_rx_queues * sizeof(int),
1675                                     0);
1676                 if (!intr_handle->intr_vec) {
1677                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1678                                      " intr_vec\n", dev->data->nb_rx_queues);
1679                         return -ENOMEM;
1680                 }
1681         }
1682
1683         /* Initialize VSI */
1684         ret = i40e_dev_rxtx_init(pf);
1685         if (ret != I40E_SUCCESS) {
1686                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1687                 goto err_up;
1688         }
1689
1690         /* Map queues with MSIX interrupt */
1691         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1692                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1693         i40e_vsi_queues_bind_intr(main_vsi);
1694         i40e_vsi_enable_queues_intr(main_vsi);
1695
1696         /* Map VMDQ VSI queues with MSIX interrupt */
1697         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1698                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1699                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1700                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1701         }
1702
1703         /* enable FDIR MSIX interrupt */
1704         if (pf->fdir.fdir_vsi) {
1705                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1706                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1707         }
1708
1709         /* Enable all queues which have been configured */
1710         ret = i40e_dev_switch_queues(pf, TRUE);
1711         if (ret != I40E_SUCCESS) {
1712                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1713                 goto err_up;
1714         }
1715
1716         /* Enable receiving broadcast packets */
1717         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1718         if (ret != I40E_SUCCESS)
1719                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1720
1721         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1722                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1723                                                 true, NULL);
1724                 if (ret != I40E_SUCCESS)
1725                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1726         }
1727
1728         /* Apply link configure */
1729         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1730                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1731                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1732                 PMD_DRV_LOG(ERR, "Invalid link setting");
1733                 goto err_up;
1734         }
1735         ret = i40e_apply_link_speed(dev);
1736         if (I40E_SUCCESS != ret) {
1737                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1738                 goto err_up;
1739         }
1740
1741         if (!rte_intr_allow_others(intr_handle)) {
1742                 rte_intr_callback_unregister(intr_handle,
1743                                              i40e_dev_interrupt_handler,
1744                                              (void *)dev);
1745                 /* configure and enable device interrupt */
1746                 i40e_pf_config_irq0(hw, FALSE);
1747                 i40e_pf_enable_irq0(hw);
1748
1749                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1750                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1751                                      " no intr multiplex\n");
1752         }
1753
1754         /* enable uio intr after callback register */
1755         rte_intr_enable(intr_handle);
1756
1757         return I40E_SUCCESS;
1758
1759 err_up:
1760         i40e_dev_switch_queues(pf, FALSE);
1761         i40e_dev_clear_queues(dev);
1762
1763         return ret;
1764 }
1765
1766 static void
1767 i40e_dev_stop(struct rte_eth_dev *dev)
1768 {
1769         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1770         struct i40e_vsi *main_vsi = pf->main_vsi;
1771         struct i40e_mirror_rule *p_mirror;
1772         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1773         int i;
1774
1775         /* Disable all queues */
1776         i40e_dev_switch_queues(pf, FALSE);
1777
1778         /* un-map queues with interrupt registers */
1779         i40e_vsi_disable_queues_intr(main_vsi);
1780         i40e_vsi_queues_unbind_intr(main_vsi);
1781
1782         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1783                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1784                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1785         }
1786
1787         if (pf->fdir.fdir_vsi) {
1788                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1789                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1790         }
1791         /* Clear all queues and release memory */
1792         i40e_dev_clear_queues(dev);
1793
1794         /* Set link down */
1795         i40e_dev_set_link_down(dev);
1796
1797         /* Remove all mirror rules */
1798         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1799                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1800                 rte_free(p_mirror);
1801         }
1802         pf->nb_mirror_rule = 0;
1803
1804         if (!rte_intr_allow_others(intr_handle))
1805                 /* resume to the default handler */
1806                 rte_intr_callback_register(intr_handle,
1807                                            i40e_dev_interrupt_handler,
1808                                            (void *)dev);
1809
1810         /* Clean datapath event and queue/vec mapping */
1811         rte_intr_efd_disable(intr_handle);
1812         if (intr_handle->intr_vec) {
1813                 rte_free(intr_handle->intr_vec);
1814                 intr_handle->intr_vec = NULL;
1815         }
1816 }
1817
1818 static void
1819 i40e_dev_close(struct rte_eth_dev *dev)
1820 {
1821         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1822         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1823         uint32_t reg;
1824         int i;
1825
1826         PMD_INIT_FUNC_TRACE();
1827
1828         i40e_dev_stop(dev);
1829         hw->adapter_stopped = 1;
1830         i40e_dev_free_queues(dev);
1831
1832         /* Disable interrupt */
1833         i40e_pf_disable_irq0(hw);
1834         rte_intr_disable(&(dev->pci_dev->intr_handle));
1835
1836         /* shutdown and destroy the HMC */
1837         i40e_shutdown_lan_hmc(hw);
1838
1839         /* release all the existing VSIs and VEBs */
1840         i40e_fdir_teardown(pf);
1841         i40e_vsi_release(pf->main_vsi);
1842
1843         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1844                 i40e_vsi_release(pf->vmdq[i].vsi);
1845                 pf->vmdq[i].vsi = NULL;
1846         }
1847
1848         rte_free(pf->vmdq);
1849         pf->vmdq = NULL;
1850
1851         /* shutdown the adminq */
1852         i40e_aq_queue_shutdown(hw, true);
1853         i40e_shutdown_adminq(hw);
1854
1855         i40e_res_pool_destroy(&pf->qp_pool);
1856         i40e_res_pool_destroy(&pf->msix_pool);
1857
1858         /* force a PF reset to clean anything leftover */
1859         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1860         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1861                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1862         I40E_WRITE_FLUSH(hw);
1863 }
1864
1865 static void
1866 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1867 {
1868         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1869         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1870         struct i40e_vsi *vsi = pf->main_vsi;
1871         int status;
1872
1873         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1874                                                      true, NULL, true);
1875         if (status != I40E_SUCCESS)
1876                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1877
1878         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1879                                                         TRUE, NULL);
1880         if (status != I40E_SUCCESS)
1881                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1882
1883 }
1884
1885 static void
1886 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1887 {
1888         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1889         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1890         struct i40e_vsi *vsi = pf->main_vsi;
1891         int status;
1892
1893         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1894                                                      false, NULL, true);
1895         if (status != I40E_SUCCESS)
1896                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1897
1898         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1899                                                         false, NULL);
1900         if (status != I40E_SUCCESS)
1901                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1902 }
1903
1904 static void
1905 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1906 {
1907         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1908         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1909         struct i40e_vsi *vsi = pf->main_vsi;
1910         int ret;
1911
1912         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1913         if (ret != I40E_SUCCESS)
1914                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1915 }
1916
1917 static void
1918 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1919 {
1920         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1921         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         struct i40e_vsi *vsi = pf->main_vsi;
1923         int ret;
1924
1925         if (dev->data->promiscuous == 1)
1926                 return; /* must remain in all_multicast mode */
1927
1928         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1929                                 vsi->seid, FALSE, NULL);
1930         if (ret != I40E_SUCCESS)
1931                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1932 }
1933
1934 /*
1935  * Set device link up.
1936  */
1937 static int
1938 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1939 {
1940         /* re-apply link speed setting */
1941         return i40e_apply_link_speed(dev);
1942 }
1943
1944 /*
1945  * Set device link down.
1946  */
1947 static int
1948 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1949 {
1950         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1951         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1952         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1953
1954         return i40e_phy_conf_link(hw, abilities, speed);
1955 }
1956
1957 int
1958 i40e_dev_link_update(struct rte_eth_dev *dev,
1959                      int wait_to_complete)
1960 {
1961 #define CHECK_INTERVAL 100  /* 100ms */
1962 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1963         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1964         struct i40e_link_status link_status;
1965         struct rte_eth_link link, old;
1966         int status;
1967         unsigned rep_cnt = MAX_REPEAT_TIME;
1968
1969         memset(&link, 0, sizeof(link));
1970         memset(&old, 0, sizeof(old));
1971         memset(&link_status, 0, sizeof(link_status));
1972         rte_i40e_dev_atomic_read_link_status(dev, &old);
1973
1974         do {
1975                 /* Get link status information from hardware */
1976                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1977                 if (status != I40E_SUCCESS) {
1978                         link.link_speed = ETH_SPEED_NUM_100M;
1979                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1980                         PMD_DRV_LOG(ERR, "Failed to get link info");
1981                         goto out;
1982                 }
1983
1984                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1985                 if (!wait_to_complete)
1986                         break;
1987
1988                 rte_delay_ms(CHECK_INTERVAL);
1989         } while (!link.link_status && rep_cnt--);
1990
1991         if (!link.link_status)
1992                 goto out;
1993
1994         /* i40e uses full duplex only */
1995         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1996
1997         /* Parse the link status */
1998         switch (link_status.link_speed) {
1999         case I40E_LINK_SPEED_100MB:
2000                 link.link_speed = ETH_SPEED_NUM_100M;
2001                 break;
2002         case I40E_LINK_SPEED_1GB:
2003                 link.link_speed = ETH_SPEED_NUM_1G;
2004                 break;
2005         case I40E_LINK_SPEED_10GB:
2006                 link.link_speed = ETH_SPEED_NUM_10G;
2007                 break;
2008         case I40E_LINK_SPEED_20GB:
2009                 link.link_speed = ETH_SPEED_NUM_20G;
2010                 break;
2011         case I40E_LINK_SPEED_40GB:
2012                 link.link_speed = ETH_SPEED_NUM_40G;
2013                 break;
2014         default:
2015                 link.link_speed = ETH_SPEED_NUM_100M;
2016                 break;
2017         }
2018
2019         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2020                         ETH_LINK_SPEED_FIXED);
2021
2022 out:
2023         rte_i40e_dev_atomic_write_link_status(dev, &link);
2024         if (link.link_status == old.link_status)
2025                 return -1;
2026
2027         return 0;
2028 }
2029
2030 /* Get all the statistics of a VSI */
2031 void
2032 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2033 {
2034         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2035         struct i40e_eth_stats *nes = &vsi->eth_stats;
2036         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2037         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2038
2039         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2040                             vsi->offset_loaded, &oes->rx_bytes,
2041                             &nes->rx_bytes);
2042         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2043                             vsi->offset_loaded, &oes->rx_unicast,
2044                             &nes->rx_unicast);
2045         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2046                             vsi->offset_loaded, &oes->rx_multicast,
2047                             &nes->rx_multicast);
2048         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2049                             vsi->offset_loaded, &oes->rx_broadcast,
2050                             &nes->rx_broadcast);
2051         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2052                             &oes->rx_discards, &nes->rx_discards);
2053         /* GLV_REPC not supported */
2054         /* GLV_RMPC not supported */
2055         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2056                             &oes->rx_unknown_protocol,
2057                             &nes->rx_unknown_protocol);
2058         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2059                             vsi->offset_loaded, &oes->tx_bytes,
2060                             &nes->tx_bytes);
2061         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2062                             vsi->offset_loaded, &oes->tx_unicast,
2063                             &nes->tx_unicast);
2064         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2065                             vsi->offset_loaded, &oes->tx_multicast,
2066                             &nes->tx_multicast);
2067         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2068                             vsi->offset_loaded,  &oes->tx_broadcast,
2069                             &nes->tx_broadcast);
2070         /* GLV_TDPC not supported */
2071         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2072                             &oes->tx_errors, &nes->tx_errors);
2073         vsi->offset_loaded = true;
2074
2075         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2076                     vsi->vsi_id);
2077         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2078         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2079         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2080         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2081         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2082         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2083                     nes->rx_unknown_protocol);
2084         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2085         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2086         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2087         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2088         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2089         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2090         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2091                     vsi->vsi_id);
2092 }
2093
2094 static void
2095 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2096 {
2097         unsigned int i;
2098         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2099         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2100
2101         /* Get statistics of struct i40e_eth_stats */
2102         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2103                             I40E_GLPRT_GORCL(hw->port),
2104                             pf->offset_loaded, &os->eth.rx_bytes,
2105                             &ns->eth.rx_bytes);
2106         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2107                             I40E_GLPRT_UPRCL(hw->port),
2108                             pf->offset_loaded, &os->eth.rx_unicast,
2109                             &ns->eth.rx_unicast);
2110         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2111                             I40E_GLPRT_MPRCL(hw->port),
2112                             pf->offset_loaded, &os->eth.rx_multicast,
2113                             &ns->eth.rx_multicast);
2114         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2115                             I40E_GLPRT_BPRCL(hw->port),
2116                             pf->offset_loaded, &os->eth.rx_broadcast,
2117                             &ns->eth.rx_broadcast);
2118         /* Workaround: CRC size should not be included in byte statistics,
2119          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2120          */
2121         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2122                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2123
2124         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2125                             pf->offset_loaded, &os->eth.rx_discards,
2126                             &ns->eth.rx_discards);
2127         /* GLPRT_REPC not supported */
2128         /* GLPRT_RMPC not supported */
2129         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2130                             pf->offset_loaded,
2131                             &os->eth.rx_unknown_protocol,
2132                             &ns->eth.rx_unknown_protocol);
2133         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2134                             I40E_GLPRT_GOTCL(hw->port),
2135                             pf->offset_loaded, &os->eth.tx_bytes,
2136                             &ns->eth.tx_bytes);
2137         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2138                             I40E_GLPRT_UPTCL(hw->port),
2139                             pf->offset_loaded, &os->eth.tx_unicast,
2140                             &ns->eth.tx_unicast);
2141         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2142                             I40E_GLPRT_MPTCL(hw->port),
2143                             pf->offset_loaded, &os->eth.tx_multicast,
2144                             &ns->eth.tx_multicast);
2145         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2146                             I40E_GLPRT_BPTCL(hw->port),
2147                             pf->offset_loaded, &os->eth.tx_broadcast,
2148                             &ns->eth.tx_broadcast);
2149         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2150                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2151         /* GLPRT_TEPC not supported */
2152
2153         /* additional port specific stats */
2154         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2155                             pf->offset_loaded, &os->tx_dropped_link_down,
2156                             &ns->tx_dropped_link_down);
2157         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2158                             pf->offset_loaded, &os->crc_errors,
2159                             &ns->crc_errors);
2160         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2161                             pf->offset_loaded, &os->illegal_bytes,
2162                             &ns->illegal_bytes);
2163         /* GLPRT_ERRBC not supported */
2164         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2165                             pf->offset_loaded, &os->mac_local_faults,
2166                             &ns->mac_local_faults);
2167         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2168                             pf->offset_loaded, &os->mac_remote_faults,
2169                             &ns->mac_remote_faults);
2170         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2171                             pf->offset_loaded, &os->rx_length_errors,
2172                             &ns->rx_length_errors);
2173         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2174                             pf->offset_loaded, &os->link_xon_rx,
2175                             &ns->link_xon_rx);
2176         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2177                             pf->offset_loaded, &os->link_xoff_rx,
2178                             &ns->link_xoff_rx);
2179         for (i = 0; i < 8; i++) {
2180                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2181                                     pf->offset_loaded,
2182                                     &os->priority_xon_rx[i],
2183                                     &ns->priority_xon_rx[i]);
2184                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2185                                     pf->offset_loaded,
2186                                     &os->priority_xoff_rx[i],
2187                                     &ns->priority_xoff_rx[i]);
2188         }
2189         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2190                             pf->offset_loaded, &os->link_xon_tx,
2191                             &ns->link_xon_tx);
2192         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2193                             pf->offset_loaded, &os->link_xoff_tx,
2194                             &ns->link_xoff_tx);
2195         for (i = 0; i < 8; i++) {
2196                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2197                                     pf->offset_loaded,
2198                                     &os->priority_xon_tx[i],
2199                                     &ns->priority_xon_tx[i]);
2200                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2201                                     pf->offset_loaded,
2202                                     &os->priority_xoff_tx[i],
2203                                     &ns->priority_xoff_tx[i]);
2204                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2205                                     pf->offset_loaded,
2206                                     &os->priority_xon_2_xoff[i],
2207                                     &ns->priority_xon_2_xoff[i]);
2208         }
2209         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2210                             I40E_GLPRT_PRC64L(hw->port),
2211                             pf->offset_loaded, &os->rx_size_64,
2212                             &ns->rx_size_64);
2213         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2214                             I40E_GLPRT_PRC127L(hw->port),
2215                             pf->offset_loaded, &os->rx_size_127,
2216                             &ns->rx_size_127);
2217         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2218                             I40E_GLPRT_PRC255L(hw->port),
2219                             pf->offset_loaded, &os->rx_size_255,
2220                             &ns->rx_size_255);
2221         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2222                             I40E_GLPRT_PRC511L(hw->port),
2223                             pf->offset_loaded, &os->rx_size_511,
2224                             &ns->rx_size_511);
2225         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2226                             I40E_GLPRT_PRC1023L(hw->port),
2227                             pf->offset_loaded, &os->rx_size_1023,
2228                             &ns->rx_size_1023);
2229         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2230                             I40E_GLPRT_PRC1522L(hw->port),
2231                             pf->offset_loaded, &os->rx_size_1522,
2232                             &ns->rx_size_1522);
2233         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2234                             I40E_GLPRT_PRC9522L(hw->port),
2235                             pf->offset_loaded, &os->rx_size_big,
2236                             &ns->rx_size_big);
2237         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2238                             pf->offset_loaded, &os->rx_undersize,
2239                             &ns->rx_undersize);
2240         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2241                             pf->offset_loaded, &os->rx_fragments,
2242                             &ns->rx_fragments);
2243         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2244                             pf->offset_loaded, &os->rx_oversize,
2245                             &ns->rx_oversize);
2246         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2247                             pf->offset_loaded, &os->rx_jabber,
2248                             &ns->rx_jabber);
2249         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2250                             I40E_GLPRT_PTC64L(hw->port),
2251                             pf->offset_loaded, &os->tx_size_64,
2252                             &ns->tx_size_64);
2253         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2254                             I40E_GLPRT_PTC127L(hw->port),
2255                             pf->offset_loaded, &os->tx_size_127,
2256                             &ns->tx_size_127);
2257         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2258                             I40E_GLPRT_PTC255L(hw->port),
2259                             pf->offset_loaded, &os->tx_size_255,
2260                             &ns->tx_size_255);
2261         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2262                             I40E_GLPRT_PTC511L(hw->port),
2263                             pf->offset_loaded, &os->tx_size_511,
2264                             &ns->tx_size_511);
2265         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2266                             I40E_GLPRT_PTC1023L(hw->port),
2267                             pf->offset_loaded, &os->tx_size_1023,
2268                             &ns->tx_size_1023);
2269         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2270                             I40E_GLPRT_PTC1522L(hw->port),
2271                             pf->offset_loaded, &os->tx_size_1522,
2272                             &ns->tx_size_1522);
2273         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2274                             I40E_GLPRT_PTC9522L(hw->port),
2275                             pf->offset_loaded, &os->tx_size_big,
2276                             &ns->tx_size_big);
2277         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2278                            pf->offset_loaded,
2279                            &os->fd_sb_match, &ns->fd_sb_match);
2280         /* GLPRT_MSPDC not supported */
2281         /* GLPRT_XEC not supported */
2282
2283         pf->offset_loaded = true;
2284
2285         if (pf->main_vsi)
2286                 i40e_update_vsi_stats(pf->main_vsi);
2287 }
2288
2289 /* Get all statistics of a port */
2290 static void
2291 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2292 {
2293         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2294         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2295         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2296         unsigned i;
2297
2298         /* call read registers - updates values, now write them to struct */
2299         i40e_read_stats_registers(pf, hw);
2300
2301         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2302                         pf->main_vsi->eth_stats.rx_multicast +
2303                         pf->main_vsi->eth_stats.rx_broadcast -
2304                         pf->main_vsi->eth_stats.rx_discards;
2305         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2306                         pf->main_vsi->eth_stats.tx_multicast +
2307                         pf->main_vsi->eth_stats.tx_broadcast;
2308         stats->ibytes   = ns->eth.rx_bytes;
2309         stats->obytes   = ns->eth.tx_bytes;
2310         stats->oerrors  = ns->eth.tx_errors +
2311                         pf->main_vsi->eth_stats.tx_errors;
2312
2313         /* Rx Errors */
2314         stats->imissed  = ns->eth.rx_discards +
2315                         pf->main_vsi->eth_stats.rx_discards;
2316         stats->ierrors  = ns->crc_errors +
2317                         ns->rx_length_errors + ns->rx_undersize +
2318                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2319
2320         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2321         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2322         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2323         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2324         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2325         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2326         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2327                     ns->eth.rx_unknown_protocol);
2328         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2329         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2330         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2331         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2332         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2333         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2334
2335         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2336                     ns->tx_dropped_link_down);
2337         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2338         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2339                     ns->illegal_bytes);
2340         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2341         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2342                     ns->mac_local_faults);
2343         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2344                     ns->mac_remote_faults);
2345         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2346                     ns->rx_length_errors);
2347         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2348         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2349         for (i = 0; i < 8; i++) {
2350                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2351                                 i, ns->priority_xon_rx[i]);
2352                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2353                                 i, ns->priority_xoff_rx[i]);
2354         }
2355         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2356         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2357         for (i = 0; i < 8; i++) {
2358                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2359                                 i, ns->priority_xon_tx[i]);
2360                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2361                                 i, ns->priority_xoff_tx[i]);
2362                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2363                                 i, ns->priority_xon_2_xoff[i]);
2364         }
2365         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2366         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2367         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2368         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2369         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2370         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2371         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2372         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2373         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2374         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2375         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2376         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2377         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2378         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2379         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2380         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2381         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2382         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2383         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2384                         ns->mac_short_packet_dropped);
2385         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2386                     ns->checksum_error);
2387         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2388         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2389 }
2390
2391 /* Reset the statistics */
2392 static void
2393 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2394 {
2395         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2396         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2397
2398         /* Mark PF and VSI stats to update the offset, aka "reset" */
2399         pf->offset_loaded = false;
2400         if (pf->main_vsi)
2401                 pf->main_vsi->offset_loaded = false;
2402
2403         /* read the stats, reading current register values into offset */
2404         i40e_read_stats_registers(pf, hw);
2405 }
2406
2407 static uint32_t
2408 i40e_xstats_calc_num(void)
2409 {
2410         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2411                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2412                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2413 }
2414
2415 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2416                                      struct rte_eth_xstat_name *xstats_names,
2417                                      __rte_unused unsigned limit)
2418 {
2419         unsigned count = 0;
2420         unsigned i, prio;
2421
2422         if (xstats_names == NULL)
2423                 return i40e_xstats_calc_num();
2424
2425         /* Note: limit checked in rte_eth_xstats_names() */
2426
2427         /* Get stats from i40e_eth_stats struct */
2428         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2429                 snprintf(xstats_names[count].name,
2430                          sizeof(xstats_names[count].name),
2431                          "%s", rte_i40e_stats_strings[i].name);
2432                 count++;
2433         }
2434
2435         /* Get individiual stats from i40e_hw_port struct */
2436         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2437                 snprintf(xstats_names[count].name,
2438                         sizeof(xstats_names[count].name),
2439                          "%s", rte_i40e_hw_port_strings[i].name);
2440                 count++;
2441         }
2442
2443         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2444                 for (prio = 0; prio < 8; prio++) {
2445                         snprintf(xstats_names[count].name,
2446                                  sizeof(xstats_names[count].name),
2447                                  "rx_priority%u_%s", prio,
2448                                  rte_i40e_rxq_prio_strings[i].name);
2449                         count++;
2450                 }
2451         }
2452
2453         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2454                 for (prio = 0; prio < 8; prio++) {
2455                         snprintf(xstats_names[count].name,
2456                                  sizeof(xstats_names[count].name),
2457                                  "tx_priority%u_%s", prio,
2458                                  rte_i40e_txq_prio_strings[i].name);
2459                         count++;
2460                 }
2461         }
2462         return count;
2463 }
2464
2465 static int
2466 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2467                     unsigned n)
2468 {
2469         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2470         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2471         unsigned i, count, prio;
2472         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2473
2474         count = i40e_xstats_calc_num();
2475         if (n < count)
2476                 return count;
2477
2478         i40e_read_stats_registers(pf, hw);
2479
2480         if (xstats == NULL)
2481                 return 0;
2482
2483         count = 0;
2484
2485         /* Get stats from i40e_eth_stats struct */
2486         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2487                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2488                         rte_i40e_stats_strings[i].offset);
2489                 count++;
2490         }
2491
2492         /* Get individiual stats from i40e_hw_port struct */
2493         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2494                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2495                         rte_i40e_hw_port_strings[i].offset);
2496                 count++;
2497         }
2498
2499         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2500                 for (prio = 0; prio < 8; prio++) {
2501                         xstats[count].value =
2502                                 *(uint64_t *)(((char *)hw_stats) +
2503                                 rte_i40e_rxq_prio_strings[i].offset +
2504                                 (sizeof(uint64_t) * prio));
2505                         count++;
2506                 }
2507         }
2508
2509         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2510                 for (prio = 0; prio < 8; prio++) {
2511                         xstats[count].value =
2512                                 *(uint64_t *)(((char *)hw_stats) +
2513                                 rte_i40e_txq_prio_strings[i].offset +
2514                                 (sizeof(uint64_t) * prio));
2515                         count++;
2516                 }
2517         }
2518
2519         return count;
2520 }
2521
2522 static int
2523 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2524                                  __rte_unused uint16_t queue_id,
2525                                  __rte_unused uint8_t stat_idx,
2526                                  __rte_unused uint8_t is_rx)
2527 {
2528         PMD_INIT_FUNC_TRACE();
2529
2530         return -ENOSYS;
2531 }
2532
2533 static void
2534 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2535 {
2536         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2537         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538         struct i40e_vsi *vsi = pf->main_vsi;
2539
2540         dev_info->max_rx_queues = vsi->nb_qps;
2541         dev_info->max_tx_queues = vsi->nb_qps;
2542         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2543         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2544         dev_info->max_mac_addrs = vsi->max_macaddrs;
2545         dev_info->max_vfs = dev->pci_dev->max_vfs;
2546         dev_info->rx_offload_capa =
2547                 DEV_RX_OFFLOAD_VLAN_STRIP |
2548                 DEV_RX_OFFLOAD_QINQ_STRIP |
2549                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2550                 DEV_RX_OFFLOAD_UDP_CKSUM |
2551                 DEV_RX_OFFLOAD_TCP_CKSUM;
2552         dev_info->tx_offload_capa =
2553                 DEV_TX_OFFLOAD_VLAN_INSERT |
2554                 DEV_TX_OFFLOAD_QINQ_INSERT |
2555                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2556                 DEV_TX_OFFLOAD_UDP_CKSUM |
2557                 DEV_TX_OFFLOAD_TCP_CKSUM |
2558                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2559                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2560                 DEV_TX_OFFLOAD_TCP_TSO;
2561         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2562                                                 sizeof(uint32_t);
2563         dev_info->reta_size = pf->hash_lut_size;
2564         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2565
2566         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2567                 .rx_thresh = {
2568                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2569                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2570                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2571                 },
2572                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2573                 .rx_drop_en = 0,
2574         };
2575
2576         dev_info->default_txconf = (struct rte_eth_txconf) {
2577                 .tx_thresh = {
2578                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2579                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2580                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2581                 },
2582                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2583                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2584                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2585                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2586         };
2587
2588         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2589                 .nb_max = I40E_MAX_RING_DESC,
2590                 .nb_min = I40E_MIN_RING_DESC,
2591                 .nb_align = I40E_ALIGN_RING_DESC,
2592         };
2593
2594         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2595                 .nb_max = I40E_MAX_RING_DESC,
2596                 .nb_min = I40E_MIN_RING_DESC,
2597                 .nb_align = I40E_ALIGN_RING_DESC,
2598         };
2599
2600         if (pf->flags & I40E_FLAG_VMDQ) {
2601                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2602                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2603                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2604                                                 pf->max_nb_vmdq_vsi;
2605                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2606                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2607                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2608         }
2609
2610         if (i40e_is_40G_device(hw->device_id))
2611                 /* For XL710 */
2612                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2613         else
2614                 /* For X710 */
2615                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2616 }
2617
2618 static int
2619 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2620 {
2621         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2622         struct i40e_vsi *vsi = pf->main_vsi;
2623         PMD_INIT_FUNC_TRACE();
2624
2625         if (on)
2626                 return i40e_vsi_add_vlan(vsi, vlan_id);
2627         else
2628                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2629 }
2630
2631 static int
2632 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2633                    enum rte_vlan_type vlan_type,
2634                    uint16_t tpid)
2635 {
2636         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2637         uint64_t reg_r = 0, reg_w = 0;
2638         uint16_t reg_id = 0;
2639         int ret = 0;
2640         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2641
2642         switch (vlan_type) {
2643         case ETH_VLAN_TYPE_OUTER:
2644                 if (qinq)
2645                         reg_id = 2;
2646                 else
2647                         reg_id = 3;
2648                 break;
2649         case ETH_VLAN_TYPE_INNER:
2650                 if (qinq)
2651                         reg_id = 3;
2652                 else {
2653                         ret = -EINVAL;
2654                         PMD_DRV_LOG(ERR,
2655                                 "Unsupported vlan type in single vlan.\n");
2656                         return ret;
2657                 }
2658                 break;
2659         default:
2660                 ret = -EINVAL;
2661                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2662                 return ret;
2663         }
2664         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2665                                           &reg_r, NULL);
2666         if (ret != I40E_SUCCESS) {
2667                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2668                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2669                 ret = -EIO;
2670                 return ret;
2671         }
2672         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2673                     "0x%08"PRIx64"", reg_id, reg_r);
2674
2675         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2676         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2677         if (reg_r == reg_w) {
2678                 ret = 0;
2679                 PMD_DRV_LOG(DEBUG, "No need to write");
2680                 return ret;
2681         }
2682
2683         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2684                                            reg_w, NULL);
2685         if (ret != I40E_SUCCESS) {
2686                 ret = -EIO;
2687                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2688                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2689                 return ret;
2690         }
2691         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2692                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2693
2694         return ret;
2695 }
2696
2697 static void
2698 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2699 {
2700         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2701         struct i40e_vsi *vsi = pf->main_vsi;
2702
2703         if (mask & ETH_VLAN_FILTER_MASK) {
2704                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2705                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2706                 else
2707                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2708         }
2709
2710         if (mask & ETH_VLAN_STRIP_MASK) {
2711                 /* Enable or disable VLAN stripping */
2712                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2713                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2714                 else
2715                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2716         }
2717
2718         if (mask & ETH_VLAN_EXTEND_MASK) {
2719                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2720                         i40e_vsi_config_double_vlan(vsi, TRUE);
2721                         /* Set global registers with default ether type value */
2722                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2723                                            ETHER_TYPE_VLAN);
2724                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2725                                            ETHER_TYPE_VLAN);
2726                 }
2727                 else
2728                         i40e_vsi_config_double_vlan(vsi, FALSE);
2729         }
2730 }
2731
2732 static void
2733 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2734                           __rte_unused uint16_t queue,
2735                           __rte_unused int on)
2736 {
2737         PMD_INIT_FUNC_TRACE();
2738 }
2739
2740 static int
2741 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2742 {
2743         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2744         struct i40e_vsi *vsi = pf->main_vsi;
2745         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2746         struct i40e_vsi_vlan_pvid_info info;
2747
2748         memset(&info, 0, sizeof(info));
2749         info.on = on;
2750         if (info.on)
2751                 info.config.pvid = pvid;
2752         else {
2753                 info.config.reject.tagged =
2754                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2755                 info.config.reject.untagged =
2756                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2757         }
2758
2759         return i40e_vsi_vlan_pvid_set(vsi, &info);
2760 }
2761
2762 static int
2763 i40e_dev_led_on(struct rte_eth_dev *dev)
2764 {
2765         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2766         uint32_t mode = i40e_led_get(hw);
2767
2768         if (mode == 0)
2769                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2770
2771         return 0;
2772 }
2773
2774 static int
2775 i40e_dev_led_off(struct rte_eth_dev *dev)
2776 {
2777         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2778         uint32_t mode = i40e_led_get(hw);
2779
2780         if (mode != 0)
2781                 i40e_led_set(hw, 0, false);
2782
2783         return 0;
2784 }
2785
2786 static int
2787 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2788 {
2789         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2790         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2791
2792         fc_conf->pause_time = pf->fc_conf.pause_time;
2793         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2794         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2795
2796          /* Return current mode according to actual setting*/
2797         switch (hw->fc.current_mode) {
2798         case I40E_FC_FULL:
2799                 fc_conf->mode = RTE_FC_FULL;
2800                 break;
2801         case I40E_FC_TX_PAUSE:
2802                 fc_conf->mode = RTE_FC_TX_PAUSE;
2803                 break;
2804         case I40E_FC_RX_PAUSE:
2805                 fc_conf->mode = RTE_FC_RX_PAUSE;
2806                 break;
2807         case I40E_FC_NONE:
2808         default:
2809                 fc_conf->mode = RTE_FC_NONE;
2810         };
2811
2812         return 0;
2813 }
2814
2815 static int
2816 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2817 {
2818         uint32_t mflcn_reg, fctrl_reg, reg;
2819         uint32_t max_high_water;
2820         uint8_t i, aq_failure;
2821         int err;
2822         struct i40e_hw *hw;
2823         struct i40e_pf *pf;
2824         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2825                 [RTE_FC_NONE] = I40E_FC_NONE,
2826                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2827                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2828                 [RTE_FC_FULL] = I40E_FC_FULL
2829         };
2830
2831         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2832
2833         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2834         if ((fc_conf->high_water > max_high_water) ||
2835                         (fc_conf->high_water < fc_conf->low_water)) {
2836                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2837                         "High_water must <= %d.", max_high_water);
2838                 return -EINVAL;
2839         }
2840
2841         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2843         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2844
2845         pf->fc_conf.pause_time = fc_conf->pause_time;
2846         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2847         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2848
2849         PMD_INIT_FUNC_TRACE();
2850
2851         /* All the link flow control related enable/disable register
2852          * configuration is handle by the F/W
2853          */
2854         err = i40e_set_fc(hw, &aq_failure, true);
2855         if (err < 0)
2856                 return -ENOSYS;
2857
2858         if (i40e_is_40G_device(hw->device_id)) {
2859                 /* Configure flow control refresh threshold,
2860                  * the value for stat_tx_pause_refresh_timer[8]
2861                  * is used for global pause operation.
2862                  */
2863
2864                 I40E_WRITE_REG(hw,
2865                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2866                                pf->fc_conf.pause_time);
2867
2868                 /* configure the timer value included in transmitted pause
2869                  * frame,
2870                  * the value for stat_tx_pause_quanta[8] is used for global
2871                  * pause operation
2872                  */
2873                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2874                                pf->fc_conf.pause_time);
2875
2876                 fctrl_reg = I40E_READ_REG(hw,
2877                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2878
2879                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2880                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2881                 else
2882                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2883
2884                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2885                                fctrl_reg);
2886         } else {
2887                 /* Configure pause time (2 TCs per register) */
2888                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2889                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2890                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2891
2892                 /* Configure flow control refresh threshold value */
2893                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2894                                pf->fc_conf.pause_time / 2);
2895
2896                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2897
2898                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2899                  *depending on configuration
2900                  */
2901                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2902                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2903                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2904                 } else {
2905                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2906                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2907                 }
2908
2909                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2910         }
2911
2912         /* config the water marker both based on the packets and bytes */
2913         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2914                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2915                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2916         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2917                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2918                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2919         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2920                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2921                        << I40E_KILOSHIFT);
2922         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2923                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2924                        << I40E_KILOSHIFT);
2925
2926         I40E_WRITE_FLUSH(hw);
2927
2928         return 0;
2929 }
2930
2931 static int
2932 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2933                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2934 {
2935         PMD_INIT_FUNC_TRACE();
2936
2937         return -ENOSYS;
2938 }
2939
2940 /* Add a MAC address, and update filters */
2941 static void
2942 i40e_macaddr_add(struct rte_eth_dev *dev,
2943                  struct ether_addr *mac_addr,
2944                  __rte_unused uint32_t index,
2945                  uint32_t pool)
2946 {
2947         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2948         struct i40e_mac_filter_info mac_filter;
2949         struct i40e_vsi *vsi;
2950         int ret;
2951
2952         /* If VMDQ not enabled or configured, return */
2953         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
2954                           !pf->nb_cfg_vmdq_vsi)) {
2955                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2956                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
2957                         pool);
2958                 return;
2959         }
2960
2961         if (pool > pf->nb_cfg_vmdq_vsi) {
2962                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2963                                 pool, pf->nb_cfg_vmdq_vsi);
2964                 return;
2965         }
2966
2967         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2968         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2969                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2970         else
2971                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2972
2973         if (pool == 0)
2974                 vsi = pf->main_vsi;
2975         else
2976                 vsi = pf->vmdq[pool - 1].vsi;
2977
2978         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2979         if (ret != I40E_SUCCESS) {
2980                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2981                 return;
2982         }
2983 }
2984
2985 /* Remove a MAC address, and update filters */
2986 static void
2987 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2988 {
2989         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2990         struct i40e_vsi *vsi;
2991         struct rte_eth_dev_data *data = dev->data;
2992         struct ether_addr *macaddr;
2993         int ret;
2994         uint32_t i;
2995         uint64_t pool_sel;
2996
2997         macaddr = &(data->mac_addrs[index]);
2998
2999         pool_sel = dev->data->mac_pool_sel[index];
3000
3001         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3002                 if (pool_sel & (1ULL << i)) {
3003                         if (i == 0)
3004                                 vsi = pf->main_vsi;
3005                         else {
3006                                 /* No VMDQ pool enabled or configured */
3007                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3008                                         (i > pf->nb_cfg_vmdq_vsi)) {
3009                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3010                                                         "/configured");
3011                                         return;
3012                                 }
3013                                 vsi = pf->vmdq[i - 1].vsi;
3014                         }
3015                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3016
3017                         if (ret) {
3018                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3019                                 return;
3020                         }
3021                 }
3022         }
3023 }
3024
3025 /* Set perfect match or hash match of MAC and VLAN for a VF */
3026 static int
3027 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3028                  struct rte_eth_mac_filter *filter,
3029                  bool add)
3030 {
3031         struct i40e_hw *hw;
3032         struct i40e_mac_filter_info mac_filter;
3033         struct ether_addr old_mac;
3034         struct ether_addr *new_mac;
3035         struct i40e_pf_vf *vf = NULL;
3036         uint16_t vf_id;
3037         int ret;
3038
3039         if (pf == NULL) {
3040                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3041                 return -EINVAL;
3042         }
3043         hw = I40E_PF_TO_HW(pf);
3044
3045         if (filter == NULL) {
3046                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3047                 return -EINVAL;
3048         }
3049
3050         new_mac = &filter->mac_addr;
3051
3052         if (is_zero_ether_addr(new_mac)) {
3053                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3054                 return -EINVAL;
3055         }
3056
3057         vf_id = filter->dst_id;
3058
3059         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3060                 PMD_DRV_LOG(ERR, "Invalid argument.");
3061                 return -EINVAL;
3062         }
3063         vf = &pf->vfs[vf_id];
3064
3065         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3066                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3067                 return -EINVAL;
3068         }
3069
3070         if (add) {
3071                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3072                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3073                                 ETHER_ADDR_LEN);
3074                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3075                                  ETHER_ADDR_LEN);
3076
3077                 mac_filter.filter_type = filter->filter_type;
3078                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3079                 if (ret != I40E_SUCCESS) {
3080                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3081                         return -1;
3082                 }
3083                 ether_addr_copy(new_mac, &pf->dev_addr);
3084         } else {
3085                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3086                                 ETHER_ADDR_LEN);
3087                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3088                 if (ret != I40E_SUCCESS) {
3089                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3090                         return -1;
3091                 }
3092
3093                 /* Clear device address as it has been removed */
3094                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3095                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3096         }
3097
3098         return 0;
3099 }
3100
3101 /* MAC filter handle */
3102 static int
3103 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3104                 void *arg)
3105 {
3106         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3107         struct rte_eth_mac_filter *filter;
3108         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3109         int ret = I40E_NOT_SUPPORTED;
3110
3111         filter = (struct rte_eth_mac_filter *)(arg);
3112
3113         switch (filter_op) {
3114         case RTE_ETH_FILTER_NOP:
3115                 ret = I40E_SUCCESS;
3116                 break;
3117         case RTE_ETH_FILTER_ADD:
3118                 i40e_pf_disable_irq0(hw);
3119                 if (filter->is_vf)
3120                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3121                 i40e_pf_enable_irq0(hw);
3122                 break;
3123         case RTE_ETH_FILTER_DELETE:
3124                 i40e_pf_disable_irq0(hw);
3125                 if (filter->is_vf)
3126                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3127                 i40e_pf_enable_irq0(hw);
3128                 break;
3129         default:
3130                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3131                 ret = I40E_ERR_PARAM;
3132                 break;
3133         }
3134
3135         return ret;
3136 }
3137
3138 static int
3139 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3140 {
3141         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3142         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3143         int ret;
3144
3145         if (!lut)
3146                 return -EINVAL;
3147
3148         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3149                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3150                                           lut, lut_size);
3151                 if (ret) {
3152                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3153                         return ret;
3154                 }
3155         } else {
3156                 uint32_t *lut_dw = (uint32_t *)lut;
3157                 uint16_t i, lut_size_dw = lut_size / 4;
3158
3159                 for (i = 0; i < lut_size_dw; i++)
3160                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3161         }
3162
3163         return 0;
3164 }
3165
3166 static int
3167 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3168 {
3169         struct i40e_pf *pf;
3170         struct i40e_hw *hw;
3171         int ret;
3172
3173         if (!vsi || !lut)
3174                 return -EINVAL;
3175
3176         pf = I40E_VSI_TO_PF(vsi);
3177         hw = I40E_VSI_TO_HW(vsi);
3178
3179         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3180                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3181                                           lut, lut_size);
3182                 if (ret) {
3183                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3184                         return ret;
3185                 }
3186         } else {
3187                 uint32_t *lut_dw = (uint32_t *)lut;
3188                 uint16_t i, lut_size_dw = lut_size / 4;
3189
3190                 for (i = 0; i < lut_size_dw; i++)
3191                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3192                 I40E_WRITE_FLUSH(hw);
3193         }
3194
3195         return 0;
3196 }
3197
3198 static int
3199 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3200                          struct rte_eth_rss_reta_entry64 *reta_conf,
3201                          uint16_t reta_size)
3202 {
3203         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3204         uint16_t i, lut_size = pf->hash_lut_size;
3205         uint16_t idx, shift;
3206         uint8_t *lut;
3207         int ret;
3208
3209         if (reta_size != lut_size ||
3210                 reta_size > ETH_RSS_RETA_SIZE_512) {
3211                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3212                         "(%d) doesn't match the number hardware can supported "
3213                                         "(%d)\n", reta_size, lut_size);
3214                 return -EINVAL;
3215         }
3216
3217         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3218         if (!lut) {
3219                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3220                 return -ENOMEM;
3221         }
3222         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3223         if (ret)
3224                 goto out;
3225         for (i = 0; i < reta_size; i++) {
3226                 idx = i / RTE_RETA_GROUP_SIZE;
3227                 shift = i % RTE_RETA_GROUP_SIZE;
3228                 if (reta_conf[idx].mask & (1ULL << shift))
3229                         lut[i] = reta_conf[idx].reta[shift];
3230         }
3231         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3232
3233 out:
3234         rte_free(lut);
3235
3236         return ret;
3237 }
3238
3239 static int
3240 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3241                         struct rte_eth_rss_reta_entry64 *reta_conf,
3242                         uint16_t reta_size)
3243 {
3244         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3245         uint16_t i, lut_size = pf->hash_lut_size;
3246         uint16_t idx, shift;
3247         uint8_t *lut;
3248         int ret;
3249
3250         if (reta_size != lut_size ||
3251                 reta_size > ETH_RSS_RETA_SIZE_512) {
3252                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3253                         "(%d) doesn't match the number hardware can supported "
3254                                         "(%d)\n", reta_size, lut_size);
3255                 return -EINVAL;
3256         }
3257
3258         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3259         if (!lut) {
3260                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3261                 return -ENOMEM;
3262         }
3263
3264         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3265         if (ret)
3266                 goto out;
3267         for (i = 0; i < reta_size; i++) {
3268                 idx = i / RTE_RETA_GROUP_SIZE;
3269                 shift = i % RTE_RETA_GROUP_SIZE;
3270                 if (reta_conf[idx].mask & (1ULL << shift))
3271                         reta_conf[idx].reta[shift] = lut[i];
3272         }
3273
3274 out:
3275         rte_free(lut);
3276
3277         return ret;
3278 }
3279
3280 /**
3281  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3282  * @hw:   pointer to the HW structure
3283  * @mem:  pointer to mem struct to fill out
3284  * @size: size of memory requested
3285  * @alignment: what to align the allocation to
3286  **/
3287 enum i40e_status_code
3288 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3289                         struct i40e_dma_mem *mem,
3290                         u64 size,
3291                         u32 alignment)
3292 {
3293         const struct rte_memzone *mz = NULL;
3294         char z_name[RTE_MEMZONE_NAMESIZE];
3295
3296         if (!mem)
3297                 return I40E_ERR_PARAM;
3298
3299         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3300         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3301                                          alignment, RTE_PGSIZE_2M);
3302         if (!mz)
3303                 return I40E_ERR_NO_MEMORY;
3304
3305         mem->size = size;
3306         mem->va = mz->addr;
3307         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3308         mem->zone = (const void *)mz;
3309         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3310                     "%"PRIu64, mz->name, mem->pa);
3311
3312         return I40E_SUCCESS;
3313 }
3314
3315 /**
3316  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3317  * @hw:   pointer to the HW structure
3318  * @mem:  ptr to mem struct to free
3319  **/
3320 enum i40e_status_code
3321 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3322                     struct i40e_dma_mem *mem)
3323 {
3324         if (!mem)
3325                 return I40E_ERR_PARAM;
3326
3327         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3328                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3329                     mem->pa);
3330         rte_memzone_free((const struct rte_memzone *)mem->zone);
3331         mem->zone = NULL;
3332         mem->va = NULL;
3333         mem->pa = (u64)0;
3334
3335         return I40E_SUCCESS;
3336 }
3337
3338 /**
3339  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3340  * @hw:   pointer to the HW structure
3341  * @mem:  pointer to mem struct to fill out
3342  * @size: size of memory requested
3343  **/
3344 enum i40e_status_code
3345 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3346                          struct i40e_virt_mem *mem,
3347                          u32 size)
3348 {
3349         if (!mem)
3350                 return I40E_ERR_PARAM;
3351
3352         mem->size = size;
3353         mem->va = rte_zmalloc("i40e", size, 0);
3354
3355         if (mem->va)
3356                 return I40E_SUCCESS;
3357         else
3358                 return I40E_ERR_NO_MEMORY;
3359 }
3360
3361 /**
3362  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3363  * @hw:   pointer to the HW structure
3364  * @mem:  pointer to mem struct to free
3365  **/
3366 enum i40e_status_code
3367 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3368                      struct i40e_virt_mem *mem)
3369 {
3370         if (!mem)
3371                 return I40E_ERR_PARAM;
3372
3373         rte_free(mem->va);
3374         mem->va = NULL;
3375
3376         return I40E_SUCCESS;
3377 }
3378
3379 void
3380 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3381 {
3382         rte_spinlock_init(&sp->spinlock);
3383 }
3384
3385 void
3386 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3387 {
3388         rte_spinlock_lock(&sp->spinlock);
3389 }
3390
3391 void
3392 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3393 {
3394         rte_spinlock_unlock(&sp->spinlock);
3395 }
3396
3397 void
3398 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3399 {
3400         return;
3401 }
3402
3403 /**
3404  * Get the hardware capabilities, which will be parsed
3405  * and saved into struct i40e_hw.
3406  */
3407 static int
3408 i40e_get_cap(struct i40e_hw *hw)
3409 {
3410         struct i40e_aqc_list_capabilities_element_resp *buf;
3411         uint16_t len, size = 0;
3412         int ret;
3413
3414         /* Calculate a huge enough buff for saving response data temporarily */
3415         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3416                                                 I40E_MAX_CAP_ELE_NUM;
3417         buf = rte_zmalloc("i40e", len, 0);
3418         if (!buf) {
3419                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3420                 return I40E_ERR_NO_MEMORY;
3421         }
3422
3423         /* Get, parse the capabilities and save it to hw */
3424         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3425                         i40e_aqc_opc_list_func_capabilities, NULL);
3426         if (ret != I40E_SUCCESS)
3427                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3428
3429         /* Free the temporary buffer after being used */
3430         rte_free(buf);
3431
3432         return ret;
3433 }
3434
3435 static int
3436 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3437 {
3438         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3439         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3440         uint16_t qp_count = 0, vsi_count = 0;
3441
3442         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3443                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3444                 return -EINVAL;
3445         }
3446         /* Add the parameter init for LFC */
3447         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3448         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3449         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3450
3451         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3452         pf->max_num_vsi = hw->func_caps.num_vsis;
3453         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3454         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3455         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3456
3457         /* FDir queue/VSI allocation */
3458         pf->fdir_qp_offset = 0;
3459         if (hw->func_caps.fd) {
3460                 pf->flags |= I40E_FLAG_FDIR;
3461                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3462         } else {
3463                 pf->fdir_nb_qps = 0;
3464         }
3465         qp_count += pf->fdir_nb_qps;
3466         vsi_count += 1;
3467
3468         /* LAN queue/VSI allocation */
3469         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3470         if (!hw->func_caps.rss) {
3471                 pf->lan_nb_qps = 1;
3472         } else {
3473                 pf->flags |= I40E_FLAG_RSS;
3474                 if (hw->mac.type == I40E_MAC_X722)
3475                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3476                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3477         }
3478         qp_count += pf->lan_nb_qps;
3479         vsi_count += 1;
3480
3481         /* VF queue/VSI allocation */
3482         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3483         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3484                 pf->flags |= I40E_FLAG_SRIOV;
3485                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3486                 pf->vf_num = dev->pci_dev->max_vfs;
3487                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3488                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3489                             pf->vf_nb_qps * pf->vf_num);
3490         } else {
3491                 pf->vf_nb_qps = 0;
3492                 pf->vf_num = 0;
3493         }
3494         qp_count += pf->vf_nb_qps * pf->vf_num;
3495         vsi_count += pf->vf_num;
3496
3497         /* VMDq queue/VSI allocation */
3498         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3499         pf->vmdq_nb_qps = 0;
3500         pf->max_nb_vmdq_vsi = 0;
3501         if (hw->func_caps.vmdq) {
3502                 if (qp_count < hw->func_caps.num_tx_qp &&
3503                         vsi_count < hw->func_caps.num_vsis) {
3504                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3505                                 qp_count) / pf->vmdq_nb_qp_max;
3506
3507                         /* Limit the maximum number of VMDq vsi to the maximum
3508                          * ethdev can support
3509                          */
3510                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3511                                 hw->func_caps.num_vsis - vsi_count);
3512                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3513                                 ETH_64_POOLS);
3514                         if (pf->max_nb_vmdq_vsi) {
3515                                 pf->flags |= I40E_FLAG_VMDQ;
3516                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3517                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3518                                             "per VMDQ VSI, in total %u queues",
3519                                             pf->max_nb_vmdq_vsi,
3520                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3521                                             pf->max_nb_vmdq_vsi);
3522                         } else {
3523                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3524                                             "VMDq");
3525                         }
3526                 } else {
3527                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3528                 }
3529         }
3530         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3531         vsi_count += pf->max_nb_vmdq_vsi;
3532
3533         if (hw->func_caps.dcb)
3534                 pf->flags |= I40E_FLAG_DCB;
3535
3536         if (qp_count > hw->func_caps.num_tx_qp) {
3537                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3538                             "the hardware maximum %u", qp_count,
3539                             hw->func_caps.num_tx_qp);
3540                 return -EINVAL;
3541         }
3542         if (vsi_count > hw->func_caps.num_vsis) {
3543                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3544                             "the hardware maximum %u", vsi_count,
3545                             hw->func_caps.num_vsis);
3546                 return -EINVAL;
3547         }
3548
3549         return 0;
3550 }
3551
3552 static int
3553 i40e_pf_get_switch_config(struct i40e_pf *pf)
3554 {
3555         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3556         struct i40e_aqc_get_switch_config_resp *switch_config;
3557         struct i40e_aqc_switch_config_element_resp *element;
3558         uint16_t start_seid = 0, num_reported;
3559         int ret;
3560
3561         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3562                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3563         if (!switch_config) {
3564                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3565                 return -ENOMEM;
3566         }
3567
3568         /* Get the switch configurations */
3569         ret = i40e_aq_get_switch_config(hw, switch_config,
3570                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3571         if (ret != I40E_SUCCESS) {
3572                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3573                 goto fail;
3574         }
3575         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3576         if (num_reported != 1) { /* The number should be 1 */
3577                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3578                 goto fail;
3579         }
3580
3581         /* Parse the switch configuration elements */
3582         element = &(switch_config->element[0]);
3583         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3584                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3585                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3586         } else
3587                 PMD_DRV_LOG(INFO, "Unknown element type");
3588
3589 fail:
3590         rte_free(switch_config);
3591
3592         return ret;
3593 }
3594
3595 static int
3596 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3597                         uint32_t num)
3598 {
3599         struct pool_entry *entry;
3600
3601         if (pool == NULL || num == 0)
3602                 return -EINVAL;
3603
3604         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3605         if (entry == NULL) {
3606                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3607                 return -ENOMEM;
3608         }
3609
3610         /* queue heap initialize */
3611         pool->num_free = num;
3612         pool->num_alloc = 0;
3613         pool->base = base;
3614         LIST_INIT(&pool->alloc_list);
3615         LIST_INIT(&pool->free_list);
3616
3617         /* Initialize element  */
3618         entry->base = 0;
3619         entry->len = num;
3620
3621         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3622         return 0;
3623 }
3624
3625 static void
3626 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3627 {
3628         struct pool_entry *entry, *next_entry;
3629
3630         if (pool == NULL)
3631                 return;
3632
3633         for (entry = LIST_FIRST(&pool->alloc_list);
3634                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3635                         entry = next_entry) {
3636                 LIST_REMOVE(entry, next);
3637                 rte_free(entry);
3638         }
3639
3640         for (entry = LIST_FIRST(&pool->free_list);
3641                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3642                         entry = next_entry) {
3643                 LIST_REMOVE(entry, next);
3644                 rte_free(entry);
3645         }
3646
3647         pool->num_free = 0;
3648         pool->num_alloc = 0;
3649         pool->base = 0;
3650         LIST_INIT(&pool->alloc_list);
3651         LIST_INIT(&pool->free_list);
3652 }
3653
3654 static int
3655 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3656                        uint32_t base)
3657 {
3658         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3659         uint32_t pool_offset;
3660         int insert;
3661
3662         if (pool == NULL) {
3663                 PMD_DRV_LOG(ERR, "Invalid parameter");
3664                 return -EINVAL;
3665         }
3666
3667         pool_offset = base - pool->base;
3668         /* Lookup in alloc list */
3669         LIST_FOREACH(entry, &pool->alloc_list, next) {
3670                 if (entry->base == pool_offset) {
3671                         valid_entry = entry;
3672                         LIST_REMOVE(entry, next);
3673                         break;
3674                 }
3675         }
3676
3677         /* Not find, return */
3678         if (valid_entry == NULL) {
3679                 PMD_DRV_LOG(ERR, "Failed to find entry");
3680                 return -EINVAL;
3681         }
3682
3683         /**
3684          * Found it, move it to free list  and try to merge.
3685          * In order to make merge easier, always sort it by qbase.
3686          * Find adjacent prev and last entries.
3687          */
3688         prev = next = NULL;
3689         LIST_FOREACH(entry, &pool->free_list, next) {
3690                 if (entry->base > valid_entry->base) {
3691                         next = entry;
3692                         break;
3693                 }
3694                 prev = entry;
3695         }
3696
3697         insert = 0;
3698         /* Try to merge with next one*/
3699         if (next != NULL) {
3700                 /* Merge with next one */
3701                 if (valid_entry->base + valid_entry->len == next->base) {
3702                         next->base = valid_entry->base;
3703                         next->len += valid_entry->len;
3704                         rte_free(valid_entry);
3705                         valid_entry = next;
3706                         insert = 1;
3707                 }
3708         }
3709
3710         if (prev != NULL) {
3711                 /* Merge with previous one */
3712                 if (prev->base + prev->len == valid_entry->base) {
3713                         prev->len += valid_entry->len;
3714                         /* If it merge with next one, remove next node */
3715                         if (insert == 1) {
3716                                 LIST_REMOVE(valid_entry, next);
3717                                 rte_free(valid_entry);
3718                         } else {
3719                                 rte_free(valid_entry);
3720                                 insert = 1;
3721                         }
3722                 }
3723         }
3724
3725         /* Not find any entry to merge, insert */
3726         if (insert == 0) {
3727                 if (prev != NULL)
3728                         LIST_INSERT_AFTER(prev, valid_entry, next);
3729                 else if (next != NULL)
3730                         LIST_INSERT_BEFORE(next, valid_entry, next);
3731                 else /* It's empty list, insert to head */
3732                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3733         }
3734
3735         pool->num_free += valid_entry->len;
3736         pool->num_alloc -= valid_entry->len;
3737
3738         return 0;
3739 }
3740
3741 static int
3742 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3743                        uint16_t num)
3744 {
3745         struct pool_entry *entry, *valid_entry;
3746
3747         if (pool == NULL || num == 0) {
3748                 PMD_DRV_LOG(ERR, "Invalid parameter");
3749                 return -EINVAL;
3750         }
3751
3752         if (pool->num_free < num) {
3753                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3754                             num, pool->num_free);
3755                 return -ENOMEM;
3756         }
3757
3758         valid_entry = NULL;
3759         /* Lookup  in free list and find most fit one */
3760         LIST_FOREACH(entry, &pool->free_list, next) {
3761                 if (entry->len >= num) {
3762                         /* Find best one */
3763                         if (entry->len == num) {
3764                                 valid_entry = entry;
3765                                 break;
3766                         }
3767                         if (valid_entry == NULL || valid_entry->len > entry->len)
3768                                 valid_entry = entry;
3769                 }
3770         }
3771
3772         /* Not find one to satisfy the request, return */
3773         if (valid_entry == NULL) {
3774                 PMD_DRV_LOG(ERR, "No valid entry found");
3775                 return -ENOMEM;
3776         }
3777         /**
3778          * The entry have equal queue number as requested,
3779          * remove it from alloc_list.
3780          */
3781         if (valid_entry->len == num) {
3782                 LIST_REMOVE(valid_entry, next);
3783         } else {
3784                 /**
3785                  * The entry have more numbers than requested,
3786                  * create a new entry for alloc_list and minus its
3787                  * queue base and number in free_list.
3788                  */
3789                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3790                 if (entry == NULL) {
3791                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3792                                     "resource pool");
3793                         return -ENOMEM;
3794                 }
3795                 entry->base = valid_entry->base;
3796                 entry->len = num;
3797                 valid_entry->base += num;
3798                 valid_entry->len -= num;
3799                 valid_entry = entry;
3800         }
3801
3802         /* Insert it into alloc list, not sorted */
3803         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3804
3805         pool->num_free -= valid_entry->len;
3806         pool->num_alloc += valid_entry->len;
3807
3808         return valid_entry->base + pool->base;
3809 }
3810
3811 /**
3812  * bitmap_is_subset - Check whether src2 is subset of src1
3813  **/
3814 static inline int
3815 bitmap_is_subset(uint8_t src1, uint8_t src2)
3816 {
3817         return !((src1 ^ src2) & src2);
3818 }
3819
3820 static enum i40e_status_code
3821 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3822 {
3823         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3824
3825         /* If DCB is not supported, only default TC is supported */
3826         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3827                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3828                 return I40E_NOT_SUPPORTED;
3829         }
3830
3831         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3832                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3833                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3834                             enabled_tcmap);
3835                 return I40E_NOT_SUPPORTED;
3836         }
3837         return I40E_SUCCESS;
3838 }
3839
3840 int
3841 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3842                                 struct i40e_vsi_vlan_pvid_info *info)
3843 {
3844         struct i40e_hw *hw;
3845         struct i40e_vsi_context ctxt;
3846         uint8_t vlan_flags = 0;
3847         int ret;
3848
3849         if (vsi == NULL || info == NULL) {
3850                 PMD_DRV_LOG(ERR, "invalid parameters");
3851                 return I40E_ERR_PARAM;
3852         }
3853
3854         if (info->on) {
3855                 vsi->info.pvid = info->config.pvid;
3856                 /**
3857                  * If insert pvid is enabled, only tagged pkts are
3858                  * allowed to be sent out.
3859                  */
3860                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3861                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3862         } else {
3863                 vsi->info.pvid = 0;
3864                 if (info->config.reject.tagged == 0)
3865                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3866
3867                 if (info->config.reject.untagged == 0)
3868                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3869         }
3870         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3871                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3872         vsi->info.port_vlan_flags |= vlan_flags;
3873         vsi->info.valid_sections =
3874                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3875         memset(&ctxt, 0, sizeof(ctxt));
3876         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3877         ctxt.seid = vsi->seid;
3878
3879         hw = I40E_VSI_TO_HW(vsi);
3880         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3881         if (ret != I40E_SUCCESS)
3882                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3883
3884         return ret;
3885 }
3886
3887 static int
3888 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3889 {
3890         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3891         int i, ret;
3892         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3893
3894         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3895         if (ret != I40E_SUCCESS)
3896                 return ret;
3897
3898         if (!vsi->seid) {
3899                 PMD_DRV_LOG(ERR, "seid not valid");
3900                 return -EINVAL;
3901         }
3902
3903         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3904         tc_bw_data.tc_valid_bits = enabled_tcmap;
3905         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3906                 tc_bw_data.tc_bw_credits[i] =
3907                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3908
3909         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3910         if (ret != I40E_SUCCESS) {
3911                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3912                 return ret;
3913         }
3914
3915         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3916                                         sizeof(vsi->info.qs_handle));
3917         return I40E_SUCCESS;
3918 }
3919
3920 static enum i40e_status_code
3921 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3922                                  struct i40e_aqc_vsi_properties_data *info,
3923                                  uint8_t enabled_tcmap)
3924 {
3925         enum i40e_status_code ret;
3926         int i, total_tc = 0;
3927         uint16_t qpnum_per_tc, bsf, qp_idx;
3928
3929         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3930         if (ret != I40E_SUCCESS)
3931                 return ret;
3932
3933         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3934                 if (enabled_tcmap & (1 << i))
3935                         total_tc++;
3936         vsi->enabled_tc = enabled_tcmap;
3937
3938         /* Number of queues per enabled TC */
3939         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3940         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3941         bsf = rte_bsf32(qpnum_per_tc);
3942
3943         /* Adjust the queue number to actual queues that can be applied */
3944         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3945                 vsi->nb_qps = qpnum_per_tc * total_tc;
3946
3947         /**
3948          * Configure TC and queue mapping parameters, for enabled TC,
3949          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3950          * default queue will serve it.
3951          */
3952         qp_idx = 0;
3953         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3954                 if (vsi->enabled_tc & (1 << i)) {
3955                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3956                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3957                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3958                         qp_idx += qpnum_per_tc;
3959                 } else
3960                         info->tc_mapping[i] = 0;
3961         }
3962
3963         /* Associate queue number with VSI */
3964         if (vsi->type == I40E_VSI_SRIOV) {
3965                 info->mapping_flags |=
3966                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3967                 for (i = 0; i < vsi->nb_qps; i++)
3968                         info->queue_mapping[i] =
3969                                 rte_cpu_to_le_16(vsi->base_queue + i);
3970         } else {
3971                 info->mapping_flags |=
3972                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3973                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3974         }
3975         info->valid_sections |=
3976                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3977
3978         return I40E_SUCCESS;
3979 }
3980
3981 static int
3982 i40e_veb_release(struct i40e_veb *veb)
3983 {
3984         struct i40e_vsi *vsi;
3985         struct i40e_hw *hw;
3986
3987         if (veb == NULL)
3988                 return -EINVAL;
3989
3990         if (!TAILQ_EMPTY(&veb->head)) {
3991                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3992                 return -EACCES;
3993         }
3994         /* associate_vsi field is NULL for floating VEB */
3995         if (veb->associate_vsi != NULL) {
3996                 vsi = veb->associate_vsi;
3997                 hw = I40E_VSI_TO_HW(vsi);
3998
3999                 vsi->uplink_seid = veb->uplink_seid;
4000                 vsi->veb = NULL;
4001         } else {
4002                 veb->associate_pf->main_vsi->floating_veb = NULL;
4003                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4004         }
4005
4006         i40e_aq_delete_element(hw, veb->seid, NULL);
4007         rte_free(veb);
4008         return I40E_SUCCESS;
4009 }
4010
4011 /* Setup a veb */
4012 static struct i40e_veb *
4013 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4014 {
4015         struct i40e_veb *veb;
4016         int ret;
4017         struct i40e_hw *hw;
4018
4019         if (pf == NULL) {
4020                 PMD_DRV_LOG(ERR,
4021                             "veb setup failed, associated PF shouldn't null");
4022                 return NULL;
4023         }
4024         hw = I40E_PF_TO_HW(pf);
4025
4026         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4027         if (!veb) {
4028                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4029                 goto fail;
4030         }
4031
4032         veb->associate_vsi = vsi;
4033         veb->associate_pf = pf;
4034         TAILQ_INIT(&veb->head);
4035         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4036
4037         /* create floating veb if vsi is NULL */
4038         if (vsi != NULL) {
4039                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4040                                       I40E_DEFAULT_TCMAP, false,
4041                                       &veb->seid, false, NULL);
4042         } else {
4043                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4044                                       true, &veb->seid, false, NULL);
4045         }
4046
4047         if (ret != I40E_SUCCESS) {
4048                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4049                             hw->aq.asq_last_status);
4050                 goto fail;
4051         }
4052
4053         /* get statistics index */
4054         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4055                                 &veb->stats_idx, NULL, NULL, NULL);
4056         if (ret != I40E_SUCCESS) {
4057                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4058                             hw->aq.asq_last_status);
4059                 goto fail;
4060         }
4061         /* Get VEB bandwidth, to be implemented */
4062         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4063         if (vsi)
4064                 vsi->uplink_seid = veb->seid;
4065
4066         return veb;
4067 fail:
4068         rte_free(veb);
4069         return NULL;
4070 }
4071
4072 int
4073 i40e_vsi_release(struct i40e_vsi *vsi)
4074 {
4075         struct i40e_pf *pf;
4076         struct i40e_hw *hw;
4077         struct i40e_vsi_list *vsi_list;
4078         void *temp;
4079         int ret;
4080         struct i40e_mac_filter *f;
4081         uint16_t user_param = vsi->user_param;
4082
4083         if (!vsi)
4084                 return I40E_SUCCESS;
4085
4086         pf = I40E_VSI_TO_PF(vsi);
4087         hw = I40E_VSI_TO_HW(vsi);
4088
4089         /* VSI has child to attach, release child first */
4090         if (vsi->veb) {
4091                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4092                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4093                                 return -1;
4094                 }
4095                 i40e_veb_release(vsi->veb);
4096         }
4097
4098         if (vsi->floating_veb) {
4099                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4100                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4101                                 return -1;
4102                 }
4103         }
4104
4105         /* Remove all macvlan filters of the VSI */
4106         i40e_vsi_remove_all_macvlan_filter(vsi);
4107         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4108                 rte_free(f);
4109
4110         if (vsi->type != I40E_VSI_MAIN &&
4111             ((vsi->type != I40E_VSI_SRIOV) ||
4112             !pf->floating_veb_list[user_param])) {
4113                 /* Remove vsi from parent's sibling list */
4114                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4115                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4116                         return I40E_ERR_PARAM;
4117                 }
4118                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4119                                 &vsi->sib_vsi_list, list);
4120
4121                 /* Remove all switch element of the VSI */
4122                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4123                 if (ret != I40E_SUCCESS)
4124                         PMD_DRV_LOG(ERR, "Failed to delete element");
4125         }
4126
4127         if ((vsi->type == I40E_VSI_SRIOV) &&
4128             pf->floating_veb_list[user_param]) {
4129                 /* Remove vsi from parent's sibling list */
4130                 if (vsi->parent_vsi == NULL ||
4131                     vsi->parent_vsi->floating_veb == NULL) {
4132                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4133                         return I40E_ERR_PARAM;
4134                 }
4135                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4136                              &vsi->sib_vsi_list, list);
4137
4138                 /* Remove all switch element of the VSI */
4139                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4140                 if (ret != I40E_SUCCESS)
4141                         PMD_DRV_LOG(ERR, "Failed to delete element");
4142         }
4143
4144         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4145
4146         if (vsi->type != I40E_VSI_SRIOV)
4147                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4148         rte_free(vsi);
4149
4150         return I40E_SUCCESS;
4151 }
4152
4153 static int
4154 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4155 {
4156         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4157         struct i40e_aqc_remove_macvlan_element_data def_filter;
4158         struct i40e_mac_filter_info filter;
4159         int ret;
4160
4161         if (vsi->type != I40E_VSI_MAIN)
4162                 return I40E_ERR_CONFIG;
4163         memset(&def_filter, 0, sizeof(def_filter));
4164         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4165                                         ETH_ADDR_LEN);
4166         def_filter.vlan_tag = 0;
4167         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4168                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4169         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4170         if (ret != I40E_SUCCESS) {
4171                 struct i40e_mac_filter *f;
4172                 struct ether_addr *mac;
4173
4174                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4175                             "macvlan filter");
4176                 /* It needs to add the permanent mac into mac list */
4177                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4178                 if (f == NULL) {
4179                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4180                         return I40E_ERR_NO_MEMORY;
4181                 }
4182                 mac = &f->mac_info.mac_addr;
4183                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4184                                 ETH_ADDR_LEN);
4185                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4186                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4187                 vsi->mac_num++;
4188
4189                 return ret;
4190         }
4191         (void)rte_memcpy(&filter.mac_addr,
4192                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4193         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4194         return i40e_vsi_add_mac(vsi, &filter);
4195 }
4196
4197 /*
4198  * i40e_vsi_get_bw_config - Query VSI BW Information
4199  * @vsi: the VSI to be queried
4200  *
4201  * Returns 0 on success, negative value on failure
4202  */
4203 static enum i40e_status_code
4204 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4205 {
4206         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4207         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4208         struct i40e_hw *hw = &vsi->adapter->hw;
4209         i40e_status ret;
4210         int i;
4211         uint32_t bw_max;
4212
4213         memset(&bw_config, 0, sizeof(bw_config));
4214         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4215         if (ret != I40E_SUCCESS) {
4216                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4217                             hw->aq.asq_last_status);
4218                 return ret;
4219         }
4220
4221         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4222         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4223                                         &ets_sla_config, NULL);
4224         if (ret != I40E_SUCCESS) {
4225                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4226                             "configuration %u", hw->aq.asq_last_status);
4227                 return ret;
4228         }
4229
4230         /* store and print out BW info */
4231         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4232         vsi->bw_info.bw_max = bw_config.max_bw;
4233         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4234         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4235         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4236                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4237                      I40E_16_BIT_WIDTH);
4238         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4239                 vsi->bw_info.bw_ets_share_credits[i] =
4240                                 ets_sla_config.share_credits[i];
4241                 vsi->bw_info.bw_ets_credits[i] =
4242                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4243                 /* 4 bits per TC, 4th bit is reserved */
4244                 vsi->bw_info.bw_ets_max[i] =
4245                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4246                                   RTE_LEN2MASK(3, uint8_t));
4247                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4248                             vsi->bw_info.bw_ets_share_credits[i]);
4249                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4250                             vsi->bw_info.bw_ets_credits[i]);
4251                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4252                             vsi->bw_info.bw_ets_max[i]);
4253         }
4254
4255         return I40E_SUCCESS;
4256 }
4257
4258 /* i40e_enable_pf_lb
4259  * @pf: pointer to the pf structure
4260  *
4261  * allow loopback on pf
4262  */
4263 static inline void
4264 i40e_enable_pf_lb(struct i40e_pf *pf)
4265 {
4266         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4267         struct i40e_vsi_context ctxt;
4268         int ret;
4269
4270         /* Use the FW API if FW >= v5.0 */
4271         if (hw->aq.fw_maj_ver < 5) {
4272                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4273                 return;
4274         }
4275
4276         memset(&ctxt, 0, sizeof(ctxt));
4277         ctxt.seid = pf->main_vsi_seid;
4278         ctxt.pf_num = hw->pf_id;
4279         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4280         if (ret) {
4281                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4282                             ret, hw->aq.asq_last_status);
4283                 return;
4284         }
4285         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4286         ctxt.info.valid_sections =
4287                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4288         ctxt.info.switch_id |=
4289                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4290
4291         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4292         if (ret)
4293                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4294                             hw->aq.asq_last_status);
4295 }
4296
4297 /* Setup a VSI */
4298 struct i40e_vsi *
4299 i40e_vsi_setup(struct i40e_pf *pf,
4300                enum i40e_vsi_type type,
4301                struct i40e_vsi *uplink_vsi,
4302                uint16_t user_param)
4303 {
4304         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4305         struct i40e_vsi *vsi;
4306         struct i40e_mac_filter_info filter;
4307         int ret;
4308         struct i40e_vsi_context ctxt;
4309         struct ether_addr broadcast =
4310                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4311
4312         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4313             uplink_vsi == NULL) {
4314                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4315                             "VSI link shouldn't be NULL");
4316                 return NULL;
4317         }
4318
4319         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4320                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4321                             "uplink VSI should be NULL");
4322                 return NULL;
4323         }
4324
4325         /* two situations
4326          * 1.type is not MAIN and uplink vsi is not NULL
4327          * If uplink vsi didn't setup VEB, create one first under veb field
4328          * 2.type is SRIOV and the uplink is NULL
4329          * If floating VEB is NULL, create one veb under floating veb field
4330          */
4331
4332         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4333             uplink_vsi->veb == NULL) {
4334                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4335
4336                 if (uplink_vsi->veb == NULL) {
4337                         PMD_DRV_LOG(ERR, "VEB setup failed");
4338                         return NULL;
4339                 }
4340                 /* set ALLOWLOOPBACk on pf, when veb is created */
4341                 i40e_enable_pf_lb(pf);
4342         }
4343
4344         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4345             pf->main_vsi->floating_veb == NULL) {
4346                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4347
4348                 if (pf->main_vsi->floating_veb == NULL) {
4349                         PMD_DRV_LOG(ERR, "VEB setup failed");
4350                         return NULL;
4351                 }
4352         }
4353
4354         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4355         if (!vsi) {
4356                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4357                 return NULL;
4358         }
4359         TAILQ_INIT(&vsi->mac_list);
4360         vsi->type = type;
4361         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4362         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4363         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4364         vsi->user_param = user_param;
4365         /* Allocate queues */
4366         switch (vsi->type) {
4367         case I40E_VSI_MAIN  :
4368                 vsi->nb_qps = pf->lan_nb_qps;
4369                 break;
4370         case I40E_VSI_SRIOV :
4371                 vsi->nb_qps = pf->vf_nb_qps;
4372                 break;
4373         case I40E_VSI_VMDQ2:
4374                 vsi->nb_qps = pf->vmdq_nb_qps;
4375                 break;
4376         case I40E_VSI_FDIR:
4377                 vsi->nb_qps = pf->fdir_nb_qps;
4378                 break;
4379         default:
4380                 goto fail_mem;
4381         }
4382         /*
4383          * The filter status descriptor is reported in rx queue 0,
4384          * while the tx queue for fdir filter programming has no
4385          * such constraints, can be non-zero queues.
4386          * To simplify it, choose FDIR vsi use queue 0 pair.
4387          * To make sure it will use queue 0 pair, queue allocation
4388          * need be done before this function is called
4389          */
4390         if (type != I40E_VSI_FDIR) {
4391                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4392                         if (ret < 0) {
4393                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4394                                                 vsi->seid, ret);
4395                                 goto fail_mem;
4396                         }
4397                         vsi->base_queue = ret;
4398         } else
4399                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4400
4401         /* VF has MSIX interrupt in VF range, don't allocate here */
4402         if (type == I40E_VSI_MAIN) {
4403                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4404                                           RTE_MIN(vsi->nb_qps,
4405                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4406                 if (ret < 0) {
4407                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4408                                     vsi->seid, ret);
4409                         goto fail_queue_alloc;
4410                 }
4411                 vsi->msix_intr = ret;
4412                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4413         } else if (type != I40E_VSI_SRIOV) {
4414                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4415                 if (ret < 0) {
4416                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4417                         goto fail_queue_alloc;
4418                 }
4419                 vsi->msix_intr = ret;
4420                 vsi->nb_msix = 1;
4421         } else {
4422                 vsi->msix_intr = 0;
4423                 vsi->nb_msix = 0;
4424         }
4425
4426         /* Add VSI */
4427         if (type == I40E_VSI_MAIN) {
4428                 /* For main VSI, no need to add since it's default one */
4429                 vsi->uplink_seid = pf->mac_seid;
4430                 vsi->seid = pf->main_vsi_seid;
4431                 /* Bind queues with specific MSIX interrupt */
4432                 /**
4433                  * Needs 2 interrupt at least, one for misc cause which will
4434                  * enabled from OS side, Another for queues binding the
4435                  * interrupt from device side only.
4436                  */
4437
4438                 /* Get default VSI parameters from hardware */
4439                 memset(&ctxt, 0, sizeof(ctxt));
4440                 ctxt.seid = vsi->seid;
4441                 ctxt.pf_num = hw->pf_id;
4442                 ctxt.uplink_seid = vsi->uplink_seid;
4443                 ctxt.vf_num = 0;
4444                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4445                 if (ret != I40E_SUCCESS) {
4446                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4447                         goto fail_msix_alloc;
4448                 }
4449                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4450                         sizeof(struct i40e_aqc_vsi_properties_data));
4451                 vsi->vsi_id = ctxt.vsi_number;
4452                 vsi->info.valid_sections = 0;
4453
4454                 /* Configure tc, enabled TC0 only */
4455                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4456                         I40E_SUCCESS) {
4457                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4458                         goto fail_msix_alloc;
4459                 }
4460
4461                 /* TC, queue mapping */
4462                 memset(&ctxt, 0, sizeof(ctxt));
4463                 vsi->info.valid_sections |=
4464                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4465                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4466                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4467                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4468                         sizeof(struct i40e_aqc_vsi_properties_data));
4469                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4470                                                 I40E_DEFAULT_TCMAP);
4471                 if (ret != I40E_SUCCESS) {
4472                         PMD_DRV_LOG(ERR, "Failed to configure "
4473                                     "TC queue mapping");
4474                         goto fail_msix_alloc;
4475                 }
4476                 ctxt.seid = vsi->seid;
4477                 ctxt.pf_num = hw->pf_id;
4478                 ctxt.uplink_seid = vsi->uplink_seid;
4479                 ctxt.vf_num = 0;
4480
4481                 /* Update VSI parameters */
4482                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4483                 if (ret != I40E_SUCCESS) {
4484                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4485                         goto fail_msix_alloc;
4486                 }
4487
4488                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4489                                                 sizeof(vsi->info.tc_mapping));
4490                 (void)rte_memcpy(&vsi->info.queue_mapping,
4491                                 &ctxt.info.queue_mapping,
4492                         sizeof(vsi->info.queue_mapping));
4493                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4494                 vsi->info.valid_sections = 0;
4495
4496                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4497                                 ETH_ADDR_LEN);
4498
4499                 /**
4500                  * Updating default filter settings are necessary to prevent
4501                  * reception of tagged packets.
4502                  * Some old firmware configurations load a default macvlan
4503                  * filter which accepts both tagged and untagged packets.
4504                  * The updating is to use a normal filter instead if needed.
4505                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4506                  * The firmware with correct configurations load the default
4507                  * macvlan filter which is expected and cannot be removed.
4508                  */
4509                 i40e_update_default_filter_setting(vsi);
4510                 i40e_config_qinq(hw, vsi);
4511         } else if (type == I40E_VSI_SRIOV) {
4512                 memset(&ctxt, 0, sizeof(ctxt));
4513                 /**
4514                  * For other VSI, the uplink_seid equals to uplink VSI's
4515                  * uplink_seid since they share same VEB
4516                  */
4517                 if (uplink_vsi == NULL)
4518                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4519                 else
4520                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4521                 ctxt.pf_num = hw->pf_id;
4522                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4523                 ctxt.uplink_seid = vsi->uplink_seid;
4524                 ctxt.connection_type = 0x1;
4525                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4526
4527                 /* Use the VEB configuration if FW >= v5.0 */
4528                 if (hw->aq.fw_maj_ver >= 5) {
4529                         /* Configure switch ID */
4530                         ctxt.info.valid_sections |=
4531                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4532                         ctxt.info.switch_id =
4533                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4534                 }
4535
4536                 /* Configure port/vlan */
4537                 ctxt.info.valid_sections |=
4538                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4539                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4540                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4541                                                 I40E_DEFAULT_TCMAP);
4542                 if (ret != I40E_SUCCESS) {
4543                         PMD_DRV_LOG(ERR, "Failed to configure "
4544                                     "TC queue mapping");
4545                         goto fail_msix_alloc;
4546                 }
4547                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4548                 ctxt.info.valid_sections |=
4549                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4550                 /**
4551                  * Since VSI is not created yet, only configure parameter,
4552                  * will add vsi below.
4553                  */
4554
4555                 i40e_config_qinq(hw, vsi);
4556         } else if (type == I40E_VSI_VMDQ2) {
4557                 memset(&ctxt, 0, sizeof(ctxt));
4558                 /*
4559                  * For other VSI, the uplink_seid equals to uplink VSI's
4560                  * uplink_seid since they share same VEB
4561                  */
4562                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4563                 ctxt.pf_num = hw->pf_id;
4564                 ctxt.vf_num = 0;
4565                 ctxt.uplink_seid = vsi->uplink_seid;
4566                 ctxt.connection_type = 0x1;
4567                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4568
4569                 ctxt.info.valid_sections |=
4570                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4571                 /* user_param carries flag to enable loop back */
4572                 if (user_param) {
4573                         ctxt.info.switch_id =
4574                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4575                         ctxt.info.switch_id |=
4576                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4577                 }
4578
4579                 /* Configure port/vlan */
4580                 ctxt.info.valid_sections |=
4581                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4582                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4583                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4584                                                 I40E_DEFAULT_TCMAP);
4585                 if (ret != I40E_SUCCESS) {
4586                         PMD_DRV_LOG(ERR, "Failed to configure "
4587                                         "TC queue mapping");
4588                         goto fail_msix_alloc;
4589                 }
4590                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4591                 ctxt.info.valid_sections |=
4592                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4593         } else if (type == I40E_VSI_FDIR) {
4594                 memset(&ctxt, 0, sizeof(ctxt));
4595                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4596                 ctxt.pf_num = hw->pf_id;
4597                 ctxt.vf_num = 0;
4598                 ctxt.uplink_seid = vsi->uplink_seid;
4599                 ctxt.connection_type = 0x1;     /* regular data port */
4600                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4601                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4602                                                 I40E_DEFAULT_TCMAP);
4603                 if (ret != I40E_SUCCESS) {
4604                         PMD_DRV_LOG(ERR, "Failed to configure "
4605                                         "TC queue mapping.");
4606                         goto fail_msix_alloc;
4607                 }
4608                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4609                 ctxt.info.valid_sections |=
4610                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4611         } else {
4612                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4613                 goto fail_msix_alloc;
4614         }
4615
4616         if (vsi->type != I40E_VSI_MAIN) {
4617                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4618                 if (ret != I40E_SUCCESS) {
4619                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4620                                     hw->aq.asq_last_status);
4621                         goto fail_msix_alloc;
4622                 }
4623                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4624                 vsi->info.valid_sections = 0;
4625                 vsi->seid = ctxt.seid;
4626                 vsi->vsi_id = ctxt.vsi_number;
4627                 vsi->sib_vsi_list.vsi = vsi;
4628                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4629                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4630                                           &vsi->sib_vsi_list, list);
4631                 } else {
4632                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4633                                           &vsi->sib_vsi_list, list);
4634                 }
4635         }
4636
4637         /* MAC/VLAN configuration */
4638         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4639         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4640
4641         ret = i40e_vsi_add_mac(vsi, &filter);
4642         if (ret != I40E_SUCCESS) {
4643                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4644                 goto fail_msix_alloc;
4645         }
4646
4647         /* Get VSI BW information */
4648         i40e_vsi_get_bw_config(vsi);
4649         return vsi;
4650 fail_msix_alloc:
4651         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4652 fail_queue_alloc:
4653         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4654 fail_mem:
4655         rte_free(vsi);
4656         return NULL;
4657 }
4658
4659 /* Configure vlan filter on or off */
4660 int
4661 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4662 {
4663         int i, num;
4664         struct i40e_mac_filter *f;
4665         void *temp;
4666         struct i40e_mac_filter_info *mac_filter;
4667         enum rte_mac_filter_type desired_filter;
4668         int ret = I40E_SUCCESS;
4669
4670         if (on) {
4671                 /* Filter to match MAC and VLAN */
4672                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4673         } else {
4674                 /* Filter to match only MAC */
4675                 desired_filter = RTE_MAC_PERFECT_MATCH;
4676         }
4677
4678         num = vsi->mac_num;
4679
4680         mac_filter = rte_zmalloc("mac_filter_info_data",
4681                                  num * sizeof(*mac_filter), 0);
4682         if (mac_filter == NULL) {
4683                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4684                 return I40E_ERR_NO_MEMORY;
4685         }
4686
4687         i = 0;
4688
4689         /* Remove all existing mac */
4690         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4691                 mac_filter[i] = f->mac_info;
4692                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4693                 if (ret) {
4694                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4695                                     on ? "enable" : "disable");
4696                         goto DONE;
4697                 }
4698                 i++;
4699         }
4700
4701         /* Override with new filter */
4702         for (i = 0; i < num; i++) {
4703                 mac_filter[i].filter_type = desired_filter;
4704                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4705                 if (ret) {
4706                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4707                                     on ? "enable" : "disable");
4708                         goto DONE;
4709                 }
4710         }
4711
4712 DONE:
4713         rte_free(mac_filter);
4714         return ret;
4715 }
4716
4717 /* Configure vlan stripping on or off */
4718 int
4719 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4720 {
4721         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4722         struct i40e_vsi_context ctxt;
4723         uint8_t vlan_flags;
4724         int ret = I40E_SUCCESS;
4725
4726         /* Check if it has been already on or off */
4727         if (vsi->info.valid_sections &
4728                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4729                 if (on) {
4730                         if ((vsi->info.port_vlan_flags &
4731                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4732                                 return 0; /* already on */
4733                 } else {
4734                         if ((vsi->info.port_vlan_flags &
4735                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4736                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4737                                 return 0; /* already off */
4738                 }
4739         }
4740
4741         if (on)
4742                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4743         else
4744                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4745         vsi->info.valid_sections =
4746                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4747         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4748         vsi->info.port_vlan_flags |= vlan_flags;
4749         ctxt.seid = vsi->seid;
4750         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4751         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4752         if (ret)
4753                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4754                             on ? "enable" : "disable");
4755
4756         return ret;
4757 }
4758
4759 static int
4760 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4761 {
4762         struct rte_eth_dev_data *data = dev->data;
4763         int ret;
4764         int mask = 0;
4765
4766         /* Apply vlan offload setting */
4767         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4768         i40e_vlan_offload_set(dev, mask);
4769
4770         /* Apply double-vlan setting, not implemented yet */
4771
4772         /* Apply pvid setting */
4773         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4774                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4775         if (ret)
4776                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4777
4778         return ret;
4779 }
4780
4781 static int
4782 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4783 {
4784         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4785
4786         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4787 }
4788
4789 static int
4790 i40e_update_flow_control(struct i40e_hw *hw)
4791 {
4792 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4793         struct i40e_link_status link_status;
4794         uint32_t rxfc = 0, txfc = 0, reg;
4795         uint8_t an_info;
4796         int ret;
4797
4798         memset(&link_status, 0, sizeof(link_status));
4799         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4800         if (ret != I40E_SUCCESS) {
4801                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4802                 goto write_reg; /* Disable flow control */
4803         }
4804
4805         an_info = hw->phy.link_info.an_info;
4806         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4807                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4808                 ret = I40E_ERR_NOT_READY;
4809                 goto write_reg; /* Disable flow control */
4810         }
4811         /**
4812          * If link auto negotiation is enabled, flow control needs to
4813          * be configured according to it
4814          */
4815         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4816         case I40E_LINK_PAUSE_RXTX:
4817                 rxfc = 1;
4818                 txfc = 1;
4819                 hw->fc.current_mode = I40E_FC_FULL;
4820                 break;
4821         case I40E_AQ_LINK_PAUSE_RX:
4822                 rxfc = 1;
4823                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4824                 break;
4825         case I40E_AQ_LINK_PAUSE_TX:
4826                 txfc = 1;
4827                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4828                 break;
4829         default:
4830                 hw->fc.current_mode = I40E_FC_NONE;
4831                 break;
4832         }
4833
4834 write_reg:
4835         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4836                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4837         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4838         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4839         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4840         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4841
4842         return ret;
4843 }
4844
4845 /* PF setup */
4846 static int
4847 i40e_pf_setup(struct i40e_pf *pf)
4848 {
4849         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4850         struct i40e_filter_control_settings settings;
4851         struct i40e_vsi *vsi;
4852         int ret;
4853
4854         /* Clear all stats counters */
4855         pf->offset_loaded = FALSE;
4856         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4857         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4858
4859         ret = i40e_pf_get_switch_config(pf);
4860         if (ret != I40E_SUCCESS) {
4861                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4862                 return ret;
4863         }
4864         if (pf->flags & I40E_FLAG_FDIR) {
4865                 /* make queue allocated first, let FDIR use queue pair 0*/
4866                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4867                 if (ret != I40E_FDIR_QUEUE_ID) {
4868                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4869                                     " ret =%d", ret);
4870                         pf->flags &= ~I40E_FLAG_FDIR;
4871                 }
4872         }
4873         /*  main VSI setup */
4874         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4875         if (!vsi) {
4876                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4877                 return I40E_ERR_NOT_READY;
4878         }
4879         pf->main_vsi = vsi;
4880
4881         /* Configure filter control */
4882         memset(&settings, 0, sizeof(settings));
4883         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4884                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4885         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4886                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4887         else {
4888                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4889                                                 hw->func_caps.rss_table_size);
4890                 return I40E_ERR_PARAM;
4891         }
4892         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4893                         "size: %u\n", hw->func_caps.rss_table_size);
4894         pf->hash_lut_size = hw->func_caps.rss_table_size;
4895
4896         /* Enable ethtype and macvlan filters */
4897         settings.enable_ethtype = TRUE;
4898         settings.enable_macvlan = TRUE;
4899         ret = i40e_set_filter_control(hw, &settings);
4900         if (ret)
4901                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4902                                                                 ret);
4903
4904         /* Update flow control according to the auto negotiation */
4905         i40e_update_flow_control(hw);
4906
4907         return I40E_SUCCESS;
4908 }
4909
4910 int
4911 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4912 {
4913         uint32_t reg;
4914         uint16_t j;
4915
4916         /**
4917          * Set or clear TX Queue Disable flags,
4918          * which is required by hardware.
4919          */
4920         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4921         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4922
4923         /* Wait until the request is finished */
4924         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4925                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4926                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4927                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4928                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4929                                                         & 0x1))) {
4930                         break;
4931                 }
4932         }
4933         if (on) {
4934                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4935                         return I40E_SUCCESS; /* already on, skip next steps */
4936
4937                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4938                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4939         } else {
4940                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4941                         return I40E_SUCCESS; /* already off, skip next steps */
4942                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4943         }
4944         /* Write the register */
4945         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4946         /* Check the result */
4947         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4948                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4949                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4950                 if (on) {
4951                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4952                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4953                                 break;
4954                 } else {
4955                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4956                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4957                                 break;
4958                 }
4959         }
4960         /* Check if it is timeout */
4961         if (j >= I40E_CHK_Q_ENA_COUNT) {
4962                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4963                             (on ? "enable" : "disable"), q_idx);
4964                 return I40E_ERR_TIMEOUT;
4965         }
4966
4967         return I40E_SUCCESS;
4968 }
4969
4970 /* Swith on or off the tx queues */
4971 static int
4972 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4973 {
4974         struct rte_eth_dev_data *dev_data = pf->dev_data;
4975         struct i40e_tx_queue *txq;
4976         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4977         uint16_t i;
4978         int ret;
4979
4980         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4981                 txq = dev_data->tx_queues[i];
4982                 /* Don't operate the queue if not configured or
4983                  * if starting only per queue */
4984                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4985                         continue;
4986                 if (on)
4987                         ret = i40e_dev_tx_queue_start(dev, i);
4988                 else
4989                         ret = i40e_dev_tx_queue_stop(dev, i);
4990                 if ( ret != I40E_SUCCESS)
4991                         return ret;
4992         }
4993
4994         return I40E_SUCCESS;
4995 }
4996
4997 int
4998 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4999 {
5000         uint32_t reg;
5001         uint16_t j;
5002
5003         /* Wait until the request is finished */
5004         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5005                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5006                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5007                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5008                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5009                         break;
5010         }
5011
5012         if (on) {
5013                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5014                         return I40E_SUCCESS; /* Already on, skip next steps */
5015                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5016         } else {
5017                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5018                         return I40E_SUCCESS; /* Already off, skip next steps */
5019                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5020         }
5021
5022         /* Write the register */
5023         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5024         /* Check the result */
5025         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5026                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5027                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5028                 if (on) {
5029                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5030                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5031                                 break;
5032                 } else {
5033                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5034                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5035                                 break;
5036                 }
5037         }
5038
5039         /* Check if it is timeout */
5040         if (j >= I40E_CHK_Q_ENA_COUNT) {
5041                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5042                             (on ? "enable" : "disable"), q_idx);
5043                 return I40E_ERR_TIMEOUT;
5044         }
5045
5046         return I40E_SUCCESS;
5047 }
5048 /* Switch on or off the rx queues */
5049 static int
5050 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5051 {
5052         struct rte_eth_dev_data *dev_data = pf->dev_data;
5053         struct i40e_rx_queue *rxq;
5054         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5055         uint16_t i;
5056         int ret;
5057
5058         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5059                 rxq = dev_data->rx_queues[i];
5060                 /* Don't operate the queue if not configured or
5061                  * if starting only per queue */
5062                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5063                         continue;
5064                 if (on)
5065                         ret = i40e_dev_rx_queue_start(dev, i);
5066                 else
5067                         ret = i40e_dev_rx_queue_stop(dev, i);
5068                 if (ret != I40E_SUCCESS)
5069                         return ret;
5070         }
5071
5072         return I40E_SUCCESS;
5073 }
5074
5075 /* Switch on or off all the rx/tx queues */
5076 int
5077 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5078 {
5079         int ret;
5080
5081         if (on) {
5082                 /* enable rx queues before enabling tx queues */
5083                 ret = i40e_dev_switch_rx_queues(pf, on);
5084                 if (ret) {
5085                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5086                         return ret;
5087                 }
5088                 ret = i40e_dev_switch_tx_queues(pf, on);
5089         } else {
5090                 /* Stop tx queues before stopping rx queues */
5091                 ret = i40e_dev_switch_tx_queues(pf, on);
5092                 if (ret) {
5093                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5094                         return ret;
5095                 }
5096                 ret = i40e_dev_switch_rx_queues(pf, on);
5097         }
5098
5099         return ret;
5100 }
5101
5102 /* Initialize VSI for TX */
5103 static int
5104 i40e_dev_tx_init(struct i40e_pf *pf)
5105 {
5106         struct rte_eth_dev_data *data = pf->dev_data;
5107         uint16_t i;
5108         uint32_t ret = I40E_SUCCESS;
5109         struct i40e_tx_queue *txq;
5110
5111         for (i = 0; i < data->nb_tx_queues; i++) {
5112                 txq = data->tx_queues[i];
5113                 if (!txq || !txq->q_set)
5114                         continue;
5115                 ret = i40e_tx_queue_init(txq);
5116                 if (ret != I40E_SUCCESS)
5117                         break;
5118         }
5119         if (ret == I40E_SUCCESS)
5120                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5121                                      ->eth_dev);
5122
5123         return ret;
5124 }
5125
5126 /* Initialize VSI for RX */
5127 static int
5128 i40e_dev_rx_init(struct i40e_pf *pf)
5129 {
5130         struct rte_eth_dev_data *data = pf->dev_data;
5131         int ret = I40E_SUCCESS;
5132         uint16_t i;
5133         struct i40e_rx_queue *rxq;
5134
5135         i40e_pf_config_mq_rx(pf);
5136         for (i = 0; i < data->nb_rx_queues; i++) {
5137                 rxq = data->rx_queues[i];
5138                 if (!rxq || !rxq->q_set)
5139                         continue;
5140
5141                 ret = i40e_rx_queue_init(rxq);
5142                 if (ret != I40E_SUCCESS) {
5143                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5144                                     "initialization");
5145                         break;
5146                 }
5147         }
5148         if (ret == I40E_SUCCESS)
5149                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5150                                      ->eth_dev);
5151
5152         return ret;
5153 }
5154
5155 static int
5156 i40e_dev_rxtx_init(struct i40e_pf *pf)
5157 {
5158         int err;
5159
5160         err = i40e_dev_tx_init(pf);
5161         if (err) {
5162                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5163                 return err;
5164         }
5165         err = i40e_dev_rx_init(pf);
5166         if (err) {
5167                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5168                 return err;
5169         }
5170
5171         return err;
5172 }
5173
5174 static int
5175 i40e_vmdq_setup(struct rte_eth_dev *dev)
5176 {
5177         struct rte_eth_conf *conf = &dev->data->dev_conf;
5178         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5179         int i, err, conf_vsis, j, loop;
5180         struct i40e_vsi *vsi;
5181         struct i40e_vmdq_info *vmdq_info;
5182         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5183         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5184
5185         /*
5186          * Disable interrupt to avoid message from VF. Furthermore, it will
5187          * avoid race condition in VSI creation/destroy.
5188          */
5189         i40e_pf_disable_irq0(hw);
5190
5191         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5192                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5193                 return -ENOTSUP;
5194         }
5195
5196         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5197         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5198                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5199                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5200                         pf->max_nb_vmdq_vsi);
5201                 return -ENOTSUP;
5202         }
5203
5204         if (pf->vmdq != NULL) {
5205                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5206                 return 0;
5207         }
5208
5209         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5210                                 sizeof(*vmdq_info) * conf_vsis, 0);
5211
5212         if (pf->vmdq == NULL) {
5213                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5214                 return -ENOMEM;
5215         }
5216
5217         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5218
5219         /* Create VMDQ VSI */
5220         for (i = 0; i < conf_vsis; i++) {
5221                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5222                                 vmdq_conf->enable_loop_back);
5223                 if (vsi == NULL) {
5224                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5225                         err = -1;
5226                         goto err_vsi_setup;
5227                 }
5228                 vmdq_info = &pf->vmdq[i];
5229                 vmdq_info->pf = pf;
5230                 vmdq_info->vsi = vsi;
5231         }
5232         pf->nb_cfg_vmdq_vsi = conf_vsis;
5233
5234         /* Configure Vlan */
5235         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5236         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5237                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5238                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5239                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5240                                         vmdq_conf->pool_map[i].vlan_id, j);
5241
5242                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5243                                                 vmdq_conf->pool_map[i].vlan_id);
5244                                 if (err) {
5245                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5246                                         err = -1;
5247                                         goto err_vsi_setup;
5248                                 }
5249                         }
5250                 }
5251         }
5252
5253         i40e_pf_enable_irq0(hw);
5254
5255         return 0;
5256
5257 err_vsi_setup:
5258         for (i = 0; i < conf_vsis; i++)
5259                 if (pf->vmdq[i].vsi == NULL)
5260                         break;
5261                 else
5262                         i40e_vsi_release(pf->vmdq[i].vsi);
5263
5264         rte_free(pf->vmdq);
5265         pf->vmdq = NULL;
5266         i40e_pf_enable_irq0(hw);
5267         return err;
5268 }
5269
5270 static void
5271 i40e_stat_update_32(struct i40e_hw *hw,
5272                    uint32_t reg,
5273                    bool offset_loaded,
5274                    uint64_t *offset,
5275                    uint64_t *stat)
5276 {
5277         uint64_t new_data;
5278
5279         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5280         if (!offset_loaded)
5281                 *offset = new_data;
5282
5283         if (new_data >= *offset)
5284                 *stat = (uint64_t)(new_data - *offset);
5285         else
5286                 *stat = (uint64_t)((new_data +
5287                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5288 }
5289
5290 static void
5291 i40e_stat_update_48(struct i40e_hw *hw,
5292                    uint32_t hireg,
5293                    uint32_t loreg,
5294                    bool offset_loaded,
5295                    uint64_t *offset,
5296                    uint64_t *stat)
5297 {
5298         uint64_t new_data;
5299
5300         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5301         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5302                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5303
5304         if (!offset_loaded)
5305                 *offset = new_data;
5306
5307         if (new_data >= *offset)
5308                 *stat = new_data - *offset;
5309         else
5310                 *stat = (uint64_t)((new_data +
5311                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5312
5313         *stat &= I40E_48_BIT_MASK;
5314 }
5315
5316 /* Disable IRQ0 */
5317 void
5318 i40e_pf_disable_irq0(struct i40e_hw *hw)
5319 {
5320         /* Disable all interrupt types */
5321         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5322         I40E_WRITE_FLUSH(hw);
5323 }
5324
5325 /* Enable IRQ0 */
5326 void
5327 i40e_pf_enable_irq0(struct i40e_hw *hw)
5328 {
5329         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5330                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5331                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5332                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5333         I40E_WRITE_FLUSH(hw);
5334 }
5335
5336 static void
5337 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5338 {
5339         /* read pending request and disable first */
5340         i40e_pf_disable_irq0(hw);
5341         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5342         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5343                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5344
5345         if (no_queue)
5346                 /* Link no queues with irq0 */
5347                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5348                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5349 }
5350
5351 static void
5352 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5353 {
5354         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5355         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5356         int i;
5357         uint16_t abs_vf_id;
5358         uint32_t index, offset, val;
5359
5360         if (!pf->vfs)
5361                 return;
5362         /**
5363          * Try to find which VF trigger a reset, use absolute VF id to access
5364          * since the reg is global register.
5365          */
5366         for (i = 0; i < pf->vf_num; i++) {
5367                 abs_vf_id = hw->func_caps.vf_base_id + i;
5368                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5369                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5370                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5371                 /* VFR event occured */
5372                 if (val & (0x1 << offset)) {
5373                         int ret;
5374
5375                         /* Clear the event first */
5376                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5377                                                         (0x1 << offset));
5378                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5379                         /**
5380                          * Only notify a VF reset event occured,
5381                          * don't trigger another SW reset
5382                          */
5383                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5384                         if (ret != I40E_SUCCESS)
5385                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5386                 }
5387         }
5388 }
5389
5390 static void
5391 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5392 {
5393         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5394         struct i40e_arq_event_info info;
5395         uint16_t pending, opcode;
5396         int ret;
5397
5398         info.buf_len = I40E_AQ_BUF_SZ;
5399         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5400         if (!info.msg_buf) {
5401                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5402                 return;
5403         }
5404
5405         pending = 1;
5406         while (pending) {
5407                 ret = i40e_clean_arq_element(hw, &info, &pending);
5408
5409                 if (ret != I40E_SUCCESS) {
5410                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5411                                     "aq_err: %u", hw->aq.asq_last_status);
5412                         break;
5413                 }
5414                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5415
5416                 switch (opcode) {
5417                 case i40e_aqc_opc_send_msg_to_pf:
5418                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5419                         i40e_pf_host_handle_vf_msg(dev,
5420                                         rte_le_to_cpu_16(info.desc.retval),
5421                                         rte_le_to_cpu_32(info.desc.cookie_high),
5422                                         rte_le_to_cpu_32(info.desc.cookie_low),
5423                                         info.msg_buf,
5424                                         info.msg_len);
5425                         break;
5426                 default:
5427                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5428                                     opcode);
5429                         break;
5430                 }
5431         }
5432         rte_free(info.msg_buf);
5433 }
5434
5435 /*
5436  * Interrupt handler is registered as the alarm callback for handling LSC
5437  * interrupt in a definite of time, in order to wait the NIC into a stable
5438  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5439  * no need for link down interrupt.
5440  */
5441 static void
5442 i40e_dev_interrupt_delayed_handler(void *param)
5443 {
5444         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5445         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5446         uint32_t icr0;
5447
5448         /* read interrupt causes again */
5449         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5450
5451 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5452         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5453                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5454         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5455                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5456         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5457                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5458         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5459                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5460         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5461                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5462                                                                 "state\n");
5463         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5464                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5465         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5466                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5467 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5468
5469         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5470                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5471                 i40e_dev_handle_vfr_event(dev);
5472         }
5473         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5474                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5475                 i40e_dev_handle_aq_msg(dev);
5476         }
5477
5478         /* handle the link up interrupt in an alarm callback */
5479         i40e_dev_link_update(dev, 0);
5480         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5481
5482         i40e_pf_enable_irq0(hw);
5483         rte_intr_enable(&(dev->pci_dev->intr_handle));
5484 }
5485
5486 /**
5487  * Interrupt handler triggered by NIC  for handling
5488  * specific interrupt.
5489  *
5490  * @param handle
5491  *  Pointer to interrupt handle.
5492  * @param param
5493  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5494  *
5495  * @return
5496  *  void
5497  */
5498 static void
5499 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5500                            void *param)
5501 {
5502         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5503         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5504         uint32_t icr0;
5505
5506         /* Disable interrupt */
5507         i40e_pf_disable_irq0(hw);
5508
5509         /* read out interrupt causes */
5510         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5511
5512         /* No interrupt event indicated */
5513         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5514                 PMD_DRV_LOG(INFO, "No interrupt event");
5515                 goto done;
5516         }
5517 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5518         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5519                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5520         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5521                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5522         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5523                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5524         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5525                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5526         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5527                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5528         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5529                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5530         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5531                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5532 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5533
5534         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5535                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5536                 i40e_dev_handle_vfr_event(dev);
5537         }
5538         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5539                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5540                 i40e_dev_handle_aq_msg(dev);
5541         }
5542
5543         /* Link Status Change interrupt */
5544         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5545 #define I40E_US_PER_SECOND 1000000
5546                 struct rte_eth_link link;
5547
5548                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5549                 memset(&link, 0, sizeof(link));
5550                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5551                 i40e_dev_link_update(dev, 0);
5552
5553                 /*
5554                  * For link up interrupt, it needs to wait 1 second to let the
5555                  * hardware be a stable state. Otherwise several consecutive
5556                  * interrupts can be observed.
5557                  * For link down interrupt, no need to wait.
5558                  */
5559                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5560                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5561                         return;
5562                 else
5563                         _rte_eth_dev_callback_process(dev,
5564                                 RTE_ETH_EVENT_INTR_LSC);
5565         }
5566
5567 done:
5568         /* Enable interrupt */
5569         i40e_pf_enable_irq0(hw);
5570         rte_intr_enable(&(dev->pci_dev->intr_handle));
5571 }
5572
5573 static int
5574 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5575                          struct i40e_macvlan_filter *filter,
5576                          int total)
5577 {
5578         int ele_num, ele_buff_size;
5579         int num, actual_num, i;
5580         uint16_t flags;
5581         int ret = I40E_SUCCESS;
5582         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5583         struct i40e_aqc_add_macvlan_element_data *req_list;
5584
5585         if (filter == NULL  || total == 0)
5586                 return I40E_ERR_PARAM;
5587         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5588         ele_buff_size = hw->aq.asq_buf_size;
5589
5590         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5591         if (req_list == NULL) {
5592                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5593                 return I40E_ERR_NO_MEMORY;
5594         }
5595
5596         num = 0;
5597         do {
5598                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5599                 memset(req_list, 0, ele_buff_size);
5600
5601                 for (i = 0; i < actual_num; i++) {
5602                         (void)rte_memcpy(req_list[i].mac_addr,
5603                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5604                         req_list[i].vlan_tag =
5605                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5606
5607                         switch (filter[num + i].filter_type) {
5608                         case RTE_MAC_PERFECT_MATCH:
5609                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5610                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5611                                 break;
5612                         case RTE_MACVLAN_PERFECT_MATCH:
5613                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5614                                 break;
5615                         case RTE_MAC_HASH_MATCH:
5616                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5617                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5618                                 break;
5619                         case RTE_MACVLAN_HASH_MATCH:
5620                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5621                                 break;
5622                         default:
5623                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5624                                 ret = I40E_ERR_PARAM;
5625                                 goto DONE;
5626                         }
5627
5628                         req_list[i].queue_number = 0;
5629
5630                         req_list[i].flags = rte_cpu_to_le_16(flags);
5631                 }
5632
5633                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5634                                                 actual_num, NULL);
5635                 if (ret != I40E_SUCCESS) {
5636                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5637                         goto DONE;
5638                 }
5639                 num += actual_num;
5640         } while (num < total);
5641
5642 DONE:
5643         rte_free(req_list);
5644         return ret;
5645 }
5646
5647 static int
5648 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5649                             struct i40e_macvlan_filter *filter,
5650                             int total)
5651 {
5652         int ele_num, ele_buff_size;
5653         int num, actual_num, i;
5654         uint16_t flags;
5655         int ret = I40E_SUCCESS;
5656         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5657         struct i40e_aqc_remove_macvlan_element_data *req_list;
5658
5659         if (filter == NULL  || total == 0)
5660                 return I40E_ERR_PARAM;
5661
5662         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5663         ele_buff_size = hw->aq.asq_buf_size;
5664
5665         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5666         if (req_list == NULL) {
5667                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5668                 return I40E_ERR_NO_MEMORY;
5669         }
5670
5671         num = 0;
5672         do {
5673                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5674                 memset(req_list, 0, ele_buff_size);
5675
5676                 for (i = 0; i < actual_num; i++) {
5677                         (void)rte_memcpy(req_list[i].mac_addr,
5678                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5679                         req_list[i].vlan_tag =
5680                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5681
5682                         switch (filter[num + i].filter_type) {
5683                         case RTE_MAC_PERFECT_MATCH:
5684                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5685                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5686                                 break;
5687                         case RTE_MACVLAN_PERFECT_MATCH:
5688                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5689                                 break;
5690                         case RTE_MAC_HASH_MATCH:
5691                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5692                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5693                                 break;
5694                         case RTE_MACVLAN_HASH_MATCH:
5695                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5696                                 break;
5697                         default:
5698                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5699                                 ret = I40E_ERR_PARAM;
5700                                 goto DONE;
5701                         }
5702                         req_list[i].flags = rte_cpu_to_le_16(flags);
5703                 }
5704
5705                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5706                                                 actual_num, NULL);
5707                 if (ret != I40E_SUCCESS) {
5708                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5709                         goto DONE;
5710                 }
5711                 num += actual_num;
5712         } while (num < total);
5713
5714 DONE:
5715         rte_free(req_list);
5716         return ret;
5717 }
5718
5719 /* Find out specific MAC filter */
5720 static struct i40e_mac_filter *
5721 i40e_find_mac_filter(struct i40e_vsi *vsi,
5722                          struct ether_addr *macaddr)
5723 {
5724         struct i40e_mac_filter *f;
5725
5726         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5727                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5728                         return f;
5729         }
5730
5731         return NULL;
5732 }
5733
5734 static bool
5735 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5736                          uint16_t vlan_id)
5737 {
5738         uint32_t vid_idx, vid_bit;
5739
5740         if (vlan_id > ETH_VLAN_ID_MAX)
5741                 return 0;
5742
5743         vid_idx = I40E_VFTA_IDX(vlan_id);
5744         vid_bit = I40E_VFTA_BIT(vlan_id);
5745
5746         if (vsi->vfta[vid_idx] & vid_bit)
5747                 return 1;
5748         else
5749                 return 0;
5750 }
5751
5752 static void
5753 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5754                          uint16_t vlan_id, bool on)
5755 {
5756         uint32_t vid_idx, vid_bit;
5757
5758         if (vlan_id > ETH_VLAN_ID_MAX)
5759                 return;
5760
5761         vid_idx = I40E_VFTA_IDX(vlan_id);
5762         vid_bit = I40E_VFTA_BIT(vlan_id);
5763
5764         if (on)
5765                 vsi->vfta[vid_idx] |= vid_bit;
5766         else
5767                 vsi->vfta[vid_idx] &= ~vid_bit;
5768 }
5769
5770 /**
5771  * Find all vlan options for specific mac addr,
5772  * return with actual vlan found.
5773  */
5774 static inline int
5775 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5776                            struct i40e_macvlan_filter *mv_f,
5777                            int num, struct ether_addr *addr)
5778 {
5779         int i;
5780         uint32_t j, k;
5781
5782         /**
5783          * Not to use i40e_find_vlan_filter to decrease the loop time,
5784          * although the code looks complex.
5785           */
5786         if (num < vsi->vlan_num)
5787                 return I40E_ERR_PARAM;
5788
5789         i = 0;
5790         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5791                 if (vsi->vfta[j]) {
5792                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5793                                 if (vsi->vfta[j] & (1 << k)) {
5794                                         if (i > num - 1) {
5795                                                 PMD_DRV_LOG(ERR, "vlan number "
5796                                                             "not match");
5797                                                 return I40E_ERR_PARAM;
5798                                         }
5799                                         (void)rte_memcpy(&mv_f[i].macaddr,
5800                                                         addr, ETH_ADDR_LEN);
5801                                         mv_f[i].vlan_id =
5802                                                 j * I40E_UINT32_BIT_SIZE + k;
5803                                         i++;
5804                                 }
5805                         }
5806                 }
5807         }
5808         return I40E_SUCCESS;
5809 }
5810
5811 static inline int
5812 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5813                            struct i40e_macvlan_filter *mv_f,
5814                            int num,
5815                            uint16_t vlan)
5816 {
5817         int i = 0;
5818         struct i40e_mac_filter *f;
5819
5820         if (num < vsi->mac_num)
5821                 return I40E_ERR_PARAM;
5822
5823         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5824                 if (i > num - 1) {
5825                         PMD_DRV_LOG(ERR, "buffer number not match");
5826                         return I40E_ERR_PARAM;
5827                 }
5828                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5829                                 ETH_ADDR_LEN);
5830                 mv_f[i].vlan_id = vlan;
5831                 mv_f[i].filter_type = f->mac_info.filter_type;
5832                 i++;
5833         }
5834
5835         return I40E_SUCCESS;
5836 }
5837
5838 static int
5839 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5840 {
5841         int i, num;
5842         struct i40e_mac_filter *f;
5843         struct i40e_macvlan_filter *mv_f;
5844         int ret = I40E_SUCCESS;
5845
5846         if (vsi == NULL || vsi->mac_num == 0)
5847                 return I40E_ERR_PARAM;
5848
5849         /* Case that no vlan is set */
5850         if (vsi->vlan_num == 0)
5851                 num = vsi->mac_num;
5852         else
5853                 num = vsi->mac_num * vsi->vlan_num;
5854
5855         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5856         if (mv_f == NULL) {
5857                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5858                 return I40E_ERR_NO_MEMORY;
5859         }
5860
5861         i = 0;
5862         if (vsi->vlan_num == 0) {
5863                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5864                         (void)rte_memcpy(&mv_f[i].macaddr,
5865                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5866                         mv_f[i].vlan_id = 0;
5867                         i++;
5868                 }
5869         } else {
5870                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5871                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5872                                         vsi->vlan_num, &f->mac_info.mac_addr);
5873                         if (ret != I40E_SUCCESS)
5874                                 goto DONE;
5875                         i += vsi->vlan_num;
5876                 }
5877         }
5878
5879         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5880 DONE:
5881         rte_free(mv_f);
5882
5883         return ret;
5884 }
5885
5886 int
5887 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5888 {
5889         struct i40e_macvlan_filter *mv_f;
5890         int mac_num;
5891         int ret = I40E_SUCCESS;
5892
5893         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5894                 return I40E_ERR_PARAM;
5895
5896         /* If it's already set, just return */
5897         if (i40e_find_vlan_filter(vsi,vlan))
5898                 return I40E_SUCCESS;
5899
5900         mac_num = vsi->mac_num;
5901
5902         if (mac_num == 0) {
5903                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5904                 return I40E_ERR_PARAM;
5905         }
5906
5907         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5908
5909         if (mv_f == NULL) {
5910                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5911                 return I40E_ERR_NO_MEMORY;
5912         }
5913
5914         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5915
5916         if (ret != I40E_SUCCESS)
5917                 goto DONE;
5918
5919         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5920
5921         if (ret != I40E_SUCCESS)
5922                 goto DONE;
5923
5924         i40e_set_vlan_filter(vsi, vlan, 1);
5925
5926         vsi->vlan_num++;
5927         ret = I40E_SUCCESS;
5928 DONE:
5929         rte_free(mv_f);
5930         return ret;
5931 }
5932
5933 int
5934 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5935 {
5936         struct i40e_macvlan_filter *mv_f;
5937         int mac_num;
5938         int ret = I40E_SUCCESS;
5939
5940         /**
5941          * Vlan 0 is the generic filter for untagged packets
5942          * and can't be removed.
5943          */
5944         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5945                 return I40E_ERR_PARAM;
5946
5947         /* If can't find it, just return */
5948         if (!i40e_find_vlan_filter(vsi, vlan))
5949                 return I40E_ERR_PARAM;
5950
5951         mac_num = vsi->mac_num;
5952
5953         if (mac_num == 0) {
5954                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5955                 return I40E_ERR_PARAM;
5956         }
5957
5958         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5959
5960         if (mv_f == NULL) {
5961                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5962                 return I40E_ERR_NO_MEMORY;
5963         }
5964
5965         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5966
5967         if (ret != I40E_SUCCESS)
5968                 goto DONE;
5969
5970         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5971
5972         if (ret != I40E_SUCCESS)
5973                 goto DONE;
5974
5975         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5976         if (vsi->vlan_num == 1) {
5977                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5978                 if (ret != I40E_SUCCESS)
5979                         goto DONE;
5980
5981                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5982                 if (ret != I40E_SUCCESS)
5983                         goto DONE;
5984         }
5985
5986         i40e_set_vlan_filter(vsi, vlan, 0);
5987
5988         vsi->vlan_num--;
5989         ret = I40E_SUCCESS;
5990 DONE:
5991         rte_free(mv_f);
5992         return ret;
5993 }
5994
5995 int
5996 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5997 {
5998         struct i40e_mac_filter *f;
5999         struct i40e_macvlan_filter *mv_f;
6000         int i, vlan_num = 0;
6001         int ret = I40E_SUCCESS;
6002
6003         /* If it's add and we've config it, return */
6004         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6005         if (f != NULL)
6006                 return I40E_SUCCESS;
6007         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6008                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6009
6010                 /**
6011                  * If vlan_num is 0, that's the first time to add mac,
6012                  * set mask for vlan_id 0.
6013                  */
6014                 if (vsi->vlan_num == 0) {
6015                         i40e_set_vlan_filter(vsi, 0, 1);
6016                         vsi->vlan_num = 1;
6017                 }
6018                 vlan_num = vsi->vlan_num;
6019         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6020                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6021                 vlan_num = 1;
6022
6023         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6024         if (mv_f == NULL) {
6025                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6026                 return I40E_ERR_NO_MEMORY;
6027         }
6028
6029         for (i = 0; i < vlan_num; i++) {
6030                 mv_f[i].filter_type = mac_filter->filter_type;
6031                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6032                                 ETH_ADDR_LEN);
6033         }
6034
6035         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6036                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6037                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6038                                         &mac_filter->mac_addr);
6039                 if (ret != I40E_SUCCESS)
6040                         goto DONE;
6041         }
6042
6043         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6044         if (ret != I40E_SUCCESS)
6045                 goto DONE;
6046
6047         /* Add the mac addr into mac list */
6048         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6049         if (f == NULL) {
6050                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6051                 ret = I40E_ERR_NO_MEMORY;
6052                 goto DONE;
6053         }
6054         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6055                         ETH_ADDR_LEN);
6056         f->mac_info.filter_type = mac_filter->filter_type;
6057         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6058         vsi->mac_num++;
6059
6060         ret = I40E_SUCCESS;
6061 DONE:
6062         rte_free(mv_f);
6063
6064         return ret;
6065 }
6066
6067 int
6068 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6069 {
6070         struct i40e_mac_filter *f;
6071         struct i40e_macvlan_filter *mv_f;
6072         int i, vlan_num;
6073         enum rte_mac_filter_type filter_type;
6074         int ret = I40E_SUCCESS;
6075
6076         /* Can't find it, return an error */
6077         f = i40e_find_mac_filter(vsi, addr);
6078         if (f == NULL)
6079                 return I40E_ERR_PARAM;
6080
6081         vlan_num = vsi->vlan_num;
6082         filter_type = f->mac_info.filter_type;
6083         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6084                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6085                 if (vlan_num == 0) {
6086                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6087                         return I40E_ERR_PARAM;
6088                 }
6089         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6090                         filter_type == RTE_MAC_HASH_MATCH)
6091                 vlan_num = 1;
6092
6093         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6094         if (mv_f == NULL) {
6095                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6096                 return I40E_ERR_NO_MEMORY;
6097         }
6098
6099         for (i = 0; i < vlan_num; i++) {
6100                 mv_f[i].filter_type = filter_type;
6101                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6102                                 ETH_ADDR_LEN);
6103         }
6104         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6105                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6106                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6107                 if (ret != I40E_SUCCESS)
6108                         goto DONE;
6109         }
6110
6111         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6112         if (ret != I40E_SUCCESS)
6113                 goto DONE;
6114
6115         /* Remove the mac addr into mac list */
6116         TAILQ_REMOVE(&vsi->mac_list, f, next);
6117         rte_free(f);
6118         vsi->mac_num--;
6119
6120         ret = I40E_SUCCESS;
6121 DONE:
6122         rte_free(mv_f);
6123         return ret;
6124 }
6125
6126 /* Configure hash enable flags for RSS */
6127 uint64_t
6128 i40e_config_hena(uint64_t flags)
6129 {
6130         uint64_t hena = 0;
6131
6132         if (!flags)
6133                 return hena;
6134
6135         if (flags & ETH_RSS_FRAG_IPV4)
6136                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6137         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
6138                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6139         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
6140                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6141         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6142                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6143         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6144                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6145         if (flags & ETH_RSS_FRAG_IPV6)
6146                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6147         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
6148                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6149         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
6150                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6151         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6152                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6153         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6154                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6155         if (flags & ETH_RSS_L2_PAYLOAD)
6156                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6157
6158         return hena;
6159 }
6160
6161 /* Parse the hash enable flags */
6162 uint64_t
6163 i40e_parse_hena(uint64_t flags)
6164 {
6165         uint64_t rss_hf = 0;
6166
6167         if (!flags)
6168                 return rss_hf;
6169         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6170                 rss_hf |= ETH_RSS_FRAG_IPV4;
6171         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6172                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6173         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6174                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6175         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6176                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6177         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6178                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6179         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6180                 rss_hf |= ETH_RSS_FRAG_IPV6;
6181         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6182                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6183         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6184                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6185         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6186                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6187         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6188                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6189         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6190                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6191
6192         return rss_hf;
6193 }
6194
6195 /* Disable RSS */
6196 static void
6197 i40e_pf_disable_rss(struct i40e_pf *pf)
6198 {
6199         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6200         uint64_t hena;
6201
6202         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6203         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6204         hena &= ~I40E_RSS_HENA_ALL;
6205         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6206         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6207         I40E_WRITE_FLUSH(hw);
6208 }
6209
6210 static int
6211 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6212 {
6213         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6214         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6215         int ret = 0;
6216
6217         if (!key || key_len == 0) {
6218                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6219                 return 0;
6220         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6221                 sizeof(uint32_t)) {
6222                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6223                 return -EINVAL;
6224         }
6225
6226         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6227                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6228                         (struct i40e_aqc_get_set_rss_key_data *)key;
6229
6230                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6231                 if (ret)
6232                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6233                                      "via AQ");
6234         } else {
6235                 uint32_t *hash_key = (uint32_t *)key;
6236                 uint16_t i;
6237
6238                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6239                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6240                 I40E_WRITE_FLUSH(hw);
6241         }
6242
6243         return ret;
6244 }
6245
6246 static int
6247 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6248 {
6249         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6250         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6251         int ret;
6252
6253         if (!key || !key_len)
6254                 return -EINVAL;
6255
6256         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6257                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6258                         (struct i40e_aqc_get_set_rss_key_data *)key);
6259                 if (ret) {
6260                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6261                         return ret;
6262                 }
6263         } else {
6264                 uint32_t *key_dw = (uint32_t *)key;
6265                 uint16_t i;
6266
6267                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6268                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6269         }
6270         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6271
6272         return 0;
6273 }
6274
6275 static int
6276 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6277 {
6278         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6279         uint64_t rss_hf;
6280         uint64_t hena;
6281         int ret;
6282
6283         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6284                                rss_conf->rss_key_len);
6285         if (ret)
6286                 return ret;
6287
6288         rss_hf = rss_conf->rss_hf;
6289         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6290         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6291         hena &= ~I40E_RSS_HENA_ALL;
6292         hena |= i40e_config_hena(rss_hf);
6293         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6294         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6295         I40E_WRITE_FLUSH(hw);
6296
6297         return 0;
6298 }
6299
6300 static int
6301 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6302                          struct rte_eth_rss_conf *rss_conf)
6303 {
6304         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6305         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6306         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6307         uint64_t hena;
6308
6309         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6310         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6311         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6312                 if (rss_hf != 0) /* Enable RSS */
6313                         return -EINVAL;
6314                 return 0; /* Nothing to do */
6315         }
6316         /* RSS enabled */
6317         if (rss_hf == 0) /* Disable RSS */
6318                 return -EINVAL;
6319
6320         return i40e_hw_rss_hash_set(pf, rss_conf);
6321 }
6322
6323 static int
6324 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6325                            struct rte_eth_rss_conf *rss_conf)
6326 {
6327         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6328         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6329         uint64_t hena;
6330
6331         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6332                          &rss_conf->rss_key_len);
6333
6334         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6335         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6336         rss_conf->rss_hf = i40e_parse_hena(hena);
6337
6338         return 0;
6339 }
6340
6341 static int
6342 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6343 {
6344         switch (filter_type) {
6345         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6346                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6347                 break;
6348         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6349                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6350                 break;
6351         case RTE_TUNNEL_FILTER_IMAC_TENID:
6352                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6353                 break;
6354         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6355                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6356                 break;
6357         case ETH_TUNNEL_FILTER_IMAC:
6358                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6359                 break;
6360         case ETH_TUNNEL_FILTER_OIP:
6361                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6362                 break;
6363         case ETH_TUNNEL_FILTER_IIP:
6364                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6365                 break;
6366         default:
6367                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6368                 return -EINVAL;
6369         }
6370
6371         return 0;
6372 }
6373
6374 static int
6375 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6376                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6377                         uint8_t add)
6378 {
6379         uint16_t ip_type;
6380         uint32_t ipv4_addr;
6381         uint8_t i, tun_type = 0;
6382         /* internal varialbe to convert ipv6 byte order */
6383         uint32_t convert_ipv6[4];
6384         int val, ret = 0;
6385         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6386         struct i40e_vsi *vsi = pf->main_vsi;
6387         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6388         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6389
6390         cld_filter = rte_zmalloc("tunnel_filter",
6391                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6392                 0);
6393
6394         if (NULL == cld_filter) {
6395                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6396                 return -EINVAL;
6397         }
6398         pfilter = cld_filter;
6399
6400         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6401         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6402
6403         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6404         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6405                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6406                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6407                 rte_memcpy(&pfilter->ipaddr.v4.data,
6408                                 &rte_cpu_to_le_32(ipv4_addr),
6409                                 sizeof(pfilter->ipaddr.v4.data));
6410         } else {
6411                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6412                 for (i = 0; i < 4; i++) {
6413                         convert_ipv6[i] =
6414                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6415                 }
6416                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6417                                 sizeof(pfilter->ipaddr.v6.data));
6418         }
6419
6420         /* check tunneled type */
6421         switch (tunnel_filter->tunnel_type) {
6422         case RTE_TUNNEL_TYPE_VXLAN:
6423                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6424                 break;
6425         case RTE_TUNNEL_TYPE_NVGRE:
6426                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6427                 break;
6428         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6429                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6430                 break;
6431         default:
6432                 /* Other tunnel types is not supported. */
6433                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6434                 rte_free(cld_filter);
6435                 return -EINVAL;
6436         }
6437
6438         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6439                                                 &pfilter->flags);
6440         if (val < 0) {
6441                 rte_free(cld_filter);
6442                 return -EINVAL;
6443         }
6444
6445         pfilter->flags |= rte_cpu_to_le_16(
6446                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6447                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6448         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6449         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6450
6451         if (add)
6452                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6453         else
6454                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6455                                                 cld_filter, 1);
6456
6457         rte_free(cld_filter);
6458         return ret;
6459 }
6460
6461 static int
6462 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6463 {
6464         uint8_t i;
6465
6466         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6467                 if (pf->vxlan_ports[i] == port)
6468                         return i;
6469         }
6470
6471         return -1;
6472 }
6473
6474 static int
6475 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6476 {
6477         int  idx, ret;
6478         uint8_t filter_idx;
6479         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6480
6481         idx = i40e_get_vxlan_port_idx(pf, port);
6482
6483         /* Check if port already exists */
6484         if (idx >= 0) {
6485                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6486                 return -EINVAL;
6487         }
6488
6489         /* Now check if there is space to add the new port */
6490         idx = i40e_get_vxlan_port_idx(pf, 0);
6491         if (idx < 0) {
6492                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6493                         "not adding port %d", port);
6494                 return -ENOSPC;
6495         }
6496
6497         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6498                                         &filter_idx, NULL);
6499         if (ret < 0) {
6500                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6501                 return -1;
6502         }
6503
6504         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6505                          port,  filter_idx);
6506
6507         /* New port: add it and mark its index in the bitmap */
6508         pf->vxlan_ports[idx] = port;
6509         pf->vxlan_bitmap |= (1 << idx);
6510
6511         if (!(pf->flags & I40E_FLAG_VXLAN))
6512                 pf->flags |= I40E_FLAG_VXLAN;
6513
6514         return 0;
6515 }
6516
6517 static int
6518 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6519 {
6520         int idx;
6521         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6522
6523         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6524                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6525                 return -EINVAL;
6526         }
6527
6528         idx = i40e_get_vxlan_port_idx(pf, port);
6529
6530         if (idx < 0) {
6531                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6532                 return -EINVAL;
6533         }
6534
6535         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6536                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6537                 return -1;
6538         }
6539
6540         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6541                         port, idx);
6542
6543         pf->vxlan_ports[idx] = 0;
6544         pf->vxlan_bitmap &= ~(1 << idx);
6545
6546         if (!pf->vxlan_bitmap)
6547                 pf->flags &= ~I40E_FLAG_VXLAN;
6548
6549         return 0;
6550 }
6551
6552 /* Add UDP tunneling port */
6553 static int
6554 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6555                              struct rte_eth_udp_tunnel *udp_tunnel)
6556 {
6557         int ret = 0;
6558         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6559
6560         if (udp_tunnel == NULL)
6561                 return -EINVAL;
6562
6563         switch (udp_tunnel->prot_type) {
6564         case RTE_TUNNEL_TYPE_VXLAN:
6565                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6566                 break;
6567
6568         case RTE_TUNNEL_TYPE_GENEVE:
6569         case RTE_TUNNEL_TYPE_TEREDO:
6570                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6571                 ret = -1;
6572                 break;
6573
6574         default:
6575                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6576                 ret = -1;
6577                 break;
6578         }
6579
6580         return ret;
6581 }
6582
6583 /* Remove UDP tunneling port */
6584 static int
6585 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6586                              struct rte_eth_udp_tunnel *udp_tunnel)
6587 {
6588         int ret = 0;
6589         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6590
6591         if (udp_tunnel == NULL)
6592                 return -EINVAL;
6593
6594         switch (udp_tunnel->prot_type) {
6595         case RTE_TUNNEL_TYPE_VXLAN:
6596                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6597                 break;
6598         case RTE_TUNNEL_TYPE_GENEVE:
6599         case RTE_TUNNEL_TYPE_TEREDO:
6600                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6601                 ret = -1;
6602                 break;
6603         default:
6604                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6605                 ret = -1;
6606                 break;
6607         }
6608
6609         return ret;
6610 }
6611
6612 /* Calculate the maximum number of contiguous PF queues that are configured */
6613 static int
6614 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6615 {
6616         struct rte_eth_dev_data *data = pf->dev_data;
6617         int i, num;
6618         struct i40e_rx_queue *rxq;
6619
6620         num = 0;
6621         for (i = 0; i < pf->lan_nb_qps; i++) {
6622                 rxq = data->rx_queues[i];
6623                 if (rxq && rxq->q_set)
6624                         num++;
6625                 else
6626                         break;
6627         }
6628
6629         return num;
6630 }
6631
6632 /* Configure RSS */
6633 static int
6634 i40e_pf_config_rss(struct i40e_pf *pf)
6635 {
6636         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6637         struct rte_eth_rss_conf rss_conf;
6638         uint32_t i, lut = 0;
6639         uint16_t j, num;
6640
6641         /*
6642          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6643          * It's necessary to calulate the actual PF queues that are configured.
6644          */
6645         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6646                 num = i40e_pf_calc_configured_queues_num(pf);
6647         else
6648                 num = pf->dev_data->nb_rx_queues;
6649
6650         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6651         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6652                         num);
6653
6654         if (num == 0) {
6655                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6656                 return -ENOTSUP;
6657         }
6658
6659         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6660                 if (j == num)
6661                         j = 0;
6662                 lut = (lut << 8) | (j & ((0x1 <<
6663                         hw->func_caps.rss_table_entry_width) - 1));
6664                 if ((i & 3) == 3)
6665                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6666         }
6667
6668         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6669         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6670                 i40e_pf_disable_rss(pf);
6671                 return 0;
6672         }
6673         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6674                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6675                 /* Random default keys */
6676                 static uint32_t rss_key_default[] = {0x6b793944,
6677                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6678                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6679                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6680
6681                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6682                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6683                                                         sizeof(uint32_t);
6684         }
6685
6686         return i40e_hw_rss_hash_set(pf, &rss_conf);
6687 }
6688
6689 static int
6690 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6691                                struct rte_eth_tunnel_filter_conf *filter)
6692 {
6693         if (pf == NULL || filter == NULL) {
6694                 PMD_DRV_LOG(ERR, "Invalid parameter");
6695                 return -EINVAL;
6696         }
6697
6698         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6699                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6700                 return -EINVAL;
6701         }
6702
6703         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6704                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6705                 return -EINVAL;
6706         }
6707
6708         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6709                 (is_zero_ether_addr(&filter->outer_mac))) {
6710                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6711                 return -EINVAL;
6712         }
6713
6714         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6715                 (is_zero_ether_addr(&filter->inner_mac))) {
6716                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6717                 return -EINVAL;
6718         }
6719
6720         return 0;
6721 }
6722
6723 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6724 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6725 static int
6726 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6727 {
6728         uint32_t val, reg;
6729         int ret = -EINVAL;
6730
6731         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6732         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6733
6734         if (len == 3) {
6735                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6736         } else if (len == 4) {
6737                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6738         } else {
6739                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6740                 return ret;
6741         }
6742
6743         if (reg != val) {
6744                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6745                                                    reg, NULL);
6746                 if (ret != 0)
6747                         return ret;
6748         } else {
6749                 ret = 0;
6750         }
6751         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6752                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6753
6754         return ret;
6755 }
6756
6757 static int
6758 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6759 {
6760         int ret = -EINVAL;
6761
6762         if (!hw || !cfg)
6763                 return -EINVAL;
6764
6765         switch (cfg->cfg_type) {
6766         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6767                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6768                 break;
6769         default:
6770                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6771                 break;
6772         }
6773
6774         return ret;
6775 }
6776
6777 static int
6778 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6779                                enum rte_filter_op filter_op,
6780                                void *arg)
6781 {
6782         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6783         int ret = I40E_ERR_PARAM;
6784
6785         switch (filter_op) {
6786         case RTE_ETH_FILTER_SET:
6787                 ret = i40e_dev_global_config_set(hw,
6788                         (struct rte_eth_global_cfg *)arg);
6789                 break;
6790         default:
6791                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6792                 break;
6793         }
6794
6795         return ret;
6796 }
6797
6798 static int
6799 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6800                           enum rte_filter_op filter_op,
6801                           void *arg)
6802 {
6803         struct rte_eth_tunnel_filter_conf *filter;
6804         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6805         int ret = I40E_SUCCESS;
6806
6807         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6808
6809         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6810                 return I40E_ERR_PARAM;
6811
6812         switch (filter_op) {
6813         case RTE_ETH_FILTER_NOP:
6814                 if (!(pf->flags & I40E_FLAG_VXLAN))
6815                         ret = I40E_NOT_SUPPORTED;
6816                 break;
6817         case RTE_ETH_FILTER_ADD:
6818                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6819                 break;
6820         case RTE_ETH_FILTER_DELETE:
6821                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6822                 break;
6823         default:
6824                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6825                 ret = I40E_ERR_PARAM;
6826                 break;
6827         }
6828
6829         return ret;
6830 }
6831
6832 static int
6833 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6834 {
6835         int ret = 0;
6836         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6837
6838         /* RSS setup */
6839         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6840                 ret = i40e_pf_config_rss(pf);
6841         else
6842                 i40e_pf_disable_rss(pf);
6843
6844         return ret;
6845 }
6846
6847 /* Get the symmetric hash enable configurations per port */
6848 static void
6849 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6850 {
6851         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6852
6853         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6854 }
6855
6856 /* Set the symmetric hash enable configurations per port */
6857 static void
6858 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6859 {
6860         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6861
6862         if (enable > 0) {
6863                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6864                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6865                                                         "been enabled");
6866                         return;
6867                 }
6868                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6869         } else {
6870                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6871                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6872                                                         "been disabled");
6873                         return;
6874                 }
6875                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6876         }
6877         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6878         I40E_WRITE_FLUSH(hw);
6879 }
6880
6881 /*
6882  * Get global configurations of hash function type and symmetric hash enable
6883  * per flow type (pctype). Note that global configuration means it affects all
6884  * the ports on the same NIC.
6885  */
6886 static int
6887 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6888                                    struct rte_eth_hash_global_conf *g_cfg)
6889 {
6890         uint32_t reg, mask = I40E_FLOW_TYPES;
6891         uint16_t i;
6892         enum i40e_filter_pctype pctype;
6893
6894         memset(g_cfg, 0, sizeof(*g_cfg));
6895         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6896         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6897                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6898         else
6899                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6900         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6901                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6902
6903         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6904                 if (!(mask & (1UL << i)))
6905                         continue;
6906                 mask &= ~(1UL << i);
6907                 /* Bit set indicats the coresponding flow type is supported */
6908                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6909                 /* if flowtype is invalid, continue */
6910                 if (!I40E_VALID_FLOW(i))
6911                         continue;
6912                 pctype = i40e_flowtype_to_pctype(i);
6913                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6914                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6915                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6916         }
6917
6918         return 0;
6919 }
6920
6921 static int
6922 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6923 {
6924         uint32_t i;
6925         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6926
6927         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6928                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6929                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6930                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6931                                                 g_cfg->hash_func);
6932                 return -EINVAL;
6933         }
6934
6935         /*
6936          * As i40e supports less than 32 flow types, only first 32 bits need to
6937          * be checked.
6938          */
6939         mask0 = g_cfg->valid_bit_mask[0];
6940         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6941                 if (i == 0) {
6942                         /* Check if any unsupported flow type configured */
6943                         if ((mask0 | i40e_mask) ^ i40e_mask)
6944                                 goto mask_err;
6945                 } else {
6946                         if (g_cfg->valid_bit_mask[i])
6947                                 goto mask_err;
6948                 }
6949         }
6950
6951         return 0;
6952
6953 mask_err:
6954         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6955
6956         return -EINVAL;
6957 }
6958
6959 /*
6960  * Set global configurations of hash function type and symmetric hash enable
6961  * per flow type (pctype). Note any modifying global configuration will affect
6962  * all the ports on the same NIC.
6963  */
6964 static int
6965 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6966                                    struct rte_eth_hash_global_conf *g_cfg)
6967 {
6968         int ret;
6969         uint16_t i;
6970         uint32_t reg;
6971         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6972         enum i40e_filter_pctype pctype;
6973
6974         /* Check the input parameters */
6975         ret = i40e_hash_global_config_check(g_cfg);
6976         if (ret < 0)
6977                 return ret;
6978
6979         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6980                 if (!(mask0 & (1UL << i)))
6981                         continue;
6982                 mask0 &= ~(1UL << i);
6983                 /* if flowtype is invalid, continue */
6984                 if (!I40E_VALID_FLOW(i))
6985                         continue;
6986                 pctype = i40e_flowtype_to_pctype(i);
6987                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6988                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6989                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6990         }
6991
6992         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6993         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6994                 /* Toeplitz */
6995                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6996                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6997                                                                 "Toeplitz");
6998                         goto out;
6999                 }
7000                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7001         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7002                 /* Simple XOR */
7003                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7004                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7005                                                         "Simple XOR");
7006                         goto out;
7007                 }
7008                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7009         } else
7010                 /* Use the default, and keep it as it is */
7011                 goto out;
7012
7013         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7014
7015 out:
7016         I40E_WRITE_FLUSH(hw);
7017
7018         return 0;
7019 }
7020
7021 /**
7022  * Valid input sets for hash and flow director filters per PCTYPE
7023  */
7024 static uint64_t
7025 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7026                 enum rte_filter_type filter)
7027 {
7028         uint64_t valid;
7029
7030         static const uint64_t valid_hash_inset_table[] = {
7031                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7032                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7033                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7034                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7035                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7036                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7037                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7038                         I40E_INSET_FLEX_PAYLOAD,
7039                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7040                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7041                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7042                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7043                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7044                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7045                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7046                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7047                         I40E_INSET_FLEX_PAYLOAD,
7048                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7049                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7050                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7051                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7052                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7053                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7054                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7055                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7056                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7057                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7058                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7059                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7060                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7061                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7062                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7063                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7064                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7065                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7066                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7067                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7068                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7069                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7070                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7071                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7072                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7073                         I40E_INSET_FLEX_PAYLOAD,
7074                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7075                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7076                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7077                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7078                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7079                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7080                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7081                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7082                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7083                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7084                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7085                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7086                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7087                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7088                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7089                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7090                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7091                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7092                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7093                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7094                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7095                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7096                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7097                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7098                         I40E_INSET_FLEX_PAYLOAD,
7099                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7100                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7101                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7102                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7103                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7104                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7105                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7106                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7107                         I40E_INSET_FLEX_PAYLOAD,
7108                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7109                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7110                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7111                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7112                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7113                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7114                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7115                         I40E_INSET_FLEX_PAYLOAD,
7116                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7117                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7118                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7119                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7120                         I40E_INSET_FLEX_PAYLOAD,
7121         };
7122
7123         /**
7124          * Flow director supports only fields defined in
7125          * union rte_eth_fdir_flow.
7126          */
7127         static const uint64_t valid_fdir_inset_table[] = {
7128                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7129                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7130                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7131                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7132                 I40E_INSET_IPV4_TTL,
7133                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7134                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7135                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7136                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7137                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7138                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7139                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7140                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7141                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7142                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7143                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7144                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7145                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7146                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7147                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7148                 I40E_INSET_SCTP_VT,
7149                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7150                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7151                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7152                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7153                 I40E_INSET_IPV4_TTL,
7154                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7155                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7156                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7157                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7158                 I40E_INSET_IPV6_HOP_LIMIT,
7159                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7160                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7161                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7162                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7163                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7164                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7165                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7166                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7167                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7168                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7169                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7170                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7171                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7172                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7173                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7174                 I40E_INSET_SCTP_VT,
7175                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7176                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7177                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7178                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7179                 I40E_INSET_IPV6_HOP_LIMIT,
7180                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7181                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7182                 I40E_INSET_LAST_ETHER_TYPE,
7183         };
7184
7185         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7186                 return 0;
7187         if (filter == RTE_ETH_FILTER_HASH)
7188                 valid = valid_hash_inset_table[pctype];
7189         else
7190                 valid = valid_fdir_inset_table[pctype];
7191
7192         return valid;
7193 }
7194
7195 /**
7196  * Validate if the input set is allowed for a specific PCTYPE
7197  */
7198 static int
7199 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7200                 enum rte_filter_type filter, uint64_t inset)
7201 {
7202         uint64_t valid;
7203
7204         valid = i40e_get_valid_input_set(pctype, filter);
7205         if (inset & (~valid))
7206                 return -EINVAL;
7207
7208         return 0;
7209 }
7210
7211 /* default input set fields combination per pctype */
7212 static uint64_t
7213 i40e_get_default_input_set(uint16_t pctype)
7214 {
7215         static const uint64_t default_inset_table[] = {
7216                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7217                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7218                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7219                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7220                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7221                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7222                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7223                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7224                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7225                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7226                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7227                         I40E_INSET_SCTP_VT,
7228                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7229                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7230                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7231                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7232                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7233                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7234                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7235                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7236                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7237                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7238                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7239                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7240                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7241                         I40E_INSET_SCTP_VT,
7242                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7243                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7244                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7245                         I40E_INSET_LAST_ETHER_TYPE,
7246         };
7247
7248         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7249                 return 0;
7250
7251         return default_inset_table[pctype];
7252 }
7253
7254 /**
7255  * Parse the input set from index to logical bit masks
7256  */
7257 static int
7258 i40e_parse_input_set(uint64_t *inset,
7259                      enum i40e_filter_pctype pctype,
7260                      enum rte_eth_input_set_field *field,
7261                      uint16_t size)
7262 {
7263         uint16_t i, j;
7264         int ret = -EINVAL;
7265
7266         static const struct {
7267                 enum rte_eth_input_set_field field;
7268                 uint64_t inset;
7269         } inset_convert_table[] = {
7270                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7271                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7272                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7273                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7274                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7275                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7276                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7277                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7278                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7279                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7280                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7281                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7282                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7283                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7284                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7285                         I40E_INSET_IPV6_NEXT_HDR},
7286                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7287                         I40E_INSET_IPV6_HOP_LIMIT},
7288                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7289                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7290                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7291                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7292                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7293                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7294                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7295                         I40E_INSET_SCTP_VT},
7296                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7297                         I40E_INSET_TUNNEL_DMAC},
7298                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7299                         I40E_INSET_VLAN_TUNNEL},
7300                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7301                         I40E_INSET_TUNNEL_ID},
7302                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7303                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7304                         I40E_INSET_FLEX_PAYLOAD_W1},
7305                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7306                         I40E_INSET_FLEX_PAYLOAD_W2},
7307                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7308                         I40E_INSET_FLEX_PAYLOAD_W3},
7309                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7310                         I40E_INSET_FLEX_PAYLOAD_W4},
7311                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7312                         I40E_INSET_FLEX_PAYLOAD_W5},
7313                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7314                         I40E_INSET_FLEX_PAYLOAD_W6},
7315                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7316                         I40E_INSET_FLEX_PAYLOAD_W7},
7317                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7318                         I40E_INSET_FLEX_PAYLOAD_W8},
7319         };
7320
7321         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7322                 return ret;
7323
7324         /* Only one item allowed for default or all */
7325         if (size == 1) {
7326                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7327                         *inset = i40e_get_default_input_set(pctype);
7328                         return 0;
7329                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7330                         *inset = I40E_INSET_NONE;
7331                         return 0;
7332                 }
7333         }
7334
7335         for (i = 0, *inset = 0; i < size; i++) {
7336                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7337                         if (field[i] == inset_convert_table[j].field) {
7338                                 *inset |= inset_convert_table[j].inset;
7339                                 break;
7340                         }
7341                 }
7342
7343                 /* It contains unsupported input set, return immediately */
7344                 if (j == RTE_DIM(inset_convert_table))
7345                         return ret;
7346         }
7347
7348         return 0;
7349 }
7350
7351 /**
7352  * Translate the input set from bit masks to register aware bit masks
7353  * and vice versa
7354  */
7355 static uint64_t
7356 i40e_translate_input_set_reg(uint64_t input)
7357 {
7358         uint64_t val = 0;
7359         uint16_t i;
7360
7361         static const struct {
7362                 uint64_t inset;
7363                 uint64_t inset_reg;
7364         } inset_map[] = {
7365                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7366                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7367                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7368                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7369                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7370                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7371                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7372                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7373                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7374                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7375                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7376                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7377                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7378                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7379                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7380                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7381                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7382                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7383                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7384                 {I40E_INSET_TUNNEL_DMAC,
7385                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7386                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7387                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7388                 {I40E_INSET_TUNNEL_SRC_PORT,
7389                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7390                 {I40E_INSET_TUNNEL_DST_PORT,
7391                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7392                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7393                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7394                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7395                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7396                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7397                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7398                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7399                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7400                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7401         };
7402
7403         if (input == 0)
7404                 return val;
7405
7406         /* Translate input set to register aware inset */
7407         for (i = 0; i < RTE_DIM(inset_map); i++) {
7408                 if (input & inset_map[i].inset)
7409                         val |= inset_map[i].inset_reg;
7410         }
7411
7412         return val;
7413 }
7414
7415 static int
7416 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7417 {
7418         uint8_t i, idx = 0;
7419         uint64_t inset_need_mask = inset;
7420
7421         static const struct {
7422                 uint64_t inset;
7423                 uint32_t mask;
7424         } inset_mask_map[] = {
7425                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7426                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7427                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7428                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7429                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7430                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7431                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7432                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7433         };
7434
7435         if (!inset || !mask || !nb_elem)
7436                 return 0;
7437
7438         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7439                 /* Clear the inset bit, if no MASK is required,
7440                  * for example proto + ttl
7441                  */
7442                 if ((inset & inset_mask_map[i].inset) ==
7443                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7444                         inset_need_mask &= ~inset_mask_map[i].inset;
7445                 if (!inset_need_mask)
7446                         return 0;
7447         }
7448         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7449                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7450                     inset_mask_map[i].inset) {
7451                         if (idx >= nb_elem) {
7452                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7453                                 return -EINVAL;
7454                         }
7455                         mask[idx] = inset_mask_map[i].mask;
7456                         idx++;
7457                 }
7458         }
7459
7460         return idx;
7461 }
7462
7463 static void
7464 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7465 {
7466         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7467
7468         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7469         if (reg != val)
7470                 i40e_write_rx_ctl(hw, addr, val);
7471         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7472                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7473 }
7474
7475 static void
7476 i40e_filter_input_set_init(struct i40e_pf *pf)
7477 {
7478         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7479         enum i40e_filter_pctype pctype;
7480         uint64_t input_set, inset_reg;
7481         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7482         int num, i;
7483
7484         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7485              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7486                 if (!I40E_VALID_PCTYPE(pctype))
7487                         continue;
7488                 input_set = i40e_get_default_input_set(pctype);
7489
7490                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7491                                                    I40E_INSET_MASK_NUM_REG);
7492                 if (num < 0)
7493                         return;
7494                 inset_reg = i40e_translate_input_set_reg(input_set);
7495
7496                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7497                                       (uint32_t)(inset_reg & UINT32_MAX));
7498                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7499                                      (uint32_t)((inset_reg >>
7500                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7501                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7502                                       (uint32_t)(inset_reg & UINT32_MAX));
7503                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7504                                      (uint32_t)((inset_reg >>
7505                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7506
7507                 for (i = 0; i < num; i++) {
7508                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7509                                              mask_reg[i]);
7510                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7511                                              mask_reg[i]);
7512                 }
7513                 /*clear unused mask registers of the pctype */
7514                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7515                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7516                                              0);
7517                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7518                                              0);
7519                 }
7520                 I40E_WRITE_FLUSH(hw);
7521
7522                 /* store the default input set */
7523                 pf->hash_input_set[pctype] = input_set;
7524                 pf->fdir.input_set[pctype] = input_set;
7525         }
7526 }
7527
7528 int
7529 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7530                          struct rte_eth_input_set_conf *conf)
7531 {
7532         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7533         enum i40e_filter_pctype pctype;
7534         uint64_t input_set, inset_reg = 0;
7535         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7536         int ret, i, num;
7537
7538         if (!conf) {
7539                 PMD_DRV_LOG(ERR, "Invalid pointer");
7540                 return -EFAULT;
7541         }
7542         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7543             conf->op != RTE_ETH_INPUT_SET_ADD) {
7544                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7545                 return -EINVAL;
7546         }
7547
7548         if (!I40E_VALID_FLOW(conf->flow_type)) {
7549                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7550                 return -EINVAL;
7551         }
7552         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7553         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7554                                    conf->inset_size);
7555         if (ret) {
7556                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7557                 return -EINVAL;
7558         }
7559         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7560                                     input_set) != 0) {
7561                 PMD_DRV_LOG(ERR, "Invalid input set");
7562                 return -EINVAL;
7563         }
7564         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7565                 /* get inset value in register */
7566                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7567                 inset_reg <<= I40E_32_BIT_WIDTH;
7568                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7569                 input_set |= pf->hash_input_set[pctype];
7570         }
7571         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7572                                            I40E_INSET_MASK_NUM_REG);
7573         if (num < 0)
7574                 return -EINVAL;
7575
7576         inset_reg |= i40e_translate_input_set_reg(input_set);
7577
7578         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7579                               (uint32_t)(inset_reg & UINT32_MAX));
7580         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7581                              (uint32_t)((inset_reg >>
7582                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7583
7584         for (i = 0; i < num; i++)
7585                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7586                                      mask_reg[i]);
7587         /*clear unused mask registers of the pctype */
7588         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7589                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7590                                      0);
7591         I40E_WRITE_FLUSH(hw);
7592
7593         pf->hash_input_set[pctype] = input_set;
7594         return 0;
7595 }
7596
7597 int
7598 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7599                          struct rte_eth_input_set_conf *conf)
7600 {
7601         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7602         enum i40e_filter_pctype pctype;
7603         uint64_t input_set, inset_reg = 0;
7604         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7605         int ret, i, num;
7606
7607         if (!hw || !conf) {
7608                 PMD_DRV_LOG(ERR, "Invalid pointer");
7609                 return -EFAULT;
7610         }
7611         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7612             conf->op != RTE_ETH_INPUT_SET_ADD) {
7613                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7614                 return -EINVAL;
7615         }
7616
7617         if (!I40E_VALID_FLOW(conf->flow_type)) {
7618                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7619                 return -EINVAL;
7620         }
7621         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7622         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7623                                    conf->inset_size);
7624         if (ret) {
7625                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7626                 return -EINVAL;
7627         }
7628         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7629                                     input_set) != 0) {
7630                 PMD_DRV_LOG(ERR, "Invalid input set");
7631                 return -EINVAL;
7632         }
7633
7634         /* get inset value in register */
7635         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7636         inset_reg <<= I40E_32_BIT_WIDTH;
7637         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7638
7639         /* Can not change the inset reg for flex payload for fdir,
7640          * it is done by writing I40E_PRTQF_FD_FLXINSET
7641          * in i40e_set_flex_mask_on_pctype.
7642          */
7643         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7644                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7645         else
7646                 input_set |= pf->fdir.input_set[pctype];
7647         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7648                                            I40E_INSET_MASK_NUM_REG);
7649         if (num < 0)
7650                 return -EINVAL;
7651
7652         inset_reg |= i40e_translate_input_set_reg(input_set);
7653
7654         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7655                               (uint32_t)(inset_reg & UINT32_MAX));
7656         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7657                              (uint32_t)((inset_reg >>
7658                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7659
7660         for (i = 0; i < num; i++)
7661                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7662                                      mask_reg[i]);
7663         /*clear unused mask registers of the pctype */
7664         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7665                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7666                                      0);
7667         I40E_WRITE_FLUSH(hw);
7668
7669         pf->fdir.input_set[pctype] = input_set;
7670         return 0;
7671 }
7672
7673 static int
7674 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7675 {
7676         int ret = 0;
7677
7678         if (!hw || !info) {
7679                 PMD_DRV_LOG(ERR, "Invalid pointer");
7680                 return -EFAULT;
7681         }
7682
7683         switch (info->info_type) {
7684         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7685                 i40e_get_symmetric_hash_enable_per_port(hw,
7686                                         &(info->info.enable));
7687                 break;
7688         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7689                 ret = i40e_get_hash_filter_global_config(hw,
7690                                 &(info->info.global_conf));
7691                 break;
7692         default:
7693                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7694                                                         info->info_type);
7695                 ret = -EINVAL;
7696                 break;
7697         }
7698
7699         return ret;
7700 }
7701
7702 static int
7703 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7704 {
7705         int ret = 0;
7706
7707         if (!hw || !info) {
7708                 PMD_DRV_LOG(ERR, "Invalid pointer");
7709                 return -EFAULT;
7710         }
7711
7712         switch (info->info_type) {
7713         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7714                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7715                 break;
7716         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7717                 ret = i40e_set_hash_filter_global_config(hw,
7718                                 &(info->info.global_conf));
7719                 break;
7720         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7721                 ret = i40e_hash_filter_inset_select(hw,
7722                                                &(info->info.input_set_conf));
7723                 break;
7724
7725         default:
7726                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7727                                                         info->info_type);
7728                 ret = -EINVAL;
7729                 break;
7730         }
7731
7732         return ret;
7733 }
7734
7735 /* Operations for hash function */
7736 static int
7737 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7738                       enum rte_filter_op filter_op,
7739                       void *arg)
7740 {
7741         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7742         int ret = 0;
7743
7744         switch (filter_op) {
7745         case RTE_ETH_FILTER_NOP:
7746                 break;
7747         case RTE_ETH_FILTER_GET:
7748                 ret = i40e_hash_filter_get(hw,
7749                         (struct rte_eth_hash_filter_info *)arg);
7750                 break;
7751         case RTE_ETH_FILTER_SET:
7752                 ret = i40e_hash_filter_set(hw,
7753                         (struct rte_eth_hash_filter_info *)arg);
7754                 break;
7755         default:
7756                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7757                                                                 filter_op);
7758                 ret = -ENOTSUP;
7759                 break;
7760         }
7761
7762         return ret;
7763 }
7764
7765 /*
7766  * Configure ethertype filter, which can director packet by filtering
7767  * with mac address and ether_type or only ether_type
7768  */
7769 static int
7770 i40e_ethertype_filter_set(struct i40e_pf *pf,
7771                         struct rte_eth_ethertype_filter *filter,
7772                         bool add)
7773 {
7774         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7775         struct i40e_control_filter_stats stats;
7776         uint16_t flags = 0;
7777         int ret;
7778
7779         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7780                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7781                 return -EINVAL;
7782         }
7783         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7784                 filter->ether_type == ETHER_TYPE_IPv6) {
7785                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7786                         " control packet filter.", filter->ether_type);
7787                 return -EINVAL;
7788         }
7789         if (filter->ether_type == ETHER_TYPE_VLAN)
7790                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7791                         " not supported.");
7792
7793         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7794                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7795         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7796                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7797         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7798
7799         memset(&stats, 0, sizeof(stats));
7800         ret = i40e_aq_add_rem_control_packet_filter(hw,
7801                         filter->mac_addr.addr_bytes,
7802                         filter->ether_type, flags,
7803                         pf->main_vsi->seid,
7804                         filter->queue, add, &stats, NULL);
7805
7806         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7807                          " mac_etype_used = %u, etype_used = %u,"
7808                          " mac_etype_free = %u, etype_free = %u\n",
7809                          ret, stats.mac_etype_used, stats.etype_used,
7810                          stats.mac_etype_free, stats.etype_free);
7811         if (ret < 0)
7812                 return -ENOSYS;
7813         return 0;
7814 }
7815
7816 /*
7817  * Handle operations for ethertype filter.
7818  */
7819 static int
7820 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7821                                 enum rte_filter_op filter_op,
7822                                 void *arg)
7823 {
7824         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7825         int ret = 0;
7826
7827         if (filter_op == RTE_ETH_FILTER_NOP)
7828                 return ret;
7829
7830         if (arg == NULL) {
7831                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7832                             filter_op);
7833                 return -EINVAL;
7834         }
7835
7836         switch (filter_op) {
7837         case RTE_ETH_FILTER_ADD:
7838                 ret = i40e_ethertype_filter_set(pf,
7839                         (struct rte_eth_ethertype_filter *)arg,
7840                         TRUE);
7841                 break;
7842         case RTE_ETH_FILTER_DELETE:
7843                 ret = i40e_ethertype_filter_set(pf,
7844                         (struct rte_eth_ethertype_filter *)arg,
7845                         FALSE);
7846                 break;
7847         default:
7848                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7849                 ret = -ENOSYS;
7850                 break;
7851         }
7852         return ret;
7853 }
7854
7855 static int
7856 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7857                      enum rte_filter_type filter_type,
7858                      enum rte_filter_op filter_op,
7859                      void *arg)
7860 {
7861         int ret = 0;
7862
7863         if (dev == NULL)
7864                 return -EINVAL;
7865
7866         switch (filter_type) {
7867         case RTE_ETH_FILTER_NONE:
7868                 /* For global configuration */
7869                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7870                 break;
7871         case RTE_ETH_FILTER_HASH:
7872                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7873                 break;
7874         case RTE_ETH_FILTER_MACVLAN:
7875                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7876                 break;
7877         case RTE_ETH_FILTER_ETHERTYPE:
7878                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7879                 break;
7880         case RTE_ETH_FILTER_TUNNEL:
7881                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7882                 break;
7883         case RTE_ETH_FILTER_FDIR:
7884                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7885                 break;
7886         default:
7887                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7888                                                         filter_type);
7889                 ret = -EINVAL;
7890                 break;
7891         }
7892
7893         return ret;
7894 }
7895
7896 /*
7897  * Check and enable Extended Tag.
7898  * Enabling Extended Tag is important for 40G performance.
7899  */
7900 static void
7901 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7902 {
7903         uint32_t buf = 0;
7904         int ret;
7905
7906         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7907                                       PCI_DEV_CAP_REG);
7908         if (ret < 0) {
7909                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7910                             PCI_DEV_CAP_REG);
7911                 return;
7912         }
7913         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7914                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7915                 return;
7916         }
7917
7918         buf = 0;
7919         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7920                                       PCI_DEV_CTRL_REG);
7921         if (ret < 0) {
7922                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7923                             PCI_DEV_CTRL_REG);
7924                 return;
7925         }
7926         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7927                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7928                 return;
7929         }
7930         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7931         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7932                                        PCI_DEV_CTRL_REG);
7933         if (ret < 0) {
7934                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7935                             PCI_DEV_CTRL_REG);
7936                 return;
7937         }
7938 }
7939
7940 /*
7941  * As some registers wouldn't be reset unless a global hardware reset,
7942  * hardware initialization is needed to put those registers into an
7943  * expected initial state.
7944  */
7945 static void
7946 i40e_hw_init(struct rte_eth_dev *dev)
7947 {
7948         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7949
7950         i40e_enable_extended_tag(dev);
7951
7952         /* clear the PF Queue Filter control register */
7953         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7954
7955         /* Disable symmetric hash per port */
7956         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7957 }
7958
7959 enum i40e_filter_pctype
7960 i40e_flowtype_to_pctype(uint16_t flow_type)
7961 {
7962         static const enum i40e_filter_pctype pctype_table[] = {
7963                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7964                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7965                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7966                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7967                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7968                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7969                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7970                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7971                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7972                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7973                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7974                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7975                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7976                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7977                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7978                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7979                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7980                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7981                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7982         };
7983
7984         return pctype_table[flow_type];
7985 }
7986
7987 uint16_t
7988 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7989 {
7990         static const uint16_t flowtype_table[] = {
7991                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7992                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7993                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7994                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7995                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7996                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7997                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7998                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7999                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8000                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8001                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8002                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8003                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8004                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8005                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8006                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8007                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8008                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8009                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8010         };
8011
8012         return flowtype_table[pctype];
8013 }
8014
8015 /*
8016  * On X710, performance number is far from the expectation on recent firmware
8017  * versions; on XL710, performance number is also far from the expectation on
8018  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8019  * mode is enabled and port MAC address is equal to the packet destination MAC
8020  * address. The fix for this issue may not be integrated in the following
8021  * firmware version. So the workaround in software driver is needed. It needs
8022  * to modify the initial values of 3 internal only registers for both X710 and
8023  * XL710. Note that the values for X710 or XL710 could be different, and the
8024  * workaround can be removed when it is fixed in firmware in the future.
8025  */
8026
8027 /* For both X710 and XL710 */
8028 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8029 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8030
8031 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8032 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8033
8034 /* For X710 */
8035 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8036 /* For XL710 */
8037 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8038 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8039
8040 static void
8041 i40e_configure_registers(struct i40e_hw *hw)
8042 {
8043         static struct {
8044                 uint32_t addr;
8045                 uint64_t val;
8046         } reg_table[] = {
8047                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8048                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8049                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8050         };
8051         uint64_t reg;
8052         uint32_t i;
8053         int ret;
8054
8055         for (i = 0; i < RTE_DIM(reg_table); i++) {
8056                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8057                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
8058                                 reg_table[i].val =
8059                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8060                         else /* For X710 */
8061                                 reg_table[i].val =
8062                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8063                 }
8064
8065                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8066                                                         &reg, NULL);
8067                 if (ret < 0) {
8068                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8069                                                         reg_table[i].addr);
8070                         break;
8071                 }
8072                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8073                                                 reg_table[i].addr, reg);
8074                 if (reg == reg_table[i].val)
8075                         continue;
8076
8077                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8078                                                 reg_table[i].val, NULL);
8079                 if (ret < 0) {
8080                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8081                                 "address of 0x%"PRIx32, reg_table[i].val,
8082                                                         reg_table[i].addr);
8083                         break;
8084                 }
8085                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8086                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8087         }
8088 }
8089
8090 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8091 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8092 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8093 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8094 static int
8095 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8096 {
8097         uint32_t reg;
8098         int ret;
8099
8100         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8101                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8102                 return -EINVAL;
8103         }
8104
8105         /* Configure for double VLAN RX stripping */
8106         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8107         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8108                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8109                 ret = i40e_aq_debug_write_register(hw,
8110                                                    I40E_VSI_TSR(vsi->vsi_id),
8111                                                    reg, NULL);
8112                 if (ret < 0) {
8113                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8114                                     vsi->vsi_id);
8115                         return I40E_ERR_CONFIG;
8116                 }
8117         }
8118
8119         /* Configure for double VLAN TX insertion */
8120         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8121         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8122                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8123                 ret = i40e_aq_debug_write_register(hw,
8124                                                    I40E_VSI_L2TAGSTXVALID(
8125                                                    vsi->vsi_id), reg, NULL);
8126                 if (ret < 0) {
8127                         PMD_DRV_LOG(ERR, "Failed to update "
8128                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8129                         return I40E_ERR_CONFIG;
8130                 }
8131         }
8132
8133         return 0;
8134 }
8135
8136 /**
8137  * i40e_aq_add_mirror_rule
8138  * @hw: pointer to the hardware structure
8139  * @seid: VEB seid to add mirror rule to
8140  * @dst_id: destination vsi seid
8141  * @entries: Buffer which contains the entities to be mirrored
8142  * @count: number of entities contained in the buffer
8143  * @rule_id:the rule_id of the rule to be added
8144  *
8145  * Add a mirror rule for a given veb.
8146  *
8147  **/
8148 static enum i40e_status_code
8149 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8150                         uint16_t seid, uint16_t dst_id,
8151                         uint16_t rule_type, uint16_t *entries,
8152                         uint16_t count, uint16_t *rule_id)
8153 {
8154         struct i40e_aq_desc desc;
8155         struct i40e_aqc_add_delete_mirror_rule cmd;
8156         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8157                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8158                 &desc.params.raw;
8159         uint16_t buff_len;
8160         enum i40e_status_code status;
8161
8162         i40e_fill_default_direct_cmd_desc(&desc,
8163                                           i40e_aqc_opc_add_mirror_rule);
8164         memset(&cmd, 0, sizeof(cmd));
8165
8166         buff_len = sizeof(uint16_t) * count;
8167         desc.datalen = rte_cpu_to_le_16(buff_len);
8168         if (buff_len > 0)
8169                 desc.flags |= rte_cpu_to_le_16(
8170                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8171         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8172                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8173         cmd.num_entries = rte_cpu_to_le_16(count);
8174         cmd.seid = rte_cpu_to_le_16(seid);
8175         cmd.destination = rte_cpu_to_le_16(dst_id);
8176
8177         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8178         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8179         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8180                          "rule_id = %u"
8181                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8182                          hw->aq.asq_last_status, resp->rule_id,
8183                          resp->mirror_rules_used, resp->mirror_rules_free);
8184         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8185
8186         return status;
8187 }
8188
8189 /**
8190  * i40e_aq_del_mirror_rule
8191  * @hw: pointer to the hardware structure
8192  * @seid: VEB seid to add mirror rule to
8193  * @entries: Buffer which contains the entities to be mirrored
8194  * @count: number of entities contained in the buffer
8195  * @rule_id:the rule_id of the rule to be delete
8196  *
8197  * Delete a mirror rule for a given veb.
8198  *
8199  **/
8200 static enum i40e_status_code
8201 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8202                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8203                 uint16_t count, uint16_t rule_id)
8204 {
8205         struct i40e_aq_desc desc;
8206         struct i40e_aqc_add_delete_mirror_rule cmd;
8207         uint16_t buff_len = 0;
8208         enum i40e_status_code status;
8209         void *buff = NULL;
8210
8211         i40e_fill_default_direct_cmd_desc(&desc,
8212                                           i40e_aqc_opc_delete_mirror_rule);
8213         memset(&cmd, 0, sizeof(cmd));
8214         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8215                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8216                                                           I40E_AQ_FLAG_RD));
8217                 cmd.num_entries = count;
8218                 buff_len = sizeof(uint16_t) * count;
8219                 desc.datalen = rte_cpu_to_le_16(buff_len);
8220                 buff = (void *)entries;
8221         } else
8222                 /* rule id is filled in destination field for deleting mirror rule */
8223                 cmd.destination = rte_cpu_to_le_16(rule_id);
8224
8225         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8226                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8227         cmd.seid = rte_cpu_to_le_16(seid);
8228
8229         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8230         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8231
8232         return status;
8233 }
8234
8235 /**
8236  * i40e_mirror_rule_set
8237  * @dev: pointer to the hardware structure
8238  * @mirror_conf: mirror rule info
8239  * @sw_id: mirror rule's sw_id
8240  * @on: enable/disable
8241  *
8242  * set a mirror rule.
8243  *
8244  **/
8245 static int
8246 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8247                         struct rte_eth_mirror_conf *mirror_conf,
8248                         uint8_t sw_id, uint8_t on)
8249 {
8250         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8251         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8252         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8253         struct i40e_mirror_rule *parent = NULL;
8254         uint16_t seid, dst_seid, rule_id;
8255         uint16_t i, j = 0;
8256         int ret;
8257
8258         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8259
8260         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8261                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8262                         " without veb or vfs.");
8263                 return -ENOSYS;
8264         }
8265         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8266                 PMD_DRV_LOG(ERR, "mirror table is full.");
8267                 return -ENOSPC;
8268         }
8269         if (mirror_conf->dst_pool > pf->vf_num) {
8270                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8271                                  mirror_conf->dst_pool);
8272                 return -EINVAL;
8273         }
8274
8275         seid = pf->main_vsi->veb->seid;
8276
8277         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8278                 if (sw_id <= it->index) {
8279                         mirr_rule = it;
8280                         break;
8281                 }
8282                 parent = it;
8283         }
8284         if (mirr_rule && sw_id == mirr_rule->index) {
8285                 if (on) {
8286                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8287                         return -EEXIST;
8288                 } else {
8289                         ret = i40e_aq_del_mirror_rule(hw, seid,
8290                                         mirr_rule->rule_type,
8291                                         mirr_rule->entries,
8292                                         mirr_rule->num_entries, mirr_rule->id);
8293                         if (ret < 0) {
8294                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8295                                                    " ret = %d, aq_err = %d.",
8296                                                    ret, hw->aq.asq_last_status);
8297                                 return -ENOSYS;
8298                         }
8299                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8300                         rte_free(mirr_rule);
8301                         pf->nb_mirror_rule--;
8302                         return 0;
8303                 }
8304         } else if (!on) {
8305                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8306                 return -ENOENT;
8307         }
8308
8309         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8310                                 sizeof(struct i40e_mirror_rule) , 0);
8311         if (!mirr_rule) {
8312                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8313                 return I40E_ERR_NO_MEMORY;
8314         }
8315         switch (mirror_conf->rule_type) {
8316         case ETH_MIRROR_VLAN:
8317                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8318                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8319                                 mirr_rule->entries[j] =
8320                                         mirror_conf->vlan.vlan_id[i];
8321                                 j++;
8322                         }
8323                 }
8324                 if (j == 0) {
8325                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8326                         rte_free(mirr_rule);
8327                         return -EINVAL;
8328                 }
8329                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8330                 break;
8331         case ETH_MIRROR_VIRTUAL_POOL_UP:
8332         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8333                 /* check if the specified pool bit is out of range */
8334                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8335                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8336                         rte_free(mirr_rule);
8337                         return -EINVAL;
8338                 }
8339                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8340                         if (mirror_conf->pool_mask & (1ULL << i)) {
8341                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8342                                 j++;
8343                         }
8344                 }
8345                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8346                         /* add pf vsi to entries */
8347                         mirr_rule->entries[j] = pf->main_vsi_seid;
8348                         j++;
8349                 }
8350                 if (j == 0) {
8351                         PMD_DRV_LOG(ERR, "pool is not specified.");
8352                         rte_free(mirr_rule);
8353                         return -EINVAL;
8354                 }
8355                 /* egress and ingress in aq commands means from switch but not port */
8356                 mirr_rule->rule_type =
8357                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8358                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8359                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8360                 break;
8361         case ETH_MIRROR_UPLINK_PORT:
8362                 /* egress and ingress in aq commands means from switch but not port*/
8363                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8364                 break;
8365         case ETH_MIRROR_DOWNLINK_PORT:
8366                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8367                 break;
8368         default:
8369                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8370                         mirror_conf->rule_type);
8371                 rte_free(mirr_rule);
8372                 return -EINVAL;
8373         }
8374
8375         /* If the dst_pool is equal to vf_num, consider it as PF */
8376         if (mirror_conf->dst_pool == pf->vf_num)
8377                 dst_seid = pf->main_vsi_seid;
8378         else
8379                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8380
8381         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8382                                       mirr_rule->rule_type, mirr_rule->entries,
8383                                       j, &rule_id);
8384         if (ret < 0) {
8385                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8386                                    " ret = %d, aq_err = %d.",
8387                                    ret, hw->aq.asq_last_status);
8388                 rte_free(mirr_rule);
8389                 return -ENOSYS;
8390         }
8391
8392         mirr_rule->index = sw_id;
8393         mirr_rule->num_entries = j;
8394         mirr_rule->id = rule_id;
8395         mirr_rule->dst_vsi_seid = dst_seid;
8396
8397         if (parent)
8398                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8399         else
8400                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8401
8402         pf->nb_mirror_rule++;
8403         return 0;
8404 }
8405
8406 /**
8407  * i40e_mirror_rule_reset
8408  * @dev: pointer to the device
8409  * @sw_id: mirror rule's sw_id
8410  *
8411  * reset a mirror rule.
8412  *
8413  **/
8414 static int
8415 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8416 {
8417         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8418         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8419         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8420         uint16_t seid;
8421         int ret;
8422
8423         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8424
8425         seid = pf->main_vsi->veb->seid;
8426
8427         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8428                 if (sw_id == it->index) {
8429                         mirr_rule = it;
8430                         break;
8431                 }
8432         }
8433         if (mirr_rule) {
8434                 ret = i40e_aq_del_mirror_rule(hw, seid,
8435                                 mirr_rule->rule_type,
8436                                 mirr_rule->entries,
8437                                 mirr_rule->num_entries, mirr_rule->id);
8438                 if (ret < 0) {
8439                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8440                                            " status = %d, aq_err = %d.",
8441                                            ret, hw->aq.asq_last_status);
8442                         return -ENOSYS;
8443                 }
8444                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8445                 rte_free(mirr_rule);
8446                 pf->nb_mirror_rule--;
8447         } else {
8448                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8449                 return -ENOENT;
8450         }
8451         return 0;
8452 }
8453
8454 static uint64_t
8455 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8456 {
8457         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8458         uint64_t systim_cycles;
8459
8460         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8461         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8462                         << 32;
8463
8464         return systim_cycles;
8465 }
8466
8467 static uint64_t
8468 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8469 {
8470         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8471         uint64_t rx_tstamp;
8472
8473         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8474         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8475                         << 32;
8476
8477         return rx_tstamp;
8478 }
8479
8480 static uint64_t
8481 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8482 {
8483         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8484         uint64_t tx_tstamp;
8485
8486         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8487         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8488                         << 32;
8489
8490         return tx_tstamp;
8491 }
8492
8493 static void
8494 i40e_start_timecounters(struct rte_eth_dev *dev)
8495 {
8496         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8497         struct i40e_adapter *adapter =
8498                         (struct i40e_adapter *)dev->data->dev_private;
8499         struct rte_eth_link link;
8500         uint32_t tsync_inc_l;
8501         uint32_t tsync_inc_h;
8502
8503         /* Get current link speed. */
8504         memset(&link, 0, sizeof(link));
8505         i40e_dev_link_update(dev, 1);
8506         rte_i40e_dev_atomic_read_link_status(dev, &link);
8507
8508         switch (link.link_speed) {
8509         case ETH_SPEED_NUM_40G:
8510                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8511                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8512                 break;
8513         case ETH_SPEED_NUM_10G:
8514                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8515                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8516                 break;
8517         case ETH_SPEED_NUM_1G:
8518                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8519                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8520                 break;
8521         default:
8522                 tsync_inc_l = 0x0;
8523                 tsync_inc_h = 0x0;
8524         }
8525
8526         /* Set the timesync increment value. */
8527         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8528         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8529
8530         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8531         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8532         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8533
8534         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8535         adapter->systime_tc.cc_shift = 0;
8536         adapter->systime_tc.nsec_mask = 0;
8537
8538         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8539         adapter->rx_tstamp_tc.cc_shift = 0;
8540         adapter->rx_tstamp_tc.nsec_mask = 0;
8541
8542         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8543         adapter->tx_tstamp_tc.cc_shift = 0;
8544         adapter->tx_tstamp_tc.nsec_mask = 0;
8545 }
8546
8547 static int
8548 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8549 {
8550         struct i40e_adapter *adapter =
8551                         (struct i40e_adapter *)dev->data->dev_private;
8552
8553         adapter->systime_tc.nsec += delta;
8554         adapter->rx_tstamp_tc.nsec += delta;
8555         adapter->tx_tstamp_tc.nsec += delta;
8556
8557         return 0;
8558 }
8559
8560 static int
8561 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8562 {
8563         uint64_t ns;
8564         struct i40e_adapter *adapter =
8565                         (struct i40e_adapter *)dev->data->dev_private;
8566
8567         ns = rte_timespec_to_ns(ts);
8568
8569         /* Set the timecounters to a new value. */
8570         adapter->systime_tc.nsec = ns;
8571         adapter->rx_tstamp_tc.nsec = ns;
8572         adapter->tx_tstamp_tc.nsec = ns;
8573
8574         return 0;
8575 }
8576
8577 static int
8578 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8579 {
8580         uint64_t ns, systime_cycles;
8581         struct i40e_adapter *adapter =
8582                         (struct i40e_adapter *)dev->data->dev_private;
8583
8584         systime_cycles = i40e_read_systime_cyclecounter(dev);
8585         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8586         *ts = rte_ns_to_timespec(ns);
8587
8588         return 0;
8589 }
8590
8591 static int
8592 i40e_timesync_enable(struct rte_eth_dev *dev)
8593 {
8594         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8595         uint32_t tsync_ctl_l;
8596         uint32_t tsync_ctl_h;
8597
8598         /* Stop the timesync system time. */
8599         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8600         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8601         /* Reset the timesync system time value. */
8602         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8603         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8604
8605         i40e_start_timecounters(dev);
8606
8607         /* Clear timesync registers. */
8608         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8609         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8610         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8611         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8612         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8613         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8614
8615         /* Enable timestamping of PTP packets. */
8616         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8617         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8618
8619         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8620         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8621         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8622
8623         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8624         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8625
8626         return 0;
8627 }
8628
8629 static int
8630 i40e_timesync_disable(struct rte_eth_dev *dev)
8631 {
8632         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8633         uint32_t tsync_ctl_l;
8634         uint32_t tsync_ctl_h;
8635
8636         /* Disable timestamping of transmitted PTP packets. */
8637         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8638         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8639
8640         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8641         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8642
8643         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8644         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8645
8646         /* Reset the timesync increment value. */
8647         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8648         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8649
8650         return 0;
8651 }
8652
8653 static int
8654 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8655                                 struct timespec *timestamp, uint32_t flags)
8656 {
8657         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8658         struct i40e_adapter *adapter =
8659                 (struct i40e_adapter *)dev->data->dev_private;
8660
8661         uint32_t sync_status;
8662         uint32_t index = flags & 0x03;
8663         uint64_t rx_tstamp_cycles;
8664         uint64_t ns;
8665
8666         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8667         if ((sync_status & (1 << index)) == 0)
8668                 return -EINVAL;
8669
8670         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8671         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8672         *timestamp = rte_ns_to_timespec(ns);
8673
8674         return 0;
8675 }
8676
8677 static int
8678 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8679                                 struct timespec *timestamp)
8680 {
8681         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8682         struct i40e_adapter *adapter =
8683                 (struct i40e_adapter *)dev->data->dev_private;
8684
8685         uint32_t sync_status;
8686         uint64_t tx_tstamp_cycles;
8687         uint64_t ns;
8688
8689         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8690         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8691                 return -EINVAL;
8692
8693         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8694         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8695         *timestamp = rte_ns_to_timespec(ns);
8696
8697         return 0;
8698 }
8699
8700 /*
8701  * i40e_parse_dcb_configure - parse dcb configure from user
8702  * @dev: the device being configured
8703  * @dcb_cfg: pointer of the result of parse
8704  * @*tc_map: bit map of enabled traffic classes
8705  *
8706  * Returns 0 on success, negative value on failure
8707  */
8708 static int
8709 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8710                          struct i40e_dcbx_config *dcb_cfg,
8711                          uint8_t *tc_map)
8712 {
8713         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8714         uint8_t i, tc_bw, bw_lf;
8715
8716         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8717
8718         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8719         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8720                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8721                 return -EINVAL;
8722         }
8723
8724         /* assume each tc has the same bw */
8725         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8726         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8727                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8728         /* to ensure the sum of tcbw is equal to 100 */
8729         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8730         for (i = 0; i < bw_lf; i++)
8731                 dcb_cfg->etscfg.tcbwtable[i]++;
8732
8733         /* assume each tc has the same Transmission Selection Algorithm */
8734         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8735                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8736
8737         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8738                 dcb_cfg->etscfg.prioritytable[i] =
8739                                 dcb_rx_conf->dcb_tc[i];
8740
8741         /* FW needs one App to configure HW */
8742         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8743         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8744         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8745         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8746
8747         if (dcb_rx_conf->nb_tcs == 0)
8748                 *tc_map = 1; /* tc0 only */
8749         else
8750                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8751
8752         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8753                 dcb_cfg->pfc.willing = 0;
8754                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8755                 dcb_cfg->pfc.pfcenable = *tc_map;
8756         }
8757         return 0;
8758 }
8759
8760
8761 static enum i40e_status_code
8762 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8763                               struct i40e_aqc_vsi_properties_data *info,
8764                               uint8_t enabled_tcmap)
8765 {
8766         enum i40e_status_code ret;
8767         int i, total_tc = 0;
8768         uint16_t qpnum_per_tc, bsf, qp_idx;
8769         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8770         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8771         uint16_t used_queues;
8772
8773         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8774         if (ret != I40E_SUCCESS)
8775                 return ret;
8776
8777         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8778                 if (enabled_tcmap & (1 << i))
8779                         total_tc++;
8780         }
8781         if (total_tc == 0)
8782                 total_tc = 1;
8783         vsi->enabled_tc = enabled_tcmap;
8784
8785         /* different VSI has different queues assigned */
8786         if (vsi->type == I40E_VSI_MAIN)
8787                 used_queues = dev_data->nb_rx_queues -
8788                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8789         else if (vsi->type == I40E_VSI_VMDQ2)
8790                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8791         else {
8792                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8793                 return I40E_ERR_NO_AVAILABLE_VSI;
8794         }
8795
8796         qpnum_per_tc = used_queues / total_tc;
8797         /* Number of queues per enabled TC */
8798         if (qpnum_per_tc == 0) {
8799                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8800                 return I40E_ERR_INVALID_QP_ID;
8801         }
8802         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8803                                 I40E_MAX_Q_PER_TC);
8804         bsf = rte_bsf32(qpnum_per_tc);
8805
8806         /**
8807          * Configure TC and queue mapping parameters, for enabled TC,
8808          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8809          * default queue will serve it.
8810          */
8811         qp_idx = 0;
8812         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8813                 if (vsi->enabled_tc & (1 << i)) {
8814                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8815                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8816                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8817                         qp_idx += qpnum_per_tc;
8818                 } else
8819                         info->tc_mapping[i] = 0;
8820         }
8821
8822         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8823         if (vsi->type == I40E_VSI_SRIOV) {
8824                 info->mapping_flags |=
8825                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8826                 for (i = 0; i < vsi->nb_qps; i++)
8827                         info->queue_mapping[i] =
8828                                 rte_cpu_to_le_16(vsi->base_queue + i);
8829         } else {
8830                 info->mapping_flags |=
8831                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8832                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8833         }
8834         info->valid_sections |=
8835                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8836
8837         return I40E_SUCCESS;
8838 }
8839
8840 /*
8841  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8842  * @veb: VEB to be configured
8843  * @tc_map: enabled TC bitmap
8844  *
8845  * Returns 0 on success, negative value on failure
8846  */
8847 static enum i40e_status_code
8848 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8849 {
8850         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8851         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8852         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8853         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8854         enum i40e_status_code ret = I40E_SUCCESS;
8855         int i;
8856         uint32_t bw_max;
8857
8858         /* Check if enabled_tc is same as existing or new TCs */
8859         if (veb->enabled_tc == tc_map)
8860                 return ret;
8861
8862         /* configure tc bandwidth */
8863         memset(&veb_bw, 0, sizeof(veb_bw));
8864         veb_bw.tc_valid_bits = tc_map;
8865         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8866         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8867                 if (tc_map & BIT_ULL(i))
8868                         veb_bw.tc_bw_share_credits[i] = 1;
8869         }
8870         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8871                                                    &veb_bw, NULL);
8872         if (ret) {
8873                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8874                                   " per TC failed = %d",
8875                                   hw->aq.asq_last_status);
8876                 return ret;
8877         }
8878
8879         memset(&ets_query, 0, sizeof(ets_query));
8880         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8881                                                    &ets_query, NULL);
8882         if (ret != I40E_SUCCESS) {
8883                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8884                                  " configuration %u", hw->aq.asq_last_status);
8885                 return ret;
8886         }
8887         memset(&bw_query, 0, sizeof(bw_query));
8888         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8889                                                   &bw_query, NULL);
8890         if (ret != I40E_SUCCESS) {
8891                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8892                                  " configuration %u", hw->aq.asq_last_status);
8893                 return ret;
8894         }
8895
8896         /* store and print out BW info */
8897         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8898         veb->bw_info.bw_max = ets_query.tc_bw_max;
8899         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8900         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8901         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8902                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8903                      I40E_16_BIT_WIDTH);
8904         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8905                 veb->bw_info.bw_ets_share_credits[i] =
8906                                 bw_query.tc_bw_share_credits[i];
8907                 veb->bw_info.bw_ets_credits[i] =
8908                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8909                 /* 4 bits per TC, 4th bit is reserved */
8910                 veb->bw_info.bw_ets_max[i] =
8911                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8912                                   RTE_LEN2MASK(3, uint8_t));
8913                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8914                             veb->bw_info.bw_ets_share_credits[i]);
8915                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8916                             veb->bw_info.bw_ets_credits[i]);
8917                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8918                             veb->bw_info.bw_ets_max[i]);
8919         }
8920
8921         veb->enabled_tc = tc_map;
8922
8923         return ret;
8924 }
8925
8926
8927 /*
8928  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8929  * @vsi: VSI to be configured
8930  * @tc_map: enabled TC bitmap
8931  *
8932  * Returns 0 on success, negative value on failure
8933  */
8934 static enum i40e_status_code
8935 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8936 {
8937         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8938         struct i40e_vsi_context ctxt;
8939         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8940         enum i40e_status_code ret = I40E_SUCCESS;
8941         int i;
8942
8943         /* Check if enabled_tc is same as existing or new TCs */
8944         if (vsi->enabled_tc == tc_map)
8945                 return ret;
8946
8947         /* configure tc bandwidth */
8948         memset(&bw_data, 0, sizeof(bw_data));
8949         bw_data.tc_valid_bits = tc_map;
8950         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8951         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8952                 if (tc_map & BIT_ULL(i))
8953                         bw_data.tc_bw_credits[i] = 1;
8954         }
8955         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8956         if (ret) {
8957                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8958                         " per TC failed = %d",
8959                         hw->aq.asq_last_status);
8960                 goto out;
8961         }
8962         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8963                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8964
8965         /* Update Queue Pairs Mapping for currently enabled UPs */
8966         ctxt.seid = vsi->seid;
8967         ctxt.pf_num = hw->pf_id;
8968         ctxt.vf_num = 0;
8969         ctxt.uplink_seid = vsi->uplink_seid;
8970         ctxt.info = vsi->info;
8971         i40e_get_cap(hw);
8972         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8973         if (ret)
8974                 goto out;
8975
8976         /* Update the VSI after updating the VSI queue-mapping information */
8977         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8978         if (ret) {
8979                 PMD_INIT_LOG(ERR, "Failed to configure "
8980                             "TC queue mapping = %d",
8981                             hw->aq.asq_last_status);
8982                 goto out;
8983         }
8984         /* update the local VSI info with updated queue map */
8985         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8986                                         sizeof(vsi->info.tc_mapping));
8987         (void)rte_memcpy(&vsi->info.queue_mapping,
8988                         &ctxt.info.queue_mapping,
8989                 sizeof(vsi->info.queue_mapping));
8990         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8991         vsi->info.valid_sections = 0;
8992
8993         /* query and update current VSI BW information */
8994         ret = i40e_vsi_get_bw_config(vsi);
8995         if (ret) {
8996                 PMD_INIT_LOG(ERR,
8997                          "Failed updating vsi bw info, err %s aq_err %s",
8998                          i40e_stat_str(hw, ret),
8999                          i40e_aq_str(hw, hw->aq.asq_last_status));
9000                 goto out;
9001         }
9002
9003         vsi->enabled_tc = tc_map;
9004
9005 out:
9006         return ret;
9007 }
9008
9009 /*
9010  * i40e_dcb_hw_configure - program the dcb setting to hw
9011  * @pf: pf the configuration is taken on
9012  * @new_cfg: new configuration
9013  * @tc_map: enabled TC bitmap
9014  *
9015  * Returns 0 on success, negative value on failure
9016  */
9017 static enum i40e_status_code
9018 i40e_dcb_hw_configure(struct i40e_pf *pf,
9019                       struct i40e_dcbx_config *new_cfg,
9020                       uint8_t tc_map)
9021 {
9022         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9023         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9024         struct i40e_vsi *main_vsi = pf->main_vsi;
9025         struct i40e_vsi_list *vsi_list;
9026         enum i40e_status_code ret;
9027         int i;
9028         uint32_t val;
9029
9030         /* Use the FW API if FW > v4.4*/
9031         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9032               (hw->aq.fw_maj_ver >= 5))) {
9033                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9034                                   " to configure DCB");
9035                 return I40E_ERR_FIRMWARE_API_VERSION;
9036         }
9037
9038         /* Check if need reconfiguration */
9039         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9040                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9041                 return I40E_SUCCESS;
9042         }
9043
9044         /* Copy the new config to the current config */
9045         *old_cfg = *new_cfg;
9046         old_cfg->etsrec = old_cfg->etscfg;
9047         ret = i40e_set_dcb_config(hw);
9048         if (ret) {
9049                 PMD_INIT_LOG(ERR,
9050                          "Set DCB Config failed, err %s aq_err %s\n",
9051                          i40e_stat_str(hw, ret),
9052                          i40e_aq_str(hw, hw->aq.asq_last_status));
9053                 return ret;
9054         }
9055         /* set receive Arbiter to RR mode and ETS scheme by default */
9056         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9057                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9058                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9059                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9060                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9061                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9062                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9063                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9064                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9065                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9066                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9067                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9068                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9069         }
9070         /* get local mib to check whether it is configured correctly */
9071         /* IEEE mode */
9072         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9073         /* Get Local DCB Config */
9074         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9075                                      &hw->local_dcbx_config);
9076
9077         /* if Veb is created, need to update TC of it at first */
9078         if (main_vsi->veb) {
9079                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9080                 if (ret)
9081                         PMD_INIT_LOG(WARNING,
9082                                  "Failed configuring TC for VEB seid=%d\n",
9083                                  main_vsi->veb->seid);
9084         }
9085         /* Update each VSI */
9086         i40e_vsi_config_tc(main_vsi, tc_map);
9087         if (main_vsi->veb) {
9088                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9089                         /* Beside main VSI and VMDQ VSIs, only enable default
9090                          * TC for other VSIs
9091                          */
9092                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9093                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9094                                                          tc_map);
9095                         else
9096                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9097                                                          I40E_DEFAULT_TCMAP);
9098                         if (ret)
9099                                 PMD_INIT_LOG(WARNING,
9100                                          "Failed configuring TC for VSI seid=%d\n",
9101                                          vsi_list->vsi->seid);
9102                         /* continue */
9103                 }
9104         }
9105         return I40E_SUCCESS;
9106 }
9107
9108 /*
9109  * i40e_dcb_init_configure - initial dcb config
9110  * @dev: device being configured
9111  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9112  *
9113  * Returns 0 on success, negative value on failure
9114  */
9115 static int
9116 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9117 {
9118         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9119         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9120         int ret = 0;
9121
9122         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9123                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9124                 return -ENOTSUP;
9125         }
9126
9127         /* DCB initialization:
9128          * Update DCB configuration from the Firmware and configure
9129          * LLDP MIB change event.
9130          */
9131         if (sw_dcb == TRUE) {
9132                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
9133                 if (ret != I40E_SUCCESS)
9134                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
9135
9136                 ret = i40e_init_dcb(hw);
9137                 /* if sw_dcb, lldp agent is stopped, the return from
9138                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9139                  * adminq status.
9140                  */
9141                 if (ret != I40E_SUCCESS &&
9142                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
9143                         memset(&hw->local_dcbx_config, 0,
9144                                 sizeof(struct i40e_dcbx_config));
9145                         /* set dcb default configuration */
9146                         hw->local_dcbx_config.etscfg.willing = 0;
9147                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9148                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9149                         hw->local_dcbx_config.etscfg.tsatable[0] =
9150                                                 I40E_IEEE_TSA_ETS;
9151                         hw->local_dcbx_config.etsrec =
9152                                 hw->local_dcbx_config.etscfg;
9153                         hw->local_dcbx_config.pfc.willing = 0;
9154                         hw->local_dcbx_config.pfc.pfccap =
9155                                                 I40E_MAX_TRAFFIC_CLASS;
9156                         /* FW needs one App to configure HW */
9157                         hw->local_dcbx_config.numapps = 1;
9158                         hw->local_dcbx_config.app[0].selector =
9159                                                 I40E_APP_SEL_ETHTYPE;
9160                         hw->local_dcbx_config.app[0].priority = 3;
9161                         hw->local_dcbx_config.app[0].protocolid =
9162                                                 I40E_APP_PROTOID_FCOE;
9163                         ret = i40e_set_dcb_config(hw);
9164                         if (ret) {
9165                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9166                                         " err = %d, aq_err = %d.", ret,
9167                                           hw->aq.asq_last_status);
9168                                 return -ENOSYS;
9169                         }
9170                 } else {
9171                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9172                                           " aq_err = %d.", ret,
9173                                           hw->aq.asq_last_status);
9174                         return -ENOTSUP;
9175                 }
9176         } else {
9177                 ret = i40e_aq_start_lldp(hw, NULL);
9178                 if (ret != I40E_SUCCESS)
9179                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9180
9181                 ret = i40e_init_dcb(hw);
9182                 if (!ret) {
9183                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9184                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9185                                                   " DCBX offload.");
9186                                 return -ENOTSUP;
9187                         }
9188                 } else {
9189                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9190                                           " aq_err = %d.", ret,
9191                                           hw->aq.asq_last_status);
9192                         return -ENOTSUP;
9193                 }
9194         }
9195         return 0;
9196 }
9197
9198 /*
9199  * i40e_dcb_setup - setup dcb related config
9200  * @dev: device being configured
9201  *
9202  * Returns 0 on success, negative value on failure
9203  */
9204 static int
9205 i40e_dcb_setup(struct rte_eth_dev *dev)
9206 {
9207         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9208         struct i40e_dcbx_config dcb_cfg;
9209         uint8_t tc_map = 0;
9210         int ret = 0;
9211
9212         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9213                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9214                 return -ENOTSUP;
9215         }
9216
9217         if (pf->vf_num != 0)
9218                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9219
9220         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9221         if (ret) {
9222                 PMD_INIT_LOG(ERR, "invalid dcb config");
9223                 return -EINVAL;
9224         }
9225         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9226         if (ret) {
9227                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9228                 return -ENOSYS;
9229         }
9230
9231         return 0;
9232 }
9233
9234 static int
9235 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9236                       struct rte_eth_dcb_info *dcb_info)
9237 {
9238         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9239         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9240         struct i40e_vsi *vsi = pf->main_vsi;
9241         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9242         uint16_t bsf, tc_mapping;
9243         int i, j = 0;
9244
9245         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9246                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9247         else
9248                 dcb_info->nb_tcs = 1;
9249         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9250                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9251         for (i = 0; i < dcb_info->nb_tcs; i++)
9252                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9253
9254         /* get queue mapping if vmdq is disabled */
9255         if (!pf->nb_cfg_vmdq_vsi) {
9256                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9257                         if (!(vsi->enabled_tc & (1 << i)))
9258                                 continue;
9259                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9260                         dcb_info->tc_queue.tc_rxq[j][i].base =
9261                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9262                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9263                         dcb_info->tc_queue.tc_txq[j][i].base =
9264                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9265                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9266                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9267                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9268                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9269                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9270                 }
9271                 return 0;
9272         }
9273
9274         /* get queue mapping if vmdq is enabled */
9275         do {
9276                 vsi = pf->vmdq[j].vsi;
9277                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9278                         if (!(vsi->enabled_tc & (1 << i)))
9279                                 continue;
9280                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9281                         dcb_info->tc_queue.tc_rxq[j][i].base =
9282                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9283                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9284                         dcb_info->tc_queue.tc_txq[j][i].base =
9285                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9286                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9287                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9288                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9289                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9290                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9291                 }
9292                 j++;
9293         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9294         return 0;
9295 }
9296
9297 static int
9298 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9299 {
9300         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9301         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9302         uint16_t interval =
9303                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9304         uint16_t msix_intr;
9305
9306         msix_intr = intr_handle->intr_vec[queue_id];
9307         if (msix_intr == I40E_MISC_VEC_ID)
9308                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9309                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9310                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9311                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9312                                (interval <<
9313                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9314         else
9315                 I40E_WRITE_REG(hw,
9316                                I40E_PFINT_DYN_CTLN(msix_intr -
9317                                                    I40E_RX_VEC_START),
9318                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9319                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9320                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9321                                (interval <<
9322                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9323
9324         I40E_WRITE_FLUSH(hw);
9325         rte_intr_enable(&dev->pci_dev->intr_handle);
9326
9327         return 0;
9328 }
9329
9330 static int
9331 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9332 {
9333         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9334         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9335         uint16_t msix_intr;
9336
9337         msix_intr = intr_handle->intr_vec[queue_id];
9338         if (msix_intr == I40E_MISC_VEC_ID)
9339                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9340         else
9341                 I40E_WRITE_REG(hw,
9342                                I40E_PFINT_DYN_CTLN(msix_intr -
9343                                                    I40E_RX_VEC_START),
9344                                0);
9345         I40E_WRITE_FLUSH(hw);
9346
9347         return 0;
9348 }
9349
9350 static int i40e_get_regs(struct rte_eth_dev *dev,
9351                          struct rte_dev_reg_info *regs)
9352 {
9353         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9354         uint32_t *ptr_data = regs->data;
9355         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9356         const struct i40e_reg_info *reg_info;
9357
9358         if (ptr_data == NULL) {
9359                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9360                 regs->width = sizeof(uint32_t);
9361                 return 0;
9362         }
9363
9364         /* The first few registers have to be read using AQ operations */
9365         reg_idx = 0;
9366         while (i40e_regs_adminq[reg_idx].name) {
9367                 reg_info = &i40e_regs_adminq[reg_idx++];
9368                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9369                         for (arr_idx2 = 0;
9370                                         arr_idx2 <= reg_info->count2;
9371                                         arr_idx2++) {
9372                                 reg_offset = arr_idx * reg_info->stride1 +
9373                                         arr_idx2 * reg_info->stride2;
9374                                 reg_offset += reg_info->base_addr;
9375                                 ptr_data[reg_offset >> 2] =
9376                                         i40e_read_rx_ctl(hw, reg_offset);
9377                         }
9378         }
9379
9380         /* The remaining registers can be read using primitives */
9381         reg_idx = 0;
9382         while (i40e_regs_others[reg_idx].name) {
9383                 reg_info = &i40e_regs_others[reg_idx++];
9384                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9385                         for (arr_idx2 = 0;
9386                                         arr_idx2 <= reg_info->count2;
9387                                         arr_idx2++) {
9388                                 reg_offset = arr_idx * reg_info->stride1 +
9389                                         arr_idx2 * reg_info->stride2;
9390                                 reg_offset += reg_info->base_addr;
9391                                 ptr_data[reg_offset >> 2] =
9392                                         I40E_READ_REG(hw, reg_offset);
9393                         }
9394         }
9395
9396         return 0;
9397 }
9398
9399 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9400 {
9401         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9402
9403         /* Convert word count to byte count */
9404         return hw->nvm.sr_size << 1;
9405 }
9406
9407 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9408                            struct rte_dev_eeprom_info *eeprom)
9409 {
9410         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9411         uint16_t *data = eeprom->data;
9412         uint16_t offset, length, cnt_words;
9413         int ret_code;
9414
9415         offset = eeprom->offset >> 1;
9416         length = eeprom->length >> 1;
9417         cnt_words = length;
9418
9419         if (offset > hw->nvm.sr_size ||
9420                 offset + length > hw->nvm.sr_size) {
9421                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9422                 return -EINVAL;
9423         }
9424
9425         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9426
9427         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9428         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9429                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9430                 return -EIO;
9431         }
9432
9433         return 0;
9434 }
9435
9436 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9437                                       struct ether_addr *mac_addr)
9438 {
9439         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9440
9441         if (!is_valid_assigned_ether_addr(mac_addr)) {
9442                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9443                 return;
9444         }
9445
9446         /* Flags: 0x3 updates port address */
9447         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9448 }
9449
9450 static int
9451 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9452 {
9453         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9454         struct rte_eth_dev_data *dev_data = pf->dev_data;
9455         uint32_t frame_size = mtu + ETHER_HDR_LEN
9456                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9457         int ret = 0;
9458
9459         /* check if mtu is within the allowed range */
9460         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9461                 return -EINVAL;
9462
9463         /* mtu setting is forbidden if port is start */
9464         if (dev_data->dev_started) {
9465                 PMD_DRV_LOG(ERR,
9466                             "port %d must be stopped before configuration\n",
9467                             dev_data->port_id);
9468                 return -EBUSY;
9469         }
9470
9471         if (frame_size > ETHER_MAX_LEN)
9472                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9473         else
9474                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9475
9476         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9477
9478         return ret;
9479 }