4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
53 #include <rte_tailq.h>
55 #include "i40e_logs.h"
56 #include "base/i40e_prototype.h"
57 #include "base/i40e_adminq_cmd.h"
58 #include "base/i40e_type.h"
59 #include "base/i40e_register.h"
60 #include "base/i40e_dcb.h"
61 #include "i40e_ethdev.h"
62 #include "i40e_rxtx.h"
64 #include "i40e_regs.h"
66 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
67 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
69 #define I40E_CLEAR_PXE_WAIT_MS 200
71 /* Maximun number of capability elements */
72 #define I40E_MAX_CAP_ELE_NUM 128
74 /* Wait count and inteval */
75 #define I40E_CHK_Q_ENA_COUNT 1000
76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
78 /* Maximun number of VSI */
79 #define I40E_MAX_NUM_VSIS (384UL)
81 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
83 /* Flow control default timer */
84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
86 /* Flow control default high water */
87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
89 /* Flow control default low water */
90 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
92 /* Flow control enable fwd bit */
93 #define I40E_PRTMAC_FWD_CTRL 0x00000001
95 /* Receive Packet Buffer size */
96 #define I40E_RXPBSIZE (968 * 1024)
99 #define I40E_KILOSHIFT 10
101 /* Receive Average Packet Size in Byte*/
102 #define I40E_PACKET_AVERAGE_SIZE 128
104 /* Mask of PF interrupt causes */
105 #define I40E_PFINT_ICR0_ENA_MASK ( \
106 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
107 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
108 I40E_PFINT_ICR0_ENA_GRST_MASK | \
109 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
110 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
111 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
112 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
113 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
114 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
115 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
117 #define I40E_FLOW_TYPES ( \
118 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
119 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
120 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
123 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
128 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
130 /* Additional timesync values. */
131 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
132 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
133 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
134 #define I40E_PRTTSYN_TSYNENA 0x80000000
135 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
136 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
138 #define I40E_MAX_PERCENT 100
139 #define I40E_DEFAULT_DCB_APP_NUM 1
140 #define I40E_DEFAULT_DCB_APP_PRIO 3
142 #define I40E_INSET_NONE 0x00000000000000000ULL
145 #define I40E_INSET_DMAC 0x0000000000000001ULL
146 #define I40E_INSET_SMAC 0x0000000000000002ULL
147 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
148 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
149 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
152 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
153 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
154 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
155 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
156 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
157 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
158 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
160 /* bit 16 ~ bit 31 */
161 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
162 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
163 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
164 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
165 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
166 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
167 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
168 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
170 /* bit 32 ~ bit 47, tunnel fields */
171 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
172 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
173 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
174 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
175 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
176 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
178 /* bit 48 ~ bit 55 */
179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
181 /* bit 56 ~ bit 63, Flex Payload */
182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
190 #define I40E_INSET_FLEX_PAYLOAD \
191 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
192 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
193 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
194 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
197 * Below are values for writing un-exposed registers suggested
200 /* Destination MAC address */
201 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
202 /* Source MAC address */
203 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
205 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0200000000000000ULL
206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
207 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
208 /* Single VLAN tag in the inner L2 header */
209 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
210 /* Source IPv4 address */
211 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
212 /* Destination IPv4 address */
213 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
214 /* IPv4 Type of Service (TOS) */
215 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
217 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
218 /* IPv4 Time to Live */
219 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
220 /* Source IPv6 address */
221 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
222 /* Destination IPv6 address */
223 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
224 /* IPv6 Traffic Class (TC) */
225 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
226 /* IPv6 Next Header */
227 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
229 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
231 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
232 /* Destination L4 port */
233 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
234 /* SCTP verification tag */
235 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
236 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
237 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
238 /* Source port of tunneling UDP */
239 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
240 /* Destination port of tunneling UDP */
241 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
242 /* UDP Tunneling ID, NVGRE/GRE key */
243 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
244 /* Last ether type */
245 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
246 /* Tunneling outer destination IPv4 address */
247 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
248 /* Tunneling outer destination IPv6 address */
249 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
250 /* 1st word of flex payload */
251 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
252 /* 2nd word of flex payload */
253 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
254 /* 3rd word of flex payload */
255 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
256 /* 4th word of flex payload */
257 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
258 /* 5th word of flex payload */
259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
260 /* 6th word of flex payload */
261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
262 /* 7th word of flex payload */
263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
264 /* 8th word of flex payload */
265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
266 /* all 8 words flex payload */
267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
268 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
270 #define I40E_TRANSLATE_INSET 0
271 #define I40E_TRANSLATE_REG 1
273 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
274 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
275 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
276 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
277 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
278 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
280 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
281 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
282 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
283 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
285 /* PCI offset for querying capability */
286 #define PCI_DEV_CAP_REG 0xA4
287 /* PCI offset for enabling/disabling Extended Tag */
288 #define PCI_DEV_CTRL_REG 0xA8
289 /* Bit mask of Extended Tag capability */
290 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
291 /* Bit shift of Extended Tag enable/disable */
292 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
293 /* Bit mask of Extended Tag enable/disable */
294 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
296 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
297 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
298 static int i40e_dev_configure(struct rte_eth_dev *dev);
299 static int i40e_dev_start(struct rte_eth_dev *dev);
300 static void i40e_dev_stop(struct rte_eth_dev *dev);
301 static void i40e_dev_close(struct rte_eth_dev *dev);
302 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
303 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
304 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
305 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
306 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
307 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
308 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
309 struct rte_eth_stats *stats);
310 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
311 struct rte_eth_xstat *xstats, unsigned n);
312 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
313 struct rte_eth_xstat_name *xstats_names,
315 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
316 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
320 static void i40e_dev_info_get(struct rte_eth_dev *dev,
321 struct rte_eth_dev_info *dev_info);
322 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
325 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
326 enum rte_vlan_type vlan_type,
328 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
329 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
332 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
333 static int i40e_dev_led_on(struct rte_eth_dev *dev);
334 static int i40e_dev_led_off(struct rte_eth_dev *dev);
335 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
336 struct rte_eth_fc_conf *fc_conf);
337 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
338 struct rte_eth_fc_conf *fc_conf);
339 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
340 struct rte_eth_pfc_conf *pfc_conf);
341 static void i40e_macaddr_add(struct rte_eth_dev *dev,
342 struct ether_addr *mac_addr,
345 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
346 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
347 struct rte_eth_rss_reta_entry64 *reta_conf,
349 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
350 struct rte_eth_rss_reta_entry64 *reta_conf,
353 static int i40e_get_cap(struct i40e_hw *hw);
354 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
355 static int i40e_pf_setup(struct i40e_pf *pf);
356 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
357 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
358 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
359 static int i40e_dcb_setup(struct rte_eth_dev *dev);
360 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
361 bool offset_loaded, uint64_t *offset, uint64_t *stat);
362 static void i40e_stat_update_48(struct i40e_hw *hw,
368 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
369 static void i40e_dev_interrupt_handler(
370 __rte_unused struct rte_intr_handle *handle, void *param);
371 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
372 uint32_t base, uint32_t num);
373 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
374 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
376 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
378 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
379 static int i40e_veb_release(struct i40e_veb *veb);
380 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
381 struct i40e_vsi *vsi);
382 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
383 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
384 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
385 struct i40e_macvlan_filter *mv_f,
387 struct ether_addr *addr);
388 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
389 struct i40e_macvlan_filter *mv_f,
392 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
393 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
394 struct rte_eth_rss_conf *rss_conf);
395 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
396 struct rte_eth_rss_conf *rss_conf);
397 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
398 struct rte_eth_udp_tunnel *udp_tunnel);
399 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
400 struct rte_eth_udp_tunnel *udp_tunnel);
401 static void i40e_filter_input_set_init(struct i40e_pf *pf);
402 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
403 struct rte_eth_ethertype_filter *filter,
405 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
406 enum rte_filter_op filter_op,
408 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
409 enum rte_filter_type filter_type,
410 enum rte_filter_op filter_op,
412 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
413 struct rte_eth_dcb_info *dcb_info);
414 static void i40e_configure_registers(struct i40e_hw *hw);
415 static void i40e_hw_init(struct rte_eth_dev *dev);
416 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
417 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
418 struct rte_eth_mirror_conf *mirror_conf,
419 uint8_t sw_id, uint8_t on);
420 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
422 static int i40e_timesync_enable(struct rte_eth_dev *dev);
423 static int i40e_timesync_disable(struct rte_eth_dev *dev);
424 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
425 struct timespec *timestamp,
427 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
428 struct timespec *timestamp);
429 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
431 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
433 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
434 struct timespec *timestamp);
435 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
436 const struct timespec *timestamp);
438 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
440 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
443 static int i40e_get_regs(struct rte_eth_dev *dev,
444 struct rte_dev_reg_info *regs);
446 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
448 static int i40e_get_eeprom(struct rte_eth_dev *dev,
449 struct rte_dev_eeprom_info *eeprom);
451 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
452 struct ether_addr *mac_addr);
454 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
456 static const struct rte_pci_id pci_id_i40e_map[] = {
457 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
458 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
459 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
460 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
461 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
462 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
463 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
464 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
465 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
466 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
467 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
468 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
469 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
470 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
471 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
472 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
473 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
474 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
475 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
476 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
477 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_I_X722) },
478 { .vendor_id = 0, /* sentinel */ },
481 static const struct eth_dev_ops i40e_eth_dev_ops = {
482 .dev_configure = i40e_dev_configure,
483 .dev_start = i40e_dev_start,
484 .dev_stop = i40e_dev_stop,
485 .dev_close = i40e_dev_close,
486 .promiscuous_enable = i40e_dev_promiscuous_enable,
487 .promiscuous_disable = i40e_dev_promiscuous_disable,
488 .allmulticast_enable = i40e_dev_allmulticast_enable,
489 .allmulticast_disable = i40e_dev_allmulticast_disable,
490 .dev_set_link_up = i40e_dev_set_link_up,
491 .dev_set_link_down = i40e_dev_set_link_down,
492 .link_update = i40e_dev_link_update,
493 .stats_get = i40e_dev_stats_get,
494 .xstats_get = i40e_dev_xstats_get,
495 .xstats_get_names = i40e_dev_xstats_get_names,
496 .stats_reset = i40e_dev_stats_reset,
497 .xstats_reset = i40e_dev_stats_reset,
498 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
499 .dev_infos_get = i40e_dev_info_get,
500 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
501 .vlan_filter_set = i40e_vlan_filter_set,
502 .vlan_tpid_set = i40e_vlan_tpid_set,
503 .vlan_offload_set = i40e_vlan_offload_set,
504 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
505 .vlan_pvid_set = i40e_vlan_pvid_set,
506 .rx_queue_start = i40e_dev_rx_queue_start,
507 .rx_queue_stop = i40e_dev_rx_queue_stop,
508 .tx_queue_start = i40e_dev_tx_queue_start,
509 .tx_queue_stop = i40e_dev_tx_queue_stop,
510 .rx_queue_setup = i40e_dev_rx_queue_setup,
511 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
512 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
513 .rx_queue_release = i40e_dev_rx_queue_release,
514 .rx_queue_count = i40e_dev_rx_queue_count,
515 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
516 .tx_queue_setup = i40e_dev_tx_queue_setup,
517 .tx_queue_release = i40e_dev_tx_queue_release,
518 .dev_led_on = i40e_dev_led_on,
519 .dev_led_off = i40e_dev_led_off,
520 .flow_ctrl_get = i40e_flow_ctrl_get,
521 .flow_ctrl_set = i40e_flow_ctrl_set,
522 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
523 .mac_addr_add = i40e_macaddr_add,
524 .mac_addr_remove = i40e_macaddr_remove,
525 .reta_update = i40e_dev_rss_reta_update,
526 .reta_query = i40e_dev_rss_reta_query,
527 .rss_hash_update = i40e_dev_rss_hash_update,
528 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
529 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
530 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
531 .filter_ctrl = i40e_dev_filter_ctrl,
532 .rxq_info_get = i40e_rxq_info_get,
533 .txq_info_get = i40e_txq_info_get,
534 .mirror_rule_set = i40e_mirror_rule_set,
535 .mirror_rule_reset = i40e_mirror_rule_reset,
536 .timesync_enable = i40e_timesync_enable,
537 .timesync_disable = i40e_timesync_disable,
538 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
539 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
540 .get_dcb_info = i40e_dev_get_dcb_info,
541 .timesync_adjust_time = i40e_timesync_adjust_time,
542 .timesync_read_time = i40e_timesync_read_time,
543 .timesync_write_time = i40e_timesync_write_time,
544 .get_reg = i40e_get_regs,
545 .get_eeprom_length = i40e_get_eeprom_length,
546 .get_eeprom = i40e_get_eeprom,
547 .mac_addr_set = i40e_set_default_mac_addr,
548 .mtu_set = i40e_dev_mtu_set,
551 /* store statistics names and its offset in stats structure */
552 struct rte_i40e_xstats_name_off {
553 char name[RTE_ETH_XSTATS_NAME_SIZE];
557 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
558 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
559 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
560 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
561 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
562 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
563 rx_unknown_protocol)},
564 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
565 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
566 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
567 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
570 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
571 sizeof(rte_i40e_stats_strings[0]))
573 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
574 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
575 tx_dropped_link_down)},
576 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
577 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
579 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
580 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
582 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
584 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
586 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
587 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
588 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
589 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
590 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
591 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
593 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
595 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
597 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
599 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
601 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
603 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
605 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
607 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
608 mac_short_packet_dropped)},
609 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
611 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
612 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
613 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
615 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
617 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
619 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
621 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
623 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
625 {"rx_flow_director_atr_match_packets",
626 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
627 {"rx_flow_director_sb_match_packets",
628 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
629 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
631 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
633 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
635 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
639 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
640 sizeof(rte_i40e_hw_port_strings[0]))
642 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
643 {"xon_packets", offsetof(struct i40e_hw_port_stats,
645 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
649 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
650 sizeof(rte_i40e_rxq_prio_strings[0]))
652 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
653 {"xon_packets", offsetof(struct i40e_hw_port_stats,
655 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
657 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
658 priority_xon_2_xoff)},
661 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
662 sizeof(rte_i40e_txq_prio_strings[0]))
664 static struct eth_driver rte_i40e_pmd = {
666 .name = "rte_i40e_pmd",
667 .id_table = pci_id_i40e_map,
668 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
669 RTE_PCI_DRV_DETACHABLE,
670 .probe = rte_eth_dev_pci_probe,
671 .remove = rte_eth_dev_pci_remove,
673 .eth_dev_init = eth_i40e_dev_init,
674 .eth_dev_uninit = eth_i40e_dev_uninit,
675 .dev_private_size = sizeof(struct i40e_adapter),
679 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
680 struct rte_eth_link *link)
682 struct rte_eth_link *dst = link;
683 struct rte_eth_link *src = &(dev->data->dev_link);
685 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
686 *(uint64_t *)src) == 0)
693 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
694 struct rte_eth_link *link)
696 struct rte_eth_link *dst = &(dev->data->dev_link);
697 struct rte_eth_link *src = link;
699 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
700 *(uint64_t *)src) == 0)
706 DRIVER_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
707 DRIVER_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
710 * Initialize registers for flexible payload, which should be set by NVM.
711 * This should be removed from code once it is fixed in NVM.
713 #ifndef I40E_GLQF_ORT
714 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
716 #ifndef I40E_GLQF_PIT
717 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
720 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
722 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
723 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
724 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
725 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
726 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
727 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
728 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
729 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
730 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
731 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
733 /* GLQF_PIT Registers */
734 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
735 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
738 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
741 * Add a ethertype filter to drop all flow control frames transmitted
745 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
747 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
748 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
749 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
750 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
753 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
754 I40E_FLOW_CONTROL_ETHERTYPE, flags,
755 pf->main_vsi_seid, 0,
758 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
759 " frames from VSIs.");
763 floating_veb_list_handler(__rte_unused const char *key,
764 const char *floating_veb_value,
768 unsigned int count = 0;
771 bool *vf_floating_veb = opaque;
773 while (isblank(*floating_veb_value))
774 floating_veb_value++;
776 /* Reset floating VEB configuration for VFs */
777 for (idx = 0; idx < I40E_MAX_VF; idx++)
778 vf_floating_veb[idx] = false;
782 while (isblank(*floating_veb_value))
783 floating_veb_value++;
784 if (*floating_veb_value == '\0')
787 idx = strtoul(floating_veb_value, &end, 10);
788 if (errno || end == NULL)
790 while (isblank(*end))
794 } else if ((*end == ';') || (*end == '\0')) {
796 if (min == I40E_MAX_VF)
798 if (max >= I40E_MAX_VF)
799 max = I40E_MAX_VF - 1;
800 for (idx = min; idx <= max; idx++) {
801 vf_floating_veb[idx] = true;
808 floating_veb_value = end + 1;
809 } while (*end != '\0');
818 config_vf_floating_veb(struct rte_devargs *devargs,
819 uint16_t floating_veb,
820 bool *vf_floating_veb)
822 struct rte_kvargs *kvlist;
824 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
828 /* All the VFs attach to the floating VEB by default
829 * when the floating VEB is enabled.
831 for (i = 0; i < I40E_MAX_VF; i++)
832 vf_floating_veb[i] = true;
837 kvlist = rte_kvargs_parse(devargs->args, NULL);
841 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
842 rte_kvargs_free(kvlist);
845 /* When the floating_veb_list parameter exists, all the VFs
846 * will attach to the legacy VEB firstly, then configure VFs
847 * to the floating VEB according to the floating_veb_list.
849 if (rte_kvargs_process(kvlist, floating_veb_list,
850 floating_veb_list_handler,
851 vf_floating_veb) < 0) {
852 rte_kvargs_free(kvlist);
855 rte_kvargs_free(kvlist);
859 i40e_check_floating_handler(__rte_unused const char *key,
861 __rte_unused void *opaque)
863 if (strcmp(value, "1"))
870 is_floating_veb_supported(struct rte_devargs *devargs)
872 struct rte_kvargs *kvlist;
873 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
878 kvlist = rte_kvargs_parse(devargs->args, NULL);
882 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
883 rte_kvargs_free(kvlist);
886 /* Floating VEB is enabled when there's key-value:
887 * enable_floating_veb=1
889 if (rte_kvargs_process(kvlist, floating_veb_key,
890 i40e_check_floating_handler, NULL) < 0) {
891 rte_kvargs_free(kvlist);
894 rte_kvargs_free(kvlist);
900 config_floating_veb(struct rte_eth_dev *dev)
902 struct rte_pci_device *pci_dev = dev->pci_dev;
903 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
904 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
906 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
908 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
909 pf->floating_veb = is_floating_veb_supported(pci_dev->devargs);
910 config_vf_floating_veb(pci_dev->devargs, pf->floating_veb,
911 pf->floating_veb_list);
913 pf->floating_veb = false;
918 eth_i40e_dev_init(struct rte_eth_dev *dev)
920 struct rte_pci_device *pci_dev;
921 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
922 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
923 struct i40e_vsi *vsi;
928 PMD_INIT_FUNC_TRACE();
930 dev->dev_ops = &i40e_eth_dev_ops;
931 dev->rx_pkt_burst = i40e_recv_pkts;
932 dev->tx_pkt_burst = i40e_xmit_pkts;
934 /* for secondary processes, we don't initialise any further as primary
935 * has already done this work. Only check we don't need a different
937 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
938 i40e_set_rx_function(dev);
939 i40e_set_tx_function(dev);
942 pci_dev = dev->pci_dev;
944 rte_eth_copy_pci_info(dev, pci_dev);
946 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
947 pf->adapter->eth_dev = dev;
948 pf->dev_data = dev->data;
950 hw->back = I40E_PF_TO_ADAPTER(pf);
951 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
953 PMD_INIT_LOG(ERR, "Hardware is not available, "
954 "as address is NULL");
958 hw->vendor_id = pci_dev->id.vendor_id;
959 hw->device_id = pci_dev->id.device_id;
960 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
961 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
962 hw->bus.device = pci_dev->addr.devid;
963 hw->bus.func = pci_dev->addr.function;
964 hw->adapter_stopped = 0;
966 /* Make sure all is clean before doing PF reset */
969 /* Initialize the hardware */
972 /* Reset here to make sure all is clean for each PF */
973 ret = i40e_pf_reset(hw);
975 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
979 /* Initialize the shared code (base driver) */
980 ret = i40e_init_shared_code(hw);
982 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
987 * To work around the NVM issue,initialize registers
988 * for flexible payload by software.
989 * It should be removed once issues are fixed in NVM.
991 i40e_flex_payload_reg_init(hw);
993 /* Initialize the input set for filters (hash and fd) to default value */
994 i40e_filter_input_set_init(pf);
996 /* Initialize the parameters for adminq */
997 i40e_init_adminq_parameter(hw);
998 ret = i40e_init_adminq(hw);
999 if (ret != I40E_SUCCESS) {
1000 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1003 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1004 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1005 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1006 ((hw->nvm.version >> 12) & 0xf),
1007 ((hw->nvm.version >> 4) & 0xff),
1008 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1010 /* Need the special FW version to support floating VEB */
1011 config_floating_veb(dev);
1012 /* Clear PXE mode */
1013 i40e_clear_pxe_mode(hw);
1016 * On X710, performance number is far from the expectation on recent
1017 * firmware versions. The fix for this issue may not be integrated in
1018 * the following firmware version. So the workaround in software driver
1019 * is needed. It needs to modify the initial values of 3 internal only
1020 * registers. Note that the workaround can be removed when it is fixed
1021 * in firmware in the future.
1023 i40e_configure_registers(hw);
1025 /* Get hw capabilities */
1026 ret = i40e_get_cap(hw);
1027 if (ret != I40E_SUCCESS) {
1028 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1029 goto err_get_capabilities;
1032 /* Initialize parameters for PF */
1033 ret = i40e_pf_parameter_init(dev);
1035 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1036 goto err_parameter_init;
1039 /* Initialize the queue management */
1040 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1042 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1043 goto err_qp_pool_init;
1045 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1046 hw->func_caps.num_msix_vectors - 1);
1048 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1049 goto err_msix_pool_init;
1052 /* Initialize lan hmc */
1053 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1054 hw->func_caps.num_rx_qp, 0, 0);
1055 if (ret != I40E_SUCCESS) {
1056 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1057 goto err_init_lan_hmc;
1060 /* Configure lan hmc */
1061 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1062 if (ret != I40E_SUCCESS) {
1063 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1064 goto err_configure_lan_hmc;
1067 /* Get and check the mac address */
1068 i40e_get_mac_addr(hw, hw->mac.addr);
1069 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1070 PMD_INIT_LOG(ERR, "mac address is not valid");
1072 goto err_get_mac_addr;
1074 /* Copy the permanent MAC address */
1075 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1076 (struct ether_addr *) hw->mac.perm_addr);
1078 /* Disable flow control */
1079 hw->fc.requested_mode = I40E_FC_NONE;
1080 i40e_set_fc(hw, &aq_fail, TRUE);
1082 /* Set the global registers with default ether type value */
1083 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1084 if (ret != I40E_SUCCESS) {
1085 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1087 goto err_setup_pf_switch;
1090 /* PF setup, which includes VSI setup */
1091 ret = i40e_pf_setup(pf);
1093 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1094 goto err_setup_pf_switch;
1097 /* reset all stats of the device, including pf and main vsi */
1098 i40e_dev_stats_reset(dev);
1102 /* Disable double vlan by default */
1103 i40e_vsi_config_double_vlan(vsi, FALSE);
1105 if (!vsi->max_macaddrs)
1106 len = ETHER_ADDR_LEN;
1108 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1110 /* Should be after VSI initialized */
1111 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1112 if (!dev->data->mac_addrs) {
1113 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1114 "for storing mac address");
1117 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1118 &dev->data->mac_addrs[0]);
1120 /* initialize pf host driver to setup SRIOV resource if applicable */
1121 i40e_pf_host_init(dev);
1123 /* register callback func to eal lib */
1124 rte_intr_callback_register(&(pci_dev->intr_handle),
1125 i40e_dev_interrupt_handler, (void *)dev);
1127 /* configure and enable device interrupt */
1128 i40e_pf_config_irq0(hw, TRUE);
1129 i40e_pf_enable_irq0(hw);
1131 /* enable uio intr after callback register */
1132 rte_intr_enable(&(pci_dev->intr_handle));
1134 * Add an ethertype filter to drop all flow control frames transmitted
1135 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1138 i40e_add_tx_flow_control_drop_filter(pf);
1140 /* Set the max frame size to 0x2600 by default,
1141 * in case other drivers changed the default value.
1143 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1145 /* initialize mirror rule list */
1146 TAILQ_INIT(&pf->mirror_list);
1148 /* Init dcb to sw mode by default */
1149 ret = i40e_dcb_init_configure(dev, TRUE);
1150 if (ret != I40E_SUCCESS) {
1151 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1152 pf->flags &= ~I40E_FLAG_DCB;
1158 i40e_vsi_release(pf->main_vsi);
1159 err_setup_pf_switch:
1161 err_configure_lan_hmc:
1162 (void)i40e_shutdown_lan_hmc(hw);
1164 i40e_res_pool_destroy(&pf->msix_pool);
1166 i40e_res_pool_destroy(&pf->qp_pool);
1169 err_get_capabilities:
1170 (void)i40e_shutdown_adminq(hw);
1176 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1178 struct rte_pci_device *pci_dev;
1180 struct i40e_filter_control_settings settings;
1182 uint8_t aq_fail = 0;
1184 PMD_INIT_FUNC_TRACE();
1186 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1189 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1190 pci_dev = dev->pci_dev;
1192 if (hw->adapter_stopped == 0)
1193 i40e_dev_close(dev);
1195 dev->dev_ops = NULL;
1196 dev->rx_pkt_burst = NULL;
1197 dev->tx_pkt_burst = NULL;
1200 ret = i40e_aq_stop_lldp(hw, true, NULL);
1201 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1202 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1204 /* Clear PXE mode */
1205 i40e_clear_pxe_mode(hw);
1207 /* Unconfigure filter control */
1208 memset(&settings, 0, sizeof(settings));
1209 ret = i40e_set_filter_control(hw, &settings);
1211 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1214 /* Disable flow control */
1215 hw->fc.requested_mode = I40E_FC_NONE;
1216 i40e_set_fc(hw, &aq_fail, TRUE);
1218 /* uninitialize pf host driver */
1219 i40e_pf_host_uninit(dev);
1221 rte_free(dev->data->mac_addrs);
1222 dev->data->mac_addrs = NULL;
1224 /* disable uio intr before callback unregister */
1225 rte_intr_disable(&(pci_dev->intr_handle));
1227 /* register callback func to eal lib */
1228 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1229 i40e_dev_interrupt_handler, (void *)dev);
1235 i40e_dev_configure(struct rte_eth_dev *dev)
1237 struct i40e_adapter *ad =
1238 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1239 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1240 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1243 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1244 * bulk allocation or vector Rx preconditions we will reset it.
1246 ad->rx_bulk_alloc_allowed = true;
1247 ad->rx_vec_allowed = true;
1248 ad->tx_simple_allowed = true;
1249 ad->tx_vec_allowed = true;
1251 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1252 ret = i40e_fdir_setup(pf);
1253 if (ret != I40E_SUCCESS) {
1254 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1257 ret = i40e_fdir_configure(dev);
1259 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1263 i40e_fdir_teardown(pf);
1265 ret = i40e_dev_init_vlan(dev);
1270 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1271 * RSS setting have different requirements.
1272 * General PMD driver call sequence are NIC init, configure,
1273 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1274 * will try to lookup the VSI that specific queue belongs to if VMDQ
1275 * applicable. So, VMDQ setting has to be done before
1276 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1277 * For RSS setting, it will try to calculate actual configured RX queue
1278 * number, which will be available after rx_queue_setup(). dev_start()
1279 * function is good to place RSS setup.
1281 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1282 ret = i40e_vmdq_setup(dev);
1287 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1288 ret = i40e_dcb_setup(dev);
1290 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1298 /* need to release vmdq resource if exists */
1299 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1300 i40e_vsi_release(pf->vmdq[i].vsi);
1301 pf->vmdq[i].vsi = NULL;
1306 /* need to release fdir resource if exists */
1307 i40e_fdir_teardown(pf);
1312 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1314 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1315 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1316 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1317 uint16_t msix_vect = vsi->msix_intr;
1320 for (i = 0; i < vsi->nb_qps; i++) {
1321 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1322 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1326 if (vsi->type != I40E_VSI_SRIOV) {
1327 if (!rte_intr_allow_others(intr_handle)) {
1328 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1329 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1331 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1334 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1335 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1337 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1342 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1343 vsi->user_param + (msix_vect - 1);
1345 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1346 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1348 I40E_WRITE_FLUSH(hw);
1352 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1353 int base_queue, int nb_queue)
1357 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1359 /* Bind all RX queues to allocated MSIX interrupt */
1360 for (i = 0; i < nb_queue; i++) {
1361 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1362 I40E_QINT_RQCTL_ITR_INDX_MASK |
1363 ((base_queue + i + 1) <<
1364 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1365 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1366 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1368 if (i == nb_queue - 1)
1369 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1370 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1373 /* Write first RX queue to Link list register as the head element */
1374 if (vsi->type != I40E_VSI_SRIOV) {
1376 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1378 if (msix_vect == I40E_MISC_VEC_ID) {
1379 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1381 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1383 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1385 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1388 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1390 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1392 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1394 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1401 if (msix_vect == I40E_MISC_VEC_ID) {
1403 I40E_VPINT_LNKLST0(vsi->user_param),
1405 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1407 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1409 /* num_msix_vectors_vf needs to minus irq0 */
1410 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1411 vsi->user_param + (msix_vect - 1);
1413 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1415 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1417 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1421 I40E_WRITE_FLUSH(hw);
1425 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1427 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1428 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1429 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1430 uint16_t msix_vect = vsi->msix_intr;
1431 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1432 uint16_t queue_idx = 0;
1437 for (i = 0; i < vsi->nb_qps; i++) {
1438 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1439 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1442 /* INTENA flag is not auto-cleared for interrupt */
1443 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1444 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1445 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1446 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1447 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1449 /* VF bind interrupt */
1450 if (vsi->type == I40E_VSI_SRIOV) {
1451 __vsi_queues_bind_intr(vsi, msix_vect,
1452 vsi->base_queue, vsi->nb_qps);
1456 /* PF & VMDq bind interrupt */
1457 if (rte_intr_dp_is_en(intr_handle)) {
1458 if (vsi->type == I40E_VSI_MAIN) {
1461 } else if (vsi->type == I40E_VSI_VMDQ2) {
1462 struct i40e_vsi *main_vsi =
1463 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1464 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1469 for (i = 0; i < vsi->nb_used_qps; i++) {
1471 if (!rte_intr_allow_others(intr_handle))
1472 /* allow to share MISC_VEC_ID */
1473 msix_vect = I40E_MISC_VEC_ID;
1475 /* no enough msix_vect, map all to one */
1476 __vsi_queues_bind_intr(vsi, msix_vect,
1477 vsi->base_queue + i,
1478 vsi->nb_used_qps - i);
1479 for (; !!record && i < vsi->nb_used_qps; i++)
1480 intr_handle->intr_vec[queue_idx + i] =
1484 /* 1:1 queue/msix_vect mapping */
1485 __vsi_queues_bind_intr(vsi, msix_vect,
1486 vsi->base_queue + i, 1);
1488 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1496 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1498 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1499 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1500 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1501 uint16_t interval = i40e_calc_itr_interval(\
1502 RTE_LIBRTE_I40E_ITR_INTERVAL);
1503 uint16_t msix_intr, i;
1505 if (rte_intr_allow_others(intr_handle))
1506 for (i = 0; i < vsi->nb_msix; i++) {
1507 msix_intr = vsi->msix_intr + i;
1508 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1509 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1510 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1511 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1513 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1516 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1517 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1518 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1519 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1521 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1523 I40E_WRITE_FLUSH(hw);
1527 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1529 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1530 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1531 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1532 uint16_t msix_intr, i;
1534 if (rte_intr_allow_others(intr_handle))
1535 for (i = 0; i < vsi->nb_msix; i++) {
1536 msix_intr = vsi->msix_intr + i;
1537 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1541 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1543 I40E_WRITE_FLUSH(hw);
1546 static inline uint8_t
1547 i40e_parse_link_speeds(uint16_t link_speeds)
1549 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1551 if (link_speeds & ETH_LINK_SPEED_40G)
1552 link_speed |= I40E_LINK_SPEED_40GB;
1553 if (link_speeds & ETH_LINK_SPEED_20G)
1554 link_speed |= I40E_LINK_SPEED_20GB;
1555 if (link_speeds & ETH_LINK_SPEED_10G)
1556 link_speed |= I40E_LINK_SPEED_10GB;
1557 if (link_speeds & ETH_LINK_SPEED_1G)
1558 link_speed |= I40E_LINK_SPEED_1GB;
1559 if (link_speeds & ETH_LINK_SPEED_100M)
1560 link_speed |= I40E_LINK_SPEED_100MB;
1566 i40e_phy_conf_link(struct i40e_hw *hw,
1568 uint8_t force_speed)
1570 enum i40e_status_code status;
1571 struct i40e_aq_get_phy_abilities_resp phy_ab;
1572 struct i40e_aq_set_phy_config phy_conf;
1573 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1574 I40E_AQ_PHY_FLAG_PAUSE_RX |
1575 I40E_AQ_PHY_FLAG_PAUSE_RX |
1576 I40E_AQ_PHY_FLAG_LOW_POWER;
1577 const uint8_t advt = I40E_LINK_SPEED_40GB |
1578 I40E_LINK_SPEED_10GB |
1579 I40E_LINK_SPEED_1GB |
1580 I40E_LINK_SPEED_100MB;
1584 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1589 memset(&phy_conf, 0, sizeof(phy_conf));
1591 /* bits 0-2 use the values from get_phy_abilities_resp */
1593 abilities |= phy_ab.abilities & mask;
1595 /* update ablities and speed */
1596 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1597 phy_conf.link_speed = advt;
1599 phy_conf.link_speed = force_speed;
1601 phy_conf.abilities = abilities;
1603 /* use get_phy_abilities_resp value for the rest */
1604 phy_conf.phy_type = phy_ab.phy_type;
1605 phy_conf.eee_capability = phy_ab.eee_capability;
1606 phy_conf.eeer = phy_ab.eeer_val;
1607 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1609 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1610 phy_ab.abilities, phy_ab.link_speed);
1611 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1612 phy_conf.abilities, phy_conf.link_speed);
1614 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1618 return I40E_SUCCESS;
1622 i40e_apply_link_speed(struct rte_eth_dev *dev)
1625 uint8_t abilities = 0;
1626 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1627 struct rte_eth_conf *conf = &dev->data->dev_conf;
1629 speed = i40e_parse_link_speeds(conf->link_speeds);
1630 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1631 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1632 abilities |= I40E_AQ_PHY_AN_ENABLED;
1633 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1635 /* Skip changing speed on 40G interfaces, FW does not support */
1636 if (i40e_is_40G_device(hw->device_id)) {
1637 speed = I40E_LINK_SPEED_UNKNOWN;
1638 abilities |= I40E_AQ_PHY_AN_ENABLED;
1641 return i40e_phy_conf_link(hw, abilities, speed);
1645 i40e_dev_start(struct rte_eth_dev *dev)
1647 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1648 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1649 struct i40e_vsi *main_vsi = pf->main_vsi;
1651 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1652 uint32_t intr_vector = 0;
1654 hw->adapter_stopped = 0;
1656 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1657 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1658 dev->data->port_id);
1662 rte_intr_disable(intr_handle);
1664 if ((rte_intr_cap_multiple(intr_handle) ||
1665 !RTE_ETH_DEV_SRIOV(dev).active) &&
1666 dev->data->dev_conf.intr_conf.rxq != 0) {
1667 intr_vector = dev->data->nb_rx_queues;
1668 if (rte_intr_efd_enable(intr_handle, intr_vector))
1672 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1673 intr_handle->intr_vec =
1674 rte_zmalloc("intr_vec",
1675 dev->data->nb_rx_queues * sizeof(int),
1677 if (!intr_handle->intr_vec) {
1678 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1679 " intr_vec\n", dev->data->nb_rx_queues);
1684 /* Initialize VSI */
1685 ret = i40e_dev_rxtx_init(pf);
1686 if (ret != I40E_SUCCESS) {
1687 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1691 /* Map queues with MSIX interrupt */
1692 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1693 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1694 i40e_vsi_queues_bind_intr(main_vsi);
1695 i40e_vsi_enable_queues_intr(main_vsi);
1697 /* Map VMDQ VSI queues with MSIX interrupt */
1698 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1699 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1700 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1701 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1704 /* enable FDIR MSIX interrupt */
1705 if (pf->fdir.fdir_vsi) {
1706 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1707 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1710 /* Enable all queues which have been configured */
1711 ret = i40e_dev_switch_queues(pf, TRUE);
1712 if (ret != I40E_SUCCESS) {
1713 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1717 /* Enable receiving broadcast packets */
1718 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1719 if (ret != I40E_SUCCESS)
1720 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1722 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1723 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1725 if (ret != I40E_SUCCESS)
1726 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1729 /* Apply link configure */
1730 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1731 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1732 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1733 PMD_DRV_LOG(ERR, "Invalid link setting");
1736 ret = i40e_apply_link_speed(dev);
1737 if (I40E_SUCCESS != ret) {
1738 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1742 if (!rte_intr_allow_others(intr_handle)) {
1743 rte_intr_callback_unregister(intr_handle,
1744 i40e_dev_interrupt_handler,
1746 /* configure and enable device interrupt */
1747 i40e_pf_config_irq0(hw, FALSE);
1748 i40e_pf_enable_irq0(hw);
1750 if (dev->data->dev_conf.intr_conf.lsc != 0)
1751 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1752 " no intr multiplex\n");
1755 /* enable uio intr after callback register */
1756 rte_intr_enable(intr_handle);
1758 return I40E_SUCCESS;
1761 i40e_dev_switch_queues(pf, FALSE);
1762 i40e_dev_clear_queues(dev);
1768 i40e_dev_stop(struct rte_eth_dev *dev)
1770 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1771 struct i40e_vsi *main_vsi = pf->main_vsi;
1772 struct i40e_mirror_rule *p_mirror;
1773 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1776 /* Disable all queues */
1777 i40e_dev_switch_queues(pf, FALSE);
1779 /* un-map queues with interrupt registers */
1780 i40e_vsi_disable_queues_intr(main_vsi);
1781 i40e_vsi_queues_unbind_intr(main_vsi);
1783 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1784 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1785 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1788 if (pf->fdir.fdir_vsi) {
1789 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1790 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1792 /* Clear all queues and release memory */
1793 i40e_dev_clear_queues(dev);
1796 i40e_dev_set_link_down(dev);
1798 /* Remove all mirror rules */
1799 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1800 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1803 pf->nb_mirror_rule = 0;
1805 if (!rte_intr_allow_others(intr_handle))
1806 /* resume to the default handler */
1807 rte_intr_callback_register(intr_handle,
1808 i40e_dev_interrupt_handler,
1811 /* Clean datapath event and queue/vec mapping */
1812 rte_intr_efd_disable(intr_handle);
1813 if (intr_handle->intr_vec) {
1814 rte_free(intr_handle->intr_vec);
1815 intr_handle->intr_vec = NULL;
1820 i40e_dev_close(struct rte_eth_dev *dev)
1822 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1823 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1827 PMD_INIT_FUNC_TRACE();
1830 hw->adapter_stopped = 1;
1831 i40e_dev_free_queues(dev);
1833 /* Disable interrupt */
1834 i40e_pf_disable_irq0(hw);
1835 rte_intr_disable(&(dev->pci_dev->intr_handle));
1837 /* shutdown and destroy the HMC */
1838 i40e_shutdown_lan_hmc(hw);
1840 /* release all the existing VSIs and VEBs */
1841 i40e_fdir_teardown(pf);
1842 i40e_vsi_release(pf->main_vsi);
1844 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1845 i40e_vsi_release(pf->vmdq[i].vsi);
1846 pf->vmdq[i].vsi = NULL;
1852 /* shutdown the adminq */
1853 i40e_aq_queue_shutdown(hw, true);
1854 i40e_shutdown_adminq(hw);
1856 i40e_res_pool_destroy(&pf->qp_pool);
1857 i40e_res_pool_destroy(&pf->msix_pool);
1859 /* force a PF reset to clean anything leftover */
1860 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1861 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1862 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1863 I40E_WRITE_FLUSH(hw);
1867 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1869 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1870 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1871 struct i40e_vsi *vsi = pf->main_vsi;
1874 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1876 if (status != I40E_SUCCESS)
1877 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1879 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1881 if (status != I40E_SUCCESS)
1882 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1887 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1889 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1890 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1891 struct i40e_vsi *vsi = pf->main_vsi;
1894 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1896 if (status != I40E_SUCCESS)
1897 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1899 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1901 if (status != I40E_SUCCESS)
1902 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1906 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1908 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1909 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1910 struct i40e_vsi *vsi = pf->main_vsi;
1913 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1914 if (ret != I40E_SUCCESS)
1915 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1919 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1921 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1922 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1923 struct i40e_vsi *vsi = pf->main_vsi;
1926 if (dev->data->promiscuous == 1)
1927 return; /* must remain in all_multicast mode */
1929 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1930 vsi->seid, FALSE, NULL);
1931 if (ret != I40E_SUCCESS)
1932 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1936 * Set device link up.
1939 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1941 /* re-apply link speed setting */
1942 return i40e_apply_link_speed(dev);
1946 * Set device link down.
1949 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1951 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1952 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1953 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1955 return i40e_phy_conf_link(hw, abilities, speed);
1959 i40e_dev_link_update(struct rte_eth_dev *dev,
1960 int wait_to_complete)
1962 #define CHECK_INTERVAL 100 /* 100ms */
1963 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1964 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1965 struct i40e_link_status link_status;
1966 struct rte_eth_link link, old;
1968 unsigned rep_cnt = MAX_REPEAT_TIME;
1970 memset(&link, 0, sizeof(link));
1971 memset(&old, 0, sizeof(old));
1972 memset(&link_status, 0, sizeof(link_status));
1973 rte_i40e_dev_atomic_read_link_status(dev, &old);
1976 /* Get link status information from hardware */
1977 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1978 if (status != I40E_SUCCESS) {
1979 link.link_speed = ETH_SPEED_NUM_100M;
1980 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1981 PMD_DRV_LOG(ERR, "Failed to get link info");
1985 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1986 if (!wait_to_complete)
1989 rte_delay_ms(CHECK_INTERVAL);
1990 } while (!link.link_status && rep_cnt--);
1992 if (!link.link_status)
1995 /* i40e uses full duplex only */
1996 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1998 /* Parse the link status */
1999 switch (link_status.link_speed) {
2000 case I40E_LINK_SPEED_100MB:
2001 link.link_speed = ETH_SPEED_NUM_100M;
2003 case I40E_LINK_SPEED_1GB:
2004 link.link_speed = ETH_SPEED_NUM_1G;
2006 case I40E_LINK_SPEED_10GB:
2007 link.link_speed = ETH_SPEED_NUM_10G;
2009 case I40E_LINK_SPEED_20GB:
2010 link.link_speed = ETH_SPEED_NUM_20G;
2012 case I40E_LINK_SPEED_40GB:
2013 link.link_speed = ETH_SPEED_NUM_40G;
2016 link.link_speed = ETH_SPEED_NUM_100M;
2020 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2021 ETH_LINK_SPEED_FIXED);
2024 rte_i40e_dev_atomic_write_link_status(dev, &link);
2025 if (link.link_status == old.link_status)
2031 /* Get all the statistics of a VSI */
2033 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2035 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2036 struct i40e_eth_stats *nes = &vsi->eth_stats;
2037 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2038 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2040 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2041 vsi->offset_loaded, &oes->rx_bytes,
2043 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2044 vsi->offset_loaded, &oes->rx_unicast,
2046 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2047 vsi->offset_loaded, &oes->rx_multicast,
2048 &nes->rx_multicast);
2049 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2050 vsi->offset_loaded, &oes->rx_broadcast,
2051 &nes->rx_broadcast);
2052 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2053 &oes->rx_discards, &nes->rx_discards);
2054 /* GLV_REPC not supported */
2055 /* GLV_RMPC not supported */
2056 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2057 &oes->rx_unknown_protocol,
2058 &nes->rx_unknown_protocol);
2059 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2060 vsi->offset_loaded, &oes->tx_bytes,
2062 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2063 vsi->offset_loaded, &oes->tx_unicast,
2065 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2066 vsi->offset_loaded, &oes->tx_multicast,
2067 &nes->tx_multicast);
2068 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2069 vsi->offset_loaded, &oes->tx_broadcast,
2070 &nes->tx_broadcast);
2071 /* GLV_TDPC not supported */
2072 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2073 &oes->tx_errors, &nes->tx_errors);
2074 vsi->offset_loaded = true;
2076 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2078 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2079 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2080 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2081 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2082 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2083 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2084 nes->rx_unknown_protocol);
2085 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2086 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2087 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2088 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2089 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2090 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2091 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2096 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2099 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2100 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2102 /* Get statistics of struct i40e_eth_stats */
2103 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2104 I40E_GLPRT_GORCL(hw->port),
2105 pf->offset_loaded, &os->eth.rx_bytes,
2107 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2108 I40E_GLPRT_UPRCL(hw->port),
2109 pf->offset_loaded, &os->eth.rx_unicast,
2110 &ns->eth.rx_unicast);
2111 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2112 I40E_GLPRT_MPRCL(hw->port),
2113 pf->offset_loaded, &os->eth.rx_multicast,
2114 &ns->eth.rx_multicast);
2115 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2116 I40E_GLPRT_BPRCL(hw->port),
2117 pf->offset_loaded, &os->eth.rx_broadcast,
2118 &ns->eth.rx_broadcast);
2119 /* Workaround: CRC size should not be included in byte statistics,
2120 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2122 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2123 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2125 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2126 pf->offset_loaded, &os->eth.rx_discards,
2127 &ns->eth.rx_discards);
2128 /* GLPRT_REPC not supported */
2129 /* GLPRT_RMPC not supported */
2130 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2132 &os->eth.rx_unknown_protocol,
2133 &ns->eth.rx_unknown_protocol);
2134 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2135 I40E_GLPRT_GOTCL(hw->port),
2136 pf->offset_loaded, &os->eth.tx_bytes,
2138 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2139 I40E_GLPRT_UPTCL(hw->port),
2140 pf->offset_loaded, &os->eth.tx_unicast,
2141 &ns->eth.tx_unicast);
2142 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2143 I40E_GLPRT_MPTCL(hw->port),
2144 pf->offset_loaded, &os->eth.tx_multicast,
2145 &ns->eth.tx_multicast);
2146 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2147 I40E_GLPRT_BPTCL(hw->port),
2148 pf->offset_loaded, &os->eth.tx_broadcast,
2149 &ns->eth.tx_broadcast);
2150 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2151 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2152 /* GLPRT_TEPC not supported */
2154 /* additional port specific stats */
2155 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2156 pf->offset_loaded, &os->tx_dropped_link_down,
2157 &ns->tx_dropped_link_down);
2158 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2159 pf->offset_loaded, &os->crc_errors,
2161 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2162 pf->offset_loaded, &os->illegal_bytes,
2163 &ns->illegal_bytes);
2164 /* GLPRT_ERRBC not supported */
2165 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2166 pf->offset_loaded, &os->mac_local_faults,
2167 &ns->mac_local_faults);
2168 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2169 pf->offset_loaded, &os->mac_remote_faults,
2170 &ns->mac_remote_faults);
2171 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2172 pf->offset_loaded, &os->rx_length_errors,
2173 &ns->rx_length_errors);
2174 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2175 pf->offset_loaded, &os->link_xon_rx,
2177 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2178 pf->offset_loaded, &os->link_xoff_rx,
2180 for (i = 0; i < 8; i++) {
2181 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2183 &os->priority_xon_rx[i],
2184 &ns->priority_xon_rx[i]);
2185 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2187 &os->priority_xoff_rx[i],
2188 &ns->priority_xoff_rx[i]);
2190 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2191 pf->offset_loaded, &os->link_xon_tx,
2193 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2194 pf->offset_loaded, &os->link_xoff_tx,
2196 for (i = 0; i < 8; i++) {
2197 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2199 &os->priority_xon_tx[i],
2200 &ns->priority_xon_tx[i]);
2201 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2203 &os->priority_xoff_tx[i],
2204 &ns->priority_xoff_tx[i]);
2205 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2207 &os->priority_xon_2_xoff[i],
2208 &ns->priority_xon_2_xoff[i]);
2210 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2211 I40E_GLPRT_PRC64L(hw->port),
2212 pf->offset_loaded, &os->rx_size_64,
2214 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2215 I40E_GLPRT_PRC127L(hw->port),
2216 pf->offset_loaded, &os->rx_size_127,
2218 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2219 I40E_GLPRT_PRC255L(hw->port),
2220 pf->offset_loaded, &os->rx_size_255,
2222 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2223 I40E_GLPRT_PRC511L(hw->port),
2224 pf->offset_loaded, &os->rx_size_511,
2226 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2227 I40E_GLPRT_PRC1023L(hw->port),
2228 pf->offset_loaded, &os->rx_size_1023,
2230 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2231 I40E_GLPRT_PRC1522L(hw->port),
2232 pf->offset_loaded, &os->rx_size_1522,
2234 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2235 I40E_GLPRT_PRC9522L(hw->port),
2236 pf->offset_loaded, &os->rx_size_big,
2238 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2239 pf->offset_loaded, &os->rx_undersize,
2241 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2242 pf->offset_loaded, &os->rx_fragments,
2244 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2245 pf->offset_loaded, &os->rx_oversize,
2247 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2248 pf->offset_loaded, &os->rx_jabber,
2250 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2251 I40E_GLPRT_PTC64L(hw->port),
2252 pf->offset_loaded, &os->tx_size_64,
2254 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2255 I40E_GLPRT_PTC127L(hw->port),
2256 pf->offset_loaded, &os->tx_size_127,
2258 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2259 I40E_GLPRT_PTC255L(hw->port),
2260 pf->offset_loaded, &os->tx_size_255,
2262 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2263 I40E_GLPRT_PTC511L(hw->port),
2264 pf->offset_loaded, &os->tx_size_511,
2266 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2267 I40E_GLPRT_PTC1023L(hw->port),
2268 pf->offset_loaded, &os->tx_size_1023,
2270 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2271 I40E_GLPRT_PTC1522L(hw->port),
2272 pf->offset_loaded, &os->tx_size_1522,
2274 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2275 I40E_GLPRT_PTC9522L(hw->port),
2276 pf->offset_loaded, &os->tx_size_big,
2278 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2280 &os->fd_sb_match, &ns->fd_sb_match);
2281 /* GLPRT_MSPDC not supported */
2282 /* GLPRT_XEC not supported */
2284 pf->offset_loaded = true;
2287 i40e_update_vsi_stats(pf->main_vsi);
2290 /* Get all statistics of a port */
2292 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2294 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2295 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2296 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2299 /* call read registers - updates values, now write them to struct */
2300 i40e_read_stats_registers(pf, hw);
2302 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2303 pf->main_vsi->eth_stats.rx_multicast +
2304 pf->main_vsi->eth_stats.rx_broadcast -
2305 pf->main_vsi->eth_stats.rx_discards;
2306 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2307 pf->main_vsi->eth_stats.tx_multicast +
2308 pf->main_vsi->eth_stats.tx_broadcast;
2309 stats->ibytes = ns->eth.rx_bytes;
2310 stats->obytes = ns->eth.tx_bytes;
2311 stats->oerrors = ns->eth.tx_errors +
2312 pf->main_vsi->eth_stats.tx_errors;
2315 stats->imissed = ns->eth.rx_discards +
2316 pf->main_vsi->eth_stats.rx_discards;
2317 stats->ierrors = ns->crc_errors +
2318 ns->rx_length_errors + ns->rx_undersize +
2319 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2321 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2322 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2323 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2324 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2325 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2326 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2327 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2328 ns->eth.rx_unknown_protocol);
2329 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2330 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2331 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2332 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2333 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2334 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2336 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2337 ns->tx_dropped_link_down);
2338 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2339 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2341 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2342 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2343 ns->mac_local_faults);
2344 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2345 ns->mac_remote_faults);
2346 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2347 ns->rx_length_errors);
2348 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2349 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2350 for (i = 0; i < 8; i++) {
2351 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2352 i, ns->priority_xon_rx[i]);
2353 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2354 i, ns->priority_xoff_rx[i]);
2356 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2357 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2358 for (i = 0; i < 8; i++) {
2359 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2360 i, ns->priority_xon_tx[i]);
2361 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2362 i, ns->priority_xoff_tx[i]);
2363 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2364 i, ns->priority_xon_2_xoff[i]);
2366 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2367 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2368 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2369 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2370 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2371 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2372 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2373 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2374 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2375 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2376 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2377 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2378 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2379 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2380 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2381 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2382 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2383 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2384 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2385 ns->mac_short_packet_dropped);
2386 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2387 ns->checksum_error);
2388 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2389 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2392 /* Reset the statistics */
2394 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2396 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2397 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2399 /* Mark PF and VSI stats to update the offset, aka "reset" */
2400 pf->offset_loaded = false;
2402 pf->main_vsi->offset_loaded = false;
2404 /* read the stats, reading current register values into offset */
2405 i40e_read_stats_registers(pf, hw);
2409 i40e_xstats_calc_num(void)
2411 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2412 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2413 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2416 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2417 struct rte_eth_xstat_name *xstats_names,
2418 __rte_unused unsigned limit)
2423 if (xstats_names == NULL)
2424 return i40e_xstats_calc_num();
2426 /* Note: limit checked in rte_eth_xstats_names() */
2428 /* Get stats from i40e_eth_stats struct */
2429 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2430 snprintf(xstats_names[count].name,
2431 sizeof(xstats_names[count].name),
2432 "%s", rte_i40e_stats_strings[i].name);
2436 /* Get individiual stats from i40e_hw_port struct */
2437 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2438 snprintf(xstats_names[count].name,
2439 sizeof(xstats_names[count].name),
2440 "%s", rte_i40e_hw_port_strings[i].name);
2444 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2445 for (prio = 0; prio < 8; prio++) {
2446 snprintf(xstats_names[count].name,
2447 sizeof(xstats_names[count].name),
2448 "rx_priority%u_%s", prio,
2449 rte_i40e_rxq_prio_strings[i].name);
2454 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2455 for (prio = 0; prio < 8; prio++) {
2456 snprintf(xstats_names[count].name,
2457 sizeof(xstats_names[count].name),
2458 "tx_priority%u_%s", prio,
2459 rte_i40e_txq_prio_strings[i].name);
2467 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2470 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2471 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2472 unsigned i, count, prio;
2473 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2475 count = i40e_xstats_calc_num();
2479 i40e_read_stats_registers(pf, hw);
2486 /* Get stats from i40e_eth_stats struct */
2487 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2488 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2489 rte_i40e_stats_strings[i].offset);
2493 /* Get individiual stats from i40e_hw_port struct */
2494 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2495 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2496 rte_i40e_hw_port_strings[i].offset);
2500 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2501 for (prio = 0; prio < 8; prio++) {
2502 xstats[count].value =
2503 *(uint64_t *)(((char *)hw_stats) +
2504 rte_i40e_rxq_prio_strings[i].offset +
2505 (sizeof(uint64_t) * prio));
2510 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2511 for (prio = 0; prio < 8; prio++) {
2512 xstats[count].value =
2513 *(uint64_t *)(((char *)hw_stats) +
2514 rte_i40e_txq_prio_strings[i].offset +
2515 (sizeof(uint64_t) * prio));
2524 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2525 __rte_unused uint16_t queue_id,
2526 __rte_unused uint8_t stat_idx,
2527 __rte_unused uint8_t is_rx)
2529 PMD_INIT_FUNC_TRACE();
2535 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2537 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2538 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2539 struct i40e_vsi *vsi = pf->main_vsi;
2541 dev_info->max_rx_queues = vsi->nb_qps;
2542 dev_info->max_tx_queues = vsi->nb_qps;
2543 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2544 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2545 dev_info->max_mac_addrs = vsi->max_macaddrs;
2546 dev_info->max_vfs = dev->pci_dev->max_vfs;
2547 dev_info->rx_offload_capa =
2548 DEV_RX_OFFLOAD_VLAN_STRIP |
2549 DEV_RX_OFFLOAD_QINQ_STRIP |
2550 DEV_RX_OFFLOAD_IPV4_CKSUM |
2551 DEV_RX_OFFLOAD_UDP_CKSUM |
2552 DEV_RX_OFFLOAD_TCP_CKSUM;
2553 dev_info->tx_offload_capa =
2554 DEV_TX_OFFLOAD_VLAN_INSERT |
2555 DEV_TX_OFFLOAD_QINQ_INSERT |
2556 DEV_TX_OFFLOAD_IPV4_CKSUM |
2557 DEV_TX_OFFLOAD_UDP_CKSUM |
2558 DEV_TX_OFFLOAD_TCP_CKSUM |
2559 DEV_TX_OFFLOAD_SCTP_CKSUM |
2560 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2561 DEV_TX_OFFLOAD_TCP_TSO;
2562 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2564 dev_info->reta_size = pf->hash_lut_size;
2565 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2567 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2569 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2570 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2571 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2573 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2577 dev_info->default_txconf = (struct rte_eth_txconf) {
2579 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2580 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2581 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2583 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2584 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2585 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2586 ETH_TXQ_FLAGS_NOOFFLOADS,
2589 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2590 .nb_max = I40E_MAX_RING_DESC,
2591 .nb_min = I40E_MIN_RING_DESC,
2592 .nb_align = I40E_ALIGN_RING_DESC,
2595 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2596 .nb_max = I40E_MAX_RING_DESC,
2597 .nb_min = I40E_MIN_RING_DESC,
2598 .nb_align = I40E_ALIGN_RING_DESC,
2601 if (pf->flags & I40E_FLAG_VMDQ) {
2602 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2603 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2604 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2605 pf->max_nb_vmdq_vsi;
2606 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2607 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2608 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2611 if (i40e_is_40G_device(hw->device_id))
2613 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2616 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2620 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2622 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2623 struct i40e_vsi *vsi = pf->main_vsi;
2624 PMD_INIT_FUNC_TRACE();
2627 return i40e_vsi_add_vlan(vsi, vlan_id);
2629 return i40e_vsi_delete_vlan(vsi, vlan_id);
2633 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2634 enum rte_vlan_type vlan_type,
2637 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2638 uint64_t reg_r = 0, reg_w = 0;
2639 uint16_t reg_id = 0;
2641 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2643 switch (vlan_type) {
2644 case ETH_VLAN_TYPE_OUTER:
2650 case ETH_VLAN_TYPE_INNER:
2656 "Unsupported vlan type in single vlan.\n");
2662 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2665 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2667 if (ret != I40E_SUCCESS) {
2668 PMD_DRV_LOG(ERR, "Fail to debug read from "
2669 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2673 PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2674 "0x%08"PRIx64"", reg_id, reg_r);
2676 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2677 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2678 if (reg_r == reg_w) {
2680 PMD_DRV_LOG(DEBUG, "No need to write");
2684 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2686 if (ret != I40E_SUCCESS) {
2688 PMD_DRV_LOG(ERR, "Fail to debug write to "
2689 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2692 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2693 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2699 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2701 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2702 struct i40e_vsi *vsi = pf->main_vsi;
2704 if (mask & ETH_VLAN_FILTER_MASK) {
2705 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2706 i40e_vsi_config_vlan_filter(vsi, TRUE);
2708 i40e_vsi_config_vlan_filter(vsi, FALSE);
2711 if (mask & ETH_VLAN_STRIP_MASK) {
2712 /* Enable or disable VLAN stripping */
2713 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2714 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2716 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2719 if (mask & ETH_VLAN_EXTEND_MASK) {
2720 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2721 i40e_vsi_config_double_vlan(vsi, TRUE);
2722 /* Set global registers with default ether type value */
2723 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2725 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2729 i40e_vsi_config_double_vlan(vsi, FALSE);
2734 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2735 __rte_unused uint16_t queue,
2736 __rte_unused int on)
2738 PMD_INIT_FUNC_TRACE();
2742 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2744 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2745 struct i40e_vsi *vsi = pf->main_vsi;
2746 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2747 struct i40e_vsi_vlan_pvid_info info;
2749 memset(&info, 0, sizeof(info));
2752 info.config.pvid = pvid;
2754 info.config.reject.tagged =
2755 data->dev_conf.txmode.hw_vlan_reject_tagged;
2756 info.config.reject.untagged =
2757 data->dev_conf.txmode.hw_vlan_reject_untagged;
2760 return i40e_vsi_vlan_pvid_set(vsi, &info);
2764 i40e_dev_led_on(struct rte_eth_dev *dev)
2766 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2767 uint32_t mode = i40e_led_get(hw);
2770 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2776 i40e_dev_led_off(struct rte_eth_dev *dev)
2778 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2779 uint32_t mode = i40e_led_get(hw);
2782 i40e_led_set(hw, 0, false);
2788 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2790 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2791 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2793 fc_conf->pause_time = pf->fc_conf.pause_time;
2794 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2795 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2797 /* Return current mode according to actual setting*/
2798 switch (hw->fc.current_mode) {
2800 fc_conf->mode = RTE_FC_FULL;
2802 case I40E_FC_TX_PAUSE:
2803 fc_conf->mode = RTE_FC_TX_PAUSE;
2805 case I40E_FC_RX_PAUSE:
2806 fc_conf->mode = RTE_FC_RX_PAUSE;
2810 fc_conf->mode = RTE_FC_NONE;
2817 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2819 uint32_t mflcn_reg, fctrl_reg, reg;
2820 uint32_t max_high_water;
2821 uint8_t i, aq_failure;
2825 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2826 [RTE_FC_NONE] = I40E_FC_NONE,
2827 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2828 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2829 [RTE_FC_FULL] = I40E_FC_FULL
2832 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2834 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2835 if ((fc_conf->high_water > max_high_water) ||
2836 (fc_conf->high_water < fc_conf->low_water)) {
2837 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2838 "High_water must <= %d.", max_high_water);
2842 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2843 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2844 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2846 pf->fc_conf.pause_time = fc_conf->pause_time;
2847 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2848 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2850 PMD_INIT_FUNC_TRACE();
2852 /* All the link flow control related enable/disable register
2853 * configuration is handle by the F/W
2855 err = i40e_set_fc(hw, &aq_failure, true);
2859 if (i40e_is_40G_device(hw->device_id)) {
2860 /* Configure flow control refresh threshold,
2861 * the value for stat_tx_pause_refresh_timer[8]
2862 * is used for global pause operation.
2866 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2867 pf->fc_conf.pause_time);
2869 /* configure the timer value included in transmitted pause
2871 * the value for stat_tx_pause_quanta[8] is used for global
2874 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2875 pf->fc_conf.pause_time);
2877 fctrl_reg = I40E_READ_REG(hw,
2878 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2880 if (fc_conf->mac_ctrl_frame_fwd != 0)
2881 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2883 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2885 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2888 /* Configure pause time (2 TCs per register) */
2889 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2890 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2891 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2893 /* Configure flow control refresh threshold value */
2894 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2895 pf->fc_conf.pause_time / 2);
2897 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2899 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2900 *depending on configuration
2902 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2903 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2904 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2906 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2907 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2910 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2913 /* config the water marker both based on the packets and bytes */
2914 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2915 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2916 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2917 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2918 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2919 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2920 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2921 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2923 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2924 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2927 I40E_WRITE_FLUSH(hw);
2933 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2934 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2936 PMD_INIT_FUNC_TRACE();
2941 /* Add a MAC address, and update filters */
2943 i40e_macaddr_add(struct rte_eth_dev *dev,
2944 struct ether_addr *mac_addr,
2945 __rte_unused uint32_t index,
2948 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2949 struct i40e_mac_filter_info mac_filter;
2950 struct i40e_vsi *vsi;
2953 /* If VMDQ not enabled or configured, return */
2954 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
2955 !pf->nb_cfg_vmdq_vsi)) {
2956 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2957 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
2962 if (pool > pf->nb_cfg_vmdq_vsi) {
2963 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2964 pool, pf->nb_cfg_vmdq_vsi);
2968 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2969 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2970 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2972 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2977 vsi = pf->vmdq[pool - 1].vsi;
2979 ret = i40e_vsi_add_mac(vsi, &mac_filter);
2980 if (ret != I40E_SUCCESS) {
2981 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2986 /* Remove a MAC address, and update filters */
2988 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2990 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2991 struct i40e_vsi *vsi;
2992 struct rte_eth_dev_data *data = dev->data;
2993 struct ether_addr *macaddr;
2998 macaddr = &(data->mac_addrs[index]);
3000 pool_sel = dev->data->mac_pool_sel[index];
3002 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3003 if (pool_sel & (1ULL << i)) {
3007 /* No VMDQ pool enabled or configured */
3008 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3009 (i > pf->nb_cfg_vmdq_vsi)) {
3010 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3014 vsi = pf->vmdq[i - 1].vsi;
3016 ret = i40e_vsi_delete_mac(vsi, macaddr);
3019 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3026 /* Set perfect match or hash match of MAC and VLAN for a VF */
3028 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3029 struct rte_eth_mac_filter *filter,
3033 struct i40e_mac_filter_info mac_filter;
3034 struct ether_addr old_mac;
3035 struct ether_addr *new_mac;
3036 struct i40e_pf_vf *vf = NULL;
3041 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3044 hw = I40E_PF_TO_HW(pf);
3046 if (filter == NULL) {
3047 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3051 new_mac = &filter->mac_addr;
3053 if (is_zero_ether_addr(new_mac)) {
3054 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3058 vf_id = filter->dst_id;
3060 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3061 PMD_DRV_LOG(ERR, "Invalid argument.");
3064 vf = &pf->vfs[vf_id];
3066 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3067 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3072 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3073 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3075 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3078 mac_filter.filter_type = filter->filter_type;
3079 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3080 if (ret != I40E_SUCCESS) {
3081 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3084 ether_addr_copy(new_mac, &pf->dev_addr);
3086 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3088 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3089 if (ret != I40E_SUCCESS) {
3090 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3094 /* Clear device address as it has been removed */
3095 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3096 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3102 /* MAC filter handle */
3104 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3107 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3108 struct rte_eth_mac_filter *filter;
3109 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3110 int ret = I40E_NOT_SUPPORTED;
3112 filter = (struct rte_eth_mac_filter *)(arg);
3114 switch (filter_op) {
3115 case RTE_ETH_FILTER_NOP:
3118 case RTE_ETH_FILTER_ADD:
3119 i40e_pf_disable_irq0(hw);
3121 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3122 i40e_pf_enable_irq0(hw);
3124 case RTE_ETH_FILTER_DELETE:
3125 i40e_pf_disable_irq0(hw);
3127 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3128 i40e_pf_enable_irq0(hw);
3131 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3132 ret = I40E_ERR_PARAM;
3140 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3142 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3143 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3149 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3150 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3153 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3157 uint32_t *lut_dw = (uint32_t *)lut;
3158 uint16_t i, lut_size_dw = lut_size / 4;
3160 for (i = 0; i < lut_size_dw; i++)
3161 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3168 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3177 pf = I40E_VSI_TO_PF(vsi);
3178 hw = I40E_VSI_TO_HW(vsi);
3180 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3181 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3184 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3188 uint32_t *lut_dw = (uint32_t *)lut;
3189 uint16_t i, lut_size_dw = lut_size / 4;
3191 for (i = 0; i < lut_size_dw; i++)
3192 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3193 I40E_WRITE_FLUSH(hw);
3200 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3201 struct rte_eth_rss_reta_entry64 *reta_conf,
3204 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3205 uint16_t i, lut_size = pf->hash_lut_size;
3206 uint16_t idx, shift;
3210 if (reta_size != lut_size ||
3211 reta_size > ETH_RSS_RETA_SIZE_512) {
3212 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3213 "(%d) doesn't match the number hardware can supported "
3214 "(%d)\n", reta_size, lut_size);
3218 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3220 PMD_DRV_LOG(ERR, "No memory can be allocated");
3223 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3226 for (i = 0; i < reta_size; i++) {
3227 idx = i / RTE_RETA_GROUP_SIZE;
3228 shift = i % RTE_RETA_GROUP_SIZE;
3229 if (reta_conf[idx].mask & (1ULL << shift))
3230 lut[i] = reta_conf[idx].reta[shift];
3232 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3241 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3242 struct rte_eth_rss_reta_entry64 *reta_conf,
3245 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3246 uint16_t i, lut_size = pf->hash_lut_size;
3247 uint16_t idx, shift;
3251 if (reta_size != lut_size ||
3252 reta_size > ETH_RSS_RETA_SIZE_512) {
3253 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3254 "(%d) doesn't match the number hardware can supported "
3255 "(%d)\n", reta_size, lut_size);
3259 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3261 PMD_DRV_LOG(ERR, "No memory can be allocated");
3265 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3268 for (i = 0; i < reta_size; i++) {
3269 idx = i / RTE_RETA_GROUP_SIZE;
3270 shift = i % RTE_RETA_GROUP_SIZE;
3271 if (reta_conf[idx].mask & (1ULL << shift))
3272 reta_conf[idx].reta[shift] = lut[i];
3282 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3283 * @hw: pointer to the HW structure
3284 * @mem: pointer to mem struct to fill out
3285 * @size: size of memory requested
3286 * @alignment: what to align the allocation to
3288 enum i40e_status_code
3289 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3290 struct i40e_dma_mem *mem,
3294 const struct rte_memzone *mz = NULL;
3295 char z_name[RTE_MEMZONE_NAMESIZE];
3298 return I40E_ERR_PARAM;
3300 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3301 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3302 alignment, RTE_PGSIZE_2M);
3304 return I40E_ERR_NO_MEMORY;
3308 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3309 mem->zone = (const void *)mz;
3310 PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3311 "%"PRIu64, mz->name, mem->pa);
3313 return I40E_SUCCESS;
3317 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3318 * @hw: pointer to the HW structure
3319 * @mem: ptr to mem struct to free
3321 enum i40e_status_code
3322 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3323 struct i40e_dma_mem *mem)
3326 return I40E_ERR_PARAM;
3328 PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3329 "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3331 rte_memzone_free((const struct rte_memzone *)mem->zone);
3336 return I40E_SUCCESS;
3340 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3341 * @hw: pointer to the HW structure
3342 * @mem: pointer to mem struct to fill out
3343 * @size: size of memory requested
3345 enum i40e_status_code
3346 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3347 struct i40e_virt_mem *mem,
3351 return I40E_ERR_PARAM;
3354 mem->va = rte_zmalloc("i40e", size, 0);
3357 return I40E_SUCCESS;
3359 return I40E_ERR_NO_MEMORY;
3363 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3364 * @hw: pointer to the HW structure
3365 * @mem: pointer to mem struct to free
3367 enum i40e_status_code
3368 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3369 struct i40e_virt_mem *mem)
3372 return I40E_ERR_PARAM;
3377 return I40E_SUCCESS;
3381 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3383 rte_spinlock_init(&sp->spinlock);
3387 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3389 rte_spinlock_lock(&sp->spinlock);
3393 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3395 rte_spinlock_unlock(&sp->spinlock);
3399 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3405 * Get the hardware capabilities, which will be parsed
3406 * and saved into struct i40e_hw.
3409 i40e_get_cap(struct i40e_hw *hw)
3411 struct i40e_aqc_list_capabilities_element_resp *buf;
3412 uint16_t len, size = 0;
3415 /* Calculate a huge enough buff for saving response data temporarily */
3416 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3417 I40E_MAX_CAP_ELE_NUM;
3418 buf = rte_zmalloc("i40e", len, 0);
3420 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3421 return I40E_ERR_NO_MEMORY;
3424 /* Get, parse the capabilities and save it to hw */
3425 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3426 i40e_aqc_opc_list_func_capabilities, NULL);
3427 if (ret != I40E_SUCCESS)
3428 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3430 /* Free the temporary buffer after being used */
3437 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3439 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3440 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3441 uint16_t qp_count = 0, vsi_count = 0;
3443 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3444 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3447 /* Add the parameter init for LFC */
3448 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3449 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3450 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3452 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3453 pf->max_num_vsi = hw->func_caps.num_vsis;
3454 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3455 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3456 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3458 /* FDir queue/VSI allocation */
3459 pf->fdir_qp_offset = 0;
3460 if (hw->func_caps.fd) {
3461 pf->flags |= I40E_FLAG_FDIR;
3462 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3464 pf->fdir_nb_qps = 0;
3466 qp_count += pf->fdir_nb_qps;
3469 /* LAN queue/VSI allocation */
3470 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3471 if (!hw->func_caps.rss) {
3474 pf->flags |= I40E_FLAG_RSS;
3475 if (hw->mac.type == I40E_MAC_X722)
3476 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3477 pf->lan_nb_qps = pf->lan_nb_qp_max;
3479 qp_count += pf->lan_nb_qps;
3482 /* VF queue/VSI allocation */
3483 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3484 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3485 pf->flags |= I40E_FLAG_SRIOV;
3486 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3487 pf->vf_num = dev->pci_dev->max_vfs;
3488 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3489 "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3490 pf->vf_nb_qps * pf->vf_num);
3495 qp_count += pf->vf_nb_qps * pf->vf_num;
3496 vsi_count += pf->vf_num;
3498 /* VMDq queue/VSI allocation */
3499 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3500 pf->vmdq_nb_qps = 0;
3501 pf->max_nb_vmdq_vsi = 0;
3502 if (hw->func_caps.vmdq) {
3503 if (qp_count < hw->func_caps.num_tx_qp &&
3504 vsi_count < hw->func_caps.num_vsis) {
3505 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3506 qp_count) / pf->vmdq_nb_qp_max;
3508 /* Limit the maximum number of VMDq vsi to the maximum
3509 * ethdev can support
3511 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3512 hw->func_caps.num_vsis - vsi_count);
3513 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3515 if (pf->max_nb_vmdq_vsi) {
3516 pf->flags |= I40E_FLAG_VMDQ;
3517 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3518 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3519 "per VMDQ VSI, in total %u queues",
3520 pf->max_nb_vmdq_vsi,
3521 pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3522 pf->max_nb_vmdq_vsi);
3524 PMD_DRV_LOG(INFO, "No enough queues left for "
3528 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3531 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3532 vsi_count += pf->max_nb_vmdq_vsi;
3534 if (hw->func_caps.dcb)
3535 pf->flags |= I40E_FLAG_DCB;
3537 if (qp_count > hw->func_caps.num_tx_qp) {
3538 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3539 "the hardware maximum %u", qp_count,
3540 hw->func_caps.num_tx_qp);
3543 if (vsi_count > hw->func_caps.num_vsis) {
3544 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3545 "the hardware maximum %u", vsi_count,
3546 hw->func_caps.num_vsis);
3554 i40e_pf_get_switch_config(struct i40e_pf *pf)
3556 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3557 struct i40e_aqc_get_switch_config_resp *switch_config;
3558 struct i40e_aqc_switch_config_element_resp *element;
3559 uint16_t start_seid = 0, num_reported;
3562 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3563 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3564 if (!switch_config) {
3565 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3569 /* Get the switch configurations */
3570 ret = i40e_aq_get_switch_config(hw, switch_config,
3571 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3572 if (ret != I40E_SUCCESS) {
3573 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3576 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3577 if (num_reported != 1) { /* The number should be 1 */
3578 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3582 /* Parse the switch configuration elements */
3583 element = &(switch_config->element[0]);
3584 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3585 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3586 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3588 PMD_DRV_LOG(INFO, "Unknown element type");
3591 rte_free(switch_config);
3597 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3600 struct pool_entry *entry;
3602 if (pool == NULL || num == 0)
3605 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3606 if (entry == NULL) {
3607 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3611 /* queue heap initialize */
3612 pool->num_free = num;
3613 pool->num_alloc = 0;
3615 LIST_INIT(&pool->alloc_list);
3616 LIST_INIT(&pool->free_list);
3618 /* Initialize element */
3622 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3627 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3629 struct pool_entry *entry, *next_entry;
3634 for (entry = LIST_FIRST(&pool->alloc_list);
3635 entry && (next_entry = LIST_NEXT(entry, next), 1);
3636 entry = next_entry) {
3637 LIST_REMOVE(entry, next);
3641 for (entry = LIST_FIRST(&pool->free_list);
3642 entry && (next_entry = LIST_NEXT(entry, next), 1);
3643 entry = next_entry) {
3644 LIST_REMOVE(entry, next);
3649 pool->num_alloc = 0;
3651 LIST_INIT(&pool->alloc_list);
3652 LIST_INIT(&pool->free_list);
3656 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3659 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3660 uint32_t pool_offset;
3664 PMD_DRV_LOG(ERR, "Invalid parameter");
3668 pool_offset = base - pool->base;
3669 /* Lookup in alloc list */
3670 LIST_FOREACH(entry, &pool->alloc_list, next) {
3671 if (entry->base == pool_offset) {
3672 valid_entry = entry;
3673 LIST_REMOVE(entry, next);
3678 /* Not find, return */
3679 if (valid_entry == NULL) {
3680 PMD_DRV_LOG(ERR, "Failed to find entry");
3685 * Found it, move it to free list and try to merge.
3686 * In order to make merge easier, always sort it by qbase.
3687 * Find adjacent prev and last entries.
3690 LIST_FOREACH(entry, &pool->free_list, next) {
3691 if (entry->base > valid_entry->base) {
3699 /* Try to merge with next one*/
3701 /* Merge with next one */
3702 if (valid_entry->base + valid_entry->len == next->base) {
3703 next->base = valid_entry->base;
3704 next->len += valid_entry->len;
3705 rte_free(valid_entry);
3712 /* Merge with previous one */
3713 if (prev->base + prev->len == valid_entry->base) {
3714 prev->len += valid_entry->len;
3715 /* If it merge with next one, remove next node */
3717 LIST_REMOVE(valid_entry, next);
3718 rte_free(valid_entry);
3720 rte_free(valid_entry);
3726 /* Not find any entry to merge, insert */
3729 LIST_INSERT_AFTER(prev, valid_entry, next);
3730 else if (next != NULL)
3731 LIST_INSERT_BEFORE(next, valid_entry, next);
3732 else /* It's empty list, insert to head */
3733 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3736 pool->num_free += valid_entry->len;
3737 pool->num_alloc -= valid_entry->len;
3743 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3746 struct pool_entry *entry, *valid_entry;
3748 if (pool == NULL || num == 0) {
3749 PMD_DRV_LOG(ERR, "Invalid parameter");
3753 if (pool->num_free < num) {
3754 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3755 num, pool->num_free);
3760 /* Lookup in free list and find most fit one */
3761 LIST_FOREACH(entry, &pool->free_list, next) {
3762 if (entry->len >= num) {
3764 if (entry->len == num) {
3765 valid_entry = entry;
3768 if (valid_entry == NULL || valid_entry->len > entry->len)
3769 valid_entry = entry;
3773 /* Not find one to satisfy the request, return */
3774 if (valid_entry == NULL) {
3775 PMD_DRV_LOG(ERR, "No valid entry found");
3779 * The entry have equal queue number as requested,
3780 * remove it from alloc_list.
3782 if (valid_entry->len == num) {
3783 LIST_REMOVE(valid_entry, next);
3786 * The entry have more numbers than requested,
3787 * create a new entry for alloc_list and minus its
3788 * queue base and number in free_list.
3790 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3791 if (entry == NULL) {
3792 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3796 entry->base = valid_entry->base;
3798 valid_entry->base += num;
3799 valid_entry->len -= num;
3800 valid_entry = entry;
3803 /* Insert it into alloc list, not sorted */
3804 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3806 pool->num_free -= valid_entry->len;
3807 pool->num_alloc += valid_entry->len;
3809 return valid_entry->base + pool->base;
3813 * bitmap_is_subset - Check whether src2 is subset of src1
3816 bitmap_is_subset(uint8_t src1, uint8_t src2)
3818 return !((src1 ^ src2) & src2);
3821 static enum i40e_status_code
3822 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3824 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3826 /* If DCB is not supported, only default TC is supported */
3827 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3828 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3829 return I40E_NOT_SUPPORTED;
3832 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3833 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3834 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3836 return I40E_NOT_SUPPORTED;
3838 return I40E_SUCCESS;
3842 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3843 struct i40e_vsi_vlan_pvid_info *info)
3846 struct i40e_vsi_context ctxt;
3847 uint8_t vlan_flags = 0;
3850 if (vsi == NULL || info == NULL) {
3851 PMD_DRV_LOG(ERR, "invalid parameters");
3852 return I40E_ERR_PARAM;
3856 vsi->info.pvid = info->config.pvid;
3858 * If insert pvid is enabled, only tagged pkts are
3859 * allowed to be sent out.
3861 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3862 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3865 if (info->config.reject.tagged == 0)
3866 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3868 if (info->config.reject.untagged == 0)
3869 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3871 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3872 I40E_AQ_VSI_PVLAN_MODE_MASK);
3873 vsi->info.port_vlan_flags |= vlan_flags;
3874 vsi->info.valid_sections =
3875 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3876 memset(&ctxt, 0, sizeof(ctxt));
3877 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3878 ctxt.seid = vsi->seid;
3880 hw = I40E_VSI_TO_HW(vsi);
3881 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3882 if (ret != I40E_SUCCESS)
3883 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3889 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3891 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3893 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3895 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3896 if (ret != I40E_SUCCESS)
3900 PMD_DRV_LOG(ERR, "seid not valid");
3904 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3905 tc_bw_data.tc_valid_bits = enabled_tcmap;
3906 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3907 tc_bw_data.tc_bw_credits[i] =
3908 (enabled_tcmap & (1 << i)) ? 1 : 0;
3910 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3911 if (ret != I40E_SUCCESS) {
3912 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3916 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3917 sizeof(vsi->info.qs_handle));
3918 return I40E_SUCCESS;
3921 static enum i40e_status_code
3922 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3923 struct i40e_aqc_vsi_properties_data *info,
3924 uint8_t enabled_tcmap)
3926 enum i40e_status_code ret;
3927 int i, total_tc = 0;
3928 uint16_t qpnum_per_tc, bsf, qp_idx;
3930 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3931 if (ret != I40E_SUCCESS)
3934 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3935 if (enabled_tcmap & (1 << i))
3937 vsi->enabled_tc = enabled_tcmap;
3939 /* Number of queues per enabled TC */
3940 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3941 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3942 bsf = rte_bsf32(qpnum_per_tc);
3944 /* Adjust the queue number to actual queues that can be applied */
3945 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3946 vsi->nb_qps = qpnum_per_tc * total_tc;
3949 * Configure TC and queue mapping parameters, for enabled TC,
3950 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3951 * default queue will serve it.
3954 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3955 if (vsi->enabled_tc & (1 << i)) {
3956 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3957 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3958 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3959 qp_idx += qpnum_per_tc;
3961 info->tc_mapping[i] = 0;
3964 /* Associate queue number with VSI */
3965 if (vsi->type == I40E_VSI_SRIOV) {
3966 info->mapping_flags |=
3967 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3968 for (i = 0; i < vsi->nb_qps; i++)
3969 info->queue_mapping[i] =
3970 rte_cpu_to_le_16(vsi->base_queue + i);
3972 info->mapping_flags |=
3973 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3974 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3976 info->valid_sections |=
3977 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3979 return I40E_SUCCESS;
3983 i40e_veb_release(struct i40e_veb *veb)
3985 struct i40e_vsi *vsi;
3991 if (!TAILQ_EMPTY(&veb->head)) {
3992 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3995 /* associate_vsi field is NULL for floating VEB */
3996 if (veb->associate_vsi != NULL) {
3997 vsi = veb->associate_vsi;
3998 hw = I40E_VSI_TO_HW(vsi);
4000 vsi->uplink_seid = veb->uplink_seid;
4003 veb->associate_pf->main_vsi->floating_veb = NULL;
4004 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4007 i40e_aq_delete_element(hw, veb->seid, NULL);
4009 return I40E_SUCCESS;
4013 static struct i40e_veb *
4014 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4016 struct i40e_veb *veb;
4022 "veb setup failed, associated PF shouldn't null");
4025 hw = I40E_PF_TO_HW(pf);
4027 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4029 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4033 veb->associate_vsi = vsi;
4034 veb->associate_pf = pf;
4035 TAILQ_INIT(&veb->head);
4036 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4038 /* create floating veb if vsi is NULL */
4040 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4041 I40E_DEFAULT_TCMAP, false,
4042 &veb->seid, false, NULL);
4044 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4045 true, &veb->seid, false, NULL);
4048 if (ret != I40E_SUCCESS) {
4049 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4050 hw->aq.asq_last_status);
4054 /* get statistics index */
4055 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4056 &veb->stats_idx, NULL, NULL, NULL);
4057 if (ret != I40E_SUCCESS) {
4058 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4059 hw->aq.asq_last_status);
4062 /* Get VEB bandwidth, to be implemented */
4063 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4065 vsi->uplink_seid = veb->seid;
4074 i40e_vsi_release(struct i40e_vsi *vsi)
4078 struct i40e_vsi_list *vsi_list;
4081 struct i40e_mac_filter *f;
4082 uint16_t user_param = vsi->user_param;
4085 return I40E_SUCCESS;
4087 pf = I40E_VSI_TO_PF(vsi);
4088 hw = I40E_VSI_TO_HW(vsi);
4090 /* VSI has child to attach, release child first */
4092 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4093 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4096 i40e_veb_release(vsi->veb);
4099 if (vsi->floating_veb) {
4100 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4101 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4106 /* Remove all macvlan filters of the VSI */
4107 i40e_vsi_remove_all_macvlan_filter(vsi);
4108 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4111 if (vsi->type != I40E_VSI_MAIN &&
4112 ((vsi->type != I40E_VSI_SRIOV) ||
4113 !pf->floating_veb_list[user_param])) {
4114 /* Remove vsi from parent's sibling list */
4115 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4116 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4117 return I40E_ERR_PARAM;
4119 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4120 &vsi->sib_vsi_list, list);
4122 /* Remove all switch element of the VSI */
4123 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4124 if (ret != I40E_SUCCESS)
4125 PMD_DRV_LOG(ERR, "Failed to delete element");
4128 if ((vsi->type == I40E_VSI_SRIOV) &&
4129 pf->floating_veb_list[user_param]) {
4130 /* Remove vsi from parent's sibling list */
4131 if (vsi->parent_vsi == NULL ||
4132 vsi->parent_vsi->floating_veb == NULL) {
4133 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4134 return I40E_ERR_PARAM;
4136 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4137 &vsi->sib_vsi_list, list);
4139 /* Remove all switch element of the VSI */
4140 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4141 if (ret != I40E_SUCCESS)
4142 PMD_DRV_LOG(ERR, "Failed to delete element");
4145 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4147 if (vsi->type != I40E_VSI_SRIOV)
4148 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4151 return I40E_SUCCESS;
4155 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4157 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4158 struct i40e_aqc_remove_macvlan_element_data def_filter;
4159 struct i40e_mac_filter_info filter;
4162 if (vsi->type != I40E_VSI_MAIN)
4163 return I40E_ERR_CONFIG;
4164 memset(&def_filter, 0, sizeof(def_filter));
4165 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4167 def_filter.vlan_tag = 0;
4168 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4169 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4170 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4171 if (ret != I40E_SUCCESS) {
4172 struct i40e_mac_filter *f;
4173 struct ether_addr *mac;
4175 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4177 /* It needs to add the permanent mac into mac list */
4178 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4180 PMD_DRV_LOG(ERR, "failed to allocate memory");
4181 return I40E_ERR_NO_MEMORY;
4183 mac = &f->mac_info.mac_addr;
4184 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4186 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4187 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4192 (void)rte_memcpy(&filter.mac_addr,
4193 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4194 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4195 return i40e_vsi_add_mac(vsi, &filter);
4199 * i40e_vsi_get_bw_config - Query VSI BW Information
4200 * @vsi: the VSI to be queried
4202 * Returns 0 on success, negative value on failure
4204 static enum i40e_status_code
4205 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4207 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4208 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4209 struct i40e_hw *hw = &vsi->adapter->hw;
4214 memset(&bw_config, 0, sizeof(bw_config));
4215 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4216 if (ret != I40E_SUCCESS) {
4217 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4218 hw->aq.asq_last_status);
4222 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4223 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4224 &ets_sla_config, NULL);
4225 if (ret != I40E_SUCCESS) {
4226 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4227 "configuration %u", hw->aq.asq_last_status);
4231 /* store and print out BW info */
4232 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4233 vsi->bw_info.bw_max = bw_config.max_bw;
4234 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4235 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4236 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4237 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4239 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4240 vsi->bw_info.bw_ets_share_credits[i] =
4241 ets_sla_config.share_credits[i];
4242 vsi->bw_info.bw_ets_credits[i] =
4243 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4244 /* 4 bits per TC, 4th bit is reserved */
4245 vsi->bw_info.bw_ets_max[i] =
4246 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4247 RTE_LEN2MASK(3, uint8_t));
4248 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4249 vsi->bw_info.bw_ets_share_credits[i]);
4250 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4251 vsi->bw_info.bw_ets_credits[i]);
4252 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4253 vsi->bw_info.bw_ets_max[i]);
4256 return I40E_SUCCESS;
4259 /* i40e_enable_pf_lb
4260 * @pf: pointer to the pf structure
4262 * allow loopback on pf
4265 i40e_enable_pf_lb(struct i40e_pf *pf)
4267 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4268 struct i40e_vsi_context ctxt;
4271 /* Use the FW API if FW >= v5.0 */
4272 if (hw->aq.fw_maj_ver < 5) {
4273 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4277 memset(&ctxt, 0, sizeof(ctxt));
4278 ctxt.seid = pf->main_vsi_seid;
4279 ctxt.pf_num = hw->pf_id;
4280 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4282 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4283 ret, hw->aq.asq_last_status);
4286 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4287 ctxt.info.valid_sections =
4288 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4289 ctxt.info.switch_id |=
4290 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4292 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4294 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4295 hw->aq.asq_last_status);
4300 i40e_vsi_setup(struct i40e_pf *pf,
4301 enum i40e_vsi_type type,
4302 struct i40e_vsi *uplink_vsi,
4303 uint16_t user_param)
4305 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4306 struct i40e_vsi *vsi;
4307 struct i40e_mac_filter_info filter;
4309 struct i40e_vsi_context ctxt;
4310 struct ether_addr broadcast =
4311 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4313 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4314 uplink_vsi == NULL) {
4315 PMD_DRV_LOG(ERR, "VSI setup failed, "
4316 "VSI link shouldn't be NULL");
4320 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4321 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4322 "uplink VSI should be NULL");
4327 * 1.type is not MAIN and uplink vsi is not NULL
4328 * If uplink vsi didn't setup VEB, create one first under veb field
4329 * 2.type is SRIOV and the uplink is NULL
4330 * If floating VEB is NULL, create one veb under floating veb field
4333 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4334 uplink_vsi->veb == NULL) {
4335 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4337 if (uplink_vsi->veb == NULL) {
4338 PMD_DRV_LOG(ERR, "VEB setup failed");
4341 /* set ALLOWLOOPBACk on pf, when veb is created */
4342 i40e_enable_pf_lb(pf);
4345 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4346 pf->main_vsi->floating_veb == NULL) {
4347 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4349 if (pf->main_vsi->floating_veb == NULL) {
4350 PMD_DRV_LOG(ERR, "VEB setup failed");
4355 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4357 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4360 TAILQ_INIT(&vsi->mac_list);
4362 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4363 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4364 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4365 vsi->user_param = user_param;
4366 /* Allocate queues */
4367 switch (vsi->type) {
4368 case I40E_VSI_MAIN :
4369 vsi->nb_qps = pf->lan_nb_qps;
4371 case I40E_VSI_SRIOV :
4372 vsi->nb_qps = pf->vf_nb_qps;
4374 case I40E_VSI_VMDQ2:
4375 vsi->nb_qps = pf->vmdq_nb_qps;
4378 vsi->nb_qps = pf->fdir_nb_qps;
4384 * The filter status descriptor is reported in rx queue 0,
4385 * while the tx queue for fdir filter programming has no
4386 * such constraints, can be non-zero queues.
4387 * To simplify it, choose FDIR vsi use queue 0 pair.
4388 * To make sure it will use queue 0 pair, queue allocation
4389 * need be done before this function is called
4391 if (type != I40E_VSI_FDIR) {
4392 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4394 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4398 vsi->base_queue = ret;
4400 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4402 /* VF has MSIX interrupt in VF range, don't allocate here */
4403 if (type == I40E_VSI_MAIN) {
4404 ret = i40e_res_pool_alloc(&pf->msix_pool,
4405 RTE_MIN(vsi->nb_qps,
4406 RTE_MAX_RXTX_INTR_VEC_ID));
4408 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4410 goto fail_queue_alloc;
4412 vsi->msix_intr = ret;
4413 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4414 } else if (type != I40E_VSI_SRIOV) {
4415 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4417 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4418 goto fail_queue_alloc;
4420 vsi->msix_intr = ret;
4428 if (type == I40E_VSI_MAIN) {
4429 /* For main VSI, no need to add since it's default one */
4430 vsi->uplink_seid = pf->mac_seid;
4431 vsi->seid = pf->main_vsi_seid;
4432 /* Bind queues with specific MSIX interrupt */
4434 * Needs 2 interrupt at least, one for misc cause which will
4435 * enabled from OS side, Another for queues binding the
4436 * interrupt from device side only.
4439 /* Get default VSI parameters from hardware */
4440 memset(&ctxt, 0, sizeof(ctxt));
4441 ctxt.seid = vsi->seid;
4442 ctxt.pf_num = hw->pf_id;
4443 ctxt.uplink_seid = vsi->uplink_seid;
4445 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4446 if (ret != I40E_SUCCESS) {
4447 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4448 goto fail_msix_alloc;
4450 (void)rte_memcpy(&vsi->info, &ctxt.info,
4451 sizeof(struct i40e_aqc_vsi_properties_data));
4452 vsi->vsi_id = ctxt.vsi_number;
4453 vsi->info.valid_sections = 0;
4455 /* Configure tc, enabled TC0 only */
4456 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4458 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4459 goto fail_msix_alloc;
4462 /* TC, queue mapping */
4463 memset(&ctxt, 0, sizeof(ctxt));
4464 vsi->info.valid_sections |=
4465 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4466 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4467 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4468 (void)rte_memcpy(&ctxt.info, &vsi->info,
4469 sizeof(struct i40e_aqc_vsi_properties_data));
4470 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4471 I40E_DEFAULT_TCMAP);
4472 if (ret != I40E_SUCCESS) {
4473 PMD_DRV_LOG(ERR, "Failed to configure "
4474 "TC queue mapping");
4475 goto fail_msix_alloc;
4477 ctxt.seid = vsi->seid;
4478 ctxt.pf_num = hw->pf_id;
4479 ctxt.uplink_seid = vsi->uplink_seid;
4482 /* Update VSI parameters */
4483 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4484 if (ret != I40E_SUCCESS) {
4485 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4486 goto fail_msix_alloc;
4489 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4490 sizeof(vsi->info.tc_mapping));
4491 (void)rte_memcpy(&vsi->info.queue_mapping,
4492 &ctxt.info.queue_mapping,
4493 sizeof(vsi->info.queue_mapping));
4494 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4495 vsi->info.valid_sections = 0;
4497 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4501 * Updating default filter settings are necessary to prevent
4502 * reception of tagged packets.
4503 * Some old firmware configurations load a default macvlan
4504 * filter which accepts both tagged and untagged packets.
4505 * The updating is to use a normal filter instead if needed.
4506 * For NVM 4.2.2 or after, the updating is not needed anymore.
4507 * The firmware with correct configurations load the default
4508 * macvlan filter which is expected and cannot be removed.
4510 i40e_update_default_filter_setting(vsi);
4511 i40e_config_qinq(hw, vsi);
4512 } else if (type == I40E_VSI_SRIOV) {
4513 memset(&ctxt, 0, sizeof(ctxt));
4515 * For other VSI, the uplink_seid equals to uplink VSI's
4516 * uplink_seid since they share same VEB
4518 if (uplink_vsi == NULL)
4519 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4521 vsi->uplink_seid = uplink_vsi->uplink_seid;
4522 ctxt.pf_num = hw->pf_id;
4523 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4524 ctxt.uplink_seid = vsi->uplink_seid;
4525 ctxt.connection_type = 0x1;
4526 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4528 /* Use the VEB configuration if FW >= v5.0 */
4529 if (hw->aq.fw_maj_ver >= 5) {
4530 /* Configure switch ID */
4531 ctxt.info.valid_sections |=
4532 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4533 ctxt.info.switch_id =
4534 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4537 /* Configure port/vlan */
4538 ctxt.info.valid_sections |=
4539 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4540 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4541 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4542 I40E_DEFAULT_TCMAP);
4543 if (ret != I40E_SUCCESS) {
4544 PMD_DRV_LOG(ERR, "Failed to configure "
4545 "TC queue mapping");
4546 goto fail_msix_alloc;
4548 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4549 ctxt.info.valid_sections |=
4550 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4552 * Since VSI is not created yet, only configure parameter,
4553 * will add vsi below.
4556 i40e_config_qinq(hw, vsi);
4557 } else if (type == I40E_VSI_VMDQ2) {
4558 memset(&ctxt, 0, sizeof(ctxt));
4560 * For other VSI, the uplink_seid equals to uplink VSI's
4561 * uplink_seid since they share same VEB
4563 vsi->uplink_seid = uplink_vsi->uplink_seid;
4564 ctxt.pf_num = hw->pf_id;
4566 ctxt.uplink_seid = vsi->uplink_seid;
4567 ctxt.connection_type = 0x1;
4568 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4570 ctxt.info.valid_sections |=
4571 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4572 /* user_param carries flag to enable loop back */
4574 ctxt.info.switch_id =
4575 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4576 ctxt.info.switch_id |=
4577 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4580 /* Configure port/vlan */
4581 ctxt.info.valid_sections |=
4582 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4583 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4584 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4585 I40E_DEFAULT_TCMAP);
4586 if (ret != I40E_SUCCESS) {
4587 PMD_DRV_LOG(ERR, "Failed to configure "
4588 "TC queue mapping");
4589 goto fail_msix_alloc;
4591 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4592 ctxt.info.valid_sections |=
4593 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4594 } else if (type == I40E_VSI_FDIR) {
4595 memset(&ctxt, 0, sizeof(ctxt));
4596 vsi->uplink_seid = uplink_vsi->uplink_seid;
4597 ctxt.pf_num = hw->pf_id;
4599 ctxt.uplink_seid = vsi->uplink_seid;
4600 ctxt.connection_type = 0x1; /* regular data port */
4601 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4602 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4603 I40E_DEFAULT_TCMAP);
4604 if (ret != I40E_SUCCESS) {
4605 PMD_DRV_LOG(ERR, "Failed to configure "
4606 "TC queue mapping.");
4607 goto fail_msix_alloc;
4609 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4610 ctxt.info.valid_sections |=
4611 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4613 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4614 goto fail_msix_alloc;
4617 if (vsi->type != I40E_VSI_MAIN) {
4618 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4619 if (ret != I40E_SUCCESS) {
4620 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4621 hw->aq.asq_last_status);
4622 goto fail_msix_alloc;
4624 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4625 vsi->info.valid_sections = 0;
4626 vsi->seid = ctxt.seid;
4627 vsi->vsi_id = ctxt.vsi_number;
4628 vsi->sib_vsi_list.vsi = vsi;
4629 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4630 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4631 &vsi->sib_vsi_list, list);
4633 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4634 &vsi->sib_vsi_list, list);
4638 /* MAC/VLAN configuration */
4639 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4640 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4642 ret = i40e_vsi_add_mac(vsi, &filter);
4643 if (ret != I40E_SUCCESS) {
4644 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4645 goto fail_msix_alloc;
4648 /* Get VSI BW information */
4649 i40e_vsi_get_bw_config(vsi);
4652 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4654 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4660 /* Configure vlan filter on or off */
4662 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4665 struct i40e_mac_filter *f;
4667 struct i40e_mac_filter_info *mac_filter;
4668 enum rte_mac_filter_type desired_filter;
4669 int ret = I40E_SUCCESS;
4672 /* Filter to match MAC and VLAN */
4673 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4675 /* Filter to match only MAC */
4676 desired_filter = RTE_MAC_PERFECT_MATCH;
4681 mac_filter = rte_zmalloc("mac_filter_info_data",
4682 num * sizeof(*mac_filter), 0);
4683 if (mac_filter == NULL) {
4684 PMD_DRV_LOG(ERR, "failed to allocate memory");
4685 return I40E_ERR_NO_MEMORY;
4690 /* Remove all existing mac */
4691 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4692 mac_filter[i] = f->mac_info;
4693 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4695 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4696 on ? "enable" : "disable");
4702 /* Override with new filter */
4703 for (i = 0; i < num; i++) {
4704 mac_filter[i].filter_type = desired_filter;
4705 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4707 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4708 on ? "enable" : "disable");
4714 rte_free(mac_filter);
4718 /* Configure vlan stripping on or off */
4720 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4722 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4723 struct i40e_vsi_context ctxt;
4725 int ret = I40E_SUCCESS;
4727 /* Check if it has been already on or off */
4728 if (vsi->info.valid_sections &
4729 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4731 if ((vsi->info.port_vlan_flags &
4732 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4733 return 0; /* already on */
4735 if ((vsi->info.port_vlan_flags &
4736 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4737 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4738 return 0; /* already off */
4743 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4745 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4746 vsi->info.valid_sections =
4747 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4748 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4749 vsi->info.port_vlan_flags |= vlan_flags;
4750 ctxt.seid = vsi->seid;
4751 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4752 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4754 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4755 on ? "enable" : "disable");
4761 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4763 struct rte_eth_dev_data *data = dev->data;
4767 /* Apply vlan offload setting */
4768 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4769 i40e_vlan_offload_set(dev, mask);
4771 /* Apply double-vlan setting, not implemented yet */
4773 /* Apply pvid setting */
4774 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4775 data->dev_conf.txmode.hw_vlan_insert_pvid);
4777 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4783 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4785 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4787 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4791 i40e_update_flow_control(struct i40e_hw *hw)
4793 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4794 struct i40e_link_status link_status;
4795 uint32_t rxfc = 0, txfc = 0, reg;
4799 memset(&link_status, 0, sizeof(link_status));
4800 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4801 if (ret != I40E_SUCCESS) {
4802 PMD_DRV_LOG(ERR, "Failed to get link status information");
4803 goto write_reg; /* Disable flow control */
4806 an_info = hw->phy.link_info.an_info;
4807 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4808 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4809 ret = I40E_ERR_NOT_READY;
4810 goto write_reg; /* Disable flow control */
4813 * If link auto negotiation is enabled, flow control needs to
4814 * be configured according to it
4816 switch (an_info & I40E_LINK_PAUSE_RXTX) {
4817 case I40E_LINK_PAUSE_RXTX:
4820 hw->fc.current_mode = I40E_FC_FULL;
4822 case I40E_AQ_LINK_PAUSE_RX:
4824 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4826 case I40E_AQ_LINK_PAUSE_TX:
4828 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4831 hw->fc.current_mode = I40E_FC_NONE;
4836 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4837 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4838 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4839 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4840 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4841 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4848 i40e_pf_setup(struct i40e_pf *pf)
4850 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4851 struct i40e_filter_control_settings settings;
4852 struct i40e_vsi *vsi;
4855 /* Clear all stats counters */
4856 pf->offset_loaded = FALSE;
4857 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4858 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4860 ret = i40e_pf_get_switch_config(pf);
4861 if (ret != I40E_SUCCESS) {
4862 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4865 if (pf->flags & I40E_FLAG_FDIR) {
4866 /* make queue allocated first, let FDIR use queue pair 0*/
4867 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4868 if (ret != I40E_FDIR_QUEUE_ID) {
4869 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4871 pf->flags &= ~I40E_FLAG_FDIR;
4874 /* main VSI setup */
4875 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4877 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4878 return I40E_ERR_NOT_READY;
4882 /* Configure filter control */
4883 memset(&settings, 0, sizeof(settings));
4884 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4885 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4886 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4887 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4889 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4890 hw->func_caps.rss_table_size);
4891 return I40E_ERR_PARAM;
4893 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4894 "size: %u\n", hw->func_caps.rss_table_size);
4895 pf->hash_lut_size = hw->func_caps.rss_table_size;
4897 /* Enable ethtype and macvlan filters */
4898 settings.enable_ethtype = TRUE;
4899 settings.enable_macvlan = TRUE;
4900 ret = i40e_set_filter_control(hw, &settings);
4902 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4905 /* Update flow control according to the auto negotiation */
4906 i40e_update_flow_control(hw);
4908 return I40E_SUCCESS;
4912 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4918 * Set or clear TX Queue Disable flags,
4919 * which is required by hardware.
4921 i40e_pre_tx_queue_cfg(hw, q_idx, on);
4922 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4924 /* Wait until the request is finished */
4925 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4926 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4927 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4928 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4929 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4935 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4936 return I40E_SUCCESS; /* already on, skip next steps */
4938 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4939 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4941 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4942 return I40E_SUCCESS; /* already off, skip next steps */
4943 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4945 /* Write the register */
4946 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4947 /* Check the result */
4948 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4949 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4950 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4952 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4953 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4956 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4957 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4961 /* Check if it is timeout */
4962 if (j >= I40E_CHK_Q_ENA_COUNT) {
4963 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4964 (on ? "enable" : "disable"), q_idx);
4965 return I40E_ERR_TIMEOUT;
4968 return I40E_SUCCESS;
4971 /* Swith on or off the tx queues */
4973 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4975 struct rte_eth_dev_data *dev_data = pf->dev_data;
4976 struct i40e_tx_queue *txq;
4977 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4981 for (i = 0; i < dev_data->nb_tx_queues; i++) {
4982 txq = dev_data->tx_queues[i];
4983 /* Don't operate the queue if not configured or
4984 * if starting only per queue */
4985 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4988 ret = i40e_dev_tx_queue_start(dev, i);
4990 ret = i40e_dev_tx_queue_stop(dev, i);
4991 if ( ret != I40E_SUCCESS)
4995 return I40E_SUCCESS;
4999 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5004 /* Wait until the request is finished */
5005 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5006 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5007 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5008 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5009 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5014 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5015 return I40E_SUCCESS; /* Already on, skip next steps */
5016 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5018 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5019 return I40E_SUCCESS; /* Already off, skip next steps */
5020 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5023 /* Write the register */
5024 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5025 /* Check the result */
5026 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5027 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5028 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5030 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5031 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5034 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5035 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5040 /* Check if it is timeout */
5041 if (j >= I40E_CHK_Q_ENA_COUNT) {
5042 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5043 (on ? "enable" : "disable"), q_idx);
5044 return I40E_ERR_TIMEOUT;
5047 return I40E_SUCCESS;
5049 /* Switch on or off the rx queues */
5051 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5053 struct rte_eth_dev_data *dev_data = pf->dev_data;
5054 struct i40e_rx_queue *rxq;
5055 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5059 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5060 rxq = dev_data->rx_queues[i];
5061 /* Don't operate the queue if not configured or
5062 * if starting only per queue */
5063 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5066 ret = i40e_dev_rx_queue_start(dev, i);
5068 ret = i40e_dev_rx_queue_stop(dev, i);
5069 if (ret != I40E_SUCCESS)
5073 return I40E_SUCCESS;
5076 /* Switch on or off all the rx/tx queues */
5078 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5083 /* enable rx queues before enabling tx queues */
5084 ret = i40e_dev_switch_rx_queues(pf, on);
5086 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5089 ret = i40e_dev_switch_tx_queues(pf, on);
5091 /* Stop tx queues before stopping rx queues */
5092 ret = i40e_dev_switch_tx_queues(pf, on);
5094 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5097 ret = i40e_dev_switch_rx_queues(pf, on);
5103 /* Initialize VSI for TX */
5105 i40e_dev_tx_init(struct i40e_pf *pf)
5107 struct rte_eth_dev_data *data = pf->dev_data;
5109 uint32_t ret = I40E_SUCCESS;
5110 struct i40e_tx_queue *txq;
5112 for (i = 0; i < data->nb_tx_queues; i++) {
5113 txq = data->tx_queues[i];
5114 if (!txq || !txq->q_set)
5116 ret = i40e_tx_queue_init(txq);
5117 if (ret != I40E_SUCCESS)
5120 if (ret == I40E_SUCCESS)
5121 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5127 /* Initialize VSI for RX */
5129 i40e_dev_rx_init(struct i40e_pf *pf)
5131 struct rte_eth_dev_data *data = pf->dev_data;
5132 int ret = I40E_SUCCESS;
5134 struct i40e_rx_queue *rxq;
5136 i40e_pf_config_mq_rx(pf);
5137 for (i = 0; i < data->nb_rx_queues; i++) {
5138 rxq = data->rx_queues[i];
5139 if (!rxq || !rxq->q_set)
5142 ret = i40e_rx_queue_init(rxq);
5143 if (ret != I40E_SUCCESS) {
5144 PMD_DRV_LOG(ERR, "Failed to do RX queue "
5149 if (ret == I40E_SUCCESS)
5150 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5157 i40e_dev_rxtx_init(struct i40e_pf *pf)
5161 err = i40e_dev_tx_init(pf);
5163 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5166 err = i40e_dev_rx_init(pf);
5168 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5176 i40e_vmdq_setup(struct rte_eth_dev *dev)
5178 struct rte_eth_conf *conf = &dev->data->dev_conf;
5179 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5180 int i, err, conf_vsis, j, loop;
5181 struct i40e_vsi *vsi;
5182 struct i40e_vmdq_info *vmdq_info;
5183 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5184 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5187 * Disable interrupt to avoid message from VF. Furthermore, it will
5188 * avoid race condition in VSI creation/destroy.
5190 i40e_pf_disable_irq0(hw);
5192 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5193 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5197 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5198 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5199 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5200 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5201 pf->max_nb_vmdq_vsi);
5205 if (pf->vmdq != NULL) {
5206 PMD_INIT_LOG(INFO, "VMDQ already configured");
5210 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5211 sizeof(*vmdq_info) * conf_vsis, 0);
5213 if (pf->vmdq == NULL) {
5214 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5218 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5220 /* Create VMDQ VSI */
5221 for (i = 0; i < conf_vsis; i++) {
5222 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5223 vmdq_conf->enable_loop_back);
5225 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5229 vmdq_info = &pf->vmdq[i];
5231 vmdq_info->vsi = vsi;
5233 pf->nb_cfg_vmdq_vsi = conf_vsis;
5235 /* Configure Vlan */
5236 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5237 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5238 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5239 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5240 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5241 vmdq_conf->pool_map[i].vlan_id, j);
5243 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5244 vmdq_conf->pool_map[i].vlan_id);
5246 PMD_INIT_LOG(ERR, "Failed to add vlan");
5254 i40e_pf_enable_irq0(hw);
5259 for (i = 0; i < conf_vsis; i++)
5260 if (pf->vmdq[i].vsi == NULL)
5263 i40e_vsi_release(pf->vmdq[i].vsi);
5267 i40e_pf_enable_irq0(hw);
5272 i40e_stat_update_32(struct i40e_hw *hw,
5280 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5284 if (new_data >= *offset)
5285 *stat = (uint64_t)(new_data - *offset);
5287 *stat = (uint64_t)((new_data +
5288 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5292 i40e_stat_update_48(struct i40e_hw *hw,
5301 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5302 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5303 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5308 if (new_data >= *offset)
5309 *stat = new_data - *offset;
5311 *stat = (uint64_t)((new_data +
5312 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5314 *stat &= I40E_48_BIT_MASK;
5319 i40e_pf_disable_irq0(struct i40e_hw *hw)
5321 /* Disable all interrupt types */
5322 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5323 I40E_WRITE_FLUSH(hw);
5328 i40e_pf_enable_irq0(struct i40e_hw *hw)
5330 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5331 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5332 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5333 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5334 I40E_WRITE_FLUSH(hw);
5338 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5340 /* read pending request and disable first */
5341 i40e_pf_disable_irq0(hw);
5342 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5343 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5344 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5347 /* Link no queues with irq0 */
5348 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5349 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5353 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5355 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5356 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5359 uint32_t index, offset, val;
5364 * Try to find which VF trigger a reset, use absolute VF id to access
5365 * since the reg is global register.
5367 for (i = 0; i < pf->vf_num; i++) {
5368 abs_vf_id = hw->func_caps.vf_base_id + i;
5369 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5370 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5371 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5372 /* VFR event occured */
5373 if (val & (0x1 << offset)) {
5376 /* Clear the event first */
5377 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5379 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5381 * Only notify a VF reset event occured,
5382 * don't trigger another SW reset
5384 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5385 if (ret != I40E_SUCCESS)
5386 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5392 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5394 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5395 struct i40e_arq_event_info info;
5396 uint16_t pending, opcode;
5399 info.buf_len = I40E_AQ_BUF_SZ;
5400 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5401 if (!info.msg_buf) {
5402 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5408 ret = i40e_clean_arq_element(hw, &info, &pending);
5410 if (ret != I40E_SUCCESS) {
5411 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5412 "aq_err: %u", hw->aq.asq_last_status);
5415 opcode = rte_le_to_cpu_16(info.desc.opcode);
5418 case i40e_aqc_opc_send_msg_to_pf:
5419 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5420 i40e_pf_host_handle_vf_msg(dev,
5421 rte_le_to_cpu_16(info.desc.retval),
5422 rte_le_to_cpu_32(info.desc.cookie_high),
5423 rte_le_to_cpu_32(info.desc.cookie_low),
5428 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5433 rte_free(info.msg_buf);
5437 * Interrupt handler is registered as the alarm callback for handling LSC
5438 * interrupt in a definite of time, in order to wait the NIC into a stable
5439 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5440 * no need for link down interrupt.
5443 i40e_dev_interrupt_delayed_handler(void *param)
5445 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5446 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5449 /* read interrupt causes again */
5450 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5452 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5453 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5454 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5455 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5456 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5457 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5458 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5459 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5460 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5461 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5462 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5464 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5465 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5466 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5467 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5468 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5470 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5471 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5472 i40e_dev_handle_vfr_event(dev);
5474 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5475 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5476 i40e_dev_handle_aq_msg(dev);
5479 /* handle the link up interrupt in an alarm callback */
5480 i40e_dev_link_update(dev, 0);
5481 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5483 i40e_pf_enable_irq0(hw);
5484 rte_intr_enable(&(dev->pci_dev->intr_handle));
5488 * Interrupt handler triggered by NIC for handling
5489 * specific interrupt.
5492 * Pointer to interrupt handle.
5494 * The address of parameter (struct rte_eth_dev *) regsitered before.
5500 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5503 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5504 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5507 /* Disable interrupt */
5508 i40e_pf_disable_irq0(hw);
5510 /* read out interrupt causes */
5511 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5513 /* No interrupt event indicated */
5514 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5515 PMD_DRV_LOG(INFO, "No interrupt event");
5518 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5519 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5520 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5521 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5522 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5523 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5524 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5525 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5526 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5527 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5528 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5529 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5530 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5531 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5532 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5533 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5535 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5536 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5537 i40e_dev_handle_vfr_event(dev);
5539 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5540 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5541 i40e_dev_handle_aq_msg(dev);
5544 /* Link Status Change interrupt */
5545 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5546 #define I40E_US_PER_SECOND 1000000
5547 struct rte_eth_link link;
5549 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5550 memset(&link, 0, sizeof(link));
5551 rte_i40e_dev_atomic_read_link_status(dev, &link);
5552 i40e_dev_link_update(dev, 0);
5555 * For link up interrupt, it needs to wait 1 second to let the
5556 * hardware be a stable state. Otherwise several consecutive
5557 * interrupts can be observed.
5558 * For link down interrupt, no need to wait.
5560 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5561 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5564 _rte_eth_dev_callback_process(dev,
5565 RTE_ETH_EVENT_INTR_LSC);
5569 /* Enable interrupt */
5570 i40e_pf_enable_irq0(hw);
5571 rte_intr_enable(&(dev->pci_dev->intr_handle));
5575 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5576 struct i40e_macvlan_filter *filter,
5579 int ele_num, ele_buff_size;
5580 int num, actual_num, i;
5582 int ret = I40E_SUCCESS;
5583 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5584 struct i40e_aqc_add_macvlan_element_data *req_list;
5586 if (filter == NULL || total == 0)
5587 return I40E_ERR_PARAM;
5588 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5589 ele_buff_size = hw->aq.asq_buf_size;
5591 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5592 if (req_list == NULL) {
5593 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5594 return I40E_ERR_NO_MEMORY;
5599 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5600 memset(req_list, 0, ele_buff_size);
5602 for (i = 0; i < actual_num; i++) {
5603 (void)rte_memcpy(req_list[i].mac_addr,
5604 &filter[num + i].macaddr, ETH_ADDR_LEN);
5605 req_list[i].vlan_tag =
5606 rte_cpu_to_le_16(filter[num + i].vlan_id);
5608 switch (filter[num + i].filter_type) {
5609 case RTE_MAC_PERFECT_MATCH:
5610 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5611 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5613 case RTE_MACVLAN_PERFECT_MATCH:
5614 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5616 case RTE_MAC_HASH_MATCH:
5617 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5618 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5620 case RTE_MACVLAN_HASH_MATCH:
5621 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5624 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5625 ret = I40E_ERR_PARAM;
5629 req_list[i].queue_number = 0;
5631 req_list[i].flags = rte_cpu_to_le_16(flags);
5634 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5636 if (ret != I40E_SUCCESS) {
5637 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5641 } while (num < total);
5649 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5650 struct i40e_macvlan_filter *filter,
5653 int ele_num, ele_buff_size;
5654 int num, actual_num, i;
5656 int ret = I40E_SUCCESS;
5657 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5658 struct i40e_aqc_remove_macvlan_element_data *req_list;
5660 if (filter == NULL || total == 0)
5661 return I40E_ERR_PARAM;
5663 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5664 ele_buff_size = hw->aq.asq_buf_size;
5666 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5667 if (req_list == NULL) {
5668 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5669 return I40E_ERR_NO_MEMORY;
5674 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5675 memset(req_list, 0, ele_buff_size);
5677 for (i = 0; i < actual_num; i++) {
5678 (void)rte_memcpy(req_list[i].mac_addr,
5679 &filter[num + i].macaddr, ETH_ADDR_LEN);
5680 req_list[i].vlan_tag =
5681 rte_cpu_to_le_16(filter[num + i].vlan_id);
5683 switch (filter[num + i].filter_type) {
5684 case RTE_MAC_PERFECT_MATCH:
5685 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5686 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5688 case RTE_MACVLAN_PERFECT_MATCH:
5689 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5691 case RTE_MAC_HASH_MATCH:
5692 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5693 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5695 case RTE_MACVLAN_HASH_MATCH:
5696 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5699 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5700 ret = I40E_ERR_PARAM;
5703 req_list[i].flags = rte_cpu_to_le_16(flags);
5706 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5708 if (ret != I40E_SUCCESS) {
5709 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5713 } while (num < total);
5720 /* Find out specific MAC filter */
5721 static struct i40e_mac_filter *
5722 i40e_find_mac_filter(struct i40e_vsi *vsi,
5723 struct ether_addr *macaddr)
5725 struct i40e_mac_filter *f;
5727 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5728 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5736 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5739 uint32_t vid_idx, vid_bit;
5741 if (vlan_id > ETH_VLAN_ID_MAX)
5744 vid_idx = I40E_VFTA_IDX(vlan_id);
5745 vid_bit = I40E_VFTA_BIT(vlan_id);
5747 if (vsi->vfta[vid_idx] & vid_bit)
5754 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5755 uint16_t vlan_id, bool on)
5757 uint32_t vid_idx, vid_bit;
5759 if (vlan_id > ETH_VLAN_ID_MAX)
5762 vid_idx = I40E_VFTA_IDX(vlan_id);
5763 vid_bit = I40E_VFTA_BIT(vlan_id);
5766 vsi->vfta[vid_idx] |= vid_bit;
5768 vsi->vfta[vid_idx] &= ~vid_bit;
5772 * Find all vlan options for specific mac addr,
5773 * return with actual vlan found.
5776 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5777 struct i40e_macvlan_filter *mv_f,
5778 int num, struct ether_addr *addr)
5784 * Not to use i40e_find_vlan_filter to decrease the loop time,
5785 * although the code looks complex.
5787 if (num < vsi->vlan_num)
5788 return I40E_ERR_PARAM;
5791 for (j = 0; j < I40E_VFTA_SIZE; j++) {
5793 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5794 if (vsi->vfta[j] & (1 << k)) {
5796 PMD_DRV_LOG(ERR, "vlan number "
5798 return I40E_ERR_PARAM;
5800 (void)rte_memcpy(&mv_f[i].macaddr,
5801 addr, ETH_ADDR_LEN);
5803 j * I40E_UINT32_BIT_SIZE + k;
5809 return I40E_SUCCESS;
5813 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5814 struct i40e_macvlan_filter *mv_f,
5819 struct i40e_mac_filter *f;
5821 if (num < vsi->mac_num)
5822 return I40E_ERR_PARAM;
5824 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5826 PMD_DRV_LOG(ERR, "buffer number not match");
5827 return I40E_ERR_PARAM;
5829 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5831 mv_f[i].vlan_id = vlan;
5832 mv_f[i].filter_type = f->mac_info.filter_type;
5836 return I40E_SUCCESS;
5840 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5843 struct i40e_mac_filter *f;
5844 struct i40e_macvlan_filter *mv_f;
5845 int ret = I40E_SUCCESS;
5847 if (vsi == NULL || vsi->mac_num == 0)
5848 return I40E_ERR_PARAM;
5850 /* Case that no vlan is set */
5851 if (vsi->vlan_num == 0)
5854 num = vsi->mac_num * vsi->vlan_num;
5856 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5858 PMD_DRV_LOG(ERR, "failed to allocate memory");
5859 return I40E_ERR_NO_MEMORY;
5863 if (vsi->vlan_num == 0) {
5864 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5865 (void)rte_memcpy(&mv_f[i].macaddr,
5866 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5867 mv_f[i].vlan_id = 0;
5871 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5872 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5873 vsi->vlan_num, &f->mac_info.mac_addr);
5874 if (ret != I40E_SUCCESS)
5880 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5888 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5890 struct i40e_macvlan_filter *mv_f;
5892 int ret = I40E_SUCCESS;
5894 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5895 return I40E_ERR_PARAM;
5897 /* If it's already set, just return */
5898 if (i40e_find_vlan_filter(vsi,vlan))
5899 return I40E_SUCCESS;
5901 mac_num = vsi->mac_num;
5904 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5905 return I40E_ERR_PARAM;
5908 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5911 PMD_DRV_LOG(ERR, "failed to allocate memory");
5912 return I40E_ERR_NO_MEMORY;
5915 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5917 if (ret != I40E_SUCCESS)
5920 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5922 if (ret != I40E_SUCCESS)
5925 i40e_set_vlan_filter(vsi, vlan, 1);
5935 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5937 struct i40e_macvlan_filter *mv_f;
5939 int ret = I40E_SUCCESS;
5942 * Vlan 0 is the generic filter for untagged packets
5943 * and can't be removed.
5945 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5946 return I40E_ERR_PARAM;
5948 /* If can't find it, just return */
5949 if (!i40e_find_vlan_filter(vsi, vlan))
5950 return I40E_ERR_PARAM;
5952 mac_num = vsi->mac_num;
5955 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5956 return I40E_ERR_PARAM;
5959 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5962 PMD_DRV_LOG(ERR, "failed to allocate memory");
5963 return I40E_ERR_NO_MEMORY;
5966 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5968 if (ret != I40E_SUCCESS)
5971 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5973 if (ret != I40E_SUCCESS)
5976 /* This is last vlan to remove, replace all mac filter with vlan 0 */
5977 if (vsi->vlan_num == 1) {
5978 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5979 if (ret != I40E_SUCCESS)
5982 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5983 if (ret != I40E_SUCCESS)
5987 i40e_set_vlan_filter(vsi, vlan, 0);
5997 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5999 struct i40e_mac_filter *f;
6000 struct i40e_macvlan_filter *mv_f;
6001 int i, vlan_num = 0;
6002 int ret = I40E_SUCCESS;
6004 /* If it's add and we've config it, return */
6005 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6007 return I40E_SUCCESS;
6008 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6009 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6012 * If vlan_num is 0, that's the first time to add mac,
6013 * set mask for vlan_id 0.
6015 if (vsi->vlan_num == 0) {
6016 i40e_set_vlan_filter(vsi, 0, 1);
6019 vlan_num = vsi->vlan_num;
6020 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6021 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6024 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6026 PMD_DRV_LOG(ERR, "failed to allocate memory");
6027 return I40E_ERR_NO_MEMORY;
6030 for (i = 0; i < vlan_num; i++) {
6031 mv_f[i].filter_type = mac_filter->filter_type;
6032 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6036 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6037 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6038 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6039 &mac_filter->mac_addr);
6040 if (ret != I40E_SUCCESS)
6044 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6045 if (ret != I40E_SUCCESS)
6048 /* Add the mac addr into mac list */
6049 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6051 PMD_DRV_LOG(ERR, "failed to allocate memory");
6052 ret = I40E_ERR_NO_MEMORY;
6055 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6057 f->mac_info.filter_type = mac_filter->filter_type;
6058 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6069 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6071 struct i40e_mac_filter *f;
6072 struct i40e_macvlan_filter *mv_f;
6074 enum rte_mac_filter_type filter_type;
6075 int ret = I40E_SUCCESS;
6077 /* Can't find it, return an error */
6078 f = i40e_find_mac_filter(vsi, addr);
6080 return I40E_ERR_PARAM;
6082 vlan_num = vsi->vlan_num;
6083 filter_type = f->mac_info.filter_type;
6084 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6085 filter_type == RTE_MACVLAN_HASH_MATCH) {
6086 if (vlan_num == 0) {
6087 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6088 return I40E_ERR_PARAM;
6090 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6091 filter_type == RTE_MAC_HASH_MATCH)
6094 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6096 PMD_DRV_LOG(ERR, "failed to allocate memory");
6097 return I40E_ERR_NO_MEMORY;
6100 for (i = 0; i < vlan_num; i++) {
6101 mv_f[i].filter_type = filter_type;
6102 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6105 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6106 filter_type == RTE_MACVLAN_HASH_MATCH) {
6107 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6108 if (ret != I40E_SUCCESS)
6112 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6113 if (ret != I40E_SUCCESS)
6116 /* Remove the mac addr into mac list */
6117 TAILQ_REMOVE(&vsi->mac_list, f, next);
6127 /* Configure hash enable flags for RSS */
6129 i40e_config_hena(uint64_t flags)
6136 if (flags & ETH_RSS_FRAG_IPV4)
6137 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6138 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
6139 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6140 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
6141 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6142 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6143 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6144 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6145 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6146 if (flags & ETH_RSS_FRAG_IPV6)
6147 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6148 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
6149 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6150 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
6151 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6152 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6153 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6154 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6155 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6156 if (flags & ETH_RSS_L2_PAYLOAD)
6157 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6162 /* Parse the hash enable flags */
6164 i40e_parse_hena(uint64_t flags)
6166 uint64_t rss_hf = 0;
6170 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6171 rss_hf |= ETH_RSS_FRAG_IPV4;
6172 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6173 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6174 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6175 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6176 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6177 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6178 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6179 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6180 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6181 rss_hf |= ETH_RSS_FRAG_IPV6;
6182 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6183 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6184 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6185 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6186 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6187 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6188 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6189 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6190 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6191 rss_hf |= ETH_RSS_L2_PAYLOAD;
6198 i40e_pf_disable_rss(struct i40e_pf *pf)
6200 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6203 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6204 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6205 hena &= ~I40E_RSS_HENA_ALL;
6206 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6207 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6208 I40E_WRITE_FLUSH(hw);
6212 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6214 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6215 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6218 if (!key || key_len == 0) {
6219 PMD_DRV_LOG(DEBUG, "No key to be configured");
6221 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6223 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6227 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6228 struct i40e_aqc_get_set_rss_key_data *key_dw =
6229 (struct i40e_aqc_get_set_rss_key_data *)key;
6231 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6233 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6236 uint32_t *hash_key = (uint32_t *)key;
6239 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6240 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6241 I40E_WRITE_FLUSH(hw);
6248 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6250 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6251 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6254 if (!key || !key_len)
6257 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6258 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6259 (struct i40e_aqc_get_set_rss_key_data *)key);
6261 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6265 uint32_t *key_dw = (uint32_t *)key;
6268 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6269 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6271 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6277 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6279 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6284 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6285 rss_conf->rss_key_len);
6289 rss_hf = rss_conf->rss_hf;
6290 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6291 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6292 hena &= ~I40E_RSS_HENA_ALL;
6293 hena |= i40e_config_hena(rss_hf);
6294 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6295 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6296 I40E_WRITE_FLUSH(hw);
6302 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6303 struct rte_eth_rss_conf *rss_conf)
6305 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6306 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6307 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6310 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6311 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6312 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6313 if (rss_hf != 0) /* Enable RSS */
6315 return 0; /* Nothing to do */
6318 if (rss_hf == 0) /* Disable RSS */
6321 return i40e_hw_rss_hash_set(pf, rss_conf);
6325 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6326 struct rte_eth_rss_conf *rss_conf)
6328 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6329 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6332 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6333 &rss_conf->rss_key_len);
6335 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6336 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6337 rss_conf->rss_hf = i40e_parse_hena(hena);
6343 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6345 switch (filter_type) {
6346 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6347 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6349 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6350 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6352 case RTE_TUNNEL_FILTER_IMAC_TENID:
6353 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6355 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6356 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6358 case ETH_TUNNEL_FILTER_IMAC:
6359 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6361 case ETH_TUNNEL_FILTER_OIP:
6362 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6364 case ETH_TUNNEL_FILTER_IIP:
6365 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6368 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6376 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6377 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6382 uint8_t i, tun_type = 0;
6383 /* internal varialbe to convert ipv6 byte order */
6384 uint32_t convert_ipv6[4];
6386 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6387 struct i40e_vsi *vsi = pf->main_vsi;
6388 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6389 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6391 cld_filter = rte_zmalloc("tunnel_filter",
6392 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6395 if (NULL == cld_filter) {
6396 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6399 pfilter = cld_filter;
6401 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6402 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6404 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6405 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6406 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6407 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6408 rte_memcpy(&pfilter->ipaddr.v4.data,
6409 &rte_cpu_to_le_32(ipv4_addr),
6410 sizeof(pfilter->ipaddr.v4.data));
6412 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6413 for (i = 0; i < 4; i++) {
6415 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6417 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6418 sizeof(pfilter->ipaddr.v6.data));
6421 /* check tunneled type */
6422 switch (tunnel_filter->tunnel_type) {
6423 case RTE_TUNNEL_TYPE_VXLAN:
6424 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6426 case RTE_TUNNEL_TYPE_NVGRE:
6427 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6429 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6430 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6433 /* Other tunnel types is not supported. */
6434 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6435 rte_free(cld_filter);
6439 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6442 rte_free(cld_filter);
6446 pfilter->flags |= rte_cpu_to_le_16(
6447 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6448 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6449 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6450 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6453 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6455 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6458 rte_free(cld_filter);
6463 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6467 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6468 if (pf->vxlan_ports[i] == port)
6476 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6480 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6482 idx = i40e_get_vxlan_port_idx(pf, port);
6484 /* Check if port already exists */
6486 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6490 /* Now check if there is space to add the new port */
6491 idx = i40e_get_vxlan_port_idx(pf, 0);
6493 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6494 "not adding port %d", port);
6498 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6501 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6505 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6508 /* New port: add it and mark its index in the bitmap */
6509 pf->vxlan_ports[idx] = port;
6510 pf->vxlan_bitmap |= (1 << idx);
6512 if (!(pf->flags & I40E_FLAG_VXLAN))
6513 pf->flags |= I40E_FLAG_VXLAN;
6519 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6522 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6524 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6525 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6529 idx = i40e_get_vxlan_port_idx(pf, port);
6532 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6536 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6537 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6541 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6544 pf->vxlan_ports[idx] = 0;
6545 pf->vxlan_bitmap &= ~(1 << idx);
6547 if (!pf->vxlan_bitmap)
6548 pf->flags &= ~I40E_FLAG_VXLAN;
6553 /* Add UDP tunneling port */
6555 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6556 struct rte_eth_udp_tunnel *udp_tunnel)
6559 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6561 if (udp_tunnel == NULL)
6564 switch (udp_tunnel->prot_type) {
6565 case RTE_TUNNEL_TYPE_VXLAN:
6566 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6569 case RTE_TUNNEL_TYPE_GENEVE:
6570 case RTE_TUNNEL_TYPE_TEREDO:
6571 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6576 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6584 /* Remove UDP tunneling port */
6586 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6587 struct rte_eth_udp_tunnel *udp_tunnel)
6590 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6592 if (udp_tunnel == NULL)
6595 switch (udp_tunnel->prot_type) {
6596 case RTE_TUNNEL_TYPE_VXLAN:
6597 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6599 case RTE_TUNNEL_TYPE_GENEVE:
6600 case RTE_TUNNEL_TYPE_TEREDO:
6601 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6605 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6613 /* Calculate the maximum number of contiguous PF queues that are configured */
6615 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6617 struct rte_eth_dev_data *data = pf->dev_data;
6619 struct i40e_rx_queue *rxq;
6622 for (i = 0; i < pf->lan_nb_qps; i++) {
6623 rxq = data->rx_queues[i];
6624 if (rxq && rxq->q_set)
6635 i40e_pf_config_rss(struct i40e_pf *pf)
6637 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6638 struct rte_eth_rss_conf rss_conf;
6639 uint32_t i, lut = 0;
6643 * If both VMDQ and RSS enabled, not all of PF queues are configured.
6644 * It's necessary to calulate the actual PF queues that are configured.
6646 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6647 num = i40e_pf_calc_configured_queues_num(pf);
6649 num = pf->dev_data->nb_rx_queues;
6651 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6652 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6656 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6660 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6663 lut = (lut << 8) | (j & ((0x1 <<
6664 hw->func_caps.rss_table_entry_width) - 1));
6666 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6669 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6670 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6671 i40e_pf_disable_rss(pf);
6674 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6675 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6676 /* Random default keys */
6677 static uint32_t rss_key_default[] = {0x6b793944,
6678 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6679 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6680 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6682 rss_conf.rss_key = (uint8_t *)rss_key_default;
6683 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6687 return i40e_hw_rss_hash_set(pf, &rss_conf);
6691 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6692 struct rte_eth_tunnel_filter_conf *filter)
6694 if (pf == NULL || filter == NULL) {
6695 PMD_DRV_LOG(ERR, "Invalid parameter");
6699 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6700 PMD_DRV_LOG(ERR, "Invalid queue ID");
6704 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6705 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6709 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6710 (is_zero_ether_addr(&filter->outer_mac))) {
6711 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6715 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6716 (is_zero_ether_addr(&filter->inner_mac))) {
6717 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6724 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6725 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
6727 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6732 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6733 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6736 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6737 } else if (len == 4) {
6738 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6740 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6745 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6752 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6753 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6759 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6766 switch (cfg->cfg_type) {
6767 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6768 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6771 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6779 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6780 enum rte_filter_op filter_op,
6783 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6784 int ret = I40E_ERR_PARAM;
6786 switch (filter_op) {
6787 case RTE_ETH_FILTER_SET:
6788 ret = i40e_dev_global_config_set(hw,
6789 (struct rte_eth_global_cfg *)arg);
6792 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6800 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6801 enum rte_filter_op filter_op,
6804 struct rte_eth_tunnel_filter_conf *filter;
6805 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6806 int ret = I40E_SUCCESS;
6808 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6810 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6811 return I40E_ERR_PARAM;
6813 switch (filter_op) {
6814 case RTE_ETH_FILTER_NOP:
6815 if (!(pf->flags & I40E_FLAG_VXLAN))
6816 ret = I40E_NOT_SUPPORTED;
6818 case RTE_ETH_FILTER_ADD:
6819 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6821 case RTE_ETH_FILTER_DELETE:
6822 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6825 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6826 ret = I40E_ERR_PARAM;
6834 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6837 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6840 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6841 ret = i40e_pf_config_rss(pf);
6843 i40e_pf_disable_rss(pf);
6848 /* Get the symmetric hash enable configurations per port */
6850 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6852 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6854 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6857 /* Set the symmetric hash enable configurations per port */
6859 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6861 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6864 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6865 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6869 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6871 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6872 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6876 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6878 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6879 I40E_WRITE_FLUSH(hw);
6883 * Get global configurations of hash function type and symmetric hash enable
6884 * per flow type (pctype). Note that global configuration means it affects all
6885 * the ports on the same NIC.
6888 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6889 struct rte_eth_hash_global_conf *g_cfg)
6891 uint32_t reg, mask = I40E_FLOW_TYPES;
6893 enum i40e_filter_pctype pctype;
6895 memset(g_cfg, 0, sizeof(*g_cfg));
6896 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6897 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6898 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6900 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6901 PMD_DRV_LOG(DEBUG, "Hash function is %s",
6902 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6904 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6905 if (!(mask & (1UL << i)))
6907 mask &= ~(1UL << i);
6908 /* Bit set indicats the coresponding flow type is supported */
6909 g_cfg->valid_bit_mask[0] |= (1UL << i);
6910 /* if flowtype is invalid, continue */
6911 if (!I40E_VALID_FLOW(i))
6913 pctype = i40e_flowtype_to_pctype(i);
6914 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6915 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6916 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6923 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6926 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6928 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6929 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6930 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6931 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6937 * As i40e supports less than 32 flow types, only first 32 bits need to
6940 mask0 = g_cfg->valid_bit_mask[0];
6941 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6943 /* Check if any unsupported flow type configured */
6944 if ((mask0 | i40e_mask) ^ i40e_mask)
6947 if (g_cfg->valid_bit_mask[i])
6955 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6961 * Set global configurations of hash function type and symmetric hash enable
6962 * per flow type (pctype). Note any modifying global configuration will affect
6963 * all the ports on the same NIC.
6966 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6967 struct rte_eth_hash_global_conf *g_cfg)
6972 uint32_t mask0 = g_cfg->valid_bit_mask[0];
6973 enum i40e_filter_pctype pctype;
6975 /* Check the input parameters */
6976 ret = i40e_hash_global_config_check(g_cfg);
6980 for (i = 0; mask0 && i < UINT32_BIT; i++) {
6981 if (!(mask0 & (1UL << i)))
6983 mask0 &= ~(1UL << i);
6984 /* if flowtype is invalid, continue */
6985 if (!I40E_VALID_FLOW(i))
6987 pctype = i40e_flowtype_to_pctype(i);
6988 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6989 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6990 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6993 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6994 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6996 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6997 PMD_DRV_LOG(DEBUG, "Hash function already set to "
7001 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7002 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7004 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7005 PMD_DRV_LOG(DEBUG, "Hash function already set to "
7009 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7011 /* Use the default, and keep it as it is */
7014 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7017 I40E_WRITE_FLUSH(hw);
7023 * Valid input sets for hash and flow director filters per PCTYPE
7026 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7027 enum rte_filter_type filter)
7031 static const uint64_t valid_hash_inset_table[] = {
7032 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7033 I40E_INSET_DMAC | I40E_INSET_SMAC |
7034 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7035 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7036 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7037 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7038 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7039 I40E_INSET_FLEX_PAYLOAD,
7040 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7041 I40E_INSET_DMAC | I40E_INSET_SMAC |
7042 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7043 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7044 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7045 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7046 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7047 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7048 I40E_INSET_FLEX_PAYLOAD,
7049 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7050 I40E_INSET_DMAC | I40E_INSET_SMAC |
7051 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7052 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7053 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7054 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7055 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7056 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7057 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7058 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7059 I40E_INSET_DMAC | I40E_INSET_SMAC |
7060 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7061 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7062 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7063 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7064 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7065 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7066 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7067 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7068 I40E_INSET_DMAC | I40E_INSET_SMAC |
7069 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7070 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7071 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7072 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7073 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7074 I40E_INSET_FLEX_PAYLOAD,
7075 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7076 I40E_INSET_DMAC | I40E_INSET_SMAC |
7077 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7078 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7079 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7080 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7081 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7082 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7083 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7084 I40E_INSET_DMAC | I40E_INSET_SMAC |
7085 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7086 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7087 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7088 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7089 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7090 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7091 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7092 I40E_INSET_DMAC | I40E_INSET_SMAC |
7093 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7094 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7095 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7096 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7097 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7098 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7099 I40E_INSET_FLEX_PAYLOAD,
7100 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7101 I40E_INSET_DMAC | I40E_INSET_SMAC |
7102 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7103 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7104 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7105 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7106 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7107 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7108 I40E_INSET_FLEX_PAYLOAD,
7109 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7110 I40E_INSET_DMAC | I40E_INSET_SMAC |
7111 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7112 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7113 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7114 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7115 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7116 I40E_INSET_FLEX_PAYLOAD,
7117 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7118 I40E_INSET_DMAC | I40E_INSET_SMAC |
7119 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7120 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7121 I40E_INSET_FLEX_PAYLOAD,
7125 * Flow director supports only fields defined in
7126 * union rte_eth_fdir_flow.
7128 static const uint64_t valid_fdir_inset_table[] = {
7129 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7130 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7131 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7132 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7133 I40E_INSET_IPV4_TTL,
7134 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7135 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7136 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7137 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7138 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7139 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7140 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7141 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7142 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7143 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7144 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7145 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7146 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7147 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7148 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7150 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7151 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7152 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7153 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7154 I40E_INSET_IPV4_TTL,
7155 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7156 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7157 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7158 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7159 I40E_INSET_IPV6_HOP_LIMIT,
7160 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7161 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7162 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7163 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7164 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7165 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7166 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7167 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7168 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7169 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7170 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7171 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7172 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7173 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7174 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7176 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7177 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7178 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7179 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7180 I40E_INSET_IPV6_HOP_LIMIT,
7181 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7182 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7183 I40E_INSET_LAST_ETHER_TYPE,
7186 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7188 if (filter == RTE_ETH_FILTER_HASH)
7189 valid = valid_hash_inset_table[pctype];
7191 valid = valid_fdir_inset_table[pctype];
7197 * Validate if the input set is allowed for a specific PCTYPE
7200 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7201 enum rte_filter_type filter, uint64_t inset)
7205 valid = i40e_get_valid_input_set(pctype, filter);
7206 if (inset & (~valid))
7212 /* default input set fields combination per pctype */
7214 i40e_get_default_input_set(uint16_t pctype)
7216 static const uint64_t default_inset_table[] = {
7217 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7218 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7219 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7220 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7221 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7222 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7223 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7224 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7225 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7226 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7227 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7229 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7230 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7231 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7232 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7233 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7234 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7235 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7236 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7237 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7238 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7239 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7240 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7241 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7243 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7244 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7245 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7246 I40E_INSET_LAST_ETHER_TYPE,
7249 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7252 return default_inset_table[pctype];
7256 * Parse the input set from index to logical bit masks
7259 i40e_parse_input_set(uint64_t *inset,
7260 enum i40e_filter_pctype pctype,
7261 enum rte_eth_input_set_field *field,
7267 static const struct {
7268 enum rte_eth_input_set_field field;
7270 } inset_convert_table[] = {
7271 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7272 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7273 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7274 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7275 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7276 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7277 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7278 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7279 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7280 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7281 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7282 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7283 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7284 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7285 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7286 I40E_INSET_IPV6_NEXT_HDR},
7287 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7288 I40E_INSET_IPV6_HOP_LIMIT},
7289 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7290 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7291 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7292 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7293 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7294 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7295 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7296 I40E_INSET_SCTP_VT},
7297 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7298 I40E_INSET_TUNNEL_DMAC},
7299 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7300 I40E_INSET_VLAN_TUNNEL},
7301 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7302 I40E_INSET_TUNNEL_ID},
7303 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7304 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7305 I40E_INSET_FLEX_PAYLOAD_W1},
7306 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7307 I40E_INSET_FLEX_PAYLOAD_W2},
7308 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7309 I40E_INSET_FLEX_PAYLOAD_W3},
7310 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7311 I40E_INSET_FLEX_PAYLOAD_W4},
7312 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7313 I40E_INSET_FLEX_PAYLOAD_W5},
7314 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7315 I40E_INSET_FLEX_PAYLOAD_W6},
7316 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7317 I40E_INSET_FLEX_PAYLOAD_W7},
7318 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7319 I40E_INSET_FLEX_PAYLOAD_W8},
7322 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7325 /* Only one item allowed for default or all */
7327 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7328 *inset = i40e_get_default_input_set(pctype);
7330 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7331 *inset = I40E_INSET_NONE;
7336 for (i = 0, *inset = 0; i < size; i++) {
7337 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7338 if (field[i] == inset_convert_table[j].field) {
7339 *inset |= inset_convert_table[j].inset;
7344 /* It contains unsupported input set, return immediately */
7345 if (j == RTE_DIM(inset_convert_table))
7353 * Translate the input set from bit masks to register aware bit masks
7357 i40e_translate_input_set_reg(uint64_t input)
7362 static const struct {
7366 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7367 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7368 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7369 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7370 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7371 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7372 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7373 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7374 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7375 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7376 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7377 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7378 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7379 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7380 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7381 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7382 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7383 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7384 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7385 {I40E_INSET_TUNNEL_DMAC,
7386 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7387 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7388 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7389 {I40E_INSET_TUNNEL_SRC_PORT,
7390 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7391 {I40E_INSET_TUNNEL_DST_PORT,
7392 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7393 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7394 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7395 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7396 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7397 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7398 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7399 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7400 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7401 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7407 /* Translate input set to register aware inset */
7408 for (i = 0; i < RTE_DIM(inset_map); i++) {
7409 if (input & inset_map[i].inset)
7410 val |= inset_map[i].inset_reg;
7417 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7420 uint64_t inset_need_mask = inset;
7422 static const struct {
7425 } inset_mask_map[] = {
7426 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7427 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7428 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7429 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7430 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7431 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7432 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7433 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7436 if (!inset || !mask || !nb_elem)
7439 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7440 /* Clear the inset bit, if no MASK is required,
7441 * for example proto + ttl
7443 if ((inset & inset_mask_map[i].inset) ==
7444 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7445 inset_need_mask &= ~inset_mask_map[i].inset;
7446 if (!inset_need_mask)
7449 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7450 if ((inset_need_mask & inset_mask_map[i].inset) ==
7451 inset_mask_map[i].inset) {
7452 if (idx >= nb_elem) {
7453 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7456 mask[idx] = inset_mask_map[i].mask;
7465 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7467 uint32_t reg = i40e_read_rx_ctl(hw, addr);
7469 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7471 i40e_write_rx_ctl(hw, addr, val);
7472 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7473 (uint32_t)i40e_read_rx_ctl(hw, addr));
7477 i40e_filter_input_set_init(struct i40e_pf *pf)
7479 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7480 enum i40e_filter_pctype pctype;
7481 uint64_t input_set, inset_reg;
7482 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7485 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7486 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7487 if (!I40E_VALID_PCTYPE(pctype))
7489 input_set = i40e_get_default_input_set(pctype);
7491 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7492 I40E_INSET_MASK_NUM_REG);
7495 inset_reg = i40e_translate_input_set_reg(input_set);
7497 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7498 (uint32_t)(inset_reg & UINT32_MAX));
7499 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7500 (uint32_t)((inset_reg >>
7501 I40E_32_BIT_WIDTH) & UINT32_MAX));
7502 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7503 (uint32_t)(inset_reg & UINT32_MAX));
7504 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7505 (uint32_t)((inset_reg >>
7506 I40E_32_BIT_WIDTH) & UINT32_MAX));
7508 for (i = 0; i < num; i++) {
7509 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7511 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7514 /*clear unused mask registers of the pctype */
7515 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7516 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7518 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7521 I40E_WRITE_FLUSH(hw);
7523 /* store the default input set */
7524 pf->hash_input_set[pctype] = input_set;
7525 pf->fdir.input_set[pctype] = input_set;
7530 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7531 struct rte_eth_input_set_conf *conf)
7533 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7534 enum i40e_filter_pctype pctype;
7535 uint64_t input_set, inset_reg = 0;
7536 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7540 PMD_DRV_LOG(ERR, "Invalid pointer");
7543 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7544 conf->op != RTE_ETH_INPUT_SET_ADD) {
7545 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7549 if (!I40E_VALID_FLOW(conf->flow_type)) {
7550 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7553 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7554 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7557 PMD_DRV_LOG(ERR, "Failed to parse input set");
7560 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7562 PMD_DRV_LOG(ERR, "Invalid input set");
7565 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7566 /* get inset value in register */
7567 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7568 inset_reg <<= I40E_32_BIT_WIDTH;
7569 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7570 input_set |= pf->hash_input_set[pctype];
7572 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7573 I40E_INSET_MASK_NUM_REG);
7577 inset_reg |= i40e_translate_input_set_reg(input_set);
7579 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7580 (uint32_t)(inset_reg & UINT32_MAX));
7581 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7582 (uint32_t)((inset_reg >>
7583 I40E_32_BIT_WIDTH) & UINT32_MAX));
7585 for (i = 0; i < num; i++)
7586 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7588 /*clear unused mask registers of the pctype */
7589 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7590 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7592 I40E_WRITE_FLUSH(hw);
7594 pf->hash_input_set[pctype] = input_set;
7599 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7600 struct rte_eth_input_set_conf *conf)
7602 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7603 enum i40e_filter_pctype pctype;
7604 uint64_t input_set, inset_reg = 0;
7605 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7609 PMD_DRV_LOG(ERR, "Invalid pointer");
7612 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7613 conf->op != RTE_ETH_INPUT_SET_ADD) {
7614 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7618 if (!I40E_VALID_FLOW(conf->flow_type)) {
7619 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7622 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7623 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7626 PMD_DRV_LOG(ERR, "Failed to parse input set");
7629 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7631 PMD_DRV_LOG(ERR, "Invalid input set");
7635 /* get inset value in register */
7636 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7637 inset_reg <<= I40E_32_BIT_WIDTH;
7638 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7640 /* Can not change the inset reg for flex payload for fdir,
7641 * it is done by writing I40E_PRTQF_FD_FLXINSET
7642 * in i40e_set_flex_mask_on_pctype.
7644 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7645 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7647 input_set |= pf->fdir.input_set[pctype];
7648 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7649 I40E_INSET_MASK_NUM_REG);
7653 inset_reg |= i40e_translate_input_set_reg(input_set);
7655 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7656 (uint32_t)(inset_reg & UINT32_MAX));
7657 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7658 (uint32_t)((inset_reg >>
7659 I40E_32_BIT_WIDTH) & UINT32_MAX));
7661 for (i = 0; i < num; i++)
7662 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7664 /*clear unused mask registers of the pctype */
7665 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7666 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7668 I40E_WRITE_FLUSH(hw);
7670 pf->fdir.input_set[pctype] = input_set;
7675 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7680 PMD_DRV_LOG(ERR, "Invalid pointer");
7684 switch (info->info_type) {
7685 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7686 i40e_get_symmetric_hash_enable_per_port(hw,
7687 &(info->info.enable));
7689 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7690 ret = i40e_get_hash_filter_global_config(hw,
7691 &(info->info.global_conf));
7694 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7704 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7709 PMD_DRV_LOG(ERR, "Invalid pointer");
7713 switch (info->info_type) {
7714 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7715 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7717 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7718 ret = i40e_set_hash_filter_global_config(hw,
7719 &(info->info.global_conf));
7721 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7722 ret = i40e_hash_filter_inset_select(hw,
7723 &(info->info.input_set_conf));
7727 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7736 /* Operations for hash function */
7738 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7739 enum rte_filter_op filter_op,
7742 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7745 switch (filter_op) {
7746 case RTE_ETH_FILTER_NOP:
7748 case RTE_ETH_FILTER_GET:
7749 ret = i40e_hash_filter_get(hw,
7750 (struct rte_eth_hash_filter_info *)arg);
7752 case RTE_ETH_FILTER_SET:
7753 ret = i40e_hash_filter_set(hw,
7754 (struct rte_eth_hash_filter_info *)arg);
7757 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7767 * Configure ethertype filter, which can director packet by filtering
7768 * with mac address and ether_type or only ether_type
7771 i40e_ethertype_filter_set(struct i40e_pf *pf,
7772 struct rte_eth_ethertype_filter *filter,
7775 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7776 struct i40e_control_filter_stats stats;
7780 if (filter->queue >= pf->dev_data->nb_rx_queues) {
7781 PMD_DRV_LOG(ERR, "Invalid queue ID");
7784 if (filter->ether_type == ETHER_TYPE_IPv4 ||
7785 filter->ether_type == ETHER_TYPE_IPv6) {
7786 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7787 " control packet filter.", filter->ether_type);
7790 if (filter->ether_type == ETHER_TYPE_VLAN)
7791 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7794 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7795 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7796 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7797 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7798 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7800 memset(&stats, 0, sizeof(stats));
7801 ret = i40e_aq_add_rem_control_packet_filter(hw,
7802 filter->mac_addr.addr_bytes,
7803 filter->ether_type, flags,
7805 filter->queue, add, &stats, NULL);
7807 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7808 " mac_etype_used = %u, etype_used = %u,"
7809 " mac_etype_free = %u, etype_free = %u\n",
7810 ret, stats.mac_etype_used, stats.etype_used,
7811 stats.mac_etype_free, stats.etype_free);
7818 * Handle operations for ethertype filter.
7821 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7822 enum rte_filter_op filter_op,
7825 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7828 if (filter_op == RTE_ETH_FILTER_NOP)
7832 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7837 switch (filter_op) {
7838 case RTE_ETH_FILTER_ADD:
7839 ret = i40e_ethertype_filter_set(pf,
7840 (struct rte_eth_ethertype_filter *)arg,
7843 case RTE_ETH_FILTER_DELETE:
7844 ret = i40e_ethertype_filter_set(pf,
7845 (struct rte_eth_ethertype_filter *)arg,
7849 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7857 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7858 enum rte_filter_type filter_type,
7859 enum rte_filter_op filter_op,
7867 switch (filter_type) {
7868 case RTE_ETH_FILTER_NONE:
7869 /* For global configuration */
7870 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7872 case RTE_ETH_FILTER_HASH:
7873 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7875 case RTE_ETH_FILTER_MACVLAN:
7876 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7878 case RTE_ETH_FILTER_ETHERTYPE:
7879 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7881 case RTE_ETH_FILTER_TUNNEL:
7882 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7884 case RTE_ETH_FILTER_FDIR:
7885 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7888 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7898 * Check and enable Extended Tag.
7899 * Enabling Extended Tag is important for 40G performance.
7902 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7907 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7910 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7914 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7915 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7920 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7923 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7927 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7928 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7931 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7932 ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7935 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7942 * As some registers wouldn't be reset unless a global hardware reset,
7943 * hardware initialization is needed to put those registers into an
7944 * expected initial state.
7947 i40e_hw_init(struct rte_eth_dev *dev)
7949 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7951 i40e_enable_extended_tag(dev);
7953 /* clear the PF Queue Filter control register */
7954 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7956 /* Disable symmetric hash per port */
7957 i40e_set_symmetric_hash_enable_per_port(hw, 0);
7960 enum i40e_filter_pctype
7961 i40e_flowtype_to_pctype(uint16_t flow_type)
7963 static const enum i40e_filter_pctype pctype_table[] = {
7964 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7965 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7966 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7967 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7968 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7969 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7970 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7971 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7972 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7973 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7974 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7975 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7976 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7977 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7978 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7979 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7980 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7981 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7982 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7985 return pctype_table[flow_type];
7989 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7991 static const uint16_t flowtype_table[] = {
7992 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7993 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7994 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7995 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7996 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7997 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7998 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7999 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8000 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8001 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8002 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8003 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8004 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8005 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8006 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8007 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8008 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8009 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8010 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8013 return flowtype_table[pctype];
8017 * On X710, performance number is far from the expectation on recent firmware
8018 * versions; on XL710, performance number is also far from the expectation on
8019 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8020 * mode is enabled and port MAC address is equal to the packet destination MAC
8021 * address. The fix for this issue may not be integrated in the following
8022 * firmware version. So the workaround in software driver is needed. It needs
8023 * to modify the initial values of 3 internal only registers for both X710 and
8024 * XL710. Note that the values for X710 or XL710 could be different, and the
8025 * workaround can be removed when it is fixed in firmware in the future.
8028 /* For both X710 and XL710 */
8029 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8030 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
8032 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8033 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
8036 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
8038 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
8039 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
8042 i40e_configure_registers(struct i40e_hw *hw)
8048 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8049 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8050 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8056 for (i = 0; i < RTE_DIM(reg_table); i++) {
8057 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8058 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
8060 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8063 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8066 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8069 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8073 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8074 reg_table[i].addr, reg);
8075 if (reg == reg_table[i].val)
8078 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8079 reg_table[i].val, NULL);
8081 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8082 "address of 0x%"PRIx32, reg_table[i].val,
8086 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8087 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8091 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
8092 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
8093 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
8094 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8096 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8101 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8102 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8106 /* Configure for double VLAN RX stripping */
8107 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8108 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8109 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8110 ret = i40e_aq_debug_write_register(hw,
8111 I40E_VSI_TSR(vsi->vsi_id),
8114 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8116 return I40E_ERR_CONFIG;
8120 /* Configure for double VLAN TX insertion */
8121 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8122 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8123 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8124 ret = i40e_aq_debug_write_register(hw,
8125 I40E_VSI_L2TAGSTXVALID(
8126 vsi->vsi_id), reg, NULL);
8128 PMD_DRV_LOG(ERR, "Failed to update "
8129 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8130 return I40E_ERR_CONFIG;
8138 * i40e_aq_add_mirror_rule
8139 * @hw: pointer to the hardware structure
8140 * @seid: VEB seid to add mirror rule to
8141 * @dst_id: destination vsi seid
8142 * @entries: Buffer which contains the entities to be mirrored
8143 * @count: number of entities contained in the buffer
8144 * @rule_id:the rule_id of the rule to be added
8146 * Add a mirror rule for a given veb.
8149 static enum i40e_status_code
8150 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8151 uint16_t seid, uint16_t dst_id,
8152 uint16_t rule_type, uint16_t *entries,
8153 uint16_t count, uint16_t *rule_id)
8155 struct i40e_aq_desc desc;
8156 struct i40e_aqc_add_delete_mirror_rule cmd;
8157 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8158 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8161 enum i40e_status_code status;
8163 i40e_fill_default_direct_cmd_desc(&desc,
8164 i40e_aqc_opc_add_mirror_rule);
8165 memset(&cmd, 0, sizeof(cmd));
8167 buff_len = sizeof(uint16_t) * count;
8168 desc.datalen = rte_cpu_to_le_16(buff_len);
8170 desc.flags |= rte_cpu_to_le_16(
8171 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8172 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8173 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8174 cmd.num_entries = rte_cpu_to_le_16(count);
8175 cmd.seid = rte_cpu_to_le_16(seid);
8176 cmd.destination = rte_cpu_to_le_16(dst_id);
8178 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8179 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8180 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8182 " mirror_rules_used = %u, mirror_rules_free = %u,",
8183 hw->aq.asq_last_status, resp->rule_id,
8184 resp->mirror_rules_used, resp->mirror_rules_free);
8185 *rule_id = rte_le_to_cpu_16(resp->rule_id);
8191 * i40e_aq_del_mirror_rule
8192 * @hw: pointer to the hardware structure
8193 * @seid: VEB seid to add mirror rule to
8194 * @entries: Buffer which contains the entities to be mirrored
8195 * @count: number of entities contained in the buffer
8196 * @rule_id:the rule_id of the rule to be delete
8198 * Delete a mirror rule for a given veb.
8201 static enum i40e_status_code
8202 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8203 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8204 uint16_t count, uint16_t rule_id)
8206 struct i40e_aq_desc desc;
8207 struct i40e_aqc_add_delete_mirror_rule cmd;
8208 uint16_t buff_len = 0;
8209 enum i40e_status_code status;
8212 i40e_fill_default_direct_cmd_desc(&desc,
8213 i40e_aqc_opc_delete_mirror_rule);
8214 memset(&cmd, 0, sizeof(cmd));
8215 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8216 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8218 cmd.num_entries = count;
8219 buff_len = sizeof(uint16_t) * count;
8220 desc.datalen = rte_cpu_to_le_16(buff_len);
8221 buff = (void *)entries;
8223 /* rule id is filled in destination field for deleting mirror rule */
8224 cmd.destination = rte_cpu_to_le_16(rule_id);
8226 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8227 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8228 cmd.seid = rte_cpu_to_le_16(seid);
8230 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8231 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8237 * i40e_mirror_rule_set
8238 * @dev: pointer to the hardware structure
8239 * @mirror_conf: mirror rule info
8240 * @sw_id: mirror rule's sw_id
8241 * @on: enable/disable
8243 * set a mirror rule.
8247 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8248 struct rte_eth_mirror_conf *mirror_conf,
8249 uint8_t sw_id, uint8_t on)
8251 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8252 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8253 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8254 struct i40e_mirror_rule *parent = NULL;
8255 uint16_t seid, dst_seid, rule_id;
8259 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8261 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8262 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8263 " without veb or vfs.");
8266 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8267 PMD_DRV_LOG(ERR, "mirror table is full.");
8270 if (mirror_conf->dst_pool > pf->vf_num) {
8271 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8272 mirror_conf->dst_pool);
8276 seid = pf->main_vsi->veb->seid;
8278 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8279 if (sw_id <= it->index) {
8285 if (mirr_rule && sw_id == mirr_rule->index) {
8287 PMD_DRV_LOG(ERR, "mirror rule exists.");
8290 ret = i40e_aq_del_mirror_rule(hw, seid,
8291 mirr_rule->rule_type,
8293 mirr_rule->num_entries, mirr_rule->id);
8295 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8296 " ret = %d, aq_err = %d.",
8297 ret, hw->aq.asq_last_status);
8300 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8301 rte_free(mirr_rule);
8302 pf->nb_mirror_rule--;
8306 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8310 mirr_rule = rte_zmalloc("i40e_mirror_rule",
8311 sizeof(struct i40e_mirror_rule) , 0);
8313 PMD_DRV_LOG(ERR, "failed to allocate memory");
8314 return I40E_ERR_NO_MEMORY;
8316 switch (mirror_conf->rule_type) {
8317 case ETH_MIRROR_VLAN:
8318 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8319 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8320 mirr_rule->entries[j] =
8321 mirror_conf->vlan.vlan_id[i];
8326 PMD_DRV_LOG(ERR, "vlan is not specified.");
8327 rte_free(mirr_rule);
8330 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8332 case ETH_MIRROR_VIRTUAL_POOL_UP:
8333 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8334 /* check if the specified pool bit is out of range */
8335 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8336 PMD_DRV_LOG(ERR, "pool mask is out of range.");
8337 rte_free(mirr_rule);
8340 for (i = 0, j = 0; i < pf->vf_num; i++) {
8341 if (mirror_conf->pool_mask & (1ULL << i)) {
8342 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8346 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8347 /* add pf vsi to entries */
8348 mirr_rule->entries[j] = pf->main_vsi_seid;
8352 PMD_DRV_LOG(ERR, "pool is not specified.");
8353 rte_free(mirr_rule);
8356 /* egress and ingress in aq commands means from switch but not port */
8357 mirr_rule->rule_type =
8358 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8359 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8360 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8362 case ETH_MIRROR_UPLINK_PORT:
8363 /* egress and ingress in aq commands means from switch but not port*/
8364 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8366 case ETH_MIRROR_DOWNLINK_PORT:
8367 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8370 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8371 mirror_conf->rule_type);
8372 rte_free(mirr_rule);
8376 /* If the dst_pool is equal to vf_num, consider it as PF */
8377 if (mirror_conf->dst_pool == pf->vf_num)
8378 dst_seid = pf->main_vsi_seid;
8380 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8382 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8383 mirr_rule->rule_type, mirr_rule->entries,
8386 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8387 " ret = %d, aq_err = %d.",
8388 ret, hw->aq.asq_last_status);
8389 rte_free(mirr_rule);
8393 mirr_rule->index = sw_id;
8394 mirr_rule->num_entries = j;
8395 mirr_rule->id = rule_id;
8396 mirr_rule->dst_vsi_seid = dst_seid;
8399 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8401 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8403 pf->nb_mirror_rule++;
8408 * i40e_mirror_rule_reset
8409 * @dev: pointer to the device
8410 * @sw_id: mirror rule's sw_id
8412 * reset a mirror rule.
8416 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8418 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8419 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8420 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8424 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8426 seid = pf->main_vsi->veb->seid;
8428 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8429 if (sw_id == it->index) {
8435 ret = i40e_aq_del_mirror_rule(hw, seid,
8436 mirr_rule->rule_type,
8438 mirr_rule->num_entries, mirr_rule->id);
8440 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8441 " status = %d, aq_err = %d.",
8442 ret, hw->aq.asq_last_status);
8445 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8446 rte_free(mirr_rule);
8447 pf->nb_mirror_rule--;
8449 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8456 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8458 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8459 uint64_t systim_cycles;
8461 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8462 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8465 return systim_cycles;
8469 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8471 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8474 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8475 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8482 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8484 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8487 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8488 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8495 i40e_start_timecounters(struct rte_eth_dev *dev)
8497 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8498 struct i40e_adapter *adapter =
8499 (struct i40e_adapter *)dev->data->dev_private;
8500 struct rte_eth_link link;
8501 uint32_t tsync_inc_l;
8502 uint32_t tsync_inc_h;
8504 /* Get current link speed. */
8505 memset(&link, 0, sizeof(link));
8506 i40e_dev_link_update(dev, 1);
8507 rte_i40e_dev_atomic_read_link_status(dev, &link);
8509 switch (link.link_speed) {
8510 case ETH_SPEED_NUM_40G:
8511 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8512 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8514 case ETH_SPEED_NUM_10G:
8515 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8516 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8518 case ETH_SPEED_NUM_1G:
8519 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8520 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8527 /* Set the timesync increment value. */
8528 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8529 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8531 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8532 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8533 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8535 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8536 adapter->systime_tc.cc_shift = 0;
8537 adapter->systime_tc.nsec_mask = 0;
8539 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8540 adapter->rx_tstamp_tc.cc_shift = 0;
8541 adapter->rx_tstamp_tc.nsec_mask = 0;
8543 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8544 adapter->tx_tstamp_tc.cc_shift = 0;
8545 adapter->tx_tstamp_tc.nsec_mask = 0;
8549 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8551 struct i40e_adapter *adapter =
8552 (struct i40e_adapter *)dev->data->dev_private;
8554 adapter->systime_tc.nsec += delta;
8555 adapter->rx_tstamp_tc.nsec += delta;
8556 adapter->tx_tstamp_tc.nsec += delta;
8562 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8565 struct i40e_adapter *adapter =
8566 (struct i40e_adapter *)dev->data->dev_private;
8568 ns = rte_timespec_to_ns(ts);
8570 /* Set the timecounters to a new value. */
8571 adapter->systime_tc.nsec = ns;
8572 adapter->rx_tstamp_tc.nsec = ns;
8573 adapter->tx_tstamp_tc.nsec = ns;
8579 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8581 uint64_t ns, systime_cycles;
8582 struct i40e_adapter *adapter =
8583 (struct i40e_adapter *)dev->data->dev_private;
8585 systime_cycles = i40e_read_systime_cyclecounter(dev);
8586 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8587 *ts = rte_ns_to_timespec(ns);
8593 i40e_timesync_enable(struct rte_eth_dev *dev)
8595 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8596 uint32_t tsync_ctl_l;
8597 uint32_t tsync_ctl_h;
8599 /* Stop the timesync system time. */
8600 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8601 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8602 /* Reset the timesync system time value. */
8603 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8604 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8606 i40e_start_timecounters(dev);
8608 /* Clear timesync registers. */
8609 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8610 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8611 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8612 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8613 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8614 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8616 /* Enable timestamping of PTP packets. */
8617 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8618 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8620 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8621 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8622 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8624 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8625 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8631 i40e_timesync_disable(struct rte_eth_dev *dev)
8633 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8634 uint32_t tsync_ctl_l;
8635 uint32_t tsync_ctl_h;
8637 /* Disable timestamping of transmitted PTP packets. */
8638 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8639 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8641 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8642 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8644 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8645 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8647 /* Reset the timesync increment value. */
8648 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8649 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8655 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8656 struct timespec *timestamp, uint32_t flags)
8658 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8659 struct i40e_adapter *adapter =
8660 (struct i40e_adapter *)dev->data->dev_private;
8662 uint32_t sync_status;
8663 uint32_t index = flags & 0x03;
8664 uint64_t rx_tstamp_cycles;
8667 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8668 if ((sync_status & (1 << index)) == 0)
8671 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8672 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8673 *timestamp = rte_ns_to_timespec(ns);
8679 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8680 struct timespec *timestamp)
8682 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8683 struct i40e_adapter *adapter =
8684 (struct i40e_adapter *)dev->data->dev_private;
8686 uint32_t sync_status;
8687 uint64_t tx_tstamp_cycles;
8690 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8691 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8694 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8695 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8696 *timestamp = rte_ns_to_timespec(ns);
8702 * i40e_parse_dcb_configure - parse dcb configure from user
8703 * @dev: the device being configured
8704 * @dcb_cfg: pointer of the result of parse
8705 * @*tc_map: bit map of enabled traffic classes
8707 * Returns 0 on success, negative value on failure
8710 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8711 struct i40e_dcbx_config *dcb_cfg,
8714 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8715 uint8_t i, tc_bw, bw_lf;
8717 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8719 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8720 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8721 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8725 /* assume each tc has the same bw */
8726 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8727 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8728 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8729 /* to ensure the sum of tcbw is equal to 100 */
8730 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8731 for (i = 0; i < bw_lf; i++)
8732 dcb_cfg->etscfg.tcbwtable[i]++;
8734 /* assume each tc has the same Transmission Selection Algorithm */
8735 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8736 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8738 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8739 dcb_cfg->etscfg.prioritytable[i] =
8740 dcb_rx_conf->dcb_tc[i];
8742 /* FW needs one App to configure HW */
8743 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8744 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8745 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8746 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8748 if (dcb_rx_conf->nb_tcs == 0)
8749 *tc_map = 1; /* tc0 only */
8751 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8753 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8754 dcb_cfg->pfc.willing = 0;
8755 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8756 dcb_cfg->pfc.pfcenable = *tc_map;
8762 static enum i40e_status_code
8763 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8764 struct i40e_aqc_vsi_properties_data *info,
8765 uint8_t enabled_tcmap)
8767 enum i40e_status_code ret;
8768 int i, total_tc = 0;
8769 uint16_t qpnum_per_tc, bsf, qp_idx;
8770 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8771 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8772 uint16_t used_queues;
8774 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8775 if (ret != I40E_SUCCESS)
8778 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8779 if (enabled_tcmap & (1 << i))
8784 vsi->enabled_tc = enabled_tcmap;
8786 /* different VSI has different queues assigned */
8787 if (vsi->type == I40E_VSI_MAIN)
8788 used_queues = dev_data->nb_rx_queues -
8789 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8790 else if (vsi->type == I40E_VSI_VMDQ2)
8791 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8793 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8794 return I40E_ERR_NO_AVAILABLE_VSI;
8797 qpnum_per_tc = used_queues / total_tc;
8798 /* Number of queues per enabled TC */
8799 if (qpnum_per_tc == 0) {
8800 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8801 return I40E_ERR_INVALID_QP_ID;
8803 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8805 bsf = rte_bsf32(qpnum_per_tc);
8808 * Configure TC and queue mapping parameters, for enabled TC,
8809 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8810 * default queue will serve it.
8813 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8814 if (vsi->enabled_tc & (1 << i)) {
8815 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8816 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8817 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8818 qp_idx += qpnum_per_tc;
8820 info->tc_mapping[i] = 0;
8823 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8824 if (vsi->type == I40E_VSI_SRIOV) {
8825 info->mapping_flags |=
8826 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8827 for (i = 0; i < vsi->nb_qps; i++)
8828 info->queue_mapping[i] =
8829 rte_cpu_to_le_16(vsi->base_queue + i);
8831 info->mapping_flags |=
8832 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8833 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8835 info->valid_sections |=
8836 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8838 return I40E_SUCCESS;
8842 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8843 * @veb: VEB to be configured
8844 * @tc_map: enabled TC bitmap
8846 * Returns 0 on success, negative value on failure
8848 static enum i40e_status_code
8849 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8851 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8852 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8853 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8854 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8855 enum i40e_status_code ret = I40E_SUCCESS;
8859 /* Check if enabled_tc is same as existing or new TCs */
8860 if (veb->enabled_tc == tc_map)
8863 /* configure tc bandwidth */
8864 memset(&veb_bw, 0, sizeof(veb_bw));
8865 veb_bw.tc_valid_bits = tc_map;
8866 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8867 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8868 if (tc_map & BIT_ULL(i))
8869 veb_bw.tc_bw_share_credits[i] = 1;
8871 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8874 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8875 " per TC failed = %d",
8876 hw->aq.asq_last_status);
8880 memset(&ets_query, 0, sizeof(ets_query));
8881 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8883 if (ret != I40E_SUCCESS) {
8884 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8885 " configuration %u", hw->aq.asq_last_status);
8888 memset(&bw_query, 0, sizeof(bw_query));
8889 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8891 if (ret != I40E_SUCCESS) {
8892 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8893 " configuration %u", hw->aq.asq_last_status);
8897 /* store and print out BW info */
8898 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8899 veb->bw_info.bw_max = ets_query.tc_bw_max;
8900 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8901 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8902 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8903 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8905 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8906 veb->bw_info.bw_ets_share_credits[i] =
8907 bw_query.tc_bw_share_credits[i];
8908 veb->bw_info.bw_ets_credits[i] =
8909 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8910 /* 4 bits per TC, 4th bit is reserved */
8911 veb->bw_info.bw_ets_max[i] =
8912 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8913 RTE_LEN2MASK(3, uint8_t));
8914 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8915 veb->bw_info.bw_ets_share_credits[i]);
8916 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8917 veb->bw_info.bw_ets_credits[i]);
8918 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8919 veb->bw_info.bw_ets_max[i]);
8922 veb->enabled_tc = tc_map;
8929 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8930 * @vsi: VSI to be configured
8931 * @tc_map: enabled TC bitmap
8933 * Returns 0 on success, negative value on failure
8935 static enum i40e_status_code
8936 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8938 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8939 struct i40e_vsi_context ctxt;
8940 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8941 enum i40e_status_code ret = I40E_SUCCESS;
8944 /* Check if enabled_tc is same as existing or new TCs */
8945 if (vsi->enabled_tc == tc_map)
8948 /* configure tc bandwidth */
8949 memset(&bw_data, 0, sizeof(bw_data));
8950 bw_data.tc_valid_bits = tc_map;
8951 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8952 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8953 if (tc_map & BIT_ULL(i))
8954 bw_data.tc_bw_credits[i] = 1;
8956 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8958 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8959 " per TC failed = %d",
8960 hw->aq.asq_last_status);
8963 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8964 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8966 /* Update Queue Pairs Mapping for currently enabled UPs */
8967 ctxt.seid = vsi->seid;
8968 ctxt.pf_num = hw->pf_id;
8970 ctxt.uplink_seid = vsi->uplink_seid;
8971 ctxt.info = vsi->info;
8973 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8977 /* Update the VSI after updating the VSI queue-mapping information */
8978 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8980 PMD_INIT_LOG(ERR, "Failed to configure "
8981 "TC queue mapping = %d",
8982 hw->aq.asq_last_status);
8985 /* update the local VSI info with updated queue map */
8986 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8987 sizeof(vsi->info.tc_mapping));
8988 (void)rte_memcpy(&vsi->info.queue_mapping,
8989 &ctxt.info.queue_mapping,
8990 sizeof(vsi->info.queue_mapping));
8991 vsi->info.mapping_flags = ctxt.info.mapping_flags;
8992 vsi->info.valid_sections = 0;
8994 /* query and update current VSI BW information */
8995 ret = i40e_vsi_get_bw_config(vsi);
8998 "Failed updating vsi bw info, err %s aq_err %s",
8999 i40e_stat_str(hw, ret),
9000 i40e_aq_str(hw, hw->aq.asq_last_status));
9004 vsi->enabled_tc = tc_map;
9011 * i40e_dcb_hw_configure - program the dcb setting to hw
9012 * @pf: pf the configuration is taken on
9013 * @new_cfg: new configuration
9014 * @tc_map: enabled TC bitmap
9016 * Returns 0 on success, negative value on failure
9018 static enum i40e_status_code
9019 i40e_dcb_hw_configure(struct i40e_pf *pf,
9020 struct i40e_dcbx_config *new_cfg,
9023 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9024 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9025 struct i40e_vsi *main_vsi = pf->main_vsi;
9026 struct i40e_vsi_list *vsi_list;
9027 enum i40e_status_code ret;
9031 /* Use the FW API if FW > v4.4*/
9032 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9033 (hw->aq.fw_maj_ver >= 5))) {
9034 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9035 " to configure DCB");
9036 return I40E_ERR_FIRMWARE_API_VERSION;
9039 /* Check if need reconfiguration */
9040 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9041 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9042 return I40E_SUCCESS;
9045 /* Copy the new config to the current config */
9046 *old_cfg = *new_cfg;
9047 old_cfg->etsrec = old_cfg->etscfg;
9048 ret = i40e_set_dcb_config(hw);
9051 "Set DCB Config failed, err %s aq_err %s\n",
9052 i40e_stat_str(hw, ret),
9053 i40e_aq_str(hw, hw->aq.asq_last_status));
9056 /* set receive Arbiter to RR mode and ETS scheme by default */
9057 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9058 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9059 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
9060 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9061 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9062 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9063 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9064 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9065 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9066 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9067 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9068 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9069 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9071 /* get local mib to check whether it is configured correctly */
9073 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9074 /* Get Local DCB Config */
9075 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9076 &hw->local_dcbx_config);
9078 /* if Veb is created, need to update TC of it at first */
9079 if (main_vsi->veb) {
9080 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9082 PMD_INIT_LOG(WARNING,
9083 "Failed configuring TC for VEB seid=%d\n",
9084 main_vsi->veb->seid);
9086 /* Update each VSI */
9087 i40e_vsi_config_tc(main_vsi, tc_map);
9088 if (main_vsi->veb) {
9089 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9090 /* Beside main VSI and VMDQ VSIs, only enable default
9093 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9094 ret = i40e_vsi_config_tc(vsi_list->vsi,
9097 ret = i40e_vsi_config_tc(vsi_list->vsi,
9098 I40E_DEFAULT_TCMAP);
9100 PMD_INIT_LOG(WARNING,
9101 "Failed configuring TC for VSI seid=%d\n",
9102 vsi_list->vsi->seid);
9106 return I40E_SUCCESS;
9110 * i40e_dcb_init_configure - initial dcb config
9111 * @dev: device being configured
9112 * @sw_dcb: indicate whether dcb is sw configured or hw offload
9114 * Returns 0 on success, negative value on failure
9117 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9119 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9120 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9123 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9124 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9128 /* DCB initialization:
9129 * Update DCB configuration from the Firmware and configure
9130 * LLDP MIB change event.
9132 if (sw_dcb == TRUE) {
9133 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
9134 if (ret != I40E_SUCCESS)
9135 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
9137 ret = i40e_init_dcb(hw);
9138 /* if sw_dcb, lldp agent is stopped, the return from
9139 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9142 if (ret != I40E_SUCCESS &&
9143 hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
9144 memset(&hw->local_dcbx_config, 0,
9145 sizeof(struct i40e_dcbx_config));
9146 /* set dcb default configuration */
9147 hw->local_dcbx_config.etscfg.willing = 0;
9148 hw->local_dcbx_config.etscfg.maxtcs = 0;
9149 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9150 hw->local_dcbx_config.etscfg.tsatable[0] =
9152 hw->local_dcbx_config.etsrec =
9153 hw->local_dcbx_config.etscfg;
9154 hw->local_dcbx_config.pfc.willing = 0;
9155 hw->local_dcbx_config.pfc.pfccap =
9156 I40E_MAX_TRAFFIC_CLASS;
9157 /* FW needs one App to configure HW */
9158 hw->local_dcbx_config.numapps = 1;
9159 hw->local_dcbx_config.app[0].selector =
9160 I40E_APP_SEL_ETHTYPE;
9161 hw->local_dcbx_config.app[0].priority = 3;
9162 hw->local_dcbx_config.app[0].protocolid =
9163 I40E_APP_PROTOID_FCOE;
9164 ret = i40e_set_dcb_config(hw);
9166 PMD_INIT_LOG(ERR, "default dcb config fails."
9167 " err = %d, aq_err = %d.", ret,
9168 hw->aq.asq_last_status);
9172 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9173 " aq_err = %d.", ret,
9174 hw->aq.asq_last_status);
9178 ret = i40e_aq_start_lldp(hw, NULL);
9179 if (ret != I40E_SUCCESS)
9180 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9182 ret = i40e_init_dcb(hw);
9184 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9185 PMD_INIT_LOG(ERR, "HW doesn't support"
9190 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9191 " aq_err = %d.", ret,
9192 hw->aq.asq_last_status);
9200 * i40e_dcb_setup - setup dcb related config
9201 * @dev: device being configured
9203 * Returns 0 on success, negative value on failure
9206 i40e_dcb_setup(struct rte_eth_dev *dev)
9208 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9209 struct i40e_dcbx_config dcb_cfg;
9213 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9214 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9218 if (pf->vf_num != 0)
9219 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9221 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9223 PMD_INIT_LOG(ERR, "invalid dcb config");
9226 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9228 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9236 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9237 struct rte_eth_dcb_info *dcb_info)
9239 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9240 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9241 struct i40e_vsi *vsi = pf->main_vsi;
9242 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9243 uint16_t bsf, tc_mapping;
9246 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9247 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9249 dcb_info->nb_tcs = 1;
9250 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9251 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9252 for (i = 0; i < dcb_info->nb_tcs; i++)
9253 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9255 /* get queue mapping if vmdq is disabled */
9256 if (!pf->nb_cfg_vmdq_vsi) {
9257 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9258 if (!(vsi->enabled_tc & (1 << i)))
9260 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9261 dcb_info->tc_queue.tc_rxq[j][i].base =
9262 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9263 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9264 dcb_info->tc_queue.tc_txq[j][i].base =
9265 dcb_info->tc_queue.tc_rxq[j][i].base;
9266 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9267 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9268 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9269 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9270 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9275 /* get queue mapping if vmdq is enabled */
9277 vsi = pf->vmdq[j].vsi;
9278 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9279 if (!(vsi->enabled_tc & (1 << i)))
9281 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9282 dcb_info->tc_queue.tc_rxq[j][i].base =
9283 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9284 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9285 dcb_info->tc_queue.tc_txq[j][i].base =
9286 dcb_info->tc_queue.tc_rxq[j][i].base;
9287 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9288 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9289 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9290 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9291 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9294 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9299 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9301 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9302 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9304 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9307 msix_intr = intr_handle->intr_vec[queue_id];
9308 if (msix_intr == I40E_MISC_VEC_ID)
9309 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9310 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9311 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9312 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9314 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9317 I40E_PFINT_DYN_CTLN(msix_intr -
9319 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9320 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9321 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9323 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9325 I40E_WRITE_FLUSH(hw);
9326 rte_intr_enable(&dev->pci_dev->intr_handle);
9332 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9334 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9335 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9338 msix_intr = intr_handle->intr_vec[queue_id];
9339 if (msix_intr == I40E_MISC_VEC_ID)
9340 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9343 I40E_PFINT_DYN_CTLN(msix_intr -
9346 I40E_WRITE_FLUSH(hw);
9351 static int i40e_get_regs(struct rte_eth_dev *dev,
9352 struct rte_dev_reg_info *regs)
9354 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9355 uint32_t *ptr_data = regs->data;
9356 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9357 const struct i40e_reg_info *reg_info;
9359 if (ptr_data == NULL) {
9360 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9361 regs->width = sizeof(uint32_t);
9365 /* The first few registers have to be read using AQ operations */
9367 while (i40e_regs_adminq[reg_idx].name) {
9368 reg_info = &i40e_regs_adminq[reg_idx++];
9369 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9371 arr_idx2 <= reg_info->count2;
9373 reg_offset = arr_idx * reg_info->stride1 +
9374 arr_idx2 * reg_info->stride2;
9375 reg_offset += reg_info->base_addr;
9376 ptr_data[reg_offset >> 2] =
9377 i40e_read_rx_ctl(hw, reg_offset);
9381 /* The remaining registers can be read using primitives */
9383 while (i40e_regs_others[reg_idx].name) {
9384 reg_info = &i40e_regs_others[reg_idx++];
9385 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9387 arr_idx2 <= reg_info->count2;
9389 reg_offset = arr_idx * reg_info->stride1 +
9390 arr_idx2 * reg_info->stride2;
9391 reg_offset += reg_info->base_addr;
9392 ptr_data[reg_offset >> 2] =
9393 I40E_READ_REG(hw, reg_offset);
9400 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9402 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9404 /* Convert word count to byte count */
9405 return hw->nvm.sr_size << 1;
9408 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9409 struct rte_dev_eeprom_info *eeprom)
9411 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9412 uint16_t *data = eeprom->data;
9413 uint16_t offset, length, cnt_words;
9416 offset = eeprom->offset >> 1;
9417 length = eeprom->length >> 1;
9420 if (offset > hw->nvm.sr_size ||
9421 offset + length > hw->nvm.sr_size) {
9422 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9426 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9428 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9429 if (ret_code != I40E_SUCCESS || cnt_words != length) {
9430 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9437 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9438 struct ether_addr *mac_addr)
9440 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9442 if (!is_valid_assigned_ether_addr(mac_addr)) {
9443 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9447 /* Flags: 0x3 updates port address */
9448 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9452 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9454 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9455 struct rte_eth_dev_data *dev_data = pf->dev_data;
9456 uint32_t frame_size = mtu + ETHER_HDR_LEN
9457 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9460 /* check if mtu is within the allowed range */
9461 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9464 /* mtu setting is forbidden if port is start */
9465 if (dev_data->dev_started) {
9467 "port %d must be stopped before configuration\n",
9472 if (frame_size > ETHER_MAX_LEN)
9473 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9475 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9477 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;