drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54 #include <rte_hash_crc.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_adminq_cmd.h"
  59 #include "base/i40e_type.h"
  60 #include "base/i40e_register.h"
  61 #include "base/i40e_dcb.h"
  62 #include "i40e_ethdev.h"
  63 #include "i40e_rxtx.h"
  64 #include "i40e_pf.h"
  65 #include "i40e_regs.h"
  66
  67 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  68 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  69
  70 #define I40E_CLEAR_PXE_WAIT_MS     200
  71
  72 /* Maximun number of capability elements */
  73 #define I40E_MAX_CAP_ELE_NUM       128
  74
  75 /* Wait count and inteval */
  76 #define I40E_CHK_Q_ENA_COUNT       1000
  77 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  78
  79 /* Maximun number of VSI */
  80 #define I40E_MAX_NUM_VSIS          (384UL)
  81
  82 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  83
  84 /* Flow control default timer */
  85 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  86
  87 /* Flow control default high water */
  88 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  89
  90 /* Flow control default low water */
  91 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  92
  93 /* Flow control enable fwd bit */
  94 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  95
  96 /* Receive Packet Buffer size */
  97 #define I40E_RXPBSIZE (968 * 1024)
  98
  99 /* Kilobytes shift */
 100 #define I40E_KILOSHIFT 10
 101
 102 /* Receive Average Packet Size in Byte*/
 103 #define I40E_PACKET_AVERAGE_SIZE 128
 104
 105 /* Mask of PF interrupt causes */
 106 #define I40E_PFINT_ICR0_ENA_MASK ( \
 107                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 108                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 110                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 111                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 112                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 116
 117 #define I40E_FLOW_TYPES ( \
 118         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 123         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 128         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 129
 130 /* Additional timesync values. */
 131 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA     0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 136 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 /**
 143  * Below are values for writing un-exposed registers suggested
 144  * by silicon experts
 145  */
 146 /* Destination MAC address */
 147 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 148 /* Source MAC address */
 149 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 150 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 151 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 152 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 154 /* Single VLAN tag in the inner L2 header */
 155 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 156 /* Source IPv4 address */
 157 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 158 /* Destination IPv4 address */
 159 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 160 /* Source IPv4 address for X722 */
 161 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 162 /* Destination IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 164 /* IPv4 Protocol for X722 */
 165 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 166 /* IPv4 Time to Live for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 168 /* IPv4 Type of Service (TOS) */
 169 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 170 /* IPv4 Protocol */
 171 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 172 /* IPv4 Time to Live */
 173 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 174 /* Source IPv6 address */
 175 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 176 /* Destination IPv6 address */
 177 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 178 /* IPv6 Traffic Class (TC) */
 179 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 180 /* IPv6 Next Header */
 181 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 182 /* IPv6 Hop Limit */
 183 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 184 /* Source L4 port */
 185 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 186 /* Destination L4 port */
 187 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 188 /* SCTP verification tag */
 189 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 190 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 191 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 192 /* Source port of tunneling UDP */
 193 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 194 /* Destination port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 196 /* UDP Tunneling ID, NVGRE/GRE key */
 197 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 198 /* Last ether type */
 199 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 200 /* Tunneling outer destination IPv4 address */
 201 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 202 /* Tunneling outer destination IPv6 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 204 /* 1st word of flex payload */
 205 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 206 /* 2nd word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 208 /* 3rd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 210 /* 4th word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 212 /* 5th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 214 /* 6th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 216 /* 7th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 218 /* 8th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 220 /* all 8 words flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 222 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 223
 224 #define I40E_TRANSLATE_INSET 0
 225 #define I40E_TRANSLATE_REG   1
 226
 227 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 228 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 229 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 230 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 231 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 232 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 233
 234 /* PCI offset for querying capability */
 235 #define PCI_DEV_CAP_REG            0xA4
 236 /* PCI offset for enabling/disabling Extended Tag */
 237 #define PCI_DEV_CTRL_REG           0xA8
 238 /* Bit mask of Extended Tag capability */
 239 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 240 /* Bit shift of Extended Tag enable/disable */
 241 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 242 /* Bit mask of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 244
 245 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 246 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 247 static int i40e_dev_configure(struct rte_eth_dev *dev);
 248 static int i40e_dev_start(struct rte_eth_dev *dev);
 249 static void i40e_dev_stop(struct rte_eth_dev *dev);
 250 static void i40e_dev_close(struct rte_eth_dev *dev);
 251 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 252 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 253 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 254 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 255 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 256 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 257 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 258                                struct rte_eth_stats *stats);
 259 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 260                                struct rte_eth_xstat *xstats, unsigned n);
 261 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 262                                      struct rte_eth_xstat_name *xstats_names,
 263                                      unsigned limit);
 264 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 265 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 266                                             uint16_t queue_id,
 267                                             uint8_t stat_idx,
 268                                             uint8_t is_rx);
 269 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 270                                 char *fw_version, size_t fw_size);
 271 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 272                               struct rte_eth_dev_info *dev_info);
 273 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 274                                 uint16_t vlan_id,
 275                                 int on);
 276 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 277                               enum rte_vlan_type vlan_type,
 278                               uint16_t tpid);
 279 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 280 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 281                                       uint16_t queue,
 282                                       int on);
 283 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 284 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 285 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 286 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 287                               struct rte_eth_fc_conf *fc_conf);
 288 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 289                               struct rte_eth_fc_conf *fc_conf);
 290 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 291                                        struct rte_eth_pfc_conf *pfc_conf);
 292 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 293                           struct ether_addr *mac_addr,
 294                           uint32_t index,
 295                           uint32_t pool);
 296 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 297 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 298                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 299                                     uint16_t reta_size);
 300 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 301                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 302                                    uint16_t reta_size);
 303
 304 static int i40e_get_cap(struct i40e_hw *hw);
 305 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 306 static int i40e_pf_setup(struct i40e_pf *pf);
 307 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 308 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 309 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 310 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 311 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 312                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 313 static void i40e_stat_update_48(struct i40e_hw *hw,
 314                                uint32_t hireg,
 315                                uint32_t loreg,
 316                                bool offset_loaded,
 317                                uint64_t *offset,
 318                                uint64_t *stat);
 319 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 320 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 321                                        void *param);
 322 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 323                                 uint32_t base, uint32_t num);
 324 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 325 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 326                         uint32_t base);
 327 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 328                         uint16_t num);
 329 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 330 static int i40e_veb_release(struct i40e_veb *veb);
 331 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 332                                                 struct i40e_vsi *vsi);
 333 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 334 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 335 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 336                                              struct i40e_macvlan_filter *mv_f,
 337                                              int num,
 338                                              struct ether_addr *addr);
 339 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 340                                              struct i40e_macvlan_filter *mv_f,
 341                                              int num,
 342                                              uint16_t vlan);
 343 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 344 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 345                                     struct rte_eth_rss_conf *rss_conf);
 346 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 347                                       struct rte_eth_rss_conf *rss_conf);
 348 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 349                                         struct rte_eth_udp_tunnel *udp_tunnel);
 350 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 351                                         struct rte_eth_udp_tunnel *udp_tunnel);
 352 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 353 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 354                                 enum rte_filter_op filter_op,
 355                                 void *arg);
 356 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 357                                 enum rte_filter_type filter_type,
 358                                 enum rte_filter_op filter_op,
 359                                 void *arg);
 360 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 361                                   struct rte_eth_dcb_info *dcb_info);
 362 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 363 static void i40e_configure_registers(struct i40e_hw *hw);
 364 static void i40e_hw_init(struct rte_eth_dev *dev);
 365 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 366 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 367                         struct rte_eth_mirror_conf *mirror_conf,
 368                         uint8_t sw_id, uint8_t on);
 369 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 370
 371 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 372 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 373 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 374                                            struct timespec *timestamp,
 375                                            uint32_t flags);
 376 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 377                                            struct timespec *timestamp);
 378 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 379
 380 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 381
 382 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 383                                    struct timespec *timestamp);
 384 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 385                                     const struct timespec *timestamp);
 386
 387 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 388                                          uint16_t queue_id);
 389 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 390                                           uint16_t queue_id);
 391
 392 static int i40e_get_regs(struct rte_eth_dev *dev,
 393                          struct rte_dev_reg_info *regs);
 394
 395 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 396
 397 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 398                            struct rte_dev_eeprom_info *eeprom);
 399
 400 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 401                                       struct ether_addr *mac_addr);
 402
 403 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 404
 405 static int i40e_ethertype_filter_convert(
 406         const struct rte_eth_ethertype_filter *input,
 407         struct i40e_ethertype_filter *filter);
 408 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 409                                    struct i40e_ethertype_filter *filter);
 410
 411 static int i40e_tunnel_filter_convert(
 412         struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter,
 413         struct i40e_tunnel_filter *tunnel_filter);
 414 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 415                                 struct i40e_tunnel_filter *tunnel_filter);
 416
 417 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 418 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 419 static void i40e_filter_restore(struct i40e_pf *pf);
 420
 421 static const struct rte_pci_id pci_id_i40e_map[] = {
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 442         { .vendor_id = 0, /* sentinel */ },
 443 };
 444
 445 static const struct eth_dev_ops i40e_eth_dev_ops = {
 446         .dev_configure                = i40e_dev_configure,
 447         .dev_start                    = i40e_dev_start,
 448         .dev_stop                     = i40e_dev_stop,
 449         .dev_close                    = i40e_dev_close,
 450         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 451         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 452         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 453         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 454         .dev_set_link_up              = i40e_dev_set_link_up,
 455         .dev_set_link_down            = i40e_dev_set_link_down,
 456         .link_update                  = i40e_dev_link_update,
 457         .stats_get                    = i40e_dev_stats_get,
 458         .xstats_get                   = i40e_dev_xstats_get,
 459         .xstats_get_names             = i40e_dev_xstats_get_names,
 460         .stats_reset                  = i40e_dev_stats_reset,
 461         .xstats_reset                 = i40e_dev_stats_reset,
 462         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 463         .fw_version_get               = i40e_fw_version_get,
 464         .dev_infos_get                = i40e_dev_info_get,
 465         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 466         .vlan_filter_set              = i40e_vlan_filter_set,
 467         .vlan_tpid_set                = i40e_vlan_tpid_set,
 468         .vlan_offload_set             = i40e_vlan_offload_set,
 469         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 470         .vlan_pvid_set                = i40e_vlan_pvid_set,
 471         .rx_queue_start               = i40e_dev_rx_queue_start,
 472         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 473         .tx_queue_start               = i40e_dev_tx_queue_start,
 474         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 475         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 476         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 477         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 478         .rx_queue_release             = i40e_dev_rx_queue_release,
 479         .rx_queue_count               = i40e_dev_rx_queue_count,
 480         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 481         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 482         .tx_queue_release             = i40e_dev_tx_queue_release,
 483         .dev_led_on                   = i40e_dev_led_on,
 484         .dev_led_off                  = i40e_dev_led_off,
 485         .flow_ctrl_get                = i40e_flow_ctrl_get,
 486         .flow_ctrl_set                = i40e_flow_ctrl_set,
 487         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 488         .mac_addr_add                 = i40e_macaddr_add,
 489         .mac_addr_remove              = i40e_macaddr_remove,
 490         .reta_update                  = i40e_dev_rss_reta_update,
 491         .reta_query                   = i40e_dev_rss_reta_query,
 492         .rss_hash_update              = i40e_dev_rss_hash_update,
 493         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 494         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 495         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 496         .filter_ctrl                  = i40e_dev_filter_ctrl,
 497         .rxq_info_get                 = i40e_rxq_info_get,
 498         .txq_info_get                 = i40e_txq_info_get,
 499         .mirror_rule_set              = i40e_mirror_rule_set,
 500         .mirror_rule_reset            = i40e_mirror_rule_reset,
 501         .timesync_enable              = i40e_timesync_enable,
 502         .timesync_disable             = i40e_timesync_disable,
 503         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 504         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 505         .get_dcb_info                 = i40e_dev_get_dcb_info,
 506         .timesync_adjust_time         = i40e_timesync_adjust_time,
 507         .timesync_read_time           = i40e_timesync_read_time,
 508         .timesync_write_time          = i40e_timesync_write_time,
 509         .get_reg                      = i40e_get_regs,
 510         .get_eeprom_length            = i40e_get_eeprom_length,
 511         .get_eeprom                   = i40e_get_eeprom,
 512         .mac_addr_set                 = i40e_set_default_mac_addr,
 513         .mtu_set                      = i40e_dev_mtu_set,
 514 };
 515
 516 /* store statistics names and its offset in stats structure */
 517 struct rte_i40e_xstats_name_off {
 518         char name[RTE_ETH_XSTATS_NAME_SIZE];
 519         unsigned offset;
 520 };
 521
 522 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 523         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 524         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 525         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 526         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 527         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 528                 rx_unknown_protocol)},
 529         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 530         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 531         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 532         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 533 };
 534
 535 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 536                 sizeof(rte_i40e_stats_strings[0]))
 537
 538 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 539         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 540                 tx_dropped_link_down)},
 541         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 542         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 543                 illegal_bytes)},
 544         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 545         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 546                 mac_local_faults)},
 547         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 548                 mac_remote_faults)},
 549         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 550                 rx_length_errors)},
 551         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 552         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 553         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 554         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 555         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 556         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 557                 rx_size_127)},
 558         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 559                 rx_size_255)},
 560         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 561                 rx_size_511)},
 562         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 563                 rx_size_1023)},
 564         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 565                 rx_size_1522)},
 566         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 567                 rx_size_big)},
 568         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 569                 rx_undersize)},
 570         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 571                 rx_oversize)},
 572         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 573                 mac_short_packet_dropped)},
 574         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 575                 rx_fragments)},
 576         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 577         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 578         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 579                 tx_size_127)},
 580         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 581                 tx_size_255)},
 582         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 583                 tx_size_511)},
 584         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 585                 tx_size_1023)},
 586         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 587                 tx_size_1522)},
 588         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 589                 tx_size_big)},
 590         {"rx_flow_director_atr_match_packets",
 591                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 592         {"rx_flow_director_sb_match_packets",
 593                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 594         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 595                 tx_lpi_status)},
 596         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 597                 rx_lpi_status)},
 598         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 599                 tx_lpi_count)},
 600         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 601                 rx_lpi_count)},
 602 };
 603
 604 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 605                 sizeof(rte_i40e_hw_port_strings[0]))
 606
 607 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 608         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 609                 priority_xon_rx)},
 610         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 611                 priority_xoff_rx)},
 612 };
 613
 614 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 615                 sizeof(rte_i40e_rxq_prio_strings[0]))
 616
 617 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 618         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 619                 priority_xon_tx)},
 620         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 621                 priority_xoff_tx)},
 622         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 623                 priority_xon_2_xoff)},
 624 };
 625
 626 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 627                 sizeof(rte_i40e_txq_prio_strings[0]))
 628
 629 static struct eth_driver rte_i40e_pmd = {
 630         .pci_drv = {
 631                 .id_table = pci_id_i40e_map,
 632                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 633                 .probe = rte_eth_dev_pci_probe,
 634                 .remove = rte_eth_dev_pci_remove,
 635         },
 636         .eth_dev_init = eth_i40e_dev_init,
 637         .eth_dev_uninit = eth_i40e_dev_uninit,
 638         .dev_private_size = sizeof(struct i40e_adapter),
 639 };
 640
 641 static inline int
 642 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 643                                      struct rte_eth_link *link)
 644 {
 645         struct rte_eth_link *dst = link;
 646         struct rte_eth_link *src = &(dev->data->dev_link);
 647
 648         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 649                                         *(uint64_t *)src) == 0)
 650                 return -1;
 651
 652         return 0;
 653 }
 654
 655 static inline int
 656 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 657                                       struct rte_eth_link *link)
 658 {
 659         struct rte_eth_link *dst = &(dev->data->dev_link);
 660         struct rte_eth_link *src = link;
 661
 662         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 663                                         *(uint64_t *)src) == 0)
 664                 return -1;
 665
 666         return 0;
 667 }
 668
 669 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 670 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 671 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 672
 673 #ifndef I40E_GLQF_ORT
 674 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 675 #endif
 676 #ifndef I40E_GLQF_PIT
 677 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 678 #endif
 679
 680 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 681 {
 682         /*
 683          * Initialize registers for flexible payload, which should be set by NVM.
 684          * This should be removed from code once it is fixed in NVM.
 685          */
 686         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 687         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 688         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 689         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 690         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 691         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 692         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 693         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 694         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 695         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 696         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 697         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 698
 699         /* Initialize registers for parsing packet type of QinQ */
 700         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 701         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 702 }
 703
 704 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 705
 706 /*
 707  * Add a ethertype filter to drop all flow control frames transmitted
 708  * from VSIs.
 709 */
 710 static void
 711 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 712 {
 713         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 714         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 715                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 716                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 717         int ret;
 718
 719         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 720                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 721                                 pf->main_vsi_seid, 0,
 722                                 TRUE, NULL, NULL);
 723         if (ret)
 724                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 725                                   " frames from VSIs.");
 726 }
 727
 728 static int
 729 floating_veb_list_handler(__rte_unused const char *key,
 730                           const char *floating_veb_value,
 731                           void *opaque)
 732 {
 733         int idx = 0;
 734         unsigned int count = 0;
 735         char *end = NULL;
 736         int min, max;
 737         bool *vf_floating_veb = opaque;
 738
 739         while (isblank(*floating_veb_value))
 740                 floating_veb_value++;
 741
 742         /* Reset floating VEB configuration for VFs */
 743         for (idx = 0; idx < I40E_MAX_VF; idx++)
 744                 vf_floating_veb[idx] = false;
 745
 746         min = I40E_MAX_VF;
 747         do {
 748                 while (isblank(*floating_veb_value))
 749                         floating_veb_value++;
 750                 if (*floating_veb_value == '\0')
 751                         return -1;
 752                 errno = 0;
 753                 idx = strtoul(floating_veb_value, &end, 10);
 754                 if (errno || end == NULL)
 755                         return -1;
 756                 while (isblank(*end))
 757                         end++;
 758                 if (*end == '-') {
 759                         min = idx;
 760                 } else if ((*end == ';') || (*end == '\0')) {
 761                         max = idx;
 762                         if (min == I40E_MAX_VF)
 763                                 min = idx;
 764                         if (max >= I40E_MAX_VF)
 765                                 max = I40E_MAX_VF - 1;
 766                         for (idx = min; idx <= max; idx++) {
 767                                 vf_floating_veb[idx] = true;
 768                                 count++;
 769                         }
 770                         min = I40E_MAX_VF;
 771                 } else {
 772                         return -1;
 773                 }
 774                 floating_veb_value = end + 1;
 775         } while (*end != '\0');
 776
 777         if (count == 0)
 778                 return -1;
 779
 780         return 0;
 781 }
 782
 783 static void
 784 config_vf_floating_veb(struct rte_devargs *devargs,
 785                        uint16_t floating_veb,
 786                        bool *vf_floating_veb)
 787 {
 788         struct rte_kvargs *kvlist;
 789         int i;
 790         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 791
 792         if (!floating_veb)
 793                 return;
 794         /* All the VFs attach to the floating VEB by default
 795          * when the floating VEB is enabled.
 796          */
 797         for (i = 0; i < I40E_MAX_VF; i++)
 798                 vf_floating_veb[i] = true;
 799
 800         if (devargs == NULL)
 801                 return;
 802
 803         kvlist = rte_kvargs_parse(devargs->args, NULL);
 804         if (kvlist == NULL)
 805                 return;
 806
 807         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 808                 rte_kvargs_free(kvlist);
 809                 return;
 810         }
 811         /* When the floating_veb_list parameter exists, all the VFs
 812          * will attach to the legacy VEB firstly, then configure VFs
 813          * to the floating VEB according to the floating_veb_list.
 814          */
 815         if (rte_kvargs_process(kvlist, floating_veb_list,
 816                                floating_veb_list_handler,
 817                                vf_floating_veb) < 0) {
 818                 rte_kvargs_free(kvlist);
 819                 return;
 820         }
 821         rte_kvargs_free(kvlist);
 822 }
 823
 824 static int
 825 i40e_check_floating_handler(__rte_unused const char *key,
 826                             const char *value,
 827                             __rte_unused void *opaque)
 828 {
 829         if (strcmp(value, "1"))
 830                 return -1;
 831
 832         return 0;
 833 }
 834
 835 static int
 836 is_floating_veb_supported(struct rte_devargs *devargs)
 837 {
 838         struct rte_kvargs *kvlist;
 839         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 840
 841         if (devargs == NULL)
 842                 return 0;
 843
 844         kvlist = rte_kvargs_parse(devargs->args, NULL);
 845         if (kvlist == NULL)
 846                 return 0;
 847
 848         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 849                 rte_kvargs_free(kvlist);
 850                 return 0;
 851         }
 852         /* Floating VEB is enabled when there's key-value:
 853          * enable_floating_veb=1
 854          */
 855         if (rte_kvargs_process(kvlist, floating_veb_key,
 856                                i40e_check_floating_handler, NULL) < 0) {
 857                 rte_kvargs_free(kvlist);
 858                 return 0;
 859         }
 860         rte_kvargs_free(kvlist);
 861
 862         return 1;
 863 }
 864
 865 static void
 866 config_floating_veb(struct rte_eth_dev *dev)
 867 {
 868         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 869         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 870         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 871
 872         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 873
 874         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 875                 pf->floating_veb =
 876                         is_floating_veb_supported(pci_dev->device.devargs);
 877                 config_vf_floating_veb(pci_dev->device.devargs,
 878                                        pf->floating_veb,
 879                                        pf->floating_veb_list);
 880         } else {
 881                 pf->floating_veb = false;
 882         }
 883 }
 884
 885 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 886 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 887
 888 static int
 889 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 890 {
 891         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 892         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 893         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 894         int ret;
 895
 896         struct rte_hash_parameters ethertype_hash_params = {
 897                 .name = ethertype_hash_name,
 898                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 899                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 900                 .hash_func = rte_hash_crc,
 901         };
 902
 903         /* Initialize ethertype filter rule list and hash */
 904         TAILQ_INIT(&ethertype_rule->ethertype_list);
 905         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 906                  "ethertype_%s", dev->data->name);
 907         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 908         if (!ethertype_rule->hash_table) {
 909                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 910                 return -EINVAL;
 911         }
 912         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 913                                        sizeof(struct i40e_ethertype_filter *) *
 914                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 915                                        0);
 916         if (!ethertype_rule->hash_map) {
 917                 PMD_INIT_LOG(ERR,
 918                              "Failed to allocate memory for ethertype hash map!");
 919                 ret = -ENOMEM;
 920                 goto err_ethertype_hash_map_alloc;
 921         }
 922
 923         return 0;
 924
 925 err_ethertype_hash_map_alloc:
 926         rte_hash_free(ethertype_rule->hash_table);
 927
 928         return ret;
 929 }
 930
 931 static int
 932 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 933 {
 934         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 935         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 936         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 937         int ret;
 938
 939         struct rte_hash_parameters tunnel_hash_params = {
 940                 .name = tunnel_hash_name,
 941                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 942                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 943                 .hash_func = rte_hash_crc,
 944         };
 945
 946         /* Initialize tunnel filter rule list and hash */
 947         TAILQ_INIT(&tunnel_rule->tunnel_list);
 948         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 949                  "tunnel_%s", dev->data->name);
 950         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 951         if (!tunnel_rule->hash_table) {
 952                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 953                 return -EINVAL;
 954         }
 955         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 956                                     sizeof(struct i40e_tunnel_filter *) *
 957                                     I40E_MAX_TUNNEL_FILTER_NUM,
 958                                     0);
 959         if (!tunnel_rule->hash_map) {
 960                 PMD_INIT_LOG(ERR,
 961                              "Failed to allocate memory for tunnel hash map!");
 962                 ret = -ENOMEM;
 963                 goto err_tunnel_hash_map_alloc;
 964         }
 965
 966         return 0;
 967
 968 err_tunnel_hash_map_alloc:
 969         rte_hash_free(tunnel_rule->hash_table);
 970
 971         return ret;
 972 }
 973
 974 static int
 975 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 976 {
 977         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 978         struct i40e_fdir_info *fdir_info = &pf->fdir;
 979         char fdir_hash_name[RTE_HASH_NAMESIZE];
 980         int ret;
 981
 982         struct rte_hash_parameters fdir_hash_params = {
 983                 .name = fdir_hash_name,
 984                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 985                 .key_len = sizeof(struct rte_eth_fdir_input),
 986                 .hash_func = rte_hash_crc,
 987         };
 988
 989         /* Initialize flow director filter rule list and hash */
 990         TAILQ_INIT(&fdir_info->fdir_list);
 991         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 992                  "fdir_%s", dev->data->name);
 993         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
 994         if (!fdir_info->hash_table) {
 995                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 996                 return -EINVAL;
 997         }
 998         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
 999                                           sizeof(struct i40e_fdir_filter *) *
1000                                           I40E_MAX_FDIR_FILTER_NUM,
1001                                           0);
1002         if (!fdir_info->hash_map) {
1003                 PMD_INIT_LOG(ERR,
1004                              "Failed to allocate memory for fdir hash map!");
1005                 ret = -ENOMEM;
1006                 goto err_fdir_hash_map_alloc;
1007         }
1008         return 0;
1009
1010 err_fdir_hash_map_alloc:
1011         rte_hash_free(fdir_info->hash_table);
1012
1013         return ret;
1014 }
1015
1016 static int
1017 eth_i40e_dev_init(struct rte_eth_dev *dev)
1018 {
1019         struct rte_pci_device *pci_dev;
1020         struct rte_intr_handle *intr_handle;
1021         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1022         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1023         struct i40e_vsi *vsi;
1024         int ret;
1025         uint32_t len;
1026         uint8_t aq_fail = 0;
1027
1028         PMD_INIT_FUNC_TRACE();
1029
1030         dev->dev_ops = &i40e_eth_dev_ops;
1031         dev->rx_pkt_burst = i40e_recv_pkts;
1032         dev->tx_pkt_burst = i40e_xmit_pkts;
1033         dev->tx_pkt_prepare = i40e_prep_pkts;
1034
1035         /* for secondary processes, we don't initialise any further as primary
1036          * has already done this work. Only check we don't need a different
1037          * RX function */
1038         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1039                 i40e_set_rx_function(dev);
1040                 i40e_set_tx_function(dev);
1041                 return 0;
1042         }
1043         pci_dev = I40E_DEV_TO_PCI(dev);
1044         intr_handle = &pci_dev->intr_handle;
1045
1046         rte_eth_copy_pci_info(dev, pci_dev);
1047         dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1048
1049         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1050         pf->adapter->eth_dev = dev;
1051         pf->dev_data = dev->data;
1052
1053         hw->back = I40E_PF_TO_ADAPTER(pf);
1054         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1055         if (!hw->hw_addr) {
1056                 PMD_INIT_LOG(ERR, "Hardware is not available, "
1057                              "as address is NULL");
1058                 return -ENODEV;
1059         }
1060
1061         hw->vendor_id = pci_dev->id.vendor_id;
1062         hw->device_id = pci_dev->id.device_id;
1063         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1064         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1065         hw->bus.device = pci_dev->addr.devid;
1066         hw->bus.func = pci_dev->addr.function;
1067         hw->adapter_stopped = 0;
1068
1069         /* Make sure all is clean before doing PF reset */
1070         i40e_clear_hw(hw);
1071
1072         /* Initialize the hardware */
1073         i40e_hw_init(dev);
1074
1075         /* Reset here to make sure all is clean for each PF */
1076         ret = i40e_pf_reset(hw);
1077         if (ret) {
1078                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1079                 return ret;
1080         }
1081
1082         /* Initialize the shared code (base driver) */
1083         ret = i40e_init_shared_code(hw);
1084         if (ret) {
1085                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1086                 return ret;
1087         }
1088
1089         /*
1090          * To work around the NVM issue, initialize registers
1091          * for flexible payload and packet type of QinQ by
1092          * software. It should be removed once issues are fixed
1093          * in NVM.
1094          */
1095         i40e_GLQF_reg_init(hw);
1096
1097         /* Initialize the input set for filters (hash and fd) to default value */
1098         i40e_filter_input_set_init(pf);
1099
1100         /* Initialize the parameters for adminq */
1101         i40e_init_adminq_parameter(hw);
1102         ret = i40e_init_adminq(hw);
1103         if (ret != I40E_SUCCESS) {
1104                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1105                 return -EIO;
1106         }
1107         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1108                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1109                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1110                      ((hw->nvm.version >> 12) & 0xf),
1111                      ((hw->nvm.version >> 4) & 0xff),
1112                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1113
1114         /* Need the special FW version to support floating VEB */
1115         config_floating_veb(dev);
1116         /* Clear PXE mode */
1117         i40e_clear_pxe_mode(hw);
1118         ret = i40e_dev_sync_phy_type(hw);
1119         if (ret) {
1120                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1121                 goto err_sync_phy_type;
1122         }
1123         /*
1124          * On X710, performance number is far from the expectation on recent
1125          * firmware versions. The fix for this issue may not be integrated in
1126          * the following firmware version. So the workaround in software driver
1127          * is needed. It needs to modify the initial values of 3 internal only
1128          * registers. Note that the workaround can be removed when it is fixed
1129          * in firmware in the future.
1130          */
1131         i40e_configure_registers(hw);
1132
1133         /* Get hw capabilities */
1134         ret = i40e_get_cap(hw);
1135         if (ret != I40E_SUCCESS) {
1136                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1137                 goto err_get_capabilities;
1138         }
1139
1140         /* Initialize parameters for PF */
1141         ret = i40e_pf_parameter_init(dev);
1142         if (ret != 0) {
1143                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1144                 goto err_parameter_init;
1145         }
1146
1147         /* Initialize the queue management */
1148         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1149         if (ret < 0) {
1150                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1151                 goto err_qp_pool_init;
1152         }
1153         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1154                                 hw->func_caps.num_msix_vectors - 1);
1155         if (ret < 0) {
1156                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1157                 goto err_msix_pool_init;
1158         }
1159
1160         /* Initialize lan hmc */
1161         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1162                                 hw->func_caps.num_rx_qp, 0, 0);
1163         if (ret != I40E_SUCCESS) {
1164                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1165                 goto err_init_lan_hmc;
1166         }
1167
1168         /* Configure lan hmc */
1169         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1170         if (ret != I40E_SUCCESS) {
1171                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1172                 goto err_configure_lan_hmc;
1173         }
1174
1175         /* Get and check the mac address */
1176         i40e_get_mac_addr(hw, hw->mac.addr);
1177         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1178                 PMD_INIT_LOG(ERR, "mac address is not valid");
1179                 ret = -EIO;
1180                 goto err_get_mac_addr;
1181         }
1182         /* Copy the permanent MAC address */
1183         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1184                         (struct ether_addr *) hw->mac.perm_addr);
1185
1186         /* Disable flow control */
1187         hw->fc.requested_mode = I40E_FC_NONE;
1188         i40e_set_fc(hw, &aq_fail, TRUE);
1189
1190         /* Set the global registers with default ether type value */
1191         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1192         if (ret != I40E_SUCCESS) {
1193                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1194                              "VLAN ether type");
1195                 goto err_setup_pf_switch;
1196         }
1197
1198         /* PF setup, which includes VSI setup */
1199         ret = i40e_pf_setup(pf);
1200         if (ret) {
1201                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1202                 goto err_setup_pf_switch;
1203         }
1204
1205         /* reset all stats of the device, including pf and main vsi */
1206         i40e_dev_stats_reset(dev);
1207
1208         vsi = pf->main_vsi;
1209
1210         /* Disable double vlan by default */
1211         i40e_vsi_config_double_vlan(vsi, FALSE);
1212
1213         /* Disable S-TAG identification when floating_veb is disabled */
1214         if (!pf->floating_veb) {
1215                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1216                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1217                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1218                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1219                 }
1220         }
1221
1222         if (!vsi->max_macaddrs)
1223                 len = ETHER_ADDR_LEN;
1224         else
1225                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1226
1227         /* Should be after VSI initialized */
1228         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1229         if (!dev->data->mac_addrs) {
1230                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1231                                         "for storing mac address");
1232                 goto err_mac_alloc;
1233         }
1234         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1235                                         &dev->data->mac_addrs[0]);
1236
1237         /* initialize pf host driver to setup SRIOV resource if applicable */
1238         i40e_pf_host_init(dev);
1239
1240         /* register callback func to eal lib */
1241         rte_intr_callback_register(intr_handle,
1242                                    i40e_dev_interrupt_handler, dev);
1243
1244         /* configure and enable device interrupt */
1245         i40e_pf_config_irq0(hw, TRUE);
1246         i40e_pf_enable_irq0(hw);
1247
1248         /* enable uio intr after callback register */
1249         rte_intr_enable(intr_handle);
1250         /*
1251          * Add an ethertype filter to drop all flow control frames transmitted
1252          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1253          * frames to wire.
1254          */
1255         i40e_add_tx_flow_control_drop_filter(pf);
1256
1257         /* Set the max frame size to 0x2600 by default,
1258          * in case other drivers changed the default value.
1259          */
1260         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1261
1262         /* initialize mirror rule list */
1263         TAILQ_INIT(&pf->mirror_list);
1264
1265         /* Init dcb to sw mode by default */
1266         ret = i40e_dcb_init_configure(dev, TRUE);
1267         if (ret != I40E_SUCCESS) {
1268                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1269                 pf->flags &= ~I40E_FLAG_DCB;
1270         }
1271
1272         ret = i40e_init_ethtype_filter_list(dev);
1273         if (ret < 0)
1274                 goto err_init_ethtype_filter_list;
1275         ret = i40e_init_tunnel_filter_list(dev);
1276         if (ret < 0)
1277                 goto err_init_tunnel_filter_list;
1278         ret = i40e_init_fdir_filter_list(dev);
1279         if (ret < 0)
1280                 goto err_init_fdir_filter_list;
1281
1282         return 0;
1283
1284 err_init_fdir_filter_list:
1285         rte_free(pf->tunnel.hash_table);
1286         rte_free(pf->tunnel.hash_map);
1287 err_init_tunnel_filter_list:
1288         rte_free(pf->ethertype.hash_table);
1289         rte_free(pf->ethertype.hash_map);
1290 err_init_ethtype_filter_list:
1291         rte_free(dev->data->mac_addrs);
1292 err_mac_alloc:
1293         i40e_vsi_release(pf->main_vsi);
1294 err_setup_pf_switch:
1295 err_get_mac_addr:
1296 err_configure_lan_hmc:
1297         (void)i40e_shutdown_lan_hmc(hw);
1298 err_init_lan_hmc:
1299         i40e_res_pool_destroy(&pf->msix_pool);
1300 err_msix_pool_init:
1301         i40e_res_pool_destroy(&pf->qp_pool);
1302 err_qp_pool_init:
1303 err_parameter_init:
1304 err_get_capabilities:
1305 err_sync_phy_type:
1306         (void)i40e_shutdown_adminq(hw);
1307
1308         return ret;
1309 }
1310
1311 static void
1312 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1313 {
1314         struct i40e_ethertype_filter *p_ethertype;
1315         struct i40e_ethertype_rule *ethertype_rule;
1316
1317         ethertype_rule = &pf->ethertype;
1318         /* Remove all ethertype filter rules and hash */
1319         if (ethertype_rule->hash_map)
1320                 rte_free(ethertype_rule->hash_map);
1321         if (ethertype_rule->hash_table)
1322                 rte_hash_free(ethertype_rule->hash_table);
1323
1324         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1325                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1326                              p_ethertype, rules);
1327                 rte_free(p_ethertype);
1328         }
1329 }
1330
1331 static void
1332 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1333 {
1334         struct i40e_tunnel_filter *p_tunnel;
1335         struct i40e_tunnel_rule *tunnel_rule;
1336
1337         tunnel_rule = &pf->tunnel;
1338         /* Remove all tunnel director rules and hash */
1339         if (tunnel_rule->hash_map)
1340                 rte_free(tunnel_rule->hash_map);
1341         if (tunnel_rule->hash_table)
1342                 rte_hash_free(tunnel_rule->hash_table);
1343
1344         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1345                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1346                 rte_free(p_tunnel);
1347         }
1348 }
1349
1350 static void
1351 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1352 {
1353         struct i40e_fdir_filter *p_fdir;
1354         struct i40e_fdir_info *fdir_info;
1355
1356         fdir_info = &pf->fdir;
1357         /* Remove all flow director rules and hash */
1358         if (fdir_info->hash_map)
1359                 rte_free(fdir_info->hash_map);
1360         if (fdir_info->hash_table)
1361                 rte_hash_free(fdir_info->hash_table);
1362
1363         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1364                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1365                 rte_free(p_fdir);
1366         }
1367 }
1368
1369 static int
1370 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1371 {
1372         struct i40e_pf *pf;
1373         struct rte_pci_device *pci_dev;
1374         struct rte_intr_handle *intr_handle;
1375         struct i40e_hw *hw;
1376         struct i40e_filter_control_settings settings;
1377         struct rte_flow *p_flow;
1378         int ret;
1379         uint8_t aq_fail = 0;
1380
1381         PMD_INIT_FUNC_TRACE();
1382
1383         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1384                 return 0;
1385
1386         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1387         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1388         pci_dev = I40E_DEV_TO_PCI(dev);
1389         intr_handle = &pci_dev->intr_handle;
1390
1391         if (hw->adapter_stopped == 0)
1392                 i40e_dev_close(dev);
1393
1394         dev->dev_ops = NULL;
1395         dev->rx_pkt_burst = NULL;
1396         dev->tx_pkt_burst = NULL;
1397
1398         /* Clear PXE mode */
1399         i40e_clear_pxe_mode(hw);
1400
1401         /* Unconfigure filter control */
1402         memset(&settings, 0, sizeof(settings));
1403         ret = i40e_set_filter_control(hw, &settings);
1404         if (ret)
1405                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1406                                         ret);
1407
1408         /* Disable flow control */
1409         hw->fc.requested_mode = I40E_FC_NONE;
1410         i40e_set_fc(hw, &aq_fail, TRUE);
1411
1412         /* uninitialize pf host driver */
1413         i40e_pf_host_uninit(dev);
1414
1415         rte_free(dev->data->mac_addrs);
1416         dev->data->mac_addrs = NULL;
1417
1418         /* disable uio intr before callback unregister */
1419         rte_intr_disable(intr_handle);
1420
1421         /* register callback func to eal lib */
1422         rte_intr_callback_unregister(intr_handle,
1423                                      i40e_dev_interrupt_handler, dev);
1424
1425         i40e_rm_ethtype_filter_list(pf);
1426         i40e_rm_tunnel_filter_list(pf);
1427         i40e_rm_fdir_filter_list(pf);
1428
1429         /* Remove all flows */
1430         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1431                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1432                 rte_free(p_flow);
1433         }
1434
1435         return 0;
1436 }
1437
1438 static int
1439 i40e_dev_configure(struct rte_eth_dev *dev)
1440 {
1441         struct i40e_adapter *ad =
1442                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1443         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1444         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1445         int i, ret;
1446
1447         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1448          * bulk allocation or vector Rx preconditions we will reset it.
1449          */
1450         ad->rx_bulk_alloc_allowed = true;
1451         ad->rx_vec_allowed = true;
1452         ad->tx_simple_allowed = true;
1453         ad->tx_vec_allowed = true;
1454
1455         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1456                 ret = i40e_fdir_setup(pf);
1457                 if (ret != I40E_SUCCESS) {
1458                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1459                         return -ENOTSUP;
1460                 }
1461                 ret = i40e_fdir_configure(dev);
1462                 if (ret < 0) {
1463                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1464                         goto err;
1465                 }
1466         } else
1467                 i40e_fdir_teardown(pf);
1468
1469         ret = i40e_dev_init_vlan(dev);
1470         if (ret < 0)
1471                 goto err;
1472
1473         /* VMDQ setup.
1474          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1475          *  RSS setting have different requirements.
1476          *  General PMD driver call sequence are NIC init, configure,
1477          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1478          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1479          *  applicable. So, VMDQ setting has to be done before
1480          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1481          *  For RSS setting, it will try to calculate actual configured RX queue
1482          *  number, which will be available after rx_queue_setup(). dev_start()
1483          *  function is good to place RSS setup.
1484          */
1485         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1486                 ret = i40e_vmdq_setup(dev);
1487                 if (ret)
1488                         goto err;
1489         }
1490
1491         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1492                 ret = i40e_dcb_setup(dev);
1493                 if (ret) {
1494                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1495                         goto err_dcb;
1496                 }
1497         }
1498
1499         TAILQ_INIT(&pf->flow_list);
1500
1501         return 0;
1502
1503 err_dcb:
1504         /* need to release vmdq resource if exists */
1505         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1506                 i40e_vsi_release(pf->vmdq[i].vsi);
1507                 pf->vmdq[i].vsi = NULL;
1508         }
1509         rte_free(pf->vmdq);
1510         pf->vmdq = NULL;
1511 err:
1512         /* need to release fdir resource if exists */
1513         i40e_fdir_teardown(pf);
1514         return ret;
1515 }
1516
1517 void
1518 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1519 {
1520         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1521         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1522         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1523         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1524         uint16_t msix_vect = vsi->msix_intr;
1525         uint16_t i;
1526
1527         for (i = 0; i < vsi->nb_qps; i++) {
1528                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1529                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1530                 rte_wmb();
1531         }
1532
1533         if (vsi->type != I40E_VSI_SRIOV) {
1534                 if (!rte_intr_allow_others(intr_handle)) {
1535                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1536                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1537                         I40E_WRITE_REG(hw,
1538                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1539                                        0);
1540                 } else {
1541                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1542                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1543                         I40E_WRITE_REG(hw,
1544                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1545                                                        msix_vect - 1), 0);
1546                 }
1547         } else {
1548                 uint32_t reg;
1549                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1550                         vsi->user_param + (msix_vect - 1);
1551
1552                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1553                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1554         }
1555         I40E_WRITE_FLUSH(hw);
1556 }
1557
1558 static void
1559 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1560                        int base_queue, int nb_queue)
1561 {
1562         int i;
1563         uint32_t val;
1564         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1565
1566         /* Bind all RX queues to allocated MSIX interrupt */
1567         for (i = 0; i < nb_queue; i++) {
1568                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1569                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1570                         ((base_queue + i + 1) <<
1571                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1572                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1573                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1574
1575                 if (i == nb_queue - 1)
1576                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1577                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1578         }
1579
1580         /* Write first RX queue to Link list register as the head element */
1581         if (vsi->type != I40E_VSI_SRIOV) {
1582                 uint16_t interval =
1583                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1584
1585                 if (msix_vect == I40E_MISC_VEC_ID) {
1586                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1587                                        (base_queue <<
1588                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1589                                        (0x0 <<
1590                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1591                         I40E_WRITE_REG(hw,
1592                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1593                                        interval);
1594                 } else {
1595                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1596                                        (base_queue <<
1597                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1598                                        (0x0 <<
1599                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1600                         I40E_WRITE_REG(hw,
1601                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1602                                                        msix_vect - 1),
1603                                        interval);
1604                 }
1605         } else {
1606                 uint32_t reg;
1607
1608                 if (msix_vect == I40E_MISC_VEC_ID) {
1609                         I40E_WRITE_REG(hw,
1610                                        I40E_VPINT_LNKLST0(vsi->user_param),
1611                                        (base_queue <<
1612                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1613                                        (0x0 <<
1614                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1615                 } else {
1616                         /* num_msix_vectors_vf needs to minus irq0 */
1617                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1618                                 vsi->user_param + (msix_vect - 1);
1619
1620                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1621                                        (base_queue <<
1622                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1623                                        (0x0 <<
1624                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1625                 }
1626         }
1627
1628         I40E_WRITE_FLUSH(hw);
1629 }
1630
1631 void
1632 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1633 {
1634         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1635         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1636         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1637         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1638         uint16_t msix_vect = vsi->msix_intr;
1639         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1640         uint16_t queue_idx = 0;
1641         int record = 0;
1642         uint32_t val;
1643         int i;
1644
1645         for (i = 0; i < vsi->nb_qps; i++) {
1646                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1647                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1648         }
1649
1650         /* INTENA flag is not auto-cleared for interrupt */
1651         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1652         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1653                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1654                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1655         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1656
1657         /* VF bind interrupt */
1658         if (vsi->type == I40E_VSI_SRIOV) {
1659                 __vsi_queues_bind_intr(vsi, msix_vect,
1660                                        vsi->base_queue, vsi->nb_qps);
1661                 return;
1662         }
1663
1664         /* PF & VMDq bind interrupt */
1665         if (rte_intr_dp_is_en(intr_handle)) {
1666                 if (vsi->type == I40E_VSI_MAIN) {
1667                         queue_idx = 0;
1668                         record = 1;
1669                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1670                         struct i40e_vsi *main_vsi =
1671                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1672                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1673                         record = 1;
1674                 }
1675         }
1676
1677         for (i = 0; i < vsi->nb_used_qps; i++) {
1678                 if (nb_msix <= 1) {
1679                         if (!rte_intr_allow_others(intr_handle))
1680                                 /* allow to share MISC_VEC_ID */
1681                                 msix_vect = I40E_MISC_VEC_ID;
1682
1683                         /* no enough msix_vect, map all to one */
1684                         __vsi_queues_bind_intr(vsi, msix_vect,
1685                                                vsi->base_queue + i,
1686                                                vsi->nb_used_qps - i);
1687                         for (; !!record && i < vsi->nb_used_qps; i++)
1688                                 intr_handle->intr_vec[queue_idx + i] =
1689                                         msix_vect;
1690                         break;
1691                 }
1692                 /* 1:1 queue/msix_vect mapping */
1693                 __vsi_queues_bind_intr(vsi, msix_vect,
1694                                        vsi->base_queue + i, 1);
1695                 if (!!record)
1696                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1697
1698                 msix_vect++;
1699                 nb_msix--;
1700         }
1701 }
1702
1703 static void
1704 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1705 {
1706         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1707         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1708         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1709         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1710         uint16_t interval = i40e_calc_itr_interval(\
1711                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1712         uint16_t msix_intr, i;
1713
1714         if (rte_intr_allow_others(intr_handle))
1715                 for (i = 0; i < vsi->nb_msix; i++) {
1716                         msix_intr = vsi->msix_intr + i;
1717                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1718                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1719                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1720                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1721                                 (interval <<
1722                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1723                 }
1724         else
1725                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1726                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1727                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1728                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1729                                (interval <<
1730                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1731
1732         I40E_WRITE_FLUSH(hw);
1733 }
1734
1735 static void
1736 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1737 {
1738         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1739         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1740         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1741         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1742         uint16_t msix_intr, i;
1743
1744         if (rte_intr_allow_others(intr_handle))
1745                 for (i = 0; i < vsi->nb_msix; i++) {
1746                         msix_intr = vsi->msix_intr + i;
1747                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1748                                        0);
1749                 }
1750         else
1751                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1752
1753         I40E_WRITE_FLUSH(hw);
1754 }
1755
1756 static inline uint8_t
1757 i40e_parse_link_speeds(uint16_t link_speeds)
1758 {
1759         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1760
1761         if (link_speeds & ETH_LINK_SPEED_40G)
1762                 link_speed |= I40E_LINK_SPEED_40GB;
1763         if (link_speeds & ETH_LINK_SPEED_25G)
1764                 link_speed |= I40E_LINK_SPEED_25GB;
1765         if (link_speeds & ETH_LINK_SPEED_20G)
1766                 link_speed |= I40E_LINK_SPEED_20GB;
1767         if (link_speeds & ETH_LINK_SPEED_10G)
1768                 link_speed |= I40E_LINK_SPEED_10GB;
1769         if (link_speeds & ETH_LINK_SPEED_1G)
1770                 link_speed |= I40E_LINK_SPEED_1GB;
1771         if (link_speeds & ETH_LINK_SPEED_100M)
1772                 link_speed |= I40E_LINK_SPEED_100MB;
1773
1774         return link_speed;
1775 }
1776
1777 static int
1778 i40e_phy_conf_link(struct i40e_hw *hw,
1779                    uint8_t abilities,
1780                    uint8_t force_speed)
1781 {
1782         enum i40e_status_code status;
1783         struct i40e_aq_get_phy_abilities_resp phy_ab;
1784         struct i40e_aq_set_phy_config phy_conf;
1785         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1786                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1787                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1788                         I40E_AQ_PHY_FLAG_LOW_POWER;
1789         const uint8_t advt = I40E_LINK_SPEED_40GB |
1790                         I40E_LINK_SPEED_25GB |
1791                         I40E_LINK_SPEED_10GB |
1792                         I40E_LINK_SPEED_1GB |
1793                         I40E_LINK_SPEED_100MB;
1794         int ret = -ENOTSUP;
1795
1796
1797         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1798                                               NULL);
1799         if (status)
1800                 return ret;
1801
1802         memset(&phy_conf, 0, sizeof(phy_conf));
1803
1804         /* bits 0-2 use the values from get_phy_abilities_resp */
1805         abilities &= ~mask;
1806         abilities |= phy_ab.abilities & mask;
1807
1808         /* update ablities and speed */
1809         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1810                 phy_conf.link_speed = advt;
1811         else
1812                 phy_conf.link_speed = force_speed;
1813
1814         phy_conf.abilities = abilities;
1815
1816         /* use get_phy_abilities_resp value for the rest */
1817         phy_conf.phy_type = phy_ab.phy_type;
1818         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1819         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1820         phy_conf.eee_capability = phy_ab.eee_capability;
1821         phy_conf.eeer = phy_ab.eeer_val;
1822         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1823
1824         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1825                     phy_ab.abilities, phy_ab.link_speed);
1826         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1827                     phy_conf.abilities, phy_conf.link_speed);
1828
1829         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1830         if (status)
1831                 return ret;
1832
1833         return I40E_SUCCESS;
1834 }
1835
1836 static int
1837 i40e_apply_link_speed(struct rte_eth_dev *dev)
1838 {
1839         uint8_t speed;
1840         uint8_t abilities = 0;
1841         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1842         struct rte_eth_conf *conf = &dev->data->dev_conf;
1843
1844         speed = i40e_parse_link_speeds(conf->link_speeds);
1845         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1846         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1847                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1848         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1849
1850         /* Skip changing speed on 40G interfaces, FW does not support */
1851         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1852                 speed =  I40E_LINK_SPEED_UNKNOWN;
1853                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1854         }
1855
1856         return i40e_phy_conf_link(hw, abilities, speed);
1857 }
1858
1859 static int
1860 i40e_dev_start(struct rte_eth_dev *dev)
1861 {
1862         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1863         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1864         struct i40e_vsi *main_vsi = pf->main_vsi;
1865         int ret, i;
1866         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1867         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1868         uint32_t intr_vector = 0;
1869
1870         hw->adapter_stopped = 0;
1871
1872         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1873                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1874                              dev->data->port_id);
1875                 return -EINVAL;
1876         }
1877
1878         rte_intr_disable(intr_handle);
1879
1880         if ((rte_intr_cap_multiple(intr_handle) ||
1881              !RTE_ETH_DEV_SRIOV(dev).active) &&
1882             dev->data->dev_conf.intr_conf.rxq != 0) {
1883                 intr_vector = dev->data->nb_rx_queues;
1884                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1885                 if (ret)
1886                         return ret;
1887         }
1888
1889         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1890                 intr_handle->intr_vec =
1891                         rte_zmalloc("intr_vec",
1892                                     dev->data->nb_rx_queues * sizeof(int),
1893                                     0);
1894                 if (!intr_handle->intr_vec) {
1895                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1896                                      " intr_vec\n", dev->data->nb_rx_queues);
1897                         return -ENOMEM;
1898                 }
1899         }
1900
1901         /* Initialize VSI */
1902         ret = i40e_dev_rxtx_init(pf);
1903         if (ret != I40E_SUCCESS) {
1904                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1905                 goto err_up;
1906         }
1907
1908         /* Map queues with MSIX interrupt */
1909         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1910                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1911         i40e_vsi_queues_bind_intr(main_vsi);
1912         i40e_vsi_enable_queues_intr(main_vsi);
1913
1914         /* Map VMDQ VSI queues with MSIX interrupt */
1915         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1916                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1917                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1918                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1919         }
1920
1921         /* enable FDIR MSIX interrupt */
1922         if (pf->fdir.fdir_vsi) {
1923                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1924                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1925         }
1926
1927         /* Enable all queues which have been configured */
1928         ret = i40e_dev_switch_queues(pf, TRUE);
1929         if (ret != I40E_SUCCESS) {
1930                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1931                 goto err_up;
1932         }
1933
1934         /* Enable receiving broadcast packets */
1935         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1936         if (ret != I40E_SUCCESS)
1937                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1938
1939         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1940                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1941                                                 true, NULL);
1942                 if (ret != I40E_SUCCESS)
1943                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1944         }
1945
1946         /* Apply link configure */
1947         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1948                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1949                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1950                                 ETH_LINK_SPEED_40G)) {
1951                 PMD_DRV_LOG(ERR, "Invalid link setting");
1952                 goto err_up;
1953         }
1954         ret = i40e_apply_link_speed(dev);
1955         if (I40E_SUCCESS != ret) {
1956                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1957                 goto err_up;
1958         }
1959
1960         if (!rte_intr_allow_others(intr_handle)) {
1961                 rte_intr_callback_unregister(intr_handle,
1962                                              i40e_dev_interrupt_handler,
1963                                              (void *)dev);
1964                 /* configure and enable device interrupt */
1965                 i40e_pf_config_irq0(hw, FALSE);
1966                 i40e_pf_enable_irq0(hw);
1967
1968                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1969                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1970                                      " no intr multiplex\n");
1971         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1972                 ret = i40e_aq_set_phy_int_mask(hw,
1973                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1974                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1975                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1976                 if (ret != I40E_SUCCESS)
1977                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1978
1979                 /* Call get_link_info aq commond to enable LSE */
1980                 i40e_dev_link_update(dev, 0);
1981         }
1982
1983         /* enable uio intr after callback register */
1984         rte_intr_enable(intr_handle);
1985
1986         i40e_filter_restore(pf);
1987
1988         return I40E_SUCCESS;
1989
1990 err_up:
1991         i40e_dev_switch_queues(pf, FALSE);
1992         i40e_dev_clear_queues(dev);
1993
1994         return ret;
1995 }
1996
1997 static void
1998 i40e_dev_stop(struct rte_eth_dev *dev)
1999 {
2000         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2001         struct i40e_vsi *main_vsi = pf->main_vsi;
2002         struct i40e_mirror_rule *p_mirror;
2003         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2004         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2005         int i;
2006
2007         /* Disable all queues */
2008         i40e_dev_switch_queues(pf, FALSE);
2009
2010         /* un-map queues with interrupt registers */
2011         i40e_vsi_disable_queues_intr(main_vsi);
2012         i40e_vsi_queues_unbind_intr(main_vsi);
2013
2014         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2015                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2016                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2017         }
2018
2019         if (pf->fdir.fdir_vsi) {
2020                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2021                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2022         }
2023         /* Clear all queues and release memory */
2024         i40e_dev_clear_queues(dev);
2025
2026         /* Set link down */
2027         i40e_dev_set_link_down(dev);
2028
2029         /* Remove all mirror rules */
2030         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2031                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2032                 rte_free(p_mirror);
2033         }
2034         pf->nb_mirror_rule = 0;
2035
2036         if (!rte_intr_allow_others(intr_handle))
2037                 /* resume to the default handler */
2038                 rte_intr_callback_register(intr_handle,
2039                                            i40e_dev_interrupt_handler,
2040                                            (void *)dev);
2041
2042         /* Clean datapath event and queue/vec mapping */
2043         rte_intr_efd_disable(intr_handle);
2044         if (intr_handle->intr_vec) {
2045                 rte_free(intr_handle->intr_vec);
2046                 intr_handle->intr_vec = NULL;
2047         }
2048 }
2049
2050 static void
2051 i40e_dev_close(struct rte_eth_dev *dev)
2052 {
2053         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2054         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2055         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2056         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2057         uint32_t reg;
2058         int i;
2059
2060         PMD_INIT_FUNC_TRACE();
2061
2062         i40e_dev_stop(dev);
2063         hw->adapter_stopped = 1;
2064         i40e_dev_free_queues(dev);
2065
2066         /* Disable interrupt */
2067         i40e_pf_disable_irq0(hw);
2068         rte_intr_disable(intr_handle);
2069
2070         /* shutdown and destroy the HMC */
2071         i40e_shutdown_lan_hmc(hw);
2072
2073         /* release all the existing VSIs and VEBs */
2074         i40e_fdir_teardown(pf);
2075         i40e_vsi_release(pf->main_vsi);
2076
2077         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2078                 i40e_vsi_release(pf->vmdq[i].vsi);
2079                 pf->vmdq[i].vsi = NULL;
2080         }
2081
2082         rte_free(pf->vmdq);
2083         pf->vmdq = NULL;
2084
2085         /* shutdown the adminq */
2086         i40e_aq_queue_shutdown(hw, true);
2087         i40e_shutdown_adminq(hw);
2088
2089         i40e_res_pool_destroy(&pf->qp_pool);
2090         i40e_res_pool_destroy(&pf->msix_pool);
2091
2092         /* force a PF reset to clean anything leftover */
2093         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2094         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2095                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2096         I40E_WRITE_FLUSH(hw);
2097 }
2098
2099 static void
2100 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2101 {
2102         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2103         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2104         struct i40e_vsi *vsi = pf->main_vsi;
2105         int status;
2106
2107         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2108                                                      true, NULL, true);
2109         if (status != I40E_SUCCESS)
2110                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2111
2112         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2113                                                         TRUE, NULL);
2114         if (status != I40E_SUCCESS)
2115                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2116
2117 }
2118
2119 static void
2120 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2121 {
2122         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2123         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2124         struct i40e_vsi *vsi = pf->main_vsi;
2125         int status;
2126
2127         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2128                                                      false, NULL, true);
2129         if (status != I40E_SUCCESS)
2130                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2131
2132         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2133                                                         false, NULL);
2134         if (status != I40E_SUCCESS)
2135                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2136 }
2137
2138 static void
2139 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2140 {
2141         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2142         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2143         struct i40e_vsi *vsi = pf->main_vsi;
2144         int ret;
2145
2146         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2147         if (ret != I40E_SUCCESS)
2148                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2149 }
2150
2151 static void
2152 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2153 {
2154         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2155         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2156         struct i40e_vsi *vsi = pf->main_vsi;
2157         int ret;
2158
2159         if (dev->data->promiscuous == 1)
2160                 return; /* must remain in all_multicast mode */
2161
2162         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2163                                 vsi->seid, FALSE, NULL);
2164         if (ret != I40E_SUCCESS)
2165                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2166 }
2167
2168 /*
2169  * Set device link up.
2170  */
2171 static int
2172 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2173 {
2174         /* re-apply link speed setting */
2175         return i40e_apply_link_speed(dev);
2176 }
2177
2178 /*
2179  * Set device link down.
2180  */
2181 static int
2182 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2183 {
2184         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2185         uint8_t abilities = 0;
2186         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2187
2188         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2189         return i40e_phy_conf_link(hw, abilities, speed);
2190 }
2191
2192 int
2193 i40e_dev_link_update(struct rte_eth_dev *dev,
2194                      int wait_to_complete)
2195 {
2196 #define CHECK_INTERVAL 100  /* 100ms */
2197 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2198         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2199         struct i40e_link_status link_status;
2200         struct rte_eth_link link, old;
2201         int status;
2202         unsigned rep_cnt = MAX_REPEAT_TIME;
2203         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2204
2205         memset(&link, 0, sizeof(link));
2206         memset(&old, 0, sizeof(old));
2207         memset(&link_status, 0, sizeof(link_status));
2208         rte_i40e_dev_atomic_read_link_status(dev, &old);
2209
2210         do {
2211                 /* Get link status information from hardware */
2212                 status = i40e_aq_get_link_info(hw, enable_lse,
2213                                                 &link_status, NULL);
2214                 if (status != I40E_SUCCESS) {
2215                         link.link_speed = ETH_SPEED_NUM_100M;
2216                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2217                         PMD_DRV_LOG(ERR, "Failed to get link info");
2218                         goto out;
2219                 }
2220
2221                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2222                 if (!wait_to_complete)
2223                         break;
2224
2225                 rte_delay_ms(CHECK_INTERVAL);
2226         } while (!link.link_status && rep_cnt--);
2227
2228         if (!link.link_status)
2229                 goto out;
2230
2231         /* i40e uses full duplex only */
2232         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2233
2234         /* Parse the link status */
2235         switch (link_status.link_speed) {
2236         case I40E_LINK_SPEED_100MB:
2237                 link.link_speed = ETH_SPEED_NUM_100M;
2238                 break;
2239         case I40E_LINK_SPEED_1GB:
2240                 link.link_speed = ETH_SPEED_NUM_1G;
2241                 break;
2242         case I40E_LINK_SPEED_10GB:
2243                 link.link_speed = ETH_SPEED_NUM_10G;
2244                 break;
2245         case I40E_LINK_SPEED_20GB:
2246                 link.link_speed = ETH_SPEED_NUM_20G;
2247                 break;
2248         case I40E_LINK_SPEED_25GB:
2249                 link.link_speed = ETH_SPEED_NUM_25G;
2250                 break;
2251         case I40E_LINK_SPEED_40GB:
2252                 link.link_speed = ETH_SPEED_NUM_40G;
2253                 break;
2254         default:
2255                 link.link_speed = ETH_SPEED_NUM_100M;
2256                 break;
2257         }
2258
2259         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2260                         ETH_LINK_SPEED_FIXED);
2261
2262 out:
2263         rte_i40e_dev_atomic_write_link_status(dev, &link);
2264         if (link.link_status == old.link_status)
2265                 return -1;
2266
2267         return 0;
2268 }
2269
2270 /* Get all the statistics of a VSI */
2271 void
2272 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2273 {
2274         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2275         struct i40e_eth_stats *nes = &vsi->eth_stats;
2276         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2277         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2278
2279         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2280                             vsi->offset_loaded, &oes->rx_bytes,
2281                             &nes->rx_bytes);
2282         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2283                             vsi->offset_loaded, &oes->rx_unicast,
2284                             &nes->rx_unicast);
2285         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2286                             vsi->offset_loaded, &oes->rx_multicast,
2287                             &nes->rx_multicast);
2288         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2289                             vsi->offset_loaded, &oes->rx_broadcast,
2290                             &nes->rx_broadcast);
2291         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2292                             &oes->rx_discards, &nes->rx_discards);
2293         /* GLV_REPC not supported */
2294         /* GLV_RMPC not supported */
2295         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2296                             &oes->rx_unknown_protocol,
2297                             &nes->rx_unknown_protocol);
2298         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2299                             vsi->offset_loaded, &oes->tx_bytes,
2300                             &nes->tx_bytes);
2301         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2302                             vsi->offset_loaded, &oes->tx_unicast,
2303                             &nes->tx_unicast);
2304         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2305                             vsi->offset_loaded, &oes->tx_multicast,
2306                             &nes->tx_multicast);
2307         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2308                             vsi->offset_loaded,  &oes->tx_broadcast,
2309                             &nes->tx_broadcast);
2310         /* GLV_TDPC not supported */
2311         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2312                             &oes->tx_errors, &nes->tx_errors);
2313         vsi->offset_loaded = true;
2314
2315         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2316                     vsi->vsi_id);
2317         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2318         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2319         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2320         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2321         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2322         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2323                     nes->rx_unknown_protocol);
2324         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2325         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2326         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2327         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2328         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2329         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2330         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2331                     vsi->vsi_id);
2332 }
2333
2334 static void
2335 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2336 {
2337         unsigned int i;
2338         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2339         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2340
2341         /* Get statistics of struct i40e_eth_stats */
2342         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2343                             I40E_GLPRT_GORCL(hw->port),
2344                             pf->offset_loaded, &os->eth.rx_bytes,
2345                             &ns->eth.rx_bytes);
2346         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2347                             I40E_GLPRT_UPRCL(hw->port),
2348                             pf->offset_loaded, &os->eth.rx_unicast,
2349                             &ns->eth.rx_unicast);
2350         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2351                             I40E_GLPRT_MPRCL(hw->port),
2352                             pf->offset_loaded, &os->eth.rx_multicast,
2353                             &ns->eth.rx_multicast);
2354         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2355                             I40E_GLPRT_BPRCL(hw->port),
2356                             pf->offset_loaded, &os->eth.rx_broadcast,
2357                             &ns->eth.rx_broadcast);
2358         /* Workaround: CRC size should not be included in byte statistics,
2359          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2360          */
2361         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2362                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2363
2364         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2365                             pf->offset_loaded, &os->eth.rx_discards,
2366                             &ns->eth.rx_discards);
2367         /* GLPRT_REPC not supported */
2368         /* GLPRT_RMPC not supported */
2369         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2370                             pf->offset_loaded,
2371                             &os->eth.rx_unknown_protocol,
2372                             &ns->eth.rx_unknown_protocol);
2373         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2374                             I40E_GLPRT_GOTCL(hw->port),
2375                             pf->offset_loaded, &os->eth.tx_bytes,
2376                             &ns->eth.tx_bytes);
2377         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2378                             I40E_GLPRT_UPTCL(hw->port),
2379                             pf->offset_loaded, &os->eth.tx_unicast,
2380                             &ns->eth.tx_unicast);
2381         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2382                             I40E_GLPRT_MPTCL(hw->port),
2383                             pf->offset_loaded, &os->eth.tx_multicast,
2384                             &ns->eth.tx_multicast);
2385         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2386                             I40E_GLPRT_BPTCL(hw->port),
2387                             pf->offset_loaded, &os->eth.tx_broadcast,
2388                             &ns->eth.tx_broadcast);
2389         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2390                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2391         /* GLPRT_TEPC not supported */
2392
2393         /* additional port specific stats */
2394         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2395                             pf->offset_loaded, &os->tx_dropped_link_down,
2396                             &ns->tx_dropped_link_down);
2397         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2398                             pf->offset_loaded, &os->crc_errors,
2399                             &ns->crc_errors);
2400         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2401                             pf->offset_loaded, &os->illegal_bytes,
2402                             &ns->illegal_bytes);
2403         /* GLPRT_ERRBC not supported */
2404         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2405                             pf->offset_loaded, &os->mac_local_faults,
2406                             &ns->mac_local_faults);
2407         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2408                             pf->offset_loaded, &os->mac_remote_faults,
2409                             &ns->mac_remote_faults);
2410         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2411                             pf->offset_loaded, &os->rx_length_errors,
2412                             &ns->rx_length_errors);
2413         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2414                             pf->offset_loaded, &os->link_xon_rx,
2415                             &ns->link_xon_rx);
2416         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2417                             pf->offset_loaded, &os->link_xoff_rx,
2418                             &ns->link_xoff_rx);
2419         for (i = 0; i < 8; i++) {
2420                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2421                                     pf->offset_loaded,
2422                                     &os->priority_xon_rx[i],
2423                                     &ns->priority_xon_rx[i]);
2424                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2425                                     pf->offset_loaded,
2426                                     &os->priority_xoff_rx[i],
2427                                     &ns->priority_xoff_rx[i]);
2428         }
2429         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2430                             pf->offset_loaded, &os->link_xon_tx,
2431                             &ns->link_xon_tx);
2432         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2433                             pf->offset_loaded, &os->link_xoff_tx,
2434                             &ns->link_xoff_tx);
2435         for (i = 0; i < 8; i++) {
2436                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2437                                     pf->offset_loaded,
2438                                     &os->priority_xon_tx[i],
2439                                     &ns->priority_xon_tx[i]);
2440                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2441                                     pf->offset_loaded,
2442                                     &os->priority_xoff_tx[i],
2443                                     &ns->priority_xoff_tx[i]);
2444                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2445                                     pf->offset_loaded,
2446                                     &os->priority_xon_2_xoff[i],
2447                                     &ns->priority_xon_2_xoff[i]);
2448         }
2449         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2450                             I40E_GLPRT_PRC64L(hw->port),
2451                             pf->offset_loaded, &os->rx_size_64,
2452                             &ns->rx_size_64);
2453         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2454                             I40E_GLPRT_PRC127L(hw->port),
2455                             pf->offset_loaded, &os->rx_size_127,
2456                             &ns->rx_size_127);
2457         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2458                             I40E_GLPRT_PRC255L(hw->port),
2459                             pf->offset_loaded, &os->rx_size_255,
2460                             &ns->rx_size_255);
2461         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2462                             I40E_GLPRT_PRC511L(hw->port),
2463                             pf->offset_loaded, &os->rx_size_511,
2464                             &ns->rx_size_511);
2465         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2466                             I40E_GLPRT_PRC1023L(hw->port),
2467                             pf->offset_loaded, &os->rx_size_1023,
2468                             &ns->rx_size_1023);
2469         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2470                             I40E_GLPRT_PRC1522L(hw->port),
2471                             pf->offset_loaded, &os->rx_size_1522,
2472                             &ns->rx_size_1522);
2473         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2474                             I40E_GLPRT_PRC9522L(hw->port),
2475                             pf->offset_loaded, &os->rx_size_big,
2476                             &ns->rx_size_big);
2477         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2478                             pf->offset_loaded, &os->rx_undersize,
2479                             &ns->rx_undersize);
2480         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2481                             pf->offset_loaded, &os->rx_fragments,
2482                             &ns->rx_fragments);
2483         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2484                             pf->offset_loaded, &os->rx_oversize,
2485                             &ns->rx_oversize);
2486         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2487                             pf->offset_loaded, &os->rx_jabber,
2488                             &ns->rx_jabber);
2489         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2490                             I40E_GLPRT_PTC64L(hw->port),
2491                             pf->offset_loaded, &os->tx_size_64,
2492                             &ns->tx_size_64);
2493         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2494                             I40E_GLPRT_PTC127L(hw->port),
2495                             pf->offset_loaded, &os->tx_size_127,
2496                             &ns->tx_size_127);
2497         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2498                             I40E_GLPRT_PTC255L(hw->port),
2499                             pf->offset_loaded, &os->tx_size_255,
2500                             &ns->tx_size_255);
2501         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2502                             I40E_GLPRT_PTC511L(hw->port),
2503                             pf->offset_loaded, &os->tx_size_511,
2504                             &ns->tx_size_511);
2505         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2506                             I40E_GLPRT_PTC1023L(hw->port),
2507                             pf->offset_loaded, &os->tx_size_1023,
2508                             &ns->tx_size_1023);
2509         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2510                             I40E_GLPRT_PTC1522L(hw->port),
2511                             pf->offset_loaded, &os->tx_size_1522,
2512                             &ns->tx_size_1522);
2513         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2514                             I40E_GLPRT_PTC9522L(hw->port),
2515                             pf->offset_loaded, &os->tx_size_big,
2516                             &ns->tx_size_big);
2517         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2518                            pf->offset_loaded,
2519                            &os->fd_sb_match, &ns->fd_sb_match);
2520         /* GLPRT_MSPDC not supported */
2521         /* GLPRT_XEC not supported */
2522
2523         pf->offset_loaded = true;
2524
2525         if (pf->main_vsi)
2526                 i40e_update_vsi_stats(pf->main_vsi);
2527 }
2528
2529 /* Get all statistics of a port */
2530 static void
2531 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2532 {
2533         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2534         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2535         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2536         unsigned i;
2537
2538         /* call read registers - updates values, now write them to struct */
2539         i40e_read_stats_registers(pf, hw);
2540
2541         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2542                         pf->main_vsi->eth_stats.rx_multicast +
2543                         pf->main_vsi->eth_stats.rx_broadcast -
2544                         pf->main_vsi->eth_stats.rx_discards;
2545         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2546                         pf->main_vsi->eth_stats.tx_multicast +
2547                         pf->main_vsi->eth_stats.tx_broadcast;
2548         stats->ibytes   = ns->eth.rx_bytes;
2549         stats->obytes   = ns->eth.tx_bytes;
2550         stats->oerrors  = ns->eth.tx_errors +
2551                         pf->main_vsi->eth_stats.tx_errors;
2552
2553         /* Rx Errors */
2554         stats->imissed  = ns->eth.rx_discards +
2555                         pf->main_vsi->eth_stats.rx_discards;
2556         stats->ierrors  = ns->crc_errors +
2557                         ns->rx_length_errors + ns->rx_undersize +
2558                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2559
2560         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2561         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2562         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2563         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2564         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2565         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2566         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2567                     ns->eth.rx_unknown_protocol);
2568         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2569         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2570         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2571         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2572         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2573         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2574
2575         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2576                     ns->tx_dropped_link_down);
2577         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2578         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2579                     ns->illegal_bytes);
2580         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2581         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2582                     ns->mac_local_faults);
2583         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2584                     ns->mac_remote_faults);
2585         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2586                     ns->rx_length_errors);
2587         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2588         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2589         for (i = 0; i < 8; i++) {
2590                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2591                                 i, ns->priority_xon_rx[i]);
2592                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2593                                 i, ns->priority_xoff_rx[i]);
2594         }
2595         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2596         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2597         for (i = 0; i < 8; i++) {
2598                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2599                                 i, ns->priority_xon_tx[i]);
2600                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2601                                 i, ns->priority_xoff_tx[i]);
2602                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2603                                 i, ns->priority_xon_2_xoff[i]);
2604         }
2605         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2606         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2607         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2608         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2609         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2610         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2611         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2612         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2613         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2614         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2615         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2616         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2617         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2618         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2619         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2620         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2621         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2622         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2623         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2624                         ns->mac_short_packet_dropped);
2625         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2626                     ns->checksum_error);
2627         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2628         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2629 }
2630
2631 /* Reset the statistics */
2632 static void
2633 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2634 {
2635         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2636         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2637
2638         /* Mark PF and VSI stats to update the offset, aka "reset" */
2639         pf->offset_loaded = false;
2640         if (pf->main_vsi)
2641                 pf->main_vsi->offset_loaded = false;
2642
2643         /* read the stats, reading current register values into offset */
2644         i40e_read_stats_registers(pf, hw);
2645 }
2646
2647 static uint32_t
2648 i40e_xstats_calc_num(void)
2649 {
2650         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2651                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2652                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2653 }
2654
2655 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2656                                      struct rte_eth_xstat_name *xstats_names,
2657                                      __rte_unused unsigned limit)
2658 {
2659         unsigned count = 0;
2660         unsigned i, prio;
2661
2662         if (xstats_names == NULL)
2663                 return i40e_xstats_calc_num();
2664
2665         /* Note: limit checked in rte_eth_xstats_names() */
2666
2667         /* Get stats from i40e_eth_stats struct */
2668         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2669                 snprintf(xstats_names[count].name,
2670                          sizeof(xstats_names[count].name),
2671                          "%s", rte_i40e_stats_strings[i].name);
2672                 count++;
2673         }
2674
2675         /* Get individiual stats from i40e_hw_port struct */
2676         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2677                 snprintf(xstats_names[count].name,
2678                         sizeof(xstats_names[count].name),
2679                          "%s", rte_i40e_hw_port_strings[i].name);
2680                 count++;
2681         }
2682
2683         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2684                 for (prio = 0; prio < 8; prio++) {
2685                         snprintf(xstats_names[count].name,
2686                                  sizeof(xstats_names[count].name),
2687                                  "rx_priority%u_%s", prio,
2688                                  rte_i40e_rxq_prio_strings[i].name);
2689                         count++;
2690                 }
2691         }
2692
2693         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2694                 for (prio = 0; prio < 8; prio++) {
2695                         snprintf(xstats_names[count].name,
2696                                  sizeof(xstats_names[count].name),
2697                                  "tx_priority%u_%s", prio,
2698                                  rte_i40e_txq_prio_strings[i].name);
2699                         count++;
2700                 }
2701         }
2702         return count;
2703 }
2704
2705 static int
2706 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2707                     unsigned n)
2708 {
2709         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2710         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2711         unsigned i, count, prio;
2712         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2713
2714         count = i40e_xstats_calc_num();
2715         if (n < count)
2716                 return count;
2717
2718         i40e_read_stats_registers(pf, hw);
2719
2720         if (xstats == NULL)
2721                 return 0;
2722
2723         count = 0;
2724
2725         /* Get stats from i40e_eth_stats struct */
2726         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2727                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2728                         rte_i40e_stats_strings[i].offset);
2729                 xstats[count].id = count;
2730                 count++;
2731         }
2732
2733         /* Get individiual stats from i40e_hw_port struct */
2734         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2735                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2736                         rte_i40e_hw_port_strings[i].offset);
2737                 xstats[count].id = count;
2738                 count++;
2739         }
2740
2741         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2742                 for (prio = 0; prio < 8; prio++) {
2743                         xstats[count].value =
2744                                 *(uint64_t *)(((char *)hw_stats) +
2745                                 rte_i40e_rxq_prio_strings[i].offset +
2746                                 (sizeof(uint64_t) * prio));
2747                         xstats[count].id = count;
2748                         count++;
2749                 }
2750         }
2751
2752         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2753                 for (prio = 0; prio < 8; prio++) {
2754                         xstats[count].value =
2755                                 *(uint64_t *)(((char *)hw_stats) +
2756                                 rte_i40e_txq_prio_strings[i].offset +
2757                                 (sizeof(uint64_t) * prio));
2758                         xstats[count].id = count;
2759                         count++;
2760                 }
2761         }
2762
2763         return count;
2764 }
2765
2766 static int
2767 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2768                                  __rte_unused uint16_t queue_id,
2769                                  __rte_unused uint8_t stat_idx,
2770                                  __rte_unused uint8_t is_rx)
2771 {
2772         PMD_INIT_FUNC_TRACE();
2773
2774         return -ENOSYS;
2775 }
2776
2777 static int
2778 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2779 {
2780         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2781         u32 full_ver;
2782         u8 ver, patch;
2783         u16 build;
2784         int ret;
2785
2786         full_ver = hw->nvm.oem_ver;
2787         ver = (u8)(full_ver >> 24);
2788         build = (u16)((full_ver >> 8) & 0xffff);
2789         patch = (u8)(full_ver & 0xff);
2790
2791         ret = snprintf(fw_version, fw_size,
2792                  "%d.%d%d 0x%08x %d.%d.%d",
2793                  ((hw->nvm.version >> 12) & 0xf),
2794                  ((hw->nvm.version >> 4) & 0xff),
2795                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2796                  ver, build, patch);
2797
2798         ret += 1; /* add the size of '\0' */
2799         if (fw_size < (u32)ret)
2800                 return ret;
2801         else
2802                 return 0;
2803 }
2804
2805 static void
2806 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2807 {
2808         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2809         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2810         struct i40e_vsi *vsi = pf->main_vsi;
2811         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2812
2813         dev_info->pci_dev = pci_dev;
2814         dev_info->max_rx_queues = vsi->nb_qps;
2815         dev_info->max_tx_queues = vsi->nb_qps;
2816         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2817         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2818         dev_info->max_mac_addrs = vsi->max_macaddrs;
2819         dev_info->max_vfs = pci_dev->max_vfs;
2820         dev_info->rx_offload_capa =
2821                 DEV_RX_OFFLOAD_VLAN_STRIP |
2822                 DEV_RX_OFFLOAD_QINQ_STRIP |
2823                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2824                 DEV_RX_OFFLOAD_UDP_CKSUM |
2825                 DEV_RX_OFFLOAD_TCP_CKSUM;
2826         dev_info->tx_offload_capa =
2827                 DEV_TX_OFFLOAD_VLAN_INSERT |
2828                 DEV_TX_OFFLOAD_QINQ_INSERT |
2829                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2830                 DEV_TX_OFFLOAD_UDP_CKSUM |
2831                 DEV_TX_OFFLOAD_TCP_CKSUM |
2832                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2833                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2834                 DEV_TX_OFFLOAD_TCP_TSO |
2835                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2836                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2837                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2838                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2839         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2840                                                 sizeof(uint32_t);
2841         dev_info->reta_size = pf->hash_lut_size;
2842         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2843
2844         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2845                 .rx_thresh = {
2846                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2847                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2848                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2849                 },
2850                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2851                 .rx_drop_en = 0,
2852         };
2853
2854         dev_info->default_txconf = (struct rte_eth_txconf) {
2855                 .tx_thresh = {
2856                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2857                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2858                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2859                 },
2860                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2861                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2862                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2863                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2864         };
2865
2866         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2867                 .nb_max = I40E_MAX_RING_DESC,
2868                 .nb_min = I40E_MIN_RING_DESC,
2869                 .nb_align = I40E_ALIGN_RING_DESC,
2870         };
2871
2872         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2873                 .nb_max = I40E_MAX_RING_DESC,
2874                 .nb_min = I40E_MIN_RING_DESC,
2875                 .nb_align = I40E_ALIGN_RING_DESC,
2876                 .nb_seg_max = I40E_TX_MAX_SEG,
2877                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2878         };
2879
2880         if (pf->flags & I40E_FLAG_VMDQ) {
2881                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2882                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2883                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2884                                                 pf->max_nb_vmdq_vsi;
2885                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2886                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2887                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2888         }
2889
2890         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2891                 /* For XL710 */
2892                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2893         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2894                 /* For XXV710 */
2895                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2896         else
2897                 /* For X710 */
2898                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2899 }
2900
2901 static int
2902 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2903 {
2904         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2905         struct i40e_vsi *vsi = pf->main_vsi;
2906         PMD_INIT_FUNC_TRACE();
2907
2908         if (on)
2909                 return i40e_vsi_add_vlan(vsi, vlan_id);
2910         else
2911                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2912 }
2913
2914 static int
2915 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2916                    enum rte_vlan_type vlan_type,
2917                    uint16_t tpid)
2918 {
2919         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2920         uint64_t reg_r = 0, reg_w = 0;
2921         uint16_t reg_id = 0;
2922         int ret = 0;
2923         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2924
2925         switch (vlan_type) {
2926         case ETH_VLAN_TYPE_OUTER:
2927                 if (qinq)
2928                         reg_id = 2;
2929                 else
2930                         reg_id = 3;
2931                 break;
2932         case ETH_VLAN_TYPE_INNER:
2933                 if (qinq)
2934                         reg_id = 3;
2935                 else {
2936                         ret = -EINVAL;
2937                         PMD_DRV_LOG(ERR,
2938                                 "Unsupported vlan type in single vlan.\n");
2939                         return ret;
2940                 }
2941                 break;
2942         default:
2943                 ret = -EINVAL;
2944                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2945                 return ret;
2946         }
2947         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2948                                           &reg_r, NULL);
2949         if (ret != I40E_SUCCESS) {
2950                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2951                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2952                 ret = -EIO;
2953                 return ret;
2954         }
2955         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2956                     "0x%08"PRIx64"", reg_id, reg_r);
2957
2958         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2959         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2960         if (reg_r == reg_w) {
2961                 ret = 0;
2962                 PMD_DRV_LOG(DEBUG, "No need to write");
2963                 return ret;
2964         }
2965
2966         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2967                                            reg_w, NULL);
2968         if (ret != I40E_SUCCESS) {
2969                 ret = -EIO;
2970                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2971                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2972                 return ret;
2973         }
2974         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2975                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2976
2977         return ret;
2978 }
2979
2980 static void
2981 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2982 {
2983         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2984         struct i40e_vsi *vsi = pf->main_vsi;
2985
2986         if (mask & ETH_VLAN_FILTER_MASK) {
2987                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2988                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2989                 else
2990                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2991         }
2992
2993         if (mask & ETH_VLAN_STRIP_MASK) {
2994                 /* Enable or disable VLAN stripping */
2995                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2996                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2997                 else
2998                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2999         }
3000
3001         if (mask & ETH_VLAN_EXTEND_MASK) {
3002                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3003                         i40e_vsi_config_double_vlan(vsi, TRUE);
3004                         /* Set global registers with default ether type value */
3005                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3006                                            ETHER_TYPE_VLAN);
3007                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3008                                            ETHER_TYPE_VLAN);
3009                 }
3010                 else
3011                         i40e_vsi_config_double_vlan(vsi, FALSE);
3012         }
3013 }
3014
3015 static void
3016 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3017                           __rte_unused uint16_t queue,
3018                           __rte_unused int on)
3019 {
3020         PMD_INIT_FUNC_TRACE();
3021 }
3022
3023 static int
3024 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3025 {
3026         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3027         struct i40e_vsi *vsi = pf->main_vsi;
3028         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3029         struct i40e_vsi_vlan_pvid_info info;
3030
3031         memset(&info, 0, sizeof(info));
3032         info.on = on;
3033         if (info.on)
3034                 info.config.pvid = pvid;
3035         else {
3036                 info.config.reject.tagged =
3037                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3038                 info.config.reject.untagged =
3039                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3040         }
3041
3042         return i40e_vsi_vlan_pvid_set(vsi, &info);
3043 }
3044
3045 static int
3046 i40e_dev_led_on(struct rte_eth_dev *dev)
3047 {
3048         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3049         uint32_t mode = i40e_led_get(hw);
3050
3051         if (mode == 0)
3052                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3053
3054         return 0;
3055 }
3056
3057 static int
3058 i40e_dev_led_off(struct rte_eth_dev *dev)
3059 {
3060         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3061         uint32_t mode = i40e_led_get(hw);
3062
3063         if (mode != 0)
3064                 i40e_led_set(hw, 0, false);
3065
3066         return 0;
3067 }
3068
3069 static int
3070 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3071 {
3072         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3073         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3074
3075         fc_conf->pause_time = pf->fc_conf.pause_time;
3076         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3077         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3078
3079          /* Return current mode according to actual setting*/
3080         switch (hw->fc.current_mode) {
3081         case I40E_FC_FULL:
3082                 fc_conf->mode = RTE_FC_FULL;
3083                 break;
3084         case I40E_FC_TX_PAUSE:
3085                 fc_conf->mode = RTE_FC_TX_PAUSE;
3086                 break;
3087         case I40E_FC_RX_PAUSE:
3088                 fc_conf->mode = RTE_FC_RX_PAUSE;
3089                 break;
3090         case I40E_FC_NONE:
3091         default:
3092                 fc_conf->mode = RTE_FC_NONE;
3093         };
3094
3095         return 0;
3096 }
3097
3098 static int
3099 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3100 {
3101         uint32_t mflcn_reg, fctrl_reg, reg;
3102         uint32_t max_high_water;
3103         uint8_t i, aq_failure;
3104         int err;
3105         struct i40e_hw *hw;
3106         struct i40e_pf *pf;
3107         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3108                 [RTE_FC_NONE] = I40E_FC_NONE,
3109                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3110                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3111                 [RTE_FC_FULL] = I40E_FC_FULL
3112         };
3113
3114         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3115
3116         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3117         if ((fc_conf->high_water > max_high_water) ||
3118                         (fc_conf->high_water < fc_conf->low_water)) {
3119                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
3120                         "High_water must <= %d.", max_high_water);
3121                 return -EINVAL;
3122         }
3123
3124         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3125         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3126         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3127
3128         pf->fc_conf.pause_time = fc_conf->pause_time;
3129         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3130         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3131
3132         PMD_INIT_FUNC_TRACE();
3133
3134         /* All the link flow control related enable/disable register
3135          * configuration is handle by the F/W
3136          */
3137         err = i40e_set_fc(hw, &aq_failure, true);
3138         if (err < 0)
3139                 return -ENOSYS;
3140
3141         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3142                 /* Configure flow control refresh threshold,
3143                  * the value for stat_tx_pause_refresh_timer[8]
3144                  * is used for global pause operation.
3145                  */
3146
3147                 I40E_WRITE_REG(hw,
3148                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3149                                pf->fc_conf.pause_time);
3150
3151                 /* configure the timer value included in transmitted pause
3152                  * frame,
3153                  * the value for stat_tx_pause_quanta[8] is used for global
3154                  * pause operation
3155                  */
3156                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3157                                pf->fc_conf.pause_time);
3158
3159                 fctrl_reg = I40E_READ_REG(hw,
3160                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3161
3162                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3163                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3164                 else
3165                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3166
3167                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3168                                fctrl_reg);
3169         } else {
3170                 /* Configure pause time (2 TCs per register) */
3171                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3172                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3173                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3174
3175                 /* Configure flow control refresh threshold value */
3176                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3177                                pf->fc_conf.pause_time / 2);
3178
3179                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3180
3181                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3182                  *depending on configuration
3183                  */
3184                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3185                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3186                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3187                 } else {
3188                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3189                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3190                 }
3191
3192                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3193         }
3194
3195         /* config the water marker both based on the packets and bytes */
3196         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3197                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3198                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3199         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3200                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3201                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3202         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3203                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3204                        << I40E_KILOSHIFT);
3205         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3206                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3207                        << I40E_KILOSHIFT);
3208
3209         I40E_WRITE_FLUSH(hw);
3210
3211         return 0;
3212 }
3213
3214 static int
3215 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3216                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3217 {
3218         PMD_INIT_FUNC_TRACE();
3219
3220         return -ENOSYS;
3221 }
3222
3223 /* Add a MAC address, and update filters */
3224 static void
3225 i40e_macaddr_add(struct rte_eth_dev *dev,
3226                  struct ether_addr *mac_addr,
3227                  __rte_unused uint32_t index,
3228                  uint32_t pool)
3229 {
3230         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3231         struct i40e_mac_filter_info mac_filter;
3232         struct i40e_vsi *vsi;
3233         int ret;
3234
3235         /* If VMDQ not enabled or configured, return */
3236         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3237                           !pf->nb_cfg_vmdq_vsi)) {
3238                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3239                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3240                         pool);
3241                 return;
3242         }
3243
3244         if (pool > pf->nb_cfg_vmdq_vsi) {
3245                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3246                                 pool, pf->nb_cfg_vmdq_vsi);
3247                 return;
3248         }
3249
3250         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3251         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3252                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3253         else
3254                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3255
3256         if (pool == 0)
3257                 vsi = pf->main_vsi;
3258         else
3259                 vsi = pf->vmdq[pool - 1].vsi;
3260
3261         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3262         if (ret != I40E_SUCCESS) {
3263                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3264                 return;
3265         }
3266 }
3267
3268 /* Remove a MAC address, and update filters */
3269 static void
3270 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3271 {
3272         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3273         struct i40e_vsi *vsi;
3274         struct rte_eth_dev_data *data = dev->data;
3275         struct ether_addr *macaddr;
3276         int ret;
3277         uint32_t i;
3278         uint64_t pool_sel;
3279
3280         macaddr = &(data->mac_addrs[index]);
3281
3282         pool_sel = dev->data->mac_pool_sel[index];
3283
3284         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3285                 if (pool_sel & (1ULL << i)) {
3286                         if (i == 0)
3287                                 vsi = pf->main_vsi;
3288                         else {
3289                                 /* No VMDQ pool enabled or configured */
3290                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3291                                         (i > pf->nb_cfg_vmdq_vsi)) {
3292                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3293                                                         "/configured");
3294                                         return;
3295                                 }
3296                                 vsi = pf->vmdq[i - 1].vsi;
3297                         }
3298                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3299
3300                         if (ret) {
3301                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3302                                 return;
3303                         }
3304                 }
3305         }
3306 }
3307
3308 /* Set perfect match or hash match of MAC and VLAN for a VF */
3309 static int
3310 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3311                  struct rte_eth_mac_filter *filter,
3312                  bool add)
3313 {
3314         struct i40e_hw *hw;
3315         struct i40e_mac_filter_info mac_filter;
3316         struct ether_addr old_mac;
3317         struct ether_addr *new_mac;
3318         struct i40e_pf_vf *vf = NULL;
3319         uint16_t vf_id;
3320         int ret;
3321
3322         if (pf == NULL) {
3323                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3324                 return -EINVAL;
3325         }
3326         hw = I40E_PF_TO_HW(pf);
3327
3328         if (filter == NULL) {
3329                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3330                 return -EINVAL;
3331         }
3332
3333         new_mac = &filter->mac_addr;
3334
3335         if (is_zero_ether_addr(new_mac)) {
3336                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3337                 return -EINVAL;
3338         }
3339
3340         vf_id = filter->dst_id;
3341
3342         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3343                 PMD_DRV_LOG(ERR, "Invalid argument.");
3344                 return -EINVAL;
3345         }
3346         vf = &pf->vfs[vf_id];
3347
3348         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3349                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3350                 return -EINVAL;
3351         }
3352
3353         if (add) {
3354                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3355                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3356                                 ETHER_ADDR_LEN);
3357                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3358                                  ETHER_ADDR_LEN);
3359
3360                 mac_filter.filter_type = filter->filter_type;
3361                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3362                 if (ret != I40E_SUCCESS) {
3363                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3364                         return -1;
3365                 }
3366                 ether_addr_copy(new_mac, &pf->dev_addr);
3367         } else {
3368                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3369                                 ETHER_ADDR_LEN);
3370                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3371                 if (ret != I40E_SUCCESS) {
3372                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3373                         return -1;
3374                 }
3375
3376                 /* Clear device address as it has been removed */
3377                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3378                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3379         }
3380
3381         return 0;
3382 }
3383
3384 /* MAC filter handle */
3385 static int
3386 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3387                 void *arg)
3388 {
3389         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3390         struct rte_eth_mac_filter *filter;
3391         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3392         int ret = I40E_NOT_SUPPORTED;
3393
3394         filter = (struct rte_eth_mac_filter *)(arg);
3395
3396         switch (filter_op) {
3397         case RTE_ETH_FILTER_NOP:
3398                 ret = I40E_SUCCESS;
3399                 break;
3400         case RTE_ETH_FILTER_ADD:
3401                 i40e_pf_disable_irq0(hw);
3402                 if (filter->is_vf)
3403                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3404                 i40e_pf_enable_irq0(hw);
3405                 break;
3406         case RTE_ETH_FILTER_DELETE:
3407                 i40e_pf_disable_irq0(hw);
3408                 if (filter->is_vf)
3409                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3410                 i40e_pf_enable_irq0(hw);
3411                 break;
3412         default:
3413                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3414                 ret = I40E_ERR_PARAM;
3415                 break;
3416         }
3417
3418         return ret;
3419 }
3420
3421 static int
3422 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3423 {
3424         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3425         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3426         int ret;
3427
3428         if (!lut)
3429                 return -EINVAL;
3430
3431         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3432                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3433                                           lut, lut_size);
3434                 if (ret) {
3435                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3436                         return ret;
3437                 }
3438         } else {
3439                 uint32_t *lut_dw = (uint32_t *)lut;
3440                 uint16_t i, lut_size_dw = lut_size / 4;
3441
3442                 for (i = 0; i < lut_size_dw; i++)
3443                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3444         }
3445
3446         return 0;
3447 }
3448
3449 static int
3450 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3451 {
3452         struct i40e_pf *pf;
3453         struct i40e_hw *hw;
3454         int ret;
3455
3456         if (!vsi || !lut)
3457                 return -EINVAL;
3458
3459         pf = I40E_VSI_TO_PF(vsi);
3460         hw = I40E_VSI_TO_HW(vsi);
3461
3462         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3463                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3464                                           lut, lut_size);
3465                 if (ret) {
3466                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3467                         return ret;
3468                 }
3469         } else {
3470                 uint32_t *lut_dw = (uint32_t *)lut;
3471                 uint16_t i, lut_size_dw = lut_size / 4;
3472
3473                 for (i = 0; i < lut_size_dw; i++)
3474                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3475                 I40E_WRITE_FLUSH(hw);
3476         }
3477
3478         return 0;
3479 }
3480
3481 static int
3482 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3483                          struct rte_eth_rss_reta_entry64 *reta_conf,
3484                          uint16_t reta_size)
3485 {
3486         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3487         uint16_t i, lut_size = pf->hash_lut_size;
3488         uint16_t idx, shift;
3489         uint8_t *lut;
3490         int ret;
3491
3492         if (reta_size != lut_size ||
3493                 reta_size > ETH_RSS_RETA_SIZE_512) {
3494                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3495                         "(%d) doesn't match the number hardware can supported "
3496                                         "(%d)\n", reta_size, lut_size);
3497                 return -EINVAL;
3498         }
3499
3500         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3501         if (!lut) {
3502                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3503                 return -ENOMEM;
3504         }
3505         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3506         if (ret)
3507                 goto out;
3508         for (i = 0; i < reta_size; i++) {
3509                 idx = i / RTE_RETA_GROUP_SIZE;
3510                 shift = i % RTE_RETA_GROUP_SIZE;
3511                 if (reta_conf[idx].mask & (1ULL << shift))
3512                         lut[i] = reta_conf[idx].reta[shift];
3513         }
3514         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3515
3516 out:
3517         rte_free(lut);
3518
3519         return ret;
3520 }
3521
3522 static int
3523 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3524                         struct rte_eth_rss_reta_entry64 *reta_conf,
3525                         uint16_t reta_size)
3526 {
3527         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3528         uint16_t i, lut_size = pf->hash_lut_size;
3529         uint16_t idx, shift;
3530         uint8_t *lut;
3531         int ret;
3532
3533         if (reta_size != lut_size ||
3534                 reta_size > ETH_RSS_RETA_SIZE_512) {
3535                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3536                         "(%d) doesn't match the number hardware can supported "
3537                                         "(%d)\n", reta_size, lut_size);
3538                 return -EINVAL;
3539         }
3540
3541         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3542         if (!lut) {
3543                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3544                 return -ENOMEM;
3545         }
3546
3547         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3548         if (ret)
3549                 goto out;
3550         for (i = 0; i < reta_size; i++) {
3551                 idx = i / RTE_RETA_GROUP_SIZE;
3552                 shift = i % RTE_RETA_GROUP_SIZE;
3553                 if (reta_conf[idx].mask & (1ULL << shift))
3554                         reta_conf[idx].reta[shift] = lut[i];
3555         }
3556
3557 out:
3558         rte_free(lut);
3559
3560         return ret;
3561 }
3562
3563 /**
3564  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3565  * @hw:   pointer to the HW structure
3566  * @mem:  pointer to mem struct to fill out
3567  * @size: size of memory requested
3568  * @alignment: what to align the allocation to
3569  **/
3570 enum i40e_status_code
3571 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3572                         struct i40e_dma_mem *mem,
3573                         u64 size,
3574                         u32 alignment)
3575 {
3576         const struct rte_memzone *mz = NULL;
3577         char z_name[RTE_MEMZONE_NAMESIZE];
3578
3579         if (!mem)
3580                 return I40E_ERR_PARAM;
3581
3582         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3583         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3584                                          alignment, RTE_PGSIZE_2M);
3585         if (!mz)
3586                 return I40E_ERR_NO_MEMORY;
3587
3588         mem->size = size;
3589         mem->va = mz->addr;
3590         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3591         mem->zone = (const void *)mz;
3592         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3593                     "%"PRIu64, mz->name, mem->pa);
3594
3595         return I40E_SUCCESS;
3596 }
3597
3598 /**
3599  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3600  * @hw:   pointer to the HW structure
3601  * @mem:  ptr to mem struct to free
3602  **/
3603 enum i40e_status_code
3604 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3605                     struct i40e_dma_mem *mem)
3606 {
3607         if (!mem)
3608                 return I40E_ERR_PARAM;
3609
3610         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3611                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3612                     mem->pa);
3613         rte_memzone_free((const struct rte_memzone *)mem->zone);
3614         mem->zone = NULL;
3615         mem->va = NULL;
3616         mem->pa = (u64)0;
3617
3618         return I40E_SUCCESS;
3619 }
3620
3621 /**
3622  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3623  * @hw:   pointer to the HW structure
3624  * @mem:  pointer to mem struct to fill out
3625  * @size: size of memory requested
3626  **/
3627 enum i40e_status_code
3628 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3629                          struct i40e_virt_mem *mem,
3630                          u32 size)
3631 {
3632         if (!mem)
3633                 return I40E_ERR_PARAM;
3634
3635         mem->size = size;
3636         mem->va = rte_zmalloc("i40e", size, 0);
3637
3638         if (mem->va)
3639                 return I40E_SUCCESS;
3640         else
3641                 return I40E_ERR_NO_MEMORY;
3642 }
3643
3644 /**
3645  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3646  * @hw:   pointer to the HW structure
3647  * @mem:  pointer to mem struct to free
3648  **/
3649 enum i40e_status_code
3650 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3651                      struct i40e_virt_mem *mem)
3652 {
3653         if (!mem)
3654                 return I40E_ERR_PARAM;
3655
3656         rte_free(mem->va);
3657         mem->va = NULL;
3658
3659         return I40E_SUCCESS;
3660 }
3661
3662 void
3663 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3664 {
3665         rte_spinlock_init(&sp->spinlock);
3666 }
3667
3668 void
3669 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3670 {
3671         rte_spinlock_lock(&sp->spinlock);
3672 }
3673
3674 void
3675 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3676 {
3677         rte_spinlock_unlock(&sp->spinlock);
3678 }
3679
3680 void
3681 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3682 {
3683         return;
3684 }
3685
3686 /**
3687  * Get the hardware capabilities, which will be parsed
3688  * and saved into struct i40e_hw.
3689  */
3690 static int
3691 i40e_get_cap(struct i40e_hw *hw)
3692 {
3693         struct i40e_aqc_list_capabilities_element_resp *buf;
3694         uint16_t len, size = 0;
3695         int ret;
3696
3697         /* Calculate a huge enough buff for saving response data temporarily */
3698         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3699                                                 I40E_MAX_CAP_ELE_NUM;
3700         buf = rte_zmalloc("i40e", len, 0);
3701         if (!buf) {
3702                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3703                 return I40E_ERR_NO_MEMORY;
3704         }
3705
3706         /* Get, parse the capabilities and save it to hw */
3707         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3708                         i40e_aqc_opc_list_func_capabilities, NULL);
3709         if (ret != I40E_SUCCESS)
3710                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3711
3712         /* Free the temporary buffer after being used */
3713         rte_free(buf);
3714
3715         return ret;
3716 }
3717
3718 static int
3719 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3720 {
3721         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3722         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3723         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3724         uint16_t qp_count = 0, vsi_count = 0;
3725
3726         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3727                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3728                 return -EINVAL;
3729         }
3730         /* Add the parameter init for LFC */
3731         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3732         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3733         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3734
3735         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3736         pf->max_num_vsi = hw->func_caps.num_vsis;
3737         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3738         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3739         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3740
3741         /* FDir queue/VSI allocation */
3742         pf->fdir_qp_offset = 0;
3743         if (hw->func_caps.fd) {
3744                 pf->flags |= I40E_FLAG_FDIR;
3745                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3746         } else {
3747                 pf->fdir_nb_qps = 0;
3748         }
3749         qp_count += pf->fdir_nb_qps;
3750         vsi_count += 1;
3751
3752         /* LAN queue/VSI allocation */
3753         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3754         if (!hw->func_caps.rss) {
3755                 pf->lan_nb_qps = 1;
3756         } else {
3757                 pf->flags |= I40E_FLAG_RSS;
3758                 if (hw->mac.type == I40E_MAC_X722)
3759                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3760                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3761         }
3762         qp_count += pf->lan_nb_qps;
3763         vsi_count += 1;
3764
3765         /* VF queue/VSI allocation */
3766         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3767         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3768                 pf->flags |= I40E_FLAG_SRIOV;
3769                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3770                 pf->vf_num = pci_dev->max_vfs;
3771                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3772                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3773                             pf->vf_nb_qps * pf->vf_num);
3774         } else {
3775                 pf->vf_nb_qps = 0;
3776                 pf->vf_num = 0;
3777         }
3778         qp_count += pf->vf_nb_qps * pf->vf_num;
3779         vsi_count += pf->vf_num;
3780
3781         /* VMDq queue/VSI allocation */
3782         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3783         pf->vmdq_nb_qps = 0;
3784         pf->max_nb_vmdq_vsi = 0;
3785         if (hw->func_caps.vmdq) {
3786                 if (qp_count < hw->func_caps.num_tx_qp &&
3787                         vsi_count < hw->func_caps.num_vsis) {
3788                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3789                                 qp_count) / pf->vmdq_nb_qp_max;
3790
3791                         /* Limit the maximum number of VMDq vsi to the maximum
3792                          * ethdev can support
3793                          */
3794                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3795                                 hw->func_caps.num_vsis - vsi_count);
3796                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3797                                 ETH_64_POOLS);
3798                         if (pf->max_nb_vmdq_vsi) {
3799                                 pf->flags |= I40E_FLAG_VMDQ;
3800                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3801                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3802                                             "per VMDQ VSI, in total %u queues",
3803                                             pf->max_nb_vmdq_vsi,
3804                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3805                                             pf->max_nb_vmdq_vsi);
3806                         } else {
3807                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3808                                             "VMDq");
3809                         }
3810                 } else {
3811                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3812                 }
3813         }
3814         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3815         vsi_count += pf->max_nb_vmdq_vsi;
3816
3817         if (hw->func_caps.dcb)
3818                 pf->flags |= I40E_FLAG_DCB;
3819
3820         if (qp_count > hw->func_caps.num_tx_qp) {
3821                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3822                             "the hardware maximum %u", qp_count,
3823                             hw->func_caps.num_tx_qp);
3824                 return -EINVAL;
3825         }
3826         if (vsi_count > hw->func_caps.num_vsis) {
3827                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3828                             "the hardware maximum %u", vsi_count,
3829                             hw->func_caps.num_vsis);
3830                 return -EINVAL;
3831         }
3832
3833         return 0;
3834 }
3835
3836 static int
3837 i40e_pf_get_switch_config(struct i40e_pf *pf)
3838 {
3839         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3840         struct i40e_aqc_get_switch_config_resp *switch_config;
3841         struct i40e_aqc_switch_config_element_resp *element;
3842         uint16_t start_seid = 0, num_reported;
3843         int ret;
3844
3845         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3846                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3847         if (!switch_config) {
3848                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3849                 return -ENOMEM;
3850         }
3851
3852         /* Get the switch configurations */
3853         ret = i40e_aq_get_switch_config(hw, switch_config,
3854                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3855         if (ret != I40E_SUCCESS) {
3856                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3857                 goto fail;
3858         }
3859         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3860         if (num_reported != 1) { /* The number should be 1 */
3861                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3862                 goto fail;
3863         }
3864
3865         /* Parse the switch configuration elements */
3866         element = &(switch_config->element[0]);
3867         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3868                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3869                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3870         } else
3871                 PMD_DRV_LOG(INFO, "Unknown element type");
3872
3873 fail:
3874         rte_free(switch_config);
3875
3876         return ret;
3877 }
3878
3879 static int
3880 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3881                         uint32_t num)
3882 {
3883         struct pool_entry *entry;
3884
3885         if (pool == NULL || num == 0)
3886                 return -EINVAL;
3887
3888         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3889         if (entry == NULL) {
3890                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3891                 return -ENOMEM;
3892         }
3893
3894         /* queue heap initialize */
3895         pool->num_free = num;
3896         pool->num_alloc = 0;
3897         pool->base = base;
3898         LIST_INIT(&pool->alloc_list);
3899         LIST_INIT(&pool->free_list);
3900
3901         /* Initialize element  */
3902         entry->base = 0;
3903         entry->len = num;
3904
3905         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3906         return 0;
3907 }
3908
3909 static void
3910 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3911 {
3912         struct pool_entry *entry, *next_entry;
3913
3914         if (pool == NULL)
3915                 return;
3916
3917         for (entry = LIST_FIRST(&pool->alloc_list);
3918                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3919                         entry = next_entry) {
3920                 LIST_REMOVE(entry, next);
3921                 rte_free(entry);
3922         }
3923
3924         for (entry = LIST_FIRST(&pool->free_list);
3925                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3926                         entry = next_entry) {
3927                 LIST_REMOVE(entry, next);
3928                 rte_free(entry);
3929         }
3930
3931         pool->num_free = 0;
3932         pool->num_alloc = 0;
3933         pool->base = 0;
3934         LIST_INIT(&pool->alloc_list);
3935         LIST_INIT(&pool->free_list);
3936 }
3937
3938 static int
3939 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3940                        uint32_t base)
3941 {
3942         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3943         uint32_t pool_offset;
3944         int insert;
3945
3946         if (pool == NULL) {
3947                 PMD_DRV_LOG(ERR, "Invalid parameter");
3948                 return -EINVAL;
3949         }
3950
3951         pool_offset = base - pool->base;
3952         /* Lookup in alloc list */
3953         LIST_FOREACH(entry, &pool->alloc_list, next) {
3954                 if (entry->base == pool_offset) {
3955                         valid_entry = entry;
3956                         LIST_REMOVE(entry, next);
3957                         break;
3958                 }
3959         }
3960
3961         /* Not find, return */
3962         if (valid_entry == NULL) {
3963                 PMD_DRV_LOG(ERR, "Failed to find entry");
3964                 return -EINVAL;
3965         }
3966
3967         /**
3968          * Found it, move it to free list  and try to merge.
3969          * In order to make merge easier, always sort it by qbase.
3970          * Find adjacent prev and last entries.
3971          */
3972         prev = next = NULL;
3973         LIST_FOREACH(entry, &pool->free_list, next) {
3974                 if (entry->base > valid_entry->base) {
3975                         next = entry;
3976                         break;
3977                 }
3978                 prev = entry;
3979         }
3980
3981         insert = 0;
3982         /* Try to merge with next one*/
3983         if (next != NULL) {
3984                 /* Merge with next one */
3985                 if (valid_entry->base + valid_entry->len == next->base) {
3986                         next->base = valid_entry->base;
3987                         next->len += valid_entry->len;
3988                         rte_free(valid_entry);
3989                         valid_entry = next;
3990                         insert = 1;
3991                 }
3992         }
3993
3994         if (prev != NULL) {
3995                 /* Merge with previous one */
3996                 if (prev->base + prev->len == valid_entry->base) {
3997                         prev->len += valid_entry->len;
3998                         /* If it merge with next one, remove next node */
3999                         if (insert == 1) {
4000                                 LIST_REMOVE(valid_entry, next);
4001                                 rte_free(valid_entry);
4002                         } else {
4003                                 rte_free(valid_entry);
4004                                 insert = 1;
4005                         }
4006                 }
4007         }
4008
4009         /* Not find any entry to merge, insert */
4010         if (insert == 0) {
4011                 if (prev != NULL)
4012                         LIST_INSERT_AFTER(prev, valid_entry, next);
4013                 else if (next != NULL)
4014                         LIST_INSERT_BEFORE(next, valid_entry, next);
4015                 else /* It's empty list, insert to head */
4016                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4017         }
4018
4019         pool->num_free += valid_entry->len;
4020         pool->num_alloc -= valid_entry->len;
4021
4022         return 0;
4023 }
4024
4025 static int
4026 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4027                        uint16_t num)
4028 {
4029         struct pool_entry *entry, *valid_entry;
4030
4031         if (pool == NULL || num == 0) {
4032                 PMD_DRV_LOG(ERR, "Invalid parameter");
4033                 return -EINVAL;
4034         }
4035
4036         if (pool->num_free < num) {
4037                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4038                             num, pool->num_free);
4039                 return -ENOMEM;
4040         }
4041
4042         valid_entry = NULL;
4043         /* Lookup  in free list and find most fit one */
4044         LIST_FOREACH(entry, &pool->free_list, next) {
4045                 if (entry->len >= num) {
4046                         /* Find best one */
4047                         if (entry->len == num) {
4048                                 valid_entry = entry;
4049                                 break;
4050                         }
4051                         if (valid_entry == NULL || valid_entry->len > entry->len)
4052                                 valid_entry = entry;
4053                 }
4054         }
4055
4056         /* Not find one to satisfy the request, return */
4057         if (valid_entry == NULL) {
4058                 PMD_DRV_LOG(ERR, "No valid entry found");
4059                 return -ENOMEM;
4060         }
4061         /**
4062          * The entry have equal queue number as requested,
4063          * remove it from alloc_list.
4064          */
4065         if (valid_entry->len == num) {
4066                 LIST_REMOVE(valid_entry, next);
4067         } else {
4068                 /**
4069                  * The entry have more numbers than requested,
4070                  * create a new entry for alloc_list and minus its
4071                  * queue base and number in free_list.
4072                  */
4073                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4074                 if (entry == NULL) {
4075                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
4076                                     "resource pool");
4077                         return -ENOMEM;
4078                 }
4079                 entry->base = valid_entry->base;
4080                 entry->len = num;
4081                 valid_entry->base += num;
4082                 valid_entry->len -= num;
4083                 valid_entry = entry;
4084         }
4085
4086         /* Insert it into alloc list, not sorted */
4087         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4088
4089         pool->num_free -= valid_entry->len;
4090         pool->num_alloc += valid_entry->len;
4091
4092         return valid_entry->base + pool->base;
4093 }
4094
4095 /**
4096  * bitmap_is_subset - Check whether src2 is subset of src1
4097  **/
4098 static inline int
4099 bitmap_is_subset(uint8_t src1, uint8_t src2)
4100 {
4101         return !((src1 ^ src2) & src2);
4102 }
4103
4104 static enum i40e_status_code
4105 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4106 {
4107         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4108
4109         /* If DCB is not supported, only default TC is supported */
4110         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4111                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4112                 return I40E_NOT_SUPPORTED;
4113         }
4114
4115         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4116                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
4117                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
4118                             enabled_tcmap);
4119                 return I40E_NOT_SUPPORTED;
4120         }
4121         return I40E_SUCCESS;
4122 }
4123
4124 int
4125 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4126                                 struct i40e_vsi_vlan_pvid_info *info)
4127 {
4128         struct i40e_hw *hw;
4129         struct i40e_vsi_context ctxt;
4130         uint8_t vlan_flags = 0;
4131         int ret;
4132
4133         if (vsi == NULL || info == NULL) {
4134                 PMD_DRV_LOG(ERR, "invalid parameters");
4135                 return I40E_ERR_PARAM;
4136         }
4137
4138         if (info->on) {
4139                 vsi->info.pvid = info->config.pvid;
4140                 /**
4141                  * If insert pvid is enabled, only tagged pkts are
4142                  * allowed to be sent out.
4143                  */
4144                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4145                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4146         } else {
4147                 vsi->info.pvid = 0;
4148                 if (info->config.reject.tagged == 0)
4149                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4150
4151                 if (info->config.reject.untagged == 0)
4152                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4153         }
4154         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4155                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4156         vsi->info.port_vlan_flags |= vlan_flags;
4157         vsi->info.valid_sections =
4158                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4159         memset(&ctxt, 0, sizeof(ctxt));
4160         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4161         ctxt.seid = vsi->seid;
4162
4163         hw = I40E_VSI_TO_HW(vsi);
4164         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4165         if (ret != I40E_SUCCESS)
4166                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4167
4168         return ret;
4169 }
4170
4171 static int
4172 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4173 {
4174         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4175         int i, ret;
4176         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4177
4178         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4179         if (ret != I40E_SUCCESS)
4180                 return ret;
4181
4182         if (!vsi->seid) {
4183                 PMD_DRV_LOG(ERR, "seid not valid");
4184                 return -EINVAL;
4185         }
4186
4187         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4188         tc_bw_data.tc_valid_bits = enabled_tcmap;
4189         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4190                 tc_bw_data.tc_bw_credits[i] =
4191                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4192
4193         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4194         if (ret != I40E_SUCCESS) {
4195                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4196                 return ret;
4197         }
4198
4199         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4200                                         sizeof(vsi->info.qs_handle));
4201         return I40E_SUCCESS;
4202 }
4203
4204 static enum i40e_status_code
4205 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4206                                  struct i40e_aqc_vsi_properties_data *info,
4207                                  uint8_t enabled_tcmap)
4208 {
4209         enum i40e_status_code ret;
4210         int i, total_tc = 0;
4211         uint16_t qpnum_per_tc, bsf, qp_idx;
4212
4213         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4214         if (ret != I40E_SUCCESS)
4215                 return ret;
4216
4217         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4218                 if (enabled_tcmap & (1 << i))
4219                         total_tc++;
4220         vsi->enabled_tc = enabled_tcmap;
4221
4222         /* Number of queues per enabled TC */
4223         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4224         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4225         bsf = rte_bsf32(qpnum_per_tc);
4226
4227         /* Adjust the queue number to actual queues that can be applied */
4228         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4229                 vsi->nb_qps = qpnum_per_tc * total_tc;
4230
4231         /**
4232          * Configure TC and queue mapping parameters, for enabled TC,
4233          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4234          * default queue will serve it.
4235          */
4236         qp_idx = 0;
4237         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4238                 if (vsi->enabled_tc & (1 << i)) {
4239                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4240                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4241                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4242                         qp_idx += qpnum_per_tc;
4243                 } else
4244                         info->tc_mapping[i] = 0;
4245         }
4246
4247         /* Associate queue number with VSI */
4248         if (vsi->type == I40E_VSI_SRIOV) {
4249                 info->mapping_flags |=
4250                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4251                 for (i = 0; i < vsi->nb_qps; i++)
4252                         info->queue_mapping[i] =
4253                                 rte_cpu_to_le_16(vsi->base_queue + i);
4254         } else {
4255                 info->mapping_flags |=
4256                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4257                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4258         }
4259         info->valid_sections |=
4260                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4261
4262         return I40E_SUCCESS;
4263 }
4264
4265 static int
4266 i40e_veb_release(struct i40e_veb *veb)
4267 {
4268         struct i40e_vsi *vsi;
4269         struct i40e_hw *hw;
4270
4271         if (veb == NULL)
4272                 return -EINVAL;
4273
4274         if (!TAILQ_EMPTY(&veb->head)) {
4275                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4276                 return -EACCES;
4277         }
4278         /* associate_vsi field is NULL for floating VEB */
4279         if (veb->associate_vsi != NULL) {
4280                 vsi = veb->associate_vsi;
4281                 hw = I40E_VSI_TO_HW(vsi);
4282
4283                 vsi->uplink_seid = veb->uplink_seid;
4284                 vsi->veb = NULL;
4285         } else {
4286                 veb->associate_pf->main_vsi->floating_veb = NULL;
4287                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4288         }
4289
4290         i40e_aq_delete_element(hw, veb->seid, NULL);
4291         rte_free(veb);
4292         return I40E_SUCCESS;
4293 }
4294
4295 /* Setup a veb */
4296 static struct i40e_veb *
4297 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4298 {
4299         struct i40e_veb *veb;
4300         int ret;
4301         struct i40e_hw *hw;
4302
4303         if (pf == NULL) {
4304                 PMD_DRV_LOG(ERR,
4305                             "veb setup failed, associated PF shouldn't null");
4306                 return NULL;
4307         }
4308         hw = I40E_PF_TO_HW(pf);
4309
4310         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4311         if (!veb) {
4312                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4313                 goto fail;
4314         }
4315
4316         veb->associate_vsi = vsi;
4317         veb->associate_pf = pf;
4318         TAILQ_INIT(&veb->head);
4319         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4320
4321         /* create floating veb if vsi is NULL */
4322         if (vsi != NULL) {
4323                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4324                                       I40E_DEFAULT_TCMAP, false,
4325                                       &veb->seid, false, NULL);
4326         } else {
4327                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4328                                       true, &veb->seid, false, NULL);
4329         }
4330
4331         if (ret != I40E_SUCCESS) {
4332                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4333                             hw->aq.asq_last_status);
4334                 goto fail;
4335         }
4336
4337         /* get statistics index */
4338         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4339                                 &veb->stats_idx, NULL, NULL, NULL);
4340         if (ret != I40E_SUCCESS) {
4341                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4342                             hw->aq.asq_last_status);
4343                 goto fail;
4344         }
4345         /* Get VEB bandwidth, to be implemented */
4346         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4347         if (vsi)
4348                 vsi->uplink_seid = veb->seid;
4349
4350         return veb;
4351 fail:
4352         rte_free(veb);
4353         return NULL;
4354 }
4355
4356 int
4357 i40e_vsi_release(struct i40e_vsi *vsi)
4358 {
4359         struct i40e_pf *pf;
4360         struct i40e_hw *hw;
4361         struct i40e_vsi_list *vsi_list;
4362         void *temp;
4363         int ret;
4364         struct i40e_mac_filter *f;
4365         uint16_t user_param;
4366
4367         if (!vsi)
4368                 return I40E_SUCCESS;
4369
4370         user_param = vsi->user_param;
4371
4372         pf = I40E_VSI_TO_PF(vsi);
4373         hw = I40E_VSI_TO_HW(vsi);
4374
4375         /* VSI has child to attach, release child first */
4376         if (vsi->veb) {
4377                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4378                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4379                                 return -1;
4380                 }
4381                 i40e_veb_release(vsi->veb);
4382         }
4383
4384         if (vsi->floating_veb) {
4385                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4386                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4387                                 return -1;
4388                 }
4389         }
4390
4391         /* Remove all macvlan filters of the VSI */
4392         i40e_vsi_remove_all_macvlan_filter(vsi);
4393         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4394                 rte_free(f);
4395
4396         if (vsi->type != I40E_VSI_MAIN &&
4397             ((vsi->type != I40E_VSI_SRIOV) ||
4398             !pf->floating_veb_list[user_param])) {
4399                 /* Remove vsi from parent's sibling list */
4400                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4401                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4402                         return I40E_ERR_PARAM;
4403                 }
4404                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4405                                 &vsi->sib_vsi_list, list);
4406
4407                 /* Remove all switch element of the VSI */
4408                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4409                 if (ret != I40E_SUCCESS)
4410                         PMD_DRV_LOG(ERR, "Failed to delete element");
4411         }
4412
4413         if ((vsi->type == I40E_VSI_SRIOV) &&
4414             pf->floating_veb_list[user_param]) {
4415                 /* Remove vsi from parent's sibling list */
4416                 if (vsi->parent_vsi == NULL ||
4417                     vsi->parent_vsi->floating_veb == NULL) {
4418                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4419                         return I40E_ERR_PARAM;
4420                 }
4421                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4422                              &vsi->sib_vsi_list, list);
4423
4424                 /* Remove all switch element of the VSI */
4425                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4426                 if (ret != I40E_SUCCESS)
4427                         PMD_DRV_LOG(ERR, "Failed to delete element");
4428         }
4429
4430         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4431
4432         if (vsi->type != I40E_VSI_SRIOV)
4433                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4434         rte_free(vsi);
4435
4436         return I40E_SUCCESS;
4437 }
4438
4439 static int
4440 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4441 {
4442         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4443         struct i40e_aqc_remove_macvlan_element_data def_filter;
4444         struct i40e_mac_filter_info filter;
4445         int ret;
4446
4447         if (vsi->type != I40E_VSI_MAIN)
4448                 return I40E_ERR_CONFIG;
4449         memset(&def_filter, 0, sizeof(def_filter));
4450         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4451                                         ETH_ADDR_LEN);
4452         def_filter.vlan_tag = 0;
4453         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4454                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4455         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4456         if (ret != I40E_SUCCESS) {
4457                 struct i40e_mac_filter *f;
4458                 struct ether_addr *mac;
4459
4460                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4461                             "macvlan filter");
4462                 /* It needs to add the permanent mac into mac list */
4463                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4464                 if (f == NULL) {
4465                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4466                         return I40E_ERR_NO_MEMORY;
4467                 }
4468                 mac = &f->mac_info.mac_addr;
4469                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4470                                 ETH_ADDR_LEN);
4471                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4472                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4473                 vsi->mac_num++;
4474
4475                 return ret;
4476         }
4477         (void)rte_memcpy(&filter.mac_addr,
4478                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4479         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4480         return i40e_vsi_add_mac(vsi, &filter);
4481 }
4482
4483 /*
4484  * i40e_vsi_get_bw_config - Query VSI BW Information
4485  * @vsi: the VSI to be queried
4486  *
4487  * Returns 0 on success, negative value on failure
4488  */
4489 static enum i40e_status_code
4490 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4491 {
4492         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4493         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4494         struct i40e_hw *hw = &vsi->adapter->hw;
4495         i40e_status ret;
4496         int i;
4497         uint32_t bw_max;
4498
4499         memset(&bw_config, 0, sizeof(bw_config));
4500         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4501         if (ret != I40E_SUCCESS) {
4502                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4503                             hw->aq.asq_last_status);
4504                 return ret;
4505         }
4506
4507         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4508         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4509                                         &ets_sla_config, NULL);
4510         if (ret != I40E_SUCCESS) {
4511                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4512                             "configuration %u", hw->aq.asq_last_status);
4513                 return ret;
4514         }
4515
4516         /* store and print out BW info */
4517         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4518         vsi->bw_info.bw_max = bw_config.max_bw;
4519         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4520         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4521         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4522                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4523                      I40E_16_BIT_WIDTH);
4524         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4525                 vsi->bw_info.bw_ets_share_credits[i] =
4526                                 ets_sla_config.share_credits[i];
4527                 vsi->bw_info.bw_ets_credits[i] =
4528                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4529                 /* 4 bits per TC, 4th bit is reserved */
4530                 vsi->bw_info.bw_ets_max[i] =
4531                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4532                                   RTE_LEN2MASK(3, uint8_t));
4533                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4534                             vsi->bw_info.bw_ets_share_credits[i]);
4535                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4536                             vsi->bw_info.bw_ets_credits[i]);
4537                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4538                             vsi->bw_info.bw_ets_max[i]);
4539         }
4540
4541         return I40E_SUCCESS;
4542 }
4543
4544 /* i40e_enable_pf_lb
4545  * @pf: pointer to the pf structure
4546  *
4547  * allow loopback on pf
4548  */
4549 static inline void
4550 i40e_enable_pf_lb(struct i40e_pf *pf)
4551 {
4552         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4553         struct i40e_vsi_context ctxt;
4554         int ret;
4555
4556         /* Use the FW API if FW >= v5.0 */
4557         if (hw->aq.fw_maj_ver < 5) {
4558                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4559                 return;
4560         }
4561
4562         memset(&ctxt, 0, sizeof(ctxt));
4563         ctxt.seid = pf->main_vsi_seid;
4564         ctxt.pf_num = hw->pf_id;
4565         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4566         if (ret) {
4567                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4568                             ret, hw->aq.asq_last_status);
4569                 return;
4570         }
4571         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4572         ctxt.info.valid_sections =
4573                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4574         ctxt.info.switch_id |=
4575                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4576
4577         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4578         if (ret)
4579                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4580                             hw->aq.asq_last_status);
4581 }
4582
4583 /* Setup a VSI */
4584 struct i40e_vsi *
4585 i40e_vsi_setup(struct i40e_pf *pf,
4586                enum i40e_vsi_type type,
4587                struct i40e_vsi *uplink_vsi,
4588                uint16_t user_param)
4589 {
4590         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4591         struct i40e_vsi *vsi;
4592         struct i40e_mac_filter_info filter;
4593         int ret;
4594         struct i40e_vsi_context ctxt;
4595         struct ether_addr broadcast =
4596                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4597
4598         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4599             uplink_vsi == NULL) {
4600                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4601                             "VSI link shouldn't be NULL");
4602                 return NULL;
4603         }
4604
4605         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4606                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4607                             "uplink VSI should be NULL");
4608                 return NULL;
4609         }
4610
4611         /* two situations
4612          * 1.type is not MAIN and uplink vsi is not NULL
4613          * If uplink vsi didn't setup VEB, create one first under veb field
4614          * 2.type is SRIOV and the uplink is NULL
4615          * If floating VEB is NULL, create one veb under floating veb field
4616          */
4617
4618         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4619             uplink_vsi->veb == NULL) {
4620                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4621
4622                 if (uplink_vsi->veb == NULL) {
4623                         PMD_DRV_LOG(ERR, "VEB setup failed");
4624                         return NULL;
4625                 }
4626                 /* set ALLOWLOOPBACk on pf, when veb is created */
4627                 i40e_enable_pf_lb(pf);
4628         }
4629
4630         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4631             pf->main_vsi->floating_veb == NULL) {
4632                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4633
4634                 if (pf->main_vsi->floating_veb == NULL) {
4635                         PMD_DRV_LOG(ERR, "VEB setup failed");
4636                         return NULL;
4637                 }
4638         }
4639
4640         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4641         if (!vsi) {
4642                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4643                 return NULL;
4644         }
4645         TAILQ_INIT(&vsi->mac_list);
4646         vsi->type = type;
4647         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4648         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4649         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4650         vsi->user_param = user_param;
4651         /* Allocate queues */
4652         switch (vsi->type) {
4653         case I40E_VSI_MAIN  :
4654                 vsi->nb_qps = pf->lan_nb_qps;
4655                 break;
4656         case I40E_VSI_SRIOV :
4657                 vsi->nb_qps = pf->vf_nb_qps;
4658                 break;
4659         case I40E_VSI_VMDQ2:
4660                 vsi->nb_qps = pf->vmdq_nb_qps;
4661                 break;
4662         case I40E_VSI_FDIR:
4663                 vsi->nb_qps = pf->fdir_nb_qps;
4664                 break;
4665         default:
4666                 goto fail_mem;
4667         }
4668         /*
4669          * The filter status descriptor is reported in rx queue 0,
4670          * while the tx queue for fdir filter programming has no
4671          * such constraints, can be non-zero queues.
4672          * To simplify it, choose FDIR vsi use queue 0 pair.
4673          * To make sure it will use queue 0 pair, queue allocation
4674          * need be done before this function is called
4675          */
4676         if (type != I40E_VSI_FDIR) {
4677                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4678                         if (ret < 0) {
4679                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4680                                                 vsi->seid, ret);
4681                                 goto fail_mem;
4682                         }
4683                         vsi->base_queue = ret;
4684         } else
4685                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4686
4687         /* VF has MSIX interrupt in VF range, don't allocate here */
4688         if (type == I40E_VSI_MAIN) {
4689                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4690                                           RTE_MIN(vsi->nb_qps,
4691                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4692                 if (ret < 0) {
4693                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4694                                     vsi->seid, ret);
4695                         goto fail_queue_alloc;
4696                 }
4697                 vsi->msix_intr = ret;
4698                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4699         } else if (type != I40E_VSI_SRIOV) {
4700                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4701                 if (ret < 0) {
4702                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4703                         goto fail_queue_alloc;
4704                 }
4705                 vsi->msix_intr = ret;
4706                 vsi->nb_msix = 1;
4707         } else {
4708                 vsi->msix_intr = 0;
4709                 vsi->nb_msix = 0;
4710         }
4711
4712         /* Add VSI */
4713         if (type == I40E_VSI_MAIN) {
4714                 /* For main VSI, no need to add since it's default one */
4715                 vsi->uplink_seid = pf->mac_seid;
4716                 vsi->seid = pf->main_vsi_seid;
4717                 /* Bind queues with specific MSIX interrupt */
4718                 /**
4719                  * Needs 2 interrupt at least, one for misc cause which will
4720                  * enabled from OS side, Another for queues binding the
4721                  * interrupt from device side only.
4722                  */
4723
4724                 /* Get default VSI parameters from hardware */
4725                 memset(&ctxt, 0, sizeof(ctxt));
4726                 ctxt.seid = vsi->seid;
4727                 ctxt.pf_num = hw->pf_id;
4728                 ctxt.uplink_seid = vsi->uplink_seid;
4729                 ctxt.vf_num = 0;
4730                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4731                 if (ret != I40E_SUCCESS) {
4732                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4733                         goto fail_msix_alloc;
4734                 }
4735                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4736                         sizeof(struct i40e_aqc_vsi_properties_data));
4737                 vsi->vsi_id = ctxt.vsi_number;
4738                 vsi->info.valid_sections = 0;
4739
4740                 /* Configure tc, enabled TC0 only */
4741                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4742                         I40E_SUCCESS) {
4743                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4744                         goto fail_msix_alloc;
4745                 }
4746
4747                 /* TC, queue mapping */
4748                 memset(&ctxt, 0, sizeof(ctxt));
4749                 vsi->info.valid_sections |=
4750                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4751                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4752                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4753                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4754                         sizeof(struct i40e_aqc_vsi_properties_data));
4755                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4756                                                 I40E_DEFAULT_TCMAP);
4757                 if (ret != I40E_SUCCESS) {
4758                         PMD_DRV_LOG(ERR, "Failed to configure "
4759                                     "TC queue mapping");
4760                         goto fail_msix_alloc;
4761                 }
4762                 ctxt.seid = vsi->seid;
4763                 ctxt.pf_num = hw->pf_id;
4764                 ctxt.uplink_seid = vsi->uplink_seid;
4765                 ctxt.vf_num = 0;
4766
4767                 /* Update VSI parameters */
4768                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4769                 if (ret != I40E_SUCCESS) {
4770                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4771                         goto fail_msix_alloc;
4772                 }
4773
4774                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4775                                                 sizeof(vsi->info.tc_mapping));
4776                 (void)rte_memcpy(&vsi->info.queue_mapping,
4777                                 &ctxt.info.queue_mapping,
4778                         sizeof(vsi->info.queue_mapping));
4779                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4780                 vsi->info.valid_sections = 0;
4781
4782                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4783                                 ETH_ADDR_LEN);
4784
4785                 /**
4786                  * Updating default filter settings are necessary to prevent
4787                  * reception of tagged packets.
4788                  * Some old firmware configurations load a default macvlan
4789                  * filter which accepts both tagged and untagged packets.
4790                  * The updating is to use a normal filter instead if needed.
4791                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4792                  * The firmware with correct configurations load the default
4793                  * macvlan filter which is expected and cannot be removed.
4794                  */
4795                 i40e_update_default_filter_setting(vsi);
4796                 i40e_config_qinq(hw, vsi);
4797         } else if (type == I40E_VSI_SRIOV) {
4798                 memset(&ctxt, 0, sizeof(ctxt));
4799                 /**
4800                  * For other VSI, the uplink_seid equals to uplink VSI's
4801                  * uplink_seid since they share same VEB
4802                  */
4803                 if (uplink_vsi == NULL)
4804                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4805                 else
4806                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4807                 ctxt.pf_num = hw->pf_id;
4808                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4809                 ctxt.uplink_seid = vsi->uplink_seid;
4810                 ctxt.connection_type = 0x1;
4811                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4812
4813                 /* Use the VEB configuration if FW >= v5.0 */
4814                 if (hw->aq.fw_maj_ver >= 5) {
4815                         /* Configure switch ID */
4816                         ctxt.info.valid_sections |=
4817                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4818                         ctxt.info.switch_id =
4819                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4820                 }
4821
4822                 /* Configure port/vlan */
4823                 ctxt.info.valid_sections |=
4824                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4825                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4826                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4827                                                 I40E_DEFAULT_TCMAP);
4828                 if (ret != I40E_SUCCESS) {
4829                         PMD_DRV_LOG(ERR, "Failed to configure "
4830                                     "TC queue mapping");
4831                         goto fail_msix_alloc;
4832                 }
4833                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4834                 ctxt.info.valid_sections |=
4835                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4836                 /**
4837                  * Since VSI is not created yet, only configure parameter,
4838                  * will add vsi below.
4839                  */
4840
4841                 i40e_config_qinq(hw, vsi);
4842         } else if (type == I40E_VSI_VMDQ2) {
4843                 memset(&ctxt, 0, sizeof(ctxt));
4844                 /*
4845                  * For other VSI, the uplink_seid equals to uplink VSI's
4846                  * uplink_seid since they share same VEB
4847                  */
4848                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4849                 ctxt.pf_num = hw->pf_id;
4850                 ctxt.vf_num = 0;
4851                 ctxt.uplink_seid = vsi->uplink_seid;
4852                 ctxt.connection_type = 0x1;
4853                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4854
4855                 ctxt.info.valid_sections |=
4856                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4857                 /* user_param carries flag to enable loop back */
4858                 if (user_param) {
4859                         ctxt.info.switch_id =
4860                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4861                         ctxt.info.switch_id |=
4862                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4863                 }
4864
4865                 /* Configure port/vlan */
4866                 ctxt.info.valid_sections |=
4867                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4868                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4869                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4870                                                 I40E_DEFAULT_TCMAP);
4871                 if (ret != I40E_SUCCESS) {
4872                         PMD_DRV_LOG(ERR, "Failed to configure "
4873                                         "TC queue mapping");
4874                         goto fail_msix_alloc;
4875                 }
4876                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4877                 ctxt.info.valid_sections |=
4878                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4879         } else if (type == I40E_VSI_FDIR) {
4880                 memset(&ctxt, 0, sizeof(ctxt));
4881                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4882                 ctxt.pf_num = hw->pf_id;
4883                 ctxt.vf_num = 0;
4884                 ctxt.uplink_seid = vsi->uplink_seid;
4885                 ctxt.connection_type = 0x1;     /* regular data port */
4886                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4887                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4888                                                 I40E_DEFAULT_TCMAP);
4889                 if (ret != I40E_SUCCESS) {
4890                         PMD_DRV_LOG(ERR, "Failed to configure "
4891                                         "TC queue mapping.");
4892                         goto fail_msix_alloc;
4893                 }
4894                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4895                 ctxt.info.valid_sections |=
4896                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4897         } else {
4898                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4899                 goto fail_msix_alloc;
4900         }
4901
4902         if (vsi->type != I40E_VSI_MAIN) {
4903                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4904                 if (ret != I40E_SUCCESS) {
4905                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4906                                     hw->aq.asq_last_status);
4907                         goto fail_msix_alloc;
4908                 }
4909                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4910                 vsi->info.valid_sections = 0;
4911                 vsi->seid = ctxt.seid;
4912                 vsi->vsi_id = ctxt.vsi_number;
4913                 vsi->sib_vsi_list.vsi = vsi;
4914                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4915                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4916                                           &vsi->sib_vsi_list, list);
4917                 } else {
4918                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4919                                           &vsi->sib_vsi_list, list);
4920                 }
4921         }
4922
4923         /* MAC/VLAN configuration */
4924         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4925         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4926
4927         ret = i40e_vsi_add_mac(vsi, &filter);
4928         if (ret != I40E_SUCCESS) {
4929                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4930                 goto fail_msix_alloc;
4931         }
4932
4933         /* Get VSI BW information */
4934         i40e_vsi_get_bw_config(vsi);
4935         return vsi;
4936 fail_msix_alloc:
4937         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4938 fail_queue_alloc:
4939         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4940 fail_mem:
4941         rte_free(vsi);
4942         return NULL;
4943 }
4944
4945 /* Configure vlan filter on or off */
4946 int
4947 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4948 {
4949         int i, num;
4950         struct i40e_mac_filter *f;
4951         void *temp;
4952         struct i40e_mac_filter_info *mac_filter;
4953         enum rte_mac_filter_type desired_filter;
4954         int ret = I40E_SUCCESS;
4955
4956         if (on) {
4957                 /* Filter to match MAC and VLAN */
4958                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4959         } else {
4960                 /* Filter to match only MAC */
4961                 desired_filter = RTE_MAC_PERFECT_MATCH;
4962         }
4963
4964         num = vsi->mac_num;
4965
4966         mac_filter = rte_zmalloc("mac_filter_info_data",
4967                                  num * sizeof(*mac_filter), 0);
4968         if (mac_filter == NULL) {
4969                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4970                 return I40E_ERR_NO_MEMORY;
4971         }
4972
4973         i = 0;
4974
4975         /* Remove all existing mac */
4976         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4977                 mac_filter[i] = f->mac_info;
4978                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4979                 if (ret) {
4980                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4981                                     on ? "enable" : "disable");
4982                         goto DONE;
4983                 }
4984                 i++;
4985         }
4986
4987         /* Override with new filter */
4988         for (i = 0; i < num; i++) {
4989                 mac_filter[i].filter_type = desired_filter;
4990                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4991                 if (ret) {
4992                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4993                                     on ? "enable" : "disable");
4994                         goto DONE;
4995                 }
4996         }
4997
4998 DONE:
4999         rte_free(mac_filter);
5000         return ret;
5001 }
5002
5003 /* Configure vlan stripping on or off */
5004 int
5005 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5006 {
5007         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5008         struct i40e_vsi_context ctxt;
5009         uint8_t vlan_flags;
5010         int ret = I40E_SUCCESS;
5011
5012         /* Check if it has been already on or off */
5013         if (vsi->info.valid_sections &
5014                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5015                 if (on) {
5016                         if ((vsi->info.port_vlan_flags &
5017                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5018                                 return 0; /* already on */
5019                 } else {
5020                         if ((vsi->info.port_vlan_flags &
5021                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5022                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5023                                 return 0; /* already off */
5024                 }
5025         }
5026
5027         if (on)
5028                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5029         else
5030                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5031         vsi->info.valid_sections =
5032                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5033         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5034         vsi->info.port_vlan_flags |= vlan_flags;
5035         ctxt.seid = vsi->seid;
5036         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5037         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5038         if (ret)
5039                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5040                             on ? "enable" : "disable");
5041
5042         return ret;
5043 }
5044
5045 static int
5046 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5047 {
5048         struct rte_eth_dev_data *data = dev->data;
5049         int ret;
5050         int mask = 0;
5051
5052         /* Apply vlan offload setting */
5053         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5054         i40e_vlan_offload_set(dev, mask);
5055
5056         /* Apply double-vlan setting, not implemented yet */
5057
5058         /* Apply pvid setting */
5059         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5060                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5061         if (ret)
5062                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5063
5064         return ret;
5065 }
5066
5067 static int
5068 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5069 {
5070         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5071
5072         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5073 }
5074
5075 static int
5076 i40e_update_flow_control(struct i40e_hw *hw)
5077 {
5078 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5079         struct i40e_link_status link_status;
5080         uint32_t rxfc = 0, txfc = 0, reg;
5081         uint8_t an_info;
5082         int ret;
5083
5084         memset(&link_status, 0, sizeof(link_status));
5085         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5086         if (ret != I40E_SUCCESS) {
5087                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5088                 goto write_reg; /* Disable flow control */
5089         }
5090
5091         an_info = hw->phy.link_info.an_info;
5092         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5093                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5094                 ret = I40E_ERR_NOT_READY;
5095                 goto write_reg; /* Disable flow control */
5096         }
5097         /**
5098          * If link auto negotiation is enabled, flow control needs to
5099          * be configured according to it
5100          */
5101         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5102         case I40E_LINK_PAUSE_RXTX:
5103                 rxfc = 1;
5104                 txfc = 1;
5105                 hw->fc.current_mode = I40E_FC_FULL;
5106                 break;
5107         case I40E_AQ_LINK_PAUSE_RX:
5108                 rxfc = 1;
5109                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5110                 break;
5111         case I40E_AQ_LINK_PAUSE_TX:
5112                 txfc = 1;
5113                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5114                 break;
5115         default:
5116                 hw->fc.current_mode = I40E_FC_NONE;
5117                 break;
5118         }
5119
5120 write_reg:
5121         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5122                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5123         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5124         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5125         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5126         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5127
5128         return ret;
5129 }
5130
5131 /* PF setup */
5132 static int
5133 i40e_pf_setup(struct i40e_pf *pf)
5134 {
5135         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5136         struct i40e_filter_control_settings settings;
5137         struct i40e_vsi *vsi;
5138         int ret;
5139
5140         /* Clear all stats counters */
5141         pf->offset_loaded = FALSE;
5142         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5143         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5144
5145         ret = i40e_pf_get_switch_config(pf);
5146         if (ret != I40E_SUCCESS) {
5147                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5148                 return ret;
5149         }
5150         if (pf->flags & I40E_FLAG_FDIR) {
5151                 /* make queue allocated first, let FDIR use queue pair 0*/
5152                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5153                 if (ret != I40E_FDIR_QUEUE_ID) {
5154                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
5155                                     " ret =%d", ret);
5156                         pf->flags &= ~I40E_FLAG_FDIR;
5157                 }
5158         }
5159         /*  main VSI setup */
5160         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5161         if (!vsi) {
5162                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5163                 return I40E_ERR_NOT_READY;
5164         }
5165         pf->main_vsi = vsi;
5166
5167         /* Configure filter control */
5168         memset(&settings, 0, sizeof(settings));
5169         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5170                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5171         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5172                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5173         else {
5174                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
5175                                                 hw->func_caps.rss_table_size);
5176                 return I40E_ERR_PARAM;
5177         }
5178         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
5179                         "size: %u\n", hw->func_caps.rss_table_size);
5180         pf->hash_lut_size = hw->func_caps.rss_table_size;
5181
5182         /* Enable ethtype and macvlan filters */
5183         settings.enable_ethtype = TRUE;
5184         settings.enable_macvlan = TRUE;
5185         ret = i40e_set_filter_control(hw, &settings);
5186         if (ret)
5187                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5188                                                                 ret);
5189
5190         /* Update flow control according to the auto negotiation */
5191         i40e_update_flow_control(hw);
5192
5193         return I40E_SUCCESS;
5194 }
5195
5196 int
5197 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5198 {
5199         uint32_t reg;
5200         uint16_t j;
5201
5202         /**
5203          * Set or clear TX Queue Disable flags,
5204          * which is required by hardware.
5205          */
5206         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5207         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5208
5209         /* Wait until the request is finished */
5210         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5211                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5212                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5213                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5214                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5215                                                         & 0x1))) {
5216                         break;
5217                 }
5218         }
5219         if (on) {
5220                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5221                         return I40E_SUCCESS; /* already on, skip next steps */
5222
5223                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5224                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5225         } else {
5226                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5227                         return I40E_SUCCESS; /* already off, skip next steps */
5228                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5229         }
5230         /* Write the register */
5231         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5232         /* Check the result */
5233         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5234                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5235                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5236                 if (on) {
5237                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5238                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5239                                 break;
5240                 } else {
5241                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5242                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5243                                 break;
5244                 }
5245         }
5246         /* Check if it is timeout */
5247         if (j >= I40E_CHK_Q_ENA_COUNT) {
5248                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5249                             (on ? "enable" : "disable"), q_idx);
5250                 return I40E_ERR_TIMEOUT;
5251         }
5252
5253         return I40E_SUCCESS;
5254 }
5255
5256 /* Swith on or off the tx queues */
5257 static int
5258 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5259 {
5260         struct rte_eth_dev_data *dev_data = pf->dev_data;
5261         struct i40e_tx_queue *txq;
5262         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5263         uint16_t i;
5264         int ret;
5265
5266         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5267                 txq = dev_data->tx_queues[i];
5268                 /* Don't operate the queue if not configured or
5269                  * if starting only per queue */
5270                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5271                         continue;
5272                 if (on)
5273                         ret = i40e_dev_tx_queue_start(dev, i);
5274                 else
5275                         ret = i40e_dev_tx_queue_stop(dev, i);
5276                 if ( ret != I40E_SUCCESS)
5277                         return ret;
5278         }
5279
5280         return I40E_SUCCESS;
5281 }
5282
5283 int
5284 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5285 {
5286         uint32_t reg;
5287         uint16_t j;
5288
5289         /* Wait until the request is finished */
5290         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5291                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5292                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5293                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5294                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5295                         break;
5296         }
5297
5298         if (on) {
5299                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5300                         return I40E_SUCCESS; /* Already on, skip next steps */
5301                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5302         } else {
5303                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5304                         return I40E_SUCCESS; /* Already off, skip next steps */
5305                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5306         }
5307
5308         /* Write the register */
5309         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5310         /* Check the result */
5311         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5312                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5313                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5314                 if (on) {
5315                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5316                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5317                                 break;
5318                 } else {
5319                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5320                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5321                                 break;
5322                 }
5323         }
5324
5325         /* Check if it is timeout */
5326         if (j >= I40E_CHK_Q_ENA_COUNT) {
5327                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5328                             (on ? "enable" : "disable"), q_idx);
5329                 return I40E_ERR_TIMEOUT;
5330         }
5331
5332         return I40E_SUCCESS;
5333 }
5334 /* Switch on or off the rx queues */
5335 static int
5336 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5337 {
5338         struct rte_eth_dev_data *dev_data = pf->dev_data;
5339         struct i40e_rx_queue *rxq;
5340         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5341         uint16_t i;
5342         int ret;
5343
5344         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5345                 rxq = dev_data->rx_queues[i];
5346                 /* Don't operate the queue if not configured or
5347                  * if starting only per queue */
5348                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5349                         continue;
5350                 if (on)
5351                         ret = i40e_dev_rx_queue_start(dev, i);
5352                 else
5353                         ret = i40e_dev_rx_queue_stop(dev, i);
5354                 if (ret != I40E_SUCCESS)
5355                         return ret;
5356         }
5357
5358         return I40E_SUCCESS;
5359 }
5360
5361 /* Switch on or off all the rx/tx queues */
5362 int
5363 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5364 {
5365         int ret;
5366
5367         if (on) {
5368                 /* enable rx queues before enabling tx queues */
5369                 ret = i40e_dev_switch_rx_queues(pf, on);
5370                 if (ret) {
5371                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5372                         return ret;
5373                 }
5374                 ret = i40e_dev_switch_tx_queues(pf, on);
5375         } else {
5376                 /* Stop tx queues before stopping rx queues */
5377                 ret = i40e_dev_switch_tx_queues(pf, on);
5378                 if (ret) {
5379                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5380                         return ret;
5381                 }
5382                 ret = i40e_dev_switch_rx_queues(pf, on);
5383         }
5384
5385         return ret;
5386 }
5387
5388 /* Initialize VSI for TX */
5389 static int
5390 i40e_dev_tx_init(struct i40e_pf *pf)
5391 {
5392         struct rte_eth_dev_data *data = pf->dev_data;
5393         uint16_t i;
5394         uint32_t ret = I40E_SUCCESS;
5395         struct i40e_tx_queue *txq;
5396
5397         for (i = 0; i < data->nb_tx_queues; i++) {
5398                 txq = data->tx_queues[i];
5399                 if (!txq || !txq->q_set)
5400                         continue;
5401                 ret = i40e_tx_queue_init(txq);
5402                 if (ret != I40E_SUCCESS)
5403                         break;
5404         }
5405         if (ret == I40E_SUCCESS)
5406                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5407                                      ->eth_dev);
5408
5409         return ret;
5410 }
5411
5412 /* Initialize VSI for RX */
5413 static int
5414 i40e_dev_rx_init(struct i40e_pf *pf)
5415 {
5416         struct rte_eth_dev_data *data = pf->dev_data;
5417         int ret = I40E_SUCCESS;
5418         uint16_t i;
5419         struct i40e_rx_queue *rxq;
5420
5421         i40e_pf_config_mq_rx(pf);
5422         for (i = 0; i < data->nb_rx_queues; i++) {
5423                 rxq = data->rx_queues[i];
5424                 if (!rxq || !rxq->q_set)
5425                         continue;
5426
5427                 ret = i40e_rx_queue_init(rxq);
5428                 if (ret != I40E_SUCCESS) {
5429                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5430                                     "initialization");
5431                         break;
5432                 }
5433         }
5434         if (ret == I40E_SUCCESS)
5435                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5436                                      ->eth_dev);
5437
5438         return ret;
5439 }
5440
5441 static int
5442 i40e_dev_rxtx_init(struct i40e_pf *pf)
5443 {
5444         int err;
5445
5446         err = i40e_dev_tx_init(pf);
5447         if (err) {
5448                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5449                 return err;
5450         }
5451         err = i40e_dev_rx_init(pf);
5452         if (err) {
5453                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5454                 return err;
5455         }
5456
5457         return err;
5458 }
5459
5460 static int
5461 i40e_vmdq_setup(struct rte_eth_dev *dev)
5462 {
5463         struct rte_eth_conf *conf = &dev->data->dev_conf;
5464         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5465         int i, err, conf_vsis, j, loop;
5466         struct i40e_vsi *vsi;
5467         struct i40e_vmdq_info *vmdq_info;
5468         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5469         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5470
5471         /*
5472          * Disable interrupt to avoid message from VF. Furthermore, it will
5473          * avoid race condition in VSI creation/destroy.
5474          */
5475         i40e_pf_disable_irq0(hw);
5476
5477         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5478                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5479                 return -ENOTSUP;
5480         }
5481
5482         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5483         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5484                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5485                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5486                         pf->max_nb_vmdq_vsi);
5487                 return -ENOTSUP;
5488         }
5489
5490         if (pf->vmdq != NULL) {
5491                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5492                 return 0;
5493         }
5494
5495         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5496                                 sizeof(*vmdq_info) * conf_vsis, 0);
5497
5498         if (pf->vmdq == NULL) {
5499                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5500                 return -ENOMEM;
5501         }
5502
5503         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5504
5505         /* Create VMDQ VSI */
5506         for (i = 0; i < conf_vsis; i++) {
5507                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5508                                 vmdq_conf->enable_loop_back);
5509                 if (vsi == NULL) {
5510                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5511                         err = -1;
5512                         goto err_vsi_setup;
5513                 }
5514                 vmdq_info = &pf->vmdq[i];
5515                 vmdq_info->pf = pf;
5516                 vmdq_info->vsi = vsi;
5517         }
5518         pf->nb_cfg_vmdq_vsi = conf_vsis;
5519
5520         /* Configure Vlan */
5521         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5522         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5523                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5524                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5525                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5526                                         vmdq_conf->pool_map[i].vlan_id, j);
5527
5528                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5529                                                 vmdq_conf->pool_map[i].vlan_id);
5530                                 if (err) {
5531                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5532                                         err = -1;
5533                                         goto err_vsi_setup;
5534                                 }
5535                         }
5536                 }
5537         }
5538
5539         i40e_pf_enable_irq0(hw);
5540
5541         return 0;
5542
5543 err_vsi_setup:
5544         for (i = 0; i < conf_vsis; i++)
5545                 if (pf->vmdq[i].vsi == NULL)
5546                         break;
5547                 else
5548                         i40e_vsi_release(pf->vmdq[i].vsi);
5549
5550         rte_free(pf->vmdq);
5551         pf->vmdq = NULL;
5552         i40e_pf_enable_irq0(hw);
5553         return err;
5554 }
5555
5556 static void
5557 i40e_stat_update_32(struct i40e_hw *hw,
5558                    uint32_t reg,
5559                    bool offset_loaded,
5560                    uint64_t *offset,
5561                    uint64_t *stat)
5562 {
5563         uint64_t new_data;
5564
5565         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5566         if (!offset_loaded)
5567                 *offset = new_data;
5568
5569         if (new_data >= *offset)
5570                 *stat = (uint64_t)(new_data - *offset);
5571         else
5572                 *stat = (uint64_t)((new_data +
5573                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5574 }
5575
5576 static void
5577 i40e_stat_update_48(struct i40e_hw *hw,
5578                    uint32_t hireg,
5579                    uint32_t loreg,
5580                    bool offset_loaded,
5581                    uint64_t *offset,
5582                    uint64_t *stat)
5583 {
5584         uint64_t new_data;
5585
5586         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5587         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5588                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5589
5590         if (!offset_loaded)
5591                 *offset = new_data;
5592
5593         if (new_data >= *offset)
5594                 *stat = new_data - *offset;
5595         else
5596                 *stat = (uint64_t)((new_data +
5597                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5598
5599         *stat &= I40E_48_BIT_MASK;
5600 }
5601
5602 /* Disable IRQ0 */
5603 void
5604 i40e_pf_disable_irq0(struct i40e_hw *hw)
5605 {
5606         /* Disable all interrupt types */
5607         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5608         I40E_WRITE_FLUSH(hw);
5609 }
5610
5611 /* Enable IRQ0 */
5612 void
5613 i40e_pf_enable_irq0(struct i40e_hw *hw)
5614 {
5615         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5616                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5617                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5618                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5619         I40E_WRITE_FLUSH(hw);
5620 }
5621
5622 static void
5623 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5624 {
5625         /* read pending request and disable first */
5626         i40e_pf_disable_irq0(hw);
5627         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5628         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5629                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5630
5631         if (no_queue)
5632                 /* Link no queues with irq0 */
5633                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5634                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5635 }
5636
5637 static void
5638 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5639 {
5640         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5641         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5642         int i;
5643         uint16_t abs_vf_id;
5644         uint32_t index, offset, val;
5645
5646         if (!pf->vfs)
5647                 return;
5648         /**
5649          * Try to find which VF trigger a reset, use absolute VF id to access
5650          * since the reg is global register.
5651          */
5652         for (i = 0; i < pf->vf_num; i++) {
5653                 abs_vf_id = hw->func_caps.vf_base_id + i;
5654                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5655                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5656                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5657                 /* VFR event occured */
5658                 if (val & (0x1 << offset)) {
5659                         int ret;
5660
5661                         /* Clear the event first */
5662                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5663                                                         (0x1 << offset));
5664                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5665                         /**
5666                          * Only notify a VF reset event occured,
5667                          * don't trigger another SW reset
5668                          */
5669                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5670                         if (ret != I40E_SUCCESS)
5671                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5672                 }
5673         }
5674 }
5675
5676 static void
5677 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5678 {
5679         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5680         struct i40e_virtchnl_pf_event event;
5681         int i;
5682
5683         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5684         event.event_data.link_event.link_status =
5685                 dev->data->dev_link.link_status;
5686         event.event_data.link_event.link_speed =
5687                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5688
5689         for (i = 0; i < pf->vf_num; i++)
5690                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5691                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5692 }
5693
5694 static void
5695 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5696 {
5697         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5698         struct i40e_arq_event_info info;
5699         uint16_t pending, opcode;
5700         int ret;
5701
5702         info.buf_len = I40E_AQ_BUF_SZ;
5703         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5704         if (!info.msg_buf) {
5705                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5706                 return;
5707         }
5708
5709         pending = 1;
5710         while (pending) {
5711                 ret = i40e_clean_arq_element(hw, &info, &pending);
5712
5713                 if (ret != I40E_SUCCESS) {
5714                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5715                                     "aq_err: %u", hw->aq.asq_last_status);
5716                         break;
5717                 }
5718                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5719
5720                 switch (opcode) {
5721                 case i40e_aqc_opc_send_msg_to_pf:
5722                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5723                         i40e_pf_host_handle_vf_msg(dev,
5724                                         rte_le_to_cpu_16(info.desc.retval),
5725                                         rte_le_to_cpu_32(info.desc.cookie_high),
5726                                         rte_le_to_cpu_32(info.desc.cookie_low),
5727                                         info.msg_buf,
5728                                         info.msg_len);
5729                         break;
5730                 case i40e_aqc_opc_get_link_status:
5731                         ret = i40e_dev_link_update(dev, 0);
5732                         if (!ret) {
5733                                 i40e_notify_all_vfs_link_status(dev);
5734                                 _rte_eth_dev_callback_process(dev,
5735                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5736                         }
5737                         break;
5738                 default:
5739                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5740                                     opcode);
5741                         break;
5742                 }
5743         }
5744         rte_free(info.msg_buf);
5745 }
5746
5747 /**
5748  * Interrupt handler triggered by NIC  for handling
5749  * specific interrupt.
5750  *
5751  * @param handle
5752  *  Pointer to interrupt handle.
5753  * @param param
5754  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5755  *
5756  * @return
5757  *  void
5758  */
5759 static void
5760 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5761                            void *param)
5762 {
5763         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5764         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5765         uint32_t icr0;
5766
5767         /* Disable interrupt */
5768         i40e_pf_disable_irq0(hw);
5769
5770         /* read out interrupt causes */
5771         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5772
5773         /* No interrupt event indicated */
5774         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5775                 PMD_DRV_LOG(INFO, "No interrupt event");
5776                 goto done;
5777         }
5778 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5779         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5780                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5781         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5782                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5783         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5784                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5785         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5786                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5787         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5788                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5789         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5790                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5791         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5792                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5793 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5794
5795         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5796                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5797                 i40e_dev_handle_vfr_event(dev);
5798         }
5799         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5800                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5801                 i40e_dev_handle_aq_msg(dev);
5802         }
5803
5804 done:
5805         /* Enable interrupt */
5806         i40e_pf_enable_irq0(hw);
5807         rte_intr_enable(intr_handle);
5808 }
5809
5810 static int
5811 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5812                          struct i40e_macvlan_filter *filter,
5813                          int total)
5814 {
5815         int ele_num, ele_buff_size;
5816         int num, actual_num, i;
5817         uint16_t flags;
5818         int ret = I40E_SUCCESS;
5819         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5820         struct i40e_aqc_add_macvlan_element_data *req_list;
5821
5822         if (filter == NULL  || total == 0)
5823                 return I40E_ERR_PARAM;
5824         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5825         ele_buff_size = hw->aq.asq_buf_size;
5826
5827         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5828         if (req_list == NULL) {
5829                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5830                 return I40E_ERR_NO_MEMORY;
5831         }
5832
5833         num = 0;
5834         do {
5835                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5836                 memset(req_list, 0, ele_buff_size);
5837
5838                 for (i = 0; i < actual_num; i++) {
5839                         (void)rte_memcpy(req_list[i].mac_addr,
5840                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5841                         req_list[i].vlan_tag =
5842                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5843
5844                         switch (filter[num + i].filter_type) {
5845                         case RTE_MAC_PERFECT_MATCH:
5846                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5847                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5848                                 break;
5849                         case RTE_MACVLAN_PERFECT_MATCH:
5850                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5851                                 break;
5852                         case RTE_MAC_HASH_MATCH:
5853                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5854                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5855                                 break;
5856                         case RTE_MACVLAN_HASH_MATCH:
5857                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5858                                 break;
5859                         default:
5860                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5861                                 ret = I40E_ERR_PARAM;
5862                                 goto DONE;
5863                         }
5864
5865                         req_list[i].queue_number = 0;
5866
5867                         req_list[i].flags = rte_cpu_to_le_16(flags);
5868                 }
5869
5870                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5871                                                 actual_num, NULL);
5872                 if (ret != I40E_SUCCESS) {
5873                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5874                         goto DONE;
5875                 }
5876                 num += actual_num;
5877         } while (num < total);
5878
5879 DONE:
5880         rte_free(req_list);
5881         return ret;
5882 }
5883
5884 static int
5885 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5886                             struct i40e_macvlan_filter *filter,
5887                             int total)
5888 {
5889         int ele_num, ele_buff_size;
5890         int num, actual_num, i;
5891         uint16_t flags;
5892         int ret = I40E_SUCCESS;
5893         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5894         struct i40e_aqc_remove_macvlan_element_data *req_list;
5895
5896         if (filter == NULL  || total == 0)
5897                 return I40E_ERR_PARAM;
5898
5899         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5900         ele_buff_size = hw->aq.asq_buf_size;
5901
5902         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5903         if (req_list == NULL) {
5904                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5905                 return I40E_ERR_NO_MEMORY;
5906         }
5907
5908         num = 0;
5909         do {
5910                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5911                 memset(req_list, 0, ele_buff_size);
5912
5913                 for (i = 0; i < actual_num; i++) {
5914                         (void)rte_memcpy(req_list[i].mac_addr,
5915                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5916                         req_list[i].vlan_tag =
5917                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5918
5919                         switch (filter[num + i].filter_type) {
5920                         case RTE_MAC_PERFECT_MATCH:
5921                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5922                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5923                                 break;
5924                         case RTE_MACVLAN_PERFECT_MATCH:
5925                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5926                                 break;
5927                         case RTE_MAC_HASH_MATCH:
5928                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5929                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5930                                 break;
5931                         case RTE_MACVLAN_HASH_MATCH:
5932                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5933                                 break;
5934                         default:
5935                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5936                                 ret = I40E_ERR_PARAM;
5937                                 goto DONE;
5938                         }
5939                         req_list[i].flags = rte_cpu_to_le_16(flags);
5940                 }
5941
5942                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5943                                                 actual_num, NULL);
5944                 if (ret != I40E_SUCCESS) {
5945                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5946                         goto DONE;
5947                 }
5948                 num += actual_num;
5949         } while (num < total);
5950
5951 DONE:
5952         rte_free(req_list);
5953         return ret;
5954 }
5955
5956 /* Find out specific MAC filter */
5957 static struct i40e_mac_filter *
5958 i40e_find_mac_filter(struct i40e_vsi *vsi,
5959                          struct ether_addr *macaddr)
5960 {
5961         struct i40e_mac_filter *f;
5962
5963         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5964                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5965                         return f;
5966         }
5967
5968         return NULL;
5969 }
5970
5971 static bool
5972 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5973                          uint16_t vlan_id)
5974 {
5975         uint32_t vid_idx, vid_bit;
5976
5977         if (vlan_id > ETH_VLAN_ID_MAX)
5978                 return 0;
5979
5980         vid_idx = I40E_VFTA_IDX(vlan_id);
5981         vid_bit = I40E_VFTA_BIT(vlan_id);
5982
5983         if (vsi->vfta[vid_idx] & vid_bit)
5984                 return 1;
5985         else
5986                 return 0;
5987 }
5988
5989 static void
5990 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5991                          uint16_t vlan_id, bool on)
5992 {
5993         uint32_t vid_idx, vid_bit;
5994
5995         if (vlan_id > ETH_VLAN_ID_MAX)
5996                 return;
5997
5998         vid_idx = I40E_VFTA_IDX(vlan_id);
5999         vid_bit = I40E_VFTA_BIT(vlan_id);
6000
6001         if (on)
6002                 vsi->vfta[vid_idx] |= vid_bit;
6003         else
6004                 vsi->vfta[vid_idx] &= ~vid_bit;
6005 }
6006
6007 /**
6008  * Find all vlan options for specific mac addr,
6009  * return with actual vlan found.
6010  */
6011 static inline int
6012 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6013                            struct i40e_macvlan_filter *mv_f,
6014                            int num, struct ether_addr *addr)
6015 {
6016         int i;
6017         uint32_t j, k;
6018
6019         /**
6020          * Not to use i40e_find_vlan_filter to decrease the loop time,
6021          * although the code looks complex.
6022           */
6023         if (num < vsi->vlan_num)
6024                 return I40E_ERR_PARAM;
6025
6026         i = 0;
6027         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6028                 if (vsi->vfta[j]) {
6029                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6030                                 if (vsi->vfta[j] & (1 << k)) {
6031                                         if (i > num - 1) {
6032                                                 PMD_DRV_LOG(ERR, "vlan number "
6033                                                             "not match");
6034                                                 return I40E_ERR_PARAM;
6035                                         }
6036                                         (void)rte_memcpy(&mv_f[i].macaddr,
6037                                                         addr, ETH_ADDR_LEN);
6038                                         mv_f[i].vlan_id =
6039                                                 j * I40E_UINT32_BIT_SIZE + k;
6040                                         i++;
6041                                 }
6042                         }
6043                 }
6044         }
6045         return I40E_SUCCESS;
6046 }
6047
6048 static inline int
6049 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6050                            struct i40e_macvlan_filter *mv_f,
6051                            int num,
6052                            uint16_t vlan)
6053 {
6054         int i = 0;
6055         struct i40e_mac_filter *f;
6056
6057         if (num < vsi->mac_num)
6058                 return I40E_ERR_PARAM;
6059
6060         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6061                 if (i > num - 1) {
6062                         PMD_DRV_LOG(ERR, "buffer number not match");
6063                         return I40E_ERR_PARAM;
6064                 }
6065                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6066                                 ETH_ADDR_LEN);
6067                 mv_f[i].vlan_id = vlan;
6068                 mv_f[i].filter_type = f->mac_info.filter_type;
6069                 i++;
6070         }
6071
6072         return I40E_SUCCESS;
6073 }
6074
6075 static int
6076 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6077 {
6078         int i, num;
6079         struct i40e_mac_filter *f;
6080         struct i40e_macvlan_filter *mv_f;
6081         int ret = I40E_SUCCESS;
6082
6083         if (vsi == NULL || vsi->mac_num == 0)
6084                 return I40E_ERR_PARAM;
6085
6086         /* Case that no vlan is set */
6087         if (vsi->vlan_num == 0)
6088                 num = vsi->mac_num;
6089         else
6090                 num = vsi->mac_num * vsi->vlan_num;
6091
6092         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6093         if (mv_f == NULL) {
6094                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6095                 return I40E_ERR_NO_MEMORY;
6096         }
6097
6098         i = 0;
6099         if (vsi->vlan_num == 0) {
6100                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6101                         (void)rte_memcpy(&mv_f[i].macaddr,
6102                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6103                         mv_f[i].vlan_id = 0;
6104                         i++;
6105                 }
6106         } else {
6107                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6108                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6109                                         vsi->vlan_num, &f->mac_info.mac_addr);
6110                         if (ret != I40E_SUCCESS)
6111                                 goto DONE;
6112                         i += vsi->vlan_num;
6113                 }
6114         }
6115
6116         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6117 DONE:
6118         rte_free(mv_f);
6119
6120         return ret;
6121 }
6122
6123 int
6124 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6125 {
6126         struct i40e_macvlan_filter *mv_f;
6127         int mac_num;
6128         int ret = I40E_SUCCESS;
6129
6130         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6131                 return I40E_ERR_PARAM;
6132
6133         /* If it's already set, just return */
6134         if (i40e_find_vlan_filter(vsi,vlan))
6135                 return I40E_SUCCESS;
6136
6137         mac_num = vsi->mac_num;
6138
6139         if (mac_num == 0) {
6140                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6141                 return I40E_ERR_PARAM;
6142         }
6143
6144         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6145
6146         if (mv_f == NULL) {
6147                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6148                 return I40E_ERR_NO_MEMORY;
6149         }
6150
6151         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6152
6153         if (ret != I40E_SUCCESS)
6154                 goto DONE;
6155
6156         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6157
6158         if (ret != I40E_SUCCESS)
6159                 goto DONE;
6160
6161         i40e_set_vlan_filter(vsi, vlan, 1);
6162
6163         vsi->vlan_num++;
6164         ret = I40E_SUCCESS;
6165 DONE:
6166         rte_free(mv_f);
6167         return ret;
6168 }
6169
6170 int
6171 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6172 {
6173         struct i40e_macvlan_filter *mv_f;
6174         int mac_num;
6175         int ret = I40E_SUCCESS;
6176
6177         /**
6178          * Vlan 0 is the generic filter for untagged packets
6179          * and can't be removed.
6180          */
6181         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6182                 return I40E_ERR_PARAM;
6183
6184         /* If can't find it, just return */
6185         if (!i40e_find_vlan_filter(vsi, vlan))
6186                 return I40E_ERR_PARAM;
6187
6188         mac_num = vsi->mac_num;
6189
6190         if (mac_num == 0) {
6191                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6192                 return I40E_ERR_PARAM;
6193         }
6194
6195         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6196
6197         if (mv_f == NULL) {
6198                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6199                 return I40E_ERR_NO_MEMORY;
6200         }
6201
6202         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6203
6204         if (ret != I40E_SUCCESS)
6205                 goto DONE;
6206
6207         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6208
6209         if (ret != I40E_SUCCESS)
6210                 goto DONE;
6211
6212         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6213         if (vsi->vlan_num == 1) {
6214                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6215                 if (ret != I40E_SUCCESS)
6216                         goto DONE;
6217
6218                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6219                 if (ret != I40E_SUCCESS)
6220                         goto DONE;
6221         }
6222
6223         i40e_set_vlan_filter(vsi, vlan, 0);
6224
6225         vsi->vlan_num--;
6226         ret = I40E_SUCCESS;
6227 DONE:
6228         rte_free(mv_f);
6229         return ret;
6230 }
6231
6232 int
6233 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6234 {
6235         struct i40e_mac_filter *f;
6236         struct i40e_macvlan_filter *mv_f;
6237         int i, vlan_num = 0;
6238         int ret = I40E_SUCCESS;
6239
6240         /* If it's add and we've config it, return */
6241         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6242         if (f != NULL)
6243                 return I40E_SUCCESS;
6244         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6245                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6246
6247                 /**
6248                  * If vlan_num is 0, that's the first time to add mac,
6249                  * set mask for vlan_id 0.
6250                  */
6251                 if (vsi->vlan_num == 0) {
6252                         i40e_set_vlan_filter(vsi, 0, 1);
6253                         vsi->vlan_num = 1;
6254                 }
6255                 vlan_num = vsi->vlan_num;
6256         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6257                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6258                 vlan_num = 1;
6259
6260         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6261         if (mv_f == NULL) {
6262                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6263                 return I40E_ERR_NO_MEMORY;
6264         }
6265
6266         for (i = 0; i < vlan_num; i++) {
6267                 mv_f[i].filter_type = mac_filter->filter_type;
6268                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6269                                 ETH_ADDR_LEN);
6270         }
6271
6272         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6273                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6274                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6275                                         &mac_filter->mac_addr);
6276                 if (ret != I40E_SUCCESS)
6277                         goto DONE;
6278         }
6279
6280         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6281         if (ret != I40E_SUCCESS)
6282                 goto DONE;
6283
6284         /* Add the mac addr into mac list */
6285         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6286         if (f == NULL) {
6287                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6288                 ret = I40E_ERR_NO_MEMORY;
6289                 goto DONE;
6290         }
6291         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6292                         ETH_ADDR_LEN);
6293         f->mac_info.filter_type = mac_filter->filter_type;
6294         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6295         vsi->mac_num++;
6296
6297         ret = I40E_SUCCESS;
6298 DONE:
6299         rte_free(mv_f);
6300
6301         return ret;
6302 }
6303
6304 int
6305 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6306 {
6307         struct i40e_mac_filter *f;
6308         struct i40e_macvlan_filter *mv_f;
6309         int i, vlan_num;
6310         enum rte_mac_filter_type filter_type;
6311         int ret = I40E_SUCCESS;
6312
6313         /* Can't find it, return an error */
6314         f = i40e_find_mac_filter(vsi, addr);
6315         if (f == NULL)
6316                 return I40E_ERR_PARAM;
6317
6318         vlan_num = vsi->vlan_num;
6319         filter_type = f->mac_info.filter_type;
6320         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6321                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6322                 if (vlan_num == 0) {
6323                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6324                         return I40E_ERR_PARAM;
6325                 }
6326         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6327                         filter_type == RTE_MAC_HASH_MATCH)
6328                 vlan_num = 1;
6329
6330         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6331         if (mv_f == NULL) {
6332                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6333                 return I40E_ERR_NO_MEMORY;
6334         }
6335
6336         for (i = 0; i < vlan_num; i++) {
6337                 mv_f[i].filter_type = filter_type;
6338                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6339                                 ETH_ADDR_LEN);
6340         }
6341         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6342                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6343                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6344                 if (ret != I40E_SUCCESS)
6345                         goto DONE;
6346         }
6347
6348         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6349         if (ret != I40E_SUCCESS)
6350                 goto DONE;
6351
6352         /* Remove the mac addr into mac list */
6353         TAILQ_REMOVE(&vsi->mac_list, f, next);
6354         rte_free(f);
6355         vsi->mac_num--;
6356
6357         ret = I40E_SUCCESS;
6358 DONE:
6359         rte_free(mv_f);
6360         return ret;
6361 }
6362
6363 /* Configure hash enable flags for RSS */
6364 uint64_t
6365 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6366 {
6367         uint64_t hena = 0;
6368
6369         if (!flags)
6370                 return hena;
6371
6372         if (flags & ETH_RSS_FRAG_IPV4)
6373                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6374         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6375                 if (type == I40E_MAC_X722) {
6376                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6377                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6378                 } else
6379                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6380         }
6381         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6382                 if (type == I40E_MAC_X722) {
6383                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6384                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6385                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6386                 } else
6387                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6388         }
6389         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6390                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6391         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6392                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6393         if (flags & ETH_RSS_FRAG_IPV6)
6394                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6395         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6396                 if (type == I40E_MAC_X722) {
6397                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6398                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6399                 } else
6400                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6401         }
6402         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6403                 if (type == I40E_MAC_X722) {
6404                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6405                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6406                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6407                 } else
6408                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6409         }
6410         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6411                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6412         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6413                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6414         if (flags & ETH_RSS_L2_PAYLOAD)
6415                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6416
6417         return hena;
6418 }
6419
6420 /* Parse the hash enable flags */
6421 uint64_t
6422 i40e_parse_hena(uint64_t flags)
6423 {
6424         uint64_t rss_hf = 0;
6425
6426         if (!flags)
6427                 return rss_hf;
6428         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6429                 rss_hf |= ETH_RSS_FRAG_IPV4;
6430         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6431                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6432         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6433                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6434         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6435                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6436         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6437                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6438         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6439                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6440         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6441                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6442         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6443                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6444         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6445                 rss_hf |= ETH_RSS_FRAG_IPV6;
6446         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6447                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6448         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6449                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6450         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6451                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6452         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6453                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6454         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6455                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6456         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6457                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6458         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6459                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6460         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6461                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6462
6463         return rss_hf;
6464 }
6465
6466 /* Disable RSS */
6467 static void
6468 i40e_pf_disable_rss(struct i40e_pf *pf)
6469 {
6470         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6471         uint64_t hena;
6472
6473         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6474         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6475         if (hw->mac.type == I40E_MAC_X722)
6476                 hena &= ~I40E_RSS_HENA_ALL_X722;
6477         else
6478                 hena &= ~I40E_RSS_HENA_ALL;
6479         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6480         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6481         I40E_WRITE_FLUSH(hw);
6482 }
6483
6484 static int
6485 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6486 {
6487         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6488         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6489         int ret = 0;
6490
6491         if (!key || key_len == 0) {
6492                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6493                 return 0;
6494         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6495                 sizeof(uint32_t)) {
6496                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6497                 return -EINVAL;
6498         }
6499
6500         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6501                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6502                         (struct i40e_aqc_get_set_rss_key_data *)key;
6503
6504                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6505                 if (ret)
6506                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6507                                      "via AQ");
6508         } else {
6509                 uint32_t *hash_key = (uint32_t *)key;
6510                 uint16_t i;
6511
6512                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6513                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6514                 I40E_WRITE_FLUSH(hw);
6515         }
6516
6517         return ret;
6518 }
6519
6520 static int
6521 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6522 {
6523         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6524         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6525         int ret;
6526
6527         if (!key || !key_len)
6528                 return -EINVAL;
6529
6530         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6531                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6532                         (struct i40e_aqc_get_set_rss_key_data *)key);
6533                 if (ret) {
6534                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6535                         return ret;
6536                 }
6537         } else {
6538                 uint32_t *key_dw = (uint32_t *)key;
6539                 uint16_t i;
6540
6541                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6542                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6543         }
6544         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6545
6546         return 0;
6547 }
6548
6549 static int
6550 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6551 {
6552         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6553         uint64_t rss_hf;
6554         uint64_t hena;
6555         int ret;
6556
6557         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6558                                rss_conf->rss_key_len);
6559         if (ret)
6560                 return ret;
6561
6562         rss_hf = rss_conf->rss_hf;
6563         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6564         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6565         if (hw->mac.type == I40E_MAC_X722)
6566                 hena &= ~I40E_RSS_HENA_ALL_X722;
6567         else
6568                 hena &= ~I40E_RSS_HENA_ALL;
6569         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6570         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6571         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6572         I40E_WRITE_FLUSH(hw);
6573
6574         return 0;
6575 }
6576
6577 static int
6578 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6579                          struct rte_eth_rss_conf *rss_conf)
6580 {
6581         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6582         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6583         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6584         uint64_t hena;
6585
6586         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6587         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6588         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6589                  ? I40E_RSS_HENA_ALL_X722
6590                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6591                 if (rss_hf != 0) /* Enable RSS */
6592                         return -EINVAL;
6593                 return 0; /* Nothing to do */
6594         }
6595         /* RSS enabled */
6596         if (rss_hf == 0) /* Disable RSS */
6597                 return -EINVAL;
6598
6599         return i40e_hw_rss_hash_set(pf, rss_conf);
6600 }
6601
6602 static int
6603 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6604                            struct rte_eth_rss_conf *rss_conf)
6605 {
6606         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6607         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6608         uint64_t hena;
6609
6610         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6611                          &rss_conf->rss_key_len);
6612
6613         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6614         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6615         rss_conf->rss_hf = i40e_parse_hena(hena);
6616
6617         return 0;
6618 }
6619
6620 static int
6621 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6622 {
6623         switch (filter_type) {
6624         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6625                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6626                 break;
6627         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6628                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6629                 break;
6630         case RTE_TUNNEL_FILTER_IMAC_TENID:
6631                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6632                 break;
6633         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6634                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6635                 break;
6636         case ETH_TUNNEL_FILTER_IMAC:
6637                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6638                 break;
6639         case ETH_TUNNEL_FILTER_OIP:
6640                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6641                 break;
6642         case ETH_TUNNEL_FILTER_IIP:
6643                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6644                 break;
6645         default:
6646                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6647                 return -EINVAL;
6648         }
6649
6650         return 0;
6651 }
6652
6653 /* Convert tunnel filter structure */
6654 static int
6655 i40e_tunnel_filter_convert(struct i40e_aqc_add_remove_cloud_filters_element_data
6656                            *cld_filter,
6657                            struct i40e_tunnel_filter *tunnel_filter)
6658 {
6659         ether_addr_copy((struct ether_addr *)&cld_filter->outer_mac,
6660                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6661         ether_addr_copy((struct ether_addr *)&cld_filter->inner_mac,
6662                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6663         tunnel_filter->input.inner_vlan = cld_filter->inner_vlan;
6664         tunnel_filter->input.flags = cld_filter->flags;
6665         tunnel_filter->input.tenant_id = cld_filter->tenant_id;
6666         tunnel_filter->queue = cld_filter->queue_number;
6667
6668         return 0;
6669 }
6670
6671 /* Check if there exists the tunnel filter */
6672 struct i40e_tunnel_filter *
6673 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6674                              const struct i40e_tunnel_filter_input *input)
6675 {
6676         int ret;
6677
6678         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6679         if (ret < 0)
6680                 return NULL;
6681
6682         return tunnel_rule->hash_map[ret];
6683 }
6684
6685 /* Add a tunnel filter into the SW list */
6686 static int
6687 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6688                              struct i40e_tunnel_filter *tunnel_filter)
6689 {
6690         struct i40e_tunnel_rule *rule = &pf->tunnel;
6691         int ret;
6692
6693         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6694         if (ret < 0) {
6695                 PMD_DRV_LOG(ERR,
6696                             "Failed to insert tunnel filter to hash table %d!",
6697                             ret);
6698                 return ret;
6699         }
6700         rule->hash_map[ret] = tunnel_filter;
6701
6702         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6703
6704         return 0;
6705 }
6706
6707 /* Delete a tunnel filter from the SW list */
6708 int
6709 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6710                           struct i40e_tunnel_filter_input *input)
6711 {
6712         struct i40e_tunnel_rule *rule = &pf->tunnel;
6713         struct i40e_tunnel_filter *tunnel_filter;
6714         int ret;
6715
6716         ret = rte_hash_del_key(rule->hash_table, input);
6717         if (ret < 0) {
6718                 PMD_DRV_LOG(ERR,
6719                             "Failed to delete tunnel filter to hash table %d!",
6720                             ret);
6721                 return ret;
6722         }
6723         tunnel_filter = rule->hash_map[ret];
6724         rule->hash_map[ret] = NULL;
6725
6726         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6727         rte_free(tunnel_filter);
6728
6729         return 0;
6730 }
6731
6732 int
6733 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6734                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6735                         uint8_t add)
6736 {
6737         uint16_t ip_type;
6738         uint32_t ipv4_addr;
6739         uint8_t i, tun_type = 0;
6740         /* internal varialbe to convert ipv6 byte order */
6741         uint32_t convert_ipv6[4];
6742         int val, ret = 0;
6743         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6744         struct i40e_vsi *vsi = pf->main_vsi;
6745         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6746         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6747         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6748         struct i40e_tunnel_filter *tunnel, *node;
6749         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6750
6751         cld_filter = rte_zmalloc("tunnel_filter",
6752                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6753                 0);
6754
6755         if (NULL == cld_filter) {
6756                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6757                 return -EINVAL;
6758         }
6759         pfilter = cld_filter;
6760
6761         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6762         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6763
6764         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6765         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6766                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6767                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6768                 rte_memcpy(&pfilter->ipaddr.v4.data,
6769                                 &rte_cpu_to_le_32(ipv4_addr),
6770                                 sizeof(pfilter->ipaddr.v4.data));
6771         } else {
6772                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6773                 for (i = 0; i < 4; i++) {
6774                         convert_ipv6[i] =
6775                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6776                 }
6777                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6778                                 sizeof(pfilter->ipaddr.v6.data));
6779         }
6780
6781         /* check tunneled type */
6782         switch (tunnel_filter->tunnel_type) {
6783         case RTE_TUNNEL_TYPE_VXLAN:
6784                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6785                 break;
6786         case RTE_TUNNEL_TYPE_NVGRE:
6787                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6788                 break;
6789         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6790                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6791                 break;
6792         default:
6793                 /* Other tunnel types is not supported. */
6794                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6795                 rte_free(cld_filter);
6796                 return -EINVAL;
6797         }
6798
6799         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6800                                                 &pfilter->flags);
6801         if (val < 0) {
6802                 rte_free(cld_filter);
6803                 return -EINVAL;
6804         }
6805
6806         pfilter->flags |= rte_cpu_to_le_16(
6807                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6808                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6809         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6810         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6811
6812         /* Check if there is the filter in SW list */
6813         memset(&check_filter, 0, sizeof(check_filter));
6814         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6815         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6816         if (add && node) {
6817                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6818                 return -EINVAL;
6819         }
6820
6821         if (!add && !node) {
6822                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6823                 return -EINVAL;
6824         }
6825
6826         if (add) {
6827                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6828                 if (ret < 0) {
6829                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6830                         return ret;
6831                 }
6832                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6833                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6834                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6835         } else {
6836                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6837                                                    cld_filter, 1);
6838                 if (ret < 0) {
6839                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6840                         return ret;
6841                 }
6842                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6843         }
6844
6845         rte_free(cld_filter);
6846         return ret;
6847 }
6848
6849 static int
6850 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6851 {
6852         uint8_t i;
6853
6854         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6855                 if (pf->vxlan_ports[i] == port)
6856                         return i;
6857         }
6858
6859         return -1;
6860 }
6861
6862 static int
6863 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6864 {
6865         int  idx, ret;
6866         uint8_t filter_idx;
6867         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6868
6869         idx = i40e_get_vxlan_port_idx(pf, port);
6870
6871         /* Check if port already exists */
6872         if (idx >= 0) {
6873                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6874                 return -EINVAL;
6875         }
6876
6877         /* Now check if there is space to add the new port */
6878         idx = i40e_get_vxlan_port_idx(pf, 0);
6879         if (idx < 0) {
6880                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6881                         "not adding port %d", port);
6882                 return -ENOSPC;
6883         }
6884
6885         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6886                                         &filter_idx, NULL);
6887         if (ret < 0) {
6888                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6889                 return -1;
6890         }
6891
6892         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6893                          port,  filter_idx);
6894
6895         /* New port: add it and mark its index in the bitmap */
6896         pf->vxlan_ports[idx] = port;
6897         pf->vxlan_bitmap |= (1 << idx);
6898
6899         if (!(pf->flags & I40E_FLAG_VXLAN))
6900                 pf->flags |= I40E_FLAG_VXLAN;
6901
6902         return 0;
6903 }
6904
6905 static int
6906 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6907 {
6908         int idx;
6909         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6910
6911         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6912                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6913                 return -EINVAL;
6914         }
6915
6916         idx = i40e_get_vxlan_port_idx(pf, port);
6917
6918         if (idx < 0) {
6919                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6920                 return -EINVAL;
6921         }
6922
6923         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6924                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6925                 return -1;
6926         }
6927
6928         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6929                         port, idx);
6930
6931         pf->vxlan_ports[idx] = 0;
6932         pf->vxlan_bitmap &= ~(1 << idx);
6933
6934         if (!pf->vxlan_bitmap)
6935                 pf->flags &= ~I40E_FLAG_VXLAN;
6936
6937         return 0;
6938 }
6939
6940 /* Add UDP tunneling port */
6941 static int
6942 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6943                              struct rte_eth_udp_tunnel *udp_tunnel)
6944 {
6945         int ret = 0;
6946         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6947
6948         if (udp_tunnel == NULL)
6949                 return -EINVAL;
6950
6951         switch (udp_tunnel->prot_type) {
6952         case RTE_TUNNEL_TYPE_VXLAN:
6953                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6954                 break;
6955
6956         case RTE_TUNNEL_TYPE_GENEVE:
6957         case RTE_TUNNEL_TYPE_TEREDO:
6958                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6959                 ret = -1;
6960                 break;
6961
6962         default:
6963                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6964                 ret = -1;
6965                 break;
6966         }
6967
6968         return ret;
6969 }
6970
6971 /* Remove UDP tunneling port */
6972 static int
6973 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6974                              struct rte_eth_udp_tunnel *udp_tunnel)
6975 {
6976         int ret = 0;
6977         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6978
6979         if (udp_tunnel == NULL)
6980                 return -EINVAL;
6981
6982         switch (udp_tunnel->prot_type) {
6983         case RTE_TUNNEL_TYPE_VXLAN:
6984                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6985                 break;
6986         case RTE_TUNNEL_TYPE_GENEVE:
6987         case RTE_TUNNEL_TYPE_TEREDO:
6988                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6989                 ret = -1;
6990                 break;
6991         default:
6992                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6993                 ret = -1;
6994                 break;
6995         }
6996
6997         return ret;
6998 }
6999
7000 /* Calculate the maximum number of contiguous PF queues that are configured */
7001 static int
7002 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7003 {
7004         struct rte_eth_dev_data *data = pf->dev_data;
7005         int i, num;
7006         struct i40e_rx_queue *rxq;
7007
7008         num = 0;
7009         for (i = 0; i < pf->lan_nb_qps; i++) {
7010                 rxq = data->rx_queues[i];
7011                 if (rxq && rxq->q_set)
7012                         num++;
7013                 else
7014                         break;
7015         }
7016
7017         return num;
7018 }
7019
7020 /* Configure RSS */
7021 static int
7022 i40e_pf_config_rss(struct i40e_pf *pf)
7023 {
7024         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7025         struct rte_eth_rss_conf rss_conf;
7026         uint32_t i, lut = 0;
7027         uint16_t j, num;
7028
7029         /*
7030          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7031          * It's necessary to calulate the actual PF queues that are configured.
7032          */
7033         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7034                 num = i40e_pf_calc_configured_queues_num(pf);
7035         else
7036                 num = pf->dev_data->nb_rx_queues;
7037
7038         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7039         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7040                         num);
7041
7042         if (num == 0) {
7043                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7044                 return -ENOTSUP;
7045         }
7046
7047         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7048                 if (j == num)
7049                         j = 0;
7050                 lut = (lut << 8) | (j & ((0x1 <<
7051                         hw->func_caps.rss_table_entry_width) - 1));
7052                 if ((i & 3) == 3)
7053                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7054         }
7055
7056         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7057         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7058                 i40e_pf_disable_rss(pf);
7059                 return 0;
7060         }
7061         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7062                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7063                 /* Random default keys */
7064                 static uint32_t rss_key_default[] = {0x6b793944,
7065                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7066                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7067                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7068
7069                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7070                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7071                                                         sizeof(uint32_t);
7072         }
7073
7074         return i40e_hw_rss_hash_set(pf, &rss_conf);
7075 }
7076
7077 static int
7078 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7079                                struct rte_eth_tunnel_filter_conf *filter)
7080 {
7081         if (pf == NULL || filter == NULL) {
7082                 PMD_DRV_LOG(ERR, "Invalid parameter");
7083                 return -EINVAL;
7084         }
7085
7086         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7087                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7088                 return -EINVAL;
7089         }
7090
7091         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7092                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7093                 return -EINVAL;
7094         }
7095
7096         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7097                 (is_zero_ether_addr(&filter->outer_mac))) {
7098                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7099                 return -EINVAL;
7100         }
7101
7102         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7103                 (is_zero_ether_addr(&filter->inner_mac))) {
7104                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7105                 return -EINVAL;
7106         }
7107
7108         return 0;
7109 }
7110
7111 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7112 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7113 static int
7114 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7115 {
7116         uint32_t val, reg;
7117         int ret = -EINVAL;
7118
7119         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7120         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
7121
7122         if (len == 3) {
7123                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7124         } else if (len == 4) {
7125                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7126         } else {
7127                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7128                 return ret;
7129         }
7130
7131         if (reg != val) {
7132                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7133                                                    reg, NULL);
7134                 if (ret != 0)
7135                         return ret;
7136         } else {
7137                 ret = 0;
7138         }
7139         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
7140                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7141
7142         return ret;
7143 }
7144
7145 static int
7146 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7147 {
7148         int ret = -EINVAL;
7149
7150         if (!hw || !cfg)
7151                 return -EINVAL;
7152
7153         switch (cfg->cfg_type) {
7154         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7155                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7156                 break;
7157         default:
7158                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7159                 break;
7160         }
7161
7162         return ret;
7163 }
7164
7165 static int
7166 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7167                                enum rte_filter_op filter_op,
7168                                void *arg)
7169 {
7170         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7171         int ret = I40E_ERR_PARAM;
7172
7173         switch (filter_op) {
7174         case RTE_ETH_FILTER_SET:
7175                 ret = i40e_dev_global_config_set(hw,
7176                         (struct rte_eth_global_cfg *)arg);
7177                 break;
7178         default:
7179                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7180                 break;
7181         }
7182
7183         return ret;
7184 }
7185
7186 static int
7187 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7188                           enum rte_filter_op filter_op,
7189                           void *arg)
7190 {
7191         struct rte_eth_tunnel_filter_conf *filter;
7192         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7193         int ret = I40E_SUCCESS;
7194
7195         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7196
7197         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7198                 return I40E_ERR_PARAM;
7199
7200         switch (filter_op) {
7201         case RTE_ETH_FILTER_NOP:
7202                 if (!(pf->flags & I40E_FLAG_VXLAN))
7203                         ret = I40E_NOT_SUPPORTED;
7204                 break;
7205         case RTE_ETH_FILTER_ADD:
7206                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7207                 break;
7208         case RTE_ETH_FILTER_DELETE:
7209                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7210                 break;
7211         default:
7212                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7213                 ret = I40E_ERR_PARAM;
7214                 break;
7215         }
7216
7217         return ret;
7218 }
7219
7220 static int
7221 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7222 {
7223         int ret = 0;
7224         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7225
7226         /* RSS setup */
7227         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7228                 ret = i40e_pf_config_rss(pf);
7229         else
7230                 i40e_pf_disable_rss(pf);
7231
7232         return ret;
7233 }
7234
7235 /* Get the symmetric hash enable configurations per port */
7236 static void
7237 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7238 {
7239         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7240
7241         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7242 }
7243
7244 /* Set the symmetric hash enable configurations per port */
7245 static void
7246 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7247 {
7248         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7249
7250         if (enable > 0) {
7251                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7252                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
7253                                                         "been enabled");
7254                         return;
7255                 }
7256                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7257         } else {
7258                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7259                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
7260                                                         "been disabled");
7261                         return;
7262                 }
7263                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7264         }
7265         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7266         I40E_WRITE_FLUSH(hw);
7267 }
7268
7269 /*
7270  * Get global configurations of hash function type and symmetric hash enable
7271  * per flow type (pctype). Note that global configuration means it affects all
7272  * the ports on the same NIC.
7273  */
7274 static int
7275 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7276                                    struct rte_eth_hash_global_conf *g_cfg)
7277 {
7278         uint32_t reg, mask = I40E_FLOW_TYPES;
7279         uint16_t i;
7280         enum i40e_filter_pctype pctype;
7281
7282         memset(g_cfg, 0, sizeof(*g_cfg));
7283         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7284         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7285                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7286         else
7287                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7288         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7289                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7290
7291         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7292                 if (!(mask & (1UL << i)))
7293                         continue;
7294                 mask &= ~(1UL << i);
7295                 /* Bit set indicats the coresponding flow type is supported */
7296                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7297                 /* if flowtype is invalid, continue */
7298                 if (!I40E_VALID_FLOW(i))
7299                         continue;
7300                 pctype = i40e_flowtype_to_pctype(i);
7301                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7302                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7303                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7304         }
7305
7306         return 0;
7307 }
7308
7309 static int
7310 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7311 {
7312         uint32_t i;
7313         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7314
7315         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7316                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7317                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7318                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7319                                                 g_cfg->hash_func);
7320                 return -EINVAL;
7321         }
7322
7323         /*
7324          * As i40e supports less than 32 flow types, only first 32 bits need to
7325          * be checked.
7326          */
7327         mask0 = g_cfg->valid_bit_mask[0];
7328         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7329                 if (i == 0) {
7330                         /* Check if any unsupported flow type configured */
7331                         if ((mask0 | i40e_mask) ^ i40e_mask)
7332                                 goto mask_err;
7333                 } else {
7334                         if (g_cfg->valid_bit_mask[i])
7335                                 goto mask_err;
7336                 }
7337         }
7338
7339         return 0;
7340
7341 mask_err:
7342         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7343
7344         return -EINVAL;
7345 }
7346
7347 /*
7348  * Set global configurations of hash function type and symmetric hash enable
7349  * per flow type (pctype). Note any modifying global configuration will affect
7350  * all the ports on the same NIC.
7351  */
7352 static int
7353 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7354                                    struct rte_eth_hash_global_conf *g_cfg)
7355 {
7356         int ret;
7357         uint16_t i;
7358         uint32_t reg;
7359         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7360         enum i40e_filter_pctype pctype;
7361
7362         /* Check the input parameters */
7363         ret = i40e_hash_global_config_check(g_cfg);
7364         if (ret < 0)
7365                 return ret;
7366
7367         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7368                 if (!(mask0 & (1UL << i)))
7369                         continue;
7370                 mask0 &= ~(1UL << i);
7371                 /* if flowtype is invalid, continue */
7372                 if (!I40E_VALID_FLOW(i))
7373                         continue;
7374                 pctype = i40e_flowtype_to_pctype(i);
7375                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7376                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7377                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7378         }
7379
7380         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7381         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7382                 /* Toeplitz */
7383                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7384                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7385                                                                 "Toeplitz");
7386                         goto out;
7387                 }
7388                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7389         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7390                 /* Simple XOR */
7391                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7392                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7393                                                         "Simple XOR");
7394                         goto out;
7395                 }
7396                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7397         } else
7398                 /* Use the default, and keep it as it is */
7399                 goto out;
7400
7401         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7402
7403 out:
7404         I40E_WRITE_FLUSH(hw);
7405
7406         return 0;
7407 }
7408
7409 /**
7410  * Valid input sets for hash and flow director filters per PCTYPE
7411  */
7412 static uint64_t
7413 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7414                 enum rte_filter_type filter)
7415 {
7416         uint64_t valid;
7417
7418         static const uint64_t valid_hash_inset_table[] = {
7419                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7420                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7421                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7422                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7423                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7424                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7425                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7426                         I40E_INSET_FLEX_PAYLOAD,
7427                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7428                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7429                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7430                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7431                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7432                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7433                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7434                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7435                         I40E_INSET_FLEX_PAYLOAD,
7436                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7437                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7438                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7439                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7440                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7441                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7442                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7443                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7444                         I40E_INSET_FLEX_PAYLOAD,
7445                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7446                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7447                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7448                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7449                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7450                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7451                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7452                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7453                         I40E_INSET_FLEX_PAYLOAD,
7454                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7455                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7456                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7457                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7458                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7459                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7460                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7461                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7462                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7463                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7464                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7465                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7466                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7467                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7468                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7469                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7470                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7471                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7472                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7473                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7474                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7475                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7476                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7477                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7478                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7479                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7480                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7481                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7482                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7483                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7484                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7485                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7486                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7487                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7488                         I40E_INSET_FLEX_PAYLOAD,
7489                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7490                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7491                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7492                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7493                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7494                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7495                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7496                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7497                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7498                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7499                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7500                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7501                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7502                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7503                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7504                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7505                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7506                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7507                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7508                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7509                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7510                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7511                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7512                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7513                         I40E_INSET_FLEX_PAYLOAD,
7514                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7515                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7516                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7517                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7518                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7519                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7520                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7521                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7522                         I40E_INSET_FLEX_PAYLOAD,
7523                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7524                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7525                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7526                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7527                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7528                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7529                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7530                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7531                         I40E_INSET_FLEX_PAYLOAD,
7532                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7533                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7534                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7535                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7536                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7537                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7538                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7539                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7540                         I40E_INSET_FLEX_PAYLOAD,
7541                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7542                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7543                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7544                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7545                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7546                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7547                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7548                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7549                         I40E_INSET_FLEX_PAYLOAD,
7550                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7551                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7552                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7553                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7554                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7555                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7556                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7557                         I40E_INSET_FLEX_PAYLOAD,
7558                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7559                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7560                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7561                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7562                         I40E_INSET_FLEX_PAYLOAD,
7563         };
7564
7565         /**
7566          * Flow director supports only fields defined in
7567          * union rte_eth_fdir_flow.
7568          */
7569         static const uint64_t valid_fdir_inset_table[] = {
7570                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7571                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7572                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7573                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7574                 I40E_INSET_IPV4_TTL,
7575                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7576                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7577                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7578                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7579                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7580                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7581                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7582                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7583                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7584                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7585                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7586                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7587                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7588                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7589                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7590                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7591                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7592                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7593                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7594                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7595                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7596                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7597                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7598                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7599                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7600                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7601                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7602                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7603                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7604                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7605                 I40E_INSET_SCTP_VT,
7606                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7607                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7608                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7609                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7610                 I40E_INSET_IPV4_TTL,
7611                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7612                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7613                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7614                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7615                 I40E_INSET_IPV6_HOP_LIMIT,
7616                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7617                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7618                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7619                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7620                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7621                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7622                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7623                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7624                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7625                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7626                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7627                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7628                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7629                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7630                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7631                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7632                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7633                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7634                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7635                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7636                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7637                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7638                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7639                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7640                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7641                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7642                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7643                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7644                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7645                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7646                 I40E_INSET_SCTP_VT,
7647                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7648                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7649                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7650                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7651                 I40E_INSET_IPV6_HOP_LIMIT,
7652                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7653                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7654                 I40E_INSET_LAST_ETHER_TYPE,
7655         };
7656
7657         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7658                 return 0;
7659         if (filter == RTE_ETH_FILTER_HASH)
7660                 valid = valid_hash_inset_table[pctype];
7661         else
7662                 valid = valid_fdir_inset_table[pctype];
7663
7664         return valid;
7665 }
7666
7667 /**
7668  * Validate if the input set is allowed for a specific PCTYPE
7669  */
7670 static int
7671 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7672                 enum rte_filter_type filter, uint64_t inset)
7673 {
7674         uint64_t valid;
7675
7676         valid = i40e_get_valid_input_set(pctype, filter);
7677         if (inset & (~valid))
7678                 return -EINVAL;
7679
7680         return 0;
7681 }
7682
7683 /* default input set fields combination per pctype */
7684 uint64_t
7685 i40e_get_default_input_set(uint16_t pctype)
7686 {
7687         static const uint64_t default_inset_table[] = {
7688                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7689                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7690                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7691                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7692                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7693                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7694                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7695                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7696                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7697                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7698                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7699                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7700                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7701                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7702                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7703                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7704                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7705                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7706                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7707                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7708                         I40E_INSET_SCTP_VT,
7709                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7710                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7711                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7712                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7713                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7714                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7715                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7716                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7717                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7718                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7719                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7720                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7721                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7722                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7723                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7724                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7725                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7726                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7727                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7728                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7729                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7730                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7731                         I40E_INSET_SCTP_VT,
7732                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7733                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7734                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7735                         I40E_INSET_LAST_ETHER_TYPE,
7736         };
7737
7738         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7739                 return 0;
7740
7741         return default_inset_table[pctype];
7742 }
7743
7744 /**
7745  * Parse the input set from index to logical bit masks
7746  */
7747 static int
7748 i40e_parse_input_set(uint64_t *inset,
7749                      enum i40e_filter_pctype pctype,
7750                      enum rte_eth_input_set_field *field,
7751                      uint16_t size)
7752 {
7753         uint16_t i, j;
7754         int ret = -EINVAL;
7755
7756         static const struct {
7757                 enum rte_eth_input_set_field field;
7758                 uint64_t inset;
7759         } inset_convert_table[] = {
7760                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7761                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7762                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7763                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7764                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7765                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7766                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7767                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7768                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7769                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7770                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7771                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7772                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7773                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7774                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7775                         I40E_INSET_IPV6_NEXT_HDR},
7776                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7777                         I40E_INSET_IPV6_HOP_LIMIT},
7778                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7779                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7780                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7781                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7782                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7783                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7784                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7785                         I40E_INSET_SCTP_VT},
7786                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7787                         I40E_INSET_TUNNEL_DMAC},
7788                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7789                         I40E_INSET_VLAN_TUNNEL},
7790                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7791                         I40E_INSET_TUNNEL_ID},
7792                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7793                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7794                         I40E_INSET_FLEX_PAYLOAD_W1},
7795                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7796                         I40E_INSET_FLEX_PAYLOAD_W2},
7797                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7798                         I40E_INSET_FLEX_PAYLOAD_W3},
7799                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7800                         I40E_INSET_FLEX_PAYLOAD_W4},
7801                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7802                         I40E_INSET_FLEX_PAYLOAD_W5},
7803                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7804                         I40E_INSET_FLEX_PAYLOAD_W6},
7805                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7806                         I40E_INSET_FLEX_PAYLOAD_W7},
7807                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7808                         I40E_INSET_FLEX_PAYLOAD_W8},
7809         };
7810
7811         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7812                 return ret;
7813
7814         /* Only one item allowed for default or all */
7815         if (size == 1) {
7816                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7817                         *inset = i40e_get_default_input_set(pctype);
7818                         return 0;
7819                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7820                         *inset = I40E_INSET_NONE;
7821                         return 0;
7822                 }
7823         }
7824
7825         for (i = 0, *inset = 0; i < size; i++) {
7826                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7827                         if (field[i] == inset_convert_table[j].field) {
7828                                 *inset |= inset_convert_table[j].inset;
7829                                 break;
7830                         }
7831                 }
7832
7833                 /* It contains unsupported input set, return immediately */
7834                 if (j == RTE_DIM(inset_convert_table))
7835                         return ret;
7836         }
7837
7838         return 0;
7839 }
7840
7841 /**
7842  * Translate the input set from bit masks to register aware bit masks
7843  * and vice versa
7844  */
7845 static uint64_t
7846 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7847 {
7848         uint64_t val = 0;
7849         uint16_t i;
7850
7851         struct inset_map {
7852                 uint64_t inset;
7853                 uint64_t inset_reg;
7854         };
7855
7856         static const struct inset_map inset_map_common[] = {
7857                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7858                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7859                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7860                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7861                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7862                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7863                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7864                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7865                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7866                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7867                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7868                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7869                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7870                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7871                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7872                 {I40E_INSET_TUNNEL_DMAC,
7873                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7874                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7875                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7876                 {I40E_INSET_TUNNEL_SRC_PORT,
7877                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7878                 {I40E_INSET_TUNNEL_DST_PORT,
7879                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7880                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7881                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7882                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7883                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7884                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7885                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7886                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7887                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7888                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7889         };
7890
7891     /* some different registers map in x722*/
7892         static const struct inset_map inset_map_diff_x722[] = {
7893                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7894                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7895                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7896                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7897         };
7898
7899         static const struct inset_map inset_map_diff_not_x722[] = {
7900                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7901                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7902                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7903                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7904         };
7905
7906         if (input == 0)
7907                 return val;
7908
7909         /* Translate input set to register aware inset */
7910         if (type == I40E_MAC_X722) {
7911                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7912                         if (input & inset_map_diff_x722[i].inset)
7913                                 val |= inset_map_diff_x722[i].inset_reg;
7914                 }
7915         } else {
7916                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7917                         if (input & inset_map_diff_not_x722[i].inset)
7918                                 val |= inset_map_diff_not_x722[i].inset_reg;
7919                 }
7920         }
7921
7922         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7923                 if (input & inset_map_common[i].inset)
7924                         val |= inset_map_common[i].inset_reg;
7925         }
7926
7927         return val;
7928 }
7929
7930 static int
7931 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7932 {
7933         uint8_t i, idx = 0;
7934         uint64_t inset_need_mask = inset;
7935
7936         static const struct {
7937                 uint64_t inset;
7938                 uint32_t mask;
7939         } inset_mask_map[] = {
7940                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7941                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7942                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7943                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7944                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7945                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7946                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7947                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7948         };
7949
7950         if (!inset || !mask || !nb_elem)
7951                 return 0;
7952
7953         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7954                 /* Clear the inset bit, if no MASK is required,
7955                  * for example proto + ttl
7956                  */
7957                 if ((inset & inset_mask_map[i].inset) ==
7958                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7959                         inset_need_mask &= ~inset_mask_map[i].inset;
7960                 if (!inset_need_mask)
7961                         return 0;
7962         }
7963         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7964                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7965                     inset_mask_map[i].inset) {
7966                         if (idx >= nb_elem) {
7967                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7968                                 return -EINVAL;
7969                         }
7970                         mask[idx] = inset_mask_map[i].mask;
7971                         idx++;
7972                 }
7973         }
7974
7975         return idx;
7976 }
7977
7978 static void
7979 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7980 {
7981         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7982
7983         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7984         if (reg != val)
7985                 i40e_write_rx_ctl(hw, addr, val);
7986         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7987                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7988 }
7989
7990 static void
7991 i40e_filter_input_set_init(struct i40e_pf *pf)
7992 {
7993         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7994         enum i40e_filter_pctype pctype;
7995         uint64_t input_set, inset_reg;
7996         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7997         int num, i;
7998
7999         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8000              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8001                 if (hw->mac.type == I40E_MAC_X722) {
8002                         if (!I40E_VALID_PCTYPE_X722(pctype))
8003                                 continue;
8004                 } else {
8005                         if (!I40E_VALID_PCTYPE(pctype))
8006                                 continue;
8007                 }
8008
8009                 input_set = i40e_get_default_input_set(pctype);
8010
8011                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8012                                                    I40E_INSET_MASK_NUM_REG);
8013                 if (num < 0)
8014                         return;
8015                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8016                                         input_set);
8017
8018                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8019                                       (uint32_t)(inset_reg & UINT32_MAX));
8020                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8021                                      (uint32_t)((inset_reg >>
8022                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8023                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8024                                       (uint32_t)(inset_reg & UINT32_MAX));
8025                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8026                                      (uint32_t)((inset_reg >>
8027                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8028
8029                 for (i = 0; i < num; i++) {
8030                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8031                                              mask_reg[i]);
8032                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8033                                              mask_reg[i]);
8034                 }
8035                 /*clear unused mask registers of the pctype */
8036                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8037                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8038                                              0);
8039                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8040                                              0);
8041                 }
8042                 I40E_WRITE_FLUSH(hw);
8043
8044                 /* store the default input set */
8045                 pf->hash_input_set[pctype] = input_set;
8046                 pf->fdir.input_set[pctype] = input_set;
8047         }
8048 }
8049
8050 int
8051 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8052                          struct rte_eth_input_set_conf *conf)
8053 {
8054         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8055         enum i40e_filter_pctype pctype;
8056         uint64_t input_set, inset_reg = 0;
8057         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8058         int ret, i, num;
8059
8060         if (!conf) {
8061                 PMD_DRV_LOG(ERR, "Invalid pointer");
8062                 return -EFAULT;
8063         }
8064         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8065             conf->op != RTE_ETH_INPUT_SET_ADD) {
8066                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8067                 return -EINVAL;
8068         }
8069
8070         if (!I40E_VALID_FLOW(conf->flow_type)) {
8071                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8072                 return -EINVAL;
8073         }
8074
8075         if (hw->mac.type == I40E_MAC_X722) {
8076                 /* get translated pctype value in fd pctype register */
8077                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8078                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8079                         conf->flow_type)));
8080         } else
8081                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8082
8083         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8084                                    conf->inset_size);
8085         if (ret) {
8086                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8087                 return -EINVAL;
8088         }
8089         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8090                                     input_set) != 0) {
8091                 PMD_DRV_LOG(ERR, "Invalid input set");
8092                 return -EINVAL;
8093         }
8094         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8095                 /* get inset value in register */
8096                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8097                 inset_reg <<= I40E_32_BIT_WIDTH;
8098                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8099                 input_set |= pf->hash_input_set[pctype];
8100         }
8101         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8102                                            I40E_INSET_MASK_NUM_REG);
8103         if (num < 0)
8104                 return -EINVAL;
8105
8106         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8107
8108         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8109                               (uint32_t)(inset_reg & UINT32_MAX));
8110         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8111                              (uint32_t)((inset_reg >>
8112                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8113
8114         for (i = 0; i < num; i++)
8115                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8116                                      mask_reg[i]);
8117         /*clear unused mask registers of the pctype */
8118         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8119                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8120                                      0);
8121         I40E_WRITE_FLUSH(hw);
8122
8123         pf->hash_input_set[pctype] = input_set;
8124         return 0;
8125 }
8126
8127 int
8128 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8129                          struct rte_eth_input_set_conf *conf)
8130 {
8131         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8132         enum i40e_filter_pctype pctype;
8133         uint64_t input_set, inset_reg = 0;
8134         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8135         int ret, i, num;
8136
8137         if (!hw || !conf) {
8138                 PMD_DRV_LOG(ERR, "Invalid pointer");
8139                 return -EFAULT;
8140         }
8141         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8142             conf->op != RTE_ETH_INPUT_SET_ADD) {
8143                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8144                 return -EINVAL;
8145         }
8146
8147         if (!I40E_VALID_FLOW(conf->flow_type)) {
8148                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8149                 return -EINVAL;
8150         }
8151
8152         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8153
8154         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8155                                    conf->inset_size);
8156         if (ret) {
8157                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8158                 return -EINVAL;
8159         }
8160         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8161                                     input_set) != 0) {
8162                 PMD_DRV_LOG(ERR, "Invalid input set");
8163                 return -EINVAL;
8164         }
8165
8166         /* get inset value in register */
8167         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8168         inset_reg <<= I40E_32_BIT_WIDTH;
8169         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8170
8171         /* Can not change the inset reg for flex payload for fdir,
8172          * it is done by writing I40E_PRTQF_FD_FLXINSET
8173          * in i40e_set_flex_mask_on_pctype.
8174          */
8175         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8176                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8177         else
8178                 input_set |= pf->fdir.input_set[pctype];
8179         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8180                                            I40E_INSET_MASK_NUM_REG);
8181         if (num < 0)
8182                 return -EINVAL;
8183
8184         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8185
8186         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8187                               (uint32_t)(inset_reg & UINT32_MAX));
8188         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8189                              (uint32_t)((inset_reg >>
8190                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8191
8192         for (i = 0; i < num; i++)
8193                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8194                                      mask_reg[i]);
8195         /*clear unused mask registers of the pctype */
8196         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8197                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8198                                      0);
8199         I40E_WRITE_FLUSH(hw);
8200
8201         pf->fdir.input_set[pctype] = input_set;
8202         return 0;
8203 }
8204
8205 static int
8206 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8207 {
8208         int ret = 0;
8209
8210         if (!hw || !info) {
8211                 PMD_DRV_LOG(ERR, "Invalid pointer");
8212                 return -EFAULT;
8213         }
8214
8215         switch (info->info_type) {
8216         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8217                 i40e_get_symmetric_hash_enable_per_port(hw,
8218                                         &(info->info.enable));
8219                 break;
8220         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8221                 ret = i40e_get_hash_filter_global_config(hw,
8222                                 &(info->info.global_conf));
8223                 break;
8224         default:
8225                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8226                                                         info->info_type);
8227                 ret = -EINVAL;
8228                 break;
8229         }
8230
8231         return ret;
8232 }
8233
8234 static int
8235 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8236 {
8237         int ret = 0;
8238
8239         if (!hw || !info) {
8240                 PMD_DRV_LOG(ERR, "Invalid pointer");
8241                 return -EFAULT;
8242         }
8243
8244         switch (info->info_type) {
8245         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8246                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8247                 break;
8248         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8249                 ret = i40e_set_hash_filter_global_config(hw,
8250                                 &(info->info.global_conf));
8251                 break;
8252         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8253                 ret = i40e_hash_filter_inset_select(hw,
8254                                                &(info->info.input_set_conf));
8255                 break;
8256
8257         default:
8258                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8259                                                         info->info_type);
8260                 ret = -EINVAL;
8261                 break;
8262         }
8263
8264         return ret;
8265 }
8266
8267 /* Operations for hash function */
8268 static int
8269 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8270                       enum rte_filter_op filter_op,
8271                       void *arg)
8272 {
8273         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8274         int ret = 0;
8275
8276         switch (filter_op) {
8277         case RTE_ETH_FILTER_NOP:
8278                 break;
8279         case RTE_ETH_FILTER_GET:
8280                 ret = i40e_hash_filter_get(hw,
8281                         (struct rte_eth_hash_filter_info *)arg);
8282                 break;
8283         case RTE_ETH_FILTER_SET:
8284                 ret = i40e_hash_filter_set(hw,
8285                         (struct rte_eth_hash_filter_info *)arg);
8286                 break;
8287         default:
8288                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8289                                                                 filter_op);
8290                 ret = -ENOTSUP;
8291                 break;
8292         }
8293
8294         return ret;
8295 }
8296
8297 /* Convert ethertype filter structure */
8298 static int
8299 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8300                               struct i40e_ethertype_filter *filter)
8301 {
8302         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8303         filter->input.ether_type = input->ether_type;
8304         filter->flags = input->flags;
8305         filter->queue = input->queue;
8306
8307         return 0;
8308 }
8309
8310 /* Check if there exists the ehtertype filter */
8311 struct i40e_ethertype_filter *
8312 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8313                                 const struct i40e_ethertype_filter_input *input)
8314 {
8315         int ret;
8316
8317         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8318         if (ret < 0)
8319                 return NULL;
8320
8321         return ethertype_rule->hash_map[ret];
8322 }
8323
8324 /* Add ethertype filter in SW list */
8325 static int
8326 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8327                                 struct i40e_ethertype_filter *filter)
8328 {
8329         struct i40e_ethertype_rule *rule = &pf->ethertype;
8330         int ret;
8331
8332         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8333         if (ret < 0) {
8334                 PMD_DRV_LOG(ERR,
8335                             "Failed to insert ethertype filter"
8336                             " to hash table %d!",
8337                             ret);
8338                 return ret;
8339         }
8340         rule->hash_map[ret] = filter;
8341
8342         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8343
8344         return 0;
8345 }
8346
8347 /* Delete ethertype filter in SW list */
8348 int
8349 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8350                              struct i40e_ethertype_filter_input *input)
8351 {
8352         struct i40e_ethertype_rule *rule = &pf->ethertype;
8353         struct i40e_ethertype_filter *filter;
8354         int ret;
8355
8356         ret = rte_hash_del_key(rule->hash_table, input);
8357         if (ret < 0) {
8358                 PMD_DRV_LOG(ERR,
8359                             "Failed to delete ethertype filter"
8360                             " to hash table %d!",
8361                             ret);
8362                 return ret;
8363         }
8364         filter = rule->hash_map[ret];
8365         rule->hash_map[ret] = NULL;
8366
8367         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8368         rte_free(filter);
8369
8370         return 0;
8371 }
8372
8373 /*
8374  * Configure ethertype filter, which can director packet by filtering
8375  * with mac address and ether_type or only ether_type
8376  */
8377 int
8378 i40e_ethertype_filter_set(struct i40e_pf *pf,
8379                         struct rte_eth_ethertype_filter *filter,
8380                         bool add)
8381 {
8382         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8383         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8384         struct i40e_ethertype_filter *ethertype_filter, *node;
8385         struct i40e_ethertype_filter check_filter;
8386         struct i40e_control_filter_stats stats;
8387         uint16_t flags = 0;
8388         int ret;
8389
8390         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8391                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8392                 return -EINVAL;
8393         }
8394         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8395                 filter->ether_type == ETHER_TYPE_IPv6) {
8396                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8397                         " control packet filter.", filter->ether_type);
8398                 return -EINVAL;
8399         }
8400         if (filter->ether_type == ETHER_TYPE_VLAN)
8401                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8402                         " not supported.");
8403
8404         /* Check if there is the filter in SW list */
8405         memset(&check_filter, 0, sizeof(check_filter));
8406         i40e_ethertype_filter_convert(filter, &check_filter);
8407         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8408                                                &check_filter.input);
8409         if (add && node) {
8410                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8411                 return -EINVAL;
8412         }
8413
8414         if (!add && !node) {
8415                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8416                 return -EINVAL;
8417         }
8418
8419         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8420                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8421         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8422                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8423         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8424
8425         memset(&stats, 0, sizeof(stats));
8426         ret = i40e_aq_add_rem_control_packet_filter(hw,
8427                         filter->mac_addr.addr_bytes,
8428                         filter->ether_type, flags,
8429                         pf->main_vsi->seid,
8430                         filter->queue, add, &stats, NULL);
8431
8432         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8433                          " mac_etype_used = %u, etype_used = %u,"
8434                          " mac_etype_free = %u, etype_free = %u\n",
8435                          ret, stats.mac_etype_used, stats.etype_used,
8436                          stats.mac_etype_free, stats.etype_free);
8437         if (ret < 0)
8438                 return -ENOSYS;
8439
8440         /* Add or delete a filter in SW list */
8441         if (add) {
8442                 ethertype_filter = rte_zmalloc("ethertype_filter",
8443                                        sizeof(*ethertype_filter), 0);
8444                 rte_memcpy(ethertype_filter, &check_filter,
8445                            sizeof(check_filter));
8446                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8447         } else {
8448                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8449         }
8450
8451         return ret;
8452 }
8453
8454 /*
8455  * Handle operations for ethertype filter.
8456  */
8457 static int
8458 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8459                                 enum rte_filter_op filter_op,
8460                                 void *arg)
8461 {
8462         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8463         int ret = 0;
8464
8465         if (filter_op == RTE_ETH_FILTER_NOP)
8466                 return ret;
8467
8468         if (arg == NULL) {
8469                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8470                             filter_op);
8471                 return -EINVAL;
8472         }
8473
8474         switch (filter_op) {
8475         case RTE_ETH_FILTER_ADD:
8476                 ret = i40e_ethertype_filter_set(pf,
8477                         (struct rte_eth_ethertype_filter *)arg,
8478                         TRUE);
8479                 break;
8480         case RTE_ETH_FILTER_DELETE:
8481                 ret = i40e_ethertype_filter_set(pf,
8482                         (struct rte_eth_ethertype_filter *)arg,
8483                         FALSE);
8484                 break;
8485         default:
8486                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8487                 ret = -ENOSYS;
8488                 break;
8489         }
8490         return ret;
8491 }
8492
8493 static int
8494 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8495                      enum rte_filter_type filter_type,
8496                      enum rte_filter_op filter_op,
8497                      void *arg)
8498 {
8499         int ret = 0;
8500
8501         if (dev == NULL)
8502                 return -EINVAL;
8503
8504         switch (filter_type) {
8505         case RTE_ETH_FILTER_NONE:
8506                 /* For global configuration */
8507                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8508                 break;
8509         case RTE_ETH_FILTER_HASH:
8510                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8511                 break;
8512         case RTE_ETH_FILTER_MACVLAN:
8513                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8514                 break;
8515         case RTE_ETH_FILTER_ETHERTYPE:
8516                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8517                 break;
8518         case RTE_ETH_FILTER_TUNNEL:
8519                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8520                 break;
8521         case RTE_ETH_FILTER_FDIR:
8522                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8523                 break;
8524         case RTE_ETH_FILTER_GENERIC:
8525                 if (filter_op != RTE_ETH_FILTER_GET)
8526                         return -EINVAL;
8527                 *(const void **)arg = &i40e_flow_ops;
8528                 break;
8529         default:
8530                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8531                                                         filter_type);
8532                 ret = -EINVAL;
8533                 break;
8534         }
8535
8536         return ret;
8537 }
8538
8539 /*
8540  * Check and enable Extended Tag.
8541  * Enabling Extended Tag is important for 40G performance.
8542  */
8543 static void
8544 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8545 {
8546         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8547         uint32_t buf = 0;
8548         int ret;
8549
8550         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8551                                       PCI_DEV_CAP_REG);
8552         if (ret < 0) {
8553                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8554                             PCI_DEV_CAP_REG);
8555                 return;
8556         }
8557         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8558                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8559                 return;
8560         }
8561
8562         buf = 0;
8563         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8564                                       PCI_DEV_CTRL_REG);
8565         if (ret < 0) {
8566                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8567                             PCI_DEV_CTRL_REG);
8568                 return;
8569         }
8570         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8571                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8572                 return;
8573         }
8574         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8575         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8576                                        PCI_DEV_CTRL_REG);
8577         if (ret < 0) {
8578                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8579                             PCI_DEV_CTRL_REG);
8580                 return;
8581         }
8582 }
8583
8584 /*
8585  * As some registers wouldn't be reset unless a global hardware reset,
8586  * hardware initialization is needed to put those registers into an
8587  * expected initial state.
8588  */
8589 static void
8590 i40e_hw_init(struct rte_eth_dev *dev)
8591 {
8592         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8593
8594         i40e_enable_extended_tag(dev);
8595
8596         /* clear the PF Queue Filter control register */
8597         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8598
8599         /* Disable symmetric hash per port */
8600         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8601 }
8602
8603 enum i40e_filter_pctype
8604 i40e_flowtype_to_pctype(uint16_t flow_type)
8605 {
8606         static const enum i40e_filter_pctype pctype_table[] = {
8607                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8608                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8609                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8610                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8611                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8612                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8613                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8614                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8615                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8616                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8617                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8618                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8619                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8620                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8621                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8622                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8623                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8624                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8625                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8626         };
8627
8628         return pctype_table[flow_type];
8629 }
8630
8631 uint16_t
8632 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8633 {
8634         static const uint16_t flowtype_table[] = {
8635                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8636                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8637                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8638                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8639                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8640                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8641                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8642                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8643                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8644                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8645                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8646                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8647                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8648                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8649                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8650                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8651                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8652                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8653                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8654                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8655                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8656                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8657                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8658                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8659                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8660                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8661                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8662                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8663                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8664                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8665                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8666         };
8667
8668         return flowtype_table[pctype];
8669 }
8670
8671 /*
8672  * On X710, performance number is far from the expectation on recent firmware
8673  * versions; on XL710, performance number is also far from the expectation on
8674  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8675  * mode is enabled and port MAC address is equal to the packet destination MAC
8676  * address. The fix for this issue may not be integrated in the following
8677  * firmware version. So the workaround in software driver is needed. It needs
8678  * to modify the initial values of 3 internal only registers for both X710 and
8679  * XL710. Note that the values for X710 or XL710 could be different, and the
8680  * workaround can be removed when it is fixed in firmware in the future.
8681  */
8682
8683 /* For both X710 and XL710 */
8684 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8685 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8686
8687 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8688 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8689
8690 /* For X710 */
8691 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8692 /* For XL710 */
8693 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8694 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8695
8696 static int
8697 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8698 {
8699         enum i40e_status_code status;
8700         struct i40e_aq_get_phy_abilities_resp phy_ab;
8701         int ret = -ENOTSUP;
8702
8703         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8704                                               NULL);
8705
8706         if (status)
8707                 return ret;
8708
8709         return 0;
8710 }
8711
8712
8713 static void
8714 i40e_configure_registers(struct i40e_hw *hw)
8715 {
8716         static struct {
8717                 uint32_t addr;
8718                 uint64_t val;
8719         } reg_table[] = {
8720                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8721                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8722                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8723         };
8724         uint64_t reg;
8725         uint32_t i;
8726         int ret;
8727
8728         for (i = 0; i < RTE_DIM(reg_table); i++) {
8729                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8730                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8731                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8732                                 reg_table[i].val =
8733                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8734                         else /* For X710 */
8735                                 reg_table[i].val =
8736                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8737                 }
8738
8739                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8740                                                         &reg, NULL);
8741                 if (ret < 0) {
8742                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8743                                                         reg_table[i].addr);
8744                         break;
8745                 }
8746                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8747                                                 reg_table[i].addr, reg);
8748                 if (reg == reg_table[i].val)
8749                         continue;
8750
8751                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8752                                                 reg_table[i].val, NULL);
8753                 if (ret < 0) {
8754                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8755                                 "address of 0x%"PRIx32, reg_table[i].val,
8756                                                         reg_table[i].addr);
8757                         break;
8758                 }
8759                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8760                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8761         }
8762 }
8763
8764 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8765 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8766 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8767 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8768 static int
8769 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8770 {
8771         uint32_t reg;
8772         int ret;
8773
8774         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8775                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8776                 return -EINVAL;
8777         }
8778
8779         /* Configure for double VLAN RX stripping */
8780         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8781         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8782                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8783                 ret = i40e_aq_debug_write_register(hw,
8784                                                    I40E_VSI_TSR(vsi->vsi_id),
8785                                                    reg, NULL);
8786                 if (ret < 0) {
8787                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8788                                     vsi->vsi_id);
8789                         return I40E_ERR_CONFIG;
8790                 }
8791         }
8792
8793         /* Configure for double VLAN TX insertion */
8794         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8795         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8796                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8797                 ret = i40e_aq_debug_write_register(hw,
8798                                                    I40E_VSI_L2TAGSTXVALID(
8799                                                    vsi->vsi_id), reg, NULL);
8800                 if (ret < 0) {
8801                         PMD_DRV_LOG(ERR, "Failed to update "
8802                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8803                         return I40E_ERR_CONFIG;
8804                 }
8805         }
8806
8807         return 0;
8808 }
8809
8810 /**
8811  * i40e_aq_add_mirror_rule
8812  * @hw: pointer to the hardware structure
8813  * @seid: VEB seid to add mirror rule to
8814  * @dst_id: destination vsi seid
8815  * @entries: Buffer which contains the entities to be mirrored
8816  * @count: number of entities contained in the buffer
8817  * @rule_id:the rule_id of the rule to be added
8818  *
8819  * Add a mirror rule for a given veb.
8820  *
8821  **/
8822 static enum i40e_status_code
8823 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8824                         uint16_t seid, uint16_t dst_id,
8825                         uint16_t rule_type, uint16_t *entries,
8826                         uint16_t count, uint16_t *rule_id)
8827 {
8828         struct i40e_aq_desc desc;
8829         struct i40e_aqc_add_delete_mirror_rule cmd;
8830         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8831                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8832                 &desc.params.raw;
8833         uint16_t buff_len;
8834         enum i40e_status_code status;
8835
8836         i40e_fill_default_direct_cmd_desc(&desc,
8837                                           i40e_aqc_opc_add_mirror_rule);
8838         memset(&cmd, 0, sizeof(cmd));
8839
8840         buff_len = sizeof(uint16_t) * count;
8841         desc.datalen = rte_cpu_to_le_16(buff_len);
8842         if (buff_len > 0)
8843                 desc.flags |= rte_cpu_to_le_16(
8844                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8845         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8846                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8847         cmd.num_entries = rte_cpu_to_le_16(count);
8848         cmd.seid = rte_cpu_to_le_16(seid);
8849         cmd.destination = rte_cpu_to_le_16(dst_id);
8850
8851         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8852         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8853         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8854                          "rule_id = %u"
8855                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8856                          hw->aq.asq_last_status, resp->rule_id,
8857                          resp->mirror_rules_used, resp->mirror_rules_free);
8858         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8859
8860         return status;
8861 }
8862
8863 /**
8864  * i40e_aq_del_mirror_rule
8865  * @hw: pointer to the hardware structure
8866  * @seid: VEB seid to add mirror rule to
8867  * @entries: Buffer which contains the entities to be mirrored
8868  * @count: number of entities contained in the buffer
8869  * @rule_id:the rule_id of the rule to be delete
8870  *
8871  * Delete a mirror rule for a given veb.
8872  *
8873  **/
8874 static enum i40e_status_code
8875 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8876                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8877                 uint16_t count, uint16_t rule_id)
8878 {
8879         struct i40e_aq_desc desc;
8880         struct i40e_aqc_add_delete_mirror_rule cmd;
8881         uint16_t buff_len = 0;
8882         enum i40e_status_code status;
8883         void *buff = NULL;
8884
8885         i40e_fill_default_direct_cmd_desc(&desc,
8886                                           i40e_aqc_opc_delete_mirror_rule);
8887         memset(&cmd, 0, sizeof(cmd));
8888         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8889                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8890                                                           I40E_AQ_FLAG_RD));
8891                 cmd.num_entries = count;
8892                 buff_len = sizeof(uint16_t) * count;
8893                 desc.datalen = rte_cpu_to_le_16(buff_len);
8894                 buff = (void *)entries;
8895         } else
8896                 /* rule id is filled in destination field for deleting mirror rule */
8897                 cmd.destination = rte_cpu_to_le_16(rule_id);
8898
8899         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8900                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8901         cmd.seid = rte_cpu_to_le_16(seid);
8902
8903         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8904         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8905
8906         return status;
8907 }
8908
8909 /**
8910  * i40e_mirror_rule_set
8911  * @dev: pointer to the hardware structure
8912  * @mirror_conf: mirror rule info
8913  * @sw_id: mirror rule's sw_id
8914  * @on: enable/disable
8915  *
8916  * set a mirror rule.
8917  *
8918  **/
8919 static int
8920 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8921                         struct rte_eth_mirror_conf *mirror_conf,
8922                         uint8_t sw_id, uint8_t on)
8923 {
8924         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8925         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8926         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8927         struct i40e_mirror_rule *parent = NULL;
8928         uint16_t seid, dst_seid, rule_id;
8929         uint16_t i, j = 0;
8930         int ret;
8931
8932         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8933
8934         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8935                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8936                         " without veb or vfs.");
8937                 return -ENOSYS;
8938         }
8939         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8940                 PMD_DRV_LOG(ERR, "mirror table is full.");
8941                 return -ENOSPC;
8942         }
8943         if (mirror_conf->dst_pool > pf->vf_num) {
8944                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8945                                  mirror_conf->dst_pool);
8946                 return -EINVAL;
8947         }
8948
8949         seid = pf->main_vsi->veb->seid;
8950
8951         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8952                 if (sw_id <= it->index) {
8953                         mirr_rule = it;
8954                         break;
8955                 }
8956                 parent = it;
8957         }
8958         if (mirr_rule && sw_id == mirr_rule->index) {
8959                 if (on) {
8960                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8961                         return -EEXIST;
8962                 } else {
8963                         ret = i40e_aq_del_mirror_rule(hw, seid,
8964                                         mirr_rule->rule_type,
8965                                         mirr_rule->entries,
8966                                         mirr_rule->num_entries, mirr_rule->id);
8967                         if (ret < 0) {
8968                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8969                                                    " ret = %d, aq_err = %d.",
8970                                                    ret, hw->aq.asq_last_status);
8971                                 return -ENOSYS;
8972                         }
8973                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8974                         rte_free(mirr_rule);
8975                         pf->nb_mirror_rule--;
8976                         return 0;
8977                 }
8978         } else if (!on) {
8979                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8980                 return -ENOENT;
8981         }
8982
8983         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8984                                 sizeof(struct i40e_mirror_rule) , 0);
8985         if (!mirr_rule) {
8986                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8987                 return I40E_ERR_NO_MEMORY;
8988         }
8989         switch (mirror_conf->rule_type) {
8990         case ETH_MIRROR_VLAN:
8991                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8992                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8993                                 mirr_rule->entries[j] =
8994                                         mirror_conf->vlan.vlan_id[i];
8995                                 j++;
8996                         }
8997                 }
8998                 if (j == 0) {
8999                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9000                         rte_free(mirr_rule);
9001                         return -EINVAL;
9002                 }
9003                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9004                 break;
9005         case ETH_MIRROR_VIRTUAL_POOL_UP:
9006         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9007                 /* check if the specified pool bit is out of range */
9008                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9009                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9010                         rte_free(mirr_rule);
9011                         return -EINVAL;
9012                 }
9013                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9014                         if (mirror_conf->pool_mask & (1ULL << i)) {
9015                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9016                                 j++;
9017                         }
9018                 }
9019                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9020                         /* add pf vsi to entries */
9021                         mirr_rule->entries[j] = pf->main_vsi_seid;
9022                         j++;
9023                 }
9024                 if (j == 0) {
9025                         PMD_DRV_LOG(ERR, "pool is not specified.");
9026                         rte_free(mirr_rule);
9027                         return -EINVAL;
9028                 }
9029                 /* egress and ingress in aq commands means from switch but not port */
9030                 mirr_rule->rule_type =
9031                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9032                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9033                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9034                 break;
9035         case ETH_MIRROR_UPLINK_PORT:
9036                 /* egress and ingress in aq commands means from switch but not port*/
9037                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9038                 break;
9039         case ETH_MIRROR_DOWNLINK_PORT:
9040                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9041                 break;
9042         default:
9043                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9044                         mirror_conf->rule_type);
9045                 rte_free(mirr_rule);
9046                 return -EINVAL;
9047         }
9048
9049         /* If the dst_pool is equal to vf_num, consider it as PF */
9050         if (mirror_conf->dst_pool == pf->vf_num)
9051                 dst_seid = pf->main_vsi_seid;
9052         else
9053                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9054
9055         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9056                                       mirr_rule->rule_type, mirr_rule->entries,
9057                                       j, &rule_id);
9058         if (ret < 0) {
9059                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
9060                                    " ret = %d, aq_err = %d.",
9061                                    ret, hw->aq.asq_last_status);
9062                 rte_free(mirr_rule);
9063                 return -ENOSYS;
9064         }
9065
9066         mirr_rule->index = sw_id;
9067         mirr_rule->num_entries = j;
9068         mirr_rule->id = rule_id;
9069         mirr_rule->dst_vsi_seid = dst_seid;
9070
9071         if (parent)
9072                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9073         else
9074                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9075
9076         pf->nb_mirror_rule++;
9077         return 0;
9078 }
9079
9080 /**
9081  * i40e_mirror_rule_reset
9082  * @dev: pointer to the device
9083  * @sw_id: mirror rule's sw_id
9084  *
9085  * reset a mirror rule.
9086  *
9087  **/
9088 static int
9089 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9090 {
9091         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9092         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9093         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9094         uint16_t seid;
9095         int ret;
9096
9097         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9098
9099         seid = pf->main_vsi->veb->seid;
9100
9101         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9102                 if (sw_id == it->index) {
9103                         mirr_rule = it;
9104                         break;
9105                 }
9106         }
9107         if (mirr_rule) {
9108                 ret = i40e_aq_del_mirror_rule(hw, seid,
9109                                 mirr_rule->rule_type,
9110                                 mirr_rule->entries,
9111                                 mirr_rule->num_entries, mirr_rule->id);
9112                 if (ret < 0) {
9113                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
9114                                            " status = %d, aq_err = %d.",
9115                                            ret, hw->aq.asq_last_status);
9116                         return -ENOSYS;
9117                 }
9118                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9119                 rte_free(mirr_rule);
9120                 pf->nb_mirror_rule--;
9121         } else {
9122                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9123                 return -ENOENT;
9124         }
9125         return 0;
9126 }
9127
9128 static uint64_t
9129 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9130 {
9131         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9132         uint64_t systim_cycles;
9133
9134         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9135         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9136                         << 32;
9137
9138         return systim_cycles;
9139 }
9140
9141 static uint64_t
9142 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9143 {
9144         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9145         uint64_t rx_tstamp;
9146
9147         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9148         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9149                         << 32;
9150
9151         return rx_tstamp;
9152 }
9153
9154 static uint64_t
9155 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9156 {
9157         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9158         uint64_t tx_tstamp;
9159
9160         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9161         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9162                         << 32;
9163
9164         return tx_tstamp;
9165 }
9166
9167 static void
9168 i40e_start_timecounters(struct rte_eth_dev *dev)
9169 {
9170         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9171         struct i40e_adapter *adapter =
9172                         (struct i40e_adapter *)dev->data->dev_private;
9173         struct rte_eth_link link;
9174         uint32_t tsync_inc_l;
9175         uint32_t tsync_inc_h;
9176
9177         /* Get current link speed. */
9178         memset(&link, 0, sizeof(link));
9179         i40e_dev_link_update(dev, 1);
9180         rte_i40e_dev_atomic_read_link_status(dev, &link);
9181
9182         switch (link.link_speed) {
9183         case ETH_SPEED_NUM_40G:
9184                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9185                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9186                 break;
9187         case ETH_SPEED_NUM_10G:
9188                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9189                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9190                 break;
9191         case ETH_SPEED_NUM_1G:
9192                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9193                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9194                 break;
9195         default:
9196                 tsync_inc_l = 0x0;
9197                 tsync_inc_h = 0x0;
9198         }
9199
9200         /* Set the timesync increment value. */
9201         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9202         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9203
9204         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9205         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9206         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9207
9208         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9209         adapter->systime_tc.cc_shift = 0;
9210         adapter->systime_tc.nsec_mask = 0;
9211
9212         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9213         adapter->rx_tstamp_tc.cc_shift = 0;
9214         adapter->rx_tstamp_tc.nsec_mask = 0;
9215
9216         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9217         adapter->tx_tstamp_tc.cc_shift = 0;
9218         adapter->tx_tstamp_tc.nsec_mask = 0;
9219 }
9220
9221 static int
9222 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9223 {
9224         struct i40e_adapter *adapter =
9225                         (struct i40e_adapter *)dev->data->dev_private;
9226
9227         adapter->systime_tc.nsec += delta;
9228         adapter->rx_tstamp_tc.nsec += delta;
9229         adapter->tx_tstamp_tc.nsec += delta;
9230
9231         return 0;
9232 }
9233
9234 static int
9235 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9236 {
9237         uint64_t ns;
9238         struct i40e_adapter *adapter =
9239                         (struct i40e_adapter *)dev->data->dev_private;
9240
9241         ns = rte_timespec_to_ns(ts);
9242
9243         /* Set the timecounters to a new value. */
9244         adapter->systime_tc.nsec = ns;
9245         adapter->rx_tstamp_tc.nsec = ns;
9246         adapter->tx_tstamp_tc.nsec = ns;
9247
9248         return 0;
9249 }
9250
9251 static int
9252 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9253 {
9254         uint64_t ns, systime_cycles;
9255         struct i40e_adapter *adapter =
9256                         (struct i40e_adapter *)dev->data->dev_private;
9257
9258         systime_cycles = i40e_read_systime_cyclecounter(dev);
9259         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9260         *ts = rte_ns_to_timespec(ns);
9261
9262         return 0;
9263 }
9264
9265 static int
9266 i40e_timesync_enable(struct rte_eth_dev *dev)
9267 {
9268         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9269         uint32_t tsync_ctl_l;
9270         uint32_t tsync_ctl_h;
9271
9272         /* Stop the timesync system time. */
9273         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9274         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9275         /* Reset the timesync system time value. */
9276         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9277         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9278
9279         i40e_start_timecounters(dev);
9280
9281         /* Clear timesync registers. */
9282         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9283         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9284         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9285         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9286         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9287         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9288
9289         /* Enable timestamping of PTP packets. */
9290         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9291         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9292
9293         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9294         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9295         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9296
9297         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9298         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9299
9300         return 0;
9301 }
9302
9303 static int
9304 i40e_timesync_disable(struct rte_eth_dev *dev)
9305 {
9306         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9307         uint32_t tsync_ctl_l;
9308         uint32_t tsync_ctl_h;
9309
9310         /* Disable timestamping of transmitted PTP packets. */
9311         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9312         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9313
9314         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9315         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9316
9317         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9318         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9319
9320         /* Reset the timesync increment value. */
9321         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9322         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9323
9324         return 0;
9325 }
9326
9327 static int
9328 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9329                                 struct timespec *timestamp, uint32_t flags)
9330 {
9331         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9332         struct i40e_adapter *adapter =
9333                 (struct i40e_adapter *)dev->data->dev_private;
9334
9335         uint32_t sync_status;
9336         uint32_t index = flags & 0x03;
9337         uint64_t rx_tstamp_cycles;
9338         uint64_t ns;
9339
9340         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9341         if ((sync_status & (1 << index)) == 0)
9342                 return -EINVAL;
9343
9344         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9345         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9346         *timestamp = rte_ns_to_timespec(ns);
9347
9348         return 0;
9349 }
9350
9351 static int
9352 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9353                                 struct timespec *timestamp)
9354 {
9355         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9356         struct i40e_adapter *adapter =
9357                 (struct i40e_adapter *)dev->data->dev_private;
9358
9359         uint32_t sync_status;
9360         uint64_t tx_tstamp_cycles;
9361         uint64_t ns;
9362
9363         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9364         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9365                 return -EINVAL;
9366
9367         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9368         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9369         *timestamp = rte_ns_to_timespec(ns);
9370
9371         return 0;
9372 }
9373
9374 /*
9375  * i40e_parse_dcb_configure - parse dcb configure from user
9376  * @dev: the device being configured
9377  * @dcb_cfg: pointer of the result of parse
9378  * @*tc_map: bit map of enabled traffic classes
9379  *
9380  * Returns 0 on success, negative value on failure
9381  */
9382 static int
9383 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9384                          struct i40e_dcbx_config *dcb_cfg,
9385                          uint8_t *tc_map)
9386 {
9387         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9388         uint8_t i, tc_bw, bw_lf;
9389
9390         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9391
9392         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9393         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9394                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9395                 return -EINVAL;
9396         }
9397
9398         /* assume each tc has the same bw */
9399         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9400         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9401                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9402         /* to ensure the sum of tcbw is equal to 100 */
9403         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9404         for (i = 0; i < bw_lf; i++)
9405                 dcb_cfg->etscfg.tcbwtable[i]++;
9406
9407         /* assume each tc has the same Transmission Selection Algorithm */
9408         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9409                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9410
9411         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9412                 dcb_cfg->etscfg.prioritytable[i] =
9413                                 dcb_rx_conf->dcb_tc[i];
9414
9415         /* FW needs one App to configure HW */
9416         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9417         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9418         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9419         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9420
9421         if (dcb_rx_conf->nb_tcs == 0)
9422                 *tc_map = 1; /* tc0 only */
9423         else
9424                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9425
9426         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9427                 dcb_cfg->pfc.willing = 0;
9428                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9429                 dcb_cfg->pfc.pfcenable = *tc_map;
9430         }
9431         return 0;
9432 }
9433
9434
9435 static enum i40e_status_code
9436 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9437                               struct i40e_aqc_vsi_properties_data *info,
9438                               uint8_t enabled_tcmap)
9439 {
9440         enum i40e_status_code ret;
9441         int i, total_tc = 0;
9442         uint16_t qpnum_per_tc, bsf, qp_idx;
9443         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9444         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9445         uint16_t used_queues;
9446
9447         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9448         if (ret != I40E_SUCCESS)
9449                 return ret;
9450
9451         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9452                 if (enabled_tcmap & (1 << i))
9453                         total_tc++;
9454         }
9455         if (total_tc == 0)
9456                 total_tc = 1;
9457         vsi->enabled_tc = enabled_tcmap;
9458
9459         /* different VSI has different queues assigned */
9460         if (vsi->type == I40E_VSI_MAIN)
9461                 used_queues = dev_data->nb_rx_queues -
9462                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9463         else if (vsi->type == I40E_VSI_VMDQ2)
9464                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9465         else {
9466                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9467                 return I40E_ERR_NO_AVAILABLE_VSI;
9468         }
9469
9470         qpnum_per_tc = used_queues / total_tc;
9471         /* Number of queues per enabled TC */
9472         if (qpnum_per_tc == 0) {
9473                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9474                 return I40E_ERR_INVALID_QP_ID;
9475         }
9476         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9477                                 I40E_MAX_Q_PER_TC);
9478         bsf = rte_bsf32(qpnum_per_tc);
9479
9480         /**
9481          * Configure TC and queue mapping parameters, for enabled TC,
9482          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9483          * default queue will serve it.
9484          */
9485         qp_idx = 0;
9486         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9487                 if (vsi->enabled_tc & (1 << i)) {
9488                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9489                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9490                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9491                         qp_idx += qpnum_per_tc;
9492                 } else
9493                         info->tc_mapping[i] = 0;
9494         }
9495
9496         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9497         if (vsi->type == I40E_VSI_SRIOV) {
9498                 info->mapping_flags |=
9499                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9500                 for (i = 0; i < vsi->nb_qps; i++)
9501                         info->queue_mapping[i] =
9502                                 rte_cpu_to_le_16(vsi->base_queue + i);
9503         } else {
9504                 info->mapping_flags |=
9505                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9506                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9507         }
9508         info->valid_sections |=
9509                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9510
9511         return I40E_SUCCESS;
9512 }
9513
9514 /*
9515  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9516  * @veb: VEB to be configured
9517  * @tc_map: enabled TC bitmap
9518  *
9519  * Returns 0 on success, negative value on failure
9520  */
9521 static enum i40e_status_code
9522 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9523 {
9524         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9525         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9526         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9527         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9528         enum i40e_status_code ret = I40E_SUCCESS;
9529         int i;
9530         uint32_t bw_max;
9531
9532         /* Check if enabled_tc is same as existing or new TCs */
9533         if (veb->enabled_tc == tc_map)
9534                 return ret;
9535
9536         /* configure tc bandwidth */
9537         memset(&veb_bw, 0, sizeof(veb_bw));
9538         veb_bw.tc_valid_bits = tc_map;
9539         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9540         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9541                 if (tc_map & BIT_ULL(i))
9542                         veb_bw.tc_bw_share_credits[i] = 1;
9543         }
9544         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9545                                                    &veb_bw, NULL);
9546         if (ret) {
9547                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9548                                   " per TC failed = %d",
9549                                   hw->aq.asq_last_status);
9550                 return ret;
9551         }
9552
9553         memset(&ets_query, 0, sizeof(ets_query));
9554         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9555                                                    &ets_query, NULL);
9556         if (ret != I40E_SUCCESS) {
9557                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9558                                  " configuration %u", hw->aq.asq_last_status);
9559                 return ret;
9560         }
9561         memset(&bw_query, 0, sizeof(bw_query));
9562         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9563                                                   &bw_query, NULL);
9564         if (ret != I40E_SUCCESS) {
9565                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9566                                  " configuration %u", hw->aq.asq_last_status);
9567                 return ret;
9568         }
9569
9570         /* store and print out BW info */
9571         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9572         veb->bw_info.bw_max = ets_query.tc_bw_max;
9573         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9574         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9575         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9576                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9577                      I40E_16_BIT_WIDTH);
9578         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9579                 veb->bw_info.bw_ets_share_credits[i] =
9580                                 bw_query.tc_bw_share_credits[i];
9581                 veb->bw_info.bw_ets_credits[i] =
9582                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9583                 /* 4 bits per TC, 4th bit is reserved */
9584                 veb->bw_info.bw_ets_max[i] =
9585                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9586                                   RTE_LEN2MASK(3, uint8_t));
9587                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9588                             veb->bw_info.bw_ets_share_credits[i]);
9589                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9590                             veb->bw_info.bw_ets_credits[i]);
9591                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9592                             veb->bw_info.bw_ets_max[i]);
9593         }
9594
9595         veb->enabled_tc = tc_map;
9596
9597         return ret;
9598 }
9599
9600
9601 /*
9602  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9603  * @vsi: VSI to be configured
9604  * @tc_map: enabled TC bitmap
9605  *
9606  * Returns 0 on success, negative value on failure
9607  */
9608 static enum i40e_status_code
9609 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9610 {
9611         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9612         struct i40e_vsi_context ctxt;
9613         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9614         enum i40e_status_code ret = I40E_SUCCESS;
9615         int i;
9616
9617         /* Check if enabled_tc is same as existing or new TCs */
9618         if (vsi->enabled_tc == tc_map)
9619                 return ret;
9620
9621         /* configure tc bandwidth */
9622         memset(&bw_data, 0, sizeof(bw_data));
9623         bw_data.tc_valid_bits = tc_map;
9624         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9625         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9626                 if (tc_map & BIT_ULL(i))
9627                         bw_data.tc_bw_credits[i] = 1;
9628         }
9629         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9630         if (ret) {
9631                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9632                         " per TC failed = %d",
9633                         hw->aq.asq_last_status);
9634                 goto out;
9635         }
9636         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9637                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9638
9639         /* Update Queue Pairs Mapping for currently enabled UPs */
9640         ctxt.seid = vsi->seid;
9641         ctxt.pf_num = hw->pf_id;
9642         ctxt.vf_num = 0;
9643         ctxt.uplink_seid = vsi->uplink_seid;
9644         ctxt.info = vsi->info;
9645         i40e_get_cap(hw);
9646         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9647         if (ret)
9648                 goto out;
9649
9650         /* Update the VSI after updating the VSI queue-mapping information */
9651         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9652         if (ret) {
9653                 PMD_INIT_LOG(ERR, "Failed to configure "
9654                             "TC queue mapping = %d",
9655                             hw->aq.asq_last_status);
9656                 goto out;
9657         }
9658         /* update the local VSI info with updated queue map */
9659         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9660                                         sizeof(vsi->info.tc_mapping));
9661         (void)rte_memcpy(&vsi->info.queue_mapping,
9662                         &ctxt.info.queue_mapping,
9663                 sizeof(vsi->info.queue_mapping));
9664         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9665         vsi->info.valid_sections = 0;
9666
9667         /* query and update current VSI BW information */
9668         ret = i40e_vsi_get_bw_config(vsi);
9669         if (ret) {
9670                 PMD_INIT_LOG(ERR,
9671                          "Failed updating vsi bw info, err %s aq_err %s",
9672                          i40e_stat_str(hw, ret),
9673                          i40e_aq_str(hw, hw->aq.asq_last_status));
9674                 goto out;
9675         }
9676
9677         vsi->enabled_tc = tc_map;
9678
9679 out:
9680         return ret;
9681 }
9682
9683 /*
9684  * i40e_dcb_hw_configure - program the dcb setting to hw
9685  * @pf: pf the configuration is taken on
9686  * @new_cfg: new configuration
9687  * @tc_map: enabled TC bitmap
9688  *
9689  * Returns 0 on success, negative value on failure
9690  */
9691 static enum i40e_status_code
9692 i40e_dcb_hw_configure(struct i40e_pf *pf,
9693                       struct i40e_dcbx_config *new_cfg,
9694                       uint8_t tc_map)
9695 {
9696         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9697         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9698         struct i40e_vsi *main_vsi = pf->main_vsi;
9699         struct i40e_vsi_list *vsi_list;
9700         enum i40e_status_code ret;
9701         int i;
9702         uint32_t val;
9703
9704         /* Use the FW API if FW > v4.4*/
9705         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9706               (hw->aq.fw_maj_ver >= 5))) {
9707                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9708                                   " to configure DCB");
9709                 return I40E_ERR_FIRMWARE_API_VERSION;
9710         }
9711
9712         /* Check if need reconfiguration */
9713         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9714                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9715                 return I40E_SUCCESS;
9716         }
9717
9718         /* Copy the new config to the current config */
9719         *old_cfg = *new_cfg;
9720         old_cfg->etsrec = old_cfg->etscfg;
9721         ret = i40e_set_dcb_config(hw);
9722         if (ret) {
9723                 PMD_INIT_LOG(ERR,
9724                          "Set DCB Config failed, err %s aq_err %s\n",
9725                          i40e_stat_str(hw, ret),
9726                          i40e_aq_str(hw, hw->aq.asq_last_status));
9727                 return ret;
9728         }
9729         /* set receive Arbiter to RR mode and ETS scheme by default */
9730         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9731                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9732                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9733                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9734                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9735                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9736                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9737                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9738                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9739                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9740                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9741                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9742                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9743         }
9744         /* get local mib to check whether it is configured correctly */
9745         /* IEEE mode */
9746         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9747         /* Get Local DCB Config */
9748         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9749                                      &hw->local_dcbx_config);
9750
9751         /* if Veb is created, need to update TC of it at first */
9752         if (main_vsi->veb) {
9753                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9754                 if (ret)
9755                         PMD_INIT_LOG(WARNING,
9756                                  "Failed configuring TC for VEB seid=%d\n",
9757                                  main_vsi->veb->seid);
9758         }
9759         /* Update each VSI */
9760         i40e_vsi_config_tc(main_vsi, tc_map);
9761         if (main_vsi->veb) {
9762                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9763                         /* Beside main VSI and VMDQ VSIs, only enable default
9764                          * TC for other VSIs
9765                          */
9766                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9767                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9768                                                          tc_map);
9769                         else
9770                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9771                                                          I40E_DEFAULT_TCMAP);
9772                         if (ret)
9773                                 PMD_INIT_LOG(WARNING,
9774                                          "Failed configuring TC for VSI seid=%d\n",
9775                                          vsi_list->vsi->seid);
9776                         /* continue */
9777                 }
9778         }
9779         return I40E_SUCCESS;
9780 }
9781
9782 /*
9783  * i40e_dcb_init_configure - initial dcb config
9784  * @dev: device being configured
9785  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9786  *
9787  * Returns 0 on success, negative value on failure
9788  */
9789 static int
9790 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9791 {
9792         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9793         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9794         int ret = 0;
9795
9796         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9797                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9798                 return -ENOTSUP;
9799         }
9800
9801         /* DCB initialization:
9802          * Update DCB configuration from the Firmware and configure
9803          * LLDP MIB change event.
9804          */
9805         if (sw_dcb == TRUE) {
9806                 ret = i40e_init_dcb(hw);
9807                 /* If lldp agent is stopped, the return value from
9808                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9809                  * adminq status. Otherwise, it should return success.
9810                  */
9811                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9812                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9813                         memset(&hw->local_dcbx_config, 0,
9814                                 sizeof(struct i40e_dcbx_config));
9815                         /* set dcb default configuration */
9816                         hw->local_dcbx_config.etscfg.willing = 0;
9817                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9818                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9819                         hw->local_dcbx_config.etscfg.tsatable[0] =
9820                                                 I40E_IEEE_TSA_ETS;
9821                         hw->local_dcbx_config.etsrec =
9822                                 hw->local_dcbx_config.etscfg;
9823                         hw->local_dcbx_config.pfc.willing = 0;
9824                         hw->local_dcbx_config.pfc.pfccap =
9825                                                 I40E_MAX_TRAFFIC_CLASS;
9826                         /* FW needs one App to configure HW */
9827                         hw->local_dcbx_config.numapps = 1;
9828                         hw->local_dcbx_config.app[0].selector =
9829                                                 I40E_APP_SEL_ETHTYPE;
9830                         hw->local_dcbx_config.app[0].priority = 3;
9831                         hw->local_dcbx_config.app[0].protocolid =
9832                                                 I40E_APP_PROTOID_FCOE;
9833                         ret = i40e_set_dcb_config(hw);
9834                         if (ret) {
9835                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9836                                         " err = %d, aq_err = %d.", ret,
9837                                           hw->aq.asq_last_status);
9838                                 return -ENOSYS;
9839                         }
9840                 } else {
9841                         PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9842                                           " err = %d, aq_err = %d.", ret,
9843                                           hw->aq.asq_last_status);
9844                         return -ENOTSUP;
9845                 }
9846         } else {
9847                 ret = i40e_aq_start_lldp(hw, NULL);
9848                 if (ret != I40E_SUCCESS)
9849                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9850
9851                 ret = i40e_init_dcb(hw);
9852                 if (!ret) {
9853                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9854                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9855                                                   " DCBX offload.");
9856                                 return -ENOTSUP;
9857                         }
9858                 } else {
9859                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9860                                           " aq_err = %d.", ret,
9861                                           hw->aq.asq_last_status);
9862                         return -ENOTSUP;
9863                 }
9864         }
9865         return 0;
9866 }
9867
9868 /*
9869  * i40e_dcb_setup - setup dcb related config
9870  * @dev: device being configured
9871  *
9872  * Returns 0 on success, negative value on failure
9873  */
9874 static int
9875 i40e_dcb_setup(struct rte_eth_dev *dev)
9876 {
9877         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9878         struct i40e_dcbx_config dcb_cfg;
9879         uint8_t tc_map = 0;
9880         int ret = 0;
9881
9882         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9883                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9884                 return -ENOTSUP;
9885         }
9886
9887         if (pf->vf_num != 0)
9888                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9889
9890         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9891         if (ret) {
9892                 PMD_INIT_LOG(ERR, "invalid dcb config");
9893                 return -EINVAL;
9894         }
9895         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9896         if (ret) {
9897                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9898                 return -ENOSYS;
9899         }
9900
9901         return 0;
9902 }
9903
9904 static int
9905 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9906                       struct rte_eth_dcb_info *dcb_info)
9907 {
9908         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9909         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9910         struct i40e_vsi *vsi = pf->main_vsi;
9911         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9912         uint16_t bsf, tc_mapping;
9913         int i, j = 0;
9914
9915         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9916                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9917         else
9918                 dcb_info->nb_tcs = 1;
9919         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9920                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9921         for (i = 0; i < dcb_info->nb_tcs; i++)
9922                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9923
9924         /* get queue mapping if vmdq is disabled */
9925         if (!pf->nb_cfg_vmdq_vsi) {
9926                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9927                         if (!(vsi->enabled_tc & (1 << i)))
9928                                 continue;
9929                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9930                         dcb_info->tc_queue.tc_rxq[j][i].base =
9931                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9932                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9933                         dcb_info->tc_queue.tc_txq[j][i].base =
9934                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9935                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9936                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9937                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9938                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9939                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9940                 }
9941                 return 0;
9942         }
9943
9944         /* get queue mapping if vmdq is enabled */
9945         do {
9946                 vsi = pf->vmdq[j].vsi;
9947                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9948                         if (!(vsi->enabled_tc & (1 << i)))
9949                                 continue;
9950                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9951                         dcb_info->tc_queue.tc_rxq[j][i].base =
9952                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9953                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9954                         dcb_info->tc_queue.tc_txq[j][i].base =
9955                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9956                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9957                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9958                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9959                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9960                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9961                 }
9962                 j++;
9963         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9964         return 0;
9965 }
9966
9967 static int
9968 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9969 {
9970         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9971         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
9972         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9973         uint16_t interval =
9974                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9975         uint16_t msix_intr;
9976
9977         msix_intr = intr_handle->intr_vec[queue_id];
9978         if (msix_intr == I40E_MISC_VEC_ID)
9979                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9980                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9981                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9982                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9983                                (interval <<
9984                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9985         else
9986                 I40E_WRITE_REG(hw,
9987                                I40E_PFINT_DYN_CTLN(msix_intr -
9988                                                    I40E_RX_VEC_START),
9989                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9990                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9991                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9992                                (interval <<
9993                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9994
9995         I40E_WRITE_FLUSH(hw);
9996         rte_intr_enable(&pci_dev->intr_handle);
9997
9998         return 0;
9999 }
10000
10001 static int
10002 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10003 {
10004         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10005         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10006         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10007         uint16_t msix_intr;
10008
10009         msix_intr = intr_handle->intr_vec[queue_id];
10010         if (msix_intr == I40E_MISC_VEC_ID)
10011                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10012         else
10013                 I40E_WRITE_REG(hw,
10014                                I40E_PFINT_DYN_CTLN(msix_intr -
10015                                                    I40E_RX_VEC_START),
10016                                0);
10017         I40E_WRITE_FLUSH(hw);
10018
10019         return 0;
10020 }
10021
10022 static int i40e_get_regs(struct rte_eth_dev *dev,
10023                          struct rte_dev_reg_info *regs)
10024 {
10025         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10026         uint32_t *ptr_data = regs->data;
10027         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10028         const struct i40e_reg_info *reg_info;
10029
10030         if (ptr_data == NULL) {
10031                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10032                 regs->width = sizeof(uint32_t);
10033                 return 0;
10034         }
10035
10036         /* The first few registers have to be read using AQ operations */
10037         reg_idx = 0;
10038         while (i40e_regs_adminq[reg_idx].name) {
10039                 reg_info = &i40e_regs_adminq[reg_idx++];
10040                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10041                         for (arr_idx2 = 0;
10042                                         arr_idx2 <= reg_info->count2;
10043                                         arr_idx2++) {
10044                                 reg_offset = arr_idx * reg_info->stride1 +
10045                                         arr_idx2 * reg_info->stride2;
10046                                 reg_offset += reg_info->base_addr;
10047                                 ptr_data[reg_offset >> 2] =
10048                                         i40e_read_rx_ctl(hw, reg_offset);
10049                         }
10050         }
10051
10052         /* The remaining registers can be read using primitives */
10053         reg_idx = 0;
10054         while (i40e_regs_others[reg_idx].name) {
10055                 reg_info = &i40e_regs_others[reg_idx++];
10056                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10057                         for (arr_idx2 = 0;
10058                                         arr_idx2 <= reg_info->count2;
10059                                         arr_idx2++) {
10060                                 reg_offset = arr_idx * reg_info->stride1 +
10061                                         arr_idx2 * reg_info->stride2;
10062                                 reg_offset += reg_info->base_addr;
10063                                 ptr_data[reg_offset >> 2] =
10064                                         I40E_READ_REG(hw, reg_offset);
10065                         }
10066         }
10067
10068         return 0;
10069 }
10070
10071 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10072 {
10073         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10074
10075         /* Convert word count to byte count */
10076         return hw->nvm.sr_size << 1;
10077 }
10078
10079 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10080                            struct rte_dev_eeprom_info *eeprom)
10081 {
10082         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10083         uint16_t *data = eeprom->data;
10084         uint16_t offset, length, cnt_words;
10085         int ret_code;
10086
10087         offset = eeprom->offset >> 1;
10088         length = eeprom->length >> 1;
10089         cnt_words = length;
10090
10091         if (offset > hw->nvm.sr_size ||
10092                 offset + length > hw->nvm.sr_size) {
10093                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10094                 return -EINVAL;
10095         }
10096
10097         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10098
10099         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10100         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10101                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10102                 return -EIO;
10103         }
10104
10105         return 0;
10106 }
10107
10108 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10109                                       struct ether_addr *mac_addr)
10110 {
10111         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10112
10113         if (!is_valid_assigned_ether_addr(mac_addr)) {
10114                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10115                 return;
10116         }
10117
10118         /* Flags: 0x3 updates port address */
10119         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10120 }
10121
10122 static int
10123 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10124 {
10125         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10126         struct rte_eth_dev_data *dev_data = pf->dev_data;
10127         uint32_t frame_size = mtu + ETHER_HDR_LEN
10128                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10129         int ret = 0;
10130
10131         /* check if mtu is within the allowed range */
10132         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10133                 return -EINVAL;
10134
10135         /* mtu setting is forbidden if port is start */
10136         if (dev_data->dev_started) {
10137                 PMD_DRV_LOG(ERR,
10138                             "port %d must be stopped before configuration\n",
10139                             dev_data->port_id);
10140                 return -EBUSY;
10141         }
10142
10143         if (frame_size > ETHER_MAX_LEN)
10144                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10145         else
10146                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10147
10148         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10149
10150         return ret;
10151 }
10152
10153 /* Restore ethertype filter */
10154 static void
10155 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10156 {
10157         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10158         struct i40e_ethertype_filter_list
10159                 *ethertype_list = &pf->ethertype.ethertype_list;
10160         struct i40e_ethertype_filter *f;
10161         struct i40e_control_filter_stats stats;
10162         uint16_t flags;
10163
10164         TAILQ_FOREACH(f, ethertype_list, rules) {
10165                 flags = 0;
10166                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10167                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10168                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10169                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10170                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10171
10172                 memset(&stats, 0, sizeof(stats));
10173                 i40e_aq_add_rem_control_packet_filter(hw,
10174                                             f->input.mac_addr.addr_bytes,
10175                                             f->input.ether_type,
10176                                             flags, pf->main_vsi->seid,
10177                                             f->queue, 1, &stats, NULL);
10178         }
10179         PMD_DRV_LOG(INFO, "Ethertype filter:"
10180                     " mac_etype_used = %u, etype_used = %u,"
10181                     " mac_etype_free = %u, etype_free = %u\n",
10182                     stats.mac_etype_used, stats.etype_used,
10183                     stats.mac_etype_free, stats.etype_free);
10184 }
10185
10186 /* Restore tunnel filter */
10187 static void
10188 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10189 {
10190         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10191         struct i40e_vsi *vsi = pf->main_vsi;
10192         struct i40e_tunnel_filter_list
10193                 *tunnel_list = &pf->tunnel.tunnel_list;
10194         struct i40e_tunnel_filter *f;
10195         struct i40e_aqc_add_remove_cloud_filters_element_data cld_filter;
10196
10197         TAILQ_FOREACH(f, tunnel_list, rules) {
10198                 memset(&cld_filter, 0, sizeof(cld_filter));
10199                 rte_memcpy(&cld_filter, &f->input, sizeof(f->input));
10200                 cld_filter.queue_number = f->queue;
10201                 i40e_aq_add_cloud_filters(hw, vsi->seid, &cld_filter, 1);
10202         }
10203 }
10204
10205 static void
10206 i40e_filter_restore(struct i40e_pf *pf)
10207 {
10208         i40e_ethertype_filter_restore(pf);
10209         i40e_tunnel_filter_restore(pf);
10210         i40e_fdir_filter_restore(pf);
10211 }