drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 115
 116 #define I40E_FLOW_TYPES ( \
 117         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 122         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 127         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 128
 129 /* Additional timesync values. */
 130 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 131 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 132 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 133 #define I40E_PRTTSYN_TSYNENA     0x80000000
 134 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 135 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 136
 137 #define I40E_MAX_PERCENT            100
 138 #define I40E_DEFAULT_DCB_APP_NUM    1
 139 #define I40E_DEFAULT_DCB_APP_PRIO   3
 140
 141 #define I40E_INSET_NONE            0x00000000000000000ULL
 142
 143 /* bit0 ~ bit 7 */
 144 #define I40E_INSET_DMAC            0x0000000000000001ULL
 145 #define I40E_INSET_SMAC            0x0000000000000002ULL
 146 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 147 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 148 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 149
 150 /* bit 8 ~ bit 15 */
 151 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 152 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 153 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 154 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 155 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 156 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 157 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 158
 159 /* bit 16 ~ bit 31 */
 160 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 161 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 162 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 163 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 164 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 165 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 166 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 167 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 168
 169 /* bit 32 ~ bit 47, tunnel fields */
 170 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 171 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 172 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 173 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 174 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 175 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 176
 177 /* bit 48 ~ bit 55 */
 178 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 179
 180 /* bit 56 ~ bit 63, Flex Payload */
 181 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD \
 190         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 191         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 192         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 193         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 194
 195 /**
 196  * Below are values for writing un-exposed registers suggested
 197  * by silicon experts
 198  */
 199 /* Destination MAC address */
 200 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 201 /* Source MAC address */
 202 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 203 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 204 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 205 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 206 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 207 /* Single VLAN tag in the inner L2 header */
 208 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 209 /* Source IPv4 address */
 210 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 211 /* Destination IPv4 address */
 212 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 213 /* Source IPv4 address for X722 */
 214 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 215 /* Destination IPv4 address for X722 */
 216 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 217 /* IPv4 Protocol for X722 */
 218 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 219 /* IPv4 Time to Live for X722 */
 220 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 221 /* IPv4 Type of Service (TOS) */
 222 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 223 /* IPv4 Protocol */
 224 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 225 /* IPv4 Time to Live */
 226 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 227 /* Source IPv6 address */
 228 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 229 /* Destination IPv6 address */
 230 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 231 /* IPv6 Traffic Class (TC) */
 232 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 233 /* IPv6 Next Header */
 234 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 235 /* IPv6 Hop Limit */
 236 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 237 /* Source L4 port */
 238 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 239 /* Destination L4 port */
 240 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 241 /* SCTP verification tag */
 242 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 243 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 244 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 245 /* Source port of tunneling UDP */
 246 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 247 /* Destination port of tunneling UDP */
 248 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 249 /* UDP Tunneling ID, NVGRE/GRE key */
 250 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 251 /* Last ether type */
 252 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 253 /* Tunneling outer destination IPv4 address */
 254 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 255 /* Tunneling outer destination IPv6 address */
 256 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 257 /* 1st word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 259 /* 2nd word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 261 /* 3rd word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 263 /* 4th word of flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 265 /* 5th word of flex payload */
 266 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 267 /* 6th word of flex payload */
 268 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 269 /* 7th word of flex payload */
 270 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 271 /* 8th word of flex payload */
 272 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 273 /* all 8 words flex payload */
 274 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 275 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 276
 277 #define I40E_TRANSLATE_INSET 0
 278 #define I40E_TRANSLATE_REG   1
 279
 280 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 281 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 282 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 283 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 284 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 285 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 286
 287 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 288 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 290         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 291
 292 /* PCI offset for querying capability */
 293 #define PCI_DEV_CAP_REG            0xA4
 294 /* PCI offset for enabling/disabling Extended Tag */
 295 #define PCI_DEV_CTRL_REG           0xA8
 296 /* Bit mask of Extended Tag capability */
 297 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 298 /* Bit shift of Extended Tag enable/disable */
 299 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 300 /* Bit mask of Extended Tag enable/disable */
 301 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 302
 303 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 304 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 305 static int i40e_dev_configure(struct rte_eth_dev *dev);
 306 static int i40e_dev_start(struct rte_eth_dev *dev);
 307 static void i40e_dev_stop(struct rte_eth_dev *dev);
 308 static void i40e_dev_close(struct rte_eth_dev *dev);
 309 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 310 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 311 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 312 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 313 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 314 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 315 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 316                                struct rte_eth_stats *stats);
 317 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 318                                struct rte_eth_xstat *xstats, unsigned n);
 319 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 320                                      struct rte_eth_xstat_name *xstats_names,
 321                                      unsigned limit);
 322 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 323 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 324                                             uint16_t queue_id,
 325                                             uint8_t stat_idx,
 326                                             uint8_t is_rx);
 327 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 328                               struct rte_eth_dev_info *dev_info);
 329 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 330                                 uint16_t vlan_id,
 331                                 int on);
 332 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 333                               enum rte_vlan_type vlan_type,
 334                               uint16_t tpid);
 335 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 336 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 337                                       uint16_t queue,
 338                                       int on);
 339 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 340 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 341 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 342 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 343                               struct rte_eth_fc_conf *fc_conf);
 344 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 345                               struct rte_eth_fc_conf *fc_conf);
 346 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 347                                        struct rte_eth_pfc_conf *pfc_conf);
 348 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 349                           struct ether_addr *mac_addr,
 350                           uint32_t index,
 351                           uint32_t pool);
 352 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 353 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 354                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 355                                     uint16_t reta_size);
 356 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 357                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 358                                    uint16_t reta_size);
 359
 360 static int i40e_get_cap(struct i40e_hw *hw);
 361 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 362 static int i40e_pf_setup(struct i40e_pf *pf);
 363 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 364 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 365 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 366 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 367 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 368                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 369 static void i40e_stat_update_48(struct i40e_hw *hw,
 370                                uint32_t hireg,
 371                                uint32_t loreg,
 372                                bool offset_loaded,
 373                                uint64_t *offset,
 374                                uint64_t *stat);
 375 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 376 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 377                                        void *param);
 378 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 379                                 uint32_t base, uint32_t num);
 380 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 381 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 382                         uint32_t base);
 383 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 384                         uint16_t num);
 385 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 386 static int i40e_veb_release(struct i40e_veb *veb);
 387 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 388                                                 struct i40e_vsi *vsi);
 389 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 390 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 391 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 392                                              struct i40e_macvlan_filter *mv_f,
 393                                              int num,
 394                                              struct ether_addr *addr);
 395 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 396                                              struct i40e_macvlan_filter *mv_f,
 397                                              int num,
 398                                              uint16_t vlan);
 399 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 400 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 401                                     struct rte_eth_rss_conf *rss_conf);
 402 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 403                                       struct rte_eth_rss_conf *rss_conf);
 404 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 405                                         struct rte_eth_udp_tunnel *udp_tunnel);
 406 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 407                                         struct rte_eth_udp_tunnel *udp_tunnel);
 408 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 409 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 410                         struct rte_eth_ethertype_filter *filter,
 411                         bool add);
 412 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 413                                 enum rte_filter_op filter_op,
 414                                 void *arg);
 415 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 416                                 enum rte_filter_type filter_type,
 417                                 enum rte_filter_op filter_op,
 418                                 void *arg);
 419 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 420                                   struct rte_eth_dcb_info *dcb_info);
 421 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 422 static void i40e_configure_registers(struct i40e_hw *hw);
 423 static void i40e_hw_init(struct rte_eth_dev *dev);
 424 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 425 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 426                         struct rte_eth_mirror_conf *mirror_conf,
 427                         uint8_t sw_id, uint8_t on);
 428 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 429
 430 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 431 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 432 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 433                                            struct timespec *timestamp,
 434                                            uint32_t flags);
 435 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 436                                            struct timespec *timestamp);
 437 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 438
 439 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 440
 441 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 442                                    struct timespec *timestamp);
 443 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 444                                     const struct timespec *timestamp);
 445
 446 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 447                                          uint16_t queue_id);
 448 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 449                                           uint16_t queue_id);
 450
 451 static int i40e_get_regs(struct rte_eth_dev *dev,
 452                          struct rte_dev_reg_info *regs);
 453
 454 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 455
 456 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 457                            struct rte_dev_eeprom_info *eeprom);
 458
 459 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 460                                       struct ether_addr *mac_addr);
 461
 462 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 463
 464 static const struct rte_pci_id pci_id_i40e_map[] = {
 465         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 466         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 467         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 468         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 469         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 470         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 471         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 478         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 479         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 480         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 481         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 482         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 483         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 484         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 485         { .vendor_id = 0, /* sentinel */ },
 486 };
 487
 488 static const struct eth_dev_ops i40e_eth_dev_ops = {
 489         .dev_configure                = i40e_dev_configure,
 490         .dev_start                    = i40e_dev_start,
 491         .dev_stop                     = i40e_dev_stop,
 492         .dev_close                    = i40e_dev_close,
 493         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 494         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 495         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 496         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 497         .dev_set_link_up              = i40e_dev_set_link_up,
 498         .dev_set_link_down            = i40e_dev_set_link_down,
 499         .link_update                  = i40e_dev_link_update,
 500         .stats_get                    = i40e_dev_stats_get,
 501         .xstats_get                   = i40e_dev_xstats_get,
 502         .xstats_get_names             = i40e_dev_xstats_get_names,
 503         .stats_reset                  = i40e_dev_stats_reset,
 504         .xstats_reset                 = i40e_dev_stats_reset,
 505         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 506         .dev_infos_get                = i40e_dev_info_get,
 507         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 508         .vlan_filter_set              = i40e_vlan_filter_set,
 509         .vlan_tpid_set                = i40e_vlan_tpid_set,
 510         .vlan_offload_set             = i40e_vlan_offload_set,
 511         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 512         .vlan_pvid_set                = i40e_vlan_pvid_set,
 513         .rx_queue_start               = i40e_dev_rx_queue_start,
 514         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 515         .tx_queue_start               = i40e_dev_tx_queue_start,
 516         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 517         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 518         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 519         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 520         .rx_queue_release             = i40e_dev_rx_queue_release,
 521         .rx_queue_count               = i40e_dev_rx_queue_count,
 522         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 523         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 524         .tx_queue_release             = i40e_dev_tx_queue_release,
 525         .dev_led_on                   = i40e_dev_led_on,
 526         .dev_led_off                  = i40e_dev_led_off,
 527         .flow_ctrl_get                = i40e_flow_ctrl_get,
 528         .flow_ctrl_set                = i40e_flow_ctrl_set,
 529         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 530         .mac_addr_add                 = i40e_macaddr_add,
 531         .mac_addr_remove              = i40e_macaddr_remove,
 532         .reta_update                  = i40e_dev_rss_reta_update,
 533         .reta_query                   = i40e_dev_rss_reta_query,
 534         .rss_hash_update              = i40e_dev_rss_hash_update,
 535         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 536         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 537         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 538         .filter_ctrl                  = i40e_dev_filter_ctrl,
 539         .rxq_info_get                 = i40e_rxq_info_get,
 540         .txq_info_get                 = i40e_txq_info_get,
 541         .mirror_rule_set              = i40e_mirror_rule_set,
 542         .mirror_rule_reset            = i40e_mirror_rule_reset,
 543         .timesync_enable              = i40e_timesync_enable,
 544         .timesync_disable             = i40e_timesync_disable,
 545         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 546         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 547         .get_dcb_info                 = i40e_dev_get_dcb_info,
 548         .timesync_adjust_time         = i40e_timesync_adjust_time,
 549         .timesync_read_time           = i40e_timesync_read_time,
 550         .timesync_write_time          = i40e_timesync_write_time,
 551         .get_reg                      = i40e_get_regs,
 552         .get_eeprom_length            = i40e_get_eeprom_length,
 553         .get_eeprom                   = i40e_get_eeprom,
 554         .mac_addr_set                 = i40e_set_default_mac_addr,
 555         .mtu_set                      = i40e_dev_mtu_set,
 556 };
 557
 558 /* store statistics names and its offset in stats structure */
 559 struct rte_i40e_xstats_name_off {
 560         char name[RTE_ETH_XSTATS_NAME_SIZE];
 561         unsigned offset;
 562 };
 563
 564 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 565         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 566         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 567         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 568         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 569         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 570                 rx_unknown_protocol)},
 571         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 572         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 573         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 574         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 575 };
 576
 577 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 578                 sizeof(rte_i40e_stats_strings[0]))
 579
 580 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 581         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 582                 tx_dropped_link_down)},
 583         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 584         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 585                 illegal_bytes)},
 586         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 587         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 588                 mac_local_faults)},
 589         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 590                 mac_remote_faults)},
 591         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 592                 rx_length_errors)},
 593         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 594         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 595         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 596         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 597         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 598         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 599                 rx_size_127)},
 600         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 601                 rx_size_255)},
 602         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 603                 rx_size_511)},
 604         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 605                 rx_size_1023)},
 606         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 607                 rx_size_1522)},
 608         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 609                 rx_size_big)},
 610         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 611                 rx_undersize)},
 612         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 613                 rx_oversize)},
 614         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 615                 mac_short_packet_dropped)},
 616         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 617                 rx_fragments)},
 618         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 619         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 620         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 621                 tx_size_127)},
 622         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 623                 tx_size_255)},
 624         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 625                 tx_size_511)},
 626         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 627                 tx_size_1023)},
 628         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 629                 tx_size_1522)},
 630         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 631                 tx_size_big)},
 632         {"rx_flow_director_atr_match_packets",
 633                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 634         {"rx_flow_director_sb_match_packets",
 635                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 636         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 637                 tx_lpi_status)},
 638         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 639                 rx_lpi_status)},
 640         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 641                 tx_lpi_count)},
 642         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 643                 rx_lpi_count)},
 644 };
 645
 646 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 647                 sizeof(rte_i40e_hw_port_strings[0]))
 648
 649 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 650         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 651                 priority_xon_rx)},
 652         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 653                 priority_xoff_rx)},
 654 };
 655
 656 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 657                 sizeof(rte_i40e_rxq_prio_strings[0]))
 658
 659 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 660         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 661                 priority_xon_tx)},
 662         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 663                 priority_xoff_tx)},
 664         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 665                 priority_xon_2_xoff)},
 666 };
 667
 668 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 669                 sizeof(rte_i40e_txq_prio_strings[0]))
 670
 671 static struct eth_driver rte_i40e_pmd = {
 672         .pci_drv = {
 673                 .id_table = pci_id_i40e_map,
 674                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 675                         RTE_PCI_DRV_DETACHABLE,
 676                 .probe = rte_eth_dev_pci_probe,
 677                 .remove = rte_eth_dev_pci_remove,
 678         },
 679         .eth_dev_init = eth_i40e_dev_init,
 680         .eth_dev_uninit = eth_i40e_dev_uninit,
 681         .dev_private_size = sizeof(struct i40e_adapter),
 682 };
 683
 684 static inline int
 685 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 686                                      struct rte_eth_link *link)
 687 {
 688         struct rte_eth_link *dst = link;
 689         struct rte_eth_link *src = &(dev->data->dev_link);
 690
 691         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 692                                         *(uint64_t *)src) == 0)
 693                 return -1;
 694
 695         return 0;
 696 }
 697
 698 static inline int
 699 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 700                                       struct rte_eth_link *link)
 701 {
 702         struct rte_eth_link *dst = &(dev->data->dev_link);
 703         struct rte_eth_link *src = link;
 704
 705         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 706                                         *(uint64_t *)src) == 0)
 707                 return -1;
 708
 709         return 0;
 710 }
 711
 712 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 713 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 714 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 715
 716 #ifndef I40E_GLQF_ORT
 717 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 718 #endif
 719 #ifndef I40E_GLQF_PIT
 720 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 721 #endif
 722
 723 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 724 {
 725         /*
 726          * Initialize registers for flexible payload, which should be set by NVM.
 727          * This should be removed from code once it is fixed in NVM.
 728          */
 729         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 730         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 731         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 732         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 733         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 734         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 735         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 736         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 737         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 738         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 739         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 740         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 741
 742         /* Initialize registers for parsing packet type of QinQ */
 743         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 744         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 745 }
 746
 747 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 748
 749 /*
 750  * Add a ethertype filter to drop all flow control frames transmitted
 751  * from VSIs.
 752 */
 753 static void
 754 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 755 {
 756         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 757         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 758                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 759                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 760         int ret;
 761
 762         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 763                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 764                                 pf->main_vsi_seid, 0,
 765                                 TRUE, NULL, NULL);
 766         if (ret)
 767                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 768                                   " frames from VSIs.");
 769 }
 770
 771 static int
 772 floating_veb_list_handler(__rte_unused const char *key,
 773                           const char *floating_veb_value,
 774                           void *opaque)
 775 {
 776         int idx = 0;
 777         unsigned int count = 0;
 778         char *end = NULL;
 779         int min, max;
 780         bool *vf_floating_veb = opaque;
 781
 782         while (isblank(*floating_veb_value))
 783                 floating_veb_value++;
 784
 785         /* Reset floating VEB configuration for VFs */
 786         for (idx = 0; idx < I40E_MAX_VF; idx++)
 787                 vf_floating_veb[idx] = false;
 788
 789         min = I40E_MAX_VF;
 790         do {
 791                 while (isblank(*floating_veb_value))
 792                         floating_veb_value++;
 793                 if (*floating_veb_value == '\0')
 794                         return -1;
 795                 errno = 0;
 796                 idx = strtoul(floating_veb_value, &end, 10);
 797                 if (errno || end == NULL)
 798                         return -1;
 799                 while (isblank(*end))
 800                         end++;
 801                 if (*end == '-') {
 802                         min = idx;
 803                 } else if ((*end == ';') || (*end == '\0')) {
 804                         max = idx;
 805                         if (min == I40E_MAX_VF)
 806                                 min = idx;
 807                         if (max >= I40E_MAX_VF)
 808                                 max = I40E_MAX_VF - 1;
 809                         for (idx = min; idx <= max; idx++) {
 810                                 vf_floating_veb[idx] = true;
 811                                 count++;
 812                         }
 813                         min = I40E_MAX_VF;
 814                 } else {
 815                         return -1;
 816                 }
 817                 floating_veb_value = end + 1;
 818         } while (*end != '\0');
 819
 820         if (count == 0)
 821                 return -1;
 822
 823         return 0;
 824 }
 825
 826 static void
 827 config_vf_floating_veb(struct rte_devargs *devargs,
 828                        uint16_t floating_veb,
 829                        bool *vf_floating_veb)
 830 {
 831         struct rte_kvargs *kvlist;
 832         int i;
 833         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 834
 835         if (!floating_veb)
 836                 return;
 837         /* All the VFs attach to the floating VEB by default
 838          * when the floating VEB is enabled.
 839          */
 840         for (i = 0; i < I40E_MAX_VF; i++)
 841                 vf_floating_veb[i] = true;
 842
 843         if (devargs == NULL)
 844                 return;
 845
 846         kvlist = rte_kvargs_parse(devargs->args, NULL);
 847         if (kvlist == NULL)
 848                 return;
 849
 850         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 851                 rte_kvargs_free(kvlist);
 852                 return;
 853         }
 854         /* When the floating_veb_list parameter exists, all the VFs
 855          * will attach to the legacy VEB firstly, then configure VFs
 856          * to the floating VEB according to the floating_veb_list.
 857          */
 858         if (rte_kvargs_process(kvlist, floating_veb_list,
 859                                floating_veb_list_handler,
 860                                vf_floating_veb) < 0) {
 861                 rte_kvargs_free(kvlist);
 862                 return;
 863         }
 864         rte_kvargs_free(kvlist);
 865 }
 866
 867 static int
 868 i40e_check_floating_handler(__rte_unused const char *key,
 869                             const char *value,
 870                             __rte_unused void *opaque)
 871 {
 872         if (strcmp(value, "1"))
 873                 return -1;
 874
 875         return 0;
 876 }
 877
 878 static int
 879 is_floating_veb_supported(struct rte_devargs *devargs)
 880 {
 881         struct rte_kvargs *kvlist;
 882         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 883
 884         if (devargs == NULL)
 885                 return 0;
 886
 887         kvlist = rte_kvargs_parse(devargs->args, NULL);
 888         if (kvlist == NULL)
 889                 return 0;
 890
 891         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 892                 rte_kvargs_free(kvlist);
 893                 return 0;
 894         }
 895         /* Floating VEB is enabled when there's key-value:
 896          * enable_floating_veb=1
 897          */
 898         if (rte_kvargs_process(kvlist, floating_veb_key,
 899                                i40e_check_floating_handler, NULL) < 0) {
 900                 rte_kvargs_free(kvlist);
 901                 return 0;
 902         }
 903         rte_kvargs_free(kvlist);
 904
 905         return 1;
 906 }
 907
 908 static void
 909 config_floating_veb(struct rte_eth_dev *dev)
 910 {
 911         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 912         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 913         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 914
 915         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 916
 917         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 918                 pf->floating_veb =
 919                         is_floating_veb_supported(pci_dev->device.devargs);
 920                 config_vf_floating_veb(pci_dev->device.devargs,
 921                                        pf->floating_veb,
 922                                        pf->floating_veb_list);
 923         } else {
 924                 pf->floating_veb = false;
 925         }
 926 }
 927
 928 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 929 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 930
 931 static int
 932 eth_i40e_dev_init(struct rte_eth_dev *dev)
 933 {
 934         struct rte_pci_device *pci_dev;
 935         struct rte_intr_handle *intr_handle;
 936         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 937         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 938         struct i40e_vsi *vsi;
 939         int ret;
 940         uint32_t len;
 941         uint8_t aq_fail = 0;
 942
 943         PMD_INIT_FUNC_TRACE();
 944
 945         dev->dev_ops = &i40e_eth_dev_ops;
 946         dev->rx_pkt_burst = i40e_recv_pkts;
 947         dev->tx_pkt_burst = i40e_xmit_pkts;
 948
 949         /* for secondary processes, we don't initialise any further as primary
 950          * has already done this work. Only check we don't need a different
 951          * RX function */
 952         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 953                 i40e_set_rx_function(dev);
 954                 i40e_set_tx_function(dev);
 955                 return 0;
 956         }
 957         pci_dev = I40E_DEV_TO_PCI(dev);
 958         intr_handle = &pci_dev->intr_handle;
 959
 960         rte_eth_copy_pci_info(dev, pci_dev);
 961
 962         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 963         pf->adapter->eth_dev = dev;
 964         pf->dev_data = dev->data;
 965
 966         hw->back = I40E_PF_TO_ADAPTER(pf);
 967         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 968         if (!hw->hw_addr) {
 969                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 970                              "as address is NULL");
 971                 return -ENODEV;
 972         }
 973
 974         hw->vendor_id = pci_dev->id.vendor_id;
 975         hw->device_id = pci_dev->id.device_id;
 976         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 977         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 978         hw->bus.device = pci_dev->addr.devid;
 979         hw->bus.func = pci_dev->addr.function;
 980         hw->adapter_stopped = 0;
 981
 982         /* Make sure all is clean before doing PF reset */
 983         i40e_clear_hw(hw);
 984
 985         /* Initialize the hardware */
 986         i40e_hw_init(dev);
 987
 988         /* Reset here to make sure all is clean for each PF */
 989         ret = i40e_pf_reset(hw);
 990         if (ret) {
 991                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 992                 return ret;
 993         }
 994
 995         /* Initialize the shared code (base driver) */
 996         ret = i40e_init_shared_code(hw);
 997         if (ret) {
 998                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 999                 return ret;
1000         }
1001
1002         /*
1003          * To work around the NVM issue, initialize registers
1004          * for flexible payload and packet type of QinQ by
1005          * software. It should be removed once issues are fixed
1006          * in NVM.
1007          */
1008         i40e_GLQF_reg_init(hw);
1009
1010         /* Initialize the input set for filters (hash and fd) to default value */
1011         i40e_filter_input_set_init(pf);
1012
1013         /* Initialize the parameters for adminq */
1014         i40e_init_adminq_parameter(hw);
1015         ret = i40e_init_adminq(hw);
1016         if (ret != I40E_SUCCESS) {
1017                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1018                 return -EIO;
1019         }
1020         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1021                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1022                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1023                      ((hw->nvm.version >> 12) & 0xf),
1024                      ((hw->nvm.version >> 4) & 0xff),
1025                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1026
1027         /* Need the special FW version to support floating VEB */
1028         config_floating_veb(dev);
1029         /* Clear PXE mode */
1030         i40e_clear_pxe_mode(hw);
1031         ret = i40e_dev_sync_phy_type(hw);
1032         if (ret) {
1033                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1034                 goto err_sync_phy_type;
1035         }
1036         /*
1037          * On X710, performance number is far from the expectation on recent
1038          * firmware versions. The fix for this issue may not be integrated in
1039          * the following firmware version. So the workaround in software driver
1040          * is needed. It needs to modify the initial values of 3 internal only
1041          * registers. Note that the workaround can be removed when it is fixed
1042          * in firmware in the future.
1043          */
1044         i40e_configure_registers(hw);
1045
1046         /* Get hw capabilities */
1047         ret = i40e_get_cap(hw);
1048         if (ret != I40E_SUCCESS) {
1049                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1050                 goto err_get_capabilities;
1051         }
1052
1053         /* Initialize parameters for PF */
1054         ret = i40e_pf_parameter_init(dev);
1055         if (ret != 0) {
1056                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1057                 goto err_parameter_init;
1058         }
1059
1060         /* Initialize the queue management */
1061         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1062         if (ret < 0) {
1063                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1064                 goto err_qp_pool_init;
1065         }
1066         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1067                                 hw->func_caps.num_msix_vectors - 1);
1068         if (ret < 0) {
1069                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1070                 goto err_msix_pool_init;
1071         }
1072
1073         /* Initialize lan hmc */
1074         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1075                                 hw->func_caps.num_rx_qp, 0, 0);
1076         if (ret != I40E_SUCCESS) {
1077                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1078                 goto err_init_lan_hmc;
1079         }
1080
1081         /* Configure lan hmc */
1082         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1083         if (ret != I40E_SUCCESS) {
1084                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1085                 goto err_configure_lan_hmc;
1086         }
1087
1088         /* Get and check the mac address */
1089         i40e_get_mac_addr(hw, hw->mac.addr);
1090         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1091                 PMD_INIT_LOG(ERR, "mac address is not valid");
1092                 ret = -EIO;
1093                 goto err_get_mac_addr;
1094         }
1095         /* Copy the permanent MAC address */
1096         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1097                         (struct ether_addr *) hw->mac.perm_addr);
1098
1099         /* Disable flow control */
1100         hw->fc.requested_mode = I40E_FC_NONE;
1101         i40e_set_fc(hw, &aq_fail, TRUE);
1102
1103         /* Set the global registers with default ether type value */
1104         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1105         if (ret != I40E_SUCCESS) {
1106                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1107                              "VLAN ether type");
1108                 goto err_setup_pf_switch;
1109         }
1110
1111         /* PF setup, which includes VSI setup */
1112         ret = i40e_pf_setup(pf);
1113         if (ret) {
1114                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1115                 goto err_setup_pf_switch;
1116         }
1117
1118         /* reset all stats of the device, including pf and main vsi */
1119         i40e_dev_stats_reset(dev);
1120
1121         vsi = pf->main_vsi;
1122
1123         /* Disable double vlan by default */
1124         i40e_vsi_config_double_vlan(vsi, FALSE);
1125
1126         /* Disable S-TAG identification when floating_veb is disabled */
1127         if (!pf->floating_veb) {
1128                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1129                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1130                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1131                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1132                 }
1133         }
1134
1135         if (!vsi->max_macaddrs)
1136                 len = ETHER_ADDR_LEN;
1137         else
1138                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1139
1140         /* Should be after VSI initialized */
1141         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1142         if (!dev->data->mac_addrs) {
1143                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1144                                         "for storing mac address");
1145                 goto err_mac_alloc;
1146         }
1147         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1148                                         &dev->data->mac_addrs[0]);
1149
1150         /* initialize pf host driver to setup SRIOV resource if applicable */
1151         i40e_pf_host_init(dev);
1152
1153         /* register callback func to eal lib */
1154         rte_intr_callback_register(intr_handle,
1155                                    i40e_dev_interrupt_handler, dev);
1156
1157         /* configure and enable device interrupt */
1158         i40e_pf_config_irq0(hw, TRUE);
1159         i40e_pf_enable_irq0(hw);
1160
1161         /* enable uio intr after callback register */
1162         rte_intr_enable(intr_handle);
1163         /*
1164          * Add an ethertype filter to drop all flow control frames transmitted
1165          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1166          * frames to wire.
1167          */
1168         i40e_add_tx_flow_control_drop_filter(pf);
1169
1170         /* Set the max frame size to 0x2600 by default,
1171          * in case other drivers changed the default value.
1172          */
1173         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1174
1175         /* initialize mirror rule list */
1176         TAILQ_INIT(&pf->mirror_list);
1177
1178         /* Init dcb to sw mode by default */
1179         ret = i40e_dcb_init_configure(dev, TRUE);
1180         if (ret != I40E_SUCCESS) {
1181                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1182                 pf->flags &= ~I40E_FLAG_DCB;
1183         }
1184
1185         return 0;
1186
1187 err_mac_alloc:
1188         i40e_vsi_release(pf->main_vsi);
1189 err_setup_pf_switch:
1190 err_get_mac_addr:
1191 err_configure_lan_hmc:
1192         (void)i40e_shutdown_lan_hmc(hw);
1193 err_init_lan_hmc:
1194         i40e_res_pool_destroy(&pf->msix_pool);
1195 err_msix_pool_init:
1196         i40e_res_pool_destroy(&pf->qp_pool);
1197 err_qp_pool_init:
1198 err_parameter_init:
1199 err_get_capabilities:
1200 err_sync_phy_type:
1201         (void)i40e_shutdown_adminq(hw);
1202
1203         return ret;
1204 }
1205
1206 static int
1207 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1208 {
1209         struct rte_pci_device *pci_dev;
1210         struct rte_intr_handle *intr_handle;
1211         struct i40e_hw *hw;
1212         struct i40e_filter_control_settings settings;
1213         int ret;
1214         uint8_t aq_fail = 0;
1215
1216         PMD_INIT_FUNC_TRACE();
1217
1218         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1219                 return 0;
1220
1221         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1222         pci_dev = I40E_DEV_TO_PCI(dev);
1223         intr_handle = &pci_dev->intr_handle;
1224
1225         if (hw->adapter_stopped == 0)
1226                 i40e_dev_close(dev);
1227
1228         dev->dev_ops = NULL;
1229         dev->rx_pkt_burst = NULL;
1230         dev->tx_pkt_burst = NULL;
1231
1232         /* Clear PXE mode */
1233         i40e_clear_pxe_mode(hw);
1234
1235         /* Unconfigure filter control */
1236         memset(&settings, 0, sizeof(settings));
1237         ret = i40e_set_filter_control(hw, &settings);
1238         if (ret)
1239                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1240                                         ret);
1241
1242         /* Disable flow control */
1243         hw->fc.requested_mode = I40E_FC_NONE;
1244         i40e_set_fc(hw, &aq_fail, TRUE);
1245
1246         /* uninitialize pf host driver */
1247         i40e_pf_host_uninit(dev);
1248
1249         rte_free(dev->data->mac_addrs);
1250         dev->data->mac_addrs = NULL;
1251
1252         /* disable uio intr before callback unregister */
1253         rte_intr_disable(intr_handle);
1254
1255         /* register callback func to eal lib */
1256         rte_intr_callback_unregister(intr_handle,
1257                                      i40e_dev_interrupt_handler, dev);
1258
1259         return 0;
1260 }
1261
1262 static int
1263 i40e_dev_configure(struct rte_eth_dev *dev)
1264 {
1265         struct i40e_adapter *ad =
1266                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1267         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1268         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1269         int i, ret;
1270
1271         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1272          * bulk allocation or vector Rx preconditions we will reset it.
1273          */
1274         ad->rx_bulk_alloc_allowed = true;
1275         ad->rx_vec_allowed = true;
1276         ad->tx_simple_allowed = true;
1277         ad->tx_vec_allowed = true;
1278
1279         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1280                 ret = i40e_fdir_setup(pf);
1281                 if (ret != I40E_SUCCESS) {
1282                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1283                         return -ENOTSUP;
1284                 }
1285                 ret = i40e_fdir_configure(dev);
1286                 if (ret < 0) {
1287                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1288                         goto err;
1289                 }
1290         } else
1291                 i40e_fdir_teardown(pf);
1292
1293         ret = i40e_dev_init_vlan(dev);
1294         if (ret < 0)
1295                 goto err;
1296
1297         /* VMDQ setup.
1298          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1299          *  RSS setting have different requirements.
1300          *  General PMD driver call sequence are NIC init, configure,
1301          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1302          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1303          *  applicable. So, VMDQ setting has to be done before
1304          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1305          *  For RSS setting, it will try to calculate actual configured RX queue
1306          *  number, which will be available after rx_queue_setup(). dev_start()
1307          *  function is good to place RSS setup.
1308          */
1309         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1310                 ret = i40e_vmdq_setup(dev);
1311                 if (ret)
1312                         goto err;
1313         }
1314
1315         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1316                 ret = i40e_dcb_setup(dev);
1317                 if (ret) {
1318                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1319                         goto err_dcb;
1320                 }
1321         }
1322
1323         return 0;
1324
1325 err_dcb:
1326         /* need to release vmdq resource if exists */
1327         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1328                 i40e_vsi_release(pf->vmdq[i].vsi);
1329                 pf->vmdq[i].vsi = NULL;
1330         }
1331         rte_free(pf->vmdq);
1332         pf->vmdq = NULL;
1333 err:
1334         /* need to release fdir resource if exists */
1335         i40e_fdir_teardown(pf);
1336         return ret;
1337 }
1338
1339 void
1340 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1341 {
1342         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1343         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1344         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1345         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1346         uint16_t msix_vect = vsi->msix_intr;
1347         uint16_t i;
1348
1349         for (i = 0; i < vsi->nb_qps; i++) {
1350                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1351                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1352                 rte_wmb();
1353         }
1354
1355         if (vsi->type != I40E_VSI_SRIOV) {
1356                 if (!rte_intr_allow_others(intr_handle)) {
1357                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1358                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1359                         I40E_WRITE_REG(hw,
1360                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1361                                        0);
1362                 } else {
1363                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1364                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1365                         I40E_WRITE_REG(hw,
1366                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1367                                                        msix_vect - 1), 0);
1368                 }
1369         } else {
1370                 uint32_t reg;
1371                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1372                         vsi->user_param + (msix_vect - 1);
1373
1374                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1375                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1376         }
1377         I40E_WRITE_FLUSH(hw);
1378 }
1379
1380 static void
1381 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1382                        int base_queue, int nb_queue)
1383 {
1384         int i;
1385         uint32_t val;
1386         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1387
1388         /* Bind all RX queues to allocated MSIX interrupt */
1389         for (i = 0; i < nb_queue; i++) {
1390                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1391                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1392                         ((base_queue + i + 1) <<
1393                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1394                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1395                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1396
1397                 if (i == nb_queue - 1)
1398                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1399                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1400         }
1401
1402         /* Write first RX queue to Link list register as the head element */
1403         if (vsi->type != I40E_VSI_SRIOV) {
1404                 uint16_t interval =
1405                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1406
1407                 if (msix_vect == I40E_MISC_VEC_ID) {
1408                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1409                                        (base_queue <<
1410                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1411                                        (0x0 <<
1412                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1413                         I40E_WRITE_REG(hw,
1414                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1415                                        interval);
1416                 } else {
1417                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1418                                        (base_queue <<
1419                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1420                                        (0x0 <<
1421                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1422                         I40E_WRITE_REG(hw,
1423                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1424                                                        msix_vect - 1),
1425                                        interval);
1426                 }
1427         } else {
1428                 uint32_t reg;
1429
1430                 if (msix_vect == I40E_MISC_VEC_ID) {
1431                         I40E_WRITE_REG(hw,
1432                                        I40E_VPINT_LNKLST0(vsi->user_param),
1433                                        (base_queue <<
1434                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1435                                        (0x0 <<
1436                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1437                 } else {
1438                         /* num_msix_vectors_vf needs to minus irq0 */
1439                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1440                                 vsi->user_param + (msix_vect - 1);
1441
1442                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1443                                        (base_queue <<
1444                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1445                                        (0x0 <<
1446                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1447                 }
1448         }
1449
1450         I40E_WRITE_FLUSH(hw);
1451 }
1452
1453 void
1454 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1455 {
1456         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1457         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1458         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1459         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1460         uint16_t msix_vect = vsi->msix_intr;
1461         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1462         uint16_t queue_idx = 0;
1463         int record = 0;
1464         uint32_t val;
1465         int i;
1466
1467         for (i = 0; i < vsi->nb_qps; i++) {
1468                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1469                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1470         }
1471
1472         /* INTENA flag is not auto-cleared for interrupt */
1473         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1474         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1475                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1476                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1477         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1478
1479         /* VF bind interrupt */
1480         if (vsi->type == I40E_VSI_SRIOV) {
1481                 __vsi_queues_bind_intr(vsi, msix_vect,
1482                                        vsi->base_queue, vsi->nb_qps);
1483                 return;
1484         }
1485
1486         /* PF & VMDq bind interrupt */
1487         if (rte_intr_dp_is_en(intr_handle)) {
1488                 if (vsi->type == I40E_VSI_MAIN) {
1489                         queue_idx = 0;
1490                         record = 1;
1491                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1492                         struct i40e_vsi *main_vsi =
1493                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1494                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1495                         record = 1;
1496                 }
1497         }
1498
1499         for (i = 0; i < vsi->nb_used_qps; i++) {
1500                 if (nb_msix <= 1) {
1501                         if (!rte_intr_allow_others(intr_handle))
1502                                 /* allow to share MISC_VEC_ID */
1503                                 msix_vect = I40E_MISC_VEC_ID;
1504
1505                         /* no enough msix_vect, map all to one */
1506                         __vsi_queues_bind_intr(vsi, msix_vect,
1507                                                vsi->base_queue + i,
1508                                                vsi->nb_used_qps - i);
1509                         for (; !!record && i < vsi->nb_used_qps; i++)
1510                                 intr_handle->intr_vec[queue_idx + i] =
1511                                         msix_vect;
1512                         break;
1513                 }
1514                 /* 1:1 queue/msix_vect mapping */
1515                 __vsi_queues_bind_intr(vsi, msix_vect,
1516                                        vsi->base_queue + i, 1);
1517                 if (!!record)
1518                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1519
1520                 msix_vect++;
1521                 nb_msix--;
1522         }
1523 }
1524
1525 static void
1526 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1527 {
1528         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1529         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1530         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1531         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1532         uint16_t interval = i40e_calc_itr_interval(\
1533                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1534         uint16_t msix_intr, i;
1535
1536         if (rte_intr_allow_others(intr_handle))
1537                 for (i = 0; i < vsi->nb_msix; i++) {
1538                         msix_intr = vsi->msix_intr + i;
1539                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1540                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1541                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1542                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1543                                 (interval <<
1544                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1545                 }
1546         else
1547                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1548                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1549                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1550                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1551                                (interval <<
1552                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1553
1554         I40E_WRITE_FLUSH(hw);
1555 }
1556
1557 static void
1558 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1559 {
1560         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1561         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1562         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1563         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1564         uint16_t msix_intr, i;
1565
1566         if (rte_intr_allow_others(intr_handle))
1567                 for (i = 0; i < vsi->nb_msix; i++) {
1568                         msix_intr = vsi->msix_intr + i;
1569                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1570                                        0);
1571                 }
1572         else
1573                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1574
1575         I40E_WRITE_FLUSH(hw);
1576 }
1577
1578 static inline uint8_t
1579 i40e_parse_link_speeds(uint16_t link_speeds)
1580 {
1581         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1582
1583         if (link_speeds & ETH_LINK_SPEED_40G)
1584                 link_speed |= I40E_LINK_SPEED_40GB;
1585         if (link_speeds & ETH_LINK_SPEED_25G)
1586                 link_speed |= I40E_LINK_SPEED_25GB;
1587         if (link_speeds & ETH_LINK_SPEED_20G)
1588                 link_speed |= I40E_LINK_SPEED_20GB;
1589         if (link_speeds & ETH_LINK_SPEED_10G)
1590                 link_speed |= I40E_LINK_SPEED_10GB;
1591         if (link_speeds & ETH_LINK_SPEED_1G)
1592                 link_speed |= I40E_LINK_SPEED_1GB;
1593         if (link_speeds & ETH_LINK_SPEED_100M)
1594                 link_speed |= I40E_LINK_SPEED_100MB;
1595
1596         return link_speed;
1597 }
1598
1599 static int
1600 i40e_phy_conf_link(struct i40e_hw *hw,
1601                    uint8_t abilities,
1602                    uint8_t force_speed)
1603 {
1604         enum i40e_status_code status;
1605         struct i40e_aq_get_phy_abilities_resp phy_ab;
1606         struct i40e_aq_set_phy_config phy_conf;
1607         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1608                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1609                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1610                         I40E_AQ_PHY_FLAG_LOW_POWER;
1611         const uint8_t advt = I40E_LINK_SPEED_40GB |
1612                         I40E_LINK_SPEED_25GB |
1613                         I40E_LINK_SPEED_10GB |
1614                         I40E_LINK_SPEED_1GB |
1615                         I40E_LINK_SPEED_100MB;
1616         int ret = -ENOTSUP;
1617
1618
1619         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1620                                               NULL);
1621         if (status)
1622                 return ret;
1623
1624         memset(&phy_conf, 0, sizeof(phy_conf));
1625
1626         /* bits 0-2 use the values from get_phy_abilities_resp */
1627         abilities &= ~mask;
1628         abilities |= phy_ab.abilities & mask;
1629
1630         /* update ablities and speed */
1631         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1632                 phy_conf.link_speed = advt;
1633         else
1634                 phy_conf.link_speed = force_speed;
1635
1636         phy_conf.abilities = abilities;
1637
1638         /* use get_phy_abilities_resp value for the rest */
1639         phy_conf.phy_type = phy_ab.phy_type;
1640         phy_conf.eee_capability = phy_ab.eee_capability;
1641         phy_conf.eeer = phy_ab.eeer_val;
1642         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1643
1644         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1645                     phy_ab.abilities, phy_ab.link_speed);
1646         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1647                     phy_conf.abilities, phy_conf.link_speed);
1648
1649         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1650         if (status)
1651                 return ret;
1652
1653         return I40E_SUCCESS;
1654 }
1655
1656 static int
1657 i40e_apply_link_speed(struct rte_eth_dev *dev)
1658 {
1659         uint8_t speed;
1660         uint8_t abilities = 0;
1661         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1662         struct rte_eth_conf *conf = &dev->data->dev_conf;
1663
1664         speed = i40e_parse_link_speeds(conf->link_speeds);
1665         if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
1666                 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1667         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1668                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1669         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1670
1671         /* Skip changing speed on 40G interfaces, FW does not support */
1672         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1673                 speed =  I40E_LINK_SPEED_UNKNOWN;
1674                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1675         }
1676
1677         return i40e_phy_conf_link(hw, abilities, speed);
1678 }
1679
1680 static int
1681 i40e_dev_start(struct rte_eth_dev *dev)
1682 {
1683         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1684         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1685         struct i40e_vsi *main_vsi = pf->main_vsi;
1686         int ret, i;
1687         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1688         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1689         uint32_t intr_vector = 0;
1690
1691         hw->adapter_stopped = 0;
1692
1693         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1694                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1695                              dev->data->port_id);
1696                 return -EINVAL;
1697         }
1698
1699         rte_intr_disable(intr_handle);
1700
1701         if ((rte_intr_cap_multiple(intr_handle) ||
1702              !RTE_ETH_DEV_SRIOV(dev).active) &&
1703             dev->data->dev_conf.intr_conf.rxq != 0) {
1704                 intr_vector = dev->data->nb_rx_queues;
1705                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1706                         return -1;
1707         }
1708
1709         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1710                 intr_handle->intr_vec =
1711                         rte_zmalloc("intr_vec",
1712                                     dev->data->nb_rx_queues * sizeof(int),
1713                                     0);
1714                 if (!intr_handle->intr_vec) {
1715                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1716                                      " intr_vec\n", dev->data->nb_rx_queues);
1717                         return -ENOMEM;
1718                 }
1719         }
1720
1721         /* Initialize VSI */
1722         ret = i40e_dev_rxtx_init(pf);
1723         if (ret != I40E_SUCCESS) {
1724                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1725                 goto err_up;
1726         }
1727
1728         /* Map queues with MSIX interrupt */
1729         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1730                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1731         i40e_vsi_queues_bind_intr(main_vsi);
1732         i40e_vsi_enable_queues_intr(main_vsi);
1733
1734         /* Map VMDQ VSI queues with MSIX interrupt */
1735         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1736                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1737                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1738                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1739         }
1740
1741         /* enable FDIR MSIX interrupt */
1742         if (pf->fdir.fdir_vsi) {
1743                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1744                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1745         }
1746
1747         /* Enable all queues which have been configured */
1748         ret = i40e_dev_switch_queues(pf, TRUE);
1749         if (ret != I40E_SUCCESS) {
1750                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1751                 goto err_up;
1752         }
1753
1754         /* Enable receiving broadcast packets */
1755         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1756         if (ret != I40E_SUCCESS)
1757                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1758
1759         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1760                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1761                                                 true, NULL);
1762                 if (ret != I40E_SUCCESS)
1763                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1764         }
1765
1766         /* Apply link configure */
1767         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1768                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1769                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1770                                 ETH_LINK_SPEED_40G)) {
1771                 PMD_DRV_LOG(ERR, "Invalid link setting");
1772                 goto err_up;
1773         }
1774         ret = i40e_apply_link_speed(dev);
1775         if (I40E_SUCCESS != ret) {
1776                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1777                 goto err_up;
1778         }
1779
1780         if (!rte_intr_allow_others(intr_handle)) {
1781                 rte_intr_callback_unregister(intr_handle,
1782                                              i40e_dev_interrupt_handler,
1783                                              (void *)dev);
1784                 /* configure and enable device interrupt */
1785                 i40e_pf_config_irq0(hw, FALSE);
1786                 i40e_pf_enable_irq0(hw);
1787
1788                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1789                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1790                                      " no intr multiplex\n");
1791         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1792                 ret = i40e_aq_set_phy_int_mask(hw,
1793                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1794                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1795                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1796                 if (ret != I40E_SUCCESS)
1797                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1798
1799                 /* Call get_link_info aq commond to enable LSE */
1800                 i40e_dev_link_update(dev, 0);
1801         }
1802
1803         /* enable uio intr after callback register */
1804         rte_intr_enable(intr_handle);
1805
1806         return I40E_SUCCESS;
1807
1808 err_up:
1809         i40e_dev_switch_queues(pf, FALSE);
1810         i40e_dev_clear_queues(dev);
1811
1812         return ret;
1813 }
1814
1815 static void
1816 i40e_dev_stop(struct rte_eth_dev *dev)
1817 {
1818         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1819         struct i40e_vsi *main_vsi = pf->main_vsi;
1820         struct i40e_mirror_rule *p_mirror;
1821         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1822         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1823         int i;
1824
1825         /* Disable all queues */
1826         i40e_dev_switch_queues(pf, FALSE);
1827
1828         /* un-map queues with interrupt registers */
1829         i40e_vsi_disable_queues_intr(main_vsi);
1830         i40e_vsi_queues_unbind_intr(main_vsi);
1831
1832         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1833                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1834                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1835         }
1836
1837         if (pf->fdir.fdir_vsi) {
1838                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1839                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1840         }
1841         /* Clear all queues and release memory */
1842         i40e_dev_clear_queues(dev);
1843
1844         /* Set link down */
1845         i40e_dev_set_link_down(dev);
1846
1847         /* Remove all mirror rules */
1848         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1849                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1850                 rte_free(p_mirror);
1851         }
1852         pf->nb_mirror_rule = 0;
1853
1854         if (!rte_intr_allow_others(intr_handle))
1855                 /* resume to the default handler */
1856                 rte_intr_callback_register(intr_handle,
1857                                            i40e_dev_interrupt_handler,
1858                                            (void *)dev);
1859
1860         /* Clean datapath event and queue/vec mapping */
1861         rte_intr_efd_disable(intr_handle);
1862         if (intr_handle->intr_vec) {
1863                 rte_free(intr_handle->intr_vec);
1864                 intr_handle->intr_vec = NULL;
1865         }
1866 }
1867
1868 static void
1869 i40e_dev_close(struct rte_eth_dev *dev)
1870 {
1871         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1872         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1873         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1874         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1875         uint32_t reg;
1876         int i;
1877
1878         PMD_INIT_FUNC_TRACE();
1879
1880         i40e_dev_stop(dev);
1881         hw->adapter_stopped = 1;
1882         i40e_dev_free_queues(dev);
1883
1884         /* Disable interrupt */
1885         i40e_pf_disable_irq0(hw);
1886         rte_intr_disable(intr_handle);
1887
1888         /* shutdown and destroy the HMC */
1889         i40e_shutdown_lan_hmc(hw);
1890
1891         /* release all the existing VSIs and VEBs */
1892         i40e_fdir_teardown(pf);
1893         i40e_vsi_release(pf->main_vsi);
1894
1895         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1896                 i40e_vsi_release(pf->vmdq[i].vsi);
1897                 pf->vmdq[i].vsi = NULL;
1898         }
1899
1900         rte_free(pf->vmdq);
1901         pf->vmdq = NULL;
1902
1903         /* shutdown the adminq */
1904         i40e_aq_queue_shutdown(hw, true);
1905         i40e_shutdown_adminq(hw);
1906
1907         i40e_res_pool_destroy(&pf->qp_pool);
1908         i40e_res_pool_destroy(&pf->msix_pool);
1909
1910         /* force a PF reset to clean anything leftover */
1911         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1912         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1913                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1914         I40E_WRITE_FLUSH(hw);
1915 }
1916
1917 static void
1918 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1919 {
1920         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1921         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         struct i40e_vsi *vsi = pf->main_vsi;
1923         int status;
1924
1925         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1926                                                      true, NULL, true);
1927         if (status != I40E_SUCCESS)
1928                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1929
1930         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1931                                                         TRUE, NULL);
1932         if (status != I40E_SUCCESS)
1933                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1934
1935 }
1936
1937 static void
1938 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1939 {
1940         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1941         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942         struct i40e_vsi *vsi = pf->main_vsi;
1943         int status;
1944
1945         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1946                                                      false, NULL, true);
1947         if (status != I40E_SUCCESS)
1948                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1949
1950         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1951                                                         false, NULL);
1952         if (status != I40E_SUCCESS)
1953                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1954 }
1955
1956 static void
1957 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1958 {
1959         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1960         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1961         struct i40e_vsi *vsi = pf->main_vsi;
1962         int ret;
1963
1964         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1965         if (ret != I40E_SUCCESS)
1966                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1967 }
1968
1969 static void
1970 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1971 {
1972         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1973         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1974         struct i40e_vsi *vsi = pf->main_vsi;
1975         int ret;
1976
1977         if (dev->data->promiscuous == 1)
1978                 return; /* must remain in all_multicast mode */
1979
1980         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1981                                 vsi->seid, FALSE, NULL);
1982         if (ret != I40E_SUCCESS)
1983                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1984 }
1985
1986 /*
1987  * Set device link up.
1988  */
1989 static int
1990 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1991 {
1992         /* re-apply link speed setting */
1993         return i40e_apply_link_speed(dev);
1994 }
1995
1996 /*
1997  * Set device link down.
1998  */
1999 static int
2000 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2001 {
2002         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2003         uint8_t abilities = 0;
2004         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2005
2006         if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2007                 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2008         return i40e_phy_conf_link(hw, abilities, speed);
2009 }
2010
2011 int
2012 i40e_dev_link_update(struct rte_eth_dev *dev,
2013                      int wait_to_complete)
2014 {
2015 #define CHECK_INTERVAL 100  /* 100ms */
2016 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2017         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2018         struct i40e_link_status link_status;
2019         struct rte_eth_link link, old;
2020         int status;
2021         unsigned rep_cnt = MAX_REPEAT_TIME;
2022         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2023
2024         memset(&link, 0, sizeof(link));
2025         memset(&old, 0, sizeof(old));
2026         memset(&link_status, 0, sizeof(link_status));
2027         rte_i40e_dev_atomic_read_link_status(dev, &old);
2028
2029         do {
2030                 /* Get link status information from hardware */
2031                 status = i40e_aq_get_link_info(hw, enable_lse,
2032                                                 &link_status, NULL);
2033                 if (status != I40E_SUCCESS) {
2034                         link.link_speed = ETH_SPEED_NUM_100M;
2035                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2036                         PMD_DRV_LOG(ERR, "Failed to get link info");
2037                         goto out;
2038                 }
2039
2040                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2041                 if (!wait_to_complete)
2042                         break;
2043
2044                 rte_delay_ms(CHECK_INTERVAL);
2045         } while (!link.link_status && rep_cnt--);
2046
2047         if (!link.link_status)
2048                 goto out;
2049
2050         /* i40e uses full duplex only */
2051         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2052
2053         /* Parse the link status */
2054         switch (link_status.link_speed) {
2055         case I40E_LINK_SPEED_100MB:
2056                 link.link_speed = ETH_SPEED_NUM_100M;
2057                 break;
2058         case I40E_LINK_SPEED_1GB:
2059                 link.link_speed = ETH_SPEED_NUM_1G;
2060                 break;
2061         case I40E_LINK_SPEED_10GB:
2062                 link.link_speed = ETH_SPEED_NUM_10G;
2063                 break;
2064         case I40E_LINK_SPEED_20GB:
2065                 link.link_speed = ETH_SPEED_NUM_20G;
2066                 break;
2067         case I40E_LINK_SPEED_25GB:
2068                 link.link_speed = ETH_SPEED_NUM_25G;
2069                 break;
2070         case I40E_LINK_SPEED_40GB:
2071                 link.link_speed = ETH_SPEED_NUM_40G;
2072                 break;
2073         default:
2074                 link.link_speed = ETH_SPEED_NUM_100M;
2075                 break;
2076         }
2077
2078         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2079                         ETH_LINK_SPEED_FIXED);
2080
2081 out:
2082         rte_i40e_dev_atomic_write_link_status(dev, &link);
2083         if (link.link_status == old.link_status)
2084                 return -1;
2085
2086         return 0;
2087 }
2088
2089 /* Get all the statistics of a VSI */
2090 void
2091 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2092 {
2093         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2094         struct i40e_eth_stats *nes = &vsi->eth_stats;
2095         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2096         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2097
2098         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2099                             vsi->offset_loaded, &oes->rx_bytes,
2100                             &nes->rx_bytes);
2101         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2102                             vsi->offset_loaded, &oes->rx_unicast,
2103                             &nes->rx_unicast);
2104         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2105                             vsi->offset_loaded, &oes->rx_multicast,
2106                             &nes->rx_multicast);
2107         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2108                             vsi->offset_loaded, &oes->rx_broadcast,
2109                             &nes->rx_broadcast);
2110         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2111                             &oes->rx_discards, &nes->rx_discards);
2112         /* GLV_REPC not supported */
2113         /* GLV_RMPC not supported */
2114         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2115                             &oes->rx_unknown_protocol,
2116                             &nes->rx_unknown_protocol);
2117         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2118                             vsi->offset_loaded, &oes->tx_bytes,
2119                             &nes->tx_bytes);
2120         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2121                             vsi->offset_loaded, &oes->tx_unicast,
2122                             &nes->tx_unicast);
2123         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2124                             vsi->offset_loaded, &oes->tx_multicast,
2125                             &nes->tx_multicast);
2126         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2127                             vsi->offset_loaded,  &oes->tx_broadcast,
2128                             &nes->tx_broadcast);
2129         /* GLV_TDPC not supported */
2130         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2131                             &oes->tx_errors, &nes->tx_errors);
2132         vsi->offset_loaded = true;
2133
2134         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2135                     vsi->vsi_id);
2136         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2137         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2138         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2139         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2140         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2141         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2142                     nes->rx_unknown_protocol);
2143         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2144         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2145         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2146         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2147         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2148         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2149         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2150                     vsi->vsi_id);
2151 }
2152
2153 static void
2154 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2155 {
2156         unsigned int i;
2157         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2158         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2159
2160         /* Get statistics of struct i40e_eth_stats */
2161         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2162                             I40E_GLPRT_GORCL(hw->port),
2163                             pf->offset_loaded, &os->eth.rx_bytes,
2164                             &ns->eth.rx_bytes);
2165         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2166                             I40E_GLPRT_UPRCL(hw->port),
2167                             pf->offset_loaded, &os->eth.rx_unicast,
2168                             &ns->eth.rx_unicast);
2169         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2170                             I40E_GLPRT_MPRCL(hw->port),
2171                             pf->offset_loaded, &os->eth.rx_multicast,
2172                             &ns->eth.rx_multicast);
2173         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2174                             I40E_GLPRT_BPRCL(hw->port),
2175                             pf->offset_loaded, &os->eth.rx_broadcast,
2176                             &ns->eth.rx_broadcast);
2177         /* Workaround: CRC size should not be included in byte statistics,
2178          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2179          */
2180         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2181                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2182
2183         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2184                             pf->offset_loaded, &os->eth.rx_discards,
2185                             &ns->eth.rx_discards);
2186         /* GLPRT_REPC not supported */
2187         /* GLPRT_RMPC not supported */
2188         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2189                             pf->offset_loaded,
2190                             &os->eth.rx_unknown_protocol,
2191                             &ns->eth.rx_unknown_protocol);
2192         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2193                             I40E_GLPRT_GOTCL(hw->port),
2194                             pf->offset_loaded, &os->eth.tx_bytes,
2195                             &ns->eth.tx_bytes);
2196         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2197                             I40E_GLPRT_UPTCL(hw->port),
2198                             pf->offset_loaded, &os->eth.tx_unicast,
2199                             &ns->eth.tx_unicast);
2200         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2201                             I40E_GLPRT_MPTCL(hw->port),
2202                             pf->offset_loaded, &os->eth.tx_multicast,
2203                             &ns->eth.tx_multicast);
2204         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2205                             I40E_GLPRT_BPTCL(hw->port),
2206                             pf->offset_loaded, &os->eth.tx_broadcast,
2207                             &ns->eth.tx_broadcast);
2208         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2209                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2210         /* GLPRT_TEPC not supported */
2211
2212         /* additional port specific stats */
2213         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2214                             pf->offset_loaded, &os->tx_dropped_link_down,
2215                             &ns->tx_dropped_link_down);
2216         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2217                             pf->offset_loaded, &os->crc_errors,
2218                             &ns->crc_errors);
2219         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2220                             pf->offset_loaded, &os->illegal_bytes,
2221                             &ns->illegal_bytes);
2222         /* GLPRT_ERRBC not supported */
2223         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2224                             pf->offset_loaded, &os->mac_local_faults,
2225                             &ns->mac_local_faults);
2226         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2227                             pf->offset_loaded, &os->mac_remote_faults,
2228                             &ns->mac_remote_faults);
2229         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2230                             pf->offset_loaded, &os->rx_length_errors,
2231                             &ns->rx_length_errors);
2232         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2233                             pf->offset_loaded, &os->link_xon_rx,
2234                             &ns->link_xon_rx);
2235         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2236                             pf->offset_loaded, &os->link_xoff_rx,
2237                             &ns->link_xoff_rx);
2238         for (i = 0; i < 8; i++) {
2239                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2240                                     pf->offset_loaded,
2241                                     &os->priority_xon_rx[i],
2242                                     &ns->priority_xon_rx[i]);
2243                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2244                                     pf->offset_loaded,
2245                                     &os->priority_xoff_rx[i],
2246                                     &ns->priority_xoff_rx[i]);
2247         }
2248         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2249                             pf->offset_loaded, &os->link_xon_tx,
2250                             &ns->link_xon_tx);
2251         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2252                             pf->offset_loaded, &os->link_xoff_tx,
2253                             &ns->link_xoff_tx);
2254         for (i = 0; i < 8; i++) {
2255                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2256                                     pf->offset_loaded,
2257                                     &os->priority_xon_tx[i],
2258                                     &ns->priority_xon_tx[i]);
2259                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2260                                     pf->offset_loaded,
2261                                     &os->priority_xoff_tx[i],
2262                                     &ns->priority_xoff_tx[i]);
2263                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2264                                     pf->offset_loaded,
2265                                     &os->priority_xon_2_xoff[i],
2266                                     &ns->priority_xon_2_xoff[i]);
2267         }
2268         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2269                             I40E_GLPRT_PRC64L(hw->port),
2270                             pf->offset_loaded, &os->rx_size_64,
2271                             &ns->rx_size_64);
2272         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2273                             I40E_GLPRT_PRC127L(hw->port),
2274                             pf->offset_loaded, &os->rx_size_127,
2275                             &ns->rx_size_127);
2276         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2277                             I40E_GLPRT_PRC255L(hw->port),
2278                             pf->offset_loaded, &os->rx_size_255,
2279                             &ns->rx_size_255);
2280         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2281                             I40E_GLPRT_PRC511L(hw->port),
2282                             pf->offset_loaded, &os->rx_size_511,
2283                             &ns->rx_size_511);
2284         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2285                             I40E_GLPRT_PRC1023L(hw->port),
2286                             pf->offset_loaded, &os->rx_size_1023,
2287                             &ns->rx_size_1023);
2288         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2289                             I40E_GLPRT_PRC1522L(hw->port),
2290                             pf->offset_loaded, &os->rx_size_1522,
2291                             &ns->rx_size_1522);
2292         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2293                             I40E_GLPRT_PRC9522L(hw->port),
2294                             pf->offset_loaded, &os->rx_size_big,
2295                             &ns->rx_size_big);
2296         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2297                             pf->offset_loaded, &os->rx_undersize,
2298                             &ns->rx_undersize);
2299         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2300                             pf->offset_loaded, &os->rx_fragments,
2301                             &ns->rx_fragments);
2302         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2303                             pf->offset_loaded, &os->rx_oversize,
2304                             &ns->rx_oversize);
2305         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2306                             pf->offset_loaded, &os->rx_jabber,
2307                             &ns->rx_jabber);
2308         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2309                             I40E_GLPRT_PTC64L(hw->port),
2310                             pf->offset_loaded, &os->tx_size_64,
2311                             &ns->tx_size_64);
2312         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2313                             I40E_GLPRT_PTC127L(hw->port),
2314                             pf->offset_loaded, &os->tx_size_127,
2315                             &ns->tx_size_127);
2316         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2317                             I40E_GLPRT_PTC255L(hw->port),
2318                             pf->offset_loaded, &os->tx_size_255,
2319                             &ns->tx_size_255);
2320         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2321                             I40E_GLPRT_PTC511L(hw->port),
2322                             pf->offset_loaded, &os->tx_size_511,
2323                             &ns->tx_size_511);
2324         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2325                             I40E_GLPRT_PTC1023L(hw->port),
2326                             pf->offset_loaded, &os->tx_size_1023,
2327                             &ns->tx_size_1023);
2328         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2329                             I40E_GLPRT_PTC1522L(hw->port),
2330                             pf->offset_loaded, &os->tx_size_1522,
2331                             &ns->tx_size_1522);
2332         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2333                             I40E_GLPRT_PTC9522L(hw->port),
2334                             pf->offset_loaded, &os->tx_size_big,
2335                             &ns->tx_size_big);
2336         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2337                            pf->offset_loaded,
2338                            &os->fd_sb_match, &ns->fd_sb_match);
2339         /* GLPRT_MSPDC not supported */
2340         /* GLPRT_XEC not supported */
2341
2342         pf->offset_loaded = true;
2343
2344         if (pf->main_vsi)
2345                 i40e_update_vsi_stats(pf->main_vsi);
2346 }
2347
2348 /* Get all statistics of a port */
2349 static void
2350 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2351 {
2352         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2353         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2354         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2355         unsigned i;
2356
2357         /* call read registers - updates values, now write them to struct */
2358         i40e_read_stats_registers(pf, hw);
2359
2360         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2361                         pf->main_vsi->eth_stats.rx_multicast +
2362                         pf->main_vsi->eth_stats.rx_broadcast -
2363                         pf->main_vsi->eth_stats.rx_discards;
2364         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2365                         pf->main_vsi->eth_stats.tx_multicast +
2366                         pf->main_vsi->eth_stats.tx_broadcast;
2367         stats->ibytes   = ns->eth.rx_bytes;
2368         stats->obytes   = ns->eth.tx_bytes;
2369         stats->oerrors  = ns->eth.tx_errors +
2370                         pf->main_vsi->eth_stats.tx_errors;
2371
2372         /* Rx Errors */
2373         stats->imissed  = ns->eth.rx_discards +
2374                         pf->main_vsi->eth_stats.rx_discards;
2375         stats->ierrors  = ns->crc_errors +
2376                         ns->rx_length_errors + ns->rx_undersize +
2377                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2378
2379         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2380         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2381         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2382         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2383         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2384         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2385         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2386                     ns->eth.rx_unknown_protocol);
2387         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2388         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2389         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2390         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2391         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2392         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2393
2394         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2395                     ns->tx_dropped_link_down);
2396         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2397         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2398                     ns->illegal_bytes);
2399         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2400         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2401                     ns->mac_local_faults);
2402         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2403                     ns->mac_remote_faults);
2404         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2405                     ns->rx_length_errors);
2406         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2407         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2408         for (i = 0; i < 8; i++) {
2409                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2410                                 i, ns->priority_xon_rx[i]);
2411                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2412                                 i, ns->priority_xoff_rx[i]);
2413         }
2414         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2415         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2416         for (i = 0; i < 8; i++) {
2417                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2418                                 i, ns->priority_xon_tx[i]);
2419                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2420                                 i, ns->priority_xoff_tx[i]);
2421                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2422                                 i, ns->priority_xon_2_xoff[i]);
2423         }
2424         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2425         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2426         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2427         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2428         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2429         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2430         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2431         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2432         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2433         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2434         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2435         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2436         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2437         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2438         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2439         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2440         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2441         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2442         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2443                         ns->mac_short_packet_dropped);
2444         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2445                     ns->checksum_error);
2446         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2447         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2448 }
2449
2450 /* Reset the statistics */
2451 static void
2452 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2453 {
2454         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2455         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2456
2457         /* Mark PF and VSI stats to update the offset, aka "reset" */
2458         pf->offset_loaded = false;
2459         if (pf->main_vsi)
2460                 pf->main_vsi->offset_loaded = false;
2461
2462         /* read the stats, reading current register values into offset */
2463         i40e_read_stats_registers(pf, hw);
2464 }
2465
2466 static uint32_t
2467 i40e_xstats_calc_num(void)
2468 {
2469         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2470                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2471                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2472 }
2473
2474 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2475                                      struct rte_eth_xstat_name *xstats_names,
2476                                      __rte_unused unsigned limit)
2477 {
2478         unsigned count = 0;
2479         unsigned i, prio;
2480
2481         if (xstats_names == NULL)
2482                 return i40e_xstats_calc_num();
2483
2484         /* Note: limit checked in rte_eth_xstats_names() */
2485
2486         /* Get stats from i40e_eth_stats struct */
2487         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2488                 snprintf(xstats_names[count].name,
2489                          sizeof(xstats_names[count].name),
2490                          "%s", rte_i40e_stats_strings[i].name);
2491                 count++;
2492         }
2493
2494         /* Get individiual stats from i40e_hw_port struct */
2495         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2496                 snprintf(xstats_names[count].name,
2497                         sizeof(xstats_names[count].name),
2498                          "%s", rte_i40e_hw_port_strings[i].name);
2499                 count++;
2500         }
2501
2502         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2503                 for (prio = 0; prio < 8; prio++) {
2504                         snprintf(xstats_names[count].name,
2505                                  sizeof(xstats_names[count].name),
2506                                  "rx_priority%u_%s", prio,
2507                                  rte_i40e_rxq_prio_strings[i].name);
2508                         count++;
2509                 }
2510         }
2511
2512         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2513                 for (prio = 0; prio < 8; prio++) {
2514                         snprintf(xstats_names[count].name,
2515                                  sizeof(xstats_names[count].name),
2516                                  "tx_priority%u_%s", prio,
2517                                  rte_i40e_txq_prio_strings[i].name);
2518                         count++;
2519                 }
2520         }
2521         return count;
2522 }
2523
2524 static int
2525 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2526                     unsigned n)
2527 {
2528         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2529         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2530         unsigned i, count, prio;
2531         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2532
2533         count = i40e_xstats_calc_num();
2534         if (n < count)
2535                 return count;
2536
2537         i40e_read_stats_registers(pf, hw);
2538
2539         if (xstats == NULL)
2540                 return 0;
2541
2542         count = 0;
2543
2544         /* Get stats from i40e_eth_stats struct */
2545         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2546                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2547                         rte_i40e_stats_strings[i].offset);
2548                 count++;
2549         }
2550
2551         /* Get individiual stats from i40e_hw_port struct */
2552         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2553                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2554                         rte_i40e_hw_port_strings[i].offset);
2555                 count++;
2556         }
2557
2558         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2559                 for (prio = 0; prio < 8; prio++) {
2560                         xstats[count].value =
2561                                 *(uint64_t *)(((char *)hw_stats) +
2562                                 rte_i40e_rxq_prio_strings[i].offset +
2563                                 (sizeof(uint64_t) * prio));
2564                         count++;
2565                 }
2566         }
2567
2568         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2569                 for (prio = 0; prio < 8; prio++) {
2570                         xstats[count].value =
2571                                 *(uint64_t *)(((char *)hw_stats) +
2572                                 rte_i40e_txq_prio_strings[i].offset +
2573                                 (sizeof(uint64_t) * prio));
2574                         count++;
2575                 }
2576         }
2577
2578         return count;
2579 }
2580
2581 static int
2582 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2583                                  __rte_unused uint16_t queue_id,
2584                                  __rte_unused uint8_t stat_idx,
2585                                  __rte_unused uint8_t is_rx)
2586 {
2587         PMD_INIT_FUNC_TRACE();
2588
2589         return -ENOSYS;
2590 }
2591
2592 static void
2593 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2594 {
2595         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2596         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2597         struct i40e_vsi *vsi = pf->main_vsi;
2598         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2599
2600         dev_info->pci_dev = pci_dev;
2601         dev_info->max_rx_queues = vsi->nb_qps;
2602         dev_info->max_tx_queues = vsi->nb_qps;
2603         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2604         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2605         dev_info->max_mac_addrs = vsi->max_macaddrs;
2606         dev_info->max_vfs = pci_dev->max_vfs;
2607         dev_info->rx_offload_capa =
2608                 DEV_RX_OFFLOAD_VLAN_STRIP |
2609                 DEV_RX_OFFLOAD_QINQ_STRIP |
2610                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2611                 DEV_RX_OFFLOAD_UDP_CKSUM |
2612                 DEV_RX_OFFLOAD_TCP_CKSUM;
2613         dev_info->tx_offload_capa =
2614                 DEV_TX_OFFLOAD_VLAN_INSERT |
2615                 DEV_TX_OFFLOAD_QINQ_INSERT |
2616                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2617                 DEV_TX_OFFLOAD_UDP_CKSUM |
2618                 DEV_TX_OFFLOAD_TCP_CKSUM |
2619                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2620                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2621                 DEV_TX_OFFLOAD_TCP_TSO |
2622                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2623                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2624                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2625                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2626         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2627                                                 sizeof(uint32_t);
2628         dev_info->reta_size = pf->hash_lut_size;
2629         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2630
2631         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2632                 .rx_thresh = {
2633                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2634                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2635                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2636                 },
2637                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2638                 .rx_drop_en = 0,
2639         };
2640
2641         dev_info->default_txconf = (struct rte_eth_txconf) {
2642                 .tx_thresh = {
2643                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2644                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2645                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2646                 },
2647                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2648                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2649                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2650                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2651         };
2652
2653         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2654                 .nb_max = I40E_MAX_RING_DESC,
2655                 .nb_min = I40E_MIN_RING_DESC,
2656                 .nb_align = I40E_ALIGN_RING_DESC,
2657         };
2658
2659         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2660                 .nb_max = I40E_MAX_RING_DESC,
2661                 .nb_min = I40E_MIN_RING_DESC,
2662                 .nb_align = I40E_ALIGN_RING_DESC,
2663         };
2664
2665         if (pf->flags & I40E_FLAG_VMDQ) {
2666                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2667                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2668                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2669                                                 pf->max_nb_vmdq_vsi;
2670                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2671                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2672                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2673         }
2674
2675         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2676                 /* For XL710 */
2677                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2678         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2679                 /* For XXV710 */
2680                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2681         else
2682                 /* For X710 */
2683                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2684 }
2685
2686 static int
2687 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2688 {
2689         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2690         struct i40e_vsi *vsi = pf->main_vsi;
2691         PMD_INIT_FUNC_TRACE();
2692
2693         if (on)
2694                 return i40e_vsi_add_vlan(vsi, vlan_id);
2695         else
2696                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2697 }
2698
2699 static int
2700 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2701                    enum rte_vlan_type vlan_type,
2702                    uint16_t tpid)
2703 {
2704         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2705         uint64_t reg_r = 0, reg_w = 0;
2706         uint16_t reg_id = 0;
2707         int ret = 0;
2708         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2709
2710         switch (vlan_type) {
2711         case ETH_VLAN_TYPE_OUTER:
2712                 if (qinq)
2713                         reg_id = 2;
2714                 else
2715                         reg_id = 3;
2716                 break;
2717         case ETH_VLAN_TYPE_INNER:
2718                 if (qinq)
2719                         reg_id = 3;
2720                 else {
2721                         ret = -EINVAL;
2722                         PMD_DRV_LOG(ERR,
2723                                 "Unsupported vlan type in single vlan.\n");
2724                         return ret;
2725                 }
2726                 break;
2727         default:
2728                 ret = -EINVAL;
2729                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2730                 return ret;
2731         }
2732         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2733                                           &reg_r, NULL);
2734         if (ret != I40E_SUCCESS) {
2735                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2736                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2737                 ret = -EIO;
2738                 return ret;
2739         }
2740         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2741                     "0x%08"PRIx64"", reg_id, reg_r);
2742
2743         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2744         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2745         if (reg_r == reg_w) {
2746                 ret = 0;
2747                 PMD_DRV_LOG(DEBUG, "No need to write");
2748                 return ret;
2749         }
2750
2751         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2752                                            reg_w, NULL);
2753         if (ret != I40E_SUCCESS) {
2754                 ret = -EIO;
2755                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2756                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2757                 return ret;
2758         }
2759         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2760                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2761
2762         return ret;
2763 }
2764
2765 static void
2766 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2767 {
2768         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2769         struct i40e_vsi *vsi = pf->main_vsi;
2770
2771         if (mask & ETH_VLAN_FILTER_MASK) {
2772                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2773                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2774                 else
2775                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2776         }
2777
2778         if (mask & ETH_VLAN_STRIP_MASK) {
2779                 /* Enable or disable VLAN stripping */
2780                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2781                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2782                 else
2783                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2784         }
2785
2786         if (mask & ETH_VLAN_EXTEND_MASK) {
2787                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2788                         i40e_vsi_config_double_vlan(vsi, TRUE);
2789                         /* Set global registers with default ether type value */
2790                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2791                                            ETHER_TYPE_VLAN);
2792                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2793                                            ETHER_TYPE_VLAN);
2794                 }
2795                 else
2796                         i40e_vsi_config_double_vlan(vsi, FALSE);
2797         }
2798 }
2799
2800 static void
2801 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2802                           __rte_unused uint16_t queue,
2803                           __rte_unused int on)
2804 {
2805         PMD_INIT_FUNC_TRACE();
2806 }
2807
2808 static int
2809 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2810 {
2811         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2812         struct i40e_vsi *vsi = pf->main_vsi;
2813         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2814         struct i40e_vsi_vlan_pvid_info info;
2815
2816         memset(&info, 0, sizeof(info));
2817         info.on = on;
2818         if (info.on)
2819                 info.config.pvid = pvid;
2820         else {
2821                 info.config.reject.tagged =
2822                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2823                 info.config.reject.untagged =
2824                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2825         }
2826
2827         return i40e_vsi_vlan_pvid_set(vsi, &info);
2828 }
2829
2830 static int
2831 i40e_dev_led_on(struct rte_eth_dev *dev)
2832 {
2833         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2834         uint32_t mode = i40e_led_get(hw);
2835
2836         if (mode == 0)
2837                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2838
2839         return 0;
2840 }
2841
2842 static int
2843 i40e_dev_led_off(struct rte_eth_dev *dev)
2844 {
2845         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2846         uint32_t mode = i40e_led_get(hw);
2847
2848         if (mode != 0)
2849                 i40e_led_set(hw, 0, false);
2850
2851         return 0;
2852 }
2853
2854 static int
2855 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2856 {
2857         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2858         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2859
2860         fc_conf->pause_time = pf->fc_conf.pause_time;
2861         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2862         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2863
2864          /* Return current mode according to actual setting*/
2865         switch (hw->fc.current_mode) {
2866         case I40E_FC_FULL:
2867                 fc_conf->mode = RTE_FC_FULL;
2868                 break;
2869         case I40E_FC_TX_PAUSE:
2870                 fc_conf->mode = RTE_FC_TX_PAUSE;
2871                 break;
2872         case I40E_FC_RX_PAUSE:
2873                 fc_conf->mode = RTE_FC_RX_PAUSE;
2874                 break;
2875         case I40E_FC_NONE:
2876         default:
2877                 fc_conf->mode = RTE_FC_NONE;
2878         };
2879
2880         return 0;
2881 }
2882
2883 static int
2884 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2885 {
2886         uint32_t mflcn_reg, fctrl_reg, reg;
2887         uint32_t max_high_water;
2888         uint8_t i, aq_failure;
2889         int err;
2890         struct i40e_hw *hw;
2891         struct i40e_pf *pf;
2892         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2893                 [RTE_FC_NONE] = I40E_FC_NONE,
2894                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2895                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2896                 [RTE_FC_FULL] = I40E_FC_FULL
2897         };
2898
2899         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2900
2901         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2902         if ((fc_conf->high_water > max_high_water) ||
2903                         (fc_conf->high_water < fc_conf->low_water)) {
2904                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2905                         "High_water must <= %d.", max_high_water);
2906                 return -EINVAL;
2907         }
2908
2909         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2910         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2911         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2912
2913         pf->fc_conf.pause_time = fc_conf->pause_time;
2914         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2915         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2916
2917         PMD_INIT_FUNC_TRACE();
2918
2919         /* All the link flow control related enable/disable register
2920          * configuration is handle by the F/W
2921          */
2922         err = i40e_set_fc(hw, &aq_failure, true);
2923         if (err < 0)
2924                 return -ENOSYS;
2925
2926         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
2927                 /* Configure flow control refresh threshold,
2928                  * the value for stat_tx_pause_refresh_timer[8]
2929                  * is used for global pause operation.
2930                  */
2931
2932                 I40E_WRITE_REG(hw,
2933                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2934                                pf->fc_conf.pause_time);
2935
2936                 /* configure the timer value included in transmitted pause
2937                  * frame,
2938                  * the value for stat_tx_pause_quanta[8] is used for global
2939                  * pause operation
2940                  */
2941                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2942                                pf->fc_conf.pause_time);
2943
2944                 fctrl_reg = I40E_READ_REG(hw,
2945                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2946
2947                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2948                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2949                 else
2950                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2951
2952                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2953                                fctrl_reg);
2954         } else {
2955                 /* Configure pause time (2 TCs per register) */
2956                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2957                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2958                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2959
2960                 /* Configure flow control refresh threshold value */
2961                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2962                                pf->fc_conf.pause_time / 2);
2963
2964                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2965
2966                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2967                  *depending on configuration
2968                  */
2969                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2970                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2971                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2972                 } else {
2973                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2974                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2975                 }
2976
2977                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2978         }
2979
2980         /* config the water marker both based on the packets and bytes */
2981         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2982                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2983                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2984         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2985                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2986                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2987         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2988                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2989                        << I40E_KILOSHIFT);
2990         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2991                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2992                        << I40E_KILOSHIFT);
2993
2994         I40E_WRITE_FLUSH(hw);
2995
2996         return 0;
2997 }
2998
2999 static int
3000 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3001                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3002 {
3003         PMD_INIT_FUNC_TRACE();
3004
3005         return -ENOSYS;
3006 }
3007
3008 /* Add a MAC address, and update filters */
3009 static void
3010 i40e_macaddr_add(struct rte_eth_dev *dev,
3011                  struct ether_addr *mac_addr,
3012                  __rte_unused uint32_t index,
3013                  uint32_t pool)
3014 {
3015         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3016         struct i40e_mac_filter_info mac_filter;
3017         struct i40e_vsi *vsi;
3018         int ret;
3019
3020         /* If VMDQ not enabled or configured, return */
3021         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3022                           !pf->nb_cfg_vmdq_vsi)) {
3023                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3024                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3025                         pool);
3026                 return;
3027         }
3028
3029         if (pool > pf->nb_cfg_vmdq_vsi) {
3030                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3031                                 pool, pf->nb_cfg_vmdq_vsi);
3032                 return;
3033         }
3034
3035         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3036         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3037                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3038         else
3039                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3040
3041         if (pool == 0)
3042                 vsi = pf->main_vsi;
3043         else
3044                 vsi = pf->vmdq[pool - 1].vsi;
3045
3046         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3047         if (ret != I40E_SUCCESS) {
3048                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3049                 return;
3050         }
3051 }
3052
3053 /* Remove a MAC address, and update filters */
3054 static void
3055 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3056 {
3057         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3058         struct i40e_vsi *vsi;
3059         struct rte_eth_dev_data *data = dev->data;
3060         struct ether_addr *macaddr;
3061         int ret;
3062         uint32_t i;
3063         uint64_t pool_sel;
3064
3065         macaddr = &(data->mac_addrs[index]);
3066
3067         pool_sel = dev->data->mac_pool_sel[index];
3068
3069         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3070                 if (pool_sel & (1ULL << i)) {
3071                         if (i == 0)
3072                                 vsi = pf->main_vsi;
3073                         else {
3074                                 /* No VMDQ pool enabled or configured */
3075                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3076                                         (i > pf->nb_cfg_vmdq_vsi)) {
3077                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3078                                                         "/configured");
3079                                         return;
3080                                 }
3081                                 vsi = pf->vmdq[i - 1].vsi;
3082                         }
3083                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3084
3085                         if (ret) {
3086                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3087                                 return;
3088                         }
3089                 }
3090         }
3091 }
3092
3093 /* Set perfect match or hash match of MAC and VLAN for a VF */
3094 static int
3095 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3096                  struct rte_eth_mac_filter *filter,
3097                  bool add)
3098 {
3099         struct i40e_hw *hw;
3100         struct i40e_mac_filter_info mac_filter;
3101         struct ether_addr old_mac;
3102         struct ether_addr *new_mac;
3103         struct i40e_pf_vf *vf = NULL;
3104         uint16_t vf_id;
3105         int ret;
3106
3107         if (pf == NULL) {
3108                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3109                 return -EINVAL;
3110         }
3111         hw = I40E_PF_TO_HW(pf);
3112
3113         if (filter == NULL) {
3114                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3115                 return -EINVAL;
3116         }
3117
3118         new_mac = &filter->mac_addr;
3119
3120         if (is_zero_ether_addr(new_mac)) {
3121                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3122                 return -EINVAL;
3123         }
3124
3125         vf_id = filter->dst_id;
3126
3127         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3128                 PMD_DRV_LOG(ERR, "Invalid argument.");
3129                 return -EINVAL;
3130         }
3131         vf = &pf->vfs[vf_id];
3132
3133         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3134                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3135                 return -EINVAL;
3136         }
3137
3138         if (add) {
3139                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3140                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3141                                 ETHER_ADDR_LEN);
3142                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3143                                  ETHER_ADDR_LEN);
3144
3145                 mac_filter.filter_type = filter->filter_type;
3146                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3147                 if (ret != I40E_SUCCESS) {
3148                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3149                         return -1;
3150                 }
3151                 ether_addr_copy(new_mac, &pf->dev_addr);
3152         } else {
3153                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3154                                 ETHER_ADDR_LEN);
3155                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3156                 if (ret != I40E_SUCCESS) {
3157                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3158                         return -1;
3159                 }
3160
3161                 /* Clear device address as it has been removed */
3162                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3163                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3164         }
3165
3166         return 0;
3167 }
3168
3169 /* MAC filter handle */
3170 static int
3171 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3172                 void *arg)
3173 {
3174         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3175         struct rte_eth_mac_filter *filter;
3176         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3177         int ret = I40E_NOT_SUPPORTED;
3178
3179         filter = (struct rte_eth_mac_filter *)(arg);
3180
3181         switch (filter_op) {
3182         case RTE_ETH_FILTER_NOP:
3183                 ret = I40E_SUCCESS;
3184                 break;
3185         case RTE_ETH_FILTER_ADD:
3186                 i40e_pf_disable_irq0(hw);
3187                 if (filter->is_vf)
3188                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3189                 i40e_pf_enable_irq0(hw);
3190                 break;
3191         case RTE_ETH_FILTER_DELETE:
3192                 i40e_pf_disable_irq0(hw);
3193                 if (filter->is_vf)
3194                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3195                 i40e_pf_enable_irq0(hw);
3196                 break;
3197         default:
3198                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3199                 ret = I40E_ERR_PARAM;
3200                 break;
3201         }
3202
3203         return ret;
3204 }
3205
3206 static int
3207 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3208 {
3209         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3210         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3211         int ret;
3212
3213         if (!lut)
3214                 return -EINVAL;
3215
3216         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3217                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3218                                           lut, lut_size);
3219                 if (ret) {
3220                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3221                         return ret;
3222                 }
3223         } else {
3224                 uint32_t *lut_dw = (uint32_t *)lut;
3225                 uint16_t i, lut_size_dw = lut_size / 4;
3226
3227                 for (i = 0; i < lut_size_dw; i++)
3228                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3229         }
3230
3231         return 0;
3232 }
3233
3234 static int
3235 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3236 {
3237         struct i40e_pf *pf;
3238         struct i40e_hw *hw;
3239         int ret;
3240
3241         if (!vsi || !lut)
3242                 return -EINVAL;
3243
3244         pf = I40E_VSI_TO_PF(vsi);
3245         hw = I40E_VSI_TO_HW(vsi);
3246
3247         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3248                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3249                                           lut, lut_size);
3250                 if (ret) {
3251                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3252                         return ret;
3253                 }
3254         } else {
3255                 uint32_t *lut_dw = (uint32_t *)lut;
3256                 uint16_t i, lut_size_dw = lut_size / 4;
3257
3258                 for (i = 0; i < lut_size_dw; i++)
3259                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3260                 I40E_WRITE_FLUSH(hw);
3261         }
3262
3263         return 0;
3264 }
3265
3266 static int
3267 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3268                          struct rte_eth_rss_reta_entry64 *reta_conf,
3269                          uint16_t reta_size)
3270 {
3271         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3272         uint16_t i, lut_size = pf->hash_lut_size;
3273         uint16_t idx, shift;
3274         uint8_t *lut;
3275         int ret;
3276
3277         if (reta_size != lut_size ||
3278                 reta_size > ETH_RSS_RETA_SIZE_512) {
3279                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3280                         "(%d) doesn't match the number hardware can supported "
3281                                         "(%d)\n", reta_size, lut_size);
3282                 return -EINVAL;
3283         }
3284
3285         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3286         if (!lut) {
3287                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3288                 return -ENOMEM;
3289         }
3290         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3291         if (ret)
3292                 goto out;
3293         for (i = 0; i < reta_size; i++) {
3294                 idx = i / RTE_RETA_GROUP_SIZE;
3295                 shift = i % RTE_RETA_GROUP_SIZE;
3296                 if (reta_conf[idx].mask & (1ULL << shift))
3297                         lut[i] = reta_conf[idx].reta[shift];
3298         }
3299         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3300
3301 out:
3302         rte_free(lut);
3303
3304         return ret;
3305 }
3306
3307 static int
3308 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3309                         struct rte_eth_rss_reta_entry64 *reta_conf,
3310                         uint16_t reta_size)
3311 {
3312         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3313         uint16_t i, lut_size = pf->hash_lut_size;
3314         uint16_t idx, shift;
3315         uint8_t *lut;
3316         int ret;
3317
3318         if (reta_size != lut_size ||
3319                 reta_size > ETH_RSS_RETA_SIZE_512) {
3320                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3321                         "(%d) doesn't match the number hardware can supported "
3322                                         "(%d)\n", reta_size, lut_size);
3323                 return -EINVAL;
3324         }
3325
3326         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3327         if (!lut) {
3328                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3329                 return -ENOMEM;
3330         }
3331
3332         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3333         if (ret)
3334                 goto out;
3335         for (i = 0; i < reta_size; i++) {
3336                 idx = i / RTE_RETA_GROUP_SIZE;
3337                 shift = i % RTE_RETA_GROUP_SIZE;
3338                 if (reta_conf[idx].mask & (1ULL << shift))
3339                         reta_conf[idx].reta[shift] = lut[i];
3340         }
3341
3342 out:
3343         rte_free(lut);
3344
3345         return ret;
3346 }
3347
3348 /**
3349  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3350  * @hw:   pointer to the HW structure
3351  * @mem:  pointer to mem struct to fill out
3352  * @size: size of memory requested
3353  * @alignment: what to align the allocation to
3354  **/
3355 enum i40e_status_code
3356 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3357                         struct i40e_dma_mem *mem,
3358                         u64 size,
3359                         u32 alignment)
3360 {
3361         const struct rte_memzone *mz = NULL;
3362         char z_name[RTE_MEMZONE_NAMESIZE];
3363
3364         if (!mem)
3365                 return I40E_ERR_PARAM;
3366
3367         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3368         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3369                                          alignment, RTE_PGSIZE_2M);
3370         if (!mz)
3371                 return I40E_ERR_NO_MEMORY;
3372
3373         mem->size = size;
3374         mem->va = mz->addr;
3375         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3376         mem->zone = (const void *)mz;
3377         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3378                     "%"PRIu64, mz->name, mem->pa);
3379
3380         return I40E_SUCCESS;
3381 }
3382
3383 /**
3384  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3385  * @hw:   pointer to the HW structure
3386  * @mem:  ptr to mem struct to free
3387  **/
3388 enum i40e_status_code
3389 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3390                     struct i40e_dma_mem *mem)
3391 {
3392         if (!mem)
3393                 return I40E_ERR_PARAM;
3394
3395         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3396                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3397                     mem->pa);
3398         rte_memzone_free((const struct rte_memzone *)mem->zone);
3399         mem->zone = NULL;
3400         mem->va = NULL;
3401         mem->pa = (u64)0;
3402
3403         return I40E_SUCCESS;
3404 }
3405
3406 /**
3407  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3408  * @hw:   pointer to the HW structure
3409  * @mem:  pointer to mem struct to fill out
3410  * @size: size of memory requested
3411  **/
3412 enum i40e_status_code
3413 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3414                          struct i40e_virt_mem *mem,
3415                          u32 size)
3416 {
3417         if (!mem)
3418                 return I40E_ERR_PARAM;
3419
3420         mem->size = size;
3421         mem->va = rte_zmalloc("i40e", size, 0);
3422
3423         if (mem->va)
3424                 return I40E_SUCCESS;
3425         else
3426                 return I40E_ERR_NO_MEMORY;
3427 }
3428
3429 /**
3430  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3431  * @hw:   pointer to the HW structure
3432  * @mem:  pointer to mem struct to free
3433  **/
3434 enum i40e_status_code
3435 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3436                      struct i40e_virt_mem *mem)
3437 {
3438         if (!mem)
3439                 return I40E_ERR_PARAM;
3440
3441         rte_free(mem->va);
3442         mem->va = NULL;
3443
3444         return I40E_SUCCESS;
3445 }
3446
3447 void
3448 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3449 {
3450         rte_spinlock_init(&sp->spinlock);
3451 }
3452
3453 void
3454 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3455 {
3456         rte_spinlock_lock(&sp->spinlock);
3457 }
3458
3459 void
3460 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3461 {
3462         rte_spinlock_unlock(&sp->spinlock);
3463 }
3464
3465 void
3466 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3467 {
3468         return;
3469 }
3470
3471 /**
3472  * Get the hardware capabilities, which will be parsed
3473  * and saved into struct i40e_hw.
3474  */
3475 static int
3476 i40e_get_cap(struct i40e_hw *hw)
3477 {
3478         struct i40e_aqc_list_capabilities_element_resp *buf;
3479         uint16_t len, size = 0;
3480         int ret;
3481
3482         /* Calculate a huge enough buff for saving response data temporarily */
3483         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3484                                                 I40E_MAX_CAP_ELE_NUM;
3485         buf = rte_zmalloc("i40e", len, 0);
3486         if (!buf) {
3487                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3488                 return I40E_ERR_NO_MEMORY;
3489         }
3490
3491         /* Get, parse the capabilities and save it to hw */
3492         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3493                         i40e_aqc_opc_list_func_capabilities, NULL);
3494         if (ret != I40E_SUCCESS)
3495                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3496
3497         /* Free the temporary buffer after being used */
3498         rte_free(buf);
3499
3500         return ret;
3501 }
3502
3503 static int
3504 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3505 {
3506         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3507         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3508         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3509         uint16_t qp_count = 0, vsi_count = 0;
3510
3511         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3512                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3513                 return -EINVAL;
3514         }
3515         /* Add the parameter init for LFC */
3516         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3517         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3518         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3519
3520         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3521         pf->max_num_vsi = hw->func_caps.num_vsis;
3522         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3523         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3524         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3525
3526         /* FDir queue/VSI allocation */
3527         pf->fdir_qp_offset = 0;
3528         if (hw->func_caps.fd) {
3529                 pf->flags |= I40E_FLAG_FDIR;
3530                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3531         } else {
3532                 pf->fdir_nb_qps = 0;
3533         }
3534         qp_count += pf->fdir_nb_qps;
3535         vsi_count += 1;
3536
3537         /* LAN queue/VSI allocation */
3538         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3539         if (!hw->func_caps.rss) {
3540                 pf->lan_nb_qps = 1;
3541         } else {
3542                 pf->flags |= I40E_FLAG_RSS;
3543                 if (hw->mac.type == I40E_MAC_X722)
3544                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3545                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3546         }
3547         qp_count += pf->lan_nb_qps;
3548         vsi_count += 1;
3549
3550         /* VF queue/VSI allocation */
3551         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3552         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3553                 pf->flags |= I40E_FLAG_SRIOV;
3554                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3555                 pf->vf_num = pci_dev->max_vfs;
3556                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3557                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3558                             pf->vf_nb_qps * pf->vf_num);
3559         } else {
3560                 pf->vf_nb_qps = 0;
3561                 pf->vf_num = 0;
3562         }
3563         qp_count += pf->vf_nb_qps * pf->vf_num;
3564         vsi_count += pf->vf_num;
3565
3566         /* VMDq queue/VSI allocation */
3567         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3568         pf->vmdq_nb_qps = 0;
3569         pf->max_nb_vmdq_vsi = 0;
3570         if (hw->func_caps.vmdq) {
3571                 if (qp_count < hw->func_caps.num_tx_qp &&
3572                         vsi_count < hw->func_caps.num_vsis) {
3573                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3574                                 qp_count) / pf->vmdq_nb_qp_max;
3575
3576                         /* Limit the maximum number of VMDq vsi to the maximum
3577                          * ethdev can support
3578                          */
3579                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3580                                 hw->func_caps.num_vsis - vsi_count);
3581                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3582                                 ETH_64_POOLS);
3583                         if (pf->max_nb_vmdq_vsi) {
3584                                 pf->flags |= I40E_FLAG_VMDQ;
3585                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3586                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3587                                             "per VMDQ VSI, in total %u queues",
3588                                             pf->max_nb_vmdq_vsi,
3589                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3590                                             pf->max_nb_vmdq_vsi);
3591                         } else {
3592                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3593                                             "VMDq");
3594                         }
3595                 } else {
3596                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3597                 }
3598         }
3599         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3600         vsi_count += pf->max_nb_vmdq_vsi;
3601
3602         if (hw->func_caps.dcb)
3603                 pf->flags |= I40E_FLAG_DCB;
3604
3605         if (qp_count > hw->func_caps.num_tx_qp) {
3606                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3607                             "the hardware maximum %u", qp_count,
3608                             hw->func_caps.num_tx_qp);
3609                 return -EINVAL;
3610         }
3611         if (vsi_count > hw->func_caps.num_vsis) {
3612                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3613                             "the hardware maximum %u", vsi_count,
3614                             hw->func_caps.num_vsis);
3615                 return -EINVAL;
3616         }
3617
3618         return 0;
3619 }
3620
3621 static int
3622 i40e_pf_get_switch_config(struct i40e_pf *pf)
3623 {
3624         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3625         struct i40e_aqc_get_switch_config_resp *switch_config;
3626         struct i40e_aqc_switch_config_element_resp *element;
3627         uint16_t start_seid = 0, num_reported;
3628         int ret;
3629
3630         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3631                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3632         if (!switch_config) {
3633                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3634                 return -ENOMEM;
3635         }
3636
3637         /* Get the switch configurations */
3638         ret = i40e_aq_get_switch_config(hw, switch_config,
3639                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3640         if (ret != I40E_SUCCESS) {
3641                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3642                 goto fail;
3643         }
3644         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3645         if (num_reported != 1) { /* The number should be 1 */
3646                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3647                 goto fail;
3648         }
3649
3650         /* Parse the switch configuration elements */
3651         element = &(switch_config->element[0]);
3652         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3653                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3654                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3655         } else
3656                 PMD_DRV_LOG(INFO, "Unknown element type");
3657
3658 fail:
3659         rte_free(switch_config);
3660
3661         return ret;
3662 }
3663
3664 static int
3665 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3666                         uint32_t num)
3667 {
3668         struct pool_entry *entry;
3669
3670         if (pool == NULL || num == 0)
3671                 return -EINVAL;
3672
3673         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3674         if (entry == NULL) {
3675                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3676                 return -ENOMEM;
3677         }
3678
3679         /* queue heap initialize */
3680         pool->num_free = num;
3681         pool->num_alloc = 0;
3682         pool->base = base;
3683         LIST_INIT(&pool->alloc_list);
3684         LIST_INIT(&pool->free_list);
3685
3686         /* Initialize element  */
3687         entry->base = 0;
3688         entry->len = num;
3689
3690         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3691         return 0;
3692 }
3693
3694 static void
3695 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3696 {
3697         struct pool_entry *entry, *next_entry;
3698
3699         if (pool == NULL)
3700                 return;
3701
3702         for (entry = LIST_FIRST(&pool->alloc_list);
3703                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3704                         entry = next_entry) {
3705                 LIST_REMOVE(entry, next);
3706                 rte_free(entry);
3707         }
3708
3709         for (entry = LIST_FIRST(&pool->free_list);
3710                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3711                         entry = next_entry) {
3712                 LIST_REMOVE(entry, next);
3713                 rte_free(entry);
3714         }
3715
3716         pool->num_free = 0;
3717         pool->num_alloc = 0;
3718         pool->base = 0;
3719         LIST_INIT(&pool->alloc_list);
3720         LIST_INIT(&pool->free_list);
3721 }
3722
3723 static int
3724 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3725                        uint32_t base)
3726 {
3727         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3728         uint32_t pool_offset;
3729         int insert;
3730
3731         if (pool == NULL) {
3732                 PMD_DRV_LOG(ERR, "Invalid parameter");
3733                 return -EINVAL;
3734         }
3735
3736         pool_offset = base - pool->base;
3737         /* Lookup in alloc list */
3738         LIST_FOREACH(entry, &pool->alloc_list, next) {
3739                 if (entry->base == pool_offset) {
3740                         valid_entry = entry;
3741                         LIST_REMOVE(entry, next);
3742                         break;
3743                 }
3744         }
3745
3746         /* Not find, return */
3747         if (valid_entry == NULL) {
3748                 PMD_DRV_LOG(ERR, "Failed to find entry");
3749                 return -EINVAL;
3750         }
3751
3752         /**
3753          * Found it, move it to free list  and try to merge.
3754          * In order to make merge easier, always sort it by qbase.
3755          * Find adjacent prev and last entries.
3756          */
3757         prev = next = NULL;
3758         LIST_FOREACH(entry, &pool->free_list, next) {
3759                 if (entry->base > valid_entry->base) {
3760                         next = entry;
3761                         break;
3762                 }
3763                 prev = entry;
3764         }
3765
3766         insert = 0;
3767         /* Try to merge with next one*/
3768         if (next != NULL) {
3769                 /* Merge with next one */
3770                 if (valid_entry->base + valid_entry->len == next->base) {
3771                         next->base = valid_entry->base;
3772                         next->len += valid_entry->len;
3773                         rte_free(valid_entry);
3774                         valid_entry = next;
3775                         insert = 1;
3776                 }
3777         }
3778
3779         if (prev != NULL) {
3780                 /* Merge with previous one */
3781                 if (prev->base + prev->len == valid_entry->base) {
3782                         prev->len += valid_entry->len;
3783                         /* If it merge with next one, remove next node */
3784                         if (insert == 1) {
3785                                 LIST_REMOVE(valid_entry, next);
3786                                 rte_free(valid_entry);
3787                         } else {
3788                                 rte_free(valid_entry);
3789                                 insert = 1;
3790                         }
3791                 }
3792         }
3793
3794         /* Not find any entry to merge, insert */
3795         if (insert == 0) {
3796                 if (prev != NULL)
3797                         LIST_INSERT_AFTER(prev, valid_entry, next);
3798                 else if (next != NULL)
3799                         LIST_INSERT_BEFORE(next, valid_entry, next);
3800                 else /* It's empty list, insert to head */
3801                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3802         }
3803
3804         pool->num_free += valid_entry->len;
3805         pool->num_alloc -= valid_entry->len;
3806
3807         return 0;
3808 }
3809
3810 static int
3811 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3812                        uint16_t num)
3813 {
3814         struct pool_entry *entry, *valid_entry;
3815
3816         if (pool == NULL || num == 0) {
3817                 PMD_DRV_LOG(ERR, "Invalid parameter");
3818                 return -EINVAL;
3819         }
3820
3821         if (pool->num_free < num) {
3822                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3823                             num, pool->num_free);
3824                 return -ENOMEM;
3825         }
3826
3827         valid_entry = NULL;
3828         /* Lookup  in free list and find most fit one */
3829         LIST_FOREACH(entry, &pool->free_list, next) {
3830                 if (entry->len >= num) {
3831                         /* Find best one */
3832                         if (entry->len == num) {
3833                                 valid_entry = entry;
3834                                 break;
3835                         }
3836                         if (valid_entry == NULL || valid_entry->len > entry->len)
3837                                 valid_entry = entry;
3838                 }
3839         }
3840
3841         /* Not find one to satisfy the request, return */
3842         if (valid_entry == NULL) {
3843                 PMD_DRV_LOG(ERR, "No valid entry found");
3844                 return -ENOMEM;
3845         }
3846         /**
3847          * The entry have equal queue number as requested,
3848          * remove it from alloc_list.
3849          */
3850         if (valid_entry->len == num) {
3851                 LIST_REMOVE(valid_entry, next);
3852         } else {
3853                 /**
3854                  * The entry have more numbers than requested,
3855                  * create a new entry for alloc_list and minus its
3856                  * queue base and number in free_list.
3857                  */
3858                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3859                 if (entry == NULL) {
3860                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3861                                     "resource pool");
3862                         return -ENOMEM;
3863                 }
3864                 entry->base = valid_entry->base;
3865                 entry->len = num;
3866                 valid_entry->base += num;
3867                 valid_entry->len -= num;
3868                 valid_entry = entry;
3869         }
3870
3871         /* Insert it into alloc list, not sorted */
3872         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3873
3874         pool->num_free -= valid_entry->len;
3875         pool->num_alloc += valid_entry->len;
3876
3877         return valid_entry->base + pool->base;
3878 }
3879
3880 /**
3881  * bitmap_is_subset - Check whether src2 is subset of src1
3882  **/
3883 static inline int
3884 bitmap_is_subset(uint8_t src1, uint8_t src2)
3885 {
3886         return !((src1 ^ src2) & src2);
3887 }
3888
3889 static enum i40e_status_code
3890 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3891 {
3892         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3893
3894         /* If DCB is not supported, only default TC is supported */
3895         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3896                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3897                 return I40E_NOT_SUPPORTED;
3898         }
3899
3900         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3901                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3902                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3903                             enabled_tcmap);
3904                 return I40E_NOT_SUPPORTED;
3905         }
3906         return I40E_SUCCESS;
3907 }
3908
3909 int
3910 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3911                                 struct i40e_vsi_vlan_pvid_info *info)
3912 {
3913         struct i40e_hw *hw;
3914         struct i40e_vsi_context ctxt;
3915         uint8_t vlan_flags = 0;
3916         int ret;
3917
3918         if (vsi == NULL || info == NULL) {
3919                 PMD_DRV_LOG(ERR, "invalid parameters");
3920                 return I40E_ERR_PARAM;
3921         }
3922
3923         if (info->on) {
3924                 vsi->info.pvid = info->config.pvid;
3925                 /**
3926                  * If insert pvid is enabled, only tagged pkts are
3927                  * allowed to be sent out.
3928                  */
3929                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3930                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3931         } else {
3932                 vsi->info.pvid = 0;
3933                 if (info->config.reject.tagged == 0)
3934                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3935
3936                 if (info->config.reject.untagged == 0)
3937                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3938         }
3939         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3940                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3941         vsi->info.port_vlan_flags |= vlan_flags;
3942         vsi->info.valid_sections =
3943                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3944         memset(&ctxt, 0, sizeof(ctxt));
3945         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3946         ctxt.seid = vsi->seid;
3947
3948         hw = I40E_VSI_TO_HW(vsi);
3949         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3950         if (ret != I40E_SUCCESS)
3951                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3952
3953         return ret;
3954 }
3955
3956 static int
3957 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3958 {
3959         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3960         int i, ret;
3961         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3962
3963         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3964         if (ret != I40E_SUCCESS)
3965                 return ret;
3966
3967         if (!vsi->seid) {
3968                 PMD_DRV_LOG(ERR, "seid not valid");
3969                 return -EINVAL;
3970         }
3971
3972         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3973         tc_bw_data.tc_valid_bits = enabled_tcmap;
3974         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3975                 tc_bw_data.tc_bw_credits[i] =
3976                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3977
3978         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3979         if (ret != I40E_SUCCESS) {
3980                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3981                 return ret;
3982         }
3983
3984         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3985                                         sizeof(vsi->info.qs_handle));
3986         return I40E_SUCCESS;
3987 }
3988
3989 static enum i40e_status_code
3990 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3991                                  struct i40e_aqc_vsi_properties_data *info,
3992                                  uint8_t enabled_tcmap)
3993 {
3994         enum i40e_status_code ret;
3995         int i, total_tc = 0;
3996         uint16_t qpnum_per_tc, bsf, qp_idx;
3997
3998         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3999         if (ret != I40E_SUCCESS)
4000                 return ret;
4001
4002         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4003                 if (enabled_tcmap & (1 << i))
4004                         total_tc++;
4005         vsi->enabled_tc = enabled_tcmap;
4006
4007         /* Number of queues per enabled TC */
4008         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4009         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4010         bsf = rte_bsf32(qpnum_per_tc);
4011
4012         /* Adjust the queue number to actual queues that can be applied */
4013         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4014                 vsi->nb_qps = qpnum_per_tc * total_tc;
4015
4016         /**
4017          * Configure TC and queue mapping parameters, for enabled TC,
4018          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4019          * default queue will serve it.
4020          */
4021         qp_idx = 0;
4022         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4023                 if (vsi->enabled_tc & (1 << i)) {
4024                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4025                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4026                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4027                         qp_idx += qpnum_per_tc;
4028                 } else
4029                         info->tc_mapping[i] = 0;
4030         }
4031
4032         /* Associate queue number with VSI */
4033         if (vsi->type == I40E_VSI_SRIOV) {
4034                 info->mapping_flags |=
4035                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4036                 for (i = 0; i < vsi->nb_qps; i++)
4037                         info->queue_mapping[i] =
4038                                 rte_cpu_to_le_16(vsi->base_queue + i);
4039         } else {
4040                 info->mapping_flags |=
4041                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4042                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4043         }
4044         info->valid_sections |=
4045                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4046
4047         return I40E_SUCCESS;
4048 }
4049
4050 static int
4051 i40e_veb_release(struct i40e_veb *veb)
4052 {
4053         struct i40e_vsi *vsi;
4054         struct i40e_hw *hw;
4055
4056         if (veb == NULL)
4057                 return -EINVAL;
4058
4059         if (!TAILQ_EMPTY(&veb->head)) {
4060                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4061                 return -EACCES;
4062         }
4063         /* associate_vsi field is NULL for floating VEB */
4064         if (veb->associate_vsi != NULL) {
4065                 vsi = veb->associate_vsi;
4066                 hw = I40E_VSI_TO_HW(vsi);
4067
4068                 vsi->uplink_seid = veb->uplink_seid;
4069                 vsi->veb = NULL;
4070         } else {
4071                 veb->associate_pf->main_vsi->floating_veb = NULL;
4072                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4073         }
4074
4075         i40e_aq_delete_element(hw, veb->seid, NULL);
4076         rte_free(veb);
4077         return I40E_SUCCESS;
4078 }
4079
4080 /* Setup a veb */
4081 static struct i40e_veb *
4082 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4083 {
4084         struct i40e_veb *veb;
4085         int ret;
4086         struct i40e_hw *hw;
4087
4088         if (pf == NULL) {
4089                 PMD_DRV_LOG(ERR,
4090                             "veb setup failed, associated PF shouldn't null");
4091                 return NULL;
4092         }
4093         hw = I40E_PF_TO_HW(pf);
4094
4095         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4096         if (!veb) {
4097                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4098                 goto fail;
4099         }
4100
4101         veb->associate_vsi = vsi;
4102         veb->associate_pf = pf;
4103         TAILQ_INIT(&veb->head);
4104         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4105
4106         /* create floating veb if vsi is NULL */
4107         if (vsi != NULL) {
4108                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4109                                       I40E_DEFAULT_TCMAP, false,
4110                                       &veb->seid, false, NULL);
4111         } else {
4112                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4113                                       true, &veb->seid, false, NULL);
4114         }
4115
4116         if (ret != I40E_SUCCESS) {
4117                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4118                             hw->aq.asq_last_status);
4119                 goto fail;
4120         }
4121
4122         /* get statistics index */
4123         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4124                                 &veb->stats_idx, NULL, NULL, NULL);
4125         if (ret != I40E_SUCCESS) {
4126                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4127                             hw->aq.asq_last_status);
4128                 goto fail;
4129         }
4130         /* Get VEB bandwidth, to be implemented */
4131         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4132         if (vsi)
4133                 vsi->uplink_seid = veb->seid;
4134
4135         return veb;
4136 fail:
4137         rte_free(veb);
4138         return NULL;
4139 }
4140
4141 int
4142 i40e_vsi_release(struct i40e_vsi *vsi)
4143 {
4144         struct i40e_pf *pf;
4145         struct i40e_hw *hw;
4146         struct i40e_vsi_list *vsi_list;
4147         void *temp;
4148         int ret;
4149         struct i40e_mac_filter *f;
4150         uint16_t user_param;
4151
4152         if (!vsi)
4153                 return I40E_SUCCESS;
4154
4155         user_param = vsi->user_param;
4156
4157         pf = I40E_VSI_TO_PF(vsi);
4158         hw = I40E_VSI_TO_HW(vsi);
4159
4160         /* VSI has child to attach, release child first */
4161         if (vsi->veb) {
4162                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4163                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4164                                 return -1;
4165                 }
4166                 i40e_veb_release(vsi->veb);
4167         }
4168
4169         if (vsi->floating_veb) {
4170                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4171                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4172                                 return -1;
4173                 }
4174         }
4175
4176         /* Remove all macvlan filters of the VSI */
4177         i40e_vsi_remove_all_macvlan_filter(vsi);
4178         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4179                 rte_free(f);
4180
4181         if (vsi->type != I40E_VSI_MAIN &&
4182             ((vsi->type != I40E_VSI_SRIOV) ||
4183             !pf->floating_veb_list[user_param])) {
4184                 /* Remove vsi from parent's sibling list */
4185                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4186                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4187                         return I40E_ERR_PARAM;
4188                 }
4189                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4190                                 &vsi->sib_vsi_list, list);
4191
4192                 /* Remove all switch element of the VSI */
4193                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4194                 if (ret != I40E_SUCCESS)
4195                         PMD_DRV_LOG(ERR, "Failed to delete element");
4196         }
4197
4198         if ((vsi->type == I40E_VSI_SRIOV) &&
4199             pf->floating_veb_list[user_param]) {
4200                 /* Remove vsi from parent's sibling list */
4201                 if (vsi->parent_vsi == NULL ||
4202                     vsi->parent_vsi->floating_veb == NULL) {
4203                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4204                         return I40E_ERR_PARAM;
4205                 }
4206                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4207                              &vsi->sib_vsi_list, list);
4208
4209                 /* Remove all switch element of the VSI */
4210                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4211                 if (ret != I40E_SUCCESS)
4212                         PMD_DRV_LOG(ERR, "Failed to delete element");
4213         }
4214
4215         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4216
4217         if (vsi->type != I40E_VSI_SRIOV)
4218                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4219         rte_free(vsi);
4220
4221         return I40E_SUCCESS;
4222 }
4223
4224 static int
4225 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4226 {
4227         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4228         struct i40e_aqc_remove_macvlan_element_data def_filter;
4229         struct i40e_mac_filter_info filter;
4230         int ret;
4231
4232         if (vsi->type != I40E_VSI_MAIN)
4233                 return I40E_ERR_CONFIG;
4234         memset(&def_filter, 0, sizeof(def_filter));
4235         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4236                                         ETH_ADDR_LEN);
4237         def_filter.vlan_tag = 0;
4238         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4239                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4240         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4241         if (ret != I40E_SUCCESS) {
4242                 struct i40e_mac_filter *f;
4243                 struct ether_addr *mac;
4244
4245                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4246                             "macvlan filter");
4247                 /* It needs to add the permanent mac into mac list */
4248                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4249                 if (f == NULL) {
4250                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4251                         return I40E_ERR_NO_MEMORY;
4252                 }
4253                 mac = &f->mac_info.mac_addr;
4254                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4255                                 ETH_ADDR_LEN);
4256                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4257                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4258                 vsi->mac_num++;
4259
4260                 return ret;
4261         }
4262         (void)rte_memcpy(&filter.mac_addr,
4263                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4264         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4265         return i40e_vsi_add_mac(vsi, &filter);
4266 }
4267
4268 /*
4269  * i40e_vsi_get_bw_config - Query VSI BW Information
4270  * @vsi: the VSI to be queried
4271  *
4272  * Returns 0 on success, negative value on failure
4273  */
4274 static enum i40e_status_code
4275 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4276 {
4277         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4278         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4279         struct i40e_hw *hw = &vsi->adapter->hw;
4280         i40e_status ret;
4281         int i;
4282         uint32_t bw_max;
4283
4284         memset(&bw_config, 0, sizeof(bw_config));
4285         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4286         if (ret != I40E_SUCCESS) {
4287                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4288                             hw->aq.asq_last_status);
4289                 return ret;
4290         }
4291
4292         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4293         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4294                                         &ets_sla_config, NULL);
4295         if (ret != I40E_SUCCESS) {
4296                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4297                             "configuration %u", hw->aq.asq_last_status);
4298                 return ret;
4299         }
4300
4301         /* store and print out BW info */
4302         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4303         vsi->bw_info.bw_max = bw_config.max_bw;
4304         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4305         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4306         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4307                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4308                      I40E_16_BIT_WIDTH);
4309         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4310                 vsi->bw_info.bw_ets_share_credits[i] =
4311                                 ets_sla_config.share_credits[i];
4312                 vsi->bw_info.bw_ets_credits[i] =
4313                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4314                 /* 4 bits per TC, 4th bit is reserved */
4315                 vsi->bw_info.bw_ets_max[i] =
4316                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4317                                   RTE_LEN2MASK(3, uint8_t));
4318                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4319                             vsi->bw_info.bw_ets_share_credits[i]);
4320                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4321                             vsi->bw_info.bw_ets_credits[i]);
4322                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4323                             vsi->bw_info.bw_ets_max[i]);
4324         }
4325
4326         return I40E_SUCCESS;
4327 }
4328
4329 /* i40e_enable_pf_lb
4330  * @pf: pointer to the pf structure
4331  *
4332  * allow loopback on pf
4333  */
4334 static inline void
4335 i40e_enable_pf_lb(struct i40e_pf *pf)
4336 {
4337         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4338         struct i40e_vsi_context ctxt;
4339         int ret;
4340
4341         /* Use the FW API if FW >= v5.0 */
4342         if (hw->aq.fw_maj_ver < 5) {
4343                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4344                 return;
4345         }
4346
4347         memset(&ctxt, 0, sizeof(ctxt));
4348         ctxt.seid = pf->main_vsi_seid;
4349         ctxt.pf_num = hw->pf_id;
4350         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4351         if (ret) {
4352                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4353                             ret, hw->aq.asq_last_status);
4354                 return;
4355         }
4356         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4357         ctxt.info.valid_sections =
4358                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4359         ctxt.info.switch_id |=
4360                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4361
4362         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4363         if (ret)
4364                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4365                             hw->aq.asq_last_status);
4366 }
4367
4368 /* Setup a VSI */
4369 struct i40e_vsi *
4370 i40e_vsi_setup(struct i40e_pf *pf,
4371                enum i40e_vsi_type type,
4372                struct i40e_vsi *uplink_vsi,
4373                uint16_t user_param)
4374 {
4375         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4376         struct i40e_vsi *vsi;
4377         struct i40e_mac_filter_info filter;
4378         int ret;
4379         struct i40e_vsi_context ctxt;
4380         struct ether_addr broadcast =
4381                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4382
4383         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4384             uplink_vsi == NULL) {
4385                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4386                             "VSI link shouldn't be NULL");
4387                 return NULL;
4388         }
4389
4390         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4391                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4392                             "uplink VSI should be NULL");
4393                 return NULL;
4394         }
4395
4396         /* two situations
4397          * 1.type is not MAIN and uplink vsi is not NULL
4398          * If uplink vsi didn't setup VEB, create one first under veb field
4399          * 2.type is SRIOV and the uplink is NULL
4400          * If floating VEB is NULL, create one veb under floating veb field
4401          */
4402
4403         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4404             uplink_vsi->veb == NULL) {
4405                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4406
4407                 if (uplink_vsi->veb == NULL) {
4408                         PMD_DRV_LOG(ERR, "VEB setup failed");
4409                         return NULL;
4410                 }
4411                 /* set ALLOWLOOPBACk on pf, when veb is created */
4412                 i40e_enable_pf_lb(pf);
4413         }
4414
4415         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4416             pf->main_vsi->floating_veb == NULL) {
4417                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4418
4419                 if (pf->main_vsi->floating_veb == NULL) {
4420                         PMD_DRV_LOG(ERR, "VEB setup failed");
4421                         return NULL;
4422                 }
4423         }
4424
4425         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4426         if (!vsi) {
4427                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4428                 return NULL;
4429         }
4430         TAILQ_INIT(&vsi->mac_list);
4431         vsi->type = type;
4432         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4433         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4434         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4435         vsi->user_param = user_param;
4436         /* Allocate queues */
4437         switch (vsi->type) {
4438         case I40E_VSI_MAIN  :
4439                 vsi->nb_qps = pf->lan_nb_qps;
4440                 break;
4441         case I40E_VSI_SRIOV :
4442                 vsi->nb_qps = pf->vf_nb_qps;
4443                 break;
4444         case I40E_VSI_VMDQ2:
4445                 vsi->nb_qps = pf->vmdq_nb_qps;
4446                 break;
4447         case I40E_VSI_FDIR:
4448                 vsi->nb_qps = pf->fdir_nb_qps;
4449                 break;
4450         default:
4451                 goto fail_mem;
4452         }
4453         /*
4454          * The filter status descriptor is reported in rx queue 0,
4455          * while the tx queue for fdir filter programming has no
4456          * such constraints, can be non-zero queues.
4457          * To simplify it, choose FDIR vsi use queue 0 pair.
4458          * To make sure it will use queue 0 pair, queue allocation
4459          * need be done before this function is called
4460          */
4461         if (type != I40E_VSI_FDIR) {
4462                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4463                         if (ret < 0) {
4464                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4465                                                 vsi->seid, ret);
4466                                 goto fail_mem;
4467                         }
4468                         vsi->base_queue = ret;
4469         } else
4470                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4471
4472         /* VF has MSIX interrupt in VF range, don't allocate here */
4473         if (type == I40E_VSI_MAIN) {
4474                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4475                                           RTE_MIN(vsi->nb_qps,
4476                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4477                 if (ret < 0) {
4478                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4479                                     vsi->seid, ret);
4480                         goto fail_queue_alloc;
4481                 }
4482                 vsi->msix_intr = ret;
4483                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4484         } else if (type != I40E_VSI_SRIOV) {
4485                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4486                 if (ret < 0) {
4487                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4488                         goto fail_queue_alloc;
4489                 }
4490                 vsi->msix_intr = ret;
4491                 vsi->nb_msix = 1;
4492         } else {
4493                 vsi->msix_intr = 0;
4494                 vsi->nb_msix = 0;
4495         }
4496
4497         /* Add VSI */
4498         if (type == I40E_VSI_MAIN) {
4499                 /* For main VSI, no need to add since it's default one */
4500                 vsi->uplink_seid = pf->mac_seid;
4501                 vsi->seid = pf->main_vsi_seid;
4502                 /* Bind queues with specific MSIX interrupt */
4503                 /**
4504                  * Needs 2 interrupt at least, one for misc cause which will
4505                  * enabled from OS side, Another for queues binding the
4506                  * interrupt from device side only.
4507                  */
4508
4509                 /* Get default VSI parameters from hardware */
4510                 memset(&ctxt, 0, sizeof(ctxt));
4511                 ctxt.seid = vsi->seid;
4512                 ctxt.pf_num = hw->pf_id;
4513                 ctxt.uplink_seid = vsi->uplink_seid;
4514                 ctxt.vf_num = 0;
4515                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4516                 if (ret != I40E_SUCCESS) {
4517                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4518                         goto fail_msix_alloc;
4519                 }
4520                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4521                         sizeof(struct i40e_aqc_vsi_properties_data));
4522                 vsi->vsi_id = ctxt.vsi_number;
4523                 vsi->info.valid_sections = 0;
4524
4525                 /* Configure tc, enabled TC0 only */
4526                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4527                         I40E_SUCCESS) {
4528                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4529                         goto fail_msix_alloc;
4530                 }
4531
4532                 /* TC, queue mapping */
4533                 memset(&ctxt, 0, sizeof(ctxt));
4534                 vsi->info.valid_sections |=
4535                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4536                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4537                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4538                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4539                         sizeof(struct i40e_aqc_vsi_properties_data));
4540                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4541                                                 I40E_DEFAULT_TCMAP);
4542                 if (ret != I40E_SUCCESS) {
4543                         PMD_DRV_LOG(ERR, "Failed to configure "
4544                                     "TC queue mapping");
4545                         goto fail_msix_alloc;
4546                 }
4547                 ctxt.seid = vsi->seid;
4548                 ctxt.pf_num = hw->pf_id;
4549                 ctxt.uplink_seid = vsi->uplink_seid;
4550                 ctxt.vf_num = 0;
4551
4552                 /* Update VSI parameters */
4553                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4554                 if (ret != I40E_SUCCESS) {
4555                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4556                         goto fail_msix_alloc;
4557                 }
4558
4559                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4560                                                 sizeof(vsi->info.tc_mapping));
4561                 (void)rte_memcpy(&vsi->info.queue_mapping,
4562                                 &ctxt.info.queue_mapping,
4563                         sizeof(vsi->info.queue_mapping));
4564                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4565                 vsi->info.valid_sections = 0;
4566
4567                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4568                                 ETH_ADDR_LEN);
4569
4570                 /**
4571                  * Updating default filter settings are necessary to prevent
4572                  * reception of tagged packets.
4573                  * Some old firmware configurations load a default macvlan
4574                  * filter which accepts both tagged and untagged packets.
4575                  * The updating is to use a normal filter instead if needed.
4576                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4577                  * The firmware with correct configurations load the default
4578                  * macvlan filter which is expected and cannot be removed.
4579                  */
4580                 i40e_update_default_filter_setting(vsi);
4581                 i40e_config_qinq(hw, vsi);
4582         } else if (type == I40E_VSI_SRIOV) {
4583                 memset(&ctxt, 0, sizeof(ctxt));
4584                 /**
4585                  * For other VSI, the uplink_seid equals to uplink VSI's
4586                  * uplink_seid since they share same VEB
4587                  */
4588                 if (uplink_vsi == NULL)
4589                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4590                 else
4591                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4592                 ctxt.pf_num = hw->pf_id;
4593                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4594                 ctxt.uplink_seid = vsi->uplink_seid;
4595                 ctxt.connection_type = 0x1;
4596                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4597
4598                 /* Use the VEB configuration if FW >= v5.0 */
4599                 if (hw->aq.fw_maj_ver >= 5) {
4600                         /* Configure switch ID */
4601                         ctxt.info.valid_sections |=
4602                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4603                         ctxt.info.switch_id =
4604                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4605                 }
4606
4607                 /* Configure port/vlan */
4608                 ctxt.info.valid_sections |=
4609                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4610                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4611                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4612                                                 I40E_DEFAULT_TCMAP);
4613                 if (ret != I40E_SUCCESS) {
4614                         PMD_DRV_LOG(ERR, "Failed to configure "
4615                                     "TC queue mapping");
4616                         goto fail_msix_alloc;
4617                 }
4618                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4619                 ctxt.info.valid_sections |=
4620                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4621                 /**
4622                  * Since VSI is not created yet, only configure parameter,
4623                  * will add vsi below.
4624                  */
4625
4626                 i40e_config_qinq(hw, vsi);
4627         } else if (type == I40E_VSI_VMDQ2) {
4628                 memset(&ctxt, 0, sizeof(ctxt));
4629                 /*
4630                  * For other VSI, the uplink_seid equals to uplink VSI's
4631                  * uplink_seid since they share same VEB
4632                  */
4633                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4634                 ctxt.pf_num = hw->pf_id;
4635                 ctxt.vf_num = 0;
4636                 ctxt.uplink_seid = vsi->uplink_seid;
4637                 ctxt.connection_type = 0x1;
4638                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4639
4640                 ctxt.info.valid_sections |=
4641                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4642                 /* user_param carries flag to enable loop back */
4643                 if (user_param) {
4644                         ctxt.info.switch_id =
4645                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4646                         ctxt.info.switch_id |=
4647                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4648                 }
4649
4650                 /* Configure port/vlan */
4651                 ctxt.info.valid_sections |=
4652                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4653                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4654                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4655                                                 I40E_DEFAULT_TCMAP);
4656                 if (ret != I40E_SUCCESS) {
4657                         PMD_DRV_LOG(ERR, "Failed to configure "
4658                                         "TC queue mapping");
4659                         goto fail_msix_alloc;
4660                 }
4661                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4662                 ctxt.info.valid_sections |=
4663                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4664         } else if (type == I40E_VSI_FDIR) {
4665                 memset(&ctxt, 0, sizeof(ctxt));
4666                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4667                 ctxt.pf_num = hw->pf_id;
4668                 ctxt.vf_num = 0;
4669                 ctxt.uplink_seid = vsi->uplink_seid;
4670                 ctxt.connection_type = 0x1;     /* regular data port */
4671                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4672                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4673                                                 I40E_DEFAULT_TCMAP);
4674                 if (ret != I40E_SUCCESS) {
4675                         PMD_DRV_LOG(ERR, "Failed to configure "
4676                                         "TC queue mapping.");
4677                         goto fail_msix_alloc;
4678                 }
4679                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4680                 ctxt.info.valid_sections |=
4681                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4682         } else {
4683                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4684                 goto fail_msix_alloc;
4685         }
4686
4687         if (vsi->type != I40E_VSI_MAIN) {
4688                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4689                 if (ret != I40E_SUCCESS) {
4690                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4691                                     hw->aq.asq_last_status);
4692                         goto fail_msix_alloc;
4693                 }
4694                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4695                 vsi->info.valid_sections = 0;
4696                 vsi->seid = ctxt.seid;
4697                 vsi->vsi_id = ctxt.vsi_number;
4698                 vsi->sib_vsi_list.vsi = vsi;
4699                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4700                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4701                                           &vsi->sib_vsi_list, list);
4702                 } else {
4703                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4704                                           &vsi->sib_vsi_list, list);
4705                 }
4706         }
4707
4708         /* MAC/VLAN configuration */
4709         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4710         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4711
4712         ret = i40e_vsi_add_mac(vsi, &filter);
4713         if (ret != I40E_SUCCESS) {
4714                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4715                 goto fail_msix_alloc;
4716         }
4717
4718         /* Get VSI BW information */
4719         i40e_vsi_get_bw_config(vsi);
4720         return vsi;
4721 fail_msix_alloc:
4722         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4723 fail_queue_alloc:
4724         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4725 fail_mem:
4726         rte_free(vsi);
4727         return NULL;
4728 }
4729
4730 /* Configure vlan filter on or off */
4731 int
4732 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4733 {
4734         int i, num;
4735         struct i40e_mac_filter *f;
4736         void *temp;
4737         struct i40e_mac_filter_info *mac_filter;
4738         enum rte_mac_filter_type desired_filter;
4739         int ret = I40E_SUCCESS;
4740
4741         if (on) {
4742                 /* Filter to match MAC and VLAN */
4743                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4744         } else {
4745                 /* Filter to match only MAC */
4746                 desired_filter = RTE_MAC_PERFECT_MATCH;
4747         }
4748
4749         num = vsi->mac_num;
4750
4751         mac_filter = rte_zmalloc("mac_filter_info_data",
4752                                  num * sizeof(*mac_filter), 0);
4753         if (mac_filter == NULL) {
4754                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4755                 return I40E_ERR_NO_MEMORY;
4756         }
4757
4758         i = 0;
4759
4760         /* Remove all existing mac */
4761         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4762                 mac_filter[i] = f->mac_info;
4763                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4764                 if (ret) {
4765                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4766                                     on ? "enable" : "disable");
4767                         goto DONE;
4768                 }
4769                 i++;
4770         }
4771
4772         /* Override with new filter */
4773         for (i = 0; i < num; i++) {
4774                 mac_filter[i].filter_type = desired_filter;
4775                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4776                 if (ret) {
4777                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4778                                     on ? "enable" : "disable");
4779                         goto DONE;
4780                 }
4781         }
4782
4783 DONE:
4784         rte_free(mac_filter);
4785         return ret;
4786 }
4787
4788 /* Configure vlan stripping on or off */
4789 int
4790 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4791 {
4792         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4793         struct i40e_vsi_context ctxt;
4794         uint8_t vlan_flags;
4795         int ret = I40E_SUCCESS;
4796
4797         /* Check if it has been already on or off */
4798         if (vsi->info.valid_sections &
4799                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4800                 if (on) {
4801                         if ((vsi->info.port_vlan_flags &
4802                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4803                                 return 0; /* already on */
4804                 } else {
4805                         if ((vsi->info.port_vlan_flags &
4806                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4807                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4808                                 return 0; /* already off */
4809                 }
4810         }
4811
4812         if (on)
4813                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4814         else
4815                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4816         vsi->info.valid_sections =
4817                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4818         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4819         vsi->info.port_vlan_flags |= vlan_flags;
4820         ctxt.seid = vsi->seid;
4821         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4822         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4823         if (ret)
4824                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4825                             on ? "enable" : "disable");
4826
4827         return ret;
4828 }
4829
4830 static int
4831 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4832 {
4833         struct rte_eth_dev_data *data = dev->data;
4834         int ret;
4835         int mask = 0;
4836
4837         /* Apply vlan offload setting */
4838         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4839         i40e_vlan_offload_set(dev, mask);
4840
4841         /* Apply double-vlan setting, not implemented yet */
4842
4843         /* Apply pvid setting */
4844         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4845                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4846         if (ret)
4847                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4848
4849         return ret;
4850 }
4851
4852 static int
4853 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4854 {
4855         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4856
4857         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4858 }
4859
4860 static int
4861 i40e_update_flow_control(struct i40e_hw *hw)
4862 {
4863 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4864         struct i40e_link_status link_status;
4865         uint32_t rxfc = 0, txfc = 0, reg;
4866         uint8_t an_info;
4867         int ret;
4868
4869         memset(&link_status, 0, sizeof(link_status));
4870         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4871         if (ret != I40E_SUCCESS) {
4872                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4873                 goto write_reg; /* Disable flow control */
4874         }
4875
4876         an_info = hw->phy.link_info.an_info;
4877         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4878                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4879                 ret = I40E_ERR_NOT_READY;
4880                 goto write_reg; /* Disable flow control */
4881         }
4882         /**
4883          * If link auto negotiation is enabled, flow control needs to
4884          * be configured according to it
4885          */
4886         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4887         case I40E_LINK_PAUSE_RXTX:
4888                 rxfc = 1;
4889                 txfc = 1;
4890                 hw->fc.current_mode = I40E_FC_FULL;
4891                 break;
4892         case I40E_AQ_LINK_PAUSE_RX:
4893                 rxfc = 1;
4894                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4895                 break;
4896         case I40E_AQ_LINK_PAUSE_TX:
4897                 txfc = 1;
4898                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4899                 break;
4900         default:
4901                 hw->fc.current_mode = I40E_FC_NONE;
4902                 break;
4903         }
4904
4905 write_reg:
4906         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4907                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4908         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4909         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4910         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4911         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4912
4913         return ret;
4914 }
4915
4916 /* PF setup */
4917 static int
4918 i40e_pf_setup(struct i40e_pf *pf)
4919 {
4920         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4921         struct i40e_filter_control_settings settings;
4922         struct i40e_vsi *vsi;
4923         int ret;
4924
4925         /* Clear all stats counters */
4926         pf->offset_loaded = FALSE;
4927         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4928         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4929
4930         ret = i40e_pf_get_switch_config(pf);
4931         if (ret != I40E_SUCCESS) {
4932                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4933                 return ret;
4934         }
4935         if (pf->flags & I40E_FLAG_FDIR) {
4936                 /* make queue allocated first, let FDIR use queue pair 0*/
4937                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4938                 if (ret != I40E_FDIR_QUEUE_ID) {
4939                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4940                                     " ret =%d", ret);
4941                         pf->flags &= ~I40E_FLAG_FDIR;
4942                 }
4943         }
4944         /*  main VSI setup */
4945         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4946         if (!vsi) {
4947                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4948                 return I40E_ERR_NOT_READY;
4949         }
4950         pf->main_vsi = vsi;
4951
4952         /* Configure filter control */
4953         memset(&settings, 0, sizeof(settings));
4954         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4955                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4956         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4957                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4958         else {
4959                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4960                                                 hw->func_caps.rss_table_size);
4961                 return I40E_ERR_PARAM;
4962         }
4963         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4964                         "size: %u\n", hw->func_caps.rss_table_size);
4965         pf->hash_lut_size = hw->func_caps.rss_table_size;
4966
4967         /* Enable ethtype and macvlan filters */
4968         settings.enable_ethtype = TRUE;
4969         settings.enable_macvlan = TRUE;
4970         ret = i40e_set_filter_control(hw, &settings);
4971         if (ret)
4972                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4973                                                                 ret);
4974
4975         /* Update flow control according to the auto negotiation */
4976         i40e_update_flow_control(hw);
4977
4978         return I40E_SUCCESS;
4979 }
4980
4981 int
4982 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4983 {
4984         uint32_t reg;
4985         uint16_t j;
4986
4987         /**
4988          * Set or clear TX Queue Disable flags,
4989          * which is required by hardware.
4990          */
4991         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4992         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4993
4994         /* Wait until the request is finished */
4995         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4996                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4997                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4998                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4999                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5000                                                         & 0x1))) {
5001                         break;
5002                 }
5003         }
5004         if (on) {
5005                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5006                         return I40E_SUCCESS; /* already on, skip next steps */
5007
5008                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5009                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5010         } else {
5011                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5012                         return I40E_SUCCESS; /* already off, skip next steps */
5013                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5014         }
5015         /* Write the register */
5016         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5017         /* Check the result */
5018         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5019                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5020                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5021                 if (on) {
5022                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5023                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5024                                 break;
5025                 } else {
5026                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5027                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5028                                 break;
5029                 }
5030         }
5031         /* Check if it is timeout */
5032         if (j >= I40E_CHK_Q_ENA_COUNT) {
5033                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5034                             (on ? "enable" : "disable"), q_idx);
5035                 return I40E_ERR_TIMEOUT;
5036         }
5037
5038         return I40E_SUCCESS;
5039 }
5040
5041 /* Swith on or off the tx queues */
5042 static int
5043 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5044 {
5045         struct rte_eth_dev_data *dev_data = pf->dev_data;
5046         struct i40e_tx_queue *txq;
5047         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5048         uint16_t i;
5049         int ret;
5050
5051         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5052                 txq = dev_data->tx_queues[i];
5053                 /* Don't operate the queue if not configured or
5054                  * if starting only per queue */
5055                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5056                         continue;
5057                 if (on)
5058                         ret = i40e_dev_tx_queue_start(dev, i);
5059                 else
5060                         ret = i40e_dev_tx_queue_stop(dev, i);
5061                 if ( ret != I40E_SUCCESS)
5062                         return ret;
5063         }
5064
5065         return I40E_SUCCESS;
5066 }
5067
5068 int
5069 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5070 {
5071         uint32_t reg;
5072         uint16_t j;
5073
5074         /* Wait until the request is finished */
5075         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5076                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5077                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5078                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5079                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5080                         break;
5081         }
5082
5083         if (on) {
5084                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5085                         return I40E_SUCCESS; /* Already on, skip next steps */
5086                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5087         } else {
5088                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5089                         return I40E_SUCCESS; /* Already off, skip next steps */
5090                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5091         }
5092
5093         /* Write the register */
5094         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5095         /* Check the result */
5096         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5097                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5098                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5099                 if (on) {
5100                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5101                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5102                                 break;
5103                 } else {
5104                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5105                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5106                                 break;
5107                 }
5108         }
5109
5110         /* Check if it is timeout */
5111         if (j >= I40E_CHK_Q_ENA_COUNT) {
5112                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5113                             (on ? "enable" : "disable"), q_idx);
5114                 return I40E_ERR_TIMEOUT;
5115         }
5116
5117         return I40E_SUCCESS;
5118 }
5119 /* Switch on or off the rx queues */
5120 static int
5121 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5122 {
5123         struct rte_eth_dev_data *dev_data = pf->dev_data;
5124         struct i40e_rx_queue *rxq;
5125         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5126         uint16_t i;
5127         int ret;
5128
5129         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5130                 rxq = dev_data->rx_queues[i];
5131                 /* Don't operate the queue if not configured or
5132                  * if starting only per queue */
5133                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5134                         continue;
5135                 if (on)
5136                         ret = i40e_dev_rx_queue_start(dev, i);
5137                 else
5138                         ret = i40e_dev_rx_queue_stop(dev, i);
5139                 if (ret != I40E_SUCCESS)
5140                         return ret;
5141         }
5142
5143         return I40E_SUCCESS;
5144 }
5145
5146 /* Switch on or off all the rx/tx queues */
5147 int
5148 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5149 {
5150         int ret;
5151
5152         if (on) {
5153                 /* enable rx queues before enabling tx queues */
5154                 ret = i40e_dev_switch_rx_queues(pf, on);
5155                 if (ret) {
5156                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5157                         return ret;
5158                 }
5159                 ret = i40e_dev_switch_tx_queues(pf, on);
5160         } else {
5161                 /* Stop tx queues before stopping rx queues */
5162                 ret = i40e_dev_switch_tx_queues(pf, on);
5163                 if (ret) {
5164                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5165                         return ret;
5166                 }
5167                 ret = i40e_dev_switch_rx_queues(pf, on);
5168         }
5169
5170         return ret;
5171 }
5172
5173 /* Initialize VSI for TX */
5174 static int
5175 i40e_dev_tx_init(struct i40e_pf *pf)
5176 {
5177         struct rte_eth_dev_data *data = pf->dev_data;
5178         uint16_t i;
5179         uint32_t ret = I40E_SUCCESS;
5180         struct i40e_tx_queue *txq;
5181
5182         for (i = 0; i < data->nb_tx_queues; i++) {
5183                 txq = data->tx_queues[i];
5184                 if (!txq || !txq->q_set)
5185                         continue;
5186                 ret = i40e_tx_queue_init(txq);
5187                 if (ret != I40E_SUCCESS)
5188                         break;
5189         }
5190         if (ret == I40E_SUCCESS)
5191                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5192                                      ->eth_dev);
5193
5194         return ret;
5195 }
5196
5197 /* Initialize VSI for RX */
5198 static int
5199 i40e_dev_rx_init(struct i40e_pf *pf)
5200 {
5201         struct rte_eth_dev_data *data = pf->dev_data;
5202         int ret = I40E_SUCCESS;
5203         uint16_t i;
5204         struct i40e_rx_queue *rxq;
5205
5206         i40e_pf_config_mq_rx(pf);
5207         for (i = 0; i < data->nb_rx_queues; i++) {
5208                 rxq = data->rx_queues[i];
5209                 if (!rxq || !rxq->q_set)
5210                         continue;
5211
5212                 ret = i40e_rx_queue_init(rxq);
5213                 if (ret != I40E_SUCCESS) {
5214                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5215                                     "initialization");
5216                         break;
5217                 }
5218         }
5219         if (ret == I40E_SUCCESS)
5220                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5221                                      ->eth_dev);
5222
5223         return ret;
5224 }
5225
5226 static int
5227 i40e_dev_rxtx_init(struct i40e_pf *pf)
5228 {
5229         int err;
5230
5231         err = i40e_dev_tx_init(pf);
5232         if (err) {
5233                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5234                 return err;
5235         }
5236         err = i40e_dev_rx_init(pf);
5237         if (err) {
5238                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5239                 return err;
5240         }
5241
5242         return err;
5243 }
5244
5245 static int
5246 i40e_vmdq_setup(struct rte_eth_dev *dev)
5247 {
5248         struct rte_eth_conf *conf = &dev->data->dev_conf;
5249         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5250         int i, err, conf_vsis, j, loop;
5251         struct i40e_vsi *vsi;
5252         struct i40e_vmdq_info *vmdq_info;
5253         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5254         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5255
5256         /*
5257          * Disable interrupt to avoid message from VF. Furthermore, it will
5258          * avoid race condition in VSI creation/destroy.
5259          */
5260         i40e_pf_disable_irq0(hw);
5261
5262         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5263                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5264                 return -ENOTSUP;
5265         }
5266
5267         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5268         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5269                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5270                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5271                         pf->max_nb_vmdq_vsi);
5272                 return -ENOTSUP;
5273         }
5274
5275         if (pf->vmdq != NULL) {
5276                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5277                 return 0;
5278         }
5279
5280         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5281                                 sizeof(*vmdq_info) * conf_vsis, 0);
5282
5283         if (pf->vmdq == NULL) {
5284                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5285                 return -ENOMEM;
5286         }
5287
5288         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5289
5290         /* Create VMDQ VSI */
5291         for (i = 0; i < conf_vsis; i++) {
5292                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5293                                 vmdq_conf->enable_loop_back);
5294                 if (vsi == NULL) {
5295                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5296                         err = -1;
5297                         goto err_vsi_setup;
5298                 }
5299                 vmdq_info = &pf->vmdq[i];
5300                 vmdq_info->pf = pf;
5301                 vmdq_info->vsi = vsi;
5302         }
5303         pf->nb_cfg_vmdq_vsi = conf_vsis;
5304
5305         /* Configure Vlan */
5306         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5307         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5308                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5309                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5310                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5311                                         vmdq_conf->pool_map[i].vlan_id, j);
5312
5313                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5314                                                 vmdq_conf->pool_map[i].vlan_id);
5315                                 if (err) {
5316                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5317                                         err = -1;
5318                                         goto err_vsi_setup;
5319                                 }
5320                         }
5321                 }
5322         }
5323
5324         i40e_pf_enable_irq0(hw);
5325
5326         return 0;
5327
5328 err_vsi_setup:
5329         for (i = 0; i < conf_vsis; i++)
5330                 if (pf->vmdq[i].vsi == NULL)
5331                         break;
5332                 else
5333                         i40e_vsi_release(pf->vmdq[i].vsi);
5334
5335         rte_free(pf->vmdq);
5336         pf->vmdq = NULL;
5337         i40e_pf_enable_irq0(hw);
5338         return err;
5339 }
5340
5341 static void
5342 i40e_stat_update_32(struct i40e_hw *hw,
5343                    uint32_t reg,
5344                    bool offset_loaded,
5345                    uint64_t *offset,
5346                    uint64_t *stat)
5347 {
5348         uint64_t new_data;
5349
5350         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5351         if (!offset_loaded)
5352                 *offset = new_data;
5353
5354         if (new_data >= *offset)
5355                 *stat = (uint64_t)(new_data - *offset);
5356         else
5357                 *stat = (uint64_t)((new_data +
5358                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5359 }
5360
5361 static void
5362 i40e_stat_update_48(struct i40e_hw *hw,
5363                    uint32_t hireg,
5364                    uint32_t loreg,
5365                    bool offset_loaded,
5366                    uint64_t *offset,
5367                    uint64_t *stat)
5368 {
5369         uint64_t new_data;
5370
5371         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5372         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5373                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5374
5375         if (!offset_loaded)
5376                 *offset = new_data;
5377
5378         if (new_data >= *offset)
5379                 *stat = new_data - *offset;
5380         else
5381                 *stat = (uint64_t)((new_data +
5382                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5383
5384         *stat &= I40E_48_BIT_MASK;
5385 }
5386
5387 /* Disable IRQ0 */
5388 void
5389 i40e_pf_disable_irq0(struct i40e_hw *hw)
5390 {
5391         /* Disable all interrupt types */
5392         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5393         I40E_WRITE_FLUSH(hw);
5394 }
5395
5396 /* Enable IRQ0 */
5397 void
5398 i40e_pf_enable_irq0(struct i40e_hw *hw)
5399 {
5400         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5401                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5402                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5403                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5404         I40E_WRITE_FLUSH(hw);
5405 }
5406
5407 static void
5408 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5409 {
5410         /* read pending request and disable first */
5411         i40e_pf_disable_irq0(hw);
5412         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5413         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5414                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5415
5416         if (no_queue)
5417                 /* Link no queues with irq0 */
5418                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5419                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5420 }
5421
5422 static void
5423 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5424 {
5425         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5426         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5427         int i;
5428         uint16_t abs_vf_id;
5429         uint32_t index, offset, val;
5430
5431         if (!pf->vfs)
5432                 return;
5433         /**
5434          * Try to find which VF trigger a reset, use absolute VF id to access
5435          * since the reg is global register.
5436          */
5437         for (i = 0; i < pf->vf_num; i++) {
5438                 abs_vf_id = hw->func_caps.vf_base_id + i;
5439                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5440                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5441                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5442                 /* VFR event occured */
5443                 if (val & (0x1 << offset)) {
5444                         int ret;
5445
5446                         /* Clear the event first */
5447                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5448                                                         (0x1 << offset));
5449                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5450                         /**
5451                          * Only notify a VF reset event occured,
5452                          * don't trigger another SW reset
5453                          */
5454                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5455                         if (ret != I40E_SUCCESS)
5456                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5457                 }
5458         }
5459 }
5460
5461 static void
5462 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5463 {
5464         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5465         struct i40e_virtchnl_pf_event event;
5466         int i;
5467
5468         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5469         event.event_data.link_event.link_status =
5470                 dev->data->dev_link.link_status;
5471         event.event_data.link_event.link_speed =
5472                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5473
5474         for (i = 0; i < pf->vf_num; i++)
5475                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5476                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5477 }
5478
5479 static void
5480 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5481 {
5482         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5483         struct i40e_arq_event_info info;
5484         uint16_t pending, opcode;
5485         int ret;
5486
5487         info.buf_len = I40E_AQ_BUF_SZ;
5488         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5489         if (!info.msg_buf) {
5490                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5491                 return;
5492         }
5493
5494         pending = 1;
5495         while (pending) {
5496                 ret = i40e_clean_arq_element(hw, &info, &pending);
5497
5498                 if (ret != I40E_SUCCESS) {
5499                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5500                                     "aq_err: %u", hw->aq.asq_last_status);
5501                         break;
5502                 }
5503                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5504
5505                 switch (opcode) {
5506                 case i40e_aqc_opc_send_msg_to_pf:
5507                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5508                         i40e_pf_host_handle_vf_msg(dev,
5509                                         rte_le_to_cpu_16(info.desc.retval),
5510                                         rte_le_to_cpu_32(info.desc.cookie_high),
5511                                         rte_le_to_cpu_32(info.desc.cookie_low),
5512                                         info.msg_buf,
5513                                         info.msg_len);
5514                         break;
5515                 case i40e_aqc_opc_get_link_status:
5516                         ret = i40e_dev_link_update(dev, 0);
5517                         if (!ret) {
5518                                 i40e_notify_all_vfs_link_status(dev);
5519                                 _rte_eth_dev_callback_process(dev,
5520                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5521                         }
5522                         break;
5523                 default:
5524                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5525                                     opcode);
5526                         break;
5527                 }
5528         }
5529         rte_free(info.msg_buf);
5530 }
5531
5532 /**
5533  * Interrupt handler triggered by NIC  for handling
5534  * specific interrupt.
5535  *
5536  * @param handle
5537  *  Pointer to interrupt handle.
5538  * @param param
5539  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5540  *
5541  * @return
5542  *  void
5543  */
5544 static void
5545 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5546                            void *param)
5547 {
5548         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5549         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5550         uint32_t icr0;
5551
5552         /* Disable interrupt */
5553         i40e_pf_disable_irq0(hw);
5554
5555         /* read out interrupt causes */
5556         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5557
5558         /* No interrupt event indicated */
5559         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5560                 PMD_DRV_LOG(INFO, "No interrupt event");
5561                 goto done;
5562         }
5563 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5564         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5565                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5566         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5567                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5568         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5569                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5570         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5571                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5572         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5573                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5574         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5575                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5576         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5577                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5578 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5579
5580         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5581                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5582                 i40e_dev_handle_vfr_event(dev);
5583         }
5584         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5585                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5586                 i40e_dev_handle_aq_msg(dev);
5587         }
5588
5589 done:
5590         /* Enable interrupt */
5591         i40e_pf_enable_irq0(hw);
5592         rte_intr_enable(intr_handle);
5593 }
5594
5595 static int
5596 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5597                          struct i40e_macvlan_filter *filter,
5598                          int total)
5599 {
5600         int ele_num, ele_buff_size;
5601         int num, actual_num, i;
5602         uint16_t flags;
5603         int ret = I40E_SUCCESS;
5604         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5605         struct i40e_aqc_add_macvlan_element_data *req_list;
5606
5607         if (filter == NULL  || total == 0)
5608                 return I40E_ERR_PARAM;
5609         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5610         ele_buff_size = hw->aq.asq_buf_size;
5611
5612         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5613         if (req_list == NULL) {
5614                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5615                 return I40E_ERR_NO_MEMORY;
5616         }
5617
5618         num = 0;
5619         do {
5620                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5621                 memset(req_list, 0, ele_buff_size);
5622
5623                 for (i = 0; i < actual_num; i++) {
5624                         (void)rte_memcpy(req_list[i].mac_addr,
5625                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5626                         req_list[i].vlan_tag =
5627                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5628
5629                         switch (filter[num + i].filter_type) {
5630                         case RTE_MAC_PERFECT_MATCH:
5631                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5632                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5633                                 break;
5634                         case RTE_MACVLAN_PERFECT_MATCH:
5635                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5636                                 break;
5637                         case RTE_MAC_HASH_MATCH:
5638                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5639                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5640                                 break;
5641                         case RTE_MACVLAN_HASH_MATCH:
5642                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5643                                 break;
5644                         default:
5645                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5646                                 ret = I40E_ERR_PARAM;
5647                                 goto DONE;
5648                         }
5649
5650                         req_list[i].queue_number = 0;
5651
5652                         req_list[i].flags = rte_cpu_to_le_16(flags);
5653                 }
5654
5655                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5656                                                 actual_num, NULL);
5657                 if (ret != I40E_SUCCESS) {
5658                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5659                         goto DONE;
5660                 }
5661                 num += actual_num;
5662         } while (num < total);
5663
5664 DONE:
5665         rte_free(req_list);
5666         return ret;
5667 }
5668
5669 static int
5670 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5671                             struct i40e_macvlan_filter *filter,
5672                             int total)
5673 {
5674         int ele_num, ele_buff_size;
5675         int num, actual_num, i;
5676         uint16_t flags;
5677         int ret = I40E_SUCCESS;
5678         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5679         struct i40e_aqc_remove_macvlan_element_data *req_list;
5680
5681         if (filter == NULL  || total == 0)
5682                 return I40E_ERR_PARAM;
5683
5684         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5685         ele_buff_size = hw->aq.asq_buf_size;
5686
5687         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5688         if (req_list == NULL) {
5689                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5690                 return I40E_ERR_NO_MEMORY;
5691         }
5692
5693         num = 0;
5694         do {
5695                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5696                 memset(req_list, 0, ele_buff_size);
5697
5698                 for (i = 0; i < actual_num; i++) {
5699                         (void)rte_memcpy(req_list[i].mac_addr,
5700                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5701                         req_list[i].vlan_tag =
5702                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5703
5704                         switch (filter[num + i].filter_type) {
5705                         case RTE_MAC_PERFECT_MATCH:
5706                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5707                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5708                                 break;
5709                         case RTE_MACVLAN_PERFECT_MATCH:
5710                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5711                                 break;
5712                         case RTE_MAC_HASH_MATCH:
5713                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5714                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5715                                 break;
5716                         case RTE_MACVLAN_HASH_MATCH:
5717                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5718                                 break;
5719                         default:
5720                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5721                                 ret = I40E_ERR_PARAM;
5722                                 goto DONE;
5723                         }
5724                         req_list[i].flags = rte_cpu_to_le_16(flags);
5725                 }
5726
5727                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5728                                                 actual_num, NULL);
5729                 if (ret != I40E_SUCCESS) {
5730                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5731                         goto DONE;
5732                 }
5733                 num += actual_num;
5734         } while (num < total);
5735
5736 DONE:
5737         rte_free(req_list);
5738         return ret;
5739 }
5740
5741 /* Find out specific MAC filter */
5742 static struct i40e_mac_filter *
5743 i40e_find_mac_filter(struct i40e_vsi *vsi,
5744                          struct ether_addr *macaddr)
5745 {
5746         struct i40e_mac_filter *f;
5747
5748         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5749                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5750                         return f;
5751         }
5752
5753         return NULL;
5754 }
5755
5756 static bool
5757 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5758                          uint16_t vlan_id)
5759 {
5760         uint32_t vid_idx, vid_bit;
5761
5762         if (vlan_id > ETH_VLAN_ID_MAX)
5763                 return 0;
5764
5765         vid_idx = I40E_VFTA_IDX(vlan_id);
5766         vid_bit = I40E_VFTA_BIT(vlan_id);
5767
5768         if (vsi->vfta[vid_idx] & vid_bit)
5769                 return 1;
5770         else
5771                 return 0;
5772 }
5773
5774 static void
5775 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5776                          uint16_t vlan_id, bool on)
5777 {
5778         uint32_t vid_idx, vid_bit;
5779
5780         if (vlan_id > ETH_VLAN_ID_MAX)
5781                 return;
5782
5783         vid_idx = I40E_VFTA_IDX(vlan_id);
5784         vid_bit = I40E_VFTA_BIT(vlan_id);
5785
5786         if (on)
5787                 vsi->vfta[vid_idx] |= vid_bit;
5788         else
5789                 vsi->vfta[vid_idx] &= ~vid_bit;
5790 }
5791
5792 /**
5793  * Find all vlan options for specific mac addr,
5794  * return with actual vlan found.
5795  */
5796 static inline int
5797 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5798                            struct i40e_macvlan_filter *mv_f,
5799                            int num, struct ether_addr *addr)
5800 {
5801         int i;
5802         uint32_t j, k;
5803
5804         /**
5805          * Not to use i40e_find_vlan_filter to decrease the loop time,
5806          * although the code looks complex.
5807           */
5808         if (num < vsi->vlan_num)
5809                 return I40E_ERR_PARAM;
5810
5811         i = 0;
5812         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5813                 if (vsi->vfta[j]) {
5814                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5815                                 if (vsi->vfta[j] & (1 << k)) {
5816                                         if (i > num - 1) {
5817                                                 PMD_DRV_LOG(ERR, "vlan number "
5818                                                             "not match");
5819                                                 return I40E_ERR_PARAM;
5820                                         }
5821                                         (void)rte_memcpy(&mv_f[i].macaddr,
5822                                                         addr, ETH_ADDR_LEN);
5823                                         mv_f[i].vlan_id =
5824                                                 j * I40E_UINT32_BIT_SIZE + k;
5825                                         i++;
5826                                 }
5827                         }
5828                 }
5829         }
5830         return I40E_SUCCESS;
5831 }
5832
5833 static inline int
5834 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5835                            struct i40e_macvlan_filter *mv_f,
5836                            int num,
5837                            uint16_t vlan)
5838 {
5839         int i = 0;
5840         struct i40e_mac_filter *f;
5841
5842         if (num < vsi->mac_num)
5843                 return I40E_ERR_PARAM;
5844
5845         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5846                 if (i > num - 1) {
5847                         PMD_DRV_LOG(ERR, "buffer number not match");
5848                         return I40E_ERR_PARAM;
5849                 }
5850                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5851                                 ETH_ADDR_LEN);
5852                 mv_f[i].vlan_id = vlan;
5853                 mv_f[i].filter_type = f->mac_info.filter_type;
5854                 i++;
5855         }
5856
5857         return I40E_SUCCESS;
5858 }
5859
5860 static int
5861 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5862 {
5863         int i, num;
5864         struct i40e_mac_filter *f;
5865         struct i40e_macvlan_filter *mv_f;
5866         int ret = I40E_SUCCESS;
5867
5868         if (vsi == NULL || vsi->mac_num == 0)
5869                 return I40E_ERR_PARAM;
5870
5871         /* Case that no vlan is set */
5872         if (vsi->vlan_num == 0)
5873                 num = vsi->mac_num;
5874         else
5875                 num = vsi->mac_num * vsi->vlan_num;
5876
5877         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5878         if (mv_f == NULL) {
5879                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5880                 return I40E_ERR_NO_MEMORY;
5881         }
5882
5883         i = 0;
5884         if (vsi->vlan_num == 0) {
5885                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5886                         (void)rte_memcpy(&mv_f[i].macaddr,
5887                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5888                         mv_f[i].vlan_id = 0;
5889                         i++;
5890                 }
5891         } else {
5892                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5893                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5894                                         vsi->vlan_num, &f->mac_info.mac_addr);
5895                         if (ret != I40E_SUCCESS)
5896                                 goto DONE;
5897                         i += vsi->vlan_num;
5898                 }
5899         }
5900
5901         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5902 DONE:
5903         rte_free(mv_f);
5904
5905         return ret;
5906 }
5907
5908 int
5909 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5910 {
5911         struct i40e_macvlan_filter *mv_f;
5912         int mac_num;
5913         int ret = I40E_SUCCESS;
5914
5915         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5916                 return I40E_ERR_PARAM;
5917
5918         /* If it's already set, just return */
5919         if (i40e_find_vlan_filter(vsi,vlan))
5920                 return I40E_SUCCESS;
5921
5922         mac_num = vsi->mac_num;
5923
5924         if (mac_num == 0) {
5925                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5926                 return I40E_ERR_PARAM;
5927         }
5928
5929         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5930
5931         if (mv_f == NULL) {
5932                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5933                 return I40E_ERR_NO_MEMORY;
5934         }
5935
5936         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5937
5938         if (ret != I40E_SUCCESS)
5939                 goto DONE;
5940
5941         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5942
5943         if (ret != I40E_SUCCESS)
5944                 goto DONE;
5945
5946         i40e_set_vlan_filter(vsi, vlan, 1);
5947
5948         vsi->vlan_num++;
5949         ret = I40E_SUCCESS;
5950 DONE:
5951         rte_free(mv_f);
5952         return ret;
5953 }
5954
5955 int
5956 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5957 {
5958         struct i40e_macvlan_filter *mv_f;
5959         int mac_num;
5960         int ret = I40E_SUCCESS;
5961
5962         /**
5963          * Vlan 0 is the generic filter for untagged packets
5964          * and can't be removed.
5965          */
5966         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5967                 return I40E_ERR_PARAM;
5968
5969         /* If can't find it, just return */
5970         if (!i40e_find_vlan_filter(vsi, vlan))
5971                 return I40E_ERR_PARAM;
5972
5973         mac_num = vsi->mac_num;
5974
5975         if (mac_num == 0) {
5976                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5977                 return I40E_ERR_PARAM;
5978         }
5979
5980         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5981
5982         if (mv_f == NULL) {
5983                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5984                 return I40E_ERR_NO_MEMORY;
5985         }
5986
5987         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5988
5989         if (ret != I40E_SUCCESS)
5990                 goto DONE;
5991
5992         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5993
5994         if (ret != I40E_SUCCESS)
5995                 goto DONE;
5996
5997         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5998         if (vsi->vlan_num == 1) {
5999                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6000                 if (ret != I40E_SUCCESS)
6001                         goto DONE;
6002
6003                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6004                 if (ret != I40E_SUCCESS)
6005                         goto DONE;
6006         }
6007
6008         i40e_set_vlan_filter(vsi, vlan, 0);
6009
6010         vsi->vlan_num--;
6011         ret = I40E_SUCCESS;
6012 DONE:
6013         rte_free(mv_f);
6014         return ret;
6015 }
6016
6017 int
6018 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6019 {
6020         struct i40e_mac_filter *f;
6021         struct i40e_macvlan_filter *mv_f;
6022         int i, vlan_num = 0;
6023         int ret = I40E_SUCCESS;
6024
6025         /* If it's add and we've config it, return */
6026         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6027         if (f != NULL)
6028                 return I40E_SUCCESS;
6029         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6030                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6031
6032                 /**
6033                  * If vlan_num is 0, that's the first time to add mac,
6034                  * set mask for vlan_id 0.
6035                  */
6036                 if (vsi->vlan_num == 0) {
6037                         i40e_set_vlan_filter(vsi, 0, 1);
6038                         vsi->vlan_num = 1;
6039                 }
6040                 vlan_num = vsi->vlan_num;
6041         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6042                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6043                 vlan_num = 1;
6044
6045         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6046         if (mv_f == NULL) {
6047                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6048                 return I40E_ERR_NO_MEMORY;
6049         }
6050
6051         for (i = 0; i < vlan_num; i++) {
6052                 mv_f[i].filter_type = mac_filter->filter_type;
6053                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6054                                 ETH_ADDR_LEN);
6055         }
6056
6057         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6058                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6059                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6060                                         &mac_filter->mac_addr);
6061                 if (ret != I40E_SUCCESS)
6062                         goto DONE;
6063         }
6064
6065         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6066         if (ret != I40E_SUCCESS)
6067                 goto DONE;
6068
6069         /* Add the mac addr into mac list */
6070         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6071         if (f == NULL) {
6072                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6073                 ret = I40E_ERR_NO_MEMORY;
6074                 goto DONE;
6075         }
6076         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6077                         ETH_ADDR_LEN);
6078         f->mac_info.filter_type = mac_filter->filter_type;
6079         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6080         vsi->mac_num++;
6081
6082         ret = I40E_SUCCESS;
6083 DONE:
6084         rte_free(mv_f);
6085
6086         return ret;
6087 }
6088
6089 int
6090 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6091 {
6092         struct i40e_mac_filter *f;
6093         struct i40e_macvlan_filter *mv_f;
6094         int i, vlan_num;
6095         enum rte_mac_filter_type filter_type;
6096         int ret = I40E_SUCCESS;
6097
6098         /* Can't find it, return an error */
6099         f = i40e_find_mac_filter(vsi, addr);
6100         if (f == NULL)
6101                 return I40E_ERR_PARAM;
6102
6103         vlan_num = vsi->vlan_num;
6104         filter_type = f->mac_info.filter_type;
6105         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6106                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6107                 if (vlan_num == 0) {
6108                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6109                         return I40E_ERR_PARAM;
6110                 }
6111         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6112                         filter_type == RTE_MAC_HASH_MATCH)
6113                 vlan_num = 1;
6114
6115         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6116         if (mv_f == NULL) {
6117                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6118                 return I40E_ERR_NO_MEMORY;
6119         }
6120
6121         for (i = 0; i < vlan_num; i++) {
6122                 mv_f[i].filter_type = filter_type;
6123                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6124                                 ETH_ADDR_LEN);
6125         }
6126         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6127                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6128                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6129                 if (ret != I40E_SUCCESS)
6130                         goto DONE;
6131         }
6132
6133         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6134         if (ret != I40E_SUCCESS)
6135                 goto DONE;
6136
6137         /* Remove the mac addr into mac list */
6138         TAILQ_REMOVE(&vsi->mac_list, f, next);
6139         rte_free(f);
6140         vsi->mac_num--;
6141
6142         ret = I40E_SUCCESS;
6143 DONE:
6144         rte_free(mv_f);
6145         return ret;
6146 }
6147
6148 /* Configure hash enable flags for RSS */
6149 uint64_t
6150 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6151 {
6152         uint64_t hena = 0;
6153
6154         if (!flags)
6155                 return hena;
6156
6157         if (flags & ETH_RSS_FRAG_IPV4)
6158                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6159         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6160                 if (type == I40E_MAC_X722) {
6161                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6162                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6163                 } else
6164                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6165         }
6166         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6167                 if (type == I40E_MAC_X722) {
6168                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6169                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6170                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6171                 } else
6172                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6173         }
6174         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6175                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6176         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6177                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6178         if (flags & ETH_RSS_FRAG_IPV6)
6179                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6180         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6181                 if (type == I40E_MAC_X722) {
6182                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6183                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6184                 } else
6185                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6186         }
6187         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6188                 if (type == I40E_MAC_X722) {
6189                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6190                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6191                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6192                 } else
6193                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6194         }
6195         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6196                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6197         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6198                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6199         if (flags & ETH_RSS_L2_PAYLOAD)
6200                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6201
6202         return hena;
6203 }
6204
6205 /* Parse the hash enable flags */
6206 uint64_t
6207 i40e_parse_hena(uint64_t flags)
6208 {
6209         uint64_t rss_hf = 0;
6210
6211         if (!flags)
6212                 return rss_hf;
6213         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6214                 rss_hf |= ETH_RSS_FRAG_IPV4;
6215         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6216                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6217 #ifdef X722_SUPPORT
6218         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6219                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6220 #endif
6221         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6222                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6223 #ifdef X722_SUPPORT
6224         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6225                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6226         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6227                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6228 #endif
6229         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6230                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6231         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6232                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6233         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6234                 rss_hf |= ETH_RSS_FRAG_IPV6;
6235         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6236                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6237 #ifdef X722_SUPPORT
6238         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6239                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6240 #endif
6241         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6242                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6243 #ifdef X722_SUPPORT
6244         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6245                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6246         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6247                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6248 #endif
6249         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6250                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6251         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6252                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6253         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6254                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6255
6256         return rss_hf;
6257 }
6258
6259 /* Disable RSS */
6260 static void
6261 i40e_pf_disable_rss(struct i40e_pf *pf)
6262 {
6263         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6264         uint64_t hena;
6265
6266         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6267         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6268         if (hw->mac.type == I40E_MAC_X722)
6269                 hena &= ~I40E_RSS_HENA_ALL_X722;
6270         else
6271                 hena &= ~I40E_RSS_HENA_ALL;
6272         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6273         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6274         I40E_WRITE_FLUSH(hw);
6275 }
6276
6277 static int
6278 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6279 {
6280         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6281         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6282         int ret = 0;
6283
6284         if (!key || key_len == 0) {
6285                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6286                 return 0;
6287         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6288                 sizeof(uint32_t)) {
6289                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6290                 return -EINVAL;
6291         }
6292
6293         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6294                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6295                         (struct i40e_aqc_get_set_rss_key_data *)key;
6296
6297                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6298                 if (ret)
6299                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6300                                      "via AQ");
6301         } else {
6302                 uint32_t *hash_key = (uint32_t *)key;
6303                 uint16_t i;
6304
6305                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6306                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6307                 I40E_WRITE_FLUSH(hw);
6308         }
6309
6310         return ret;
6311 }
6312
6313 static int
6314 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6315 {
6316         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6317         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6318         int ret;
6319
6320         if (!key || !key_len)
6321                 return -EINVAL;
6322
6323         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6324                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6325                         (struct i40e_aqc_get_set_rss_key_data *)key);
6326                 if (ret) {
6327                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6328                         return ret;
6329                 }
6330         } else {
6331                 uint32_t *key_dw = (uint32_t *)key;
6332                 uint16_t i;
6333
6334                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6335                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6336         }
6337         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6338
6339         return 0;
6340 }
6341
6342 static int
6343 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6344 {
6345         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6346         uint64_t rss_hf;
6347         uint64_t hena;
6348         int ret;
6349
6350         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6351                                rss_conf->rss_key_len);
6352         if (ret)
6353                 return ret;
6354
6355         rss_hf = rss_conf->rss_hf;
6356         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6357         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6358         if (hw->mac.type == I40E_MAC_X722)
6359                 hena &= ~I40E_RSS_HENA_ALL_X722;
6360         else
6361                 hena &= ~I40E_RSS_HENA_ALL;
6362         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6363         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6364         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6365         I40E_WRITE_FLUSH(hw);
6366
6367         return 0;
6368 }
6369
6370 static int
6371 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6372                          struct rte_eth_rss_conf *rss_conf)
6373 {
6374         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6375         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6376         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6377         uint64_t hena;
6378
6379         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6380         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6381         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6382                  ? I40E_RSS_HENA_ALL_X722
6383                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6384                 if (rss_hf != 0) /* Enable RSS */
6385                         return -EINVAL;
6386                 return 0; /* Nothing to do */
6387         }
6388         /* RSS enabled */
6389         if (rss_hf == 0) /* Disable RSS */
6390                 return -EINVAL;
6391
6392         return i40e_hw_rss_hash_set(pf, rss_conf);
6393 }
6394
6395 static int
6396 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6397                            struct rte_eth_rss_conf *rss_conf)
6398 {
6399         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6400         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6401         uint64_t hena;
6402
6403         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6404                          &rss_conf->rss_key_len);
6405
6406         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6407         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6408         rss_conf->rss_hf = i40e_parse_hena(hena);
6409
6410         return 0;
6411 }
6412
6413 static int
6414 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6415 {
6416         switch (filter_type) {
6417         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6418                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6419                 break;
6420         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6421                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6422                 break;
6423         case RTE_TUNNEL_FILTER_IMAC_TENID:
6424                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6425                 break;
6426         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6427                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6428                 break;
6429         case ETH_TUNNEL_FILTER_IMAC:
6430                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6431                 break;
6432         case ETH_TUNNEL_FILTER_OIP:
6433                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6434                 break;
6435         case ETH_TUNNEL_FILTER_IIP:
6436                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6437                 break;
6438         default:
6439                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6440                 return -EINVAL;
6441         }
6442
6443         return 0;
6444 }
6445
6446 static int
6447 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6448                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6449                         uint8_t add)
6450 {
6451         uint16_t ip_type;
6452         uint32_t ipv4_addr;
6453         uint8_t i, tun_type = 0;
6454         /* internal varialbe to convert ipv6 byte order */
6455         uint32_t convert_ipv6[4];
6456         int val, ret = 0;
6457         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6458         struct i40e_vsi *vsi = pf->main_vsi;
6459         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6460         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6461
6462         cld_filter = rte_zmalloc("tunnel_filter",
6463                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6464                 0);
6465
6466         if (NULL == cld_filter) {
6467                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6468                 return -EINVAL;
6469         }
6470         pfilter = cld_filter;
6471
6472         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6473         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6474
6475         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6476         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6477                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6478                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6479                 rte_memcpy(&pfilter->ipaddr.v4.data,
6480                                 &rte_cpu_to_le_32(ipv4_addr),
6481                                 sizeof(pfilter->ipaddr.v4.data));
6482         } else {
6483                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6484                 for (i = 0; i < 4; i++) {
6485                         convert_ipv6[i] =
6486                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6487                 }
6488                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6489                                 sizeof(pfilter->ipaddr.v6.data));
6490         }
6491
6492         /* check tunneled type */
6493         switch (tunnel_filter->tunnel_type) {
6494         case RTE_TUNNEL_TYPE_VXLAN:
6495                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6496                 break;
6497         case RTE_TUNNEL_TYPE_NVGRE:
6498                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6499                 break;
6500         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6501                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6502                 break;
6503         default:
6504                 /* Other tunnel types is not supported. */
6505                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6506                 rte_free(cld_filter);
6507                 return -EINVAL;
6508         }
6509
6510         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6511                                                 &pfilter->flags);
6512         if (val < 0) {
6513                 rte_free(cld_filter);
6514                 return -EINVAL;
6515         }
6516
6517         pfilter->flags |= rte_cpu_to_le_16(
6518                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6519                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6520         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6521         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6522
6523         if (add)
6524                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6525         else
6526                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6527                                                 cld_filter, 1);
6528
6529         rte_free(cld_filter);
6530         return ret;
6531 }
6532
6533 static int
6534 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6535 {
6536         uint8_t i;
6537
6538         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6539                 if (pf->vxlan_ports[i] == port)
6540                         return i;
6541         }
6542
6543         return -1;
6544 }
6545
6546 static int
6547 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6548 {
6549         int  idx, ret;
6550         uint8_t filter_idx;
6551         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6552
6553         idx = i40e_get_vxlan_port_idx(pf, port);
6554
6555         /* Check if port already exists */
6556         if (idx >= 0) {
6557                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6558                 return -EINVAL;
6559         }
6560
6561         /* Now check if there is space to add the new port */
6562         idx = i40e_get_vxlan_port_idx(pf, 0);
6563         if (idx < 0) {
6564                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6565                         "not adding port %d", port);
6566                 return -ENOSPC;
6567         }
6568
6569         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6570                                         &filter_idx, NULL);
6571         if (ret < 0) {
6572                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6573                 return -1;
6574         }
6575
6576         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6577                          port,  filter_idx);
6578
6579         /* New port: add it and mark its index in the bitmap */
6580         pf->vxlan_ports[idx] = port;
6581         pf->vxlan_bitmap |= (1 << idx);
6582
6583         if (!(pf->flags & I40E_FLAG_VXLAN))
6584                 pf->flags |= I40E_FLAG_VXLAN;
6585
6586         return 0;
6587 }
6588
6589 static int
6590 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6591 {
6592         int idx;
6593         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6594
6595         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6596                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6597                 return -EINVAL;
6598         }
6599
6600         idx = i40e_get_vxlan_port_idx(pf, port);
6601
6602         if (idx < 0) {
6603                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6604                 return -EINVAL;
6605         }
6606
6607         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6608                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6609                 return -1;
6610         }
6611
6612         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6613                         port, idx);
6614
6615         pf->vxlan_ports[idx] = 0;
6616         pf->vxlan_bitmap &= ~(1 << idx);
6617
6618         if (!pf->vxlan_bitmap)
6619                 pf->flags &= ~I40E_FLAG_VXLAN;
6620
6621         return 0;
6622 }
6623
6624 /* Add UDP tunneling port */
6625 static int
6626 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6627                              struct rte_eth_udp_tunnel *udp_tunnel)
6628 {
6629         int ret = 0;
6630         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6631
6632         if (udp_tunnel == NULL)
6633                 return -EINVAL;
6634
6635         switch (udp_tunnel->prot_type) {
6636         case RTE_TUNNEL_TYPE_VXLAN:
6637                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6638                 break;
6639
6640         case RTE_TUNNEL_TYPE_GENEVE:
6641         case RTE_TUNNEL_TYPE_TEREDO:
6642                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6643                 ret = -1;
6644                 break;
6645
6646         default:
6647                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6648                 ret = -1;
6649                 break;
6650         }
6651
6652         return ret;
6653 }
6654
6655 /* Remove UDP tunneling port */
6656 static int
6657 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6658                              struct rte_eth_udp_tunnel *udp_tunnel)
6659 {
6660         int ret = 0;
6661         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6662
6663         if (udp_tunnel == NULL)
6664                 return -EINVAL;
6665
6666         switch (udp_tunnel->prot_type) {
6667         case RTE_TUNNEL_TYPE_VXLAN:
6668                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6669                 break;
6670         case RTE_TUNNEL_TYPE_GENEVE:
6671         case RTE_TUNNEL_TYPE_TEREDO:
6672                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6673                 ret = -1;
6674                 break;
6675         default:
6676                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6677                 ret = -1;
6678                 break;
6679         }
6680
6681         return ret;
6682 }
6683
6684 /* Calculate the maximum number of contiguous PF queues that are configured */
6685 static int
6686 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6687 {
6688         struct rte_eth_dev_data *data = pf->dev_data;
6689         int i, num;
6690         struct i40e_rx_queue *rxq;
6691
6692         num = 0;
6693         for (i = 0; i < pf->lan_nb_qps; i++) {
6694                 rxq = data->rx_queues[i];
6695                 if (rxq && rxq->q_set)
6696                         num++;
6697                 else
6698                         break;
6699         }
6700
6701         return num;
6702 }
6703
6704 /* Configure RSS */
6705 static int
6706 i40e_pf_config_rss(struct i40e_pf *pf)
6707 {
6708         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6709         struct rte_eth_rss_conf rss_conf;
6710         uint32_t i, lut = 0;
6711         uint16_t j, num;
6712
6713         /*
6714          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6715          * It's necessary to calulate the actual PF queues that are configured.
6716          */
6717         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6718                 num = i40e_pf_calc_configured_queues_num(pf);
6719         else
6720                 num = pf->dev_data->nb_rx_queues;
6721
6722         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6723         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6724                         num);
6725
6726         if (num == 0) {
6727                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6728                 return -ENOTSUP;
6729         }
6730
6731         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6732                 if (j == num)
6733                         j = 0;
6734                 lut = (lut << 8) | (j & ((0x1 <<
6735                         hw->func_caps.rss_table_entry_width) - 1));
6736                 if ((i & 3) == 3)
6737                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6738         }
6739
6740         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6741         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6742                 i40e_pf_disable_rss(pf);
6743                 return 0;
6744         }
6745         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6746                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6747                 /* Random default keys */
6748                 static uint32_t rss_key_default[] = {0x6b793944,
6749                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6750                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6751                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6752
6753                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6754                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6755                                                         sizeof(uint32_t);
6756         }
6757
6758         return i40e_hw_rss_hash_set(pf, &rss_conf);
6759 }
6760
6761 static int
6762 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6763                                struct rte_eth_tunnel_filter_conf *filter)
6764 {
6765         if (pf == NULL || filter == NULL) {
6766                 PMD_DRV_LOG(ERR, "Invalid parameter");
6767                 return -EINVAL;
6768         }
6769
6770         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6771                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6772                 return -EINVAL;
6773         }
6774
6775         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6776                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6777                 return -EINVAL;
6778         }
6779
6780         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6781                 (is_zero_ether_addr(&filter->outer_mac))) {
6782                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6783                 return -EINVAL;
6784         }
6785
6786         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6787                 (is_zero_ether_addr(&filter->inner_mac))) {
6788                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6789                 return -EINVAL;
6790         }
6791
6792         return 0;
6793 }
6794
6795 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6796 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6797 static int
6798 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6799 {
6800         uint32_t val, reg;
6801         int ret = -EINVAL;
6802
6803         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6804         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6805
6806         if (len == 3) {
6807                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6808         } else if (len == 4) {
6809                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6810         } else {
6811                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6812                 return ret;
6813         }
6814
6815         if (reg != val) {
6816                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6817                                                    reg, NULL);
6818                 if (ret != 0)
6819                         return ret;
6820         } else {
6821                 ret = 0;
6822         }
6823         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6824                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6825
6826         return ret;
6827 }
6828
6829 static int
6830 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6831 {
6832         int ret = -EINVAL;
6833
6834         if (!hw || !cfg)
6835                 return -EINVAL;
6836
6837         switch (cfg->cfg_type) {
6838         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6839                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6840                 break;
6841         default:
6842                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6843                 break;
6844         }
6845
6846         return ret;
6847 }
6848
6849 static int
6850 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6851                                enum rte_filter_op filter_op,
6852                                void *arg)
6853 {
6854         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6855         int ret = I40E_ERR_PARAM;
6856
6857         switch (filter_op) {
6858         case RTE_ETH_FILTER_SET:
6859                 ret = i40e_dev_global_config_set(hw,
6860                         (struct rte_eth_global_cfg *)arg);
6861                 break;
6862         default:
6863                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6864                 break;
6865         }
6866
6867         return ret;
6868 }
6869
6870 static int
6871 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6872                           enum rte_filter_op filter_op,
6873                           void *arg)
6874 {
6875         struct rte_eth_tunnel_filter_conf *filter;
6876         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6877         int ret = I40E_SUCCESS;
6878
6879         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6880
6881         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6882                 return I40E_ERR_PARAM;
6883
6884         switch (filter_op) {
6885         case RTE_ETH_FILTER_NOP:
6886                 if (!(pf->flags & I40E_FLAG_VXLAN))
6887                         ret = I40E_NOT_SUPPORTED;
6888                 break;
6889         case RTE_ETH_FILTER_ADD:
6890                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6891                 break;
6892         case RTE_ETH_FILTER_DELETE:
6893                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6894                 break;
6895         default:
6896                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6897                 ret = I40E_ERR_PARAM;
6898                 break;
6899         }
6900
6901         return ret;
6902 }
6903
6904 static int
6905 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6906 {
6907         int ret = 0;
6908         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6909
6910         /* RSS setup */
6911         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6912                 ret = i40e_pf_config_rss(pf);
6913         else
6914                 i40e_pf_disable_rss(pf);
6915
6916         return ret;
6917 }
6918
6919 /* Get the symmetric hash enable configurations per port */
6920 static void
6921 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6922 {
6923         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6924
6925         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6926 }
6927
6928 /* Set the symmetric hash enable configurations per port */
6929 static void
6930 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6931 {
6932         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6933
6934         if (enable > 0) {
6935                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6936                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6937                                                         "been enabled");
6938                         return;
6939                 }
6940                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6941         } else {
6942                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6943                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6944                                                         "been disabled");
6945                         return;
6946                 }
6947                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6948         }
6949         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6950         I40E_WRITE_FLUSH(hw);
6951 }
6952
6953 /*
6954  * Get global configurations of hash function type and symmetric hash enable
6955  * per flow type (pctype). Note that global configuration means it affects all
6956  * the ports on the same NIC.
6957  */
6958 static int
6959 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6960                                    struct rte_eth_hash_global_conf *g_cfg)
6961 {
6962         uint32_t reg, mask = I40E_FLOW_TYPES;
6963         uint16_t i;
6964         enum i40e_filter_pctype pctype;
6965
6966         memset(g_cfg, 0, sizeof(*g_cfg));
6967         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6968         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6969                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6970         else
6971                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6972         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6973                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6974
6975         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6976                 if (!(mask & (1UL << i)))
6977                         continue;
6978                 mask &= ~(1UL << i);
6979                 /* Bit set indicats the coresponding flow type is supported */
6980                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6981                 /* if flowtype is invalid, continue */
6982                 if (!I40E_VALID_FLOW(i))
6983                         continue;
6984                 pctype = i40e_flowtype_to_pctype(i);
6985                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6986                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6987                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6988         }
6989
6990         return 0;
6991 }
6992
6993 static int
6994 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6995 {
6996         uint32_t i;
6997         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6998
6999         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7000                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7001                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7002                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7003                                                 g_cfg->hash_func);
7004                 return -EINVAL;
7005         }
7006
7007         /*
7008          * As i40e supports less than 32 flow types, only first 32 bits need to
7009          * be checked.
7010          */
7011         mask0 = g_cfg->valid_bit_mask[0];
7012         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7013                 if (i == 0) {
7014                         /* Check if any unsupported flow type configured */
7015                         if ((mask0 | i40e_mask) ^ i40e_mask)
7016                                 goto mask_err;
7017                 } else {
7018                         if (g_cfg->valid_bit_mask[i])
7019                                 goto mask_err;
7020                 }
7021         }
7022
7023         return 0;
7024
7025 mask_err:
7026         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7027
7028         return -EINVAL;
7029 }
7030
7031 /*
7032  * Set global configurations of hash function type and symmetric hash enable
7033  * per flow type (pctype). Note any modifying global configuration will affect
7034  * all the ports on the same NIC.
7035  */
7036 static int
7037 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7038                                    struct rte_eth_hash_global_conf *g_cfg)
7039 {
7040         int ret;
7041         uint16_t i;
7042         uint32_t reg;
7043         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7044         enum i40e_filter_pctype pctype;
7045
7046         /* Check the input parameters */
7047         ret = i40e_hash_global_config_check(g_cfg);
7048         if (ret < 0)
7049                 return ret;
7050
7051         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7052                 if (!(mask0 & (1UL << i)))
7053                         continue;
7054                 mask0 &= ~(1UL << i);
7055                 /* if flowtype is invalid, continue */
7056                 if (!I40E_VALID_FLOW(i))
7057                         continue;
7058                 pctype = i40e_flowtype_to_pctype(i);
7059                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7060                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7061                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7062         }
7063
7064         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7065         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7066                 /* Toeplitz */
7067                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7068                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7069                                                                 "Toeplitz");
7070                         goto out;
7071                 }
7072                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7073         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7074                 /* Simple XOR */
7075                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7076                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7077                                                         "Simple XOR");
7078                         goto out;
7079                 }
7080                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7081         } else
7082                 /* Use the default, and keep it as it is */
7083                 goto out;
7084
7085         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7086
7087 out:
7088         I40E_WRITE_FLUSH(hw);
7089
7090         return 0;
7091 }
7092
7093 /**
7094  * Valid input sets for hash and flow director filters per PCTYPE
7095  */
7096 static uint64_t
7097 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7098                 enum rte_filter_type filter)
7099 {
7100         uint64_t valid;
7101
7102         static const uint64_t valid_hash_inset_table[] = {
7103                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7104                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7105                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7106                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7107                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7108                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7109                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7110                         I40E_INSET_FLEX_PAYLOAD,
7111                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7112                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7113                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7114                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7115                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7116                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7117                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7118                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7119                         I40E_INSET_FLEX_PAYLOAD,
7120 #ifdef X722_SUPPORT
7121                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7122                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7123                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7124                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7125                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7126                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7127                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7128                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7129                         I40E_INSET_FLEX_PAYLOAD,
7130                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7131                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7132                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7133                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7134                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7135                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7136                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7137                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7138                         I40E_INSET_FLEX_PAYLOAD,
7139 #endif
7140                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7141                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7142                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7143                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7144                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7145                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7146                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7147                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7148                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7149 #ifdef X722_SUPPORT
7150                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7151                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7152                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7153                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7154                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7155                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7156                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7157                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7158                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7159 #endif
7160                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7161                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7162                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7163                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7164                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7165                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7166                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7167                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7168                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7169                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7170                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7171                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7172                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7173                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7174                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7175                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7176                         I40E_INSET_FLEX_PAYLOAD,
7177                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7178                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7179                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7180                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7181                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7182                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7183                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7184                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7185                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7186                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7187                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7188                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7189                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7190                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7191                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7192                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7193 #ifdef X722_SUPPORT
7194                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7195                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7196                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7197                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7198                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7199                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7200                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7201                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7202                         I40E_INSET_FLEX_PAYLOAD,
7203                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7204                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7205                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7206                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7207                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7208                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7209                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7210                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7211                         I40E_INSET_FLEX_PAYLOAD,
7212 #endif
7213                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7214                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7215                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7216                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7217                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7218                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7219                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7220                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7221                         I40E_INSET_FLEX_PAYLOAD,
7222 #ifdef X722_SUPPORT
7223                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7224                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7225                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7226                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7227                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7228                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7229                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7230                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7231                         I40E_INSET_FLEX_PAYLOAD,
7232 #endif
7233                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7234                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7235                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7236                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7237                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7238                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7239                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7240                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7241                         I40E_INSET_FLEX_PAYLOAD,
7242                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7243                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7244                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7245                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7246                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7247                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7248                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7249                         I40E_INSET_FLEX_PAYLOAD,
7250                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7251                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7252                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7253                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7254                         I40E_INSET_FLEX_PAYLOAD,
7255         };
7256
7257         /**
7258          * Flow director supports only fields defined in
7259          * union rte_eth_fdir_flow.
7260          */
7261         static const uint64_t valid_fdir_inset_table[] = {
7262                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7263                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7264                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7265                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7266                 I40E_INSET_IPV4_TTL,
7267                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7268                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7269                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7270                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7271                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7272 #ifdef X722_SUPPORT
7273                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7274                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7275                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7276                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7277                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7278                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7279                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7280                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7281                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7282                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7283 #endif
7284                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7285                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7286                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7287                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7288                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7289 #ifdef X722_SUPPORT
7290                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7291                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7292                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7293                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7294                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7295 #endif
7296                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7297                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7298                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7299                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7300                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7301                 I40E_INSET_SCTP_VT,
7302                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7303                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7304                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7305                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7306                 I40E_INSET_IPV4_TTL,
7307                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7308                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7309                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7310                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7311                 I40E_INSET_IPV6_HOP_LIMIT,
7312                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7313                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7314                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7315                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7316                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7317 #ifdef X722_SUPPORT
7318                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7319                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7320                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7321                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7322                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7323                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7324                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7325                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7326                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7327                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7328 #endif
7329                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7330                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7331                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7332                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7333                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7334 #ifdef X722_SUPPORT
7335                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7336                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7337                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7338                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7339                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7340 #endif
7341                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7342                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7343                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7344                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7345                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7346                 I40E_INSET_SCTP_VT,
7347                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7348                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7349                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7350                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7351                 I40E_INSET_IPV6_HOP_LIMIT,
7352                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7353                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7354                 I40E_INSET_LAST_ETHER_TYPE,
7355         };
7356
7357         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7358                 return 0;
7359         if (filter == RTE_ETH_FILTER_HASH)
7360                 valid = valid_hash_inset_table[pctype];
7361         else
7362                 valid = valid_fdir_inset_table[pctype];
7363
7364         return valid;
7365 }
7366
7367 /**
7368  * Validate if the input set is allowed for a specific PCTYPE
7369  */
7370 static int
7371 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7372                 enum rte_filter_type filter, uint64_t inset)
7373 {
7374         uint64_t valid;
7375
7376         valid = i40e_get_valid_input_set(pctype, filter);
7377         if (inset & (~valid))
7378                 return -EINVAL;
7379
7380         return 0;
7381 }
7382
7383 /* default input set fields combination per pctype */
7384 static uint64_t
7385 i40e_get_default_input_set(uint16_t pctype)
7386 {
7387         static const uint64_t default_inset_table[] = {
7388                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7389                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7390                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7391                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7392                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7393 #ifdef X722_SUPPORT
7394                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7395                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7396                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7397                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7398                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7399                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7400 #endif
7401                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7402                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7403                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7404 #ifdef X722_SUPPORT
7405                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7406                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7407                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7408 #endif
7409                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7410                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7411                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7412                         I40E_INSET_SCTP_VT,
7413                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7414                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7415                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7416                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7417                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7418                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7419                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7420 #ifdef X722_SUPPORT
7421                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7422                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7423                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7424                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7425                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7426                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7427 #endif
7428                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7429                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7430                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7431 #ifdef X722_SUPPORT
7432                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7433                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7434                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7435 #endif
7436                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7437                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7438                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7439                         I40E_INSET_SCTP_VT,
7440                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7441                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7442                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7443                         I40E_INSET_LAST_ETHER_TYPE,
7444         };
7445
7446         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7447                 return 0;
7448
7449         return default_inset_table[pctype];
7450 }
7451
7452 /**
7453  * Parse the input set from index to logical bit masks
7454  */
7455 static int
7456 i40e_parse_input_set(uint64_t *inset,
7457                      enum i40e_filter_pctype pctype,
7458                      enum rte_eth_input_set_field *field,
7459                      uint16_t size)
7460 {
7461         uint16_t i, j;
7462         int ret = -EINVAL;
7463
7464         static const struct {
7465                 enum rte_eth_input_set_field field;
7466                 uint64_t inset;
7467         } inset_convert_table[] = {
7468                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7469                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7470                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7471                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7472                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7473                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7474                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7475                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7476                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7477                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7478                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7479                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7480                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7481                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7482                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7483                         I40E_INSET_IPV6_NEXT_HDR},
7484                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7485                         I40E_INSET_IPV6_HOP_LIMIT},
7486                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7487                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7488                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7489                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7490                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7491                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7492                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7493                         I40E_INSET_SCTP_VT},
7494                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7495                         I40E_INSET_TUNNEL_DMAC},
7496                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7497                         I40E_INSET_VLAN_TUNNEL},
7498                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7499                         I40E_INSET_TUNNEL_ID},
7500                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7501                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7502                         I40E_INSET_FLEX_PAYLOAD_W1},
7503                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7504                         I40E_INSET_FLEX_PAYLOAD_W2},
7505                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7506                         I40E_INSET_FLEX_PAYLOAD_W3},
7507                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7508                         I40E_INSET_FLEX_PAYLOAD_W4},
7509                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7510                         I40E_INSET_FLEX_PAYLOAD_W5},
7511                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7512                         I40E_INSET_FLEX_PAYLOAD_W6},
7513                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7514                         I40E_INSET_FLEX_PAYLOAD_W7},
7515                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7516                         I40E_INSET_FLEX_PAYLOAD_W8},
7517         };
7518
7519         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7520                 return ret;
7521
7522         /* Only one item allowed for default or all */
7523         if (size == 1) {
7524                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7525                         *inset = i40e_get_default_input_set(pctype);
7526                         return 0;
7527                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7528                         *inset = I40E_INSET_NONE;
7529                         return 0;
7530                 }
7531         }
7532
7533         for (i = 0, *inset = 0; i < size; i++) {
7534                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7535                         if (field[i] == inset_convert_table[j].field) {
7536                                 *inset |= inset_convert_table[j].inset;
7537                                 break;
7538                         }
7539                 }
7540
7541                 /* It contains unsupported input set, return immediately */
7542                 if (j == RTE_DIM(inset_convert_table))
7543                         return ret;
7544         }
7545
7546         return 0;
7547 }
7548
7549 /**
7550  * Translate the input set from bit masks to register aware bit masks
7551  * and vice versa
7552  */
7553 static uint64_t
7554 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7555 {
7556         uint64_t val = 0;
7557         uint16_t i;
7558
7559         struct inset_map {
7560                 uint64_t inset;
7561                 uint64_t inset_reg;
7562         };
7563
7564         static const struct inset_map inset_map_common[] = {
7565                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7566                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7567                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7568                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7569                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7570                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7571                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7572                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7573                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7574                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7575                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7576                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7577                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7578                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7579                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7580                 {I40E_INSET_TUNNEL_DMAC,
7581                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7582                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7583                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7584                 {I40E_INSET_TUNNEL_SRC_PORT,
7585                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7586                 {I40E_INSET_TUNNEL_DST_PORT,
7587                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7588                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7589                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7590                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7591                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7592                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7593                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7594                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7595                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7596                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7597         };
7598
7599     /* some different registers map in x722*/
7600         static const struct inset_map inset_map_diff_x722[] = {
7601                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7602                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7603                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7604                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7605         };
7606
7607         static const struct inset_map inset_map_diff_not_x722[] = {
7608                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7609                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7610                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7611                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7612         };
7613
7614         if (input == 0)
7615                 return val;
7616
7617         /* Translate input set to register aware inset */
7618         if (type == I40E_MAC_X722) {
7619                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7620                         if (input & inset_map_diff_x722[i].inset)
7621                                 val |= inset_map_diff_x722[i].inset_reg;
7622                 }
7623         } else {
7624                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7625                         if (input & inset_map_diff_not_x722[i].inset)
7626                                 val |= inset_map_diff_not_x722[i].inset_reg;
7627                 }
7628         }
7629
7630         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7631                 if (input & inset_map_common[i].inset)
7632                         val |= inset_map_common[i].inset_reg;
7633         }
7634
7635         return val;
7636 }
7637
7638 static int
7639 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7640 {
7641         uint8_t i, idx = 0;
7642         uint64_t inset_need_mask = inset;
7643
7644         static const struct {
7645                 uint64_t inset;
7646                 uint32_t mask;
7647         } inset_mask_map[] = {
7648                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7649                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7650                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7651                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7652                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7653                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7654                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7655                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7656         };
7657
7658         if (!inset || !mask || !nb_elem)
7659                 return 0;
7660
7661         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7662                 /* Clear the inset bit, if no MASK is required,
7663                  * for example proto + ttl
7664                  */
7665                 if ((inset & inset_mask_map[i].inset) ==
7666                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7667                         inset_need_mask &= ~inset_mask_map[i].inset;
7668                 if (!inset_need_mask)
7669                         return 0;
7670         }
7671         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7672                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7673                     inset_mask_map[i].inset) {
7674                         if (idx >= nb_elem) {
7675                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7676                                 return -EINVAL;
7677                         }
7678                         mask[idx] = inset_mask_map[i].mask;
7679                         idx++;
7680                 }
7681         }
7682
7683         return idx;
7684 }
7685
7686 static void
7687 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7688 {
7689         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7690
7691         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7692         if (reg != val)
7693                 i40e_write_rx_ctl(hw, addr, val);
7694         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7695                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7696 }
7697
7698 static void
7699 i40e_filter_input_set_init(struct i40e_pf *pf)
7700 {
7701         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7702         enum i40e_filter_pctype pctype;
7703         uint64_t input_set, inset_reg;
7704         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7705         int num, i;
7706
7707         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7708              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7709                 if (hw->mac.type == I40E_MAC_X722) {
7710                         if (!I40E_VALID_PCTYPE_X722(pctype))
7711                                 continue;
7712                 } else {
7713                         if (!I40E_VALID_PCTYPE(pctype))
7714                                 continue;
7715                 }
7716
7717                 input_set = i40e_get_default_input_set(pctype);
7718
7719                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7720                                                    I40E_INSET_MASK_NUM_REG);
7721                 if (num < 0)
7722                         return;
7723                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
7724                                         input_set);
7725
7726                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7727                                       (uint32_t)(inset_reg & UINT32_MAX));
7728                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7729                                      (uint32_t)((inset_reg >>
7730                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7731                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7732                                       (uint32_t)(inset_reg & UINT32_MAX));
7733                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7734                                      (uint32_t)((inset_reg >>
7735                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7736
7737                 for (i = 0; i < num; i++) {
7738                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7739                                              mask_reg[i]);
7740                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7741                                              mask_reg[i]);
7742                 }
7743                 /*clear unused mask registers of the pctype */
7744                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7745                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7746                                              0);
7747                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7748                                              0);
7749                 }
7750                 I40E_WRITE_FLUSH(hw);
7751
7752                 /* store the default input set */
7753                 pf->hash_input_set[pctype] = input_set;
7754                 pf->fdir.input_set[pctype] = input_set;
7755         }
7756 }
7757
7758 int
7759 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7760                          struct rte_eth_input_set_conf *conf)
7761 {
7762         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7763         enum i40e_filter_pctype pctype;
7764         uint64_t input_set, inset_reg = 0;
7765         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7766         int ret, i, num;
7767
7768         if (!conf) {
7769                 PMD_DRV_LOG(ERR, "Invalid pointer");
7770                 return -EFAULT;
7771         }
7772         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7773             conf->op != RTE_ETH_INPUT_SET_ADD) {
7774                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7775                 return -EINVAL;
7776         }
7777
7778         if (!I40E_VALID_FLOW(conf->flow_type)) {
7779                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7780                 return -EINVAL;
7781         }
7782
7783         if (hw->mac.type == I40E_MAC_X722) {
7784                 /* get translated pctype value in fd pctype register */
7785                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
7786                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
7787                         conf->flow_type)));
7788         } else
7789                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7790
7791         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7792                                    conf->inset_size);
7793         if (ret) {
7794                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7795                 return -EINVAL;
7796         }
7797         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7798                                     input_set) != 0) {
7799                 PMD_DRV_LOG(ERR, "Invalid input set");
7800                 return -EINVAL;
7801         }
7802         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7803                 /* get inset value in register */
7804                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7805                 inset_reg <<= I40E_32_BIT_WIDTH;
7806                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7807                 input_set |= pf->hash_input_set[pctype];
7808         }
7809         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7810                                            I40E_INSET_MASK_NUM_REG);
7811         if (num < 0)
7812                 return -EINVAL;
7813
7814         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7815
7816         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7817                               (uint32_t)(inset_reg & UINT32_MAX));
7818         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7819                              (uint32_t)((inset_reg >>
7820                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7821
7822         for (i = 0; i < num; i++)
7823                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7824                                      mask_reg[i]);
7825         /*clear unused mask registers of the pctype */
7826         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7827                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7828                                      0);
7829         I40E_WRITE_FLUSH(hw);
7830
7831         pf->hash_input_set[pctype] = input_set;
7832         return 0;
7833 }
7834
7835 int
7836 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7837                          struct rte_eth_input_set_conf *conf)
7838 {
7839         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7840         enum i40e_filter_pctype pctype;
7841         uint64_t input_set, inset_reg = 0;
7842         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7843         int ret, i, num;
7844
7845         if (!hw || !conf) {
7846                 PMD_DRV_LOG(ERR, "Invalid pointer");
7847                 return -EFAULT;
7848         }
7849         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7850             conf->op != RTE_ETH_INPUT_SET_ADD) {
7851                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7852                 return -EINVAL;
7853         }
7854
7855         if (!I40E_VALID_FLOW(conf->flow_type)) {
7856                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7857                 return -EINVAL;
7858         }
7859
7860         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7861
7862         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7863                                    conf->inset_size);
7864         if (ret) {
7865                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7866                 return -EINVAL;
7867         }
7868         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7869                                     input_set) != 0) {
7870                 PMD_DRV_LOG(ERR, "Invalid input set");
7871                 return -EINVAL;
7872         }
7873
7874         /* get inset value in register */
7875         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7876         inset_reg <<= I40E_32_BIT_WIDTH;
7877         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7878
7879         /* Can not change the inset reg for flex payload for fdir,
7880          * it is done by writing I40E_PRTQF_FD_FLXINSET
7881          * in i40e_set_flex_mask_on_pctype.
7882          */
7883         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7884                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7885         else
7886                 input_set |= pf->fdir.input_set[pctype];
7887         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7888                                            I40E_INSET_MASK_NUM_REG);
7889         if (num < 0)
7890                 return -EINVAL;
7891
7892         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7893
7894         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7895                               (uint32_t)(inset_reg & UINT32_MAX));
7896         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7897                              (uint32_t)((inset_reg >>
7898                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7899
7900         for (i = 0; i < num; i++)
7901                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7902                                      mask_reg[i]);
7903         /*clear unused mask registers of the pctype */
7904         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7905                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7906                                      0);
7907         I40E_WRITE_FLUSH(hw);
7908
7909         pf->fdir.input_set[pctype] = input_set;
7910         return 0;
7911 }
7912
7913 static int
7914 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7915 {
7916         int ret = 0;
7917
7918         if (!hw || !info) {
7919                 PMD_DRV_LOG(ERR, "Invalid pointer");
7920                 return -EFAULT;
7921         }
7922
7923         switch (info->info_type) {
7924         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7925                 i40e_get_symmetric_hash_enable_per_port(hw,
7926                                         &(info->info.enable));
7927                 break;
7928         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7929                 ret = i40e_get_hash_filter_global_config(hw,
7930                                 &(info->info.global_conf));
7931                 break;
7932         default:
7933                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7934                                                         info->info_type);
7935                 ret = -EINVAL;
7936                 break;
7937         }
7938
7939         return ret;
7940 }
7941
7942 static int
7943 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7944 {
7945         int ret = 0;
7946
7947         if (!hw || !info) {
7948                 PMD_DRV_LOG(ERR, "Invalid pointer");
7949                 return -EFAULT;
7950         }
7951
7952         switch (info->info_type) {
7953         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7954                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7955                 break;
7956         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7957                 ret = i40e_set_hash_filter_global_config(hw,
7958                                 &(info->info.global_conf));
7959                 break;
7960         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7961                 ret = i40e_hash_filter_inset_select(hw,
7962                                                &(info->info.input_set_conf));
7963                 break;
7964
7965         default:
7966                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7967                                                         info->info_type);
7968                 ret = -EINVAL;
7969                 break;
7970         }
7971
7972         return ret;
7973 }
7974
7975 /* Operations for hash function */
7976 static int
7977 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7978                       enum rte_filter_op filter_op,
7979                       void *arg)
7980 {
7981         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7982         int ret = 0;
7983
7984         switch (filter_op) {
7985         case RTE_ETH_FILTER_NOP:
7986                 break;
7987         case RTE_ETH_FILTER_GET:
7988                 ret = i40e_hash_filter_get(hw,
7989                         (struct rte_eth_hash_filter_info *)arg);
7990                 break;
7991         case RTE_ETH_FILTER_SET:
7992                 ret = i40e_hash_filter_set(hw,
7993                         (struct rte_eth_hash_filter_info *)arg);
7994                 break;
7995         default:
7996                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7997                                                                 filter_op);
7998                 ret = -ENOTSUP;
7999                 break;
8000         }
8001
8002         return ret;
8003 }
8004
8005 /*
8006  * Configure ethertype filter, which can director packet by filtering
8007  * with mac address and ether_type or only ether_type
8008  */
8009 static int
8010 i40e_ethertype_filter_set(struct i40e_pf *pf,
8011                         struct rte_eth_ethertype_filter *filter,
8012                         bool add)
8013 {
8014         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8015         struct i40e_control_filter_stats stats;
8016         uint16_t flags = 0;
8017         int ret;
8018
8019         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8020                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8021                 return -EINVAL;
8022         }
8023         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8024                 filter->ether_type == ETHER_TYPE_IPv6) {
8025                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8026                         " control packet filter.", filter->ether_type);
8027                 return -EINVAL;
8028         }
8029         if (filter->ether_type == ETHER_TYPE_VLAN)
8030                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8031                         " not supported.");
8032
8033         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8034                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8035         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8036                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8037         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8038
8039         memset(&stats, 0, sizeof(stats));
8040         ret = i40e_aq_add_rem_control_packet_filter(hw,
8041                         filter->mac_addr.addr_bytes,
8042                         filter->ether_type, flags,
8043                         pf->main_vsi->seid,
8044                         filter->queue, add, &stats, NULL);
8045
8046         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8047                          " mac_etype_used = %u, etype_used = %u,"
8048                          " mac_etype_free = %u, etype_free = %u\n",
8049                          ret, stats.mac_etype_used, stats.etype_used,
8050                          stats.mac_etype_free, stats.etype_free);
8051         if (ret < 0)
8052                 return -ENOSYS;
8053         return 0;
8054 }
8055
8056 /*
8057  * Handle operations for ethertype filter.
8058  */
8059 static int
8060 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8061                                 enum rte_filter_op filter_op,
8062                                 void *arg)
8063 {
8064         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8065         int ret = 0;
8066
8067         if (filter_op == RTE_ETH_FILTER_NOP)
8068                 return ret;
8069
8070         if (arg == NULL) {
8071                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8072                             filter_op);
8073                 return -EINVAL;
8074         }
8075
8076         switch (filter_op) {
8077         case RTE_ETH_FILTER_ADD:
8078                 ret = i40e_ethertype_filter_set(pf,
8079                         (struct rte_eth_ethertype_filter *)arg,
8080                         TRUE);
8081                 break;
8082         case RTE_ETH_FILTER_DELETE:
8083                 ret = i40e_ethertype_filter_set(pf,
8084                         (struct rte_eth_ethertype_filter *)arg,
8085                         FALSE);
8086                 break;
8087         default:
8088                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8089                 ret = -ENOSYS;
8090                 break;
8091         }
8092         return ret;
8093 }
8094
8095 static int
8096 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8097                      enum rte_filter_type filter_type,
8098                      enum rte_filter_op filter_op,
8099                      void *arg)
8100 {
8101         int ret = 0;
8102
8103         if (dev == NULL)
8104                 return -EINVAL;
8105
8106         switch (filter_type) {
8107         case RTE_ETH_FILTER_NONE:
8108                 /* For global configuration */
8109                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8110                 break;
8111         case RTE_ETH_FILTER_HASH:
8112                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8113                 break;
8114         case RTE_ETH_FILTER_MACVLAN:
8115                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8116                 break;
8117         case RTE_ETH_FILTER_ETHERTYPE:
8118                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8119                 break;
8120         case RTE_ETH_FILTER_TUNNEL:
8121                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8122                 break;
8123         case RTE_ETH_FILTER_FDIR:
8124                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8125                 break;
8126         default:
8127                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8128                                                         filter_type);
8129                 ret = -EINVAL;
8130                 break;
8131         }
8132
8133         return ret;
8134 }
8135
8136 /*
8137  * Check and enable Extended Tag.
8138  * Enabling Extended Tag is important for 40G performance.
8139  */
8140 static void
8141 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8142 {
8143         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8144         uint32_t buf = 0;
8145         int ret;
8146
8147         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8148                                       PCI_DEV_CAP_REG);
8149         if (ret < 0) {
8150                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8151                             PCI_DEV_CAP_REG);
8152                 return;
8153         }
8154         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8155                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8156                 return;
8157         }
8158
8159         buf = 0;
8160         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8161                                       PCI_DEV_CTRL_REG);
8162         if (ret < 0) {
8163                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8164                             PCI_DEV_CTRL_REG);
8165                 return;
8166         }
8167         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8168                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8169                 return;
8170         }
8171         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8172         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8173                                        PCI_DEV_CTRL_REG);
8174         if (ret < 0) {
8175                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8176                             PCI_DEV_CTRL_REG);
8177                 return;
8178         }
8179 }
8180
8181 /*
8182  * As some registers wouldn't be reset unless a global hardware reset,
8183  * hardware initialization is needed to put those registers into an
8184  * expected initial state.
8185  */
8186 static void
8187 i40e_hw_init(struct rte_eth_dev *dev)
8188 {
8189         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8190
8191         i40e_enable_extended_tag(dev);
8192
8193         /* clear the PF Queue Filter control register */
8194         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8195
8196         /* Disable symmetric hash per port */
8197         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8198 }
8199
8200 enum i40e_filter_pctype
8201 i40e_flowtype_to_pctype(uint16_t flow_type)
8202 {
8203         static const enum i40e_filter_pctype pctype_table[] = {
8204                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8205                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8206                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8207                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8208                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8209                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8210                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8211                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8212                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8213                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8214                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8215                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8216                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8217                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8218                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8219                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8220                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8221                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8222                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8223         };
8224
8225         return pctype_table[flow_type];
8226 }
8227
8228 uint16_t
8229 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8230 {
8231         static const uint16_t flowtype_table[] = {
8232                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8233                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8234                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8235 #ifdef X722_SUPPORT
8236                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8237                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8238                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8239                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8240 #endif
8241                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8242                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8243 #ifdef X722_SUPPORT
8244                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8245                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8246 #endif
8247                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8248                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8249                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8250                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8251                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8252                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8253                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8254 #ifdef X722_SUPPORT
8255                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8256                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8257                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8258                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8259 #endif
8260                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8261                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8262 #ifdef X722_SUPPORT
8263                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8264                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8265 #endif
8266                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8267                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8268                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8269                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8270                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8271         };
8272
8273         return flowtype_table[pctype];
8274 }
8275
8276 /*
8277  * On X710, performance number is far from the expectation on recent firmware
8278  * versions; on XL710, performance number is also far from the expectation on
8279  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8280  * mode is enabled and port MAC address is equal to the packet destination MAC
8281  * address. The fix for this issue may not be integrated in the following
8282  * firmware version. So the workaround in software driver is needed. It needs
8283  * to modify the initial values of 3 internal only registers for both X710 and
8284  * XL710. Note that the values for X710 or XL710 could be different, and the
8285  * workaround can be removed when it is fixed in firmware in the future.
8286  */
8287
8288 /* For both X710 and XL710 */
8289 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8290 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8291
8292 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8293 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8294
8295 /* For X710 */
8296 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8297 /* For XL710 */
8298 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8299 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8300
8301 static int
8302 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8303 {
8304         enum i40e_status_code status;
8305         struct i40e_aq_get_phy_abilities_resp phy_ab;
8306         int ret = -ENOTSUP;
8307
8308         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8309                                               NULL);
8310
8311         if (status)
8312                 return ret;
8313
8314         return 0;
8315 }
8316
8317
8318 static void
8319 i40e_configure_registers(struct i40e_hw *hw)
8320 {
8321         static struct {
8322                 uint32_t addr;
8323                 uint64_t val;
8324         } reg_table[] = {
8325                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8326                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8327                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8328         };
8329         uint64_t reg;
8330         uint32_t i;
8331         int ret;
8332
8333         for (i = 0; i < RTE_DIM(reg_table); i++) {
8334                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8335                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8336                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8337                                 reg_table[i].val =
8338                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8339                         else /* For X710 */
8340                                 reg_table[i].val =
8341                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8342                 }
8343
8344                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8345                                                         &reg, NULL);
8346                 if (ret < 0) {
8347                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8348                                                         reg_table[i].addr);
8349                         break;
8350                 }
8351                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8352                                                 reg_table[i].addr, reg);
8353                 if (reg == reg_table[i].val)
8354                         continue;
8355
8356                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8357                                                 reg_table[i].val, NULL);
8358                 if (ret < 0) {
8359                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8360                                 "address of 0x%"PRIx32, reg_table[i].val,
8361                                                         reg_table[i].addr);
8362                         break;
8363                 }
8364                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8365                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8366         }
8367 }
8368
8369 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8370 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8371 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8372 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8373 static int
8374 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8375 {
8376         uint32_t reg;
8377         int ret;
8378
8379         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8380                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8381                 return -EINVAL;
8382         }
8383
8384         /* Configure for double VLAN RX stripping */
8385         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8386         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8387                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8388                 ret = i40e_aq_debug_write_register(hw,
8389                                                    I40E_VSI_TSR(vsi->vsi_id),
8390                                                    reg, NULL);
8391                 if (ret < 0) {
8392                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8393                                     vsi->vsi_id);
8394                         return I40E_ERR_CONFIG;
8395                 }
8396         }
8397
8398         /* Configure for double VLAN TX insertion */
8399         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8400         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8401                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8402                 ret = i40e_aq_debug_write_register(hw,
8403                                                    I40E_VSI_L2TAGSTXVALID(
8404                                                    vsi->vsi_id), reg, NULL);
8405                 if (ret < 0) {
8406                         PMD_DRV_LOG(ERR, "Failed to update "
8407                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8408                         return I40E_ERR_CONFIG;
8409                 }
8410         }
8411
8412         return 0;
8413 }
8414
8415 /**
8416  * i40e_aq_add_mirror_rule
8417  * @hw: pointer to the hardware structure
8418  * @seid: VEB seid to add mirror rule to
8419  * @dst_id: destination vsi seid
8420  * @entries: Buffer which contains the entities to be mirrored
8421  * @count: number of entities contained in the buffer
8422  * @rule_id:the rule_id of the rule to be added
8423  *
8424  * Add a mirror rule for a given veb.
8425  *
8426  **/
8427 static enum i40e_status_code
8428 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8429                         uint16_t seid, uint16_t dst_id,
8430                         uint16_t rule_type, uint16_t *entries,
8431                         uint16_t count, uint16_t *rule_id)
8432 {
8433         struct i40e_aq_desc desc;
8434         struct i40e_aqc_add_delete_mirror_rule cmd;
8435         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8436                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8437                 &desc.params.raw;
8438         uint16_t buff_len;
8439         enum i40e_status_code status;
8440
8441         i40e_fill_default_direct_cmd_desc(&desc,
8442                                           i40e_aqc_opc_add_mirror_rule);
8443         memset(&cmd, 0, sizeof(cmd));
8444
8445         buff_len = sizeof(uint16_t) * count;
8446         desc.datalen = rte_cpu_to_le_16(buff_len);
8447         if (buff_len > 0)
8448                 desc.flags |= rte_cpu_to_le_16(
8449                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8450         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8451                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8452         cmd.num_entries = rte_cpu_to_le_16(count);
8453         cmd.seid = rte_cpu_to_le_16(seid);
8454         cmd.destination = rte_cpu_to_le_16(dst_id);
8455
8456         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8457         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8458         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8459                          "rule_id = %u"
8460                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8461                          hw->aq.asq_last_status, resp->rule_id,
8462                          resp->mirror_rules_used, resp->mirror_rules_free);
8463         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8464
8465         return status;
8466 }
8467
8468 /**
8469  * i40e_aq_del_mirror_rule
8470  * @hw: pointer to the hardware structure
8471  * @seid: VEB seid to add mirror rule to
8472  * @entries: Buffer which contains the entities to be mirrored
8473  * @count: number of entities contained in the buffer
8474  * @rule_id:the rule_id of the rule to be delete
8475  *
8476  * Delete a mirror rule for a given veb.
8477  *
8478  **/
8479 static enum i40e_status_code
8480 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8481                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8482                 uint16_t count, uint16_t rule_id)
8483 {
8484         struct i40e_aq_desc desc;
8485         struct i40e_aqc_add_delete_mirror_rule cmd;
8486         uint16_t buff_len = 0;
8487         enum i40e_status_code status;
8488         void *buff = NULL;
8489
8490         i40e_fill_default_direct_cmd_desc(&desc,
8491                                           i40e_aqc_opc_delete_mirror_rule);
8492         memset(&cmd, 0, sizeof(cmd));
8493         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8494                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8495                                                           I40E_AQ_FLAG_RD));
8496                 cmd.num_entries = count;
8497                 buff_len = sizeof(uint16_t) * count;
8498                 desc.datalen = rte_cpu_to_le_16(buff_len);
8499                 buff = (void *)entries;
8500         } else
8501                 /* rule id is filled in destination field for deleting mirror rule */
8502                 cmd.destination = rte_cpu_to_le_16(rule_id);
8503
8504         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8505                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8506         cmd.seid = rte_cpu_to_le_16(seid);
8507
8508         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8509         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8510
8511         return status;
8512 }
8513
8514 /**
8515  * i40e_mirror_rule_set
8516  * @dev: pointer to the hardware structure
8517  * @mirror_conf: mirror rule info
8518  * @sw_id: mirror rule's sw_id
8519  * @on: enable/disable
8520  *
8521  * set a mirror rule.
8522  *
8523  **/
8524 static int
8525 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8526                         struct rte_eth_mirror_conf *mirror_conf,
8527                         uint8_t sw_id, uint8_t on)
8528 {
8529         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8530         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8531         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8532         struct i40e_mirror_rule *parent = NULL;
8533         uint16_t seid, dst_seid, rule_id;
8534         uint16_t i, j = 0;
8535         int ret;
8536
8537         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8538
8539         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8540                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8541                         " without veb or vfs.");
8542                 return -ENOSYS;
8543         }
8544         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8545                 PMD_DRV_LOG(ERR, "mirror table is full.");
8546                 return -ENOSPC;
8547         }
8548         if (mirror_conf->dst_pool > pf->vf_num) {
8549                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8550                                  mirror_conf->dst_pool);
8551                 return -EINVAL;
8552         }
8553
8554         seid = pf->main_vsi->veb->seid;
8555
8556         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8557                 if (sw_id <= it->index) {
8558                         mirr_rule = it;
8559                         break;
8560                 }
8561                 parent = it;
8562         }
8563         if (mirr_rule && sw_id == mirr_rule->index) {
8564                 if (on) {
8565                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8566                         return -EEXIST;
8567                 } else {
8568                         ret = i40e_aq_del_mirror_rule(hw, seid,
8569                                         mirr_rule->rule_type,
8570                                         mirr_rule->entries,
8571                                         mirr_rule->num_entries, mirr_rule->id);
8572                         if (ret < 0) {
8573                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8574                                                    " ret = %d, aq_err = %d.",
8575                                                    ret, hw->aq.asq_last_status);
8576                                 return -ENOSYS;
8577                         }
8578                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8579                         rte_free(mirr_rule);
8580                         pf->nb_mirror_rule--;
8581                         return 0;
8582                 }
8583         } else if (!on) {
8584                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8585                 return -ENOENT;
8586         }
8587
8588         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8589                                 sizeof(struct i40e_mirror_rule) , 0);
8590         if (!mirr_rule) {
8591                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8592                 return I40E_ERR_NO_MEMORY;
8593         }
8594         switch (mirror_conf->rule_type) {
8595         case ETH_MIRROR_VLAN:
8596                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8597                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8598                                 mirr_rule->entries[j] =
8599                                         mirror_conf->vlan.vlan_id[i];
8600                                 j++;
8601                         }
8602                 }
8603                 if (j == 0) {
8604                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8605                         rte_free(mirr_rule);
8606                         return -EINVAL;
8607                 }
8608                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8609                 break;
8610         case ETH_MIRROR_VIRTUAL_POOL_UP:
8611         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8612                 /* check if the specified pool bit is out of range */
8613                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8614                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8615                         rte_free(mirr_rule);
8616                         return -EINVAL;
8617                 }
8618                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8619                         if (mirror_conf->pool_mask & (1ULL << i)) {
8620                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8621                                 j++;
8622                         }
8623                 }
8624                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8625                         /* add pf vsi to entries */
8626                         mirr_rule->entries[j] = pf->main_vsi_seid;
8627                         j++;
8628                 }
8629                 if (j == 0) {
8630                         PMD_DRV_LOG(ERR, "pool is not specified.");
8631                         rte_free(mirr_rule);
8632                         return -EINVAL;
8633                 }
8634                 /* egress and ingress in aq commands means from switch but not port */
8635                 mirr_rule->rule_type =
8636                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8637                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8638                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8639                 break;
8640         case ETH_MIRROR_UPLINK_PORT:
8641                 /* egress and ingress in aq commands means from switch but not port*/
8642                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8643                 break;
8644         case ETH_MIRROR_DOWNLINK_PORT:
8645                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8646                 break;
8647         default:
8648                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8649                         mirror_conf->rule_type);
8650                 rte_free(mirr_rule);
8651                 return -EINVAL;
8652         }
8653
8654         /* If the dst_pool is equal to vf_num, consider it as PF */
8655         if (mirror_conf->dst_pool == pf->vf_num)
8656                 dst_seid = pf->main_vsi_seid;
8657         else
8658                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8659
8660         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8661                                       mirr_rule->rule_type, mirr_rule->entries,
8662                                       j, &rule_id);
8663         if (ret < 0) {
8664                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8665                                    " ret = %d, aq_err = %d.",
8666                                    ret, hw->aq.asq_last_status);
8667                 rte_free(mirr_rule);
8668                 return -ENOSYS;
8669         }
8670
8671         mirr_rule->index = sw_id;
8672         mirr_rule->num_entries = j;
8673         mirr_rule->id = rule_id;
8674         mirr_rule->dst_vsi_seid = dst_seid;
8675
8676         if (parent)
8677                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8678         else
8679                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8680
8681         pf->nb_mirror_rule++;
8682         return 0;
8683 }
8684
8685 /**
8686  * i40e_mirror_rule_reset
8687  * @dev: pointer to the device
8688  * @sw_id: mirror rule's sw_id
8689  *
8690  * reset a mirror rule.
8691  *
8692  **/
8693 static int
8694 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8695 {
8696         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8697         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8698         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8699         uint16_t seid;
8700         int ret;
8701
8702         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8703
8704         seid = pf->main_vsi->veb->seid;
8705
8706         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8707                 if (sw_id == it->index) {
8708                         mirr_rule = it;
8709                         break;
8710                 }
8711         }
8712         if (mirr_rule) {
8713                 ret = i40e_aq_del_mirror_rule(hw, seid,
8714                                 mirr_rule->rule_type,
8715                                 mirr_rule->entries,
8716                                 mirr_rule->num_entries, mirr_rule->id);
8717                 if (ret < 0) {
8718                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8719                                            " status = %d, aq_err = %d.",
8720                                            ret, hw->aq.asq_last_status);
8721                         return -ENOSYS;
8722                 }
8723                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8724                 rte_free(mirr_rule);
8725                 pf->nb_mirror_rule--;
8726         } else {
8727                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8728                 return -ENOENT;
8729         }
8730         return 0;
8731 }
8732
8733 static uint64_t
8734 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8735 {
8736         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8737         uint64_t systim_cycles;
8738
8739         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8740         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8741                         << 32;
8742
8743         return systim_cycles;
8744 }
8745
8746 static uint64_t
8747 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8748 {
8749         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8750         uint64_t rx_tstamp;
8751
8752         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8753         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8754                         << 32;
8755
8756         return rx_tstamp;
8757 }
8758
8759 static uint64_t
8760 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8761 {
8762         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8763         uint64_t tx_tstamp;
8764
8765         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8766         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8767                         << 32;
8768
8769         return tx_tstamp;
8770 }
8771
8772 static void
8773 i40e_start_timecounters(struct rte_eth_dev *dev)
8774 {
8775         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8776         struct i40e_adapter *adapter =
8777                         (struct i40e_adapter *)dev->data->dev_private;
8778         struct rte_eth_link link;
8779         uint32_t tsync_inc_l;
8780         uint32_t tsync_inc_h;
8781
8782         /* Get current link speed. */
8783         memset(&link, 0, sizeof(link));
8784         i40e_dev_link_update(dev, 1);
8785         rte_i40e_dev_atomic_read_link_status(dev, &link);
8786
8787         switch (link.link_speed) {
8788         case ETH_SPEED_NUM_40G:
8789                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8790                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8791                 break;
8792         case ETH_SPEED_NUM_10G:
8793                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8794                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8795                 break;
8796         case ETH_SPEED_NUM_1G:
8797                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8798                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8799                 break;
8800         default:
8801                 tsync_inc_l = 0x0;
8802                 tsync_inc_h = 0x0;
8803         }
8804
8805         /* Set the timesync increment value. */
8806         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8807         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8808
8809         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8810         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8811         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8812
8813         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8814         adapter->systime_tc.cc_shift = 0;
8815         adapter->systime_tc.nsec_mask = 0;
8816
8817         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8818         adapter->rx_tstamp_tc.cc_shift = 0;
8819         adapter->rx_tstamp_tc.nsec_mask = 0;
8820
8821         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8822         adapter->tx_tstamp_tc.cc_shift = 0;
8823         adapter->tx_tstamp_tc.nsec_mask = 0;
8824 }
8825
8826 static int
8827 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8828 {
8829         struct i40e_adapter *adapter =
8830                         (struct i40e_adapter *)dev->data->dev_private;
8831
8832         adapter->systime_tc.nsec += delta;
8833         adapter->rx_tstamp_tc.nsec += delta;
8834         adapter->tx_tstamp_tc.nsec += delta;
8835
8836         return 0;
8837 }
8838
8839 static int
8840 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8841 {
8842         uint64_t ns;
8843         struct i40e_adapter *adapter =
8844                         (struct i40e_adapter *)dev->data->dev_private;
8845
8846         ns = rte_timespec_to_ns(ts);
8847
8848         /* Set the timecounters to a new value. */
8849         adapter->systime_tc.nsec = ns;
8850         adapter->rx_tstamp_tc.nsec = ns;
8851         adapter->tx_tstamp_tc.nsec = ns;
8852
8853         return 0;
8854 }
8855
8856 static int
8857 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8858 {
8859         uint64_t ns, systime_cycles;
8860         struct i40e_adapter *adapter =
8861                         (struct i40e_adapter *)dev->data->dev_private;
8862
8863         systime_cycles = i40e_read_systime_cyclecounter(dev);
8864         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8865         *ts = rte_ns_to_timespec(ns);
8866
8867         return 0;
8868 }
8869
8870 static int
8871 i40e_timesync_enable(struct rte_eth_dev *dev)
8872 {
8873         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8874         uint32_t tsync_ctl_l;
8875         uint32_t tsync_ctl_h;
8876
8877         /* Stop the timesync system time. */
8878         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8879         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8880         /* Reset the timesync system time value. */
8881         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8882         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8883
8884         i40e_start_timecounters(dev);
8885
8886         /* Clear timesync registers. */
8887         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8888         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8889         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8890         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8891         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8892         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8893
8894         /* Enable timestamping of PTP packets. */
8895         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8896         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8897
8898         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8899         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8900         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8901
8902         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8903         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8904
8905         return 0;
8906 }
8907
8908 static int
8909 i40e_timesync_disable(struct rte_eth_dev *dev)
8910 {
8911         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8912         uint32_t tsync_ctl_l;
8913         uint32_t tsync_ctl_h;
8914
8915         /* Disable timestamping of transmitted PTP packets. */
8916         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8917         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8918
8919         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8920         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8921
8922         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8923         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8924
8925         /* Reset the timesync increment value. */
8926         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8927         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8928
8929         return 0;
8930 }
8931
8932 static int
8933 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8934                                 struct timespec *timestamp, uint32_t flags)
8935 {
8936         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8937         struct i40e_adapter *adapter =
8938                 (struct i40e_adapter *)dev->data->dev_private;
8939
8940         uint32_t sync_status;
8941         uint32_t index = flags & 0x03;
8942         uint64_t rx_tstamp_cycles;
8943         uint64_t ns;
8944
8945         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8946         if ((sync_status & (1 << index)) == 0)
8947                 return -EINVAL;
8948
8949         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8950         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8951         *timestamp = rte_ns_to_timespec(ns);
8952
8953         return 0;
8954 }
8955
8956 static int
8957 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8958                                 struct timespec *timestamp)
8959 {
8960         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8961         struct i40e_adapter *adapter =
8962                 (struct i40e_adapter *)dev->data->dev_private;
8963
8964         uint32_t sync_status;
8965         uint64_t tx_tstamp_cycles;
8966         uint64_t ns;
8967
8968         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8969         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8970                 return -EINVAL;
8971
8972         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8973         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8974         *timestamp = rte_ns_to_timespec(ns);
8975
8976         return 0;
8977 }
8978
8979 /*
8980  * i40e_parse_dcb_configure - parse dcb configure from user
8981  * @dev: the device being configured
8982  * @dcb_cfg: pointer of the result of parse
8983  * @*tc_map: bit map of enabled traffic classes
8984  *
8985  * Returns 0 on success, negative value on failure
8986  */
8987 static int
8988 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8989                          struct i40e_dcbx_config *dcb_cfg,
8990                          uint8_t *tc_map)
8991 {
8992         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8993         uint8_t i, tc_bw, bw_lf;
8994
8995         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8996
8997         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8998         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8999                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9000                 return -EINVAL;
9001         }
9002
9003         /* assume each tc has the same bw */
9004         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9005         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9006                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9007         /* to ensure the sum of tcbw is equal to 100 */
9008         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9009         for (i = 0; i < bw_lf; i++)
9010                 dcb_cfg->etscfg.tcbwtable[i]++;
9011
9012         /* assume each tc has the same Transmission Selection Algorithm */
9013         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9014                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9015
9016         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9017                 dcb_cfg->etscfg.prioritytable[i] =
9018                                 dcb_rx_conf->dcb_tc[i];
9019
9020         /* FW needs one App to configure HW */
9021         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9022         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9023         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9024         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9025
9026         if (dcb_rx_conf->nb_tcs == 0)
9027                 *tc_map = 1; /* tc0 only */
9028         else
9029                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9030
9031         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9032                 dcb_cfg->pfc.willing = 0;
9033                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9034                 dcb_cfg->pfc.pfcenable = *tc_map;
9035         }
9036         return 0;
9037 }
9038
9039
9040 static enum i40e_status_code
9041 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9042                               struct i40e_aqc_vsi_properties_data *info,
9043                               uint8_t enabled_tcmap)
9044 {
9045         enum i40e_status_code ret;
9046         int i, total_tc = 0;
9047         uint16_t qpnum_per_tc, bsf, qp_idx;
9048         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9049         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9050         uint16_t used_queues;
9051
9052         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9053         if (ret != I40E_SUCCESS)
9054                 return ret;
9055
9056         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9057                 if (enabled_tcmap & (1 << i))
9058                         total_tc++;
9059         }
9060         if (total_tc == 0)
9061                 total_tc = 1;
9062         vsi->enabled_tc = enabled_tcmap;
9063
9064         /* different VSI has different queues assigned */
9065         if (vsi->type == I40E_VSI_MAIN)
9066                 used_queues = dev_data->nb_rx_queues -
9067                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9068         else if (vsi->type == I40E_VSI_VMDQ2)
9069                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9070         else {
9071                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9072                 return I40E_ERR_NO_AVAILABLE_VSI;
9073         }
9074
9075         qpnum_per_tc = used_queues / total_tc;
9076         /* Number of queues per enabled TC */
9077         if (qpnum_per_tc == 0) {
9078                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9079                 return I40E_ERR_INVALID_QP_ID;
9080         }
9081         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9082                                 I40E_MAX_Q_PER_TC);
9083         bsf = rte_bsf32(qpnum_per_tc);
9084
9085         /**
9086          * Configure TC and queue mapping parameters, for enabled TC,
9087          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9088          * default queue will serve it.
9089          */
9090         qp_idx = 0;
9091         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9092                 if (vsi->enabled_tc & (1 << i)) {
9093                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9094                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9095                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9096                         qp_idx += qpnum_per_tc;
9097                 } else
9098                         info->tc_mapping[i] = 0;
9099         }
9100
9101         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9102         if (vsi->type == I40E_VSI_SRIOV) {
9103                 info->mapping_flags |=
9104                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9105                 for (i = 0; i < vsi->nb_qps; i++)
9106                         info->queue_mapping[i] =
9107                                 rte_cpu_to_le_16(vsi->base_queue + i);
9108         } else {
9109                 info->mapping_flags |=
9110                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9111                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9112         }
9113         info->valid_sections |=
9114                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9115
9116         return I40E_SUCCESS;
9117 }
9118
9119 /*
9120  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9121  * @veb: VEB to be configured
9122  * @tc_map: enabled TC bitmap
9123  *
9124  * Returns 0 on success, negative value on failure
9125  */
9126 static enum i40e_status_code
9127 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9128 {
9129         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9130         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9131         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9132         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9133         enum i40e_status_code ret = I40E_SUCCESS;
9134         int i;
9135         uint32_t bw_max;
9136
9137         /* Check if enabled_tc is same as existing or new TCs */
9138         if (veb->enabled_tc == tc_map)
9139                 return ret;
9140
9141         /* configure tc bandwidth */
9142         memset(&veb_bw, 0, sizeof(veb_bw));
9143         veb_bw.tc_valid_bits = tc_map;
9144         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9145         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9146                 if (tc_map & BIT_ULL(i))
9147                         veb_bw.tc_bw_share_credits[i] = 1;
9148         }
9149         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9150                                                    &veb_bw, NULL);
9151         if (ret) {
9152                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9153                                   " per TC failed = %d",
9154                                   hw->aq.asq_last_status);
9155                 return ret;
9156         }
9157
9158         memset(&ets_query, 0, sizeof(ets_query));
9159         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9160                                                    &ets_query, NULL);
9161         if (ret != I40E_SUCCESS) {
9162                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9163                                  " configuration %u", hw->aq.asq_last_status);
9164                 return ret;
9165         }
9166         memset(&bw_query, 0, sizeof(bw_query));
9167         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9168                                                   &bw_query, NULL);
9169         if (ret != I40E_SUCCESS) {
9170                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9171                                  " configuration %u", hw->aq.asq_last_status);
9172                 return ret;
9173         }
9174
9175         /* store and print out BW info */
9176         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9177         veb->bw_info.bw_max = ets_query.tc_bw_max;
9178         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9179         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9180         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9181                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9182                      I40E_16_BIT_WIDTH);
9183         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9184                 veb->bw_info.bw_ets_share_credits[i] =
9185                                 bw_query.tc_bw_share_credits[i];
9186                 veb->bw_info.bw_ets_credits[i] =
9187                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9188                 /* 4 bits per TC, 4th bit is reserved */
9189                 veb->bw_info.bw_ets_max[i] =
9190                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9191                                   RTE_LEN2MASK(3, uint8_t));
9192                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9193                             veb->bw_info.bw_ets_share_credits[i]);
9194                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9195                             veb->bw_info.bw_ets_credits[i]);
9196                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9197                             veb->bw_info.bw_ets_max[i]);
9198         }
9199
9200         veb->enabled_tc = tc_map;
9201
9202         return ret;
9203 }
9204
9205
9206 /*
9207  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9208  * @vsi: VSI to be configured
9209  * @tc_map: enabled TC bitmap
9210  *
9211  * Returns 0 on success, negative value on failure
9212  */
9213 static enum i40e_status_code
9214 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9215 {
9216         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9217         struct i40e_vsi_context ctxt;
9218         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9219         enum i40e_status_code ret = I40E_SUCCESS;
9220         int i;
9221
9222         /* Check if enabled_tc is same as existing or new TCs */
9223         if (vsi->enabled_tc == tc_map)
9224                 return ret;
9225
9226         /* configure tc bandwidth */
9227         memset(&bw_data, 0, sizeof(bw_data));
9228         bw_data.tc_valid_bits = tc_map;
9229         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9230         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9231                 if (tc_map & BIT_ULL(i))
9232                         bw_data.tc_bw_credits[i] = 1;
9233         }
9234         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9235         if (ret) {
9236                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9237                         " per TC failed = %d",
9238                         hw->aq.asq_last_status);
9239                 goto out;
9240         }
9241         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9242                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9243
9244         /* Update Queue Pairs Mapping for currently enabled UPs */
9245         ctxt.seid = vsi->seid;
9246         ctxt.pf_num = hw->pf_id;
9247         ctxt.vf_num = 0;
9248         ctxt.uplink_seid = vsi->uplink_seid;
9249         ctxt.info = vsi->info;
9250         i40e_get_cap(hw);
9251         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9252         if (ret)
9253                 goto out;
9254
9255         /* Update the VSI after updating the VSI queue-mapping information */
9256         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9257         if (ret) {
9258                 PMD_INIT_LOG(ERR, "Failed to configure "
9259                             "TC queue mapping = %d",
9260                             hw->aq.asq_last_status);
9261                 goto out;
9262         }
9263         /* update the local VSI info with updated queue map */
9264         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9265                                         sizeof(vsi->info.tc_mapping));
9266         (void)rte_memcpy(&vsi->info.queue_mapping,
9267                         &ctxt.info.queue_mapping,
9268                 sizeof(vsi->info.queue_mapping));
9269         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9270         vsi->info.valid_sections = 0;
9271
9272         /* query and update current VSI BW information */
9273         ret = i40e_vsi_get_bw_config(vsi);
9274         if (ret) {
9275                 PMD_INIT_LOG(ERR,
9276                          "Failed updating vsi bw info, err %s aq_err %s",
9277                          i40e_stat_str(hw, ret),
9278                          i40e_aq_str(hw, hw->aq.asq_last_status));
9279                 goto out;
9280         }
9281
9282         vsi->enabled_tc = tc_map;
9283
9284 out:
9285         return ret;
9286 }
9287
9288 /*
9289  * i40e_dcb_hw_configure - program the dcb setting to hw
9290  * @pf: pf the configuration is taken on
9291  * @new_cfg: new configuration
9292  * @tc_map: enabled TC bitmap
9293  *
9294  * Returns 0 on success, negative value on failure
9295  */
9296 static enum i40e_status_code
9297 i40e_dcb_hw_configure(struct i40e_pf *pf,
9298                       struct i40e_dcbx_config *new_cfg,
9299                       uint8_t tc_map)
9300 {
9301         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9302         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9303         struct i40e_vsi *main_vsi = pf->main_vsi;
9304         struct i40e_vsi_list *vsi_list;
9305         enum i40e_status_code ret;
9306         int i;
9307         uint32_t val;
9308
9309         /* Use the FW API if FW > v4.4*/
9310         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9311               (hw->aq.fw_maj_ver >= 5))) {
9312                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9313                                   " to configure DCB");
9314                 return I40E_ERR_FIRMWARE_API_VERSION;
9315         }
9316
9317         /* Check if need reconfiguration */
9318         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9319                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9320                 return I40E_SUCCESS;
9321         }
9322
9323         /* Copy the new config to the current config */
9324         *old_cfg = *new_cfg;
9325         old_cfg->etsrec = old_cfg->etscfg;
9326         ret = i40e_set_dcb_config(hw);
9327         if (ret) {
9328                 PMD_INIT_LOG(ERR,
9329                          "Set DCB Config failed, err %s aq_err %s\n",
9330                          i40e_stat_str(hw, ret),
9331                          i40e_aq_str(hw, hw->aq.asq_last_status));
9332                 return ret;
9333         }
9334         /* set receive Arbiter to RR mode and ETS scheme by default */
9335         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9336                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9337                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9338                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9339                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9340                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9341                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9342                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9343                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9344                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9345                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9346                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9347                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9348         }
9349         /* get local mib to check whether it is configured correctly */
9350         /* IEEE mode */
9351         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9352         /* Get Local DCB Config */
9353         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9354                                      &hw->local_dcbx_config);
9355
9356         /* if Veb is created, need to update TC of it at first */
9357         if (main_vsi->veb) {
9358                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9359                 if (ret)
9360                         PMD_INIT_LOG(WARNING,
9361                                  "Failed configuring TC for VEB seid=%d\n",
9362                                  main_vsi->veb->seid);
9363         }
9364         /* Update each VSI */
9365         i40e_vsi_config_tc(main_vsi, tc_map);
9366         if (main_vsi->veb) {
9367                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9368                         /* Beside main VSI and VMDQ VSIs, only enable default
9369                          * TC for other VSIs
9370                          */
9371                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9372                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9373                                                          tc_map);
9374                         else
9375                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9376                                                          I40E_DEFAULT_TCMAP);
9377                         if (ret)
9378                                 PMD_INIT_LOG(WARNING,
9379                                          "Failed configuring TC for VSI seid=%d\n",
9380                                          vsi_list->vsi->seid);
9381                         /* continue */
9382                 }
9383         }
9384         return I40E_SUCCESS;
9385 }
9386
9387 /*
9388  * i40e_dcb_init_configure - initial dcb config
9389  * @dev: device being configured
9390  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9391  *
9392  * Returns 0 on success, negative value on failure
9393  */
9394 static int
9395 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9396 {
9397         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9398         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9399         int ret = 0;
9400
9401         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9402                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9403                 return -ENOTSUP;
9404         }
9405
9406         /* DCB initialization:
9407          * Update DCB configuration from the Firmware and configure
9408          * LLDP MIB change event.
9409          */
9410         if (sw_dcb == TRUE) {
9411                 ret = i40e_init_dcb(hw);
9412                 /* If lldp agent is stopped, the return value from
9413                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9414                  * adminq status. Otherwise, it should return success.
9415                  */
9416                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9417                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9418                         memset(&hw->local_dcbx_config, 0,
9419                                 sizeof(struct i40e_dcbx_config));
9420                         /* set dcb default configuration */
9421                         hw->local_dcbx_config.etscfg.willing = 0;
9422                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9423                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9424                         hw->local_dcbx_config.etscfg.tsatable[0] =
9425                                                 I40E_IEEE_TSA_ETS;
9426                         hw->local_dcbx_config.etsrec =
9427                                 hw->local_dcbx_config.etscfg;
9428                         hw->local_dcbx_config.pfc.willing = 0;
9429                         hw->local_dcbx_config.pfc.pfccap =
9430                                                 I40E_MAX_TRAFFIC_CLASS;
9431                         /* FW needs one App to configure HW */
9432                         hw->local_dcbx_config.numapps = 1;
9433                         hw->local_dcbx_config.app[0].selector =
9434                                                 I40E_APP_SEL_ETHTYPE;
9435                         hw->local_dcbx_config.app[0].priority = 3;
9436                         hw->local_dcbx_config.app[0].protocolid =
9437                                                 I40E_APP_PROTOID_FCOE;
9438                         ret = i40e_set_dcb_config(hw);
9439                         if (ret) {
9440                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9441                                         " err = %d, aq_err = %d.", ret,
9442                                           hw->aq.asq_last_status);
9443                                 return -ENOSYS;
9444                         }
9445                 } else {
9446                         PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9447                                           " err = %d, aq_err = %d.", ret,
9448                                           hw->aq.asq_last_status);
9449                         return -ENOTSUP;
9450                 }
9451         } else {
9452                 ret = i40e_aq_start_lldp(hw, NULL);
9453                 if (ret != I40E_SUCCESS)
9454                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9455
9456                 ret = i40e_init_dcb(hw);
9457                 if (!ret) {
9458                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9459                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9460                                                   " DCBX offload.");
9461                                 return -ENOTSUP;
9462                         }
9463                 } else {
9464                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9465                                           " aq_err = %d.", ret,
9466                                           hw->aq.asq_last_status);
9467                         return -ENOTSUP;
9468                 }
9469         }
9470         return 0;
9471 }
9472
9473 /*
9474  * i40e_dcb_setup - setup dcb related config
9475  * @dev: device being configured
9476  *
9477  * Returns 0 on success, negative value on failure
9478  */
9479 static int
9480 i40e_dcb_setup(struct rte_eth_dev *dev)
9481 {
9482         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9483         struct i40e_dcbx_config dcb_cfg;
9484         uint8_t tc_map = 0;
9485         int ret = 0;
9486
9487         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9488                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9489                 return -ENOTSUP;
9490         }
9491
9492         if (pf->vf_num != 0)
9493                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9494
9495         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9496         if (ret) {
9497                 PMD_INIT_LOG(ERR, "invalid dcb config");
9498                 return -EINVAL;
9499         }
9500         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9501         if (ret) {
9502                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9503                 return -ENOSYS;
9504         }
9505
9506         return 0;
9507 }
9508
9509 static int
9510 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9511                       struct rte_eth_dcb_info *dcb_info)
9512 {
9513         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9514         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9515         struct i40e_vsi *vsi = pf->main_vsi;
9516         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9517         uint16_t bsf, tc_mapping;
9518         int i, j = 0;
9519
9520         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9521                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9522         else
9523                 dcb_info->nb_tcs = 1;
9524         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9525                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9526         for (i = 0; i < dcb_info->nb_tcs; i++)
9527                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9528
9529         /* get queue mapping if vmdq is disabled */
9530         if (!pf->nb_cfg_vmdq_vsi) {
9531                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9532                         if (!(vsi->enabled_tc & (1 << i)))
9533                                 continue;
9534                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9535                         dcb_info->tc_queue.tc_rxq[j][i].base =
9536                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9537                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9538                         dcb_info->tc_queue.tc_txq[j][i].base =
9539                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9540                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9541                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9542                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9543                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9544                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9545                 }
9546                 return 0;
9547         }
9548
9549         /* get queue mapping if vmdq is enabled */
9550         do {
9551                 vsi = pf->vmdq[j].vsi;
9552                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9553                         if (!(vsi->enabled_tc & (1 << i)))
9554                                 continue;
9555                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9556                         dcb_info->tc_queue.tc_rxq[j][i].base =
9557                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9558                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9559                         dcb_info->tc_queue.tc_txq[j][i].base =
9560                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9561                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9562                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9563                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9564                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9565                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9566                 }
9567                 j++;
9568         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9569         return 0;
9570 }
9571
9572 static int
9573 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9574 {
9575         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9576         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
9577         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9578         uint16_t interval =
9579                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9580         uint16_t msix_intr;
9581
9582         msix_intr = intr_handle->intr_vec[queue_id];
9583         if (msix_intr == I40E_MISC_VEC_ID)
9584                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9585                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9586                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9587                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9588                                (interval <<
9589                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9590         else
9591                 I40E_WRITE_REG(hw,
9592                                I40E_PFINT_DYN_CTLN(msix_intr -
9593                                                    I40E_RX_VEC_START),
9594                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9595                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9596                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9597                                (interval <<
9598                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9599
9600         I40E_WRITE_FLUSH(hw);
9601         rte_intr_enable(&pci_dev->intr_handle);
9602
9603         return 0;
9604 }
9605
9606 static int
9607 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9608 {
9609         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9610         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
9611         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9612         uint16_t msix_intr;
9613
9614         msix_intr = intr_handle->intr_vec[queue_id];
9615         if (msix_intr == I40E_MISC_VEC_ID)
9616                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9617         else
9618                 I40E_WRITE_REG(hw,
9619                                I40E_PFINT_DYN_CTLN(msix_intr -
9620                                                    I40E_RX_VEC_START),
9621                                0);
9622         I40E_WRITE_FLUSH(hw);
9623
9624         return 0;
9625 }
9626
9627 static int i40e_get_regs(struct rte_eth_dev *dev,
9628                          struct rte_dev_reg_info *regs)
9629 {
9630         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9631         uint32_t *ptr_data = regs->data;
9632         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9633         const struct i40e_reg_info *reg_info;
9634
9635         if (ptr_data == NULL) {
9636                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9637                 regs->width = sizeof(uint32_t);
9638                 return 0;
9639         }
9640
9641         /* The first few registers have to be read using AQ operations */
9642         reg_idx = 0;
9643         while (i40e_regs_adminq[reg_idx].name) {
9644                 reg_info = &i40e_regs_adminq[reg_idx++];
9645                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9646                         for (arr_idx2 = 0;
9647                                         arr_idx2 <= reg_info->count2;
9648                                         arr_idx2++) {
9649                                 reg_offset = arr_idx * reg_info->stride1 +
9650                                         arr_idx2 * reg_info->stride2;
9651                                 reg_offset += reg_info->base_addr;
9652                                 ptr_data[reg_offset >> 2] =
9653                                         i40e_read_rx_ctl(hw, reg_offset);
9654                         }
9655         }
9656
9657         /* The remaining registers can be read using primitives */
9658         reg_idx = 0;
9659         while (i40e_regs_others[reg_idx].name) {
9660                 reg_info = &i40e_regs_others[reg_idx++];
9661                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9662                         for (arr_idx2 = 0;
9663                                         arr_idx2 <= reg_info->count2;
9664                                         arr_idx2++) {
9665                                 reg_offset = arr_idx * reg_info->stride1 +
9666                                         arr_idx2 * reg_info->stride2;
9667                                 reg_offset += reg_info->base_addr;
9668                                 ptr_data[reg_offset >> 2] =
9669                                         I40E_READ_REG(hw, reg_offset);
9670                         }
9671         }
9672
9673         return 0;
9674 }
9675
9676 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9677 {
9678         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9679
9680         /* Convert word count to byte count */
9681         return hw->nvm.sr_size << 1;
9682 }
9683
9684 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9685                            struct rte_dev_eeprom_info *eeprom)
9686 {
9687         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9688         uint16_t *data = eeprom->data;
9689         uint16_t offset, length, cnt_words;
9690         int ret_code;
9691
9692         offset = eeprom->offset >> 1;
9693         length = eeprom->length >> 1;
9694         cnt_words = length;
9695
9696         if (offset > hw->nvm.sr_size ||
9697                 offset + length > hw->nvm.sr_size) {
9698                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9699                 return -EINVAL;
9700         }
9701
9702         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9703
9704         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9705         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9706                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9707                 return -EIO;
9708         }
9709
9710         return 0;
9711 }
9712
9713 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9714                                       struct ether_addr *mac_addr)
9715 {
9716         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9717
9718         if (!is_valid_assigned_ether_addr(mac_addr)) {
9719                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9720                 return;
9721         }
9722
9723         /* Flags: 0x3 updates port address */
9724         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9725 }
9726
9727 static int
9728 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9729 {
9730         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9731         struct rte_eth_dev_data *dev_data = pf->dev_data;
9732         uint32_t frame_size = mtu + ETHER_HDR_LEN
9733                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9734         int ret = 0;
9735
9736         /* check if mtu is within the allowed range */
9737         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9738                 return -EINVAL;
9739
9740         /* mtu setting is forbidden if port is start */
9741         if (dev_data->dev_started) {
9742                 PMD_DRV_LOG(ERR,
9743                             "port %d must be stopped before configuration\n",
9744                             dev_data->port_id);
9745                 return -EBUSY;
9746         }
9747
9748         if (frame_size > ETHER_MAX_LEN)
9749                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9750         else
9751                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9752
9753         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9754
9755         return ret;
9756 }