drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68 #include "rte_pmd_i40e.h"
  69
  70 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  71 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  72
  73 #define I40E_CLEAR_PXE_WAIT_MS     200
  74
  75 /* Maximun number of capability elements */
  76 #define I40E_MAX_CAP_ELE_NUM       128
  77
  78 /* Wait count and inteval */
  79 #define I40E_CHK_Q_ENA_COUNT       1000
  80 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  81
  82 /* Maximun number of VSI */
  83 #define I40E_MAX_NUM_VSIS          (384UL)
  84
  85 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  86
  87 /* Flow control default timer */
  88 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  89
  90 /* Flow control default high water */
  91 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  92
  93 /* Flow control default low water */
  94 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  95
  96 /* Flow control enable fwd bit */
  97 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  98
  99 /* Receive Packet Buffer size */
 100 #define I40E_RXPBSIZE (968 * 1024)
 101
 102 /* Kilobytes shift */
 103 #define I40E_KILOSHIFT 10
 104
 105 /* Receive Average Packet Size in Byte*/
 106 #define I40E_PACKET_AVERAGE_SIZE 128
 107
 108 /* Mask of PF interrupt causes */
 109 #define I40E_PFINT_ICR0_ENA_MASK ( \
 110                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 112                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 114                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 115                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 118                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 119
 120 #define I40E_FLOW_TYPES ( \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 130         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 131         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 132
 133 /* Additional timesync values. */
 134 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 135 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 136 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 137 #define I40E_PRTTSYN_TSYNENA     0x80000000
 138 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 139 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define I40E_MAX_PERCENT            100
 142 #define I40E_DEFAULT_DCB_APP_NUM    1
 143 #define I40E_DEFAULT_DCB_APP_PRIO   3
 144
 145 /**
 146  * Below are values for writing un-exposed registers suggested
 147  * by silicon experts
 148  */
 149 /* Destination MAC address */
 150 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 151 /* Source MAC address */
 152 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 153 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 154 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 155 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 156 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 157 /* Single VLAN tag in the inner L2 header */
 158 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 159 /* Source IPv4 address */
 160 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 161 /* Destination IPv4 address */
 162 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 163 /* Source IPv4 address for X722 */
 164 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 165 /* Destination IPv4 address for X722 */
 166 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 167 /* IPv4 Protocol for X722 */
 168 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 169 /* IPv4 Time to Live for X722 */
 170 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 171 /* IPv4 Type of Service (TOS) */
 172 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 173 /* IPv4 Protocol */
 174 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 175 /* IPv4 Time to Live */
 176 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 177 /* Source IPv6 address */
 178 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 179 /* Destination IPv6 address */
 180 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 181 /* IPv6 Traffic Class (TC) */
 182 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 183 /* IPv6 Next Header */
 184 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 185 /* IPv6 Hop Limit */
 186 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 187 /* Source L4 port */
 188 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 189 /* Destination L4 port */
 190 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 191 /* SCTP verification tag */
 192 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 193 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 194 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 195 /* Source port of tunneling UDP */
 196 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 197 /* Destination port of tunneling UDP */
 198 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 199 /* UDP Tunneling ID, NVGRE/GRE key */
 200 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 201 /* Last ether type */
 202 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 203 /* Tunneling outer destination IPv4 address */
 204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 205 /* Tunneling outer destination IPv6 address */
 206 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 207 /* 1st word of flex payload */
 208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 209 /* 2nd word of flex payload */
 210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 211 /* 3rd word of flex payload */
 212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 213 /* 4th word of flex payload */
 214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 215 /* 5th word of flex payload */
 216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 217 /* 6th word of flex payload */
 218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 219 /* 7th word of flex payload */
 220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 221 /* 8th word of flex payload */
 222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 223 /* all 8 words flex payload */
 224 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 225 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 226
 227 #define I40E_TRANSLATE_INSET 0
 228 #define I40E_TRANSLATE_REG   1
 229
 230 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 231 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 232 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 233 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 234 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 235 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 236
 237 /* PCI offset for querying capability */
 238 #define PCI_DEV_CAP_REG            0xA4
 239 /* PCI offset for enabling/disabling Extended Tag */
 240 #define PCI_DEV_CTRL_REG           0xA8
 241 /* Bit mask of Extended Tag capability */
 242 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 243 /* Bit shift of Extended Tag enable/disable */
 244 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 245 /* Bit mask of Extended Tag enable/disable */
 246 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 247
 248 /* The max bandwidth of i40e is 40Gbps. */
 249 #define I40E_QOS_BW_MAX 40000
 250 /* The bandwidth should be the multiple of 50Mbps. */
 251 #define I40E_QOS_BW_GRANULARITY 50
 252 /* The min bandwidth weight is 1. */
 253 #define I40E_QOS_BW_WEIGHT_MIN 1
 254 /* The max bandwidth weight is 127. */
 255 #define I40E_QOS_BW_WEIGHT_MAX 127
 256
 257 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 258 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 259 static int i40e_dev_configure(struct rte_eth_dev *dev);
 260 static int i40e_dev_start(struct rte_eth_dev *dev);
 261 static void i40e_dev_stop(struct rte_eth_dev *dev);
 262 static void i40e_dev_close(struct rte_eth_dev *dev);
 263 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 264 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 265 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 266 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 267 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 268 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 269 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 270                                struct rte_eth_stats *stats);
 271 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 272                                struct rte_eth_xstat *xstats, unsigned n);
 273 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 274                                      struct rte_eth_xstat_name *xstats_names,
 275                                      unsigned limit);
 276 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 277 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 278                                             uint16_t queue_id,
 279                                             uint8_t stat_idx,
 280                                             uint8_t is_rx);
 281 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 282                                 char *fw_version, size_t fw_size);
 283 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 284                               struct rte_eth_dev_info *dev_info);
 285 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 286                                 uint16_t vlan_id,
 287                                 int on);
 288 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 289                               enum rte_vlan_type vlan_type,
 290                               uint16_t tpid);
 291 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 292 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 293                                       uint16_t queue,
 294                                       int on);
 295 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 296 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 297 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 298 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 299                               struct rte_eth_fc_conf *fc_conf);
 300 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 301                               struct rte_eth_fc_conf *fc_conf);
 302 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 303                                        struct rte_eth_pfc_conf *pfc_conf);
 304 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 305                           struct ether_addr *mac_addr,
 306                           uint32_t index,
 307                           uint32_t pool);
 308 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 309 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 310                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 311                                     uint16_t reta_size);
 312 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 313                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 314                                    uint16_t reta_size);
 315
 316 static int i40e_get_cap(struct i40e_hw *hw);
 317 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 318 static int i40e_pf_setup(struct i40e_pf *pf);
 319 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 320 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 321 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 322 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 323 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 324                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 325 static void i40e_stat_update_48(struct i40e_hw *hw,
 326                                uint32_t hireg,
 327                                uint32_t loreg,
 328                                bool offset_loaded,
 329                                uint64_t *offset,
 330                                uint64_t *stat);
 331 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 332 static void i40e_dev_interrupt_handler(void *param);
 333 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 334                                 uint32_t base, uint32_t num);
 335 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 336 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 337                         uint32_t base);
 338 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 339                         uint16_t num);
 340 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 341 static int i40e_veb_release(struct i40e_veb *veb);
 342 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 343                                                 struct i40e_vsi *vsi);
 344 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 345 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 346 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 347                                              struct i40e_macvlan_filter *mv_f,
 348                                              int num,
 349                                              struct ether_addr *addr);
 350 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 351                                              struct i40e_macvlan_filter *mv_f,
 352                                              int num,
 353                                              uint16_t vlan);
 354 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 355 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 356                                     struct rte_eth_rss_conf *rss_conf);
 357 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 358                                       struct rte_eth_rss_conf *rss_conf);
 359 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 360                                         struct rte_eth_udp_tunnel *udp_tunnel);
 361 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 362                                         struct rte_eth_udp_tunnel *udp_tunnel);
 363 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 364 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 365                                 enum rte_filter_op filter_op,
 366                                 void *arg);
 367 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 368                                 enum rte_filter_type filter_type,
 369                                 enum rte_filter_op filter_op,
 370                                 void *arg);
 371 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 372                                   struct rte_eth_dcb_info *dcb_info);
 373 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 374 static void i40e_configure_registers(struct i40e_hw *hw);
 375 static void i40e_hw_init(struct rte_eth_dev *dev);
 376 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 377 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 378                         struct rte_eth_mirror_conf *mirror_conf,
 379                         uint8_t sw_id, uint8_t on);
 380 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 381
 382 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 383 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 384 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 385                                            struct timespec *timestamp,
 386                                            uint32_t flags);
 387 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 388                                            struct timespec *timestamp);
 389 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 390
 391 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 392
 393 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 394                                    struct timespec *timestamp);
 395 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 396                                     const struct timespec *timestamp);
 397
 398 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 399                                          uint16_t queue_id);
 400 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 401                                           uint16_t queue_id);
 402
 403 static int i40e_get_regs(struct rte_eth_dev *dev,
 404                          struct rte_dev_reg_info *regs);
 405
 406 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 407
 408 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 409                            struct rte_dev_eeprom_info *eeprom);
 410
 411 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 412                                       struct ether_addr *mac_addr);
 413
 414 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 415
 416 static int i40e_ethertype_filter_convert(
 417         const struct rte_eth_ethertype_filter *input,
 418         struct i40e_ethertype_filter *filter);
 419 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 420                                    struct i40e_ethertype_filter *filter);
 421
 422 static int i40e_tunnel_filter_convert(
 423         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 424         struct i40e_tunnel_filter *tunnel_filter);
 425 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 426                                 struct i40e_tunnel_filter *tunnel_filter);
 427 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 428
 429 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 430 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 431 static void i40e_filter_restore(struct i40e_pf *pf);
 432
 433 int i40e_logtype_init;
 434 int i40e_logtype_driver;
 435
 436 static const struct rte_pci_id pci_id_i40e_map[] = {
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 445         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 446         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 447         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 448         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 449         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 450         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 451         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 452         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 453         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 454         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 455         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 456         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 457         { .vendor_id = 0, /* sentinel */ },
 458 };
 459
 460 static const struct eth_dev_ops i40e_eth_dev_ops = {
 461         .dev_configure                = i40e_dev_configure,
 462         .dev_start                    = i40e_dev_start,
 463         .dev_stop                     = i40e_dev_stop,
 464         .dev_close                    = i40e_dev_close,
 465         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 466         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 467         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 468         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 469         .dev_set_link_up              = i40e_dev_set_link_up,
 470         .dev_set_link_down            = i40e_dev_set_link_down,
 471         .link_update                  = i40e_dev_link_update,
 472         .stats_get                    = i40e_dev_stats_get,
 473         .xstats_get                   = i40e_dev_xstats_get,
 474         .xstats_get_names             = i40e_dev_xstats_get_names,
 475         .stats_reset                  = i40e_dev_stats_reset,
 476         .xstats_reset                 = i40e_dev_stats_reset,
 477         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 478         .fw_version_get               = i40e_fw_version_get,
 479         .dev_infos_get                = i40e_dev_info_get,
 480         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 481         .vlan_filter_set              = i40e_vlan_filter_set,
 482         .vlan_tpid_set                = i40e_vlan_tpid_set,
 483         .vlan_offload_set             = i40e_vlan_offload_set,
 484         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 485         .vlan_pvid_set                = i40e_vlan_pvid_set,
 486         .rx_queue_start               = i40e_dev_rx_queue_start,
 487         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 488         .tx_queue_start               = i40e_dev_tx_queue_start,
 489         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 490         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 491         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 492         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 493         .rx_queue_release             = i40e_dev_rx_queue_release,
 494         .rx_queue_count               = i40e_dev_rx_queue_count,
 495         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 496         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 497         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 498         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 499         .tx_queue_release             = i40e_dev_tx_queue_release,
 500         .dev_led_on                   = i40e_dev_led_on,
 501         .dev_led_off                  = i40e_dev_led_off,
 502         .flow_ctrl_get                = i40e_flow_ctrl_get,
 503         .flow_ctrl_set                = i40e_flow_ctrl_set,
 504         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 505         .mac_addr_add                 = i40e_macaddr_add,
 506         .mac_addr_remove              = i40e_macaddr_remove,
 507         .reta_update                  = i40e_dev_rss_reta_update,
 508         .reta_query                   = i40e_dev_rss_reta_query,
 509         .rss_hash_update              = i40e_dev_rss_hash_update,
 510         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 511         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 512         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 513         .filter_ctrl                  = i40e_dev_filter_ctrl,
 514         .rxq_info_get                 = i40e_rxq_info_get,
 515         .txq_info_get                 = i40e_txq_info_get,
 516         .mirror_rule_set              = i40e_mirror_rule_set,
 517         .mirror_rule_reset            = i40e_mirror_rule_reset,
 518         .timesync_enable              = i40e_timesync_enable,
 519         .timesync_disable             = i40e_timesync_disable,
 520         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 521         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 522         .get_dcb_info                 = i40e_dev_get_dcb_info,
 523         .timesync_adjust_time         = i40e_timesync_adjust_time,
 524         .timesync_read_time           = i40e_timesync_read_time,
 525         .timesync_write_time          = i40e_timesync_write_time,
 526         .get_reg                      = i40e_get_regs,
 527         .get_eeprom_length            = i40e_get_eeprom_length,
 528         .get_eeprom                   = i40e_get_eeprom,
 529         .mac_addr_set                 = i40e_set_default_mac_addr,
 530         .mtu_set                      = i40e_dev_mtu_set,
 531 };
 532
 533 /* store statistics names and its offset in stats structure */
 534 struct rte_i40e_xstats_name_off {
 535         char name[RTE_ETH_XSTATS_NAME_SIZE];
 536         unsigned offset;
 537 };
 538
 539 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 540         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 541         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 542         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 543         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 544         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 545                 rx_unknown_protocol)},
 546         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 547         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 548         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 549         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 550 };
 551
 552 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 553                 sizeof(rte_i40e_stats_strings[0]))
 554
 555 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 556         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 557                 tx_dropped_link_down)},
 558         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 559         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 560                 illegal_bytes)},
 561         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 562         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 563                 mac_local_faults)},
 564         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 565                 mac_remote_faults)},
 566         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 567                 rx_length_errors)},
 568         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 569         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 570         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 571         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 572         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 573         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 574                 rx_size_127)},
 575         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 576                 rx_size_255)},
 577         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 578                 rx_size_511)},
 579         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 580                 rx_size_1023)},
 581         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 582                 rx_size_1522)},
 583         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 584                 rx_size_big)},
 585         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 586                 rx_undersize)},
 587         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 588                 rx_oversize)},
 589         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 590                 mac_short_packet_dropped)},
 591         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 592                 rx_fragments)},
 593         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 594         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 595         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 596                 tx_size_127)},
 597         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 598                 tx_size_255)},
 599         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 600                 tx_size_511)},
 601         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 602                 tx_size_1023)},
 603         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 604                 tx_size_1522)},
 605         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 606                 tx_size_big)},
 607         {"rx_flow_director_atr_match_packets",
 608                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 609         {"rx_flow_director_sb_match_packets",
 610                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 611         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 612                 tx_lpi_status)},
 613         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 614                 rx_lpi_status)},
 615         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 616                 tx_lpi_count)},
 617         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 618                 rx_lpi_count)},
 619 };
 620
 621 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 622                 sizeof(rte_i40e_hw_port_strings[0]))
 623
 624 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 625         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xon_rx)},
 627         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 628                 priority_xoff_rx)},
 629 };
 630
 631 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 632                 sizeof(rte_i40e_rxq_prio_strings[0]))
 633
 634 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 635         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 636                 priority_xon_tx)},
 637         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 638                 priority_xoff_tx)},
 639         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 640                 priority_xon_2_xoff)},
 641 };
 642
 643 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 644                 sizeof(rte_i40e_txq_prio_strings[0]))
 645
 646 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 647         struct rte_pci_device *pci_dev)
 648 {
 649         return rte_eth_dev_pci_generic_probe(pci_dev,
 650                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 651 }
 652
 653 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 654 {
 655         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 656 }
 657
 658 static struct rte_pci_driver rte_i40e_pmd = {
 659         .id_table = pci_id_i40e_map,
 660         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 661         .probe = eth_i40e_pci_probe,
 662         .remove = eth_i40e_pci_remove,
 663 };
 664
 665 static inline int
 666 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 667                                      struct rte_eth_link *link)
 668 {
 669         struct rte_eth_link *dst = link;
 670         struct rte_eth_link *src = &(dev->data->dev_link);
 671
 672         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 673                                         *(uint64_t *)src) == 0)
 674                 return -1;
 675
 676         return 0;
 677 }
 678
 679 static inline int
 680 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 681                                       struct rte_eth_link *link)
 682 {
 683         struct rte_eth_link *dst = &(dev->data->dev_link);
 684         struct rte_eth_link *src = link;
 685
 686         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 687                                         *(uint64_t *)src) == 0)
 688                 return -1;
 689
 690         return 0;
 691 }
 692
 693 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 694 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 695 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 696
 697 #ifndef I40E_GLQF_ORT
 698 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 699 #endif
 700 #ifndef I40E_GLQF_PIT
 701 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 702 #endif
 703 #ifndef I40E_GLQF_L3_MAP
 704 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 705 #endif
 706
 707 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 708 {
 709         /*
 710          * Initialize registers for flexible payload, which should be set by NVM.
 711          * This should be removed from code once it is fixed in NVM.
 712          */
 713         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 714         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 715         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 716         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 717         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 718         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 719         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 720         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 721         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 722         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 723         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 724         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 725
 726         /* Initialize registers for parsing packet type of QinQ */
 727         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 728         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 729 }
 730
 731 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 732
 733 /*
 734  * Add a ethertype filter to drop all flow control frames transmitted
 735  * from VSIs.
 736 */
 737 static void
 738 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 739 {
 740         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 741         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 742                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 743                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 744         int ret;
 745
 746         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 747                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 748                                 pf->main_vsi_seid, 0,
 749                                 TRUE, NULL, NULL);
 750         if (ret)
 751                 PMD_INIT_LOG(ERR,
 752                         "Failed to add filter to drop flow control frames from VSIs.");
 753 }
 754
 755 static int
 756 floating_veb_list_handler(__rte_unused const char *key,
 757                           const char *floating_veb_value,
 758                           void *opaque)
 759 {
 760         int idx = 0;
 761         unsigned int count = 0;
 762         char *end = NULL;
 763         int min, max;
 764         bool *vf_floating_veb = opaque;
 765
 766         while (isblank(*floating_veb_value))
 767                 floating_veb_value++;
 768
 769         /* Reset floating VEB configuration for VFs */
 770         for (idx = 0; idx < I40E_MAX_VF; idx++)
 771                 vf_floating_veb[idx] = false;
 772
 773         min = I40E_MAX_VF;
 774         do {
 775                 while (isblank(*floating_veb_value))
 776                         floating_veb_value++;
 777                 if (*floating_veb_value == '\0')
 778                         return -1;
 779                 errno = 0;
 780                 idx = strtoul(floating_veb_value, &end, 10);
 781                 if (errno || end == NULL)
 782                         return -1;
 783                 while (isblank(*end))
 784                         end++;
 785                 if (*end == '-') {
 786                         min = idx;
 787                 } else if ((*end == ';') || (*end == '\0')) {
 788                         max = idx;
 789                         if (min == I40E_MAX_VF)
 790                                 min = idx;
 791                         if (max >= I40E_MAX_VF)
 792                                 max = I40E_MAX_VF - 1;
 793                         for (idx = min; idx <= max; idx++) {
 794                                 vf_floating_veb[idx] = true;
 795                                 count++;
 796                         }
 797                         min = I40E_MAX_VF;
 798                 } else {
 799                         return -1;
 800                 }
 801                 floating_veb_value = end + 1;
 802         } while (*end != '\0');
 803
 804         if (count == 0)
 805                 return -1;
 806
 807         return 0;
 808 }
 809
 810 static void
 811 config_vf_floating_veb(struct rte_devargs *devargs,
 812                        uint16_t floating_veb,
 813                        bool *vf_floating_veb)
 814 {
 815         struct rte_kvargs *kvlist;
 816         int i;
 817         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 818
 819         if (!floating_veb)
 820                 return;
 821         /* All the VFs attach to the floating VEB by default
 822          * when the floating VEB is enabled.
 823          */
 824         for (i = 0; i < I40E_MAX_VF; i++)
 825                 vf_floating_veb[i] = true;
 826
 827         if (devargs == NULL)
 828                 return;
 829
 830         kvlist = rte_kvargs_parse(devargs->args, NULL);
 831         if (kvlist == NULL)
 832                 return;
 833
 834         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 835                 rte_kvargs_free(kvlist);
 836                 return;
 837         }
 838         /* When the floating_veb_list parameter exists, all the VFs
 839          * will attach to the legacy VEB firstly, then configure VFs
 840          * to the floating VEB according to the floating_veb_list.
 841          */
 842         if (rte_kvargs_process(kvlist, floating_veb_list,
 843                                floating_veb_list_handler,
 844                                vf_floating_veb) < 0) {
 845                 rte_kvargs_free(kvlist);
 846                 return;
 847         }
 848         rte_kvargs_free(kvlist);
 849 }
 850
 851 static int
 852 i40e_check_floating_handler(__rte_unused const char *key,
 853                             const char *value,
 854                             __rte_unused void *opaque)
 855 {
 856         if (strcmp(value, "1"))
 857                 return -1;
 858
 859         return 0;
 860 }
 861
 862 static int
 863 is_floating_veb_supported(struct rte_devargs *devargs)
 864 {
 865         struct rte_kvargs *kvlist;
 866         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 867
 868         if (devargs == NULL)
 869                 return 0;
 870
 871         kvlist = rte_kvargs_parse(devargs->args, NULL);
 872         if (kvlist == NULL)
 873                 return 0;
 874
 875         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 876                 rte_kvargs_free(kvlist);
 877                 return 0;
 878         }
 879         /* Floating VEB is enabled when there's key-value:
 880          * enable_floating_veb=1
 881          */
 882         if (rte_kvargs_process(kvlist, floating_veb_key,
 883                                i40e_check_floating_handler, NULL) < 0) {
 884                 rte_kvargs_free(kvlist);
 885                 return 0;
 886         }
 887         rte_kvargs_free(kvlist);
 888
 889         return 1;
 890 }
 891
 892 static void
 893 config_floating_veb(struct rte_eth_dev *dev)
 894 {
 895         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 896         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 897         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 898
 899         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 900
 901         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 902                 pf->floating_veb =
 903                         is_floating_veb_supported(pci_dev->device.devargs);
 904                 config_vf_floating_veb(pci_dev->device.devargs,
 905                                        pf->floating_veb,
 906                                        pf->floating_veb_list);
 907         } else {
 908                 pf->floating_veb = false;
 909         }
 910 }
 911
 912 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 913 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 914
 915 static int
 916 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 917 {
 918         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 919         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 920         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 921         int ret;
 922
 923         struct rte_hash_parameters ethertype_hash_params = {
 924                 .name = ethertype_hash_name,
 925                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 926                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 927                 .hash_func = rte_hash_crc,
 928                 .hash_func_init_val = 0,
 929                 .socket_id = rte_socket_id(),
 930         };
 931
 932         /* Initialize ethertype filter rule list and hash */
 933         TAILQ_INIT(&ethertype_rule->ethertype_list);
 934         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 935                  "ethertype_%s", dev->data->name);
 936         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 937         if (!ethertype_rule->hash_table) {
 938                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 939                 return -EINVAL;
 940         }
 941         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 942                                        sizeof(struct i40e_ethertype_filter *) *
 943                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 944                                        0);
 945         if (!ethertype_rule->hash_map) {
 946                 PMD_INIT_LOG(ERR,
 947                              "Failed to allocate memory for ethertype hash map!");
 948                 ret = -ENOMEM;
 949                 goto err_ethertype_hash_map_alloc;
 950         }
 951
 952         return 0;
 953
 954 err_ethertype_hash_map_alloc:
 955         rte_hash_free(ethertype_rule->hash_table);
 956
 957         return ret;
 958 }
 959
 960 static int
 961 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 962 {
 963         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 964         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 965         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 966         int ret;
 967
 968         struct rte_hash_parameters tunnel_hash_params = {
 969                 .name = tunnel_hash_name,
 970                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 971                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 972                 .hash_func = rte_hash_crc,
 973                 .hash_func_init_val = 0,
 974                 .socket_id = rte_socket_id(),
 975         };
 976
 977         /* Initialize tunnel filter rule list and hash */
 978         TAILQ_INIT(&tunnel_rule->tunnel_list);
 979         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 980                  "tunnel_%s", dev->data->name);
 981         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 982         if (!tunnel_rule->hash_table) {
 983                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 984                 return -EINVAL;
 985         }
 986         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 987                                     sizeof(struct i40e_tunnel_filter *) *
 988                                     I40E_MAX_TUNNEL_FILTER_NUM,
 989                                     0);
 990         if (!tunnel_rule->hash_map) {
 991                 PMD_INIT_LOG(ERR,
 992                              "Failed to allocate memory for tunnel hash map!");
 993                 ret = -ENOMEM;
 994                 goto err_tunnel_hash_map_alloc;
 995         }
 996
 997         return 0;
 998
 999 err_tunnel_hash_map_alloc:
1000         rte_hash_free(tunnel_rule->hash_table);
1001
1002         return ret;
1003 }
1004
1005 static int
1006 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1007 {
1008         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1009         struct i40e_fdir_info *fdir_info = &pf->fdir;
1010         char fdir_hash_name[RTE_HASH_NAMESIZE];
1011         int ret;
1012
1013         struct rte_hash_parameters fdir_hash_params = {
1014                 .name = fdir_hash_name,
1015                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1016                 .key_len = sizeof(struct rte_eth_fdir_input),
1017                 .hash_func = rte_hash_crc,
1018                 .hash_func_init_val = 0,
1019                 .socket_id = rte_socket_id(),
1020         };
1021
1022         /* Initialize flow director filter rule list and hash */
1023         TAILQ_INIT(&fdir_info->fdir_list);
1024         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1025                  "fdir_%s", dev->data->name);
1026         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1027         if (!fdir_info->hash_table) {
1028                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1029                 return -EINVAL;
1030         }
1031         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1032                                           sizeof(struct i40e_fdir_filter *) *
1033                                           I40E_MAX_FDIR_FILTER_NUM,
1034                                           0);
1035         if (!fdir_info->hash_map) {
1036                 PMD_INIT_LOG(ERR,
1037                              "Failed to allocate memory for fdir hash map!");
1038                 ret = -ENOMEM;
1039                 goto err_fdir_hash_map_alloc;
1040         }
1041         return 0;
1042
1043 err_fdir_hash_map_alloc:
1044         rte_hash_free(fdir_info->hash_table);
1045
1046         return ret;
1047 }
1048
1049 static int
1050 eth_i40e_dev_init(struct rte_eth_dev *dev)
1051 {
1052         struct rte_pci_device *pci_dev;
1053         struct rte_intr_handle *intr_handle;
1054         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1055         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1056         struct i40e_vsi *vsi;
1057         int ret;
1058         uint32_t len;
1059         uint8_t aq_fail = 0;
1060
1061         PMD_INIT_FUNC_TRACE();
1062
1063         dev->dev_ops = &i40e_eth_dev_ops;
1064         dev->rx_pkt_burst = i40e_recv_pkts;
1065         dev->tx_pkt_burst = i40e_xmit_pkts;
1066         dev->tx_pkt_prepare = i40e_prep_pkts;
1067
1068         /* for secondary processes, we don't initialise any further as primary
1069          * has already done this work. Only check we don't need a different
1070          * RX function */
1071         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1072                 i40e_set_rx_function(dev);
1073                 i40e_set_tx_function(dev);
1074                 return 0;
1075         }
1076         pci_dev = I40E_DEV_TO_PCI(dev);
1077         intr_handle = &pci_dev->intr_handle;
1078
1079         rte_eth_copy_pci_info(dev, pci_dev);
1080         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1081
1082         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1083         pf->adapter->eth_dev = dev;
1084         pf->dev_data = dev->data;
1085
1086         hw->back = I40E_PF_TO_ADAPTER(pf);
1087         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1088         if (!hw->hw_addr) {
1089                 PMD_INIT_LOG(ERR,
1090                         "Hardware is not available, as address is NULL");
1091                 return -ENODEV;
1092         }
1093
1094         hw->vendor_id = pci_dev->id.vendor_id;
1095         hw->device_id = pci_dev->id.device_id;
1096         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1097         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1098         hw->bus.device = pci_dev->addr.devid;
1099         hw->bus.func = pci_dev->addr.function;
1100         hw->adapter_stopped = 0;
1101
1102         /* Make sure all is clean before doing PF reset */
1103         i40e_clear_hw(hw);
1104
1105         /* Initialize the hardware */
1106         i40e_hw_init(dev);
1107
1108         /* Reset here to make sure all is clean for each PF */
1109         ret = i40e_pf_reset(hw);
1110         if (ret) {
1111                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1112                 return ret;
1113         }
1114
1115         /* Initialize the shared code (base driver) */
1116         ret = i40e_init_shared_code(hw);
1117         if (ret) {
1118                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1119                 return ret;
1120         }
1121
1122         /*
1123          * To work around the NVM issue, initialize registers
1124          * for flexible payload and packet type of QinQ by
1125          * software. It should be removed once issues are fixed
1126          * in NVM.
1127          */
1128         i40e_GLQF_reg_init(hw);
1129
1130         /* Initialize the input set for filters (hash and fd) to default value */
1131         i40e_filter_input_set_init(pf);
1132
1133         /* Initialize the parameters for adminq */
1134         i40e_init_adminq_parameter(hw);
1135         ret = i40e_init_adminq(hw);
1136         if (ret != I40E_SUCCESS) {
1137                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1138                 return -EIO;
1139         }
1140         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1141                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1142                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1143                      ((hw->nvm.version >> 12) & 0xf),
1144                      ((hw->nvm.version >> 4) & 0xff),
1145                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1146
1147         /* initialise the L3_MAP register */
1148         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1149                                    0x00000028,  NULL);
1150         if (ret)
1151                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1152
1153         /* Need the special FW version to support floating VEB */
1154         config_floating_veb(dev);
1155         /* Clear PXE mode */
1156         i40e_clear_pxe_mode(hw);
1157         ret = i40e_dev_sync_phy_type(hw);
1158         if (ret) {
1159                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1160                 goto err_sync_phy_type;
1161         }
1162         /*
1163          * On X710, performance number is far from the expectation on recent
1164          * firmware versions. The fix for this issue may not be integrated in
1165          * the following firmware version. So the workaround in software driver
1166          * is needed. It needs to modify the initial values of 3 internal only
1167          * registers. Note that the workaround can be removed when it is fixed
1168          * in firmware in the future.
1169          */
1170         i40e_configure_registers(hw);
1171
1172         /* Get hw capabilities */
1173         ret = i40e_get_cap(hw);
1174         if (ret != I40E_SUCCESS) {
1175                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1176                 goto err_get_capabilities;
1177         }
1178
1179         /* Initialize parameters for PF */
1180         ret = i40e_pf_parameter_init(dev);
1181         if (ret != 0) {
1182                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1183                 goto err_parameter_init;
1184         }
1185
1186         /* Initialize the queue management */
1187         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1188         if (ret < 0) {
1189                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1190                 goto err_qp_pool_init;
1191         }
1192         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1193                                 hw->func_caps.num_msix_vectors - 1);
1194         if (ret < 0) {
1195                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1196                 goto err_msix_pool_init;
1197         }
1198
1199         /* Initialize lan hmc */
1200         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1201                                 hw->func_caps.num_rx_qp, 0, 0);
1202         if (ret != I40E_SUCCESS) {
1203                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1204                 goto err_init_lan_hmc;
1205         }
1206
1207         /* Configure lan hmc */
1208         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1209         if (ret != I40E_SUCCESS) {
1210                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1211                 goto err_configure_lan_hmc;
1212         }
1213
1214         /* Get and check the mac address */
1215         i40e_get_mac_addr(hw, hw->mac.addr);
1216         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1217                 PMD_INIT_LOG(ERR, "mac address is not valid");
1218                 ret = -EIO;
1219                 goto err_get_mac_addr;
1220         }
1221         /* Copy the permanent MAC address */
1222         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1223                         (struct ether_addr *) hw->mac.perm_addr);
1224
1225         /* Disable flow control */
1226         hw->fc.requested_mode = I40E_FC_NONE;
1227         i40e_set_fc(hw, &aq_fail, TRUE);
1228
1229         /* Set the global registers with default ether type value */
1230         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1231         if (ret != I40E_SUCCESS) {
1232                 PMD_INIT_LOG(ERR,
1233                         "Failed to set the default outer VLAN ether type");
1234                 goto err_setup_pf_switch;
1235         }
1236
1237         /* PF setup, which includes VSI setup */
1238         ret = i40e_pf_setup(pf);
1239         if (ret) {
1240                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1241                 goto err_setup_pf_switch;
1242         }
1243
1244         /* reset all stats of the device, including pf and main vsi */
1245         i40e_dev_stats_reset(dev);
1246
1247         vsi = pf->main_vsi;
1248
1249         /* Disable double vlan by default */
1250         i40e_vsi_config_double_vlan(vsi, FALSE);
1251
1252         /* Disable S-TAG identification when floating_veb is disabled */
1253         if (!pf->floating_veb) {
1254                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1255                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1256                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1257                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1258                 }
1259         }
1260
1261         if (!vsi->max_macaddrs)
1262                 len = ETHER_ADDR_LEN;
1263         else
1264                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1265
1266         /* Should be after VSI initialized */
1267         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1268         if (!dev->data->mac_addrs) {
1269                 PMD_INIT_LOG(ERR,
1270                         "Failed to allocated memory for storing mac address");
1271                 goto err_mac_alloc;
1272         }
1273         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1274                                         &dev->data->mac_addrs[0]);
1275
1276         /* Init dcb to sw mode by default */
1277         ret = i40e_dcb_init_configure(dev, TRUE);
1278         if (ret != I40E_SUCCESS) {
1279                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1280                 pf->flags &= ~I40E_FLAG_DCB;
1281         }
1282         /* Update HW struct after DCB configuration */
1283         i40e_get_cap(hw);
1284
1285         /* initialize pf host driver to setup SRIOV resource if applicable */
1286         i40e_pf_host_init(dev);
1287
1288         /* register callback func to eal lib */
1289         rte_intr_callback_register(intr_handle,
1290                                    i40e_dev_interrupt_handler, dev);
1291
1292         /* configure and enable device interrupt */
1293         i40e_pf_config_irq0(hw, TRUE);
1294         i40e_pf_enable_irq0(hw);
1295
1296         /* enable uio intr after callback register */
1297         rte_intr_enable(intr_handle);
1298         /*
1299          * Add an ethertype filter to drop all flow control frames transmitted
1300          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1301          * frames to wire.
1302          */
1303         i40e_add_tx_flow_control_drop_filter(pf);
1304
1305         /* Set the max frame size to 0x2600 by default,
1306          * in case other drivers changed the default value.
1307          */
1308         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1309
1310         /* initialize mirror rule list */
1311         TAILQ_INIT(&pf->mirror_list);
1312
1313         ret = i40e_init_ethtype_filter_list(dev);
1314         if (ret < 0)
1315                 goto err_init_ethtype_filter_list;
1316         ret = i40e_init_tunnel_filter_list(dev);
1317         if (ret < 0)
1318                 goto err_init_tunnel_filter_list;
1319         ret = i40e_init_fdir_filter_list(dev);
1320         if (ret < 0)
1321                 goto err_init_fdir_filter_list;
1322
1323         return 0;
1324
1325 err_init_fdir_filter_list:
1326         rte_free(pf->tunnel.hash_table);
1327         rte_free(pf->tunnel.hash_map);
1328 err_init_tunnel_filter_list:
1329         rte_free(pf->ethertype.hash_table);
1330         rte_free(pf->ethertype.hash_map);
1331 err_init_ethtype_filter_list:
1332         rte_free(dev->data->mac_addrs);
1333 err_mac_alloc:
1334         i40e_vsi_release(pf->main_vsi);
1335 err_setup_pf_switch:
1336 err_get_mac_addr:
1337 err_configure_lan_hmc:
1338         (void)i40e_shutdown_lan_hmc(hw);
1339 err_init_lan_hmc:
1340         i40e_res_pool_destroy(&pf->msix_pool);
1341 err_msix_pool_init:
1342         i40e_res_pool_destroy(&pf->qp_pool);
1343 err_qp_pool_init:
1344 err_parameter_init:
1345 err_get_capabilities:
1346 err_sync_phy_type:
1347         (void)i40e_shutdown_adminq(hw);
1348
1349         return ret;
1350 }
1351
1352 static void
1353 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1354 {
1355         struct i40e_ethertype_filter *p_ethertype;
1356         struct i40e_ethertype_rule *ethertype_rule;
1357
1358         ethertype_rule = &pf->ethertype;
1359         /* Remove all ethertype filter rules and hash */
1360         if (ethertype_rule->hash_map)
1361                 rte_free(ethertype_rule->hash_map);
1362         if (ethertype_rule->hash_table)
1363                 rte_hash_free(ethertype_rule->hash_table);
1364
1365         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1366                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1367                              p_ethertype, rules);
1368                 rte_free(p_ethertype);
1369         }
1370 }
1371
1372 static void
1373 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1374 {
1375         struct i40e_tunnel_filter *p_tunnel;
1376         struct i40e_tunnel_rule *tunnel_rule;
1377
1378         tunnel_rule = &pf->tunnel;
1379         /* Remove all tunnel director rules and hash */
1380         if (tunnel_rule->hash_map)
1381                 rte_free(tunnel_rule->hash_map);
1382         if (tunnel_rule->hash_table)
1383                 rte_hash_free(tunnel_rule->hash_table);
1384
1385         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1386                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1387                 rte_free(p_tunnel);
1388         }
1389 }
1390
1391 static void
1392 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1393 {
1394         struct i40e_fdir_filter *p_fdir;
1395         struct i40e_fdir_info *fdir_info;
1396
1397         fdir_info = &pf->fdir;
1398         /* Remove all flow director rules and hash */
1399         if (fdir_info->hash_map)
1400                 rte_free(fdir_info->hash_map);
1401         if (fdir_info->hash_table)
1402                 rte_hash_free(fdir_info->hash_table);
1403
1404         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1405                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1406                 rte_free(p_fdir);
1407         }
1408 }
1409
1410 static int
1411 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1412 {
1413         struct i40e_pf *pf;
1414         struct rte_pci_device *pci_dev;
1415         struct rte_intr_handle *intr_handle;
1416         struct i40e_hw *hw;
1417         struct i40e_filter_control_settings settings;
1418         struct rte_flow *p_flow;
1419         int ret;
1420         uint8_t aq_fail = 0;
1421
1422         PMD_INIT_FUNC_TRACE();
1423
1424         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1425                 return 0;
1426
1427         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1428         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1429         pci_dev = I40E_DEV_TO_PCI(dev);
1430         intr_handle = &pci_dev->intr_handle;
1431
1432         if (hw->adapter_stopped == 0)
1433                 i40e_dev_close(dev);
1434
1435         dev->dev_ops = NULL;
1436         dev->rx_pkt_burst = NULL;
1437         dev->tx_pkt_burst = NULL;
1438
1439         /* Clear PXE mode */
1440         i40e_clear_pxe_mode(hw);
1441
1442         /* Unconfigure filter control */
1443         memset(&settings, 0, sizeof(settings));
1444         ret = i40e_set_filter_control(hw, &settings);
1445         if (ret)
1446                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1447                                         ret);
1448
1449         /* Disable flow control */
1450         hw->fc.requested_mode = I40E_FC_NONE;
1451         i40e_set_fc(hw, &aq_fail, TRUE);
1452
1453         /* uninitialize pf host driver */
1454         i40e_pf_host_uninit(dev);
1455
1456         rte_free(dev->data->mac_addrs);
1457         dev->data->mac_addrs = NULL;
1458
1459         /* disable uio intr before callback unregister */
1460         rte_intr_disable(intr_handle);
1461
1462         /* register callback func to eal lib */
1463         rte_intr_callback_unregister(intr_handle,
1464                                      i40e_dev_interrupt_handler, dev);
1465
1466         i40e_rm_ethtype_filter_list(pf);
1467         i40e_rm_tunnel_filter_list(pf);
1468         i40e_rm_fdir_filter_list(pf);
1469
1470         /* Remove all flows */
1471         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1472                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1473                 rte_free(p_flow);
1474         }
1475
1476         return 0;
1477 }
1478
1479 static int
1480 i40e_dev_configure(struct rte_eth_dev *dev)
1481 {
1482         struct i40e_adapter *ad =
1483                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1484         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1485         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1486         int i, ret;
1487
1488         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1489          * bulk allocation or vector Rx preconditions we will reset it.
1490          */
1491         ad->rx_bulk_alloc_allowed = true;
1492         ad->rx_vec_allowed = true;
1493         ad->tx_simple_allowed = true;
1494         ad->tx_vec_allowed = true;
1495
1496         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1497                 ret = i40e_fdir_setup(pf);
1498                 if (ret != I40E_SUCCESS) {
1499                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1500                         return -ENOTSUP;
1501                 }
1502                 ret = i40e_fdir_configure(dev);
1503                 if (ret < 0) {
1504                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1505                         goto err;
1506                 }
1507         } else
1508                 i40e_fdir_teardown(pf);
1509
1510         ret = i40e_dev_init_vlan(dev);
1511         if (ret < 0)
1512                 goto err;
1513
1514         /* VMDQ setup.
1515          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1516          *  RSS setting have different requirements.
1517          *  General PMD driver call sequence are NIC init, configure,
1518          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1519          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1520          *  applicable. So, VMDQ setting has to be done before
1521          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1522          *  For RSS setting, it will try to calculate actual configured RX queue
1523          *  number, which will be available after rx_queue_setup(). dev_start()
1524          *  function is good to place RSS setup.
1525          */
1526         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1527                 ret = i40e_vmdq_setup(dev);
1528                 if (ret)
1529                         goto err;
1530         }
1531
1532         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1533                 ret = i40e_dcb_setup(dev);
1534                 if (ret) {
1535                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1536                         goto err_dcb;
1537                 }
1538         }
1539
1540         TAILQ_INIT(&pf->flow_list);
1541
1542         return 0;
1543
1544 err_dcb:
1545         /* need to release vmdq resource if exists */
1546         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1547                 i40e_vsi_release(pf->vmdq[i].vsi);
1548                 pf->vmdq[i].vsi = NULL;
1549         }
1550         rte_free(pf->vmdq);
1551         pf->vmdq = NULL;
1552 err:
1553         /* need to release fdir resource if exists */
1554         i40e_fdir_teardown(pf);
1555         return ret;
1556 }
1557
1558 void
1559 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1560 {
1561         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1562         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1563         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1564         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1565         uint16_t msix_vect = vsi->msix_intr;
1566         uint16_t i;
1567
1568         for (i = 0; i < vsi->nb_qps; i++) {
1569                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1570                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1571                 rte_wmb();
1572         }
1573
1574         if (vsi->type != I40E_VSI_SRIOV) {
1575                 if (!rte_intr_allow_others(intr_handle)) {
1576                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1577                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1578                         I40E_WRITE_REG(hw,
1579                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1580                                        0);
1581                 } else {
1582                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1583                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1584                         I40E_WRITE_REG(hw,
1585                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1586                                                        msix_vect - 1), 0);
1587                 }
1588         } else {
1589                 uint32_t reg;
1590                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1591                         vsi->user_param + (msix_vect - 1);
1592
1593                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1594                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1595         }
1596         I40E_WRITE_FLUSH(hw);
1597 }
1598
1599 static void
1600 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1601                        int base_queue, int nb_queue)
1602 {
1603         int i;
1604         uint32_t val;
1605         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1606
1607         /* Bind all RX queues to allocated MSIX interrupt */
1608         for (i = 0; i < nb_queue; i++) {
1609                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1610                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1611                         ((base_queue + i + 1) <<
1612                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1613                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1614                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1615
1616                 if (i == nb_queue - 1)
1617                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1618                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1619         }
1620
1621         /* Write first RX queue to Link list register as the head element */
1622         if (vsi->type != I40E_VSI_SRIOV) {
1623                 uint16_t interval =
1624                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1625
1626                 if (msix_vect == I40E_MISC_VEC_ID) {
1627                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1628                                        (base_queue <<
1629                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1630                                        (0x0 <<
1631                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1632                         I40E_WRITE_REG(hw,
1633                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1634                                        interval);
1635                 } else {
1636                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1637                                        (base_queue <<
1638                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1639                                        (0x0 <<
1640                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1641                         I40E_WRITE_REG(hw,
1642                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1643                                                        msix_vect - 1),
1644                                        interval);
1645                 }
1646         } else {
1647                 uint32_t reg;
1648
1649                 if (msix_vect == I40E_MISC_VEC_ID) {
1650                         I40E_WRITE_REG(hw,
1651                                        I40E_VPINT_LNKLST0(vsi->user_param),
1652                                        (base_queue <<
1653                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1654                                        (0x0 <<
1655                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1656                 } else {
1657                         /* num_msix_vectors_vf needs to minus irq0 */
1658                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1659                                 vsi->user_param + (msix_vect - 1);
1660
1661                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1662                                        (base_queue <<
1663                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1664                                        (0x0 <<
1665                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1666                 }
1667         }
1668
1669         I40E_WRITE_FLUSH(hw);
1670 }
1671
1672 void
1673 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1674 {
1675         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1676         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1677         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1678         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1679         uint16_t msix_vect = vsi->msix_intr;
1680         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1681         uint16_t queue_idx = 0;
1682         int record = 0;
1683         uint32_t val;
1684         int i;
1685
1686         for (i = 0; i < vsi->nb_qps; i++) {
1687                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1688                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1689         }
1690
1691         /* INTENA flag is not auto-cleared for interrupt */
1692         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1693         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1694                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1695                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1696         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1697
1698         /* VF bind interrupt */
1699         if (vsi->type == I40E_VSI_SRIOV) {
1700                 __vsi_queues_bind_intr(vsi, msix_vect,
1701                                        vsi->base_queue, vsi->nb_qps);
1702                 return;
1703         }
1704
1705         /* PF & VMDq bind interrupt */
1706         if (rte_intr_dp_is_en(intr_handle)) {
1707                 if (vsi->type == I40E_VSI_MAIN) {
1708                         queue_idx = 0;
1709                         record = 1;
1710                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1711                         struct i40e_vsi *main_vsi =
1712                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1713                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1714                         record = 1;
1715                 }
1716         }
1717
1718         for (i = 0; i < vsi->nb_used_qps; i++) {
1719                 if (nb_msix <= 1) {
1720                         if (!rte_intr_allow_others(intr_handle))
1721                                 /* allow to share MISC_VEC_ID */
1722                                 msix_vect = I40E_MISC_VEC_ID;
1723
1724                         /* no enough msix_vect, map all to one */
1725                         __vsi_queues_bind_intr(vsi, msix_vect,
1726                                                vsi->base_queue + i,
1727                                                vsi->nb_used_qps - i);
1728                         for (; !!record && i < vsi->nb_used_qps; i++)
1729                                 intr_handle->intr_vec[queue_idx + i] =
1730                                         msix_vect;
1731                         break;
1732                 }
1733                 /* 1:1 queue/msix_vect mapping */
1734                 __vsi_queues_bind_intr(vsi, msix_vect,
1735                                        vsi->base_queue + i, 1);
1736                 if (!!record)
1737                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1738
1739                 msix_vect++;
1740                 nb_msix--;
1741         }
1742 }
1743
1744 static void
1745 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1746 {
1747         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1748         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1749         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1750         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1751         uint16_t interval = i40e_calc_itr_interval(\
1752                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1753         uint16_t msix_intr, i;
1754
1755         if (rte_intr_allow_others(intr_handle))
1756                 for (i = 0; i < vsi->nb_msix; i++) {
1757                         msix_intr = vsi->msix_intr + i;
1758                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1759                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1760                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1761                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1762                                 (interval <<
1763                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1764                 }
1765         else
1766                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1767                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1768                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1769                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1770                                (interval <<
1771                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1772
1773         I40E_WRITE_FLUSH(hw);
1774 }
1775
1776 static void
1777 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1778 {
1779         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1780         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1781         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1782         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1783         uint16_t msix_intr, i;
1784
1785         if (rte_intr_allow_others(intr_handle))
1786                 for (i = 0; i < vsi->nb_msix; i++) {
1787                         msix_intr = vsi->msix_intr + i;
1788                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1789                                        0);
1790                 }
1791         else
1792                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1793
1794         I40E_WRITE_FLUSH(hw);
1795 }
1796
1797 static inline uint8_t
1798 i40e_parse_link_speeds(uint16_t link_speeds)
1799 {
1800         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1801
1802         if (link_speeds & ETH_LINK_SPEED_40G)
1803                 link_speed |= I40E_LINK_SPEED_40GB;
1804         if (link_speeds & ETH_LINK_SPEED_25G)
1805                 link_speed |= I40E_LINK_SPEED_25GB;
1806         if (link_speeds & ETH_LINK_SPEED_20G)
1807                 link_speed |= I40E_LINK_SPEED_20GB;
1808         if (link_speeds & ETH_LINK_SPEED_10G)
1809                 link_speed |= I40E_LINK_SPEED_10GB;
1810         if (link_speeds & ETH_LINK_SPEED_1G)
1811                 link_speed |= I40E_LINK_SPEED_1GB;
1812         if (link_speeds & ETH_LINK_SPEED_100M)
1813                 link_speed |= I40E_LINK_SPEED_100MB;
1814
1815         return link_speed;
1816 }
1817
1818 static int
1819 i40e_phy_conf_link(struct i40e_hw *hw,
1820                    uint8_t abilities,
1821                    uint8_t force_speed)
1822 {
1823         enum i40e_status_code status;
1824         struct i40e_aq_get_phy_abilities_resp phy_ab;
1825         struct i40e_aq_set_phy_config phy_conf;
1826         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1827                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1828                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1829                         I40E_AQ_PHY_FLAG_LOW_POWER;
1830         const uint8_t advt = I40E_LINK_SPEED_40GB |
1831                         I40E_LINK_SPEED_25GB |
1832                         I40E_LINK_SPEED_10GB |
1833                         I40E_LINK_SPEED_1GB |
1834                         I40E_LINK_SPEED_100MB;
1835         int ret = -ENOTSUP;
1836
1837
1838         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1839                                               NULL);
1840         if (status)
1841                 return ret;
1842
1843         memset(&phy_conf, 0, sizeof(phy_conf));
1844
1845         /* bits 0-2 use the values from get_phy_abilities_resp */
1846         abilities &= ~mask;
1847         abilities |= phy_ab.abilities & mask;
1848
1849         /* update ablities and speed */
1850         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1851                 phy_conf.link_speed = advt;
1852         else
1853                 phy_conf.link_speed = force_speed;
1854
1855         phy_conf.abilities = abilities;
1856
1857         /* use get_phy_abilities_resp value for the rest */
1858         phy_conf.phy_type = phy_ab.phy_type;
1859         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1860         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1861         phy_conf.eee_capability = phy_ab.eee_capability;
1862         phy_conf.eeer = phy_ab.eeer_val;
1863         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1864
1865         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1866                     phy_ab.abilities, phy_ab.link_speed);
1867         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1868                     phy_conf.abilities, phy_conf.link_speed);
1869
1870         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1871         if (status)
1872                 return ret;
1873
1874         return I40E_SUCCESS;
1875 }
1876
1877 static int
1878 i40e_apply_link_speed(struct rte_eth_dev *dev)
1879 {
1880         uint8_t speed;
1881         uint8_t abilities = 0;
1882         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1883         struct rte_eth_conf *conf = &dev->data->dev_conf;
1884
1885         speed = i40e_parse_link_speeds(conf->link_speeds);
1886         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1887         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1888                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1889         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1890
1891         /* Skip changing speed on 40G interfaces, FW does not support */
1892         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1893                 speed =  I40E_LINK_SPEED_UNKNOWN;
1894                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1895         }
1896
1897         return i40e_phy_conf_link(hw, abilities, speed);
1898 }
1899
1900 static int
1901 i40e_dev_start(struct rte_eth_dev *dev)
1902 {
1903         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1904         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1905         struct i40e_vsi *main_vsi = pf->main_vsi;
1906         int ret, i;
1907         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1908         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1909         uint32_t intr_vector = 0;
1910         struct i40e_vsi *vsi;
1911
1912         hw->adapter_stopped = 0;
1913
1914         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1915                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1916                              dev->data->port_id);
1917                 return -EINVAL;
1918         }
1919
1920         rte_intr_disable(intr_handle);
1921
1922         if ((rte_intr_cap_multiple(intr_handle) ||
1923              !RTE_ETH_DEV_SRIOV(dev).active) &&
1924             dev->data->dev_conf.intr_conf.rxq != 0) {
1925                 intr_vector = dev->data->nb_rx_queues;
1926                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1927                 if (ret)
1928                         return ret;
1929         }
1930
1931         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1932                 intr_handle->intr_vec =
1933                         rte_zmalloc("intr_vec",
1934                                     dev->data->nb_rx_queues * sizeof(int),
1935                                     0);
1936                 if (!intr_handle->intr_vec) {
1937                         PMD_INIT_LOG(ERR,
1938                                 "Failed to allocate %d rx_queues intr_vec",
1939                                 dev->data->nb_rx_queues);
1940                         return -ENOMEM;
1941                 }
1942         }
1943
1944         /* Initialize VSI */
1945         ret = i40e_dev_rxtx_init(pf);
1946         if (ret != I40E_SUCCESS) {
1947                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1948                 goto err_up;
1949         }
1950
1951         /* Map queues with MSIX interrupt */
1952         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1953                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1954         i40e_vsi_queues_bind_intr(main_vsi);
1955         i40e_vsi_enable_queues_intr(main_vsi);
1956
1957         /* Map VMDQ VSI queues with MSIX interrupt */
1958         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1959                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1960                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1961                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1962         }
1963
1964         /* enable FDIR MSIX interrupt */
1965         if (pf->fdir.fdir_vsi) {
1966                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1967                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1968         }
1969
1970         /* Enable all queues which have been configured */
1971         ret = i40e_dev_switch_queues(pf, TRUE);
1972         if (ret != I40E_SUCCESS) {
1973                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1974                 goto err_up;
1975         }
1976
1977         /* Enable receiving broadcast packets */
1978         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1979         if (ret != I40E_SUCCESS)
1980                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1981
1982         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1983                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1984                                                 true, NULL);
1985                 if (ret != I40E_SUCCESS)
1986                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1987         }
1988
1989         /* Enable the VLAN promiscuous mode. */
1990         if (pf->vfs) {
1991                 for (i = 0; i < pf->vf_num; i++) {
1992                         vsi = pf->vfs[i].vsi;
1993                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1994                                                      true, NULL);
1995                 }
1996         }
1997
1998         /* Apply link configure */
1999         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2000                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2001                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2002                                 ETH_LINK_SPEED_40G)) {
2003                 PMD_DRV_LOG(ERR, "Invalid link setting");
2004                 goto err_up;
2005         }
2006         ret = i40e_apply_link_speed(dev);
2007         if (I40E_SUCCESS != ret) {
2008                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2009                 goto err_up;
2010         }
2011
2012         if (!rte_intr_allow_others(intr_handle)) {
2013                 rte_intr_callback_unregister(intr_handle,
2014                                              i40e_dev_interrupt_handler,
2015                                              (void *)dev);
2016                 /* configure and enable device interrupt */
2017                 i40e_pf_config_irq0(hw, FALSE);
2018                 i40e_pf_enable_irq0(hw);
2019
2020                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2021                         PMD_INIT_LOG(INFO,
2022                                 "lsc won't enable because of no intr multiplex");
2023         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2024                 ret = i40e_aq_set_phy_int_mask(hw,
2025                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2026                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2027                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2028                 if (ret != I40E_SUCCESS)
2029                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2030
2031                 /* Call get_link_info aq commond to enable LSE */
2032                 i40e_dev_link_update(dev, 0);
2033         }
2034
2035         /* enable uio intr after callback register */
2036         rte_intr_enable(intr_handle);
2037
2038         i40e_filter_restore(pf);
2039
2040         return I40E_SUCCESS;
2041
2042 err_up:
2043         i40e_dev_switch_queues(pf, FALSE);
2044         i40e_dev_clear_queues(dev);
2045
2046         return ret;
2047 }
2048
2049 static void
2050 i40e_dev_stop(struct rte_eth_dev *dev)
2051 {
2052         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2053         struct i40e_vsi *main_vsi = pf->main_vsi;
2054         struct i40e_mirror_rule *p_mirror;
2055         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2056         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2057         int i;
2058
2059         /* Disable all queues */
2060         i40e_dev_switch_queues(pf, FALSE);
2061
2062         /* un-map queues with interrupt registers */
2063         i40e_vsi_disable_queues_intr(main_vsi);
2064         i40e_vsi_queues_unbind_intr(main_vsi);
2065
2066         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2067                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2068                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2069         }
2070
2071         if (pf->fdir.fdir_vsi) {
2072                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2073                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2074         }
2075         /* Clear all queues and release memory */
2076         i40e_dev_clear_queues(dev);
2077
2078         /* Set link down */
2079         i40e_dev_set_link_down(dev);
2080
2081         /* Remove all mirror rules */
2082         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2083                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2084                 rte_free(p_mirror);
2085         }
2086         pf->nb_mirror_rule = 0;
2087
2088         if (!rte_intr_allow_others(intr_handle))
2089                 /* resume to the default handler */
2090                 rte_intr_callback_register(intr_handle,
2091                                            i40e_dev_interrupt_handler,
2092                                            (void *)dev);
2093
2094         /* Clean datapath event and queue/vec mapping */
2095         rte_intr_efd_disable(intr_handle);
2096         if (intr_handle->intr_vec) {
2097                 rte_free(intr_handle->intr_vec);
2098                 intr_handle->intr_vec = NULL;
2099         }
2100 }
2101
2102 static void
2103 i40e_dev_close(struct rte_eth_dev *dev)
2104 {
2105         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2106         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2108         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2109         uint32_t reg;
2110         int i;
2111
2112         PMD_INIT_FUNC_TRACE();
2113
2114         i40e_dev_stop(dev);
2115         hw->adapter_stopped = 1;
2116         i40e_dev_free_queues(dev);
2117
2118         /* Disable interrupt */
2119         i40e_pf_disable_irq0(hw);
2120         rte_intr_disable(intr_handle);
2121
2122         /* shutdown and destroy the HMC */
2123         i40e_shutdown_lan_hmc(hw);
2124
2125         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2126                 i40e_vsi_release(pf->vmdq[i].vsi);
2127                 pf->vmdq[i].vsi = NULL;
2128         }
2129         rte_free(pf->vmdq);
2130         pf->vmdq = NULL;
2131
2132         /* release all the existing VSIs and VEBs */
2133         i40e_fdir_teardown(pf);
2134         i40e_vsi_release(pf->main_vsi);
2135
2136         /* shutdown the adminq */
2137         i40e_aq_queue_shutdown(hw, true);
2138         i40e_shutdown_adminq(hw);
2139
2140         i40e_res_pool_destroy(&pf->qp_pool);
2141         i40e_res_pool_destroy(&pf->msix_pool);
2142
2143         /* force a PF reset to clean anything leftover */
2144         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2145         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2146                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2147         I40E_WRITE_FLUSH(hw);
2148 }
2149
2150 static void
2151 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2152 {
2153         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2154         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2155         struct i40e_vsi *vsi = pf->main_vsi;
2156         int status;
2157
2158         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2159                                                      true, NULL, true);
2160         if (status != I40E_SUCCESS)
2161                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2162
2163         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2164                                                         TRUE, NULL);
2165         if (status != I40E_SUCCESS)
2166                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2167
2168 }
2169
2170 static void
2171 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2172 {
2173         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2174         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2175         struct i40e_vsi *vsi = pf->main_vsi;
2176         int status;
2177
2178         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2179                                                      false, NULL, true);
2180         if (status != I40E_SUCCESS)
2181                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2182
2183         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2184                                                         false, NULL);
2185         if (status != I40E_SUCCESS)
2186                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2187 }
2188
2189 static void
2190 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2191 {
2192         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2193         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2194         struct i40e_vsi *vsi = pf->main_vsi;
2195         int ret;
2196
2197         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2198         if (ret != I40E_SUCCESS)
2199                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2200 }
2201
2202 static void
2203 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2204 {
2205         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2206         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2207         struct i40e_vsi *vsi = pf->main_vsi;
2208         int ret;
2209
2210         if (dev->data->promiscuous == 1)
2211                 return; /* must remain in all_multicast mode */
2212
2213         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2214                                 vsi->seid, FALSE, NULL);
2215         if (ret != I40E_SUCCESS)
2216                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2217 }
2218
2219 /*
2220  * Set device link up.
2221  */
2222 static int
2223 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2224 {
2225         /* re-apply link speed setting */
2226         return i40e_apply_link_speed(dev);
2227 }
2228
2229 /*
2230  * Set device link down.
2231  */
2232 static int
2233 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2234 {
2235         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2236         uint8_t abilities = 0;
2237         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238
2239         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2240         return i40e_phy_conf_link(hw, abilities, speed);
2241 }
2242
2243 int
2244 i40e_dev_link_update(struct rte_eth_dev *dev,
2245                      int wait_to_complete)
2246 {
2247 #define CHECK_INTERVAL 100  /* 100ms */
2248 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2249         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2250         struct i40e_link_status link_status;
2251         struct rte_eth_link link, old;
2252         int status;
2253         unsigned rep_cnt = MAX_REPEAT_TIME;
2254         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2255
2256         memset(&link, 0, sizeof(link));
2257         memset(&old, 0, sizeof(old));
2258         memset(&link_status, 0, sizeof(link_status));
2259         rte_i40e_dev_atomic_read_link_status(dev, &old);
2260
2261         do {
2262                 /* Get link status information from hardware */
2263                 status = i40e_aq_get_link_info(hw, enable_lse,
2264                                                 &link_status, NULL);
2265                 if (status != I40E_SUCCESS) {
2266                         link.link_speed = ETH_SPEED_NUM_100M;
2267                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2268                         PMD_DRV_LOG(ERR, "Failed to get link info");
2269                         goto out;
2270                 }
2271
2272                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2273                 if (!wait_to_complete || link.link_status)
2274                         break;
2275
2276                 rte_delay_ms(CHECK_INTERVAL);
2277         } while (--rep_cnt);
2278
2279         if (!link.link_status)
2280                 goto out;
2281
2282         /* i40e uses full duplex only */
2283         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2284
2285         /* Parse the link status */
2286         switch (link_status.link_speed) {
2287         case I40E_LINK_SPEED_100MB:
2288                 link.link_speed = ETH_SPEED_NUM_100M;
2289                 break;
2290         case I40E_LINK_SPEED_1GB:
2291                 link.link_speed = ETH_SPEED_NUM_1G;
2292                 break;
2293         case I40E_LINK_SPEED_10GB:
2294                 link.link_speed = ETH_SPEED_NUM_10G;
2295                 break;
2296         case I40E_LINK_SPEED_20GB:
2297                 link.link_speed = ETH_SPEED_NUM_20G;
2298                 break;
2299         case I40E_LINK_SPEED_25GB:
2300                 link.link_speed = ETH_SPEED_NUM_25G;
2301                 break;
2302         case I40E_LINK_SPEED_40GB:
2303                 link.link_speed = ETH_SPEED_NUM_40G;
2304                 break;
2305         default:
2306                 link.link_speed = ETH_SPEED_NUM_100M;
2307                 break;
2308         }
2309
2310         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2311                         ETH_LINK_SPEED_FIXED);
2312
2313 out:
2314         rte_i40e_dev_atomic_write_link_status(dev, &link);
2315         if (link.link_status == old.link_status)
2316                 return -1;
2317
2318         return 0;
2319 }
2320
2321 /* Get all the statistics of a VSI */
2322 void
2323 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2324 {
2325         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2326         struct i40e_eth_stats *nes = &vsi->eth_stats;
2327         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2328         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2329
2330         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2331                             vsi->offset_loaded, &oes->rx_bytes,
2332                             &nes->rx_bytes);
2333         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2334                             vsi->offset_loaded, &oes->rx_unicast,
2335                             &nes->rx_unicast);
2336         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2337                             vsi->offset_loaded, &oes->rx_multicast,
2338                             &nes->rx_multicast);
2339         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2340                             vsi->offset_loaded, &oes->rx_broadcast,
2341                             &nes->rx_broadcast);
2342         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2343                             &oes->rx_discards, &nes->rx_discards);
2344         /* GLV_REPC not supported */
2345         /* GLV_RMPC not supported */
2346         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2347                             &oes->rx_unknown_protocol,
2348                             &nes->rx_unknown_protocol);
2349         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2350                             vsi->offset_loaded, &oes->tx_bytes,
2351                             &nes->tx_bytes);
2352         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2353                             vsi->offset_loaded, &oes->tx_unicast,
2354                             &nes->tx_unicast);
2355         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2356                             vsi->offset_loaded, &oes->tx_multicast,
2357                             &nes->tx_multicast);
2358         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2359                             vsi->offset_loaded,  &oes->tx_broadcast,
2360                             &nes->tx_broadcast);
2361         /* GLV_TDPC not supported */
2362         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2363                             &oes->tx_errors, &nes->tx_errors);
2364         vsi->offset_loaded = true;
2365
2366         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2367                     vsi->vsi_id);
2368         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2369         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2370         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2371         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2372         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2373         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2374                     nes->rx_unknown_protocol);
2375         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2376         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2377         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2378         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2379         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2380         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2381         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2382                     vsi->vsi_id);
2383 }
2384
2385 static void
2386 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2387 {
2388         unsigned int i;
2389         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2390         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2391
2392         /* Get statistics of struct i40e_eth_stats */
2393         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2394                             I40E_GLPRT_GORCL(hw->port),
2395                             pf->offset_loaded, &os->eth.rx_bytes,
2396                             &ns->eth.rx_bytes);
2397         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2398                             I40E_GLPRT_UPRCL(hw->port),
2399                             pf->offset_loaded, &os->eth.rx_unicast,
2400                             &ns->eth.rx_unicast);
2401         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2402                             I40E_GLPRT_MPRCL(hw->port),
2403                             pf->offset_loaded, &os->eth.rx_multicast,
2404                             &ns->eth.rx_multicast);
2405         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2406                             I40E_GLPRT_BPRCL(hw->port),
2407                             pf->offset_loaded, &os->eth.rx_broadcast,
2408                             &ns->eth.rx_broadcast);
2409         /* Workaround: CRC size should not be included in byte statistics,
2410          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2411          */
2412         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2413                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2414
2415         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2416                             pf->offset_loaded, &os->eth.rx_discards,
2417                             &ns->eth.rx_discards);
2418         /* GLPRT_REPC not supported */
2419         /* GLPRT_RMPC not supported */
2420         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2421                             pf->offset_loaded,
2422                             &os->eth.rx_unknown_protocol,
2423                             &ns->eth.rx_unknown_protocol);
2424         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2425                             I40E_GLPRT_GOTCL(hw->port),
2426                             pf->offset_loaded, &os->eth.tx_bytes,
2427                             &ns->eth.tx_bytes);
2428         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2429                             I40E_GLPRT_UPTCL(hw->port),
2430                             pf->offset_loaded, &os->eth.tx_unicast,
2431                             &ns->eth.tx_unicast);
2432         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2433                             I40E_GLPRT_MPTCL(hw->port),
2434                             pf->offset_loaded, &os->eth.tx_multicast,
2435                             &ns->eth.tx_multicast);
2436         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2437                             I40E_GLPRT_BPTCL(hw->port),
2438                             pf->offset_loaded, &os->eth.tx_broadcast,
2439                             &ns->eth.tx_broadcast);
2440         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2441                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2442         /* GLPRT_TEPC not supported */
2443
2444         /* additional port specific stats */
2445         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2446                             pf->offset_loaded, &os->tx_dropped_link_down,
2447                             &ns->tx_dropped_link_down);
2448         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2449                             pf->offset_loaded, &os->crc_errors,
2450                             &ns->crc_errors);
2451         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2452                             pf->offset_loaded, &os->illegal_bytes,
2453                             &ns->illegal_bytes);
2454         /* GLPRT_ERRBC not supported */
2455         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2456                             pf->offset_loaded, &os->mac_local_faults,
2457                             &ns->mac_local_faults);
2458         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2459                             pf->offset_loaded, &os->mac_remote_faults,
2460                             &ns->mac_remote_faults);
2461         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2462                             pf->offset_loaded, &os->rx_length_errors,
2463                             &ns->rx_length_errors);
2464         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2465                             pf->offset_loaded, &os->link_xon_rx,
2466                             &ns->link_xon_rx);
2467         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2468                             pf->offset_loaded, &os->link_xoff_rx,
2469                             &ns->link_xoff_rx);
2470         for (i = 0; i < 8; i++) {
2471                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2472                                     pf->offset_loaded,
2473                                     &os->priority_xon_rx[i],
2474                                     &ns->priority_xon_rx[i]);
2475                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2476                                     pf->offset_loaded,
2477                                     &os->priority_xoff_rx[i],
2478                                     &ns->priority_xoff_rx[i]);
2479         }
2480         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2481                             pf->offset_loaded, &os->link_xon_tx,
2482                             &ns->link_xon_tx);
2483         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2484                             pf->offset_loaded, &os->link_xoff_tx,
2485                             &ns->link_xoff_tx);
2486         for (i = 0; i < 8; i++) {
2487                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2488                                     pf->offset_loaded,
2489                                     &os->priority_xon_tx[i],
2490                                     &ns->priority_xon_tx[i]);
2491                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2492                                     pf->offset_loaded,
2493                                     &os->priority_xoff_tx[i],
2494                                     &ns->priority_xoff_tx[i]);
2495                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2496                                     pf->offset_loaded,
2497                                     &os->priority_xon_2_xoff[i],
2498                                     &ns->priority_xon_2_xoff[i]);
2499         }
2500         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2501                             I40E_GLPRT_PRC64L(hw->port),
2502                             pf->offset_loaded, &os->rx_size_64,
2503                             &ns->rx_size_64);
2504         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2505                             I40E_GLPRT_PRC127L(hw->port),
2506                             pf->offset_loaded, &os->rx_size_127,
2507                             &ns->rx_size_127);
2508         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2509                             I40E_GLPRT_PRC255L(hw->port),
2510                             pf->offset_loaded, &os->rx_size_255,
2511                             &ns->rx_size_255);
2512         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2513                             I40E_GLPRT_PRC511L(hw->port),
2514                             pf->offset_loaded, &os->rx_size_511,
2515                             &ns->rx_size_511);
2516         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2517                             I40E_GLPRT_PRC1023L(hw->port),
2518                             pf->offset_loaded, &os->rx_size_1023,
2519                             &ns->rx_size_1023);
2520         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2521                             I40E_GLPRT_PRC1522L(hw->port),
2522                             pf->offset_loaded, &os->rx_size_1522,
2523                             &ns->rx_size_1522);
2524         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2525                             I40E_GLPRT_PRC9522L(hw->port),
2526                             pf->offset_loaded, &os->rx_size_big,
2527                             &ns->rx_size_big);
2528         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2529                             pf->offset_loaded, &os->rx_undersize,
2530                             &ns->rx_undersize);
2531         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2532                             pf->offset_loaded, &os->rx_fragments,
2533                             &ns->rx_fragments);
2534         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2535                             pf->offset_loaded, &os->rx_oversize,
2536                             &ns->rx_oversize);
2537         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2538                             pf->offset_loaded, &os->rx_jabber,
2539                             &ns->rx_jabber);
2540         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2541                             I40E_GLPRT_PTC64L(hw->port),
2542                             pf->offset_loaded, &os->tx_size_64,
2543                             &ns->tx_size_64);
2544         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2545                             I40E_GLPRT_PTC127L(hw->port),
2546                             pf->offset_loaded, &os->tx_size_127,
2547                             &ns->tx_size_127);
2548         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2549                             I40E_GLPRT_PTC255L(hw->port),
2550                             pf->offset_loaded, &os->tx_size_255,
2551                             &ns->tx_size_255);
2552         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2553                             I40E_GLPRT_PTC511L(hw->port),
2554                             pf->offset_loaded, &os->tx_size_511,
2555                             &ns->tx_size_511);
2556         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2557                             I40E_GLPRT_PTC1023L(hw->port),
2558                             pf->offset_loaded, &os->tx_size_1023,
2559                             &ns->tx_size_1023);
2560         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2561                             I40E_GLPRT_PTC1522L(hw->port),
2562                             pf->offset_loaded, &os->tx_size_1522,
2563                             &ns->tx_size_1522);
2564         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2565                             I40E_GLPRT_PTC9522L(hw->port),
2566                             pf->offset_loaded, &os->tx_size_big,
2567                             &ns->tx_size_big);
2568         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2569                            pf->offset_loaded,
2570                            &os->fd_sb_match, &ns->fd_sb_match);
2571         /* GLPRT_MSPDC not supported */
2572         /* GLPRT_XEC not supported */
2573
2574         pf->offset_loaded = true;
2575
2576         if (pf->main_vsi)
2577                 i40e_update_vsi_stats(pf->main_vsi);
2578 }
2579
2580 /* Get all statistics of a port */
2581 static void
2582 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2583 {
2584         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2585         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2586         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2587         unsigned i;
2588
2589         /* call read registers - updates values, now write them to struct */
2590         i40e_read_stats_registers(pf, hw);
2591
2592         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2593                         pf->main_vsi->eth_stats.rx_multicast +
2594                         pf->main_vsi->eth_stats.rx_broadcast -
2595                         pf->main_vsi->eth_stats.rx_discards;
2596         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2597                         pf->main_vsi->eth_stats.tx_multicast +
2598                         pf->main_vsi->eth_stats.tx_broadcast;
2599         stats->ibytes   = ns->eth.rx_bytes;
2600         stats->obytes   = ns->eth.tx_bytes;
2601         stats->oerrors  = ns->eth.tx_errors +
2602                         pf->main_vsi->eth_stats.tx_errors;
2603
2604         /* Rx Errors */
2605         stats->imissed  = ns->eth.rx_discards +
2606                         pf->main_vsi->eth_stats.rx_discards;
2607         stats->ierrors  = ns->crc_errors +
2608                         ns->rx_length_errors + ns->rx_undersize +
2609                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2610
2611         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2612         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2613         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2614         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2615         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2616         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2617         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2618                     ns->eth.rx_unknown_protocol);
2619         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2620         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2621         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2622         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2623         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2624         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2625
2626         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2627                     ns->tx_dropped_link_down);
2628         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2629         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2630                     ns->illegal_bytes);
2631         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2632         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2633                     ns->mac_local_faults);
2634         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2635                     ns->mac_remote_faults);
2636         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2637                     ns->rx_length_errors);
2638         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2639         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2640         for (i = 0; i < 8; i++) {
2641                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2642                                 i, ns->priority_xon_rx[i]);
2643                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2644                                 i, ns->priority_xoff_rx[i]);
2645         }
2646         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2647         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2648         for (i = 0; i < 8; i++) {
2649                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2650                                 i, ns->priority_xon_tx[i]);
2651                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2652                                 i, ns->priority_xoff_tx[i]);
2653                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2654                                 i, ns->priority_xon_2_xoff[i]);
2655         }
2656         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2657         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2658         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2659         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2660         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2661         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2662         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2663         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2664         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2665         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2666         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2667         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2668         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2669         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2670         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2671         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2672         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2673         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2674         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2675                         ns->mac_short_packet_dropped);
2676         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2677                     ns->checksum_error);
2678         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2679         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2680 }
2681
2682 /* Reset the statistics */
2683 static void
2684 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2685 {
2686         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2687         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2688
2689         /* Mark PF and VSI stats to update the offset, aka "reset" */
2690         pf->offset_loaded = false;
2691         if (pf->main_vsi)
2692                 pf->main_vsi->offset_loaded = false;
2693
2694         /* read the stats, reading current register values into offset */
2695         i40e_read_stats_registers(pf, hw);
2696 }
2697
2698 static uint32_t
2699 i40e_xstats_calc_num(void)
2700 {
2701         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2702                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2703                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2704 }
2705
2706 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2707                                      struct rte_eth_xstat_name *xstats_names,
2708                                      __rte_unused unsigned limit)
2709 {
2710         unsigned count = 0;
2711         unsigned i, prio;
2712
2713         if (xstats_names == NULL)
2714                 return i40e_xstats_calc_num();
2715
2716         /* Note: limit checked in rte_eth_xstats_names() */
2717
2718         /* Get stats from i40e_eth_stats struct */
2719         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2720                 snprintf(xstats_names[count].name,
2721                          sizeof(xstats_names[count].name),
2722                          "%s", rte_i40e_stats_strings[i].name);
2723                 count++;
2724         }
2725
2726         /* Get individiual stats from i40e_hw_port struct */
2727         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2728                 snprintf(xstats_names[count].name,
2729                         sizeof(xstats_names[count].name),
2730                          "%s", rte_i40e_hw_port_strings[i].name);
2731                 count++;
2732         }
2733
2734         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2735                 for (prio = 0; prio < 8; prio++) {
2736                         snprintf(xstats_names[count].name,
2737                                  sizeof(xstats_names[count].name),
2738                                  "rx_priority%u_%s", prio,
2739                                  rte_i40e_rxq_prio_strings[i].name);
2740                         count++;
2741                 }
2742         }
2743
2744         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2745                 for (prio = 0; prio < 8; prio++) {
2746                         snprintf(xstats_names[count].name,
2747                                  sizeof(xstats_names[count].name),
2748                                  "tx_priority%u_%s", prio,
2749                                  rte_i40e_txq_prio_strings[i].name);
2750                         count++;
2751                 }
2752         }
2753         return count;
2754 }
2755
2756 static int
2757 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2758                     unsigned n)
2759 {
2760         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2761         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2762         unsigned i, count, prio;
2763         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2764
2765         count = i40e_xstats_calc_num();
2766         if (n < count)
2767                 return count;
2768
2769         i40e_read_stats_registers(pf, hw);
2770
2771         if (xstats == NULL)
2772                 return 0;
2773
2774         count = 0;
2775
2776         /* Get stats from i40e_eth_stats struct */
2777         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2778                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2779                         rte_i40e_stats_strings[i].offset);
2780                 xstats[count].id = count;
2781                 count++;
2782         }
2783
2784         /* Get individiual stats from i40e_hw_port struct */
2785         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2786                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2787                         rte_i40e_hw_port_strings[i].offset);
2788                 xstats[count].id = count;
2789                 count++;
2790         }
2791
2792         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2793                 for (prio = 0; prio < 8; prio++) {
2794                         xstats[count].value =
2795                                 *(uint64_t *)(((char *)hw_stats) +
2796                                 rte_i40e_rxq_prio_strings[i].offset +
2797                                 (sizeof(uint64_t) * prio));
2798                         xstats[count].id = count;
2799                         count++;
2800                 }
2801         }
2802
2803         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2804                 for (prio = 0; prio < 8; prio++) {
2805                         xstats[count].value =
2806                                 *(uint64_t *)(((char *)hw_stats) +
2807                                 rte_i40e_txq_prio_strings[i].offset +
2808                                 (sizeof(uint64_t) * prio));
2809                         xstats[count].id = count;
2810                         count++;
2811                 }
2812         }
2813
2814         return count;
2815 }
2816
2817 static int
2818 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2819                                  __rte_unused uint16_t queue_id,
2820                                  __rte_unused uint8_t stat_idx,
2821                                  __rte_unused uint8_t is_rx)
2822 {
2823         PMD_INIT_FUNC_TRACE();
2824
2825         return -ENOSYS;
2826 }
2827
2828 static int
2829 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2830 {
2831         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2832         u32 full_ver;
2833         u8 ver, patch;
2834         u16 build;
2835         int ret;
2836
2837         full_ver = hw->nvm.oem_ver;
2838         ver = (u8)(full_ver >> 24);
2839         build = (u16)((full_ver >> 8) & 0xffff);
2840         patch = (u8)(full_ver & 0xff);
2841
2842         ret = snprintf(fw_version, fw_size,
2843                  "%d.%d%d 0x%08x %d.%d.%d",
2844                  ((hw->nvm.version >> 12) & 0xf),
2845                  ((hw->nvm.version >> 4) & 0xff),
2846                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2847                  ver, build, patch);
2848
2849         ret += 1; /* add the size of '\0' */
2850         if (fw_size < (u32)ret)
2851                 return ret;
2852         else
2853                 return 0;
2854 }
2855
2856 static void
2857 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2858 {
2859         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2860         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2861         struct i40e_vsi *vsi = pf->main_vsi;
2862         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2863
2864         dev_info->pci_dev = pci_dev;
2865         dev_info->max_rx_queues = vsi->nb_qps;
2866         dev_info->max_tx_queues = vsi->nb_qps;
2867         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2868         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2869         dev_info->max_mac_addrs = vsi->max_macaddrs;
2870         dev_info->max_vfs = pci_dev->max_vfs;
2871         dev_info->rx_offload_capa =
2872                 DEV_RX_OFFLOAD_VLAN_STRIP |
2873                 DEV_RX_OFFLOAD_QINQ_STRIP |
2874                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2875                 DEV_RX_OFFLOAD_UDP_CKSUM |
2876                 DEV_RX_OFFLOAD_TCP_CKSUM;
2877         dev_info->tx_offload_capa =
2878                 DEV_TX_OFFLOAD_VLAN_INSERT |
2879                 DEV_TX_OFFLOAD_QINQ_INSERT |
2880                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2881                 DEV_TX_OFFLOAD_UDP_CKSUM |
2882                 DEV_TX_OFFLOAD_TCP_CKSUM |
2883                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2884                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2885                 DEV_TX_OFFLOAD_TCP_TSO |
2886                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2887                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2888                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2889                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2890         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2891                                                 sizeof(uint32_t);
2892         dev_info->reta_size = pf->hash_lut_size;
2893         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2894
2895         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2896                 .rx_thresh = {
2897                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2898                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2899                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2900                 },
2901                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2902                 .rx_drop_en = 0,
2903         };
2904
2905         dev_info->default_txconf = (struct rte_eth_txconf) {
2906                 .tx_thresh = {
2907                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2908                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2909                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2910                 },
2911                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2912                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2913                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2914                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2915         };
2916
2917         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2918                 .nb_max = I40E_MAX_RING_DESC,
2919                 .nb_min = I40E_MIN_RING_DESC,
2920                 .nb_align = I40E_ALIGN_RING_DESC,
2921         };
2922
2923         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2924                 .nb_max = I40E_MAX_RING_DESC,
2925                 .nb_min = I40E_MIN_RING_DESC,
2926                 .nb_align = I40E_ALIGN_RING_DESC,
2927                 .nb_seg_max = I40E_TX_MAX_SEG,
2928                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2929         };
2930
2931         if (pf->flags & I40E_FLAG_VMDQ) {
2932                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2933                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2934                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2935                                                 pf->max_nb_vmdq_vsi;
2936                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2937                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2938                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2939         }
2940
2941         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2942                 /* For XL710 */
2943                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2944         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2945                 /* For XXV710 */
2946                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2947         else
2948                 /* For X710 */
2949                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2950 }
2951
2952 static int
2953 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2954 {
2955         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2956         struct i40e_vsi *vsi = pf->main_vsi;
2957         PMD_INIT_FUNC_TRACE();
2958
2959         if (on)
2960                 return i40e_vsi_add_vlan(vsi, vlan_id);
2961         else
2962                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2963 }
2964
2965 static int
2966 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2967                    enum rte_vlan_type vlan_type,
2968                    uint16_t tpid)
2969 {
2970         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971         uint64_t reg_r = 0, reg_w = 0;
2972         uint16_t reg_id = 0;
2973         int ret = 0;
2974         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2975
2976         switch (vlan_type) {
2977         case ETH_VLAN_TYPE_OUTER:
2978                 if (qinq)
2979                         reg_id = 2;
2980                 else
2981                         reg_id = 3;
2982                 break;
2983         case ETH_VLAN_TYPE_INNER:
2984                 if (qinq)
2985                         reg_id = 3;
2986                 else {
2987                         ret = -EINVAL;
2988                         PMD_DRV_LOG(ERR,
2989                                 "Unsupported vlan type in single vlan.");
2990                         return ret;
2991                 }
2992                 break;
2993         default:
2994                 ret = -EINVAL;
2995                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2996                 return ret;
2997         }
2998         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2999                                           &reg_r, NULL);
3000         if (ret != I40E_SUCCESS) {
3001                 PMD_DRV_LOG(ERR,
3002                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3003                            reg_id);
3004                 ret = -EIO;
3005                 return ret;
3006         }
3007         PMD_DRV_LOG(DEBUG,
3008                 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3009                 reg_id, reg_r);
3010
3011         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3012         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3013         if (reg_r == reg_w) {
3014                 ret = 0;
3015                 PMD_DRV_LOG(DEBUG, "No need to write");
3016                 return ret;
3017         }
3018
3019         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3020                                            reg_w, NULL);
3021         if (ret != I40E_SUCCESS) {
3022                 ret = -EIO;
3023                 PMD_DRV_LOG(ERR,
3024                         "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3025                         reg_id);
3026                 return ret;
3027         }
3028         PMD_DRV_LOG(DEBUG,
3029                 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3030                 reg_w, reg_id);
3031
3032         return ret;
3033 }
3034
3035 static void
3036 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3037 {
3038         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3039         struct i40e_vsi *vsi = pf->main_vsi;
3040
3041         if (mask & ETH_VLAN_FILTER_MASK) {
3042                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3043                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3044                 else
3045                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3046         }
3047
3048         if (mask & ETH_VLAN_STRIP_MASK) {
3049                 /* Enable or disable VLAN stripping */
3050                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3051                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3052                 else
3053                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3054         }
3055
3056         if (mask & ETH_VLAN_EXTEND_MASK) {
3057                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3058                         i40e_vsi_config_double_vlan(vsi, TRUE);
3059                         /* Set global registers with default ether type value */
3060                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3061                                            ETHER_TYPE_VLAN);
3062                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3063                                            ETHER_TYPE_VLAN);
3064                 }
3065                 else
3066                         i40e_vsi_config_double_vlan(vsi, FALSE);
3067         }
3068 }
3069
3070 static void
3071 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3072                           __rte_unused uint16_t queue,
3073                           __rte_unused int on)
3074 {
3075         PMD_INIT_FUNC_TRACE();
3076 }
3077
3078 static int
3079 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3080 {
3081         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3082         struct i40e_vsi *vsi = pf->main_vsi;
3083         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3084         struct i40e_vsi_vlan_pvid_info info;
3085
3086         memset(&info, 0, sizeof(info));
3087         info.on = on;
3088         if (info.on)
3089                 info.config.pvid = pvid;
3090         else {
3091                 info.config.reject.tagged =
3092                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3093                 info.config.reject.untagged =
3094                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3095         }
3096
3097         return i40e_vsi_vlan_pvid_set(vsi, &info);
3098 }
3099
3100 static int
3101 i40e_dev_led_on(struct rte_eth_dev *dev)
3102 {
3103         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3104         uint32_t mode = i40e_led_get(hw);
3105
3106         if (mode == 0)
3107                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3108
3109         return 0;
3110 }
3111
3112 static int
3113 i40e_dev_led_off(struct rte_eth_dev *dev)
3114 {
3115         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3116         uint32_t mode = i40e_led_get(hw);
3117
3118         if (mode != 0)
3119                 i40e_led_set(hw, 0, false);
3120
3121         return 0;
3122 }
3123
3124 static int
3125 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3126 {
3127         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3128         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3129
3130         fc_conf->pause_time = pf->fc_conf.pause_time;
3131         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3132         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3133
3134          /* Return current mode according to actual setting*/
3135         switch (hw->fc.current_mode) {
3136         case I40E_FC_FULL:
3137                 fc_conf->mode = RTE_FC_FULL;
3138                 break;
3139         case I40E_FC_TX_PAUSE:
3140                 fc_conf->mode = RTE_FC_TX_PAUSE;
3141                 break;
3142         case I40E_FC_RX_PAUSE:
3143                 fc_conf->mode = RTE_FC_RX_PAUSE;
3144                 break;
3145         case I40E_FC_NONE:
3146         default:
3147                 fc_conf->mode = RTE_FC_NONE;
3148         };
3149
3150         return 0;
3151 }
3152
3153 static int
3154 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3155 {
3156         uint32_t mflcn_reg, fctrl_reg, reg;
3157         uint32_t max_high_water;
3158         uint8_t i, aq_failure;
3159         int err;
3160         struct i40e_hw *hw;
3161         struct i40e_pf *pf;
3162         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3163                 [RTE_FC_NONE] = I40E_FC_NONE,
3164                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3165                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3166                 [RTE_FC_FULL] = I40E_FC_FULL
3167         };
3168
3169         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3170
3171         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3172         if ((fc_conf->high_water > max_high_water) ||
3173                         (fc_conf->high_water < fc_conf->low_water)) {
3174                 PMD_INIT_LOG(ERR,
3175                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3176                         max_high_water);
3177                 return -EINVAL;
3178         }
3179
3180         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3181         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3182         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3183
3184         pf->fc_conf.pause_time = fc_conf->pause_time;
3185         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3186         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3187
3188         PMD_INIT_FUNC_TRACE();
3189
3190         /* All the link flow control related enable/disable register
3191          * configuration is handle by the F/W
3192          */
3193         err = i40e_set_fc(hw, &aq_failure, true);
3194         if (err < 0)
3195                 return -ENOSYS;
3196
3197         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3198                 /* Configure flow control refresh threshold,
3199                  * the value for stat_tx_pause_refresh_timer[8]
3200                  * is used for global pause operation.
3201                  */
3202
3203                 I40E_WRITE_REG(hw,
3204                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3205                                pf->fc_conf.pause_time);
3206
3207                 /* configure the timer value included in transmitted pause
3208                  * frame,
3209                  * the value for stat_tx_pause_quanta[8] is used for global
3210                  * pause operation
3211                  */
3212                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3213                                pf->fc_conf.pause_time);
3214
3215                 fctrl_reg = I40E_READ_REG(hw,
3216                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3217
3218                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3219                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3220                 else
3221                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3222
3223                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3224                                fctrl_reg);
3225         } else {
3226                 /* Configure pause time (2 TCs per register) */
3227                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3228                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3229                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3230
3231                 /* Configure flow control refresh threshold value */
3232                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3233                                pf->fc_conf.pause_time / 2);
3234
3235                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3236
3237                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3238                  *depending on configuration
3239                  */
3240                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3241                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3242                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3243                 } else {
3244                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3245                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3246                 }
3247
3248                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3249         }
3250
3251         /* config the water marker both based on the packets and bytes */
3252         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3253                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3254                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3255         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3256                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3257                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3258         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3259                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3260                        << I40E_KILOSHIFT);
3261         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3262                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3263                        << I40E_KILOSHIFT);
3264
3265         I40E_WRITE_FLUSH(hw);
3266
3267         return 0;
3268 }
3269
3270 static int
3271 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3272                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3273 {
3274         PMD_INIT_FUNC_TRACE();
3275
3276         return -ENOSYS;
3277 }
3278
3279 /* Add a MAC address, and update filters */
3280 static void
3281 i40e_macaddr_add(struct rte_eth_dev *dev,
3282                  struct ether_addr *mac_addr,
3283                  __rte_unused uint32_t index,
3284                  uint32_t pool)
3285 {
3286         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3287         struct i40e_mac_filter_info mac_filter;
3288         struct i40e_vsi *vsi;
3289         int ret;
3290
3291         /* If VMDQ not enabled or configured, return */
3292         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3293                           !pf->nb_cfg_vmdq_vsi)) {
3294                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3295                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3296                         pool);
3297                 return;
3298         }
3299
3300         if (pool > pf->nb_cfg_vmdq_vsi) {
3301                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3302                                 pool, pf->nb_cfg_vmdq_vsi);
3303                 return;
3304         }
3305
3306         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3307         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3308                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3309         else
3310                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3311
3312         if (pool == 0)
3313                 vsi = pf->main_vsi;
3314         else
3315                 vsi = pf->vmdq[pool - 1].vsi;
3316
3317         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3318         if (ret != I40E_SUCCESS) {
3319                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3320                 return;
3321         }
3322 }
3323
3324 /* Remove a MAC address, and update filters */
3325 static void
3326 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3327 {
3328         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3329         struct i40e_vsi *vsi;
3330         struct rte_eth_dev_data *data = dev->data;
3331         struct ether_addr *macaddr;
3332         int ret;
3333         uint32_t i;
3334         uint64_t pool_sel;
3335
3336         macaddr = &(data->mac_addrs[index]);
3337
3338         pool_sel = dev->data->mac_pool_sel[index];
3339
3340         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3341                 if (pool_sel & (1ULL << i)) {
3342                         if (i == 0)
3343                                 vsi = pf->main_vsi;
3344                         else {
3345                                 /* No VMDQ pool enabled or configured */
3346                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3347                                         (i > pf->nb_cfg_vmdq_vsi)) {
3348                                         PMD_DRV_LOG(ERR,
3349                                                 "No VMDQ pool enabled/configured");
3350                                         return;
3351                                 }
3352                                 vsi = pf->vmdq[i - 1].vsi;
3353                         }
3354                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3355
3356                         if (ret) {
3357                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3358                                 return;
3359                         }
3360                 }
3361         }
3362 }
3363
3364 /* Set perfect match or hash match of MAC and VLAN for a VF */
3365 static int
3366 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3367                  struct rte_eth_mac_filter *filter,
3368                  bool add)
3369 {
3370         struct i40e_hw *hw;
3371         struct i40e_mac_filter_info mac_filter;
3372         struct ether_addr old_mac;
3373         struct ether_addr *new_mac;
3374         struct i40e_pf_vf *vf = NULL;
3375         uint16_t vf_id;
3376         int ret;
3377
3378         if (pf == NULL) {
3379                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3380                 return -EINVAL;
3381         }
3382         hw = I40E_PF_TO_HW(pf);
3383
3384         if (filter == NULL) {
3385                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3386                 return -EINVAL;
3387         }
3388
3389         new_mac = &filter->mac_addr;
3390
3391         if (is_zero_ether_addr(new_mac)) {
3392                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3393                 return -EINVAL;
3394         }
3395
3396         vf_id = filter->dst_id;
3397
3398         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3399                 PMD_DRV_LOG(ERR, "Invalid argument.");
3400                 return -EINVAL;
3401         }
3402         vf = &pf->vfs[vf_id];
3403
3404         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3405                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3406                 return -EINVAL;
3407         }
3408
3409         if (add) {
3410                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3411                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3412                                 ETHER_ADDR_LEN);
3413                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3414                                  ETHER_ADDR_LEN);
3415
3416                 mac_filter.filter_type = filter->filter_type;
3417                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3418                 if (ret != I40E_SUCCESS) {
3419                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3420                         return -1;
3421                 }
3422                 ether_addr_copy(new_mac, &pf->dev_addr);
3423         } else {
3424                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3425                                 ETHER_ADDR_LEN);
3426                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3427                 if (ret != I40E_SUCCESS) {
3428                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3429                         return -1;
3430                 }
3431
3432                 /* Clear device address as it has been removed */
3433                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3434                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3435         }
3436
3437         return 0;
3438 }
3439
3440 /* MAC filter handle */
3441 static int
3442 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3443                 void *arg)
3444 {
3445         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3446         struct rte_eth_mac_filter *filter;
3447         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3448         int ret = I40E_NOT_SUPPORTED;
3449
3450         filter = (struct rte_eth_mac_filter *)(arg);
3451
3452         switch (filter_op) {
3453         case RTE_ETH_FILTER_NOP:
3454                 ret = I40E_SUCCESS;
3455                 break;
3456         case RTE_ETH_FILTER_ADD:
3457                 i40e_pf_disable_irq0(hw);
3458                 if (filter->is_vf)
3459                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3460                 i40e_pf_enable_irq0(hw);
3461                 break;
3462         case RTE_ETH_FILTER_DELETE:
3463                 i40e_pf_disable_irq0(hw);
3464                 if (filter->is_vf)
3465                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3466                 i40e_pf_enable_irq0(hw);
3467                 break;
3468         default:
3469                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3470                 ret = I40E_ERR_PARAM;
3471                 break;
3472         }
3473
3474         return ret;
3475 }
3476
3477 static int
3478 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3479 {
3480         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3481         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3482         int ret;
3483
3484         if (!lut)
3485                 return -EINVAL;
3486
3487         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3488                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3489                                           lut, lut_size);
3490                 if (ret) {
3491                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3492                         return ret;
3493                 }
3494         } else {
3495                 uint32_t *lut_dw = (uint32_t *)lut;
3496                 uint16_t i, lut_size_dw = lut_size / 4;
3497
3498                 for (i = 0; i < lut_size_dw; i++)
3499                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3500         }
3501
3502         return 0;
3503 }
3504
3505 static int
3506 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3507 {
3508         struct i40e_pf *pf;
3509         struct i40e_hw *hw;
3510         int ret;
3511
3512         if (!vsi || !lut)
3513                 return -EINVAL;
3514
3515         pf = I40E_VSI_TO_PF(vsi);
3516         hw = I40E_VSI_TO_HW(vsi);
3517
3518         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3519                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3520                                           lut, lut_size);
3521                 if (ret) {
3522                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3523                         return ret;
3524                 }
3525         } else {
3526                 uint32_t *lut_dw = (uint32_t *)lut;
3527                 uint16_t i, lut_size_dw = lut_size / 4;
3528
3529                 for (i = 0; i < lut_size_dw; i++)
3530                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3531                 I40E_WRITE_FLUSH(hw);
3532         }
3533
3534         return 0;
3535 }
3536
3537 static int
3538 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3539                          struct rte_eth_rss_reta_entry64 *reta_conf,
3540                          uint16_t reta_size)
3541 {
3542         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3543         uint16_t i, lut_size = pf->hash_lut_size;
3544         uint16_t idx, shift;
3545         uint8_t *lut;
3546         int ret;
3547
3548         if (reta_size != lut_size ||
3549                 reta_size > ETH_RSS_RETA_SIZE_512) {
3550                 PMD_DRV_LOG(ERR,
3551                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3552                         reta_size, lut_size);
3553                 return -EINVAL;
3554         }
3555
3556         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3557         if (!lut) {
3558                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3559                 return -ENOMEM;
3560         }
3561         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3562         if (ret)
3563                 goto out;
3564         for (i = 0; i < reta_size; i++) {
3565                 idx = i / RTE_RETA_GROUP_SIZE;
3566                 shift = i % RTE_RETA_GROUP_SIZE;
3567                 if (reta_conf[idx].mask & (1ULL << shift))
3568                         lut[i] = reta_conf[idx].reta[shift];
3569         }
3570         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3571
3572 out:
3573         rte_free(lut);
3574
3575         return ret;
3576 }
3577
3578 static int
3579 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3580                         struct rte_eth_rss_reta_entry64 *reta_conf,
3581                         uint16_t reta_size)
3582 {
3583         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3584         uint16_t i, lut_size = pf->hash_lut_size;
3585         uint16_t idx, shift;
3586         uint8_t *lut;
3587         int ret;
3588
3589         if (reta_size != lut_size ||
3590                 reta_size > ETH_RSS_RETA_SIZE_512) {
3591                 PMD_DRV_LOG(ERR,
3592                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3593                         reta_size, lut_size);
3594                 return -EINVAL;
3595         }
3596
3597         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3598         if (!lut) {
3599                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3600                 return -ENOMEM;
3601         }
3602
3603         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3604         if (ret)
3605                 goto out;
3606         for (i = 0; i < reta_size; i++) {
3607                 idx = i / RTE_RETA_GROUP_SIZE;
3608                 shift = i % RTE_RETA_GROUP_SIZE;
3609                 if (reta_conf[idx].mask & (1ULL << shift))
3610                         reta_conf[idx].reta[shift] = lut[i];
3611         }
3612
3613 out:
3614         rte_free(lut);
3615
3616         return ret;
3617 }
3618
3619 /**
3620  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3621  * @hw:   pointer to the HW structure
3622  * @mem:  pointer to mem struct to fill out
3623  * @size: size of memory requested
3624  * @alignment: what to align the allocation to
3625  **/
3626 enum i40e_status_code
3627 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3628                         struct i40e_dma_mem *mem,
3629                         u64 size,
3630                         u32 alignment)
3631 {
3632         const struct rte_memzone *mz = NULL;
3633         char z_name[RTE_MEMZONE_NAMESIZE];
3634
3635         if (!mem)
3636                 return I40E_ERR_PARAM;
3637
3638         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3639         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3640                                          alignment, RTE_PGSIZE_2M);
3641         if (!mz)
3642                 return I40E_ERR_NO_MEMORY;
3643
3644         mem->size = size;
3645         mem->va = mz->addr;
3646         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3647         mem->zone = (const void *)mz;
3648         PMD_DRV_LOG(DEBUG,
3649                 "memzone %s allocated with physical address: %"PRIu64,
3650                 mz->name, mem->pa);
3651
3652         return I40E_SUCCESS;
3653 }
3654
3655 /**
3656  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3657  * @hw:   pointer to the HW structure
3658  * @mem:  ptr to mem struct to free
3659  **/
3660 enum i40e_status_code
3661 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3662                     struct i40e_dma_mem *mem)
3663 {
3664         if (!mem)
3665                 return I40E_ERR_PARAM;
3666
3667         PMD_DRV_LOG(DEBUG,
3668                 "memzone %s to be freed with physical address: %"PRIu64,
3669                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3670         rte_memzone_free((const struct rte_memzone *)mem->zone);
3671         mem->zone = NULL;
3672         mem->va = NULL;
3673         mem->pa = (u64)0;
3674
3675         return I40E_SUCCESS;
3676 }
3677
3678 /**
3679  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3680  * @hw:   pointer to the HW structure
3681  * @mem:  pointer to mem struct to fill out
3682  * @size: size of memory requested
3683  **/
3684 enum i40e_status_code
3685 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3686                          struct i40e_virt_mem *mem,
3687                          u32 size)
3688 {
3689         if (!mem)
3690                 return I40E_ERR_PARAM;
3691
3692         mem->size = size;
3693         mem->va = rte_zmalloc("i40e", size, 0);
3694
3695         if (mem->va)
3696                 return I40E_SUCCESS;
3697         else
3698                 return I40E_ERR_NO_MEMORY;
3699 }
3700
3701 /**
3702  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3703  * @hw:   pointer to the HW structure
3704  * @mem:  pointer to mem struct to free
3705  **/
3706 enum i40e_status_code
3707 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3708                      struct i40e_virt_mem *mem)
3709 {
3710         if (!mem)
3711                 return I40E_ERR_PARAM;
3712
3713         rte_free(mem->va);
3714         mem->va = NULL;
3715
3716         return I40E_SUCCESS;
3717 }
3718
3719 void
3720 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3721 {
3722         rte_spinlock_init(&sp->spinlock);
3723 }
3724
3725 void
3726 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3727 {
3728         rte_spinlock_lock(&sp->spinlock);
3729 }
3730
3731 void
3732 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3733 {
3734         rte_spinlock_unlock(&sp->spinlock);
3735 }
3736
3737 void
3738 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3739 {
3740         return;
3741 }
3742
3743 /**
3744  * Get the hardware capabilities, which will be parsed
3745  * and saved into struct i40e_hw.
3746  */
3747 static int
3748 i40e_get_cap(struct i40e_hw *hw)
3749 {
3750         struct i40e_aqc_list_capabilities_element_resp *buf;
3751         uint16_t len, size = 0;
3752         int ret;
3753
3754         /* Calculate a huge enough buff for saving response data temporarily */
3755         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3756                                                 I40E_MAX_CAP_ELE_NUM;
3757         buf = rte_zmalloc("i40e", len, 0);
3758         if (!buf) {
3759                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3760                 return I40E_ERR_NO_MEMORY;
3761         }
3762
3763         /* Get, parse the capabilities and save it to hw */
3764         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3765                         i40e_aqc_opc_list_func_capabilities, NULL);
3766         if (ret != I40E_SUCCESS)
3767                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3768
3769         /* Free the temporary buffer after being used */
3770         rte_free(buf);
3771
3772         return ret;
3773 }
3774
3775 static int
3776 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3777 {
3778         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3779         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3780         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3781         uint16_t qp_count = 0, vsi_count = 0;
3782
3783         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3784                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3785                 return -EINVAL;
3786         }
3787         /* Add the parameter init for LFC */
3788         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3789         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3790         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3791
3792         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3793         pf->max_num_vsi = hw->func_caps.num_vsis;
3794         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3795         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3796         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3797
3798         /* FDir queue/VSI allocation */
3799         pf->fdir_qp_offset = 0;
3800         if (hw->func_caps.fd) {
3801                 pf->flags |= I40E_FLAG_FDIR;
3802                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3803         } else {
3804                 pf->fdir_nb_qps = 0;
3805         }
3806         qp_count += pf->fdir_nb_qps;
3807         vsi_count += 1;
3808
3809         /* LAN queue/VSI allocation */
3810         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3811         if (!hw->func_caps.rss) {
3812                 pf->lan_nb_qps = 1;
3813         } else {
3814                 pf->flags |= I40E_FLAG_RSS;
3815                 if (hw->mac.type == I40E_MAC_X722)
3816                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3817                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3818         }
3819         qp_count += pf->lan_nb_qps;
3820         vsi_count += 1;
3821
3822         /* VF queue/VSI allocation */
3823         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3824         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3825                 pf->flags |= I40E_FLAG_SRIOV;
3826                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3827                 pf->vf_num = pci_dev->max_vfs;
3828                 PMD_DRV_LOG(DEBUG,
3829                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3830                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3831         } else {
3832                 pf->vf_nb_qps = 0;
3833                 pf->vf_num = 0;
3834         }
3835         qp_count += pf->vf_nb_qps * pf->vf_num;
3836         vsi_count += pf->vf_num;
3837
3838         /* VMDq queue/VSI allocation */
3839         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3840         pf->vmdq_nb_qps = 0;
3841         pf->max_nb_vmdq_vsi = 0;
3842         if (hw->func_caps.vmdq) {
3843                 if (qp_count < hw->func_caps.num_tx_qp &&
3844                         vsi_count < hw->func_caps.num_vsis) {
3845                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3846                                 qp_count) / pf->vmdq_nb_qp_max;
3847
3848                         /* Limit the maximum number of VMDq vsi to the maximum
3849                          * ethdev can support
3850                          */
3851                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3852                                 hw->func_caps.num_vsis - vsi_count);
3853                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3854                                 ETH_64_POOLS);
3855                         if (pf->max_nb_vmdq_vsi) {
3856                                 pf->flags |= I40E_FLAG_VMDQ;
3857                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3858                                 PMD_DRV_LOG(DEBUG,
3859                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3860                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3861                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3862                         } else {
3863                                 PMD_DRV_LOG(INFO,
3864                                         "No enough queues left for VMDq");
3865                         }
3866                 } else {
3867                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3868                 }
3869         }
3870         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3871         vsi_count += pf->max_nb_vmdq_vsi;
3872
3873         if (hw->func_caps.dcb)
3874                 pf->flags |= I40E_FLAG_DCB;
3875
3876         if (qp_count > hw->func_caps.num_tx_qp) {
3877                 PMD_DRV_LOG(ERR,
3878                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3879                         qp_count, hw->func_caps.num_tx_qp);
3880                 return -EINVAL;
3881         }
3882         if (vsi_count > hw->func_caps.num_vsis) {
3883                 PMD_DRV_LOG(ERR,
3884                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3885                         vsi_count, hw->func_caps.num_vsis);
3886                 return -EINVAL;
3887         }
3888
3889         return 0;
3890 }
3891
3892 static int
3893 i40e_pf_get_switch_config(struct i40e_pf *pf)
3894 {
3895         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3896         struct i40e_aqc_get_switch_config_resp *switch_config;
3897         struct i40e_aqc_switch_config_element_resp *element;
3898         uint16_t start_seid = 0, num_reported;
3899         int ret;
3900
3901         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3902                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3903         if (!switch_config) {
3904                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3905                 return -ENOMEM;
3906         }
3907
3908         /* Get the switch configurations */
3909         ret = i40e_aq_get_switch_config(hw, switch_config,
3910                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3911         if (ret != I40E_SUCCESS) {
3912                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3913                 goto fail;
3914         }
3915         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3916         if (num_reported != 1) { /* The number should be 1 */
3917                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3918                 goto fail;
3919         }
3920
3921         /* Parse the switch configuration elements */
3922         element = &(switch_config->element[0]);
3923         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3924                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3925                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3926         } else
3927                 PMD_DRV_LOG(INFO, "Unknown element type");
3928
3929 fail:
3930         rte_free(switch_config);
3931
3932         return ret;
3933 }
3934
3935 static int
3936 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3937                         uint32_t num)
3938 {
3939         struct pool_entry *entry;
3940
3941         if (pool == NULL || num == 0)
3942                 return -EINVAL;
3943
3944         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3945         if (entry == NULL) {
3946                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3947                 return -ENOMEM;
3948         }
3949
3950         /* queue heap initialize */
3951         pool->num_free = num;
3952         pool->num_alloc = 0;
3953         pool->base = base;
3954         LIST_INIT(&pool->alloc_list);
3955         LIST_INIT(&pool->free_list);
3956
3957         /* Initialize element  */
3958         entry->base = 0;
3959         entry->len = num;
3960
3961         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3962         return 0;
3963 }
3964
3965 static void
3966 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3967 {
3968         struct pool_entry *entry, *next_entry;
3969
3970         if (pool == NULL)
3971                 return;
3972
3973         for (entry = LIST_FIRST(&pool->alloc_list);
3974                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3975                         entry = next_entry) {
3976                 LIST_REMOVE(entry, next);
3977                 rte_free(entry);
3978         }
3979
3980         for (entry = LIST_FIRST(&pool->free_list);
3981                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3982                         entry = next_entry) {
3983                 LIST_REMOVE(entry, next);
3984                 rte_free(entry);
3985         }
3986
3987         pool->num_free = 0;
3988         pool->num_alloc = 0;
3989         pool->base = 0;
3990         LIST_INIT(&pool->alloc_list);
3991         LIST_INIT(&pool->free_list);
3992 }
3993
3994 static int
3995 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3996                        uint32_t base)
3997 {
3998         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3999         uint32_t pool_offset;
4000         int insert;
4001
4002         if (pool == NULL) {
4003                 PMD_DRV_LOG(ERR, "Invalid parameter");
4004                 return -EINVAL;
4005         }
4006
4007         pool_offset = base - pool->base;
4008         /* Lookup in alloc list */
4009         LIST_FOREACH(entry, &pool->alloc_list, next) {
4010                 if (entry->base == pool_offset) {
4011                         valid_entry = entry;
4012                         LIST_REMOVE(entry, next);
4013                         break;
4014                 }
4015         }
4016
4017         /* Not find, return */
4018         if (valid_entry == NULL) {
4019                 PMD_DRV_LOG(ERR, "Failed to find entry");
4020                 return -EINVAL;
4021         }
4022
4023         /**
4024          * Found it, move it to free list  and try to merge.
4025          * In order to make merge easier, always sort it by qbase.
4026          * Find adjacent prev and last entries.
4027          */
4028         prev = next = NULL;
4029         LIST_FOREACH(entry, &pool->free_list, next) {
4030                 if (entry->base > valid_entry->base) {
4031                         next = entry;
4032                         break;
4033                 }
4034                 prev = entry;
4035         }
4036
4037         insert = 0;
4038         /* Try to merge with next one*/
4039         if (next != NULL) {
4040                 /* Merge with next one */
4041                 if (valid_entry->base + valid_entry->len == next->base) {
4042                         next->base = valid_entry->base;
4043                         next->len += valid_entry->len;
4044                         rte_free(valid_entry);
4045                         valid_entry = next;
4046                         insert = 1;
4047                 }
4048         }
4049
4050         if (prev != NULL) {
4051                 /* Merge with previous one */
4052                 if (prev->base + prev->len == valid_entry->base) {
4053                         prev->len += valid_entry->len;
4054                         /* If it merge with next one, remove next node */
4055                         if (insert == 1) {
4056                                 LIST_REMOVE(valid_entry, next);
4057                                 rte_free(valid_entry);
4058                         } else {
4059                                 rte_free(valid_entry);
4060                                 insert = 1;
4061                         }
4062                 }
4063         }
4064
4065         /* Not find any entry to merge, insert */
4066         if (insert == 0) {
4067                 if (prev != NULL)
4068                         LIST_INSERT_AFTER(prev, valid_entry, next);
4069                 else if (next != NULL)
4070                         LIST_INSERT_BEFORE(next, valid_entry, next);
4071                 else /* It's empty list, insert to head */
4072                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4073         }
4074
4075         pool->num_free += valid_entry->len;
4076         pool->num_alloc -= valid_entry->len;
4077
4078         return 0;
4079 }
4080
4081 static int
4082 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4083                        uint16_t num)
4084 {
4085         struct pool_entry *entry, *valid_entry;
4086
4087         if (pool == NULL || num == 0) {
4088                 PMD_DRV_LOG(ERR, "Invalid parameter");
4089                 return -EINVAL;
4090         }
4091
4092         if (pool->num_free < num) {
4093                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4094                             num, pool->num_free);
4095                 return -ENOMEM;
4096         }
4097
4098         valid_entry = NULL;
4099         /* Lookup  in free list and find most fit one */
4100         LIST_FOREACH(entry, &pool->free_list, next) {
4101                 if (entry->len >= num) {
4102                         /* Find best one */
4103                         if (entry->len == num) {
4104                                 valid_entry = entry;
4105                                 break;
4106                         }
4107                         if (valid_entry == NULL || valid_entry->len > entry->len)
4108                                 valid_entry = entry;
4109                 }
4110         }
4111
4112         /* Not find one to satisfy the request, return */
4113         if (valid_entry == NULL) {
4114                 PMD_DRV_LOG(ERR, "No valid entry found");
4115                 return -ENOMEM;
4116         }
4117         /**
4118          * The entry have equal queue number as requested,
4119          * remove it from alloc_list.
4120          */
4121         if (valid_entry->len == num) {
4122                 LIST_REMOVE(valid_entry, next);
4123         } else {
4124                 /**
4125                  * The entry have more numbers than requested,
4126                  * create a new entry for alloc_list and minus its
4127                  * queue base and number in free_list.
4128                  */
4129                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4130                 if (entry == NULL) {
4131                         PMD_DRV_LOG(ERR,
4132                                 "Failed to allocate memory for resource pool");
4133                         return -ENOMEM;
4134                 }
4135                 entry->base = valid_entry->base;
4136                 entry->len = num;
4137                 valid_entry->base += num;
4138                 valid_entry->len -= num;
4139                 valid_entry = entry;
4140         }
4141
4142         /* Insert it into alloc list, not sorted */
4143         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4144
4145         pool->num_free -= valid_entry->len;
4146         pool->num_alloc += valid_entry->len;
4147
4148         return valid_entry->base + pool->base;
4149 }
4150
4151 /**
4152  * bitmap_is_subset - Check whether src2 is subset of src1
4153  **/
4154 static inline int
4155 bitmap_is_subset(uint8_t src1, uint8_t src2)
4156 {
4157         return !((src1 ^ src2) & src2);
4158 }
4159
4160 static enum i40e_status_code
4161 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4162 {
4163         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4164
4165         /* If DCB is not supported, only default TC is supported */
4166         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4167                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4168                 return I40E_NOT_SUPPORTED;
4169         }
4170
4171         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4172                 PMD_DRV_LOG(ERR,
4173                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4174                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4175                 return I40E_NOT_SUPPORTED;
4176         }
4177         return I40E_SUCCESS;
4178 }
4179
4180 int
4181 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4182                                 struct i40e_vsi_vlan_pvid_info *info)
4183 {
4184         struct i40e_hw *hw;
4185         struct i40e_vsi_context ctxt;
4186         uint8_t vlan_flags = 0;
4187         int ret;
4188
4189         if (vsi == NULL || info == NULL) {
4190                 PMD_DRV_LOG(ERR, "invalid parameters");
4191                 return I40E_ERR_PARAM;
4192         }
4193
4194         if (info->on) {
4195                 vsi->info.pvid = info->config.pvid;
4196                 /**
4197                  * If insert pvid is enabled, only tagged pkts are
4198                  * allowed to be sent out.
4199                  */
4200                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4201                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4202         } else {
4203                 vsi->info.pvid = 0;
4204                 if (info->config.reject.tagged == 0)
4205                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4206
4207                 if (info->config.reject.untagged == 0)
4208                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4209         }
4210         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4211                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4212         vsi->info.port_vlan_flags |= vlan_flags;
4213         vsi->info.valid_sections =
4214                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4215         memset(&ctxt, 0, sizeof(ctxt));
4216         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4217         ctxt.seid = vsi->seid;
4218
4219         hw = I40E_VSI_TO_HW(vsi);
4220         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4221         if (ret != I40E_SUCCESS)
4222                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4223
4224         return ret;
4225 }
4226
4227 static int
4228 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4229 {
4230         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4231         int i, ret;
4232         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4233
4234         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4235         if (ret != I40E_SUCCESS)
4236                 return ret;
4237
4238         if (!vsi->seid) {
4239                 PMD_DRV_LOG(ERR, "seid not valid");
4240                 return -EINVAL;
4241         }
4242
4243         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4244         tc_bw_data.tc_valid_bits = enabled_tcmap;
4245         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4246                 tc_bw_data.tc_bw_credits[i] =
4247                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4248
4249         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4250         if (ret != I40E_SUCCESS) {
4251                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4252                 return ret;
4253         }
4254
4255         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4256                                         sizeof(vsi->info.qs_handle));
4257         return I40E_SUCCESS;
4258 }
4259
4260 static enum i40e_status_code
4261 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4262                                  struct i40e_aqc_vsi_properties_data *info,
4263                                  uint8_t enabled_tcmap)
4264 {
4265         enum i40e_status_code ret;
4266         int i, total_tc = 0;
4267         uint16_t qpnum_per_tc, bsf, qp_idx;
4268
4269         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4270         if (ret != I40E_SUCCESS)
4271                 return ret;
4272
4273         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4274                 if (enabled_tcmap & (1 << i))
4275                         total_tc++;
4276         vsi->enabled_tc = enabled_tcmap;
4277
4278         /* Number of queues per enabled TC */
4279         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4280         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4281         bsf = rte_bsf32(qpnum_per_tc);
4282
4283         /* Adjust the queue number to actual queues that can be applied */
4284         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4285                 vsi->nb_qps = qpnum_per_tc * total_tc;
4286
4287         /**
4288          * Configure TC and queue mapping parameters, for enabled TC,
4289          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4290          * default queue will serve it.
4291          */
4292         qp_idx = 0;
4293         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4294                 if (vsi->enabled_tc & (1 << i)) {
4295                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4296                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4297                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4298                         qp_idx += qpnum_per_tc;
4299                 } else
4300                         info->tc_mapping[i] = 0;
4301         }
4302
4303         /* Associate queue number with VSI */
4304         if (vsi->type == I40E_VSI_SRIOV) {
4305                 info->mapping_flags |=
4306                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4307                 for (i = 0; i < vsi->nb_qps; i++)
4308                         info->queue_mapping[i] =
4309                                 rte_cpu_to_le_16(vsi->base_queue + i);
4310         } else {
4311                 info->mapping_flags |=
4312                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4313                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4314         }
4315         info->valid_sections |=
4316                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4317
4318         return I40E_SUCCESS;
4319 }
4320
4321 static int
4322 i40e_veb_release(struct i40e_veb *veb)
4323 {
4324         struct i40e_vsi *vsi;
4325         struct i40e_hw *hw;
4326
4327         if (veb == NULL)
4328                 return -EINVAL;
4329
4330         if (!TAILQ_EMPTY(&veb->head)) {
4331                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4332                 return -EACCES;
4333         }
4334         /* associate_vsi field is NULL for floating VEB */
4335         if (veb->associate_vsi != NULL) {
4336                 vsi = veb->associate_vsi;
4337                 hw = I40E_VSI_TO_HW(vsi);
4338
4339                 vsi->uplink_seid = veb->uplink_seid;
4340                 vsi->veb = NULL;
4341         } else {
4342                 veb->associate_pf->main_vsi->floating_veb = NULL;
4343                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4344         }
4345
4346         i40e_aq_delete_element(hw, veb->seid, NULL);
4347         rte_free(veb);
4348         return I40E_SUCCESS;
4349 }
4350
4351 /* Setup a veb */
4352 static struct i40e_veb *
4353 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4354 {
4355         struct i40e_veb *veb;
4356         int ret;
4357         struct i40e_hw *hw;
4358
4359         if (pf == NULL) {
4360                 PMD_DRV_LOG(ERR,
4361                             "veb setup failed, associated PF shouldn't null");
4362                 return NULL;
4363         }
4364         hw = I40E_PF_TO_HW(pf);
4365
4366         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4367         if (!veb) {
4368                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4369                 goto fail;
4370         }
4371
4372         veb->associate_vsi = vsi;
4373         veb->associate_pf = pf;
4374         TAILQ_INIT(&veb->head);
4375         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4376
4377         /* create floating veb if vsi is NULL */
4378         if (vsi != NULL) {
4379                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4380                                       I40E_DEFAULT_TCMAP, false,
4381                                       &veb->seid, false, NULL);
4382         } else {
4383                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4384                                       true, &veb->seid, false, NULL);
4385         }
4386
4387         if (ret != I40E_SUCCESS) {
4388                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4389                             hw->aq.asq_last_status);
4390                 goto fail;
4391         }
4392         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4393
4394         /* get statistics index */
4395         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4396                                 &veb->stats_idx, NULL, NULL, NULL);
4397         if (ret != I40E_SUCCESS) {
4398                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4399                             hw->aq.asq_last_status);
4400                 goto fail;
4401         }
4402         /* Get VEB bandwidth, to be implemented */
4403         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4404         if (vsi)
4405                 vsi->uplink_seid = veb->seid;
4406
4407         return veb;
4408 fail:
4409         rte_free(veb);
4410         return NULL;
4411 }
4412
4413 int
4414 i40e_vsi_release(struct i40e_vsi *vsi)
4415 {
4416         struct i40e_pf *pf;
4417         struct i40e_hw *hw;
4418         struct i40e_vsi_list *vsi_list;
4419         void *temp;
4420         int ret;
4421         struct i40e_mac_filter *f;
4422         uint16_t user_param;
4423
4424         if (!vsi)
4425                 return I40E_SUCCESS;
4426
4427         if (!vsi->adapter)
4428                 return -EFAULT;
4429
4430         user_param = vsi->user_param;
4431
4432         pf = I40E_VSI_TO_PF(vsi);
4433         hw = I40E_VSI_TO_HW(vsi);
4434
4435         /* VSI has child to attach, release child first */
4436         if (vsi->veb) {
4437                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4438                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4439                                 return -1;
4440                 }
4441                 i40e_veb_release(vsi->veb);
4442         }
4443
4444         if (vsi->floating_veb) {
4445                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4446                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4447                                 return -1;
4448                 }
4449         }
4450
4451         /* Remove all macvlan filters of the VSI */
4452         i40e_vsi_remove_all_macvlan_filter(vsi);
4453         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4454                 rte_free(f);
4455
4456         if (vsi->type != I40E_VSI_MAIN &&
4457             ((vsi->type != I40E_VSI_SRIOV) ||
4458             !pf->floating_veb_list[user_param])) {
4459                 /* Remove vsi from parent's sibling list */
4460                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4461                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4462                         return I40E_ERR_PARAM;
4463                 }
4464                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4465                                 &vsi->sib_vsi_list, list);
4466
4467                 /* Remove all switch element of the VSI */
4468                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4469                 if (ret != I40E_SUCCESS)
4470                         PMD_DRV_LOG(ERR, "Failed to delete element");
4471         }
4472
4473         if ((vsi->type == I40E_VSI_SRIOV) &&
4474             pf->floating_veb_list[user_param]) {
4475                 /* Remove vsi from parent's sibling list */
4476                 if (vsi->parent_vsi == NULL ||
4477                     vsi->parent_vsi->floating_veb == NULL) {
4478                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4479                         return I40E_ERR_PARAM;
4480                 }
4481                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4482                              &vsi->sib_vsi_list, list);
4483
4484                 /* Remove all switch element of the VSI */
4485                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4486                 if (ret != I40E_SUCCESS)
4487                         PMD_DRV_LOG(ERR, "Failed to delete element");
4488         }
4489
4490         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4491
4492         if (vsi->type != I40E_VSI_SRIOV)
4493                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4494         rte_free(vsi);
4495
4496         return I40E_SUCCESS;
4497 }
4498
4499 static int
4500 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4501 {
4502         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4503         struct i40e_aqc_remove_macvlan_element_data def_filter;
4504         struct i40e_mac_filter_info filter;
4505         int ret;
4506
4507         if (vsi->type != I40E_VSI_MAIN)
4508                 return I40E_ERR_CONFIG;
4509         memset(&def_filter, 0, sizeof(def_filter));
4510         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4511                                         ETH_ADDR_LEN);
4512         def_filter.vlan_tag = 0;
4513         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4514                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4515         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4516         if (ret != I40E_SUCCESS) {
4517                 struct i40e_mac_filter *f;
4518                 struct ether_addr *mac;
4519
4520                 PMD_DRV_LOG(WARNING,
4521                         "Cannot remove the default macvlan filter");
4522                 /* It needs to add the permanent mac into mac list */
4523                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4524                 if (f == NULL) {
4525                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4526                         return I40E_ERR_NO_MEMORY;
4527                 }
4528                 mac = &f->mac_info.mac_addr;
4529                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4530                                 ETH_ADDR_LEN);
4531                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4532                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4533                 vsi->mac_num++;
4534
4535                 return ret;
4536         }
4537         (void)rte_memcpy(&filter.mac_addr,
4538                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4539         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4540         return i40e_vsi_add_mac(vsi, &filter);
4541 }
4542
4543 /*
4544  * i40e_vsi_get_bw_config - Query VSI BW Information
4545  * @vsi: the VSI to be queried
4546  *
4547  * Returns 0 on success, negative value on failure
4548  */
4549 static enum i40e_status_code
4550 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4551 {
4552         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4553         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4554         struct i40e_hw *hw = &vsi->adapter->hw;
4555         i40e_status ret;
4556         int i;
4557         uint32_t bw_max;
4558
4559         memset(&bw_config, 0, sizeof(bw_config));
4560         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4561         if (ret != I40E_SUCCESS) {
4562                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4563                             hw->aq.asq_last_status);
4564                 return ret;
4565         }
4566
4567         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4568         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4569                                         &ets_sla_config, NULL);
4570         if (ret != I40E_SUCCESS) {
4571                 PMD_DRV_LOG(ERR,
4572                         "VSI failed to get TC bandwdith configuration %u",
4573                         hw->aq.asq_last_status);
4574                 return ret;
4575         }
4576
4577         /* store and print out BW info */
4578         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4579         vsi->bw_info.bw_max = bw_config.max_bw;
4580         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4581         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4582         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4583                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4584                      I40E_16_BIT_WIDTH);
4585         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4586                 vsi->bw_info.bw_ets_share_credits[i] =
4587                                 ets_sla_config.share_credits[i];
4588                 vsi->bw_info.bw_ets_credits[i] =
4589                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4590                 /* 4 bits per TC, 4th bit is reserved */
4591                 vsi->bw_info.bw_ets_max[i] =
4592                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4593                                   RTE_LEN2MASK(3, uint8_t));
4594                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4595                             vsi->bw_info.bw_ets_share_credits[i]);
4596                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4597                             vsi->bw_info.bw_ets_credits[i]);
4598                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4599                             vsi->bw_info.bw_ets_max[i]);
4600         }
4601
4602         return I40E_SUCCESS;
4603 }
4604
4605 /* i40e_enable_pf_lb
4606  * @pf: pointer to the pf structure
4607  *
4608  * allow loopback on pf
4609  */
4610 static inline void
4611 i40e_enable_pf_lb(struct i40e_pf *pf)
4612 {
4613         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4614         struct i40e_vsi_context ctxt;
4615         int ret;
4616
4617         /* Use the FW API if FW >= v5.0 */
4618         if (hw->aq.fw_maj_ver < 5) {
4619                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4620                 return;
4621         }
4622
4623         memset(&ctxt, 0, sizeof(ctxt));
4624         ctxt.seid = pf->main_vsi_seid;
4625         ctxt.pf_num = hw->pf_id;
4626         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4627         if (ret) {
4628                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4629                             ret, hw->aq.asq_last_status);
4630                 return;
4631         }
4632         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4633         ctxt.info.valid_sections =
4634                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4635         ctxt.info.switch_id |=
4636                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4637
4638         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4639         if (ret)
4640                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4641                             hw->aq.asq_last_status);
4642 }
4643
4644 /* Setup a VSI */
4645 struct i40e_vsi *
4646 i40e_vsi_setup(struct i40e_pf *pf,
4647                enum i40e_vsi_type type,
4648                struct i40e_vsi *uplink_vsi,
4649                uint16_t user_param)
4650 {
4651         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4652         struct i40e_vsi *vsi;
4653         struct i40e_mac_filter_info filter;
4654         int ret;
4655         struct i40e_vsi_context ctxt;
4656         struct ether_addr broadcast =
4657                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4658
4659         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4660             uplink_vsi == NULL) {
4661                 PMD_DRV_LOG(ERR,
4662                         "VSI setup failed, VSI link shouldn't be NULL");
4663                 return NULL;
4664         }
4665
4666         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4667                 PMD_DRV_LOG(ERR,
4668                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4669                 return NULL;
4670         }
4671
4672         /* two situations
4673          * 1.type is not MAIN and uplink vsi is not NULL
4674          * If uplink vsi didn't setup VEB, create one first under veb field
4675          * 2.type is SRIOV and the uplink is NULL
4676          * If floating VEB is NULL, create one veb under floating veb field
4677          */
4678
4679         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4680             uplink_vsi->veb == NULL) {
4681                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4682
4683                 if (uplink_vsi->veb == NULL) {
4684                         PMD_DRV_LOG(ERR, "VEB setup failed");
4685                         return NULL;
4686                 }
4687                 /* set ALLOWLOOPBACk on pf, when veb is created */
4688                 i40e_enable_pf_lb(pf);
4689         }
4690
4691         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4692             pf->main_vsi->floating_veb == NULL) {
4693                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4694
4695                 if (pf->main_vsi->floating_veb == NULL) {
4696                         PMD_DRV_LOG(ERR, "VEB setup failed");
4697                         return NULL;
4698                 }
4699         }
4700
4701         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4702         if (!vsi) {
4703                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4704                 return NULL;
4705         }
4706         TAILQ_INIT(&vsi->mac_list);
4707         vsi->type = type;
4708         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4709         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4710         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4711         vsi->user_param = user_param;
4712         vsi->vlan_anti_spoof_on = 0;
4713         vsi->vlan_filter_on = 0;
4714         /* Allocate queues */
4715         switch (vsi->type) {
4716         case I40E_VSI_MAIN  :
4717                 vsi->nb_qps = pf->lan_nb_qps;
4718                 break;
4719         case I40E_VSI_SRIOV :
4720                 vsi->nb_qps = pf->vf_nb_qps;
4721                 break;
4722         case I40E_VSI_VMDQ2:
4723                 vsi->nb_qps = pf->vmdq_nb_qps;
4724                 break;
4725         case I40E_VSI_FDIR:
4726                 vsi->nb_qps = pf->fdir_nb_qps;
4727                 break;
4728         default:
4729                 goto fail_mem;
4730         }
4731         /*
4732          * The filter status descriptor is reported in rx queue 0,
4733          * while the tx queue for fdir filter programming has no
4734          * such constraints, can be non-zero queues.
4735          * To simplify it, choose FDIR vsi use queue 0 pair.
4736          * To make sure it will use queue 0 pair, queue allocation
4737          * need be done before this function is called
4738          */
4739         if (type != I40E_VSI_FDIR) {
4740                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4741                         if (ret < 0) {
4742                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4743                                                 vsi->seid, ret);
4744                                 goto fail_mem;
4745                         }
4746                         vsi->base_queue = ret;
4747         } else
4748                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4749
4750         /* VF has MSIX interrupt in VF range, don't allocate here */
4751         if (type == I40E_VSI_MAIN) {
4752                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4753                                           RTE_MIN(vsi->nb_qps,
4754                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4755                 if (ret < 0) {
4756                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4757                                     vsi->seid, ret);
4758                         goto fail_queue_alloc;
4759                 }
4760                 vsi->msix_intr = ret;
4761                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4762         } else if (type != I40E_VSI_SRIOV) {
4763                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4764                 if (ret < 0) {
4765                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4766                         goto fail_queue_alloc;
4767                 }
4768                 vsi->msix_intr = ret;
4769                 vsi->nb_msix = 1;
4770         } else {
4771                 vsi->msix_intr = 0;
4772                 vsi->nb_msix = 0;
4773         }
4774
4775         /* Add VSI */
4776         if (type == I40E_VSI_MAIN) {
4777                 /* For main VSI, no need to add since it's default one */
4778                 vsi->uplink_seid = pf->mac_seid;
4779                 vsi->seid = pf->main_vsi_seid;
4780                 /* Bind queues with specific MSIX interrupt */
4781                 /**
4782                  * Needs 2 interrupt at least, one for misc cause which will
4783                  * enabled from OS side, Another for queues binding the
4784                  * interrupt from device side only.
4785                  */
4786
4787                 /* Get default VSI parameters from hardware */
4788                 memset(&ctxt, 0, sizeof(ctxt));
4789                 ctxt.seid = vsi->seid;
4790                 ctxt.pf_num = hw->pf_id;
4791                 ctxt.uplink_seid = vsi->uplink_seid;
4792                 ctxt.vf_num = 0;
4793                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4794                 if (ret != I40E_SUCCESS) {
4795                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4796                         goto fail_msix_alloc;
4797                 }
4798                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4799                         sizeof(struct i40e_aqc_vsi_properties_data));
4800                 vsi->vsi_id = ctxt.vsi_number;
4801                 vsi->info.valid_sections = 0;
4802
4803                 /* Configure tc, enabled TC0 only */
4804                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4805                         I40E_SUCCESS) {
4806                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4807                         goto fail_msix_alloc;
4808                 }
4809
4810                 /* TC, queue mapping */
4811                 memset(&ctxt, 0, sizeof(ctxt));
4812                 vsi->info.valid_sections |=
4813                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4814                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4815                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4816                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4817                         sizeof(struct i40e_aqc_vsi_properties_data));
4818                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4819                                                 I40E_DEFAULT_TCMAP);
4820                 if (ret != I40E_SUCCESS) {
4821                         PMD_DRV_LOG(ERR,
4822                                 "Failed to configure TC queue mapping");
4823                         goto fail_msix_alloc;
4824                 }
4825                 ctxt.seid = vsi->seid;
4826                 ctxt.pf_num = hw->pf_id;
4827                 ctxt.uplink_seid = vsi->uplink_seid;
4828                 ctxt.vf_num = 0;
4829
4830                 /* Update VSI parameters */
4831                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4832                 if (ret != I40E_SUCCESS) {
4833                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4834                         goto fail_msix_alloc;
4835                 }
4836
4837                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4838                                                 sizeof(vsi->info.tc_mapping));
4839                 (void)rte_memcpy(&vsi->info.queue_mapping,
4840                                 &ctxt.info.queue_mapping,
4841                         sizeof(vsi->info.queue_mapping));
4842                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4843                 vsi->info.valid_sections = 0;
4844
4845                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4846                                 ETH_ADDR_LEN);
4847
4848                 /**
4849                  * Updating default filter settings are necessary to prevent
4850                  * reception of tagged packets.
4851                  * Some old firmware configurations load a default macvlan
4852                  * filter which accepts both tagged and untagged packets.
4853                  * The updating is to use a normal filter instead if needed.
4854                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4855                  * The firmware with correct configurations load the default
4856                  * macvlan filter which is expected and cannot be removed.
4857                  */
4858                 i40e_update_default_filter_setting(vsi);
4859                 i40e_config_qinq(hw, vsi);
4860         } else if (type == I40E_VSI_SRIOV) {
4861                 memset(&ctxt, 0, sizeof(ctxt));
4862                 /**
4863                  * For other VSI, the uplink_seid equals to uplink VSI's
4864                  * uplink_seid since they share same VEB
4865                  */
4866                 if (uplink_vsi == NULL)
4867                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4868                 else
4869                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4870                 ctxt.pf_num = hw->pf_id;
4871                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4872                 ctxt.uplink_seid = vsi->uplink_seid;
4873                 ctxt.connection_type = 0x1;
4874                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4875
4876                 /* Use the VEB configuration if FW >= v5.0 */
4877                 if (hw->aq.fw_maj_ver >= 5) {
4878                         /* Configure switch ID */
4879                         ctxt.info.valid_sections |=
4880                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4881                         ctxt.info.switch_id =
4882                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4883                 }
4884
4885                 /* Configure port/vlan */
4886                 ctxt.info.valid_sections |=
4887                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4888                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4889                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4890                                                 hw->func_caps.enabled_tcmap);
4891                 if (ret != I40E_SUCCESS) {
4892                         PMD_DRV_LOG(ERR,
4893                                 "Failed to configure TC queue mapping");
4894                         goto fail_msix_alloc;
4895                 }
4896
4897                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4898                 ctxt.info.valid_sections |=
4899                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4900                 /**
4901                  * Since VSI is not created yet, only configure parameter,
4902                  * will add vsi below.
4903                  */
4904
4905                 i40e_config_qinq(hw, vsi);
4906         } else if (type == I40E_VSI_VMDQ2) {
4907                 memset(&ctxt, 0, sizeof(ctxt));
4908                 /*
4909                  * For other VSI, the uplink_seid equals to uplink VSI's
4910                  * uplink_seid since they share same VEB
4911                  */
4912                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4913                 ctxt.pf_num = hw->pf_id;
4914                 ctxt.vf_num = 0;
4915                 ctxt.uplink_seid = vsi->uplink_seid;
4916                 ctxt.connection_type = 0x1;
4917                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4918
4919                 ctxt.info.valid_sections |=
4920                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4921                 /* user_param carries flag to enable loop back */
4922                 if (user_param) {
4923                         ctxt.info.switch_id =
4924                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4925                         ctxt.info.switch_id |=
4926                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4927                 }
4928
4929                 /* Configure port/vlan */
4930                 ctxt.info.valid_sections |=
4931                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4932                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4933                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4934                                                 I40E_DEFAULT_TCMAP);
4935                 if (ret != I40E_SUCCESS) {
4936                         PMD_DRV_LOG(ERR,
4937                                 "Failed to configure TC queue mapping");
4938                         goto fail_msix_alloc;
4939                 }
4940                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4941                 ctxt.info.valid_sections |=
4942                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4943         } else if (type == I40E_VSI_FDIR) {
4944                 memset(&ctxt, 0, sizeof(ctxt));
4945                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4946                 ctxt.pf_num = hw->pf_id;
4947                 ctxt.vf_num = 0;
4948                 ctxt.uplink_seid = vsi->uplink_seid;
4949                 ctxt.connection_type = 0x1;     /* regular data port */
4950                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4951                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4952                                                 I40E_DEFAULT_TCMAP);
4953                 if (ret != I40E_SUCCESS) {
4954                         PMD_DRV_LOG(ERR,
4955                                 "Failed to configure TC queue mapping.");
4956                         goto fail_msix_alloc;
4957                 }
4958                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4959                 ctxt.info.valid_sections |=
4960                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4961         } else {
4962                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4963                 goto fail_msix_alloc;
4964         }
4965
4966         if (vsi->type != I40E_VSI_MAIN) {
4967                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4968                 if (ret != I40E_SUCCESS) {
4969                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4970                                     hw->aq.asq_last_status);
4971                         goto fail_msix_alloc;
4972                 }
4973                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4974                 vsi->info.valid_sections = 0;
4975                 vsi->seid = ctxt.seid;
4976                 vsi->vsi_id = ctxt.vsi_number;
4977                 vsi->sib_vsi_list.vsi = vsi;
4978                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4979                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4980                                           &vsi->sib_vsi_list, list);
4981                 } else {
4982                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4983                                           &vsi->sib_vsi_list, list);
4984                 }
4985         }
4986
4987         /* MAC/VLAN configuration */
4988         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4989         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4990
4991         ret = i40e_vsi_add_mac(vsi, &filter);
4992         if (ret != I40E_SUCCESS) {
4993                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4994                 goto fail_msix_alloc;
4995         }
4996
4997         /* Get VSI BW information */
4998         i40e_vsi_get_bw_config(vsi);
4999         return vsi;
5000 fail_msix_alloc:
5001         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5002 fail_queue_alloc:
5003         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5004 fail_mem:
5005         rte_free(vsi);
5006         return NULL;
5007 }
5008
5009 /* Configure vlan filter on or off */
5010 int
5011 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5012 {
5013         int i, num;
5014         struct i40e_mac_filter *f;
5015         void *temp;
5016         struct i40e_mac_filter_info *mac_filter;
5017         enum rte_mac_filter_type desired_filter;
5018         int ret = I40E_SUCCESS;
5019
5020         if (on) {
5021                 /* Filter to match MAC and VLAN */
5022                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5023         } else {
5024                 /* Filter to match only MAC */
5025                 desired_filter = RTE_MAC_PERFECT_MATCH;
5026         }
5027
5028         num = vsi->mac_num;
5029
5030         mac_filter = rte_zmalloc("mac_filter_info_data",
5031                                  num * sizeof(*mac_filter), 0);
5032         if (mac_filter == NULL) {
5033                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5034                 return I40E_ERR_NO_MEMORY;
5035         }
5036
5037         i = 0;
5038
5039         /* Remove all existing mac */
5040         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5041                 mac_filter[i] = f->mac_info;
5042                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5043                 if (ret) {
5044                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5045                                     on ? "enable" : "disable");
5046                         goto DONE;
5047                 }
5048                 i++;
5049         }
5050
5051         /* Override with new filter */
5052         for (i = 0; i < num; i++) {
5053                 mac_filter[i].filter_type = desired_filter;
5054                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5055                 if (ret) {
5056                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5057                                     on ? "enable" : "disable");
5058                         goto DONE;
5059                 }
5060         }
5061
5062 DONE:
5063         rte_free(mac_filter);
5064         return ret;
5065 }
5066
5067 /* Configure vlan stripping on or off */
5068 int
5069 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5070 {
5071         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5072         struct i40e_vsi_context ctxt;
5073         uint8_t vlan_flags;
5074         int ret = I40E_SUCCESS;
5075
5076         /* Check if it has been already on or off */
5077         if (vsi->info.valid_sections &
5078                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5079                 if (on) {
5080                         if ((vsi->info.port_vlan_flags &
5081                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5082                                 return 0; /* already on */
5083                 } else {
5084                         if ((vsi->info.port_vlan_flags &
5085                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5086                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5087                                 return 0; /* already off */
5088                 }
5089         }
5090
5091         if (on)
5092                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5093         else
5094                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5095         vsi->info.valid_sections =
5096                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5097         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5098         vsi->info.port_vlan_flags |= vlan_flags;
5099         ctxt.seid = vsi->seid;
5100         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5101         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5102         if (ret)
5103                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5104                             on ? "enable" : "disable");
5105
5106         return ret;
5107 }
5108
5109 static int
5110 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5111 {
5112         struct rte_eth_dev_data *data = dev->data;
5113         int ret;
5114         int mask = 0;
5115
5116         /* Apply vlan offload setting */
5117         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5118         i40e_vlan_offload_set(dev, mask);
5119
5120         /* Apply double-vlan setting, not implemented yet */
5121
5122         /* Apply pvid setting */
5123         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5124                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5125         if (ret)
5126                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5127
5128         return ret;
5129 }
5130
5131 static int
5132 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5133 {
5134         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5135
5136         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5137 }
5138
5139 static int
5140 i40e_update_flow_control(struct i40e_hw *hw)
5141 {
5142 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5143         struct i40e_link_status link_status;
5144         uint32_t rxfc = 0, txfc = 0, reg;
5145         uint8_t an_info;
5146         int ret;
5147
5148         memset(&link_status, 0, sizeof(link_status));
5149         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5150         if (ret != I40E_SUCCESS) {
5151                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5152                 goto write_reg; /* Disable flow control */
5153         }
5154
5155         an_info = hw->phy.link_info.an_info;
5156         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5157                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5158                 ret = I40E_ERR_NOT_READY;
5159                 goto write_reg; /* Disable flow control */
5160         }
5161         /**
5162          * If link auto negotiation is enabled, flow control needs to
5163          * be configured according to it
5164          */
5165         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5166         case I40E_LINK_PAUSE_RXTX:
5167                 rxfc = 1;
5168                 txfc = 1;
5169                 hw->fc.current_mode = I40E_FC_FULL;
5170                 break;
5171         case I40E_AQ_LINK_PAUSE_RX:
5172                 rxfc = 1;
5173                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5174                 break;
5175         case I40E_AQ_LINK_PAUSE_TX:
5176                 txfc = 1;
5177                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5178                 break;
5179         default:
5180                 hw->fc.current_mode = I40E_FC_NONE;
5181                 break;
5182         }
5183
5184 write_reg:
5185         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5186                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5187         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5188         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5189         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5190         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5191
5192         return ret;
5193 }
5194
5195 /* PF setup */
5196 static int
5197 i40e_pf_setup(struct i40e_pf *pf)
5198 {
5199         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5200         struct i40e_filter_control_settings settings;
5201         struct i40e_vsi *vsi;
5202         int ret;
5203
5204         /* Clear all stats counters */
5205         pf->offset_loaded = FALSE;
5206         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5207         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5208
5209         ret = i40e_pf_get_switch_config(pf);
5210         if (ret != I40E_SUCCESS) {
5211                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5212                 return ret;
5213         }
5214         if (pf->flags & I40E_FLAG_FDIR) {
5215                 /* make queue allocated first, let FDIR use queue pair 0*/
5216                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5217                 if (ret != I40E_FDIR_QUEUE_ID) {
5218                         PMD_DRV_LOG(ERR,
5219                                 "queue allocation fails for FDIR: ret =%d",
5220                                 ret);
5221                         pf->flags &= ~I40E_FLAG_FDIR;
5222                 }
5223         }
5224         /*  main VSI setup */
5225         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5226         if (!vsi) {
5227                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5228                 return I40E_ERR_NOT_READY;
5229         }
5230         pf->main_vsi = vsi;
5231
5232         /* Configure filter control */
5233         memset(&settings, 0, sizeof(settings));
5234         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5235                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5236         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5237                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5238         else {
5239                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5240                         hw->func_caps.rss_table_size);
5241                 return I40E_ERR_PARAM;
5242         }
5243         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5244                 hw->func_caps.rss_table_size);
5245         pf->hash_lut_size = hw->func_caps.rss_table_size;
5246
5247         /* Enable ethtype and macvlan filters */
5248         settings.enable_ethtype = TRUE;
5249         settings.enable_macvlan = TRUE;
5250         ret = i40e_set_filter_control(hw, &settings);
5251         if (ret)
5252                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5253                                                                 ret);
5254
5255         /* Update flow control according to the auto negotiation */
5256         i40e_update_flow_control(hw);
5257
5258         return I40E_SUCCESS;
5259 }
5260
5261 int
5262 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5263 {
5264         uint32_t reg;
5265         uint16_t j;
5266
5267         /**
5268          * Set or clear TX Queue Disable flags,
5269          * which is required by hardware.
5270          */
5271         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5272         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5273
5274         /* Wait until the request is finished */
5275         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5276                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5277                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5278                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5279                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5280                                                         & 0x1))) {
5281                         break;
5282                 }
5283         }
5284         if (on) {
5285                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5286                         return I40E_SUCCESS; /* already on, skip next steps */
5287
5288                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5289                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5290         } else {
5291                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5292                         return I40E_SUCCESS; /* already off, skip next steps */
5293                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5294         }
5295         /* Write the register */
5296         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5297         /* Check the result */
5298         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5299                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5300                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5301                 if (on) {
5302                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5303                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5304                                 break;
5305                 } else {
5306                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5307                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5308                                 break;
5309                 }
5310         }
5311         /* Check if it is timeout */
5312         if (j >= I40E_CHK_Q_ENA_COUNT) {
5313                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5314                             (on ? "enable" : "disable"), q_idx);
5315                 return I40E_ERR_TIMEOUT;
5316         }
5317
5318         return I40E_SUCCESS;
5319 }
5320
5321 /* Swith on or off the tx queues */
5322 static int
5323 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5324 {
5325         struct rte_eth_dev_data *dev_data = pf->dev_data;
5326         struct i40e_tx_queue *txq;
5327         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5328         uint16_t i;
5329         int ret;
5330
5331         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5332                 txq = dev_data->tx_queues[i];
5333                 /* Don't operate the queue if not configured or
5334                  * if starting only per queue */
5335                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5336                         continue;
5337                 if (on)
5338                         ret = i40e_dev_tx_queue_start(dev, i);
5339                 else
5340                         ret = i40e_dev_tx_queue_stop(dev, i);
5341                 if ( ret != I40E_SUCCESS)
5342                         return ret;
5343         }
5344
5345         return I40E_SUCCESS;
5346 }
5347
5348 int
5349 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5350 {
5351         uint32_t reg;
5352         uint16_t j;
5353
5354         /* Wait until the request is finished */
5355         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5356                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5357                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5358                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5359                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5360                         break;
5361         }
5362
5363         if (on) {
5364                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5365                         return I40E_SUCCESS; /* Already on, skip next steps */
5366                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5367         } else {
5368                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5369                         return I40E_SUCCESS; /* Already off, skip next steps */
5370                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5371         }
5372
5373         /* Write the register */
5374         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5375         /* Check the result */
5376         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5377                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5378                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5379                 if (on) {
5380                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5381                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5382                                 break;
5383                 } else {
5384                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5385                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5386                                 break;
5387                 }
5388         }
5389
5390         /* Check if it is timeout */
5391         if (j >= I40E_CHK_Q_ENA_COUNT) {
5392                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5393                             (on ? "enable" : "disable"), q_idx);
5394                 return I40E_ERR_TIMEOUT;
5395         }
5396
5397         return I40E_SUCCESS;
5398 }
5399 /* Switch on or off the rx queues */
5400 static int
5401 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5402 {
5403         struct rte_eth_dev_data *dev_data = pf->dev_data;
5404         struct i40e_rx_queue *rxq;
5405         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5406         uint16_t i;
5407         int ret;
5408
5409         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5410                 rxq = dev_data->rx_queues[i];
5411                 /* Don't operate the queue if not configured or
5412                  * if starting only per queue */
5413                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5414                         continue;
5415                 if (on)
5416                         ret = i40e_dev_rx_queue_start(dev, i);
5417                 else
5418                         ret = i40e_dev_rx_queue_stop(dev, i);
5419                 if (ret != I40E_SUCCESS)
5420                         return ret;
5421         }
5422
5423         return I40E_SUCCESS;
5424 }
5425
5426 /* Switch on or off all the rx/tx queues */
5427 int
5428 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5429 {
5430         int ret;
5431
5432         if (on) {
5433                 /* enable rx queues before enabling tx queues */
5434                 ret = i40e_dev_switch_rx_queues(pf, on);
5435                 if (ret) {
5436                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5437                         return ret;
5438                 }
5439                 ret = i40e_dev_switch_tx_queues(pf, on);
5440         } else {
5441                 /* Stop tx queues before stopping rx queues */
5442                 ret = i40e_dev_switch_tx_queues(pf, on);
5443                 if (ret) {
5444                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5445                         return ret;
5446                 }
5447                 ret = i40e_dev_switch_rx_queues(pf, on);
5448         }
5449
5450         return ret;
5451 }
5452
5453 /* Initialize VSI for TX */
5454 static int
5455 i40e_dev_tx_init(struct i40e_pf *pf)
5456 {
5457         struct rte_eth_dev_data *data = pf->dev_data;
5458         uint16_t i;
5459         uint32_t ret = I40E_SUCCESS;
5460         struct i40e_tx_queue *txq;
5461
5462         for (i = 0; i < data->nb_tx_queues; i++) {
5463                 txq = data->tx_queues[i];
5464                 if (!txq || !txq->q_set)
5465                         continue;
5466                 ret = i40e_tx_queue_init(txq);
5467                 if (ret != I40E_SUCCESS)
5468                         break;
5469         }
5470         if (ret == I40E_SUCCESS)
5471                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5472                                      ->eth_dev);
5473
5474         return ret;
5475 }
5476
5477 /* Initialize VSI for RX */
5478 static int
5479 i40e_dev_rx_init(struct i40e_pf *pf)
5480 {
5481         struct rte_eth_dev_data *data = pf->dev_data;
5482         int ret = I40E_SUCCESS;
5483         uint16_t i;
5484         struct i40e_rx_queue *rxq;
5485
5486         i40e_pf_config_mq_rx(pf);
5487         for (i = 0; i < data->nb_rx_queues; i++) {
5488                 rxq = data->rx_queues[i];
5489                 if (!rxq || !rxq->q_set)
5490                         continue;
5491
5492                 ret = i40e_rx_queue_init(rxq);
5493                 if (ret != I40E_SUCCESS) {
5494                         PMD_DRV_LOG(ERR,
5495                                 "Failed to do RX queue initialization");
5496                         break;
5497                 }
5498         }
5499         if (ret == I40E_SUCCESS)
5500                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5501                                      ->eth_dev);
5502
5503         return ret;
5504 }
5505
5506 static int
5507 i40e_dev_rxtx_init(struct i40e_pf *pf)
5508 {
5509         int err;
5510
5511         err = i40e_dev_tx_init(pf);
5512         if (err) {
5513                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5514                 return err;
5515         }
5516         err = i40e_dev_rx_init(pf);
5517         if (err) {
5518                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5519                 return err;
5520         }
5521
5522         return err;
5523 }
5524
5525 static int
5526 i40e_vmdq_setup(struct rte_eth_dev *dev)
5527 {
5528         struct rte_eth_conf *conf = &dev->data->dev_conf;
5529         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5530         int i, err, conf_vsis, j, loop;
5531         struct i40e_vsi *vsi;
5532         struct i40e_vmdq_info *vmdq_info;
5533         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5534         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5535
5536         /*
5537          * Disable interrupt to avoid message from VF. Furthermore, it will
5538          * avoid race condition in VSI creation/destroy.
5539          */
5540         i40e_pf_disable_irq0(hw);
5541
5542         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5543                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5544                 return -ENOTSUP;
5545         }
5546
5547         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5548         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5549                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5550                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5551                         pf->max_nb_vmdq_vsi);
5552                 return -ENOTSUP;
5553         }
5554
5555         if (pf->vmdq != NULL) {
5556                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5557                 return 0;
5558         }
5559
5560         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5561                                 sizeof(*vmdq_info) * conf_vsis, 0);
5562
5563         if (pf->vmdq == NULL) {
5564                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5565                 return -ENOMEM;
5566         }
5567
5568         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5569
5570         /* Create VMDQ VSI */
5571         for (i = 0; i < conf_vsis; i++) {
5572                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5573                                 vmdq_conf->enable_loop_back);
5574                 if (vsi == NULL) {
5575                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5576                         err = -1;
5577                         goto err_vsi_setup;
5578                 }
5579                 vmdq_info = &pf->vmdq[i];
5580                 vmdq_info->pf = pf;
5581                 vmdq_info->vsi = vsi;
5582         }
5583         pf->nb_cfg_vmdq_vsi = conf_vsis;
5584
5585         /* Configure Vlan */
5586         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5587         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5588                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5589                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5590                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5591                                         vmdq_conf->pool_map[i].vlan_id, j);
5592
5593                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5594                                                 vmdq_conf->pool_map[i].vlan_id);
5595                                 if (err) {
5596                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5597                                         err = -1;
5598                                         goto err_vsi_setup;
5599                                 }
5600                         }
5601                 }
5602         }
5603
5604         i40e_pf_enable_irq0(hw);
5605
5606         return 0;
5607
5608 err_vsi_setup:
5609         for (i = 0; i < conf_vsis; i++)
5610                 if (pf->vmdq[i].vsi == NULL)
5611                         break;
5612                 else
5613                         i40e_vsi_release(pf->vmdq[i].vsi);
5614
5615         rte_free(pf->vmdq);
5616         pf->vmdq = NULL;
5617         i40e_pf_enable_irq0(hw);
5618         return err;
5619 }
5620
5621 static void
5622 i40e_stat_update_32(struct i40e_hw *hw,
5623                    uint32_t reg,
5624                    bool offset_loaded,
5625                    uint64_t *offset,
5626                    uint64_t *stat)
5627 {
5628         uint64_t new_data;
5629
5630         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5631         if (!offset_loaded)
5632                 *offset = new_data;
5633
5634         if (new_data >= *offset)
5635                 *stat = (uint64_t)(new_data - *offset);
5636         else
5637                 *stat = (uint64_t)((new_data +
5638                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5639 }
5640
5641 static void
5642 i40e_stat_update_48(struct i40e_hw *hw,
5643                    uint32_t hireg,
5644                    uint32_t loreg,
5645                    bool offset_loaded,
5646                    uint64_t *offset,
5647                    uint64_t *stat)
5648 {
5649         uint64_t new_data;
5650
5651         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5652         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5653                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5654
5655         if (!offset_loaded)
5656                 *offset = new_data;
5657
5658         if (new_data >= *offset)
5659                 *stat = new_data - *offset;
5660         else
5661                 *stat = (uint64_t)((new_data +
5662                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5663
5664         *stat &= I40E_48_BIT_MASK;
5665 }
5666
5667 /* Disable IRQ0 */
5668 void
5669 i40e_pf_disable_irq0(struct i40e_hw *hw)
5670 {
5671         /* Disable all interrupt types */
5672         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5673         I40E_WRITE_FLUSH(hw);
5674 }
5675
5676 /* Enable IRQ0 */
5677 void
5678 i40e_pf_enable_irq0(struct i40e_hw *hw)
5679 {
5680         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5681                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5682                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5683                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5684         I40E_WRITE_FLUSH(hw);
5685 }
5686
5687 static void
5688 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5689 {
5690         /* read pending request and disable first */
5691         i40e_pf_disable_irq0(hw);
5692         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5693         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5694                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5695
5696         if (no_queue)
5697                 /* Link no queues with irq0 */
5698                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5699                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5700 }
5701
5702 static void
5703 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5704 {
5705         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5706         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5707         int i;
5708         uint16_t abs_vf_id;
5709         uint32_t index, offset, val;
5710
5711         if (!pf->vfs)
5712                 return;
5713         /**
5714          * Try to find which VF trigger a reset, use absolute VF id to access
5715          * since the reg is global register.
5716          */
5717         for (i = 0; i < pf->vf_num; i++) {
5718                 abs_vf_id = hw->func_caps.vf_base_id + i;
5719                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5720                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5721                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5722                 /* VFR event occured */
5723                 if (val & (0x1 << offset)) {
5724                         int ret;
5725
5726                         /* Clear the event first */
5727                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5728                                                         (0x1 << offset));
5729                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5730                         /**
5731                          * Only notify a VF reset event occured,
5732                          * don't trigger another SW reset
5733                          */
5734                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5735                         if (ret != I40E_SUCCESS)
5736                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5737                 }
5738         }
5739 }
5740
5741 static void
5742 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5743 {
5744         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5745         struct i40e_virtchnl_pf_event event;
5746         int i;
5747
5748         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5749         event.event_data.link_event.link_status =
5750                 dev->data->dev_link.link_status;
5751         event.event_data.link_event.link_speed =
5752                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5753
5754         for (i = 0; i < pf->vf_num; i++)
5755                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5756                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5757 }
5758
5759 static void
5760 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5761 {
5762         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5763         struct i40e_arq_event_info info;
5764         uint16_t pending, opcode;
5765         int ret;
5766
5767         info.buf_len = I40E_AQ_BUF_SZ;
5768         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5769         if (!info.msg_buf) {
5770                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5771                 return;
5772         }
5773
5774         pending = 1;
5775         while (pending) {
5776                 ret = i40e_clean_arq_element(hw, &info, &pending);
5777
5778                 if (ret != I40E_SUCCESS) {
5779                         PMD_DRV_LOG(INFO,
5780                                 "Failed to read msg from AdminQ, aq_err: %u",
5781                                 hw->aq.asq_last_status);
5782                         break;
5783                 }
5784                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5785
5786                 switch (opcode) {
5787                 case i40e_aqc_opc_send_msg_to_pf:
5788                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5789                         i40e_pf_host_handle_vf_msg(dev,
5790                                         rte_le_to_cpu_16(info.desc.retval),
5791                                         rte_le_to_cpu_32(info.desc.cookie_high),
5792                                         rte_le_to_cpu_32(info.desc.cookie_low),
5793                                         info.msg_buf,
5794                                         info.msg_len);
5795                         break;
5796                 case i40e_aqc_opc_get_link_status:
5797                         ret = i40e_dev_link_update(dev, 0);
5798                         if (!ret) {
5799                                 i40e_notify_all_vfs_link_status(dev);
5800                                 _rte_eth_dev_callback_process(dev,
5801                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5802                         }
5803                         break;
5804                 default:
5805                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5806                                     opcode);
5807                         break;
5808                 }
5809         }
5810         rte_free(info.msg_buf);
5811 }
5812
5813 /**
5814  * Interrupt handler triggered by NIC  for handling
5815  * specific interrupt.
5816  *
5817  * @param handle
5818  *  Pointer to interrupt handle.
5819  * @param param
5820  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5821  *
5822  * @return
5823  *  void
5824  */
5825 static void
5826 i40e_dev_interrupt_handler(void *param)
5827 {
5828         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5829         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5830         uint32_t icr0;
5831
5832         /* Disable interrupt */
5833         i40e_pf_disable_irq0(hw);
5834
5835         /* read out interrupt causes */
5836         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5837
5838         /* No interrupt event indicated */
5839         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5840                 PMD_DRV_LOG(INFO, "No interrupt event");
5841                 goto done;
5842         }
5843         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5844                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5845         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5846                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5847         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5848                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5849         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5850                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5851         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5852                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5853         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5854                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5855         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5856                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5857
5858         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5859                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5860                 i40e_dev_handle_vfr_event(dev);
5861         }
5862         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5863                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5864                 i40e_dev_handle_aq_msg(dev);
5865         }
5866
5867 done:
5868         /* Enable interrupt */
5869         i40e_pf_enable_irq0(hw);
5870         rte_intr_enable(dev->intr_handle);
5871 }
5872
5873 static int
5874 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5875                          struct i40e_macvlan_filter *filter,
5876                          int total)
5877 {
5878         int ele_num, ele_buff_size;
5879         int num, actual_num, i;
5880         uint16_t flags;
5881         int ret = I40E_SUCCESS;
5882         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5883         struct i40e_aqc_add_macvlan_element_data *req_list;
5884
5885         if (filter == NULL  || total == 0)
5886                 return I40E_ERR_PARAM;
5887         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5888         ele_buff_size = hw->aq.asq_buf_size;
5889
5890         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5891         if (req_list == NULL) {
5892                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5893                 return I40E_ERR_NO_MEMORY;
5894         }
5895
5896         num = 0;
5897         do {
5898                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5899                 memset(req_list, 0, ele_buff_size);
5900
5901                 for (i = 0; i < actual_num; i++) {
5902                         (void)rte_memcpy(req_list[i].mac_addr,
5903                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5904                         req_list[i].vlan_tag =
5905                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5906
5907                         switch (filter[num + i].filter_type) {
5908                         case RTE_MAC_PERFECT_MATCH:
5909                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5910                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5911                                 break;
5912                         case RTE_MACVLAN_PERFECT_MATCH:
5913                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5914                                 break;
5915                         case RTE_MAC_HASH_MATCH:
5916                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5917                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5918                                 break;
5919                         case RTE_MACVLAN_HASH_MATCH:
5920                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5921                                 break;
5922                         default:
5923                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5924                                 ret = I40E_ERR_PARAM;
5925                                 goto DONE;
5926                         }
5927
5928                         req_list[i].queue_number = 0;
5929
5930                         req_list[i].flags = rte_cpu_to_le_16(flags);
5931                 }
5932
5933                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5934                                                 actual_num, NULL);
5935                 if (ret != I40E_SUCCESS) {
5936                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5937                         goto DONE;
5938                 }
5939                 num += actual_num;
5940         } while (num < total);
5941
5942 DONE:
5943         rte_free(req_list);
5944         return ret;
5945 }
5946
5947 static int
5948 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5949                             struct i40e_macvlan_filter *filter,
5950                             int total)
5951 {
5952         int ele_num, ele_buff_size;
5953         int num, actual_num, i;
5954         uint16_t flags;
5955         int ret = I40E_SUCCESS;
5956         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5957         struct i40e_aqc_remove_macvlan_element_data *req_list;
5958
5959         if (filter == NULL  || total == 0)
5960                 return I40E_ERR_PARAM;
5961
5962         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5963         ele_buff_size = hw->aq.asq_buf_size;
5964
5965         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5966         if (req_list == NULL) {
5967                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5968                 return I40E_ERR_NO_MEMORY;
5969         }
5970
5971         num = 0;
5972         do {
5973                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5974                 memset(req_list, 0, ele_buff_size);
5975
5976                 for (i = 0; i < actual_num; i++) {
5977                         (void)rte_memcpy(req_list[i].mac_addr,
5978                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5979                         req_list[i].vlan_tag =
5980                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5981
5982                         switch (filter[num + i].filter_type) {
5983                         case RTE_MAC_PERFECT_MATCH:
5984                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5985                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5986                                 break;
5987                         case RTE_MACVLAN_PERFECT_MATCH:
5988                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5989                                 break;
5990                         case RTE_MAC_HASH_MATCH:
5991                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5992                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5993                                 break;
5994                         case RTE_MACVLAN_HASH_MATCH:
5995                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5996                                 break;
5997                         default:
5998                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5999                                 ret = I40E_ERR_PARAM;
6000                                 goto DONE;
6001                         }
6002                         req_list[i].flags = rte_cpu_to_le_16(flags);
6003                 }
6004
6005                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6006                                                 actual_num, NULL);
6007                 if (ret != I40E_SUCCESS) {
6008                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6009                         goto DONE;
6010                 }
6011                 num += actual_num;
6012         } while (num < total);
6013
6014 DONE:
6015         rte_free(req_list);
6016         return ret;
6017 }
6018
6019 /* Find out specific MAC filter */
6020 static struct i40e_mac_filter *
6021 i40e_find_mac_filter(struct i40e_vsi *vsi,
6022                          struct ether_addr *macaddr)
6023 {
6024         struct i40e_mac_filter *f;
6025
6026         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6027                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6028                         return f;
6029         }
6030
6031         return NULL;
6032 }
6033
6034 static bool
6035 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6036                          uint16_t vlan_id)
6037 {
6038         uint32_t vid_idx, vid_bit;
6039
6040         if (vlan_id > ETH_VLAN_ID_MAX)
6041                 return 0;
6042
6043         vid_idx = I40E_VFTA_IDX(vlan_id);
6044         vid_bit = I40E_VFTA_BIT(vlan_id);
6045
6046         if (vsi->vfta[vid_idx] & vid_bit)
6047                 return 1;
6048         else
6049                 return 0;
6050 }
6051
6052 static void
6053 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6054                        uint16_t vlan_id, bool on)
6055 {
6056         uint32_t vid_idx, vid_bit;
6057
6058         vid_idx = I40E_VFTA_IDX(vlan_id);
6059         vid_bit = I40E_VFTA_BIT(vlan_id);
6060
6061         if (on)
6062                 vsi->vfta[vid_idx] |= vid_bit;
6063         else
6064                 vsi->vfta[vid_idx] &= ~vid_bit;
6065 }
6066
6067 static void
6068 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6069                      uint16_t vlan_id, bool on)
6070 {
6071         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6072         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6073         int ret;
6074
6075         if (vlan_id > ETH_VLAN_ID_MAX)
6076                 return;
6077
6078         i40e_store_vlan_filter(vsi, vlan_id, on);
6079
6080         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6081                 return;
6082
6083         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6084
6085         if (on) {
6086                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6087                                        &vlan_data, 1, NULL);
6088                 if (ret != I40E_SUCCESS)
6089                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6090         } else {
6091                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6092                                           &vlan_data, 1, NULL);
6093                 if (ret != I40E_SUCCESS)
6094                         PMD_DRV_LOG(ERR,
6095                                     "Failed to remove vlan filter");
6096         }
6097 }
6098
6099 /**
6100  * Find all vlan options for specific mac addr,
6101  * return with actual vlan found.
6102  */
6103 static inline int
6104 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6105                            struct i40e_macvlan_filter *mv_f,
6106                            int num, struct ether_addr *addr)
6107 {
6108         int i;
6109         uint32_t j, k;
6110
6111         /**
6112          * Not to use i40e_find_vlan_filter to decrease the loop time,
6113          * although the code looks complex.
6114           */
6115         if (num < vsi->vlan_num)
6116                 return I40E_ERR_PARAM;
6117
6118         i = 0;
6119         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6120                 if (vsi->vfta[j]) {
6121                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6122                                 if (vsi->vfta[j] & (1 << k)) {
6123                                         if (i > num - 1) {
6124                                                 PMD_DRV_LOG(ERR,
6125                                                         "vlan number doesn't match");
6126                                                 return I40E_ERR_PARAM;
6127                                         }
6128                                         (void)rte_memcpy(&mv_f[i].macaddr,
6129                                                         addr, ETH_ADDR_LEN);
6130                                         mv_f[i].vlan_id =
6131                                                 j * I40E_UINT32_BIT_SIZE + k;
6132                                         i++;
6133                                 }
6134                         }
6135                 }
6136         }
6137         return I40E_SUCCESS;
6138 }
6139
6140 static inline int
6141 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6142                            struct i40e_macvlan_filter *mv_f,
6143                            int num,
6144                            uint16_t vlan)
6145 {
6146         int i = 0;
6147         struct i40e_mac_filter *f;
6148
6149         if (num < vsi->mac_num)
6150                 return I40E_ERR_PARAM;
6151
6152         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6153                 if (i > num - 1) {
6154                         PMD_DRV_LOG(ERR, "buffer number not match");
6155                         return I40E_ERR_PARAM;
6156                 }
6157                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6158                                 ETH_ADDR_LEN);
6159                 mv_f[i].vlan_id = vlan;
6160                 mv_f[i].filter_type = f->mac_info.filter_type;
6161                 i++;
6162         }
6163
6164         return I40E_SUCCESS;
6165 }
6166
6167 static int
6168 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6169 {
6170         int i, j, num;
6171         struct i40e_mac_filter *f;
6172         struct i40e_macvlan_filter *mv_f;
6173         int ret = I40E_SUCCESS;
6174
6175         if (vsi == NULL || vsi->mac_num == 0)
6176                 return I40E_ERR_PARAM;
6177
6178         /* Case that no vlan is set */
6179         if (vsi->vlan_num == 0)
6180                 num = vsi->mac_num;
6181         else
6182                 num = vsi->mac_num * vsi->vlan_num;
6183
6184         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6185         if (mv_f == NULL) {
6186                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6187                 return I40E_ERR_NO_MEMORY;
6188         }
6189
6190         i = 0;
6191         if (vsi->vlan_num == 0) {
6192                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6193                         (void)rte_memcpy(&mv_f[i].macaddr,
6194                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6195                         mv_f[i].filter_type = f->mac_info.filter_type;
6196                         mv_f[i].vlan_id = 0;
6197                         i++;
6198                 }
6199         } else {
6200                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6201                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6202                                         vsi->vlan_num, &f->mac_info.mac_addr);
6203                         if (ret != I40E_SUCCESS)
6204                                 goto DONE;
6205                         for (j = i; j < i + vsi->vlan_num; j++)
6206                                 mv_f[j].filter_type = f->mac_info.filter_type;
6207                         i += vsi->vlan_num;
6208                 }
6209         }
6210
6211         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6212 DONE:
6213         rte_free(mv_f);
6214
6215         return ret;
6216 }
6217
6218 int
6219 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6220 {
6221         struct i40e_macvlan_filter *mv_f;
6222         int mac_num;
6223         int ret = I40E_SUCCESS;
6224
6225         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6226                 return I40E_ERR_PARAM;
6227
6228         /* If it's already set, just return */
6229         if (i40e_find_vlan_filter(vsi,vlan))
6230                 return I40E_SUCCESS;
6231
6232         mac_num = vsi->mac_num;
6233
6234         if (mac_num == 0) {
6235                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6236                 return I40E_ERR_PARAM;
6237         }
6238
6239         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6240
6241         if (mv_f == NULL) {
6242                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6243                 return I40E_ERR_NO_MEMORY;
6244         }
6245
6246         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6247
6248         if (ret != I40E_SUCCESS)
6249                 goto DONE;
6250
6251         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6252
6253         if (ret != I40E_SUCCESS)
6254                 goto DONE;
6255
6256         i40e_set_vlan_filter(vsi, vlan, 1);
6257
6258         vsi->vlan_num++;
6259         ret = I40E_SUCCESS;
6260 DONE:
6261         rte_free(mv_f);
6262         return ret;
6263 }
6264
6265 int
6266 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6267 {
6268         struct i40e_macvlan_filter *mv_f;
6269         int mac_num;
6270         int ret = I40E_SUCCESS;
6271
6272         /**
6273          * Vlan 0 is the generic filter for untagged packets
6274          * and can't be removed.
6275          */
6276         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6277                 return I40E_ERR_PARAM;
6278
6279         /* If can't find it, just return */
6280         if (!i40e_find_vlan_filter(vsi, vlan))
6281                 return I40E_ERR_PARAM;
6282
6283         mac_num = vsi->mac_num;
6284
6285         if (mac_num == 0) {
6286                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6287                 return I40E_ERR_PARAM;
6288         }
6289
6290         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6291
6292         if (mv_f == NULL) {
6293                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6294                 return I40E_ERR_NO_MEMORY;
6295         }
6296
6297         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6298
6299         if (ret != I40E_SUCCESS)
6300                 goto DONE;
6301
6302         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6303
6304         if (ret != I40E_SUCCESS)
6305                 goto DONE;
6306
6307         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6308         if (vsi->vlan_num == 1) {
6309                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6310                 if (ret != I40E_SUCCESS)
6311                         goto DONE;
6312
6313                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6314                 if (ret != I40E_SUCCESS)
6315                         goto DONE;
6316         }
6317
6318         i40e_set_vlan_filter(vsi, vlan, 0);
6319
6320         vsi->vlan_num--;
6321         ret = I40E_SUCCESS;
6322 DONE:
6323         rte_free(mv_f);
6324         return ret;
6325 }
6326
6327 int
6328 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6329 {
6330         struct i40e_mac_filter *f;
6331         struct i40e_macvlan_filter *mv_f;
6332         int i, vlan_num = 0;
6333         int ret = I40E_SUCCESS;
6334
6335         /* If it's add and we've config it, return */
6336         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6337         if (f != NULL)
6338                 return I40E_SUCCESS;
6339         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6340                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6341
6342                 /**
6343                  * If vlan_num is 0, that's the first time to add mac,
6344                  * set mask for vlan_id 0.
6345                  */
6346                 if (vsi->vlan_num == 0) {
6347                         i40e_set_vlan_filter(vsi, 0, 1);
6348                         vsi->vlan_num = 1;
6349                 }
6350                 vlan_num = vsi->vlan_num;
6351         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6352                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6353                 vlan_num = 1;
6354
6355         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6356         if (mv_f == NULL) {
6357                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6358                 return I40E_ERR_NO_MEMORY;
6359         }
6360
6361         for (i = 0; i < vlan_num; i++) {
6362                 mv_f[i].filter_type = mac_filter->filter_type;
6363                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6364                                 ETH_ADDR_LEN);
6365         }
6366
6367         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6368                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6369                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6370                                         &mac_filter->mac_addr);
6371                 if (ret != I40E_SUCCESS)
6372                         goto DONE;
6373         }
6374
6375         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6376         if (ret != I40E_SUCCESS)
6377                 goto DONE;
6378
6379         /* Add the mac addr into mac list */
6380         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6381         if (f == NULL) {
6382                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6383                 ret = I40E_ERR_NO_MEMORY;
6384                 goto DONE;
6385         }
6386         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6387                         ETH_ADDR_LEN);
6388         f->mac_info.filter_type = mac_filter->filter_type;
6389         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6390         vsi->mac_num++;
6391
6392         ret = I40E_SUCCESS;
6393 DONE:
6394         rte_free(mv_f);
6395
6396         return ret;
6397 }
6398
6399 int
6400 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6401 {
6402         struct i40e_mac_filter *f;
6403         struct i40e_macvlan_filter *mv_f;
6404         int i, vlan_num;
6405         enum rte_mac_filter_type filter_type;
6406         int ret = I40E_SUCCESS;
6407
6408         /* Can't find it, return an error */
6409         f = i40e_find_mac_filter(vsi, addr);
6410         if (f == NULL)
6411                 return I40E_ERR_PARAM;
6412
6413         vlan_num = vsi->vlan_num;
6414         filter_type = f->mac_info.filter_type;
6415         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6416                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6417                 if (vlan_num == 0) {
6418                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6419                         return I40E_ERR_PARAM;
6420                 }
6421         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6422                         filter_type == RTE_MAC_HASH_MATCH)
6423                 vlan_num = 1;
6424
6425         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6426         if (mv_f == NULL) {
6427                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6428                 return I40E_ERR_NO_MEMORY;
6429         }
6430
6431         for (i = 0; i < vlan_num; i++) {
6432                 mv_f[i].filter_type = filter_type;
6433                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6434                                 ETH_ADDR_LEN);
6435         }
6436         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6437                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6438                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6439                 if (ret != I40E_SUCCESS)
6440                         goto DONE;
6441         }
6442
6443         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6444         if (ret != I40E_SUCCESS)
6445                 goto DONE;
6446
6447         /* Remove the mac addr into mac list */
6448         TAILQ_REMOVE(&vsi->mac_list, f, next);
6449         rte_free(f);
6450         vsi->mac_num--;
6451
6452         ret = I40E_SUCCESS;
6453 DONE:
6454         rte_free(mv_f);
6455         return ret;
6456 }
6457
6458 /* Configure hash enable flags for RSS */
6459 uint64_t
6460 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6461 {
6462         uint64_t hena = 0;
6463
6464         if (!flags)
6465                 return hena;
6466
6467         if (flags & ETH_RSS_FRAG_IPV4)
6468                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6469         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6470                 if (type == I40E_MAC_X722) {
6471                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6472                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6473                 } else
6474                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6475         }
6476         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6477                 if (type == I40E_MAC_X722) {
6478                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6479                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6480                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6481                 } else
6482                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6483         }
6484         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6485                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6486         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6487                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6488         if (flags & ETH_RSS_FRAG_IPV6)
6489                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6490         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6491                 if (type == I40E_MAC_X722) {
6492                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6493                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6494                 } else
6495                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6496         }
6497         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6498                 if (type == I40E_MAC_X722) {
6499                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6500                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6501                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6502                 } else
6503                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6504         }
6505         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6506                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6507         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6508                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6509         if (flags & ETH_RSS_L2_PAYLOAD)
6510                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6511
6512         return hena;
6513 }
6514
6515 /* Parse the hash enable flags */
6516 uint64_t
6517 i40e_parse_hena(uint64_t flags)
6518 {
6519         uint64_t rss_hf = 0;
6520
6521         if (!flags)
6522                 return rss_hf;
6523         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6524                 rss_hf |= ETH_RSS_FRAG_IPV4;
6525         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6526                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6527         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6528                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6529         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6530                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6531         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6532                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6533         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6534                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6535         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6536                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6537         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6538                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6539         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6540                 rss_hf |= ETH_RSS_FRAG_IPV6;
6541         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6542                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6543         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6544                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6545         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6546                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6547         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6548                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6549         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6550                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6551         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6552                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6553         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6554                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6555         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6556                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6557
6558         return rss_hf;
6559 }
6560
6561 /* Disable RSS */
6562 static void
6563 i40e_pf_disable_rss(struct i40e_pf *pf)
6564 {
6565         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6566         uint64_t hena;
6567
6568         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6569         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6570         if (hw->mac.type == I40E_MAC_X722)
6571                 hena &= ~I40E_RSS_HENA_ALL_X722;
6572         else
6573                 hena &= ~I40E_RSS_HENA_ALL;
6574         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6575         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6576         I40E_WRITE_FLUSH(hw);
6577 }
6578
6579 static int
6580 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6581 {
6582         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6583         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6584         int ret = 0;
6585
6586         if (!key || key_len == 0) {
6587                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6588                 return 0;
6589         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6590                 sizeof(uint32_t)) {
6591                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6592                 return -EINVAL;
6593         }
6594
6595         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6596                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6597                         (struct i40e_aqc_get_set_rss_key_data *)key;
6598
6599                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6600                 if (ret)
6601                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6602         } else {
6603                 uint32_t *hash_key = (uint32_t *)key;
6604                 uint16_t i;
6605
6606                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6607                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6608                 I40E_WRITE_FLUSH(hw);
6609         }
6610
6611         return ret;
6612 }
6613
6614 static int
6615 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6616 {
6617         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6618         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6619         int ret;
6620
6621         if (!key || !key_len)
6622                 return -EINVAL;
6623
6624         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6625                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6626                         (struct i40e_aqc_get_set_rss_key_data *)key);
6627                 if (ret) {
6628                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6629                         return ret;
6630                 }
6631         } else {
6632                 uint32_t *key_dw = (uint32_t *)key;
6633                 uint16_t i;
6634
6635                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6636                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6637         }
6638         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6639
6640         return 0;
6641 }
6642
6643 static int
6644 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6645 {
6646         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6647         uint64_t rss_hf;
6648         uint64_t hena;
6649         int ret;
6650
6651         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6652                                rss_conf->rss_key_len);
6653         if (ret)
6654                 return ret;
6655
6656         rss_hf = rss_conf->rss_hf;
6657         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6658         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6659         if (hw->mac.type == I40E_MAC_X722)
6660                 hena &= ~I40E_RSS_HENA_ALL_X722;
6661         else
6662                 hena &= ~I40E_RSS_HENA_ALL;
6663         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6664         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6665         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6666         I40E_WRITE_FLUSH(hw);
6667
6668         return 0;
6669 }
6670
6671 static int
6672 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6673                          struct rte_eth_rss_conf *rss_conf)
6674 {
6675         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6676         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6677         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6678         uint64_t hena;
6679
6680         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6681         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6682         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6683                  ? I40E_RSS_HENA_ALL_X722
6684                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6685                 if (rss_hf != 0) /* Enable RSS */
6686                         return -EINVAL;
6687                 return 0; /* Nothing to do */
6688         }
6689         /* RSS enabled */
6690         if (rss_hf == 0) /* Disable RSS */
6691                 return -EINVAL;
6692
6693         return i40e_hw_rss_hash_set(pf, rss_conf);
6694 }
6695
6696 static int
6697 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6698                            struct rte_eth_rss_conf *rss_conf)
6699 {
6700         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6701         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6702         uint64_t hena;
6703
6704         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6705                          &rss_conf->rss_key_len);
6706
6707         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6708         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6709         rss_conf->rss_hf = i40e_parse_hena(hena);
6710
6711         return 0;
6712 }
6713
6714 static int
6715 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6716 {
6717         switch (filter_type) {
6718         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6719                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6720                 break;
6721         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6722                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6723                 break;
6724         case RTE_TUNNEL_FILTER_IMAC_TENID:
6725                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6726                 break;
6727         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6728                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6729                 break;
6730         case ETH_TUNNEL_FILTER_IMAC:
6731                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6732                 break;
6733         case ETH_TUNNEL_FILTER_OIP:
6734                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6735                 break;
6736         case ETH_TUNNEL_FILTER_IIP:
6737                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6738                 break;
6739         default:
6740                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6741                 return -EINVAL;
6742         }
6743
6744         return 0;
6745 }
6746
6747 /* Convert tunnel filter structure */
6748 static int
6749 i40e_tunnel_filter_convert(
6750         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6751         struct i40e_tunnel_filter *tunnel_filter)
6752 {
6753         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6754                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6755         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6756                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6757         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6758         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6759              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6760             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6761                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6762         else
6763                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6764         tunnel_filter->input.flags = cld_filter->element.flags;
6765         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6766         tunnel_filter->queue = cld_filter->element.queue_number;
6767         rte_memcpy(tunnel_filter->input.general_fields,
6768                    cld_filter->general_fields,
6769                    sizeof(cld_filter->general_fields));
6770
6771         return 0;
6772 }
6773
6774 /* Check if there exists the tunnel filter */
6775 struct i40e_tunnel_filter *
6776 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6777                              const struct i40e_tunnel_filter_input *input)
6778 {
6779         int ret;
6780
6781         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6782         if (ret < 0)
6783                 return NULL;
6784
6785         return tunnel_rule->hash_map[ret];
6786 }
6787
6788 /* Add a tunnel filter into the SW list */
6789 static int
6790 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6791                              struct i40e_tunnel_filter *tunnel_filter)
6792 {
6793         struct i40e_tunnel_rule *rule = &pf->tunnel;
6794         int ret;
6795
6796         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6797         if (ret < 0) {
6798                 PMD_DRV_LOG(ERR,
6799                             "Failed to insert tunnel filter to hash table %d!",
6800                             ret);
6801                 return ret;
6802         }
6803         rule->hash_map[ret] = tunnel_filter;
6804
6805         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6806
6807         return 0;
6808 }
6809
6810 /* Delete a tunnel filter from the SW list */
6811 int
6812 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6813                           struct i40e_tunnel_filter_input *input)
6814 {
6815         struct i40e_tunnel_rule *rule = &pf->tunnel;
6816         struct i40e_tunnel_filter *tunnel_filter;
6817         int ret;
6818
6819         ret = rte_hash_del_key(rule->hash_table, input);
6820         if (ret < 0) {
6821                 PMD_DRV_LOG(ERR,
6822                             "Failed to delete tunnel filter to hash table %d!",
6823                             ret);
6824                 return ret;
6825         }
6826         tunnel_filter = rule->hash_map[ret];
6827         rule->hash_map[ret] = NULL;
6828
6829         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6830         rte_free(tunnel_filter);
6831
6832         return 0;
6833 }
6834
6835 int
6836 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6837                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6838                         uint8_t add)
6839 {
6840         uint16_t ip_type;
6841         uint32_t ipv4_addr;
6842         uint8_t i, tun_type = 0;
6843         /* internal varialbe to convert ipv6 byte order */
6844         uint32_t convert_ipv6[4];
6845         int val, ret = 0;
6846         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6847         struct i40e_vsi *vsi = pf->main_vsi;
6848         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6849         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6850         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6851         struct i40e_tunnel_filter *tunnel, *node;
6852         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6853
6854         cld_filter = rte_zmalloc("tunnel_filter",
6855                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6856         0);
6857
6858         if (NULL == cld_filter) {
6859                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6860                 return -ENOMEM;
6861         }
6862         pfilter = cld_filter;
6863
6864         ether_addr_copy(&tunnel_filter->outer_mac,
6865                         (struct ether_addr *)&pfilter->element.outer_mac);
6866         ether_addr_copy(&tunnel_filter->inner_mac,
6867                         (struct ether_addr *)&pfilter->element.inner_mac);
6868
6869         pfilter->element.inner_vlan =
6870                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6871         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6872                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6873                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6874                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6875                                 &rte_cpu_to_le_32(ipv4_addr),
6876                                 sizeof(pfilter->element.ipaddr.v4.data));
6877         } else {
6878                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6879                 for (i = 0; i < 4; i++) {
6880                         convert_ipv6[i] =
6881                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6882                 }
6883                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6884                            &convert_ipv6,
6885                            sizeof(pfilter->element.ipaddr.v6.data));
6886         }
6887
6888         /* check tunneled type */
6889         switch (tunnel_filter->tunnel_type) {
6890         case RTE_TUNNEL_TYPE_VXLAN:
6891                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6892                 break;
6893         case RTE_TUNNEL_TYPE_NVGRE:
6894                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6895                 break;
6896         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6897                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6898                 break;
6899         default:
6900                 /* Other tunnel types is not supported. */
6901                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6902                 rte_free(cld_filter);
6903                 return -EINVAL;
6904         }
6905
6906         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6907                                        &pfilter->element.flags);
6908         if (val < 0) {
6909                 rte_free(cld_filter);
6910                 return -EINVAL;
6911         }
6912
6913         pfilter->element.flags |= rte_cpu_to_le_16(
6914                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6915                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6916         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6917         pfilter->element.queue_number =
6918                 rte_cpu_to_le_16(tunnel_filter->queue_id);
6919
6920         /* Check if there is the filter in SW list */
6921         memset(&check_filter, 0, sizeof(check_filter));
6922         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6923         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6924         if (add && node) {
6925                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6926                 return -EINVAL;
6927         }
6928
6929         if (!add && !node) {
6930                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6931                 return -EINVAL;
6932         }
6933
6934         if (add) {
6935                 ret = i40e_aq_add_cloud_filters(hw,
6936                                         vsi->seid, &cld_filter->element, 1);
6937                 if (ret < 0) {
6938                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6939                         return -ENOTSUP;
6940                 }
6941                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6942                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6943                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6944         } else {
6945                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6946                                                    &cld_filter->element, 1);
6947                 if (ret < 0) {
6948                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6949                         return -ENOTSUP;
6950                 }
6951                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6952         }
6953
6954         rte_free(cld_filter);
6955         return ret;
6956 }
6957
6958 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
6959 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
6960 #define I40E_TR_GENEVE_KEY_MASK                 0x8
6961 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
6962 #define I40E_TR_GRE_KEY_MASK                    0x400
6963 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
6964 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
6965
6966 static enum
6967 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
6968 {
6969         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
6970         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
6971         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6972         enum i40e_status_code status = I40E_SUCCESS;
6973
6974         memset(&filter_replace, 0,
6975                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
6976         memset(&filter_replace_buf, 0,
6977                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
6978
6979         /* create L1 filter */
6980         filter_replace.old_filter_type =
6981                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
6982         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
6983         filter_replace.tr_bit = 0;
6984
6985         /* Prepare the buffer, 3 entries */
6986         filter_replace_buf.data[0] =
6987                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
6988         filter_replace_buf.data[0] |=
6989                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6990         filter_replace_buf.data[2] = 0xFF;
6991         filter_replace_buf.data[3] = 0xFF;
6992         filter_replace_buf.data[4] =
6993                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
6994         filter_replace_buf.data[4] |=
6995                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6996         filter_replace_buf.data[7] = 0xF0;
6997         filter_replace_buf.data[8]
6998                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
6999         filter_replace_buf.data[8] |=
7000                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7001         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7002                 I40E_TR_GENEVE_KEY_MASK |
7003                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7004         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7005                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7006                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7007
7008         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7009                                                &filter_replace_buf);
7010         return status;
7011 }
7012
7013 static enum
7014 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7015 {
7016         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7017         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7018         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7019         enum i40e_status_code status = I40E_SUCCESS;
7020
7021         /* For MPLSoUDP */
7022         memset(&filter_replace, 0,
7023                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7024         memset(&filter_replace_buf, 0,
7025                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7026         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7027                 I40E_AQC_MIRROR_CLOUD_FILTER;
7028         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7029         filter_replace.new_filter_type =
7030                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7031         /* Prepare the buffer, 2 entries */
7032         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7033         filter_replace_buf.data[0] |=
7034                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7035         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7036         filter_replace_buf.data[4] |=
7037                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7038         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7039                                                &filter_replace_buf);
7040         if (status < 0)
7041                 return status;
7042
7043         /* For MPLSoGRE */
7044         memset(&filter_replace, 0,
7045                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7046         memset(&filter_replace_buf, 0,
7047                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7048
7049         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7050                 I40E_AQC_MIRROR_CLOUD_FILTER;
7051         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7052         filter_replace.new_filter_type =
7053                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7054         /* Prepare the buffer, 2 entries */
7055         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7056         filter_replace_buf.data[0] |=
7057                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7058         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7059         filter_replace_buf.data[4] |=
7060                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7061
7062         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7063                                                &filter_replace_buf);
7064         return status;
7065 }
7066
7067 int
7068 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7069                       struct i40e_tunnel_filter_conf *tunnel_filter,
7070                       uint8_t add)
7071 {
7072         uint16_t ip_type;
7073         uint32_t ipv4_addr;
7074         uint8_t i, tun_type = 0;
7075         /* internal variable to convert ipv6 byte order */
7076         uint32_t convert_ipv6[4];
7077         int val, ret = 0;
7078         struct i40e_pf_vf *vf = NULL;
7079         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7080         struct i40e_vsi *vsi;
7081         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7082         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7083         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7084         struct i40e_tunnel_filter *tunnel, *node;
7085         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7086         uint32_t teid_le;
7087         bool big_buffer = 0;
7088
7089         cld_filter = rte_zmalloc("tunnel_filter",
7090                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7091                          0);
7092
7093         if (cld_filter == NULL) {
7094                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7095                 return -ENOMEM;
7096         }
7097         pfilter = cld_filter;
7098
7099         ether_addr_copy(&tunnel_filter->outer_mac,
7100                         (struct ether_addr *)&pfilter->element.outer_mac);
7101         ether_addr_copy(&tunnel_filter->inner_mac,
7102                         (struct ether_addr *)&pfilter->element.inner_mac);
7103
7104         pfilter->element.inner_vlan =
7105                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7106         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7107                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7108                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7109                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7110                                 &rte_cpu_to_le_32(ipv4_addr),
7111                                 sizeof(pfilter->element.ipaddr.v4.data));
7112         } else {
7113                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7114                 for (i = 0; i < 4; i++) {
7115                         convert_ipv6[i] =
7116                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7117                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7118                 }
7119                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7120                            &convert_ipv6,
7121                            sizeof(pfilter->element.ipaddr.v6.data));
7122         }
7123
7124         /* check tunneled type */
7125         switch (tunnel_filter->tunnel_type) {
7126         case I40E_TUNNEL_TYPE_VXLAN:
7127                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7128                 break;
7129         case I40E_TUNNEL_TYPE_NVGRE:
7130                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7131                 break;
7132         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7133                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7134                 break;
7135         case I40E_TUNNEL_TYPE_MPLSoUDP:
7136                 if (!pf->mpls_replace_flag) {
7137                         i40e_replace_mpls_l1_filter(pf);
7138                         i40e_replace_mpls_cloud_filter(pf);
7139                         pf->mpls_replace_flag = 1;
7140                 }
7141                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7142                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7143                         teid_le >> 4;
7144                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7145                         (teid_le & 0xF) << 12;
7146                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7147                         0x40;
7148                 big_buffer = 1;
7149                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7150                 break;
7151         case I40E_TUNNEL_TYPE_MPLSoGRE:
7152                 if (!pf->mpls_replace_flag) {
7153                         i40e_replace_mpls_l1_filter(pf);
7154                         i40e_replace_mpls_cloud_filter(pf);
7155                         pf->mpls_replace_flag = 1;
7156                 }
7157                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7158                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7159                         teid_le >> 4;
7160                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7161                         (teid_le & 0xF) << 12;
7162                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7163                         0x0;
7164                 big_buffer = 1;
7165                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7166                 break;
7167         case I40E_TUNNEL_TYPE_QINQ:
7168                 if (!pf->qinq_replace_flag) {
7169                         ret = i40e_cloud_filter_qinq_create(pf);
7170                         if (ret < 0)
7171                                 PMD_DRV_LOG(ERR,
7172                                         "Failed to create a qinq tunnel filter.");
7173                         pf->qinq_replace_flag = 1;
7174                 }
7175                 /*      Add in the General fields the values of
7176                  *      the Outer and Inner VLAN
7177                  *      Big Buffer should be set, see changes in
7178                  *      i40e_aq_add_cloud_filters
7179                  */
7180                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7181                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7182                 big_buffer = 1;
7183                 break;
7184         default:
7185                 /* Other tunnel types is not supported. */
7186                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7187                 rte_free(cld_filter);
7188                 return -EINVAL;
7189         }
7190
7191         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7192                 pfilter->element.flags =
7193                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7194         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7195                 pfilter->element.flags =
7196                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7197         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7198                 pfilter->element.flags |=
7199                         I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7200         else {
7201                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7202                                                 &pfilter->element.flags);
7203                 if (val < 0) {
7204                         rte_free(cld_filter);
7205                         return -EINVAL;
7206                 }
7207         }
7208
7209         pfilter->element.flags |= rte_cpu_to_le_16(
7210                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7211                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7212         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7213         pfilter->element.queue_number =
7214                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7215
7216         if (!tunnel_filter->is_to_vf)
7217                 vsi = pf->main_vsi;
7218         else {
7219                 if (tunnel_filter->vf_id >= pf->vf_num) {
7220                         PMD_DRV_LOG(ERR, "Invalid argument.");
7221                         return -EINVAL;
7222                 }
7223                 vf = &pf->vfs[tunnel_filter->vf_id];
7224                 vsi = vf->vsi;
7225         }
7226
7227         /* Check if there is the filter in SW list */
7228         memset(&check_filter, 0, sizeof(check_filter));
7229         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7230         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7231         check_filter.vf_id = tunnel_filter->vf_id;
7232         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7233         if (add && node) {
7234                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7235                 return -EINVAL;
7236         }
7237
7238         if (!add && !node) {
7239                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7240                 return -EINVAL;
7241         }
7242
7243         if (add) {
7244                 if (big_buffer)
7245                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7246                                                    vsi->seid, cld_filter, 1);
7247                 else
7248                         ret = i40e_aq_add_cloud_filters(hw,
7249                                         vsi->seid, &cld_filter->element, 1);
7250                 if (ret < 0) {
7251                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7252                         return -ENOTSUP;
7253                 }
7254                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7255                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7256                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7257         } else {
7258                 if (big_buffer)
7259                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7260                                 hw, vsi->seid, cld_filter, 1);
7261                 else
7262                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7263                                                    &cld_filter->element, 1);
7264                 if (ret < 0) {
7265                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7266                         return -ENOTSUP;
7267                 }
7268                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7269         }
7270
7271         rte_free(cld_filter);
7272         return ret;
7273 }
7274
7275 static int
7276 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7277 {
7278         uint8_t i;
7279
7280         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7281                 if (pf->vxlan_ports[i] == port)
7282                         return i;
7283         }
7284
7285         return -1;
7286 }
7287
7288 static int
7289 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7290 {
7291         int  idx, ret;
7292         uint8_t filter_idx;
7293         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7294
7295         idx = i40e_get_vxlan_port_idx(pf, port);
7296
7297         /* Check if port already exists */
7298         if (idx >= 0) {
7299                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7300                 return -EINVAL;
7301         }
7302
7303         /* Now check if there is space to add the new port */
7304         idx = i40e_get_vxlan_port_idx(pf, 0);
7305         if (idx < 0) {
7306                 PMD_DRV_LOG(ERR,
7307                         "Maximum number of UDP ports reached, not adding port %d",
7308                         port);
7309                 return -ENOSPC;
7310         }
7311
7312         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7313                                         &filter_idx, NULL);
7314         if (ret < 0) {
7315                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7316                 return -1;
7317         }
7318
7319         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7320                          port,  filter_idx);
7321
7322         /* New port: add it and mark its index in the bitmap */
7323         pf->vxlan_ports[idx] = port;
7324         pf->vxlan_bitmap |= (1 << idx);
7325
7326         if (!(pf->flags & I40E_FLAG_VXLAN))
7327                 pf->flags |= I40E_FLAG_VXLAN;
7328
7329         return 0;
7330 }
7331
7332 static int
7333 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7334 {
7335         int idx;
7336         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7337
7338         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7339                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7340                 return -EINVAL;
7341         }
7342
7343         idx = i40e_get_vxlan_port_idx(pf, port);
7344
7345         if (idx < 0) {
7346                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7347                 return -EINVAL;
7348         }
7349
7350         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7351                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7352                 return -1;
7353         }
7354
7355         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7356                         port, idx);
7357
7358         pf->vxlan_ports[idx] = 0;
7359         pf->vxlan_bitmap &= ~(1 << idx);
7360
7361         if (!pf->vxlan_bitmap)
7362                 pf->flags &= ~I40E_FLAG_VXLAN;
7363
7364         return 0;
7365 }
7366
7367 /* Add UDP tunneling port */
7368 static int
7369 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7370                              struct rte_eth_udp_tunnel *udp_tunnel)
7371 {
7372         int ret = 0;
7373         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7374
7375         if (udp_tunnel == NULL)
7376                 return -EINVAL;
7377
7378         switch (udp_tunnel->prot_type) {
7379         case RTE_TUNNEL_TYPE_VXLAN:
7380                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7381                 break;
7382
7383         case RTE_TUNNEL_TYPE_GENEVE:
7384         case RTE_TUNNEL_TYPE_TEREDO:
7385                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7386                 ret = -1;
7387                 break;
7388
7389         default:
7390                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7391                 ret = -1;
7392                 break;
7393         }
7394
7395         return ret;
7396 }
7397
7398 /* Remove UDP tunneling port */
7399 static int
7400 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7401                              struct rte_eth_udp_tunnel *udp_tunnel)
7402 {
7403         int ret = 0;
7404         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7405
7406         if (udp_tunnel == NULL)
7407                 return -EINVAL;
7408
7409         switch (udp_tunnel->prot_type) {
7410         case RTE_TUNNEL_TYPE_VXLAN:
7411                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7412                 break;
7413         case RTE_TUNNEL_TYPE_GENEVE:
7414         case RTE_TUNNEL_TYPE_TEREDO:
7415                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7416                 ret = -1;
7417                 break;
7418         default:
7419                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7420                 ret = -1;
7421                 break;
7422         }
7423
7424         return ret;
7425 }
7426
7427 /* Calculate the maximum number of contiguous PF queues that are configured */
7428 static int
7429 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7430 {
7431         struct rte_eth_dev_data *data = pf->dev_data;
7432         int i, num;
7433         struct i40e_rx_queue *rxq;
7434
7435         num = 0;
7436         for (i = 0; i < pf->lan_nb_qps; i++) {
7437                 rxq = data->rx_queues[i];
7438                 if (rxq && rxq->q_set)
7439                         num++;
7440                 else
7441                         break;
7442         }
7443
7444         return num;
7445 }
7446
7447 /* Configure RSS */
7448 static int
7449 i40e_pf_config_rss(struct i40e_pf *pf)
7450 {
7451         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7452         struct rte_eth_rss_conf rss_conf;
7453         uint32_t i, lut = 0;
7454         uint16_t j, num;
7455
7456         /*
7457          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7458          * It's necessary to calulate the actual PF queues that are configured.
7459          */
7460         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7461                 num = i40e_pf_calc_configured_queues_num(pf);
7462         else
7463                 num = pf->dev_data->nb_rx_queues;
7464
7465         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7466         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7467                         num);
7468
7469         if (num == 0) {
7470                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7471                 return -ENOTSUP;
7472         }
7473
7474         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7475                 if (j == num)
7476                         j = 0;
7477                 lut = (lut << 8) | (j & ((0x1 <<
7478                         hw->func_caps.rss_table_entry_width) - 1));
7479                 if ((i & 3) == 3)
7480                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7481         }
7482
7483         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7484         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7485                 i40e_pf_disable_rss(pf);
7486                 return 0;
7487         }
7488         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7489                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7490                 /* Random default keys */
7491                 static uint32_t rss_key_default[] = {0x6b793944,
7492                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7493                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7494                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7495
7496                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7497                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7498                                                         sizeof(uint32_t);
7499         }
7500
7501         return i40e_hw_rss_hash_set(pf, &rss_conf);
7502 }
7503
7504 static int
7505 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7506                                struct rte_eth_tunnel_filter_conf *filter)
7507 {
7508         if (pf == NULL || filter == NULL) {
7509                 PMD_DRV_LOG(ERR, "Invalid parameter");
7510                 return -EINVAL;
7511         }
7512
7513         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7514                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7515                 return -EINVAL;
7516         }
7517
7518         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7519                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7520                 return -EINVAL;
7521         }
7522
7523         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7524                 (is_zero_ether_addr(&filter->outer_mac))) {
7525                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7526                 return -EINVAL;
7527         }
7528
7529         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7530                 (is_zero_ether_addr(&filter->inner_mac))) {
7531                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7532                 return -EINVAL;
7533         }
7534
7535         return 0;
7536 }
7537
7538 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7539 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7540 static int
7541 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7542 {
7543         uint32_t val, reg;
7544         int ret = -EINVAL;
7545
7546         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7547         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7548
7549         if (len == 3) {
7550                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7551         } else if (len == 4) {
7552                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7553         } else {
7554                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7555                 return ret;
7556         }
7557
7558         if (reg != val) {
7559                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7560                                                    reg, NULL);
7561                 if (ret != 0)
7562                         return ret;
7563         } else {
7564                 ret = 0;
7565         }
7566         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7567                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7568
7569         return ret;
7570 }
7571
7572 static int
7573 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7574 {
7575         int ret = -EINVAL;
7576
7577         if (!hw || !cfg)
7578                 return -EINVAL;
7579
7580         switch (cfg->cfg_type) {
7581         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7582                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7583                 break;
7584         default:
7585                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7586                 break;
7587         }
7588
7589         return ret;
7590 }
7591
7592 static int
7593 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7594                                enum rte_filter_op filter_op,
7595                                void *arg)
7596 {
7597         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7598         int ret = I40E_ERR_PARAM;
7599
7600         switch (filter_op) {
7601         case RTE_ETH_FILTER_SET:
7602                 ret = i40e_dev_global_config_set(hw,
7603                         (struct rte_eth_global_cfg *)arg);
7604                 break;
7605         default:
7606                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7607                 break;
7608         }
7609
7610         return ret;
7611 }
7612
7613 static int
7614 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7615                           enum rte_filter_op filter_op,
7616                           void *arg)
7617 {
7618         struct rte_eth_tunnel_filter_conf *filter;
7619         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7620         int ret = I40E_SUCCESS;
7621
7622         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7623
7624         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7625                 return I40E_ERR_PARAM;
7626
7627         switch (filter_op) {
7628         case RTE_ETH_FILTER_NOP:
7629                 if (!(pf->flags & I40E_FLAG_VXLAN))
7630                         ret = I40E_NOT_SUPPORTED;
7631                 break;
7632         case RTE_ETH_FILTER_ADD:
7633                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7634                 break;
7635         case RTE_ETH_FILTER_DELETE:
7636                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7637                 break;
7638         default:
7639                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7640                 ret = I40E_ERR_PARAM;
7641                 break;
7642         }
7643
7644         return ret;
7645 }
7646
7647 static int
7648 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7649 {
7650         int ret = 0;
7651         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7652
7653         /* RSS setup */
7654         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7655                 ret = i40e_pf_config_rss(pf);
7656         else
7657                 i40e_pf_disable_rss(pf);
7658
7659         return ret;
7660 }
7661
7662 /* Get the symmetric hash enable configurations per port */
7663 static void
7664 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7665 {
7666         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7667
7668         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7669 }
7670
7671 /* Set the symmetric hash enable configurations per port */
7672 static void
7673 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7674 {
7675         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7676
7677         if (enable > 0) {
7678                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7679                         PMD_DRV_LOG(INFO,
7680                                 "Symmetric hash has already been enabled");
7681                         return;
7682                 }
7683                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7684         } else {
7685                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7686                         PMD_DRV_LOG(INFO,
7687                                 "Symmetric hash has already been disabled");
7688                         return;
7689                 }
7690                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7691         }
7692         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7693         I40E_WRITE_FLUSH(hw);
7694 }
7695
7696 /*
7697  * Get global configurations of hash function type and symmetric hash enable
7698  * per flow type (pctype). Note that global configuration means it affects all
7699  * the ports on the same NIC.
7700  */
7701 static int
7702 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7703                                    struct rte_eth_hash_global_conf *g_cfg)
7704 {
7705         uint32_t reg, mask = I40E_FLOW_TYPES;
7706         uint16_t i;
7707         enum i40e_filter_pctype pctype;
7708
7709         memset(g_cfg, 0, sizeof(*g_cfg));
7710         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7711         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7712                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7713         else
7714                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7715         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7716                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7717
7718         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7719                 if (!(mask & (1UL << i)))
7720                         continue;
7721                 mask &= ~(1UL << i);
7722                 /* Bit set indicats the coresponding flow type is supported */
7723                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7724                 /* if flowtype is invalid, continue */
7725                 if (!I40E_VALID_FLOW(i))
7726                         continue;
7727                 pctype = i40e_flowtype_to_pctype(i);
7728                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7729                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7730                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7731         }
7732
7733         return 0;
7734 }
7735
7736 static int
7737 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7738 {
7739         uint32_t i;
7740         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7741
7742         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7743                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7744                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7745                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7746                                                 g_cfg->hash_func);
7747                 return -EINVAL;
7748         }
7749
7750         /*
7751          * As i40e supports less than 32 flow types, only first 32 bits need to
7752          * be checked.
7753          */
7754         mask0 = g_cfg->valid_bit_mask[0];
7755         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7756                 if (i == 0) {
7757                         /* Check if any unsupported flow type configured */
7758                         if ((mask0 | i40e_mask) ^ i40e_mask)
7759                                 goto mask_err;
7760                 } else {
7761                         if (g_cfg->valid_bit_mask[i])
7762                                 goto mask_err;
7763                 }
7764         }
7765
7766         return 0;
7767
7768 mask_err:
7769         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7770
7771         return -EINVAL;
7772 }
7773
7774 /*
7775  * Set global configurations of hash function type and symmetric hash enable
7776  * per flow type (pctype). Note any modifying global configuration will affect
7777  * all the ports on the same NIC.
7778  */
7779 static int
7780 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7781                                    struct rte_eth_hash_global_conf *g_cfg)
7782 {
7783         int ret;
7784         uint16_t i;
7785         uint32_t reg;
7786         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7787         enum i40e_filter_pctype pctype;
7788
7789         /* Check the input parameters */
7790         ret = i40e_hash_global_config_check(g_cfg);
7791         if (ret < 0)
7792                 return ret;
7793
7794         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7795                 if (!(mask0 & (1UL << i)))
7796                         continue;
7797                 mask0 &= ~(1UL << i);
7798                 /* if flowtype is invalid, continue */
7799                 if (!I40E_VALID_FLOW(i))
7800                         continue;
7801                 pctype = i40e_flowtype_to_pctype(i);
7802                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7803                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7804                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7805         }
7806
7807         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7808         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7809                 /* Toeplitz */
7810                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7811                         PMD_DRV_LOG(DEBUG,
7812                                 "Hash function already set to Toeplitz");
7813                         goto out;
7814                 }
7815                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7816         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7817                 /* Simple XOR */
7818                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7819                         PMD_DRV_LOG(DEBUG,
7820                                 "Hash function already set to Simple XOR");
7821                         goto out;
7822                 }
7823                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7824         } else
7825                 /* Use the default, and keep it as it is */
7826                 goto out;
7827
7828         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7829
7830 out:
7831         I40E_WRITE_FLUSH(hw);
7832
7833         return 0;
7834 }
7835
7836 /**
7837  * Valid input sets for hash and flow director filters per PCTYPE
7838  */
7839 static uint64_t
7840 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7841                 enum rte_filter_type filter)
7842 {
7843         uint64_t valid;
7844
7845         static const uint64_t valid_hash_inset_table[] = {
7846                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7847                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7848                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7849                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7850                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7851                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7852                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7853                         I40E_INSET_FLEX_PAYLOAD,
7854                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7855                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7856                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7857                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7858                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7859                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7860                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7861                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7862                         I40E_INSET_FLEX_PAYLOAD,
7863                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7864                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7865                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7866                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7867                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7868                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7869                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7870                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7871                         I40E_INSET_FLEX_PAYLOAD,
7872                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7873                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7874                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7875                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7876                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7877                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7878                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7879                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7880                         I40E_INSET_FLEX_PAYLOAD,
7881                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7882                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7883                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7884                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7885                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7886                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7887                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7888                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7889                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7890                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7891                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7892                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7893                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7894                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7895                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7896                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7897                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7898                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7899                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7900                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7901                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7902                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7903                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7904                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7905                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7906                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7907                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7908                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7909                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7910                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7911                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7912                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7913                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7914                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7915                         I40E_INSET_FLEX_PAYLOAD,
7916                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7917                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7918                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7919                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7920                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7921                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7922                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7923                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7924                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7925                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7926                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7927                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7928                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7929                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7930                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7931                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7932                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7933                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7934                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7935                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7936                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7937                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7938                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7939                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7940                         I40E_INSET_FLEX_PAYLOAD,
7941                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7942                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7943                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7944                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7945                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7946                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7947                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7948                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7949                         I40E_INSET_FLEX_PAYLOAD,
7950                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7951                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7952                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7953                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7954                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7955                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7956                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7957                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7958                         I40E_INSET_FLEX_PAYLOAD,
7959                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7960                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7961                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7962                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7963                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7964                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7965                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7966                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7967                         I40E_INSET_FLEX_PAYLOAD,
7968                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7969                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7970                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7971                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7972                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7973                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7974                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7975                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7976                         I40E_INSET_FLEX_PAYLOAD,
7977                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7978                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7979                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7980                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7981                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7982                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7983                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7984                         I40E_INSET_FLEX_PAYLOAD,
7985                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7986                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7987                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7988                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7989                         I40E_INSET_FLEX_PAYLOAD,
7990         };
7991
7992         /**
7993          * Flow director supports only fields defined in
7994          * union rte_eth_fdir_flow.
7995          */
7996         static const uint64_t valid_fdir_inset_table[] = {
7997                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7998                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7999                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8000                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8001                 I40E_INSET_IPV4_TTL,
8002                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8003                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8004                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8005                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8006                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8007                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8008                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8009                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8010                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8011                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8012                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8013                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8014                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8015                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8016                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8017                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8018                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8019                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8020                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8021                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8022                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8023                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8024                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8025                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8026                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8027                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8028                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8029                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8030                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8031                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8032                 I40E_INSET_SCTP_VT,
8033                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8034                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8035                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8036                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8037                 I40E_INSET_IPV4_TTL,
8038                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8039                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8040                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8041                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8042                 I40E_INSET_IPV6_HOP_LIMIT,
8043                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8044                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8045                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8046                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8047                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8048                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8049                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8050                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8051                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8052                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8053                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8054                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8055                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8056                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8057                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8058                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8059                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8060                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8061                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8062                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8063                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8064                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8065                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8066                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8067                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8068                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8069                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8070                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8071                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8072                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8073                 I40E_INSET_SCTP_VT,
8074                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8075                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8076                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8077                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8078                 I40E_INSET_IPV6_HOP_LIMIT,
8079                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8080                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8081                 I40E_INSET_LAST_ETHER_TYPE,
8082         };
8083
8084         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8085                 return 0;
8086         if (filter == RTE_ETH_FILTER_HASH)
8087                 valid = valid_hash_inset_table[pctype];
8088         else
8089                 valid = valid_fdir_inset_table[pctype];
8090
8091         return valid;
8092 }
8093
8094 /**
8095  * Validate if the input set is allowed for a specific PCTYPE
8096  */
8097 static int
8098 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8099                 enum rte_filter_type filter, uint64_t inset)
8100 {
8101         uint64_t valid;
8102
8103         valid = i40e_get_valid_input_set(pctype, filter);
8104         if (inset & (~valid))
8105                 return -EINVAL;
8106
8107         return 0;
8108 }
8109
8110 /* default input set fields combination per pctype */
8111 uint64_t
8112 i40e_get_default_input_set(uint16_t pctype)
8113 {
8114         static const uint64_t default_inset_table[] = {
8115                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8116                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8117                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8118                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8119                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8120                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8121                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8122                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8123                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8124                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8125                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8126                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8127                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8128                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8129                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8130                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8131                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8132                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8133                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8134                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8135                         I40E_INSET_SCTP_VT,
8136                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8137                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8138                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8139                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8140                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8141                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8142                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8143                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8144                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8145                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8146                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8147                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8148                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8149                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8150                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8151                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8152                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8153                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8154                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8155                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8156                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8157                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8158                         I40E_INSET_SCTP_VT,
8159                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8160                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8161                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8162                         I40E_INSET_LAST_ETHER_TYPE,
8163         };
8164
8165         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8166                 return 0;
8167
8168         return default_inset_table[pctype];
8169 }
8170
8171 /**
8172  * Parse the input set from index to logical bit masks
8173  */
8174 static int
8175 i40e_parse_input_set(uint64_t *inset,
8176                      enum i40e_filter_pctype pctype,
8177                      enum rte_eth_input_set_field *field,
8178                      uint16_t size)
8179 {
8180         uint16_t i, j;
8181         int ret = -EINVAL;
8182
8183         static const struct {
8184                 enum rte_eth_input_set_field field;
8185                 uint64_t inset;
8186         } inset_convert_table[] = {
8187                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8188                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8189                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8190                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8191                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8192                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8193                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8194                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8195                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8196                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8197                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8198                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8199                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8200                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8201                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8202                         I40E_INSET_IPV6_NEXT_HDR},
8203                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8204                         I40E_INSET_IPV6_HOP_LIMIT},
8205                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8206                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8207                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8208                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8209                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8210                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8211                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8212                         I40E_INSET_SCTP_VT},
8213                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8214                         I40E_INSET_TUNNEL_DMAC},
8215                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8216                         I40E_INSET_VLAN_TUNNEL},
8217                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8218                         I40E_INSET_TUNNEL_ID},
8219                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8220                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8221                         I40E_INSET_FLEX_PAYLOAD_W1},
8222                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8223                         I40E_INSET_FLEX_PAYLOAD_W2},
8224                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8225                         I40E_INSET_FLEX_PAYLOAD_W3},
8226                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8227                         I40E_INSET_FLEX_PAYLOAD_W4},
8228                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8229                         I40E_INSET_FLEX_PAYLOAD_W5},
8230                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8231                         I40E_INSET_FLEX_PAYLOAD_W6},
8232                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8233                         I40E_INSET_FLEX_PAYLOAD_W7},
8234                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8235                         I40E_INSET_FLEX_PAYLOAD_W8},
8236         };
8237
8238         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8239                 return ret;
8240
8241         /* Only one item allowed for default or all */
8242         if (size == 1) {
8243                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8244                         *inset = i40e_get_default_input_set(pctype);
8245                         return 0;
8246                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8247                         *inset = I40E_INSET_NONE;
8248                         return 0;
8249                 }
8250         }
8251
8252         for (i = 0, *inset = 0; i < size; i++) {
8253                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8254                         if (field[i] == inset_convert_table[j].field) {
8255                                 *inset |= inset_convert_table[j].inset;
8256                                 break;
8257                         }
8258                 }
8259
8260                 /* It contains unsupported input set, return immediately */
8261                 if (j == RTE_DIM(inset_convert_table))
8262                         return ret;
8263         }
8264
8265         return 0;
8266 }
8267
8268 /**
8269  * Translate the input set from bit masks to register aware bit masks
8270  * and vice versa
8271  */
8272 static uint64_t
8273 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8274 {
8275         uint64_t val = 0;
8276         uint16_t i;
8277
8278         struct inset_map {
8279                 uint64_t inset;
8280                 uint64_t inset_reg;
8281         };
8282
8283         static const struct inset_map inset_map_common[] = {
8284                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8285                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8286                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8287                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8288                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8289                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8290                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8291                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8292                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8293                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8294                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8295                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8296                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8297                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8298                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8299                 {I40E_INSET_TUNNEL_DMAC,
8300                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8301                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8302                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8303                 {I40E_INSET_TUNNEL_SRC_PORT,
8304                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8305                 {I40E_INSET_TUNNEL_DST_PORT,
8306                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8307                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8308                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8309                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8310                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8311                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8312                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8313                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8314                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8315                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8316         };
8317
8318     /* some different registers map in x722*/
8319         static const struct inset_map inset_map_diff_x722[] = {
8320                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8321                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8322                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8323                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8324         };
8325
8326         static const struct inset_map inset_map_diff_not_x722[] = {
8327                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8328                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8329                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8330                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8331         };
8332
8333         if (input == 0)
8334                 return val;
8335
8336         /* Translate input set to register aware inset */
8337         if (type == I40E_MAC_X722) {
8338                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8339                         if (input & inset_map_diff_x722[i].inset)
8340                                 val |= inset_map_diff_x722[i].inset_reg;
8341                 }
8342         } else {
8343                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8344                         if (input & inset_map_diff_not_x722[i].inset)
8345                                 val |= inset_map_diff_not_x722[i].inset_reg;
8346                 }
8347         }
8348
8349         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8350                 if (input & inset_map_common[i].inset)
8351                         val |= inset_map_common[i].inset_reg;
8352         }
8353
8354         return val;
8355 }
8356
8357 static int
8358 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8359 {
8360         uint8_t i, idx = 0;
8361         uint64_t inset_need_mask = inset;
8362
8363         static const struct {
8364                 uint64_t inset;
8365                 uint32_t mask;
8366         } inset_mask_map[] = {
8367                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8368                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8369                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8370                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8371                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8372                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8373                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8374                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8375         };
8376
8377         if (!inset || !mask || !nb_elem)
8378                 return 0;
8379
8380         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8381                 /* Clear the inset bit, if no MASK is required,
8382                  * for example proto + ttl
8383                  */
8384                 if ((inset & inset_mask_map[i].inset) ==
8385                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8386                         inset_need_mask &= ~inset_mask_map[i].inset;
8387                 if (!inset_need_mask)
8388                         return 0;
8389         }
8390         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8391                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8392                     inset_mask_map[i].inset) {
8393                         if (idx >= nb_elem) {
8394                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8395                                 return -EINVAL;
8396                         }
8397                         mask[idx] = inset_mask_map[i].mask;
8398                         idx++;
8399                 }
8400         }
8401
8402         return idx;
8403 }
8404
8405 static void
8406 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8407 {
8408         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8409
8410         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8411         if (reg != val)
8412                 i40e_write_rx_ctl(hw, addr, val);
8413         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8414                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8415 }
8416
8417 static void
8418 i40e_filter_input_set_init(struct i40e_pf *pf)
8419 {
8420         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8421         enum i40e_filter_pctype pctype;
8422         uint64_t input_set, inset_reg;
8423         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8424         int num, i;
8425
8426         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8427              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8428                 if (hw->mac.type == I40E_MAC_X722) {
8429                         if (!I40E_VALID_PCTYPE_X722(pctype))
8430                                 continue;
8431                 } else {
8432                         if (!I40E_VALID_PCTYPE(pctype))
8433                                 continue;
8434                 }
8435
8436                 input_set = i40e_get_default_input_set(pctype);
8437
8438                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8439                                                    I40E_INSET_MASK_NUM_REG);
8440                 if (num < 0)
8441                         return;
8442                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8443                                         input_set);
8444
8445                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8446                                       (uint32_t)(inset_reg & UINT32_MAX));
8447                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8448                                      (uint32_t)((inset_reg >>
8449                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8450                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8451                                       (uint32_t)(inset_reg & UINT32_MAX));
8452                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8453                                      (uint32_t)((inset_reg >>
8454                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8455
8456                 for (i = 0; i < num; i++) {
8457                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8458                                              mask_reg[i]);
8459                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8460                                              mask_reg[i]);
8461                 }
8462                 /*clear unused mask registers of the pctype */
8463                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8464                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8465                                              0);
8466                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8467                                              0);
8468                 }
8469                 I40E_WRITE_FLUSH(hw);
8470
8471                 /* store the default input set */
8472                 pf->hash_input_set[pctype] = input_set;
8473                 pf->fdir.input_set[pctype] = input_set;
8474         }
8475 }
8476
8477 int
8478 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8479                          struct rte_eth_input_set_conf *conf)
8480 {
8481         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8482         enum i40e_filter_pctype pctype;
8483         uint64_t input_set, inset_reg = 0;
8484         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8485         int ret, i, num;
8486
8487         if (!conf) {
8488                 PMD_DRV_LOG(ERR, "Invalid pointer");
8489                 return -EFAULT;
8490         }
8491         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8492             conf->op != RTE_ETH_INPUT_SET_ADD) {
8493                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8494                 return -EINVAL;
8495         }
8496
8497         if (!I40E_VALID_FLOW(conf->flow_type)) {
8498                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8499                 return -EINVAL;
8500         }
8501
8502         if (hw->mac.type == I40E_MAC_X722) {
8503                 /* get translated pctype value in fd pctype register */
8504                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8505                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8506                         conf->flow_type)));
8507         } else
8508                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8509
8510         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8511                                    conf->inset_size);
8512         if (ret) {
8513                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8514                 return -EINVAL;
8515         }
8516         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8517                                     input_set) != 0) {
8518                 PMD_DRV_LOG(ERR, "Invalid input set");
8519                 return -EINVAL;
8520         }
8521         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8522                 /* get inset value in register */
8523                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8524                 inset_reg <<= I40E_32_BIT_WIDTH;
8525                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8526                 input_set |= pf->hash_input_set[pctype];
8527         }
8528         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8529                                            I40E_INSET_MASK_NUM_REG);
8530         if (num < 0)
8531                 return -EINVAL;
8532
8533         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8534
8535         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8536                               (uint32_t)(inset_reg & UINT32_MAX));
8537         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8538                              (uint32_t)((inset_reg >>
8539                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8540
8541         for (i = 0; i < num; i++)
8542                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8543                                      mask_reg[i]);
8544         /*clear unused mask registers of the pctype */
8545         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8546                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8547                                      0);
8548         I40E_WRITE_FLUSH(hw);
8549
8550         pf->hash_input_set[pctype] = input_set;
8551         return 0;
8552 }
8553
8554 int
8555 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8556                          struct rte_eth_input_set_conf *conf)
8557 {
8558         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8559         enum i40e_filter_pctype pctype;
8560         uint64_t input_set, inset_reg = 0;
8561         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8562         int ret, i, num;
8563
8564         if (!hw || !conf) {
8565                 PMD_DRV_LOG(ERR, "Invalid pointer");
8566                 return -EFAULT;
8567         }
8568         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8569             conf->op != RTE_ETH_INPUT_SET_ADD) {
8570                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8571                 return -EINVAL;
8572         }
8573
8574         if (!I40E_VALID_FLOW(conf->flow_type)) {
8575                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8576                 return -EINVAL;
8577         }
8578
8579         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8580
8581         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8582                                    conf->inset_size);
8583         if (ret) {
8584                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8585                 return -EINVAL;
8586         }
8587         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8588                                     input_set) != 0) {
8589                 PMD_DRV_LOG(ERR, "Invalid input set");
8590                 return -EINVAL;
8591         }
8592
8593         /* get inset value in register */
8594         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8595         inset_reg <<= I40E_32_BIT_WIDTH;
8596         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8597
8598         /* Can not change the inset reg for flex payload for fdir,
8599          * it is done by writing I40E_PRTQF_FD_FLXINSET
8600          * in i40e_set_flex_mask_on_pctype.
8601          */
8602         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8603                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8604         else
8605                 input_set |= pf->fdir.input_set[pctype];
8606         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8607                                            I40E_INSET_MASK_NUM_REG);
8608         if (num < 0)
8609                 return -EINVAL;
8610
8611         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8612
8613         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8614                               (uint32_t)(inset_reg & UINT32_MAX));
8615         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8616                              (uint32_t)((inset_reg >>
8617                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8618
8619         for (i = 0; i < num; i++)
8620                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8621                                      mask_reg[i]);
8622         /*clear unused mask registers of the pctype */
8623         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8624                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8625                                      0);
8626         I40E_WRITE_FLUSH(hw);
8627
8628         pf->fdir.input_set[pctype] = input_set;
8629         return 0;
8630 }
8631
8632 static int
8633 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8634 {
8635         int ret = 0;
8636
8637         if (!hw || !info) {
8638                 PMD_DRV_LOG(ERR, "Invalid pointer");
8639                 return -EFAULT;
8640         }
8641
8642         switch (info->info_type) {
8643         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8644                 i40e_get_symmetric_hash_enable_per_port(hw,
8645                                         &(info->info.enable));
8646                 break;
8647         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8648                 ret = i40e_get_hash_filter_global_config(hw,
8649                                 &(info->info.global_conf));
8650                 break;
8651         default:
8652                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8653                                                         info->info_type);
8654                 ret = -EINVAL;
8655                 break;
8656         }
8657
8658         return ret;
8659 }
8660
8661 static int
8662 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8663 {
8664         int ret = 0;
8665
8666         if (!hw || !info) {
8667                 PMD_DRV_LOG(ERR, "Invalid pointer");
8668                 return -EFAULT;
8669         }
8670
8671         switch (info->info_type) {
8672         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8673                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8674                 break;
8675         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8676                 ret = i40e_set_hash_filter_global_config(hw,
8677                                 &(info->info.global_conf));
8678                 break;
8679         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8680                 ret = i40e_hash_filter_inset_select(hw,
8681                                                &(info->info.input_set_conf));
8682                 break;
8683
8684         default:
8685                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8686                                                         info->info_type);
8687                 ret = -EINVAL;
8688                 break;
8689         }
8690
8691         return ret;
8692 }
8693
8694 /* Operations for hash function */
8695 static int
8696 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8697                       enum rte_filter_op filter_op,
8698                       void *arg)
8699 {
8700         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8701         int ret = 0;
8702
8703         switch (filter_op) {
8704         case RTE_ETH_FILTER_NOP:
8705                 break;
8706         case RTE_ETH_FILTER_GET:
8707                 ret = i40e_hash_filter_get(hw,
8708                         (struct rte_eth_hash_filter_info *)arg);
8709                 break;
8710         case RTE_ETH_FILTER_SET:
8711                 ret = i40e_hash_filter_set(hw,
8712                         (struct rte_eth_hash_filter_info *)arg);
8713                 break;
8714         default:
8715                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8716                                                                 filter_op);
8717                 ret = -ENOTSUP;
8718                 break;
8719         }
8720
8721         return ret;
8722 }
8723
8724 /* Convert ethertype filter structure */
8725 static int
8726 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8727                               struct i40e_ethertype_filter *filter)
8728 {
8729         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8730         filter->input.ether_type = input->ether_type;
8731         filter->flags = input->flags;
8732         filter->queue = input->queue;
8733
8734         return 0;
8735 }
8736
8737 /* Check if there exists the ehtertype filter */
8738 struct i40e_ethertype_filter *
8739 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8740                                 const struct i40e_ethertype_filter_input *input)
8741 {
8742         int ret;
8743
8744         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8745         if (ret < 0)
8746                 return NULL;
8747
8748         return ethertype_rule->hash_map[ret];
8749 }
8750
8751 /* Add ethertype filter in SW list */
8752 static int
8753 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8754                                 struct i40e_ethertype_filter *filter)
8755 {
8756         struct i40e_ethertype_rule *rule = &pf->ethertype;
8757         int ret;
8758
8759         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8760         if (ret < 0) {
8761                 PMD_DRV_LOG(ERR,
8762                             "Failed to insert ethertype filter"
8763                             " to hash table %d!",
8764                             ret);
8765                 return ret;
8766         }
8767         rule->hash_map[ret] = filter;
8768
8769         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8770
8771         return 0;
8772 }
8773
8774 /* Delete ethertype filter in SW list */
8775 int
8776 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8777                              struct i40e_ethertype_filter_input *input)
8778 {
8779         struct i40e_ethertype_rule *rule = &pf->ethertype;
8780         struct i40e_ethertype_filter *filter;
8781         int ret;
8782
8783         ret = rte_hash_del_key(rule->hash_table, input);
8784         if (ret < 0) {
8785                 PMD_DRV_LOG(ERR,
8786                             "Failed to delete ethertype filter"
8787                             " to hash table %d!",
8788                             ret);
8789                 return ret;
8790         }
8791         filter = rule->hash_map[ret];
8792         rule->hash_map[ret] = NULL;
8793
8794         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8795         rte_free(filter);
8796
8797         return 0;
8798 }
8799
8800 /*
8801  * Configure ethertype filter, which can director packet by filtering
8802  * with mac address and ether_type or only ether_type
8803  */
8804 int
8805 i40e_ethertype_filter_set(struct i40e_pf *pf,
8806                         struct rte_eth_ethertype_filter *filter,
8807                         bool add)
8808 {
8809         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8810         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8811         struct i40e_ethertype_filter *ethertype_filter, *node;
8812         struct i40e_ethertype_filter check_filter;
8813         struct i40e_control_filter_stats stats;
8814         uint16_t flags = 0;
8815         int ret;
8816
8817         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8818                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8819                 return -EINVAL;
8820         }
8821         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8822                 filter->ether_type == ETHER_TYPE_IPv6) {
8823                 PMD_DRV_LOG(ERR,
8824                         "unsupported ether_type(0x%04x) in control packet filter.",
8825                         filter->ether_type);
8826                 return -EINVAL;
8827         }
8828         if (filter->ether_type == ETHER_TYPE_VLAN)
8829                 PMD_DRV_LOG(WARNING,
8830                         "filter vlan ether_type in first tag is not supported.");
8831
8832         /* Check if there is the filter in SW list */
8833         memset(&check_filter, 0, sizeof(check_filter));
8834         i40e_ethertype_filter_convert(filter, &check_filter);
8835         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8836                                                &check_filter.input);
8837         if (add && node) {
8838                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8839                 return -EINVAL;
8840         }
8841
8842         if (!add && !node) {
8843                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8844                 return -EINVAL;
8845         }
8846
8847         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8848                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8849         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8850                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8851         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8852
8853         memset(&stats, 0, sizeof(stats));
8854         ret = i40e_aq_add_rem_control_packet_filter(hw,
8855                         filter->mac_addr.addr_bytes,
8856                         filter->ether_type, flags,
8857                         pf->main_vsi->seid,
8858                         filter->queue, add, &stats, NULL);
8859
8860         PMD_DRV_LOG(INFO,
8861                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8862                 ret, stats.mac_etype_used, stats.etype_used,
8863                 stats.mac_etype_free, stats.etype_free);
8864         if (ret < 0)
8865                 return -ENOSYS;
8866
8867         /* Add or delete a filter in SW list */
8868         if (add) {
8869                 ethertype_filter = rte_zmalloc("ethertype_filter",
8870                                        sizeof(*ethertype_filter), 0);
8871                 rte_memcpy(ethertype_filter, &check_filter,
8872                            sizeof(check_filter));
8873                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8874         } else {
8875                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8876         }
8877
8878         return ret;
8879 }
8880
8881 /*
8882  * Handle operations for ethertype filter.
8883  */
8884 static int
8885 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8886                                 enum rte_filter_op filter_op,
8887                                 void *arg)
8888 {
8889         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8890         int ret = 0;
8891
8892         if (filter_op == RTE_ETH_FILTER_NOP)
8893                 return ret;
8894
8895         if (arg == NULL) {
8896                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8897                             filter_op);
8898                 return -EINVAL;
8899         }
8900
8901         switch (filter_op) {
8902         case RTE_ETH_FILTER_ADD:
8903                 ret = i40e_ethertype_filter_set(pf,
8904                         (struct rte_eth_ethertype_filter *)arg,
8905                         TRUE);
8906                 break;
8907         case RTE_ETH_FILTER_DELETE:
8908                 ret = i40e_ethertype_filter_set(pf,
8909                         (struct rte_eth_ethertype_filter *)arg,
8910                         FALSE);
8911                 break;
8912         default:
8913                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8914                 ret = -ENOSYS;
8915                 break;
8916         }
8917         return ret;
8918 }
8919
8920 static int
8921 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8922                      enum rte_filter_type filter_type,
8923                      enum rte_filter_op filter_op,
8924                      void *arg)
8925 {
8926         int ret = 0;
8927
8928         if (dev == NULL)
8929                 return -EINVAL;
8930
8931         switch (filter_type) {
8932         case RTE_ETH_FILTER_NONE:
8933                 /* For global configuration */
8934                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8935                 break;
8936         case RTE_ETH_FILTER_HASH:
8937                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8938                 break;
8939         case RTE_ETH_FILTER_MACVLAN:
8940                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8941                 break;
8942         case RTE_ETH_FILTER_ETHERTYPE:
8943                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8944                 break;
8945         case RTE_ETH_FILTER_TUNNEL:
8946                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8947                 break;
8948         case RTE_ETH_FILTER_FDIR:
8949                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8950                 break;
8951         case RTE_ETH_FILTER_GENERIC:
8952                 if (filter_op != RTE_ETH_FILTER_GET)
8953                         return -EINVAL;
8954                 *(const void **)arg = &i40e_flow_ops;
8955                 break;
8956         default:
8957                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8958                                                         filter_type);
8959                 ret = -EINVAL;
8960                 break;
8961         }
8962
8963         return ret;
8964 }
8965
8966 /*
8967  * Check and enable Extended Tag.
8968  * Enabling Extended Tag is important for 40G performance.
8969  */
8970 static void
8971 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8972 {
8973         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8974         uint32_t buf = 0;
8975         int ret;
8976
8977         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8978                                       PCI_DEV_CAP_REG);
8979         if (ret < 0) {
8980                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8981                             PCI_DEV_CAP_REG);
8982                 return;
8983         }
8984         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8985                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8986                 return;
8987         }
8988
8989         buf = 0;
8990         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8991                                       PCI_DEV_CTRL_REG);
8992         if (ret < 0) {
8993                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8994                             PCI_DEV_CTRL_REG);
8995                 return;
8996         }
8997         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8998                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8999                 return;
9000         }
9001         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9002         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
9003                                        PCI_DEV_CTRL_REG);
9004         if (ret < 0) {
9005                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9006                             PCI_DEV_CTRL_REG);
9007                 return;
9008         }
9009 }
9010
9011 /*
9012  * As some registers wouldn't be reset unless a global hardware reset,
9013  * hardware initialization is needed to put those registers into an
9014  * expected initial state.
9015  */
9016 static void
9017 i40e_hw_init(struct rte_eth_dev *dev)
9018 {
9019         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9020
9021         i40e_enable_extended_tag(dev);
9022
9023         /* clear the PF Queue Filter control register */
9024         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9025
9026         /* Disable symmetric hash per port */
9027         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9028 }
9029
9030 enum i40e_filter_pctype
9031 i40e_flowtype_to_pctype(uint16_t flow_type)
9032 {
9033         static const enum i40e_filter_pctype pctype_table[] = {
9034                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9035                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9036                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9037                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9038                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9039                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9040                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9041                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9042                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9043                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9044                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9045                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9046                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9047                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9048                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9049                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9050                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9051                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9052                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9053         };
9054
9055         return pctype_table[flow_type];
9056 }
9057
9058 uint16_t
9059 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9060 {
9061         static const uint16_t flowtype_table[] = {
9062                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9063                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9064                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9065                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9066                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9067                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9068                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9069                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9070                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9071                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9072                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9073                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9074                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9075                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9076                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9077                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9078                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9079                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9080                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9081                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9082                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9083                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9084                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9085                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9086                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9087                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9088                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9089                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9090                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9091                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9092                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9093         };
9094
9095         return flowtype_table[pctype];
9096 }
9097
9098 /*
9099  * On X710, performance number is far from the expectation on recent firmware
9100  * versions; on XL710, performance number is also far from the expectation on
9101  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9102  * mode is enabled and port MAC address is equal to the packet destination MAC
9103  * address. The fix for this issue may not be integrated in the following
9104  * firmware version. So the workaround in software driver is needed. It needs
9105  * to modify the initial values of 3 internal only registers for both X710 and
9106  * XL710. Note that the values for X710 or XL710 could be different, and the
9107  * workaround can be removed when it is fixed in firmware in the future.
9108  */
9109
9110 /* For both X710 and XL710 */
9111 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
9112 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
9113
9114 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9115 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9116
9117 /* For X722 */
9118 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9119 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9120
9121 /* For X710 */
9122 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9123 /* For XL710 */
9124 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9125 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9126
9127 static int
9128 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9129 {
9130         enum i40e_status_code status;
9131         struct i40e_aq_get_phy_abilities_resp phy_ab;
9132         int ret = -ENOTSUP;
9133
9134         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9135                                               NULL);
9136
9137         if (status)
9138                 return ret;
9139
9140         return 0;
9141 }
9142
9143 static void
9144 i40e_configure_registers(struct i40e_hw *hw)
9145 {
9146         static struct {
9147                 uint32_t addr;
9148                 uint64_t val;
9149         } reg_table[] = {
9150                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9151                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9152                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9153         };
9154         uint64_t reg;
9155         uint32_t i;
9156         int ret;
9157
9158         for (i = 0; i < RTE_DIM(reg_table); i++) {
9159                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9160                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9161                                 reg_table[i].val =
9162                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9163                         else /* For X710/XL710/XXV710 */
9164                                 reg_table[i].val =
9165                                         I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9166                 }
9167
9168                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9169                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9170                                 reg_table[i].val =
9171                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9172                         else /* For X710/XL710/XXV710 */
9173                                 reg_table[i].val =
9174                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9175                 }
9176
9177                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9178                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9179                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9180                                 reg_table[i].val =
9181                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9182                         else /* For X710 */
9183                                 reg_table[i].val =
9184                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9185                 }
9186
9187                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9188                                                         &reg, NULL);
9189                 if (ret < 0) {
9190                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9191                                                         reg_table[i].addr);
9192                         break;
9193                 }
9194                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9195                                                 reg_table[i].addr, reg);
9196                 if (reg == reg_table[i].val)
9197                         continue;
9198
9199                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9200                                                 reg_table[i].val, NULL);
9201                 if (ret < 0) {
9202                         PMD_DRV_LOG(ERR,
9203                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9204                                 reg_table[i].val, reg_table[i].addr);
9205                         break;
9206                 }
9207                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9208                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9209         }
9210 }
9211
9212 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9213 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9214 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9215 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9216 static int
9217 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9218 {
9219         uint32_t reg;
9220         int ret;
9221
9222         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9223                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9224                 return -EINVAL;
9225         }
9226
9227         /* Configure for double VLAN RX stripping */
9228         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9229         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9230                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9231                 ret = i40e_aq_debug_write_register(hw,
9232                                                    I40E_VSI_TSR(vsi->vsi_id),
9233                                                    reg, NULL);
9234                 if (ret < 0) {
9235                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9236                                     vsi->vsi_id);
9237                         return I40E_ERR_CONFIG;
9238                 }
9239         }
9240
9241         /* Configure for double VLAN TX insertion */
9242         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9243         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9244                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9245                 ret = i40e_aq_debug_write_register(hw,
9246                                                    I40E_VSI_L2TAGSTXVALID(
9247                                                    vsi->vsi_id), reg, NULL);
9248                 if (ret < 0) {
9249                         PMD_DRV_LOG(ERR,
9250                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9251                                 vsi->vsi_id);
9252                         return I40E_ERR_CONFIG;
9253                 }
9254         }
9255
9256         return 0;
9257 }
9258
9259 /**
9260  * i40e_aq_add_mirror_rule
9261  * @hw: pointer to the hardware structure
9262  * @seid: VEB seid to add mirror rule to
9263  * @dst_id: destination vsi seid
9264  * @entries: Buffer which contains the entities to be mirrored
9265  * @count: number of entities contained in the buffer
9266  * @rule_id:the rule_id of the rule to be added
9267  *
9268  * Add a mirror rule for a given veb.
9269  *
9270  **/
9271 static enum i40e_status_code
9272 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9273                         uint16_t seid, uint16_t dst_id,
9274                         uint16_t rule_type, uint16_t *entries,
9275                         uint16_t count, uint16_t *rule_id)
9276 {
9277         struct i40e_aq_desc desc;
9278         struct i40e_aqc_add_delete_mirror_rule cmd;
9279         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9280                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9281                 &desc.params.raw;
9282         uint16_t buff_len;
9283         enum i40e_status_code status;
9284
9285         i40e_fill_default_direct_cmd_desc(&desc,
9286                                           i40e_aqc_opc_add_mirror_rule);
9287         memset(&cmd, 0, sizeof(cmd));
9288
9289         buff_len = sizeof(uint16_t) * count;
9290         desc.datalen = rte_cpu_to_le_16(buff_len);
9291         if (buff_len > 0)
9292                 desc.flags |= rte_cpu_to_le_16(
9293                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9294         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9295                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9296         cmd.num_entries = rte_cpu_to_le_16(count);
9297         cmd.seid = rte_cpu_to_le_16(seid);
9298         cmd.destination = rte_cpu_to_le_16(dst_id);
9299
9300         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9301         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9302         PMD_DRV_LOG(INFO,
9303                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9304                 hw->aq.asq_last_status, resp->rule_id,
9305                 resp->mirror_rules_used, resp->mirror_rules_free);
9306         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9307
9308         return status;
9309 }
9310
9311 /**
9312  * i40e_aq_del_mirror_rule
9313  * @hw: pointer to the hardware structure
9314  * @seid: VEB seid to add mirror rule to
9315  * @entries: Buffer which contains the entities to be mirrored
9316  * @count: number of entities contained in the buffer
9317  * @rule_id:the rule_id of the rule to be delete
9318  *
9319  * Delete a mirror rule for a given veb.
9320  *
9321  **/
9322 static enum i40e_status_code
9323 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9324                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9325                 uint16_t count, uint16_t rule_id)
9326 {
9327         struct i40e_aq_desc desc;
9328         struct i40e_aqc_add_delete_mirror_rule cmd;
9329         uint16_t buff_len = 0;
9330         enum i40e_status_code status;
9331         void *buff = NULL;
9332
9333         i40e_fill_default_direct_cmd_desc(&desc,
9334                                           i40e_aqc_opc_delete_mirror_rule);
9335         memset(&cmd, 0, sizeof(cmd));
9336         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9337                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9338                                                           I40E_AQ_FLAG_RD));
9339                 cmd.num_entries = count;
9340                 buff_len = sizeof(uint16_t) * count;
9341                 desc.datalen = rte_cpu_to_le_16(buff_len);
9342                 buff = (void *)entries;
9343         } else
9344                 /* rule id is filled in destination field for deleting mirror rule */
9345                 cmd.destination = rte_cpu_to_le_16(rule_id);
9346
9347         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9348                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9349         cmd.seid = rte_cpu_to_le_16(seid);
9350
9351         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9352         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9353
9354         return status;
9355 }
9356
9357 /**
9358  * i40e_mirror_rule_set
9359  * @dev: pointer to the hardware structure
9360  * @mirror_conf: mirror rule info
9361  * @sw_id: mirror rule's sw_id
9362  * @on: enable/disable
9363  *
9364  * set a mirror rule.
9365  *
9366  **/
9367 static int
9368 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9369                         struct rte_eth_mirror_conf *mirror_conf,
9370                         uint8_t sw_id, uint8_t on)
9371 {
9372         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9373         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9374         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9375         struct i40e_mirror_rule *parent = NULL;
9376         uint16_t seid, dst_seid, rule_id;
9377         uint16_t i, j = 0;
9378         int ret;
9379
9380         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9381
9382         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9383                 PMD_DRV_LOG(ERR,
9384                         "mirror rule can not be configured without veb or vfs.");
9385                 return -ENOSYS;
9386         }
9387         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9388                 PMD_DRV_LOG(ERR, "mirror table is full.");
9389                 return -ENOSPC;
9390         }
9391         if (mirror_conf->dst_pool > pf->vf_num) {
9392                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9393                                  mirror_conf->dst_pool);
9394                 return -EINVAL;
9395         }
9396
9397         seid = pf->main_vsi->veb->seid;
9398
9399         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9400                 if (sw_id <= it->index) {
9401                         mirr_rule = it;
9402                         break;
9403                 }
9404                 parent = it;
9405         }
9406         if (mirr_rule && sw_id == mirr_rule->index) {
9407                 if (on) {
9408                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9409                         return -EEXIST;
9410                 } else {
9411                         ret = i40e_aq_del_mirror_rule(hw, seid,
9412                                         mirr_rule->rule_type,
9413                                         mirr_rule->entries,
9414                                         mirr_rule->num_entries, mirr_rule->id);
9415                         if (ret < 0) {
9416                                 PMD_DRV_LOG(ERR,
9417                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9418                                         ret, hw->aq.asq_last_status);
9419                                 return -ENOSYS;
9420                         }
9421                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9422                         rte_free(mirr_rule);
9423                         pf->nb_mirror_rule--;
9424                         return 0;
9425                 }
9426         } else if (!on) {
9427                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9428                 return -ENOENT;
9429         }
9430
9431         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9432                                 sizeof(struct i40e_mirror_rule) , 0);
9433         if (!mirr_rule) {
9434                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9435                 return I40E_ERR_NO_MEMORY;
9436         }
9437         switch (mirror_conf->rule_type) {
9438         case ETH_MIRROR_VLAN:
9439                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9440                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9441                                 mirr_rule->entries[j] =
9442                                         mirror_conf->vlan.vlan_id[i];
9443                                 j++;
9444                         }
9445                 }
9446                 if (j == 0) {
9447                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9448                         rte_free(mirr_rule);
9449                         return -EINVAL;
9450                 }
9451                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9452                 break;
9453         case ETH_MIRROR_VIRTUAL_POOL_UP:
9454         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9455                 /* check if the specified pool bit is out of range */
9456                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9457                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9458                         rte_free(mirr_rule);
9459                         return -EINVAL;
9460                 }
9461                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9462                         if (mirror_conf->pool_mask & (1ULL << i)) {
9463                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9464                                 j++;
9465                         }
9466                 }
9467                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9468                         /* add pf vsi to entries */
9469                         mirr_rule->entries[j] = pf->main_vsi_seid;
9470                         j++;
9471                 }
9472                 if (j == 0) {
9473                         PMD_DRV_LOG(ERR, "pool is not specified.");
9474                         rte_free(mirr_rule);
9475                         return -EINVAL;
9476                 }
9477                 /* egress and ingress in aq commands means from switch but not port */
9478                 mirr_rule->rule_type =
9479                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9480                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9481                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9482                 break;
9483         case ETH_MIRROR_UPLINK_PORT:
9484                 /* egress and ingress in aq commands means from switch but not port*/
9485                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9486                 break;
9487         case ETH_MIRROR_DOWNLINK_PORT:
9488                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9489                 break;
9490         default:
9491                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9492                         mirror_conf->rule_type);
9493                 rte_free(mirr_rule);
9494                 return -EINVAL;
9495         }
9496
9497         /* If the dst_pool is equal to vf_num, consider it as PF */
9498         if (mirror_conf->dst_pool == pf->vf_num)
9499                 dst_seid = pf->main_vsi_seid;
9500         else
9501                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9502
9503         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9504                                       mirr_rule->rule_type, mirr_rule->entries,
9505                                       j, &rule_id);
9506         if (ret < 0) {
9507                 PMD_DRV_LOG(ERR,
9508                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9509                         ret, hw->aq.asq_last_status);
9510                 rte_free(mirr_rule);
9511                 return -ENOSYS;
9512         }
9513
9514         mirr_rule->index = sw_id;
9515         mirr_rule->num_entries = j;
9516         mirr_rule->id = rule_id;
9517         mirr_rule->dst_vsi_seid = dst_seid;
9518
9519         if (parent)
9520                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9521         else
9522                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9523
9524         pf->nb_mirror_rule++;
9525         return 0;
9526 }
9527
9528 /**
9529  * i40e_mirror_rule_reset
9530  * @dev: pointer to the device
9531  * @sw_id: mirror rule's sw_id
9532  *
9533  * reset a mirror rule.
9534  *
9535  **/
9536 static int
9537 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9538 {
9539         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9540         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9541         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9542         uint16_t seid;
9543         int ret;
9544
9545         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9546
9547         seid = pf->main_vsi->veb->seid;
9548
9549         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9550                 if (sw_id == it->index) {
9551                         mirr_rule = it;
9552                         break;
9553                 }
9554         }
9555         if (mirr_rule) {
9556                 ret = i40e_aq_del_mirror_rule(hw, seid,
9557                                 mirr_rule->rule_type,
9558                                 mirr_rule->entries,
9559                                 mirr_rule->num_entries, mirr_rule->id);
9560                 if (ret < 0) {
9561                         PMD_DRV_LOG(ERR,
9562                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9563                                 ret, hw->aq.asq_last_status);
9564                         return -ENOSYS;
9565                 }
9566                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9567                 rte_free(mirr_rule);
9568                 pf->nb_mirror_rule--;
9569         } else {
9570                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9571                 return -ENOENT;
9572         }
9573         return 0;
9574 }
9575
9576 static uint64_t
9577 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9578 {
9579         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9580         uint64_t systim_cycles;
9581
9582         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9583         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9584                         << 32;
9585
9586         return systim_cycles;
9587 }
9588
9589 static uint64_t
9590 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9591 {
9592         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9593         uint64_t rx_tstamp;
9594
9595         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9596         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9597                         << 32;
9598
9599         return rx_tstamp;
9600 }
9601
9602 static uint64_t
9603 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9604 {
9605         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9606         uint64_t tx_tstamp;
9607
9608         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9609         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9610                         << 32;
9611
9612         return tx_tstamp;
9613 }
9614
9615 static void
9616 i40e_start_timecounters(struct rte_eth_dev *dev)
9617 {
9618         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9619         struct i40e_adapter *adapter =
9620                         (struct i40e_adapter *)dev->data->dev_private;
9621         struct rte_eth_link link;
9622         uint32_t tsync_inc_l;
9623         uint32_t tsync_inc_h;
9624
9625         /* Get current link speed. */
9626         memset(&link, 0, sizeof(link));
9627         i40e_dev_link_update(dev, 1);
9628         rte_i40e_dev_atomic_read_link_status(dev, &link);
9629
9630         switch (link.link_speed) {
9631         case ETH_SPEED_NUM_40G:
9632                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9633                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9634                 break;
9635         case ETH_SPEED_NUM_10G:
9636                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9637                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9638                 break;
9639         case ETH_SPEED_NUM_1G:
9640                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9641                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9642                 break;
9643         default:
9644                 tsync_inc_l = 0x0;
9645                 tsync_inc_h = 0x0;
9646         }
9647
9648         /* Set the timesync increment value. */
9649         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9650         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9651
9652         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9653         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9654         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9655
9656         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9657         adapter->systime_tc.cc_shift = 0;
9658         adapter->systime_tc.nsec_mask = 0;
9659
9660         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9661         adapter->rx_tstamp_tc.cc_shift = 0;
9662         adapter->rx_tstamp_tc.nsec_mask = 0;
9663
9664         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9665         adapter->tx_tstamp_tc.cc_shift = 0;
9666         adapter->tx_tstamp_tc.nsec_mask = 0;
9667 }
9668
9669 static int
9670 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9671 {
9672         struct i40e_adapter *adapter =
9673                         (struct i40e_adapter *)dev->data->dev_private;
9674
9675         adapter->systime_tc.nsec += delta;
9676         adapter->rx_tstamp_tc.nsec += delta;
9677         adapter->tx_tstamp_tc.nsec += delta;
9678
9679         return 0;
9680 }
9681
9682 static int
9683 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9684 {
9685         uint64_t ns;
9686         struct i40e_adapter *adapter =
9687                         (struct i40e_adapter *)dev->data->dev_private;
9688
9689         ns = rte_timespec_to_ns(ts);
9690
9691         /* Set the timecounters to a new value. */
9692         adapter->systime_tc.nsec = ns;
9693         adapter->rx_tstamp_tc.nsec = ns;
9694         adapter->tx_tstamp_tc.nsec = ns;
9695
9696         return 0;
9697 }
9698
9699 static int
9700 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9701 {
9702         uint64_t ns, systime_cycles;
9703         struct i40e_adapter *adapter =
9704                         (struct i40e_adapter *)dev->data->dev_private;
9705
9706         systime_cycles = i40e_read_systime_cyclecounter(dev);
9707         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9708         *ts = rte_ns_to_timespec(ns);
9709
9710         return 0;
9711 }
9712
9713 static int
9714 i40e_timesync_enable(struct rte_eth_dev *dev)
9715 {
9716         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9717         uint32_t tsync_ctl_l;
9718         uint32_t tsync_ctl_h;
9719
9720         /* Stop the timesync system time. */
9721         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9722         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9723         /* Reset the timesync system time value. */
9724         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9725         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9726
9727         i40e_start_timecounters(dev);
9728
9729         /* Clear timesync registers. */
9730         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9731         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9732         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9733         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9734         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9735         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9736
9737         /* Enable timestamping of PTP packets. */
9738         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9739         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9740
9741         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9742         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9743         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9744
9745         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9746         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9747
9748         return 0;
9749 }
9750
9751 static int
9752 i40e_timesync_disable(struct rte_eth_dev *dev)
9753 {
9754         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9755         uint32_t tsync_ctl_l;
9756         uint32_t tsync_ctl_h;
9757
9758         /* Disable timestamping of transmitted PTP packets. */
9759         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9760         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9761
9762         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9763         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9764
9765         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9766         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9767
9768         /* Reset the timesync increment value. */
9769         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9770         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9771
9772         return 0;
9773 }
9774
9775 static int
9776 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9777                                 struct timespec *timestamp, uint32_t flags)
9778 {
9779         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9780         struct i40e_adapter *adapter =
9781                 (struct i40e_adapter *)dev->data->dev_private;
9782
9783         uint32_t sync_status;
9784         uint32_t index = flags & 0x03;
9785         uint64_t rx_tstamp_cycles;
9786         uint64_t ns;
9787
9788         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9789         if ((sync_status & (1 << index)) == 0)
9790                 return -EINVAL;
9791
9792         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9793         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9794         *timestamp = rte_ns_to_timespec(ns);
9795
9796         return 0;
9797 }
9798
9799 static int
9800 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9801                                 struct timespec *timestamp)
9802 {
9803         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9804         struct i40e_adapter *adapter =
9805                 (struct i40e_adapter *)dev->data->dev_private;
9806
9807         uint32_t sync_status;
9808         uint64_t tx_tstamp_cycles;
9809         uint64_t ns;
9810
9811         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9812         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9813                 return -EINVAL;
9814
9815         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9816         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9817         *timestamp = rte_ns_to_timespec(ns);
9818
9819         return 0;
9820 }
9821
9822 /*
9823  * i40e_parse_dcb_configure - parse dcb configure from user
9824  * @dev: the device being configured
9825  * @dcb_cfg: pointer of the result of parse
9826  * @*tc_map: bit map of enabled traffic classes
9827  *
9828  * Returns 0 on success, negative value on failure
9829  */
9830 static int
9831 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9832                          struct i40e_dcbx_config *dcb_cfg,
9833                          uint8_t *tc_map)
9834 {
9835         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9836         uint8_t i, tc_bw, bw_lf;
9837
9838         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9839
9840         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9841         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9842                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9843                 return -EINVAL;
9844         }
9845
9846         /* assume each tc has the same bw */
9847         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9848         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9849                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9850         /* to ensure the sum of tcbw is equal to 100 */
9851         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9852         for (i = 0; i < bw_lf; i++)
9853                 dcb_cfg->etscfg.tcbwtable[i]++;
9854
9855         /* assume each tc has the same Transmission Selection Algorithm */
9856         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9857                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9858
9859         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9860                 dcb_cfg->etscfg.prioritytable[i] =
9861                                 dcb_rx_conf->dcb_tc[i];
9862
9863         /* FW needs one App to configure HW */
9864         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9865         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9866         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9867         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9868
9869         if (dcb_rx_conf->nb_tcs == 0)
9870                 *tc_map = 1; /* tc0 only */
9871         else
9872                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9873
9874         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9875                 dcb_cfg->pfc.willing = 0;
9876                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9877                 dcb_cfg->pfc.pfcenable = *tc_map;
9878         }
9879         return 0;
9880 }
9881
9882
9883 static enum i40e_status_code
9884 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9885                               struct i40e_aqc_vsi_properties_data *info,
9886                               uint8_t enabled_tcmap)
9887 {
9888         enum i40e_status_code ret;
9889         int i, total_tc = 0;
9890         uint16_t qpnum_per_tc, bsf, qp_idx;
9891         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9892         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9893         uint16_t used_queues;
9894
9895         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9896         if (ret != I40E_SUCCESS)
9897                 return ret;
9898
9899         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9900                 if (enabled_tcmap & (1 << i))
9901                         total_tc++;
9902         }
9903         if (total_tc == 0)
9904                 total_tc = 1;
9905         vsi->enabled_tc = enabled_tcmap;
9906
9907         /* different VSI has different queues assigned */
9908         if (vsi->type == I40E_VSI_MAIN)
9909                 used_queues = dev_data->nb_rx_queues -
9910                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9911         else if (vsi->type == I40E_VSI_VMDQ2)
9912                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9913         else {
9914                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9915                 return I40E_ERR_NO_AVAILABLE_VSI;
9916         }
9917
9918         qpnum_per_tc = used_queues / total_tc;
9919         /* Number of queues per enabled TC */
9920         if (qpnum_per_tc == 0) {
9921                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9922                 return I40E_ERR_INVALID_QP_ID;
9923         }
9924         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9925                                 I40E_MAX_Q_PER_TC);
9926         bsf = rte_bsf32(qpnum_per_tc);
9927
9928         /**
9929          * Configure TC and queue mapping parameters, for enabled TC,
9930          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9931          * default queue will serve it.
9932          */
9933         qp_idx = 0;
9934         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9935                 if (vsi->enabled_tc & (1 << i)) {
9936                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9937                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9938                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9939                         qp_idx += qpnum_per_tc;
9940                 } else
9941                         info->tc_mapping[i] = 0;
9942         }
9943
9944         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9945         if (vsi->type == I40E_VSI_SRIOV) {
9946                 info->mapping_flags |=
9947                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9948                 for (i = 0; i < vsi->nb_qps; i++)
9949                         info->queue_mapping[i] =
9950                                 rte_cpu_to_le_16(vsi->base_queue + i);
9951         } else {
9952                 info->mapping_flags |=
9953                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9954                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9955         }
9956         info->valid_sections |=
9957                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9958
9959         return I40E_SUCCESS;
9960 }
9961
9962 /*
9963  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9964  * @veb: VEB to be configured
9965  * @tc_map: enabled TC bitmap
9966  *
9967  * Returns 0 on success, negative value on failure
9968  */
9969 static enum i40e_status_code
9970 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9971 {
9972         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9973         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9974         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9975         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9976         enum i40e_status_code ret = I40E_SUCCESS;
9977         int i;
9978         uint32_t bw_max;
9979
9980         /* Check if enabled_tc is same as existing or new TCs */
9981         if (veb->enabled_tc == tc_map)
9982                 return ret;
9983
9984         /* configure tc bandwidth */
9985         memset(&veb_bw, 0, sizeof(veb_bw));
9986         veb_bw.tc_valid_bits = tc_map;
9987         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9988         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9989                 if (tc_map & BIT_ULL(i))
9990                         veb_bw.tc_bw_share_credits[i] = 1;
9991         }
9992         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9993                                                    &veb_bw, NULL);
9994         if (ret) {
9995                 PMD_INIT_LOG(ERR,
9996                         "AQ command Config switch_comp BW allocation per TC failed = %d",
9997                         hw->aq.asq_last_status);
9998                 return ret;
9999         }
10000
10001         memset(&ets_query, 0, sizeof(ets_query));
10002         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10003                                                    &ets_query, NULL);
10004         if (ret != I40E_SUCCESS) {
10005                 PMD_DRV_LOG(ERR,
10006                         "Failed to get switch_comp ETS configuration %u",
10007                         hw->aq.asq_last_status);
10008                 return ret;
10009         }
10010         memset(&bw_query, 0, sizeof(bw_query));
10011         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10012                                                   &bw_query, NULL);
10013         if (ret != I40E_SUCCESS) {
10014                 PMD_DRV_LOG(ERR,
10015                         "Failed to get switch_comp bandwidth configuration %u",
10016                         hw->aq.asq_last_status);
10017                 return ret;
10018         }
10019
10020         /* store and print out BW info */
10021         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10022         veb->bw_info.bw_max = ets_query.tc_bw_max;
10023         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10024         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10025         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10026                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10027                      I40E_16_BIT_WIDTH);
10028         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10029                 veb->bw_info.bw_ets_share_credits[i] =
10030                                 bw_query.tc_bw_share_credits[i];
10031                 veb->bw_info.bw_ets_credits[i] =
10032                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10033                 /* 4 bits per TC, 4th bit is reserved */
10034                 veb->bw_info.bw_ets_max[i] =
10035                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10036                                   RTE_LEN2MASK(3, uint8_t));
10037                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10038                             veb->bw_info.bw_ets_share_credits[i]);
10039                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10040                             veb->bw_info.bw_ets_credits[i]);
10041                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10042                             veb->bw_info.bw_ets_max[i]);
10043         }
10044
10045         veb->enabled_tc = tc_map;
10046
10047         return ret;
10048 }
10049
10050
10051 /*
10052  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10053  * @vsi: VSI to be configured
10054  * @tc_map: enabled TC bitmap
10055  *
10056  * Returns 0 on success, negative value on failure
10057  */
10058 static enum i40e_status_code
10059 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10060 {
10061         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10062         struct i40e_vsi_context ctxt;
10063         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10064         enum i40e_status_code ret = I40E_SUCCESS;
10065         int i;
10066
10067         /* Check if enabled_tc is same as existing or new TCs */
10068         if (vsi->enabled_tc == tc_map)
10069                 return ret;
10070
10071         /* configure tc bandwidth */
10072         memset(&bw_data, 0, sizeof(bw_data));
10073         bw_data.tc_valid_bits = tc_map;
10074         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10075         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10076                 if (tc_map & BIT_ULL(i))
10077                         bw_data.tc_bw_credits[i] = 1;
10078         }
10079         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10080         if (ret) {
10081                 PMD_INIT_LOG(ERR,
10082                         "AQ command Config VSI BW allocation per TC failed = %d",
10083                         hw->aq.asq_last_status);
10084                 goto out;
10085         }
10086         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10087                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10088
10089         /* Update Queue Pairs Mapping for currently enabled UPs */
10090         ctxt.seid = vsi->seid;
10091         ctxt.pf_num = hw->pf_id;
10092         ctxt.vf_num = 0;
10093         ctxt.uplink_seid = vsi->uplink_seid;
10094         ctxt.info = vsi->info;
10095         i40e_get_cap(hw);
10096         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10097         if (ret)
10098                 goto out;
10099
10100         /* Update the VSI after updating the VSI queue-mapping information */
10101         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10102         if (ret) {
10103                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10104                         hw->aq.asq_last_status);
10105                 goto out;
10106         }
10107         /* update the local VSI info with updated queue map */
10108         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10109                                         sizeof(vsi->info.tc_mapping));
10110         (void)rte_memcpy(&vsi->info.queue_mapping,
10111                         &ctxt.info.queue_mapping,
10112                 sizeof(vsi->info.queue_mapping));
10113         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10114         vsi->info.valid_sections = 0;
10115
10116         /* query and update current VSI BW information */
10117         ret = i40e_vsi_get_bw_config(vsi);
10118         if (ret) {
10119                 PMD_INIT_LOG(ERR,
10120                          "Failed updating vsi bw info, err %s aq_err %s",
10121                          i40e_stat_str(hw, ret),
10122                          i40e_aq_str(hw, hw->aq.asq_last_status));
10123                 goto out;
10124         }
10125
10126         vsi->enabled_tc = tc_map;
10127
10128 out:
10129         return ret;
10130 }
10131
10132 /*
10133  * i40e_dcb_hw_configure - program the dcb setting to hw
10134  * @pf: pf the configuration is taken on
10135  * @new_cfg: new configuration
10136  * @tc_map: enabled TC bitmap
10137  *
10138  * Returns 0 on success, negative value on failure
10139  */
10140 static enum i40e_status_code
10141 i40e_dcb_hw_configure(struct i40e_pf *pf,
10142                       struct i40e_dcbx_config *new_cfg,
10143                       uint8_t tc_map)
10144 {
10145         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10146         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10147         struct i40e_vsi *main_vsi = pf->main_vsi;
10148         struct i40e_vsi_list *vsi_list;
10149         enum i40e_status_code ret;
10150         int i;
10151         uint32_t val;
10152
10153         /* Use the FW API if FW > v4.4*/
10154         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10155               (hw->aq.fw_maj_ver >= 5))) {
10156                 PMD_INIT_LOG(ERR,
10157                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10158                 return I40E_ERR_FIRMWARE_API_VERSION;
10159         }
10160
10161         /* Check if need reconfiguration */
10162         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10163                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10164                 return I40E_SUCCESS;
10165         }
10166
10167         /* Copy the new config to the current config */
10168         *old_cfg = *new_cfg;
10169         old_cfg->etsrec = old_cfg->etscfg;
10170         ret = i40e_set_dcb_config(hw);
10171         if (ret) {
10172                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10173                          i40e_stat_str(hw, ret),
10174                          i40e_aq_str(hw, hw->aq.asq_last_status));
10175                 return ret;
10176         }
10177         /* set receive Arbiter to RR mode and ETS scheme by default */
10178         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10179                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10180                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10181                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10182                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10183                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10184                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10185                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10186                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10187                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10188                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10189                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10190                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10191         }
10192         /* get local mib to check whether it is configured correctly */
10193         /* IEEE mode */
10194         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10195         /* Get Local DCB Config */
10196         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10197                                      &hw->local_dcbx_config);
10198
10199         /* if Veb is created, need to update TC of it at first */
10200         if (main_vsi->veb) {
10201                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10202                 if (ret)
10203                         PMD_INIT_LOG(WARNING,
10204                                  "Failed configuring TC for VEB seid=%d",
10205                                  main_vsi->veb->seid);
10206         }
10207         /* Update each VSI */
10208         i40e_vsi_config_tc(main_vsi, tc_map);
10209         if (main_vsi->veb) {
10210                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10211                         /* Beside main VSI and VMDQ VSIs, only enable default
10212                          * TC for other VSIs
10213                          */
10214                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10215                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10216                                                          tc_map);
10217                         else
10218                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10219                                                          I40E_DEFAULT_TCMAP);
10220                         if (ret)
10221                                 PMD_INIT_LOG(WARNING,
10222                                         "Failed configuring TC for VSI seid=%d",
10223                                         vsi_list->vsi->seid);
10224                         /* continue */
10225                 }
10226         }
10227         return I40E_SUCCESS;
10228 }
10229
10230 /*
10231  * i40e_dcb_init_configure - initial dcb config
10232  * @dev: device being configured
10233  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10234  *
10235  * Returns 0 on success, negative value on failure
10236  */
10237 static int
10238 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10239 {
10240         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10241         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10242         int i, ret = 0;
10243
10244         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10245                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10246                 return -ENOTSUP;
10247         }
10248
10249         /* DCB initialization:
10250          * Update DCB configuration from the Firmware and configure
10251          * LLDP MIB change event.
10252          */
10253         if (sw_dcb == TRUE) {
10254                 ret = i40e_init_dcb(hw);
10255                 /* If lldp agent is stopped, the return value from
10256                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10257                  * adminq status. Otherwise, it should return success.
10258                  */
10259                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10260                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10261                         memset(&hw->local_dcbx_config, 0,
10262                                 sizeof(struct i40e_dcbx_config));
10263                         /* set dcb default configuration */
10264                         hw->local_dcbx_config.etscfg.willing = 0;
10265                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10266                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10267                         hw->local_dcbx_config.etscfg.tsatable[0] =
10268                                                 I40E_IEEE_TSA_ETS;
10269                         /* all UPs mapping to TC0 */
10270                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10271                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10272                         hw->local_dcbx_config.etsrec =
10273                                 hw->local_dcbx_config.etscfg;
10274                         hw->local_dcbx_config.pfc.willing = 0;
10275                         hw->local_dcbx_config.pfc.pfccap =
10276                                                 I40E_MAX_TRAFFIC_CLASS;
10277                         hw->local_dcbx_config.pfc.pfcenable =
10278                                                 I40E_DEFAULT_TCMAP;
10279                         /* FW needs one App to configure HW */
10280                         hw->local_dcbx_config.numapps = 1;
10281                         hw->local_dcbx_config.app[0].selector =
10282                                                 I40E_APP_SEL_ETHTYPE;
10283                         hw->local_dcbx_config.app[0].priority = 3;
10284                         hw->local_dcbx_config.app[0].protocolid =
10285                                                 I40E_APP_PROTOID_FCOE;
10286                         ret = i40e_set_dcb_config(hw);
10287                         if (ret) {
10288                                 PMD_INIT_LOG(ERR,
10289                                         "default dcb config fails. err = %d, aq_err = %d.",
10290                                         ret, hw->aq.asq_last_status);
10291                                 return -ENOSYS;
10292                         }
10293                 } else {
10294                         PMD_INIT_LOG(ERR,
10295                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10296                                 ret, hw->aq.asq_last_status);
10297                         return -ENOTSUP;
10298                 }
10299         } else {
10300                 ret = i40e_aq_start_lldp(hw, NULL);
10301                 if (ret != I40E_SUCCESS)
10302                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10303
10304                 ret = i40e_init_dcb(hw);
10305                 if (!ret) {
10306                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10307                                 PMD_INIT_LOG(ERR,
10308                                         "HW doesn't support DCBX offload.");
10309                                 return -ENOTSUP;
10310                         }
10311                 } else {
10312                         PMD_INIT_LOG(ERR,
10313                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10314                                 ret, hw->aq.asq_last_status);
10315                         return -ENOTSUP;
10316                 }
10317         }
10318         return 0;
10319 }
10320
10321 /*
10322  * i40e_dcb_setup - setup dcb related config
10323  * @dev: device being configured
10324  *
10325  * Returns 0 on success, negative value on failure
10326  */
10327 static int
10328 i40e_dcb_setup(struct rte_eth_dev *dev)
10329 {
10330         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10331         struct i40e_dcbx_config dcb_cfg;
10332         uint8_t tc_map = 0;
10333         int ret = 0;
10334
10335         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10336                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10337                 return -ENOTSUP;
10338         }
10339
10340         if (pf->vf_num != 0)
10341                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10342
10343         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10344         if (ret) {
10345                 PMD_INIT_LOG(ERR, "invalid dcb config");
10346                 return -EINVAL;
10347         }
10348         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10349         if (ret) {
10350                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10351                 return -ENOSYS;
10352         }
10353
10354         return 0;
10355 }
10356
10357 static int
10358 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10359                       struct rte_eth_dcb_info *dcb_info)
10360 {
10361         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10362         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10363         struct i40e_vsi *vsi = pf->main_vsi;
10364         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10365         uint16_t bsf, tc_mapping;
10366         int i, j = 0;
10367
10368         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10369                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10370         else
10371                 dcb_info->nb_tcs = 1;
10372         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10373                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10374         for (i = 0; i < dcb_info->nb_tcs; i++)
10375                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10376
10377         /* get queue mapping if vmdq is disabled */
10378         if (!pf->nb_cfg_vmdq_vsi) {
10379                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10380                         if (!(vsi->enabled_tc & (1 << i)))
10381                                 continue;
10382                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10383                         dcb_info->tc_queue.tc_rxq[j][i].base =
10384                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10385                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10386                         dcb_info->tc_queue.tc_txq[j][i].base =
10387                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10388                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10389                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10390                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10391                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10392                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10393                 }
10394                 return 0;
10395         }
10396
10397         /* get queue mapping if vmdq is enabled */
10398         do {
10399                 vsi = pf->vmdq[j].vsi;
10400                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10401                         if (!(vsi->enabled_tc & (1 << i)))
10402                                 continue;
10403                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10404                         dcb_info->tc_queue.tc_rxq[j][i].base =
10405                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10406                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10407                         dcb_info->tc_queue.tc_txq[j][i].base =
10408                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10409                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10410                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10411                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10412                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10413                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10414                 }
10415                 j++;
10416         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10417         return 0;
10418 }
10419
10420 static int
10421 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10422 {
10423         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10424         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10425         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10426         uint16_t interval =
10427                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10428         uint16_t msix_intr;
10429
10430         msix_intr = intr_handle->intr_vec[queue_id];
10431         if (msix_intr == I40E_MISC_VEC_ID)
10432                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10433                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10434                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10435                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10436                                (interval <<
10437                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10438         else
10439                 I40E_WRITE_REG(hw,
10440                                I40E_PFINT_DYN_CTLN(msix_intr -
10441                                                    I40E_RX_VEC_START),
10442                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10443                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10444                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10445                                (interval <<
10446                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10447
10448         I40E_WRITE_FLUSH(hw);
10449         rte_intr_enable(&pci_dev->intr_handle);
10450
10451         return 0;
10452 }
10453
10454 static int
10455 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10456 {
10457         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10458         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10459         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10460         uint16_t msix_intr;
10461
10462         msix_intr = intr_handle->intr_vec[queue_id];
10463         if (msix_intr == I40E_MISC_VEC_ID)
10464                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10465         else
10466                 I40E_WRITE_REG(hw,
10467                                I40E_PFINT_DYN_CTLN(msix_intr -
10468                                                    I40E_RX_VEC_START),
10469                                0);
10470         I40E_WRITE_FLUSH(hw);
10471
10472         return 0;
10473 }
10474
10475 static int i40e_get_regs(struct rte_eth_dev *dev,
10476                          struct rte_dev_reg_info *regs)
10477 {
10478         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10479         uint32_t *ptr_data = regs->data;
10480         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10481         const struct i40e_reg_info *reg_info;
10482
10483         if (ptr_data == NULL) {
10484                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10485                 regs->width = sizeof(uint32_t);
10486                 return 0;
10487         }
10488
10489         /* The first few registers have to be read using AQ operations */
10490         reg_idx = 0;
10491         while (i40e_regs_adminq[reg_idx].name) {
10492                 reg_info = &i40e_regs_adminq[reg_idx++];
10493                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10494                         for (arr_idx2 = 0;
10495                                         arr_idx2 <= reg_info->count2;
10496                                         arr_idx2++) {
10497                                 reg_offset = arr_idx * reg_info->stride1 +
10498                                         arr_idx2 * reg_info->stride2;
10499                                 reg_offset += reg_info->base_addr;
10500                                 ptr_data[reg_offset >> 2] =
10501                                         i40e_read_rx_ctl(hw, reg_offset);
10502                         }
10503         }
10504
10505         /* The remaining registers can be read using primitives */
10506         reg_idx = 0;
10507         while (i40e_regs_others[reg_idx].name) {
10508                 reg_info = &i40e_regs_others[reg_idx++];
10509                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10510                         for (arr_idx2 = 0;
10511                                         arr_idx2 <= reg_info->count2;
10512                                         arr_idx2++) {
10513                                 reg_offset = arr_idx * reg_info->stride1 +
10514                                         arr_idx2 * reg_info->stride2;
10515                                 reg_offset += reg_info->base_addr;
10516                                 ptr_data[reg_offset >> 2] =
10517                                         I40E_READ_REG(hw, reg_offset);
10518                         }
10519         }
10520
10521         return 0;
10522 }
10523
10524 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10525 {
10526         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10527
10528         /* Convert word count to byte count */
10529         return hw->nvm.sr_size << 1;
10530 }
10531
10532 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10533                            struct rte_dev_eeprom_info *eeprom)
10534 {
10535         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10536         uint16_t *data = eeprom->data;
10537         uint16_t offset, length, cnt_words;
10538         int ret_code;
10539
10540         offset = eeprom->offset >> 1;
10541         length = eeprom->length >> 1;
10542         cnt_words = length;
10543
10544         if (offset > hw->nvm.sr_size ||
10545                 offset + length > hw->nvm.sr_size) {
10546                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10547                 return -EINVAL;
10548         }
10549
10550         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10551
10552         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10553         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10554                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10555                 return -EIO;
10556         }
10557
10558         return 0;
10559 }
10560
10561 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10562                                       struct ether_addr *mac_addr)
10563 {
10564         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10565
10566         if (!is_valid_assigned_ether_addr(mac_addr)) {
10567                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10568                 return;
10569         }
10570
10571         /* Flags: 0x3 updates port address */
10572         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10573 }
10574
10575 static int
10576 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10577 {
10578         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10579         struct rte_eth_dev_data *dev_data = pf->dev_data;
10580         uint32_t frame_size = mtu + ETHER_HDR_LEN
10581                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10582         int ret = 0;
10583
10584         /* check if mtu is within the allowed range */
10585         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10586                 return -EINVAL;
10587
10588         /* mtu setting is forbidden if port is start */
10589         if (dev_data->dev_started) {
10590                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10591                             dev_data->port_id);
10592                 return -EBUSY;
10593         }
10594
10595         if (frame_size > ETHER_MAX_LEN)
10596                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10597         else
10598                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10599
10600         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10601
10602         return ret;
10603 }
10604
10605 /* Restore ethertype filter */
10606 static void
10607 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10608 {
10609         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10610         struct i40e_ethertype_filter_list
10611                 *ethertype_list = &pf->ethertype.ethertype_list;
10612         struct i40e_ethertype_filter *f;
10613         struct i40e_control_filter_stats stats;
10614         uint16_t flags;
10615
10616         TAILQ_FOREACH(f, ethertype_list, rules) {
10617                 flags = 0;
10618                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10619                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10620                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10621                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10622                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10623
10624                 memset(&stats, 0, sizeof(stats));
10625                 i40e_aq_add_rem_control_packet_filter(hw,
10626                                             f->input.mac_addr.addr_bytes,
10627                                             f->input.ether_type,
10628                                             flags, pf->main_vsi->seid,
10629                                             f->queue, 1, &stats, NULL);
10630         }
10631         PMD_DRV_LOG(INFO, "Ethertype filter:"
10632                     " mac_etype_used = %u, etype_used = %u,"
10633                     " mac_etype_free = %u, etype_free = %u",
10634                     stats.mac_etype_used, stats.etype_used,
10635                     stats.mac_etype_free, stats.etype_free);
10636 }
10637
10638 /* Restore tunnel filter */
10639 static void
10640 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10641 {
10642         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10643         struct i40e_vsi *vsi;
10644         struct i40e_pf_vf *vf;
10645         struct i40e_tunnel_filter_list
10646                 *tunnel_list = &pf->tunnel.tunnel_list;
10647         struct i40e_tunnel_filter *f;
10648         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10649         bool big_buffer = 0;
10650
10651         TAILQ_FOREACH(f, tunnel_list, rules) {
10652                 if (!f->is_to_vf)
10653                         vsi = pf->main_vsi;
10654                 else {
10655                         vf = &pf->vfs[f->vf_id];
10656                         vsi = vf->vsi;
10657                 }
10658                 memset(&cld_filter, 0, sizeof(cld_filter));
10659                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10660                         (struct ether_addr *)&cld_filter.element.outer_mac);
10661                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10662                         (struct ether_addr *)&cld_filter.element.inner_mac);
10663                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10664                 cld_filter.element.flags = f->input.flags;
10665                 cld_filter.element.tenant_id = f->input.tenant_id;
10666                 cld_filter.element.queue_number = f->queue;
10667                 rte_memcpy(cld_filter.general_fields,
10668                            f->input.general_fields,
10669                            sizeof(f->input.general_fields));
10670
10671                 if (((f->input.flags &
10672                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10673                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10674                     ((f->input.flags &
10675                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10676                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10677                     ((f->input.flags &
10678                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10679                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10680                         big_buffer = 1;
10681
10682                 if (big_buffer)
10683                         i40e_aq_add_cloud_filters_big_buffer(hw,
10684                                              vsi->seid, &cld_filter, 1);
10685                 else
10686                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10687                                                   &cld_filter.element, 1);
10688         }
10689 }
10690
10691 static void
10692 i40e_filter_restore(struct i40e_pf *pf)
10693 {
10694         i40e_ethertype_filter_restore(pf);
10695         i40e_tunnel_filter_restore(pf);
10696         i40e_fdir_filter_restore(pf);
10697 }
10698
10699 static bool
10700 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10701 {
10702         if (strcmp(dev->data->drv_name,
10703                    drv->driver.name))
10704                 return false;
10705
10706         return true;
10707 }
10708
10709 int
10710 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10711 {
10712         struct rte_eth_dev *dev;
10713         struct i40e_pf *pf;
10714
10715         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10716
10717         dev = &rte_eth_devices[port];
10718
10719         if (!is_device_supported(dev, &rte_i40e_pmd))
10720                 return -ENOTSUP;
10721
10722         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10723
10724         if (vf >= pf->vf_num || !pf->vfs) {
10725                 PMD_DRV_LOG(ERR, "Invalid argument.");
10726                 return -EINVAL;
10727         }
10728
10729         i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
10730
10731         return 0;
10732 }
10733
10734 int
10735 rte_pmd_i40e_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10736 {
10737         struct rte_eth_dev *dev;
10738         struct i40e_pf *pf;
10739         struct i40e_vsi *vsi;
10740         struct i40e_hw *hw;
10741         struct i40e_vsi_context ctxt;
10742         int ret;
10743
10744         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10745
10746         dev = &rte_eth_devices[port];
10747
10748         if (!is_device_supported(dev, &rte_i40e_pmd))
10749                 return -ENOTSUP;
10750
10751         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10752
10753         if (vf_id >= pf->vf_num || !pf->vfs) {
10754                 PMD_DRV_LOG(ERR, "Invalid argument.");
10755                 return -EINVAL;
10756         }
10757
10758         vsi = pf->vfs[vf_id].vsi;
10759         if (!vsi) {
10760                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10761                 return -EINVAL;
10762         }
10763
10764         /* Check if it has been already on or off */
10765         if (vsi->info.valid_sections &
10766                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
10767                 if (on) {
10768                         if ((vsi->info.sec_flags &
10769                              I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
10770                             I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
10771                                 return 0; /* already on */
10772                 } else {
10773                         if ((vsi->info.sec_flags &
10774                              I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
10775                                 return 0; /* already off */
10776                 }
10777         }
10778
10779         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10780         if (on)
10781                 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10782         else
10783                 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10784
10785         memset(&ctxt, 0, sizeof(ctxt));
10786         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10787         ctxt.seid = vsi->seid;
10788
10789         hw = I40E_VSI_TO_HW(vsi);
10790         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10791         if (ret != I40E_SUCCESS) {
10792                 ret = -ENOTSUP;
10793                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10794         }
10795
10796         return ret;
10797 }
10798
10799 static int
10800 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
10801 {
10802         uint32_t j, k;
10803         uint16_t vlan_id;
10804         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10805         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
10806         int ret;
10807
10808         for (j = 0; j < I40E_VFTA_SIZE; j++) {
10809                 if (!vsi->vfta[j])
10810                         continue;
10811
10812                 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
10813                         if (!(vsi->vfta[j] & (1 << k)))
10814                                 continue;
10815
10816                         vlan_id = j * I40E_UINT32_BIT_SIZE + k;
10817                         if (!vlan_id)
10818                                 continue;
10819
10820                         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
10821                         if (add)
10822                                 ret = i40e_aq_add_vlan(hw, vsi->seid,
10823                                                        &vlan_data, 1, NULL);
10824                         else
10825                                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
10826                                                           &vlan_data, 1, NULL);
10827                         if (ret != I40E_SUCCESS) {
10828                                 PMD_DRV_LOG(ERR,
10829                                             "Failed to add/rm vlan filter");
10830                                 return ret;
10831                         }
10832                 }
10833         }
10834
10835         return I40E_SUCCESS;
10836 }
10837
10838 int
10839 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10840 {
10841         struct rte_eth_dev *dev;
10842         struct i40e_pf *pf;
10843         struct i40e_vsi *vsi;
10844         struct i40e_hw *hw;
10845         struct i40e_vsi_context ctxt;
10846         int ret;
10847
10848         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10849
10850         dev = &rte_eth_devices[port];
10851
10852         if (!is_device_supported(dev, &rte_i40e_pmd))
10853                 return -ENOTSUP;
10854
10855         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10856
10857         if (vf_id >= pf->vf_num || !pf->vfs) {
10858                 PMD_DRV_LOG(ERR, "Invalid argument.");
10859                 return -EINVAL;
10860         }
10861
10862         vsi = pf->vfs[vf_id].vsi;
10863         if (!vsi) {
10864                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10865                 return -EINVAL;
10866         }
10867
10868         /* Check if it has been already on or off */
10869         if (vsi->vlan_anti_spoof_on == on)
10870                 return 0; /* already on or off */
10871
10872         vsi->vlan_anti_spoof_on = on;
10873         if (!vsi->vlan_filter_on) {
10874                 ret = i40e_add_rm_all_vlan_filter(vsi, on);
10875                 if (ret) {
10876                         PMD_DRV_LOG(ERR, "Failed to add/remove VLAN filters.");
10877                         return -ENOTSUP;
10878                 }
10879         }
10880
10881         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10882         if (on)
10883                 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10884         else
10885                 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10886
10887         memset(&ctxt, 0, sizeof(ctxt));
10888         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10889         ctxt.seid = vsi->seid;
10890
10891         hw = I40E_VSI_TO_HW(vsi);
10892         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10893         if (ret != I40E_SUCCESS) {
10894                 ret = -ENOTSUP;
10895                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10896         }
10897
10898         return ret;
10899 }
10900
10901 static int
10902 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
10903 {
10904         struct i40e_mac_filter *f;
10905         struct i40e_macvlan_filter *mv_f;
10906         int i, vlan_num;
10907         enum rte_mac_filter_type filter_type;
10908         int ret = I40E_SUCCESS;
10909         void *temp;
10910
10911         /* remove all the MACs */
10912         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10913                 vlan_num = vsi->vlan_num;
10914                 filter_type = f->mac_info.filter_type;
10915                 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10916                     filter_type == RTE_MACVLAN_HASH_MATCH) {
10917                         if (vlan_num == 0) {
10918                                 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
10919                                 return I40E_ERR_PARAM;
10920                         }
10921                 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
10922                            filter_type == RTE_MAC_HASH_MATCH)
10923                         vlan_num = 1;
10924
10925                 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10926                 if (!mv_f) {
10927                         PMD_DRV_LOG(ERR, "failed to allocate memory");
10928                         return I40E_ERR_NO_MEMORY;
10929                 }
10930
10931                 for (i = 0; i < vlan_num; i++) {
10932                         mv_f[i].filter_type = filter_type;
10933                         (void)rte_memcpy(&mv_f[i].macaddr,
10934                                          &f->mac_info.mac_addr,
10935                                          ETH_ADDR_LEN);
10936                 }
10937                 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10938                     filter_type == RTE_MACVLAN_HASH_MATCH) {
10939                         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10940                                                          &f->mac_info.mac_addr);
10941                         if (ret != I40E_SUCCESS) {
10942                                 rte_free(mv_f);
10943                                 return ret;
10944                         }
10945                 }
10946
10947                 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
10948                 if (ret != I40E_SUCCESS) {
10949                         rte_free(mv_f);
10950                         return ret;
10951                 }
10952
10953                 rte_free(mv_f);
10954                 ret = I40E_SUCCESS;
10955         }
10956
10957         return ret;
10958 }
10959
10960 static int
10961 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
10962 {
10963         struct i40e_mac_filter *f;
10964         struct i40e_macvlan_filter *mv_f;
10965         int i, vlan_num = 0;
10966         int ret = I40E_SUCCESS;
10967         void *temp;
10968
10969         /* restore all the MACs */
10970         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10971                 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
10972                     (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
10973                         /**
10974                          * If vlan_num is 0, that's the first time to add mac,
10975                          * set mask for vlan_id 0.
10976                          */
10977                         if (vsi->vlan_num == 0) {
10978                                 i40e_set_vlan_filter(vsi, 0, 1);
10979                                 vsi->vlan_num = 1;
10980                         }
10981                         vlan_num = vsi->vlan_num;
10982                 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
10983                            (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
10984                         vlan_num = 1;
10985
10986                 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10987                 if (!mv_f) {
10988                         PMD_DRV_LOG(ERR, "failed to allocate memory");
10989                         return I40E_ERR_NO_MEMORY;
10990                 }
10991
10992                 for (i = 0; i < vlan_num; i++) {
10993                         mv_f[i].filter_type = f->mac_info.filter_type;
10994                         (void)rte_memcpy(&mv_f[i].macaddr,
10995                                          &f->mac_info.mac_addr,
10996                                          ETH_ADDR_LEN);
10997                 }
10998
10999                 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
11000                     f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
11001                         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
11002                                                          &f->mac_info.mac_addr);
11003                         if (ret != I40E_SUCCESS) {
11004                                 rte_free(mv_f);
11005                                 return ret;
11006                         }
11007                 }
11008
11009                 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
11010                 if (ret != I40E_SUCCESS) {
11011                         rte_free(mv_f);
11012                         return ret;
11013                 }
11014
11015                 rte_free(mv_f);
11016                 ret = I40E_SUCCESS;
11017         }
11018
11019         return ret;
11020 }
11021
11022 static int
11023 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
11024 {
11025         struct i40e_vsi_context ctxt;
11026         struct i40e_hw *hw;
11027         int ret;
11028
11029         if (!vsi)
11030                 return -EINVAL;
11031
11032         hw = I40E_VSI_TO_HW(vsi);
11033
11034         /* Use the FW API if FW >= v5.0 */
11035         if (hw->aq.fw_maj_ver < 5) {
11036                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
11037                 return -ENOTSUP;
11038         }
11039
11040         /* Check if it has been already on or off */
11041         if (vsi->info.valid_sections &
11042                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
11043                 if (on) {
11044                         if ((vsi->info.switch_id &
11045                              I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
11046                             I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
11047                                 return 0; /* already on */
11048                 } else {
11049                         if ((vsi->info.switch_id &
11050                              I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
11051                                 return 0; /* already off */
11052                 }
11053         }
11054
11055         /* remove all the MAC and VLAN first */
11056         ret = i40e_vsi_rm_mac_filter(vsi);
11057         if (ret) {
11058                 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
11059                 return ret;
11060         }
11061         if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
11062                 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
11063                 if (ret) {
11064                         PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
11065                         return ret;
11066                 }
11067         }
11068
11069         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
11070         if (on)
11071                 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
11072         else
11073                 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
11074
11075         memset(&ctxt, 0, sizeof(ctxt));
11076         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11077         ctxt.seid = vsi->seid;
11078
11079         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11080         if (ret != I40E_SUCCESS) {
11081                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11082                 return ret;
11083         }
11084
11085         /* add all the MAC and VLAN back */
11086         ret = i40e_vsi_restore_mac_filter(vsi);
11087         if (ret)
11088                 return ret;
11089         if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
11090                 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
11091                 if (ret)
11092                         return ret;
11093         }
11094
11095         return ret;
11096 }
11097
11098 int
11099 rte_pmd_i40e_set_tx_loopback(uint8_t port, uint8_t on)
11100 {
11101         struct rte_eth_dev *dev;
11102         struct i40e_pf *pf;
11103         struct i40e_pf_vf *vf;
11104         struct i40e_vsi *vsi;
11105         uint16_t vf_id;
11106         int ret;
11107
11108         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11109
11110         dev = &rte_eth_devices[port];
11111
11112         if (!is_device_supported(dev, &rte_i40e_pmd))
11113                 return -ENOTSUP;
11114
11115         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11116
11117         /* setup PF TX loopback */
11118         vsi = pf->main_vsi;
11119         ret = i40e_vsi_set_tx_loopback(vsi, on);
11120         if (ret)
11121                 return -ENOTSUP;
11122
11123         /* setup TX loopback for all the VFs */
11124         if (!pf->vfs) {
11125                 /* if no VF, do nothing. */
11126                 return 0;
11127         }
11128
11129         for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
11130                 vf = &pf->vfs[vf_id];
11131                 vsi = vf->vsi;
11132
11133                 ret = i40e_vsi_set_tx_loopback(vsi, on);
11134                 if (ret)
11135                         return -ENOTSUP;
11136         }
11137
11138         return ret;
11139 }
11140
11141 int
11142 rte_pmd_i40e_set_vf_unicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
11143 {
11144         struct rte_eth_dev *dev;
11145         struct i40e_pf *pf;
11146         struct i40e_vsi *vsi;
11147         struct i40e_hw *hw;
11148         int ret;
11149
11150         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11151
11152         dev = &rte_eth_devices[port];
11153
11154         if (!is_device_supported(dev, &rte_i40e_pmd))
11155                 return -ENOTSUP;
11156
11157         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11158
11159         if (vf_id >= pf->vf_num || !pf->vfs) {
11160                 PMD_DRV_LOG(ERR, "Invalid argument.");
11161                 return -EINVAL;
11162         }
11163
11164         vsi = pf->vfs[vf_id].vsi;
11165         if (!vsi) {
11166                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11167                 return -EINVAL;
11168         }
11169
11170         hw = I40E_VSI_TO_HW(vsi);
11171
11172         ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
11173                                                   on, NULL, true);
11174         if (ret != I40E_SUCCESS) {
11175                 ret = -ENOTSUP;
11176                 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
11177         }
11178
11179         return ret;
11180 }
11181
11182 int
11183 rte_pmd_i40e_set_vf_multicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
11184 {
11185         struct rte_eth_dev *dev;
11186         struct i40e_pf *pf;
11187         struct i40e_vsi *vsi;
11188         struct i40e_hw *hw;
11189         int ret;
11190
11191         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11192
11193         dev = &rte_eth_devices[port];
11194
11195         if (!is_device_supported(dev, &rte_i40e_pmd))
11196                 return -ENOTSUP;
11197
11198         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11199
11200         if (vf_id >= pf->vf_num || !pf->vfs) {
11201                 PMD_DRV_LOG(ERR, "Invalid argument.");
11202                 return -EINVAL;
11203         }
11204
11205         vsi = pf->vfs[vf_id].vsi;
11206         if (!vsi) {
11207                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11208                 return -EINVAL;
11209         }
11210
11211         hw = I40E_VSI_TO_HW(vsi);
11212
11213         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
11214                                                     on, NULL);
11215         if (ret != I40E_SUCCESS) {
11216                 ret = -ENOTSUP;
11217                 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
11218         }
11219
11220         return ret;
11221 }
11222
11223 int
11224 rte_pmd_i40e_set_vf_mac_addr(uint8_t port, uint16_t vf_id,
11225                              struct ether_addr *mac_addr)
11226 {
11227         struct i40e_mac_filter *f;
11228         struct rte_eth_dev *dev;
11229         struct i40e_pf_vf *vf;
11230         struct i40e_vsi *vsi;
11231         struct i40e_pf *pf;
11232         void *temp;
11233
11234         if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
11235                 return -EINVAL;
11236
11237         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11238
11239         dev = &rte_eth_devices[port];
11240
11241         if (!is_device_supported(dev, &rte_i40e_pmd))
11242                 return -ENOTSUP;
11243
11244         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11245
11246         if (vf_id >= pf->vf_num || !pf->vfs)
11247                 return -EINVAL;
11248
11249         vf = &pf->vfs[vf_id];
11250         vsi = vf->vsi;
11251         if (!vsi) {
11252                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11253                 return -EINVAL;
11254         }
11255
11256         ether_addr_copy(mac_addr, &vf->mac_addr);
11257
11258         /* Remove all existing mac */
11259         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
11260                 i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
11261
11262         return 0;
11263 }
11264
11265 /* Set vlan strip on/off for specific VF from host */
11266 int
11267 rte_pmd_i40e_set_vf_vlan_stripq(uint8_t port, uint16_t vf_id, uint8_t on)
11268 {
11269         struct rte_eth_dev *dev;
11270         struct i40e_pf *pf;
11271         struct i40e_vsi *vsi;
11272         int ret;
11273
11274         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11275
11276         dev = &rte_eth_devices[port];
11277
11278         if (!is_device_supported(dev, &rte_i40e_pmd))
11279                 return -ENOTSUP;
11280
11281         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11282
11283         if (vf_id >= pf->vf_num || !pf->vfs) {
11284                 PMD_DRV_LOG(ERR, "Invalid argument.");
11285                 return -EINVAL;
11286         }
11287
11288         vsi = pf->vfs[vf_id].vsi;
11289
11290         if (!vsi)
11291                 return -EINVAL;
11292
11293         ret = i40e_vsi_config_vlan_stripping(vsi, !!on);
11294         if (ret != I40E_SUCCESS) {
11295                 ret = -ENOTSUP;
11296                 PMD_DRV_LOG(ERR, "Failed to set VLAN stripping!");
11297         }
11298
11299         return ret;
11300 }
11301
11302 int rte_pmd_i40e_set_vf_vlan_insert(uint8_t port, uint16_t vf_id,
11303                                     uint16_t vlan_id)
11304 {
11305         struct rte_eth_dev *dev;
11306         struct i40e_pf *pf;
11307         struct i40e_hw *hw;
11308         struct i40e_vsi *vsi;
11309         struct i40e_vsi_context ctxt;
11310         int ret;
11311
11312         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11313
11314         if (vlan_id > ETHER_MAX_VLAN_ID) {
11315                 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11316                 return -EINVAL;
11317         }
11318
11319         dev = &rte_eth_devices[port];
11320
11321         if (!is_device_supported(dev, &rte_i40e_pmd))
11322                 return -ENOTSUP;
11323
11324         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11325         hw = I40E_PF_TO_HW(pf);
11326
11327         /**
11328          * return -ENODEV if SRIOV not enabled, VF number not configured
11329          * or no queue assigned.
11330          */
11331         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11332             pf->vf_nb_qps == 0)
11333                 return -ENODEV;
11334
11335         if (vf_id >= pf->vf_num || !pf->vfs) {
11336                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11337                 return -EINVAL;
11338         }
11339
11340         vsi = pf->vfs[vf_id].vsi;
11341         if (!vsi) {
11342                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11343                 return -EINVAL;
11344         }
11345
11346         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11347         vsi->info.pvid = vlan_id;
11348         if (vlan_id > 0)
11349                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
11350         else
11351                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_INSERT_PVID;
11352
11353         memset(&ctxt, 0, sizeof(ctxt));
11354         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11355         ctxt.seid = vsi->seid;
11356
11357         hw = I40E_VSI_TO_HW(vsi);
11358         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11359         if (ret != I40E_SUCCESS) {
11360                 ret = -ENOTSUP;
11361                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11362         }
11363
11364         return ret;
11365 }
11366
11367 int rte_pmd_i40e_set_vf_broadcast(uint8_t port, uint16_t vf_id,
11368                                   uint8_t on)
11369 {
11370         struct rte_eth_dev *dev;
11371         struct i40e_pf *pf;
11372         struct i40e_vsi *vsi;
11373         struct i40e_hw *hw;
11374         struct i40e_mac_filter_info filter;
11375         struct ether_addr broadcast = {
11376                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
11377         int ret;
11378
11379         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11380
11381         if (on > 1) {
11382                 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11383                 return -EINVAL;
11384         }
11385
11386         dev = &rte_eth_devices[port];
11387
11388         if (!is_device_supported(dev, &rte_i40e_pmd))
11389                 return -ENOTSUP;
11390
11391         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11392         hw = I40E_PF_TO_HW(pf);
11393
11394         if (vf_id >= pf->vf_num || !pf->vfs) {
11395                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11396                 return -EINVAL;
11397         }
11398
11399         /**
11400          * return -ENODEV if SRIOV not enabled, VF number not configured
11401          * or no queue assigned.
11402          */
11403         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11404             pf->vf_nb_qps == 0) {
11405                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11406                 return -ENODEV;
11407         }
11408
11409         vsi = pf->vfs[vf_id].vsi;
11410         if (!vsi) {
11411                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11412                 return -EINVAL;
11413         }
11414
11415         if (on) {
11416                 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
11417                 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
11418                 ret = i40e_vsi_add_mac(vsi, &filter);
11419         } else {
11420                 ret = i40e_vsi_delete_mac(vsi, &broadcast);
11421         }
11422
11423         if (ret != I40E_SUCCESS && ret != I40E_ERR_PARAM) {
11424                 ret = -ENOTSUP;
11425                 PMD_DRV_LOG(ERR, "Failed to set VSI broadcast");
11426         } else {
11427                 ret = 0;
11428         }
11429
11430         return ret;
11431 }
11432
11433 int rte_pmd_i40e_set_vf_vlan_tag(uint8_t port, uint16_t vf_id, uint8_t on)
11434 {
11435         struct rte_eth_dev *dev;
11436         struct i40e_pf *pf;
11437         struct i40e_hw *hw;
11438         struct i40e_vsi *vsi;
11439         struct i40e_vsi_context ctxt;
11440         int ret;
11441
11442         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11443
11444         if (on > 1) {
11445                 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11446                 return -EINVAL;
11447         }
11448
11449         dev = &rte_eth_devices[port];
11450
11451         if (!is_device_supported(dev, &rte_i40e_pmd))
11452                 return -ENOTSUP;
11453
11454         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11455         hw = I40E_PF_TO_HW(pf);
11456
11457         /**
11458          * return -ENODEV if SRIOV not enabled, VF number not configured
11459          * or no queue assigned.
11460          */
11461         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11462             pf->vf_nb_qps == 0) {
11463                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11464                 return -ENODEV;
11465         }
11466
11467         if (vf_id >= pf->vf_num || !pf->vfs) {
11468                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11469                 return -EINVAL;
11470         }
11471
11472         vsi = pf->vfs[vf_id].vsi;
11473         if (!vsi) {
11474                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11475                 return -EINVAL;
11476         }
11477
11478         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11479         if (on) {
11480                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11481                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11482         } else {
11483                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11484                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11485         }
11486
11487         memset(&ctxt, 0, sizeof(ctxt));
11488         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11489         ctxt.seid = vsi->seid;
11490
11491         hw = I40E_VSI_TO_HW(vsi);
11492         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11493         if (ret != I40E_SUCCESS) {
11494                 ret = -ENOTSUP;
11495                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11496         }
11497
11498         return ret;
11499 }
11500
11501 static int
11502 i40e_vlan_filter_count(struct i40e_vsi *vsi)
11503 {
11504         uint32_t j, k;
11505         uint16_t vlan_id;
11506         int count = 0;
11507
11508         for (j = 0; j < I40E_VFTA_SIZE; j++) {
11509                 if (!vsi->vfta[j])
11510                         continue;
11511
11512                 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
11513                         if (!(vsi->vfta[j] & (1 << k)))
11514                                 continue;
11515
11516                         vlan_id = j * I40E_UINT32_BIT_SIZE + k;
11517                         if (!vlan_id)
11518                                 continue;
11519
11520                         count++;
11521                 }
11522         }
11523
11524         return count;
11525 }
11526
11527 int rte_pmd_i40e_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,
11528                                     uint64_t vf_mask, uint8_t on)
11529 {
11530         struct rte_eth_dev *dev;
11531         struct i40e_pf *pf;
11532         struct i40e_hw *hw;
11533         struct i40e_vsi *vsi;
11534         uint16_t vf_idx;
11535         int ret = I40E_SUCCESS;
11536
11537         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11538
11539         dev = &rte_eth_devices[port];
11540
11541         if (!is_device_supported(dev, &rte_i40e_pmd))
11542                 return -ENOTSUP;
11543
11544         if (vlan_id > ETHER_MAX_VLAN_ID || !vlan_id) {
11545                 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11546                 return -EINVAL;
11547         }
11548
11549         if (vf_mask == 0) {
11550                 PMD_DRV_LOG(ERR, "No VF.");
11551                 return -EINVAL;
11552         }
11553
11554         if (on > 1) {
11555                 PMD_DRV_LOG(ERR, "on is should be 0 or 1.");
11556                 return -EINVAL;
11557         }
11558
11559         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11560         hw = I40E_PF_TO_HW(pf);
11561
11562         /**
11563          * return -ENODEV if SRIOV not enabled, VF number not configured
11564          * or no queue assigned.
11565          */
11566         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11567             pf->vf_nb_qps == 0) {
11568                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11569                 return -ENODEV;
11570         }
11571
11572         for (vf_idx = 0; vf_idx < pf->vf_num && ret == I40E_SUCCESS; vf_idx++) {
11573                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
11574                         vsi = pf->vfs[vf_idx].vsi;
11575                         if (on) {
11576                                 if (!vsi->vlan_filter_on) {
11577                                         vsi->vlan_filter_on = true;
11578                                         i40e_aq_set_vsi_vlan_promisc(hw,
11579                                                                      vsi->seid,
11580                                                                      false,
11581                                                                      NULL);
11582                                         if (!vsi->vlan_anti_spoof_on)
11583                                                 i40e_add_rm_all_vlan_filter(
11584                                                         vsi, true);
11585                                 }
11586                                 ret = i40e_vsi_add_vlan(vsi, vlan_id);
11587                         } else {
11588                                 ret = i40e_vsi_delete_vlan(vsi, vlan_id);
11589
11590                                 if (!i40e_vlan_filter_count(vsi)) {
11591                                         vsi->vlan_filter_on = false;
11592                                         i40e_aq_set_vsi_vlan_promisc(hw,
11593                                                                      vsi->seid,
11594                                                                      true,
11595                                                                      NULL);
11596                                 }
11597                         }
11598                 }
11599         }
11600
11601         if (ret != I40E_SUCCESS) {
11602                 ret = -ENOTSUP;
11603                 PMD_DRV_LOG(ERR, "Failed to set VF VLAN filter, on = %d", on);
11604         }
11605
11606         return ret;
11607 }
11608
11609 int
11610 rte_pmd_i40e_get_vf_stats(uint8_t port,
11611                           uint16_t vf_id,
11612                           struct rte_eth_stats *stats)
11613 {
11614         struct rte_eth_dev *dev;
11615         struct i40e_pf *pf;
11616         struct i40e_vsi *vsi;
11617
11618         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11619
11620         dev = &rte_eth_devices[port];
11621
11622         if (!is_device_supported(dev, &rte_i40e_pmd))
11623                 return -ENOTSUP;
11624
11625         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11626
11627         if (vf_id >= pf->vf_num || !pf->vfs) {
11628                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11629                 return -EINVAL;
11630         }
11631
11632         vsi = pf->vfs[vf_id].vsi;
11633         if (!vsi) {
11634                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11635                 return -EINVAL;
11636         }
11637
11638         i40e_update_vsi_stats(vsi);
11639
11640         stats->ipackets = vsi->eth_stats.rx_unicast +
11641                         vsi->eth_stats.rx_multicast +
11642                         vsi->eth_stats.rx_broadcast;
11643         stats->opackets = vsi->eth_stats.tx_unicast +
11644                         vsi->eth_stats.tx_multicast +
11645                         vsi->eth_stats.tx_broadcast;
11646         stats->ibytes   = vsi->eth_stats.rx_bytes;
11647         stats->obytes   = vsi->eth_stats.tx_bytes;
11648         stats->ierrors  = vsi->eth_stats.rx_discards;
11649         stats->oerrors  = vsi->eth_stats.tx_errors + vsi->eth_stats.tx_discards;
11650
11651         return 0;
11652 }
11653
11654 int
11655 rte_pmd_i40e_reset_vf_stats(uint8_t port,
11656                             uint16_t vf_id)
11657 {
11658         struct rte_eth_dev *dev;
11659         struct i40e_pf *pf;
11660         struct i40e_vsi *vsi;
11661
11662         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11663
11664         dev = &rte_eth_devices[port];
11665
11666         if (!is_device_supported(dev, &rte_i40e_pmd))
11667                 return -ENOTSUP;
11668
11669         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11670
11671         if (vf_id >= pf->vf_num || !pf->vfs) {
11672                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11673                 return -EINVAL;
11674         }
11675
11676         vsi = pf->vfs[vf_id].vsi;
11677         if (!vsi) {
11678                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11679                 return -EINVAL;
11680         }
11681
11682         vsi->offset_loaded = false;
11683         i40e_update_vsi_stats(vsi);
11684
11685         return 0;
11686 }
11687
11688 int
11689 rte_pmd_i40e_set_vf_max_bw(uint8_t port, uint16_t vf_id, uint32_t bw)
11690 {
11691         struct rte_eth_dev *dev;
11692         struct i40e_pf *pf;
11693         struct i40e_vsi *vsi;
11694         struct i40e_hw *hw;
11695         int ret = 0;
11696         int i;
11697
11698         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11699
11700         dev = &rte_eth_devices[port];
11701
11702         if (!is_device_supported(dev, &rte_i40e_pmd))
11703                 return -ENOTSUP;
11704
11705         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11706
11707         if (vf_id >= pf->vf_num || !pf->vfs) {
11708                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11709                 return -EINVAL;
11710         }
11711
11712         vsi = pf->vfs[vf_id].vsi;
11713         if (!vsi) {
11714                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11715                 return -EINVAL;
11716         }
11717
11718         if (bw > I40E_QOS_BW_MAX) {
11719                 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
11720                             I40E_QOS_BW_MAX);
11721                 return -EINVAL;
11722         }
11723
11724         if (bw % I40E_QOS_BW_GRANULARITY) {
11725                 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
11726                             I40E_QOS_BW_GRANULARITY);
11727                 return -EINVAL;
11728         }
11729
11730         bw /= I40E_QOS_BW_GRANULARITY;
11731
11732         hw = I40E_VSI_TO_HW(vsi);
11733
11734         /* No change. */
11735         if (bw == vsi->bw_info.bw_limit) {
11736                 PMD_DRV_LOG(INFO,
11737                             "No change for VF max bandwidth. Nothing to do.");
11738                 return 0;
11739         }
11740
11741         /**
11742          * VF bandwidth limitation and TC bandwidth limitation cannot be
11743          * enabled in parallel, quit if TC bandwidth limitation is enabled.
11744          *
11745          * If bw is 0, means disable bandwidth limitation. Then no need to
11746          * check TC bandwidth limitation.
11747          */
11748         if (bw) {
11749                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11750                         if ((vsi->enabled_tc & BIT_ULL(i)) &&
11751                             vsi->bw_info.bw_ets_credits[i])
11752                                 break;
11753                 }
11754                 if (i != I40E_MAX_TRAFFIC_CLASS) {
11755                         PMD_DRV_LOG(ERR,
11756                                     "TC max bandwidth has been set on this VF,"
11757                                     " please disable it first.");
11758                         return -EINVAL;
11759                 }
11760         }
11761
11762         ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, (uint16_t)bw, 0, NULL);
11763         if (ret) {
11764                 PMD_DRV_LOG(ERR,
11765                             "Failed to set VF %d bandwidth, err(%d).",
11766                             vf_id, ret);
11767                 return -EINVAL;
11768         }
11769
11770         /* Store the configuration. */
11771         vsi->bw_info.bw_limit = (uint16_t)bw;
11772         vsi->bw_info.bw_max = 0;
11773
11774         return 0;
11775 }
11776
11777 int
11778 rte_pmd_i40e_set_vf_tc_bw_alloc(uint8_t port, uint16_t vf_id,
11779                                 uint8_t tc_num, uint8_t *bw_weight)
11780 {
11781         struct rte_eth_dev *dev;
11782         struct i40e_pf *pf;
11783         struct i40e_vsi *vsi;
11784         struct i40e_hw *hw;
11785         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw;
11786         int ret = 0;
11787         int i, j;
11788         uint16_t sum;
11789         bool b_change = false;
11790
11791         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11792
11793         dev = &rte_eth_devices[port];
11794
11795         if (!is_device_supported(dev, &rte_i40e_pmd))
11796                 return -ENOTSUP;
11797
11798         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11799
11800         if (vf_id >= pf->vf_num || !pf->vfs) {
11801                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11802                 return -EINVAL;
11803         }
11804
11805         vsi = pf->vfs[vf_id].vsi;
11806         if (!vsi) {
11807                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11808                 return -EINVAL;
11809         }
11810
11811         if (tc_num > I40E_MAX_TRAFFIC_CLASS) {
11812                 PMD_DRV_LOG(ERR, "TCs should be no more than %d.",
11813                             I40E_MAX_TRAFFIC_CLASS);
11814                 return -EINVAL;
11815         }
11816
11817         sum = 0;
11818         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11819                 if (vsi->enabled_tc & BIT_ULL(i))
11820                         sum++;
11821         }
11822         if (sum != tc_num) {
11823                 PMD_DRV_LOG(ERR,
11824                             "Weight should be set for all %d enabled TCs.",
11825                             sum);
11826                 return -EINVAL;
11827         }
11828
11829         sum = 0;
11830         for (i = 0; i < tc_num; i++) {
11831                 if (!bw_weight[i]) {
11832                         PMD_DRV_LOG(ERR,
11833                                     "The weight should be 1 at least.");
11834                         return -EINVAL;
11835                 }
11836                 sum += bw_weight[i];
11837         }
11838         if (sum != 100) {
11839                 PMD_DRV_LOG(ERR,
11840                             "The summary of the TC weight should be 100.");
11841                 return -EINVAL;
11842         }
11843
11844         /**
11845          * Create the configuration for all the TCs.
11846          */
11847         memset(&tc_bw, 0, sizeof(tc_bw));
11848         tc_bw.tc_valid_bits = vsi->enabled_tc;
11849         j = 0;
11850         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11851                 if (vsi->enabled_tc & BIT_ULL(i)) {
11852                         if (bw_weight[j] !=
11853                                 vsi->bw_info.bw_ets_share_credits[i])
11854                                 b_change = true;
11855
11856                         tc_bw.tc_bw_credits[i] = bw_weight[j];
11857                         j++;
11858                 }
11859         }
11860
11861         /* No change. */
11862         if (!b_change) {
11863                 PMD_DRV_LOG(INFO,
11864                             "No change for TC allocated bandwidth."
11865                             " Nothing to do.");
11866                 return 0;
11867         }
11868
11869         hw = I40E_VSI_TO_HW(vsi);
11870
11871         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw, NULL);
11872         if (ret) {
11873                 PMD_DRV_LOG(ERR,
11874                             "Failed to set VF %d TC bandwidth weight, err(%d).",
11875                             vf_id, ret);
11876                 return -EINVAL;
11877         }
11878
11879         /* Store the configuration. */
11880         j = 0;
11881         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11882                 if (vsi->enabled_tc & BIT_ULL(i)) {
11883                         vsi->bw_info.bw_ets_share_credits[i] = bw_weight[j];
11884                         j++;
11885                 }
11886         }
11887
11888         return 0;
11889 }
11890
11891 int
11892 rte_pmd_i40e_set_vf_tc_max_bw(uint8_t port, uint16_t vf_id,
11893                               uint8_t tc_no, uint32_t bw)
11894 {
11895         struct rte_eth_dev *dev;
11896         struct i40e_pf *pf;
11897         struct i40e_vsi *vsi;
11898         struct i40e_hw *hw;
11899         struct i40e_aqc_configure_vsi_ets_sla_bw_data tc_bw;
11900         int ret = 0;
11901         int i;
11902
11903         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11904
11905         dev = &rte_eth_devices[port];
11906
11907         if (!is_device_supported(dev, &rte_i40e_pmd))
11908                 return -ENOTSUP;
11909
11910         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11911
11912         if (vf_id >= pf->vf_num || !pf->vfs) {
11913                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11914                 return -EINVAL;
11915         }
11916
11917         vsi = pf->vfs[vf_id].vsi;
11918         if (!vsi) {
11919                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11920                 return -EINVAL;
11921         }
11922
11923         if (bw > I40E_QOS_BW_MAX) {
11924                 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
11925                             I40E_QOS_BW_MAX);
11926                 return -EINVAL;
11927         }
11928
11929         if (bw % I40E_QOS_BW_GRANULARITY) {
11930                 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
11931                             I40E_QOS_BW_GRANULARITY);
11932                 return -EINVAL;
11933         }
11934
11935         bw /= I40E_QOS_BW_GRANULARITY;
11936
11937         if (tc_no >= I40E_MAX_TRAFFIC_CLASS) {
11938                 PMD_DRV_LOG(ERR, "TC No. should be less than %d.",
11939                             I40E_MAX_TRAFFIC_CLASS);
11940                 return -EINVAL;
11941         }
11942
11943         hw = I40E_VSI_TO_HW(vsi);
11944
11945         if (!(vsi->enabled_tc & BIT_ULL(tc_no))) {
11946                 PMD_DRV_LOG(ERR, "VF %d TC %d isn't enabled.",
11947                             vf_id, tc_no);
11948                 return -EINVAL;
11949         }
11950
11951         /* No change. */
11952         if (bw == vsi->bw_info.bw_ets_credits[tc_no]) {
11953                 PMD_DRV_LOG(INFO,
11954                             "No change for TC max bandwidth. Nothing to do.");
11955                 return 0;
11956         }
11957
11958         /**
11959          * VF bandwidth limitation and TC bandwidth limitation cannot be
11960          * enabled in parallel, disable VF bandwidth limitation if it's
11961          * enabled.
11962          * If bw is 0, means disable bandwidth limitation. Then no need to
11963          * care about VF bandwidth limitation configuration.
11964          */
11965         if (bw && vsi->bw_info.bw_limit) {
11966                 ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, 0, 0, NULL);
11967                 if (ret) {
11968                         PMD_DRV_LOG(ERR,
11969                                     "Failed to disable VF(%d)"
11970                                     " bandwidth limitation, err(%d).",
11971                                     vf_id, ret);
11972                         return -EINVAL;
11973                 }
11974
11975                 PMD_DRV_LOG(INFO,
11976                             "VF max bandwidth is disabled according"
11977                             " to TC max bandwidth setting.");
11978         }
11979
11980         /**
11981          * Get all the TCs' info to create a whole picture.
11982          * Because the incremental change isn't permitted.
11983          */
11984         memset(&tc_bw, 0, sizeof(tc_bw));
11985         tc_bw.tc_valid_bits = vsi->enabled_tc;
11986         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11987                 if (vsi->enabled_tc & BIT_ULL(i)) {
11988                         tc_bw.tc_bw_credits[i] =
11989                                 rte_cpu_to_le_16(
11990                                         vsi->bw_info.bw_ets_credits[i]);
11991                 }
11992         }
11993         tc_bw.tc_bw_credits[tc_no] = rte_cpu_to_le_16((uint16_t)bw);
11994
11995         ret = i40e_aq_config_vsi_ets_sla_bw_limit(hw, vsi->seid, &tc_bw, NULL);
11996         if (ret) {
11997                 PMD_DRV_LOG(ERR,
11998                             "Failed to set VF %d TC %d max bandwidth, err(%d).",
11999                             vf_id, tc_no, ret);
12000                 return -EINVAL;
12001         }
12002
12003         /* Store the configuration. */
12004         vsi->bw_info.bw_ets_credits[tc_no] = (uint16_t)bw;
12005
12006         return 0;
12007 }
12008
12009 int
12010 rte_pmd_i40e_set_tc_strict_prio(uint8_t port, uint8_t tc_map)
12011 {
12012         struct rte_eth_dev *dev;
12013         struct i40e_pf *pf;
12014         struct i40e_vsi *vsi;
12015         struct i40e_veb *veb;
12016         struct i40e_hw *hw;
12017         struct i40e_aqc_configure_switching_comp_ets_data ets_data;
12018         int i;
12019         int ret;
12020
12021         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12022
12023         dev = &rte_eth_devices[port];
12024
12025         if (!is_device_supported(dev, &rte_i40e_pmd))
12026                 return -ENOTSUP;
12027
12028         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12029
12030         vsi = pf->main_vsi;
12031         if (!vsi) {
12032                 PMD_DRV_LOG(ERR, "Invalid VSI.");
12033                 return -EINVAL;
12034         }
12035
12036         veb = vsi->veb;
12037         if (!veb) {
12038                 PMD_DRV_LOG(ERR, "Invalid VEB.");
12039                 return -EINVAL;
12040         }
12041
12042         if ((tc_map & veb->enabled_tc) != tc_map) {
12043                 PMD_DRV_LOG(ERR,
12044                             "TC bitmap isn't the subset of enabled TCs 0x%x.",
12045                             veb->enabled_tc);
12046                 return -EINVAL;
12047         }
12048
12049         if (tc_map == veb->strict_prio_tc) {
12050                 PMD_DRV_LOG(INFO, "No change for TC bitmap. Nothing to do.");
12051                 return 0;
12052         }
12053
12054         hw = I40E_VSI_TO_HW(vsi);
12055
12056         /* Disable DCBx if it's the first time to set strict priority. */
12057         if (!veb->strict_prio_tc) {
12058                 ret = i40e_aq_stop_lldp(hw, true, NULL);
12059                 if (ret)
12060                         PMD_DRV_LOG(INFO,
12061                                     "Failed to disable DCBx as it's already"
12062                                     " disabled.");
12063                 else
12064                         PMD_DRV_LOG(INFO,
12065                                     "DCBx is disabled according to strict"
12066                                     " priority setting.");
12067         }
12068
12069         memset(&ets_data, 0, sizeof(ets_data));
12070         ets_data.tc_valid_bits = veb->enabled_tc;
12071         ets_data.seepage = I40E_AQ_ETS_SEEPAGE_EN_MASK;
12072         ets_data.tc_strict_priority_flags = tc_map;
12073         /* Get all TCs' bandwidth. */
12074         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12075                 if (veb->enabled_tc & BIT_ULL(i)) {
12076                         /* For rubust, if bandwidth is 0, use 1 instead. */
12077                         if (veb->bw_info.bw_ets_share_credits[i])
12078                                 ets_data.tc_bw_share_credits[i] =
12079                                         veb->bw_info.bw_ets_share_credits[i];
12080                         else
12081                                 ets_data.tc_bw_share_credits[i] =
12082                                         I40E_QOS_BW_WEIGHT_MIN;
12083                 }
12084         }
12085
12086         if (!veb->strict_prio_tc)
12087                 ret = i40e_aq_config_switch_comp_ets(
12088                         hw, veb->uplink_seid,
12089                         &ets_data, i40e_aqc_opc_enable_switching_comp_ets,
12090                         NULL);
12091         else if (tc_map)
12092                 ret = i40e_aq_config_switch_comp_ets(
12093                         hw, veb->uplink_seid,
12094                         &ets_data, i40e_aqc_opc_modify_switching_comp_ets,
12095                         NULL);
12096         else
12097                 ret = i40e_aq_config_switch_comp_ets(
12098                         hw, veb->uplink_seid,
12099                         &ets_data, i40e_aqc_opc_disable_switching_comp_ets,
12100                         NULL);
12101
12102         if (ret) {
12103                 PMD_DRV_LOG(ERR,
12104                             "Failed to set TCs' strict priority mode."
12105                             " err (%d)", ret);
12106                 return -EINVAL;
12107         }
12108
12109         veb->strict_prio_tc = tc_map;
12110
12111         /* Enable DCBx again, if all the TCs' strict priority disabled. */
12112         if (!tc_map) {
12113                 ret = i40e_aq_start_lldp(hw, NULL);
12114                 if (ret) {
12115                         PMD_DRV_LOG(ERR,
12116                                     "Failed to enable DCBx, err(%d).", ret);
12117                         return -EINVAL;
12118                 }
12119
12120                 PMD_DRV_LOG(INFO,
12121                             "DCBx is enabled again according to strict"
12122                             " priority setting.");
12123         }
12124
12125         return ret;
12126 }
12127
12128 #define I40E_PROFILE_INFO_SIZE 48
12129 #define I40E_MAX_PROFILE_NUM 16
12130
12131 static void
12132 i40e_generate_profile_info_sec(char *name, struct i40e_ddp_version *version,
12133                                uint32_t track_id, uint8_t *profile_info_sec,
12134                                bool add)
12135 {
12136         struct i40e_profile_section_header *sec = NULL;
12137         struct i40e_profile_info *pinfo;
12138
12139         sec = (struct i40e_profile_section_header *)profile_info_sec;
12140         sec->tbl_size = 1;
12141         sec->data_end = sizeof(struct i40e_profile_section_header) +
12142                 sizeof(struct i40e_profile_info);
12143         sec->section.type = SECTION_TYPE_INFO;
12144         sec->section.offset = sizeof(struct i40e_profile_section_header);
12145         sec->section.size = sizeof(struct i40e_profile_info);
12146         pinfo = (struct i40e_profile_info *)(profile_info_sec +
12147                                              sec->section.offset);
12148         pinfo->track_id = track_id;
12149         memcpy(pinfo->name, name, I40E_DDP_NAME_SIZE);
12150         memcpy(&pinfo->version, version, sizeof(struct i40e_ddp_version));
12151         if (add)
12152                 pinfo->op = I40E_DDP_ADD_TRACKID;
12153         else
12154                 pinfo->op = I40E_DDP_REMOVE_TRACKID;
12155 }
12156
12157 static enum i40e_status_code
12158 i40e_add_rm_profile_info(struct i40e_hw *hw, uint8_t *profile_info_sec)
12159 {
12160         enum i40e_status_code status = I40E_SUCCESS;
12161         struct i40e_profile_section_header *sec;
12162         uint32_t track_id;
12163         uint32_t offset = 0;
12164         uint32_t info = 0;
12165
12166         sec = (struct i40e_profile_section_header *)profile_info_sec;
12167         track_id = ((struct i40e_profile_info *)(profile_info_sec +
12168                                          sec->section.offset))->track_id;
12169
12170         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
12171                                    track_id, &offset, &info, NULL);
12172         if (status)
12173                 PMD_DRV_LOG(ERR, "Failed to add/remove profile info: "
12174                             "offset %d, info %d",
12175                             offset, info);
12176
12177         return status;
12178 }
12179
12180 #define I40E_PROFILE_INFO_SIZE 48
12181 #define I40E_MAX_PROFILE_NUM 16
12182
12183 /* Check if the profile info exists */
12184 static int
12185 i40e_check_profile_info(uint8_t port, uint8_t *profile_info_sec)
12186 {
12187         struct rte_eth_dev *dev = &rte_eth_devices[port];
12188         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12189         uint8_t *buff;
12190         struct rte_pmd_i40e_profile_list *p_list;
12191         struct rte_pmd_i40e_profile_info *pinfo, *p;
12192         uint32_t i;
12193         int ret;
12194
12195         buff = rte_zmalloc("pinfo_list",
12196                            (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4),
12197                            0);
12198         if (!buff) {
12199                 PMD_DRV_LOG(ERR, "failed to allocate memory");
12200                 return -1;
12201         }
12202
12203         ret = i40e_aq_get_ddp_list(hw, (void *)buff,
12204                       (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4),
12205                       0, NULL);
12206         if (ret) {
12207                 PMD_DRV_LOG(ERR, "Failed to get profile info list.");
12208                 rte_free(buff);
12209                 return -1;
12210         }
12211         p_list = (struct rte_pmd_i40e_profile_list *)buff;
12212         pinfo = (struct rte_pmd_i40e_profile_info *)(profile_info_sec +
12213                              sizeof(struct i40e_profile_section_header));
12214         for (i = 0; i < p_list->p_count; i++) {
12215                 p = &p_list->p_info[i];
12216                 if ((pinfo->track_id == p->track_id) &&
12217                     !memcmp(&pinfo->version, &p->version,
12218                             sizeof(struct i40e_ddp_version)) &&
12219                     !memcmp(&pinfo->name, &p->name,
12220                             I40E_DDP_NAME_SIZE)) {
12221                         PMD_DRV_LOG(INFO, "Profile exists.");
12222                         rte_free(buff);
12223                         return 1;
12224                 }
12225         }
12226
12227         rte_free(buff);
12228         return 0;
12229 }
12230
12231 int
12232 rte_pmd_i40e_process_ddp_package(uint8_t port, uint8_t *buff,
12233                                  uint32_t size,
12234                                  enum rte_pmd_i40e_package_op op)
12235 {
12236         struct rte_eth_dev *dev;
12237         struct i40e_hw *hw;
12238         struct i40e_package_header *pkg_hdr;
12239         struct i40e_generic_seg_header *profile_seg_hdr;
12240         struct i40e_generic_seg_header *metadata_seg_hdr;
12241         uint32_t track_id;
12242         uint8_t *profile_info_sec;
12243         int is_exist;
12244         enum i40e_status_code status = I40E_SUCCESS;
12245
12246         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12247
12248         dev = &rte_eth_devices[port];
12249
12250         if (!is_device_supported(dev, &rte_i40e_pmd))
12251                 return -ENOTSUP;
12252
12253         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12254
12255         if (size < (sizeof(struct i40e_package_header) +
12256                     sizeof(struct i40e_metadata_segment) +
12257                     sizeof(uint32_t) * 2)) {
12258                 PMD_DRV_LOG(ERR, "Buff is invalid.");
12259                 return -EINVAL;
12260         }
12261
12262         pkg_hdr = (struct i40e_package_header *)buff;
12263
12264         if (!pkg_hdr) {
12265                 PMD_DRV_LOG(ERR, "Failed to fill the package structure");
12266                 return -EINVAL;
12267         }
12268
12269         if (pkg_hdr->segment_count < 2) {
12270                 PMD_DRV_LOG(ERR, "Segment_count should be 2 at least.");
12271                 return -EINVAL;
12272         }
12273
12274         /* Find metadata segment */
12275         metadata_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_METADATA,
12276                                                         pkg_hdr);
12277         if (!metadata_seg_hdr) {
12278                 PMD_DRV_LOG(ERR, "Failed to find metadata segment header");
12279                 return -EINVAL;
12280         }
12281         track_id = ((struct i40e_metadata_segment *)metadata_seg_hdr)->track_id;
12282
12283         /* Find profile segment */
12284         profile_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_I40E,
12285                                                        pkg_hdr);
12286         if (!profile_seg_hdr) {
12287                 PMD_DRV_LOG(ERR, "Failed to find profile segment header");
12288                 return -EINVAL;
12289         }
12290
12291         profile_info_sec = rte_zmalloc("i40e_profile_info",
12292                                sizeof(struct i40e_profile_section_header) +
12293                                sizeof(struct i40e_profile_info),
12294                                0);
12295         if (!profile_info_sec) {
12296                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12297                 return -EINVAL;
12298         }
12299
12300         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12301                 /* Check if the profile exists */
12302                 i40e_generate_profile_info_sec(
12303                      ((struct i40e_profile_segment *)profile_seg_hdr)->name,
12304                      &((struct i40e_profile_segment *)profile_seg_hdr)->version,
12305                      track_id, profile_info_sec, 1);
12306                 is_exist = i40e_check_profile_info(port, profile_info_sec);
12307                 if (is_exist > 0) {
12308                         PMD_DRV_LOG(ERR, "Profile already exists.");
12309                         rte_free(profile_info_sec);
12310                         return 1;
12311                 } else if (is_exist < 0) {
12312                         PMD_DRV_LOG(ERR, "Failed to check profile.");
12313                         rte_free(profile_info_sec);
12314                         return -EINVAL;
12315                 }
12316
12317                 /* Write profile to HW */
12318                 status = i40e_write_profile(hw,
12319                                  (struct i40e_profile_segment *)profile_seg_hdr,
12320                                  track_id);
12321                 if (status) {
12322                         PMD_DRV_LOG(ERR, "Failed to write profile.");
12323                         rte_free(profile_info_sec);
12324                         return status;
12325                 }
12326
12327                 /* Add profile info to info list */
12328                 status = i40e_add_rm_profile_info(hw, profile_info_sec);
12329                 if (status)
12330                         PMD_DRV_LOG(ERR, "Failed to add profile info.");
12331         } else
12332                 PMD_DRV_LOG(ERR, "Operation not supported.");
12333
12334         rte_free(profile_info_sec);
12335         return status;
12336 }
12337
12338 int
12339 rte_pmd_i40e_get_ddp_list(uint8_t port, uint8_t *buff, uint32_t size)
12340 {
12341         struct rte_eth_dev *dev;
12342         struct i40e_hw *hw;
12343         enum i40e_status_code status = I40E_SUCCESS;
12344
12345         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12346
12347         dev = &rte_eth_devices[port];
12348
12349         if (!is_device_supported(dev, &rte_i40e_pmd))
12350                 return -ENOTSUP;
12351
12352         if (size < (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4))
12353                 return -EINVAL;
12354
12355         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12356
12357         status = i40e_aq_get_ddp_list(hw, (void *)buff,
12358                                       size, 0, NULL);
12359
12360         return status;
12361 }
12362
12363 /* Create a QinQ cloud filter
12364  *
12365  * The Fortville NIC has limited resources for tunnel filters,
12366  * so we can only reuse existing filters.
12367  *
12368  * In step 1 we define which Field Vector fields can be used for
12369  * filter types.
12370  * As we do not have the inner tag defined as a field,
12371  * we have to define it first, by reusing one of L1 entries.
12372  *
12373  * In step 2 we are replacing one of existing filter types with
12374  * a new one for QinQ.
12375  * As we reusing L1 and replacing L2, some of the default filter
12376  * types will disappear,which depends on L1 and L2 entries we reuse.
12377  *
12378  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12379  *
12380  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12381  *              later when we define the cloud filter.
12382  *      a.      Valid_flags.replace_cloud = 0
12383  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12384  *      c.      New_filter = 0x10
12385  *      d.      TR bit = 0xff (optional, not used here)
12386  *      e.      Buffer – 2 entries:
12387  *              i.      Byte 0 = 8 (outer vlan FV index).
12388  *                      Byte 1 = 0 (rsv)
12389  *                      Byte 2-3 = 0x0fff
12390  *              ii.     Byte 0 = 37 (inner vlan FV index).
12391  *                      Byte 1 =0 (rsv)
12392  *                      Byte 2-3 = 0x0fff
12393  *
12394  * Step 2:
12395  * 2.   Create cloud filter using two L1 filters entries: stag and
12396  *              new filter(outer vlan+ inner vlan)
12397  *      a.      Valid_flags.replace_cloud = 1
12398  *      b.      Old_filter = 1 (instead of outer IP)
12399  *      c.      New_filter = 0x10
12400  *      d.      Buffer – 2 entries:
12401  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12402  *                      Byte 1-3 = 0 (rsv)
12403  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12404  *                      Byte 9-11 = 0 (rsv)
12405  */
12406 static int
12407 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12408 {
12409         int ret = -ENOTSUP;
12410         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12411         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12412         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12413
12414         /* Init */
12415         memset(&filter_replace, 0,
12416                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12417         memset(&filter_replace_buf, 0,
12418                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12419
12420         /* create L1 filter */
12421         filter_replace.old_filter_type =
12422                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12423         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
12424         filter_replace.tr_bit = 0;
12425
12426         /* Prepare the buffer, 2 entries */
12427         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12428         filter_replace_buf.data[0] |=
12429                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12430         /* Field Vector 12b mask */
12431         filter_replace_buf.data[2] = 0xff;
12432         filter_replace_buf.data[3] = 0x0f;
12433         filter_replace_buf.data[4] =
12434                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12435         filter_replace_buf.data[4] |=
12436                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12437         /* Field Vector 12b mask */
12438         filter_replace_buf.data[6] = 0xff;
12439         filter_replace_buf.data[7] = 0x0f;
12440         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12441                         &filter_replace_buf);
12442         if (ret != I40E_SUCCESS)
12443                 return ret;
12444
12445         /* Apply the second L2 cloud filter */
12446         memset(&filter_replace, 0,
12447                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12448         memset(&filter_replace_buf, 0,
12449                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12450
12451         /* create L2 filter, input for L2 filter will be L1 filter  */
12452         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12453         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12454         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
12455
12456         /* Prepare the buffer, 2 entries */
12457         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12458         filter_replace_buf.data[0] |=
12459                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12460         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
12461         filter_replace_buf.data[4] |=
12462                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12463         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12464                         &filter_replace_buf);
12465         return ret;
12466 }
12467
12468 RTE_INIT(i40e_init_log);
12469 static void
12470 i40e_init_log(void)
12471 {
12472         i40e_logtype_init = rte_log_register("pmd.i40e.init");
12473         if (i40e_logtype_init >= 0)
12474                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12475         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
12476         if (i40e_logtype_driver >= 0)
12477                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12478 }