4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memzone.h>
49 #include <rte_malloc.h>
50 #include <rte_memcpy.h>
51 #include <rte_alarm.h>
53 #include <rte_eth_ctrl.h>
54 #include <rte_tailq.h>
55 #include <rte_hash_crc.h>
57 #include "i40e_logs.h"
58 #include "base/i40e_prototype.h"
59 #include "base/i40e_adminq_cmd.h"
60 #include "base/i40e_type.h"
61 #include "base/i40e_register.h"
62 #include "base/i40e_dcb.h"
63 #include "i40e_ethdev.h"
64 #include "i40e_rxtx.h"
66 #include "i40e_regs.h"
67 #include "rte_pmd_i40e.h"
69 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
70 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
72 #define I40E_CLEAR_PXE_WAIT_MS 200
74 /* Maximun number of capability elements */
75 #define I40E_MAX_CAP_ELE_NUM 128
77 /* Wait count and inteval */
78 #define I40E_CHK_Q_ENA_COUNT 1000
79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
81 /* Maximun number of VSI */
82 #define I40E_MAX_NUM_VSIS (384UL)
84 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
86 /* Flow control default timer */
87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
89 /* Flow control default high water */
90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
92 /* Flow control default low water */
93 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
95 /* Flow control enable fwd bit */
96 #define I40E_PRTMAC_FWD_CTRL 0x00000001
98 /* Receive Packet Buffer size */
99 #define I40E_RXPBSIZE (968 * 1024)
101 /* Kilobytes shift */
102 #define I40E_KILOSHIFT 10
104 /* Receive Average Packet Size in Byte*/
105 #define I40E_PACKET_AVERAGE_SIZE 128
107 /* Mask of PF interrupt causes */
108 #define I40E_PFINT_ICR0_ENA_MASK ( \
109 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
110 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
111 I40E_PFINT_ICR0_ENA_GRST_MASK | \
112 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
113 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
114 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
115 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
116 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
117 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
119 #define I40E_FLOW_TYPES ( \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
125 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
130 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
132 /* Additional timesync values. */
133 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
134 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
135 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
136 #define I40E_PRTTSYN_TSYNENA 0x80000000
137 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
138 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
140 #define I40E_MAX_PERCENT 100
141 #define I40E_DEFAULT_DCB_APP_NUM 1
142 #define I40E_DEFAULT_DCB_APP_PRIO 3
145 * Below are values for writing un-exposed registers suggested
148 /* Destination MAC address */
149 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
150 /* Source MAC address */
151 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
153 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
155 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
156 /* Single VLAN tag in the inner L2 header */
157 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
158 /* Source IPv4 address */
159 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
160 /* Destination IPv4 address */
161 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
162 /* Source IPv4 address for X722 */
163 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
164 /* Destination IPv4 address for X722 */
165 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
166 /* IPv4 Protocol for X722 */
167 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
168 /* IPv4 Time to Live for X722 */
169 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
170 /* IPv4 Type of Service (TOS) */
171 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
173 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
174 /* IPv4 Time to Live */
175 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
176 /* Source IPv6 address */
177 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
178 /* Destination IPv6 address */
179 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
180 /* IPv6 Traffic Class (TC) */
181 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
182 /* IPv6 Next Header */
183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
187 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
188 /* Destination L4 port */
189 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
190 /* SCTP verification tag */
191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
194 /* Source port of tunneling UDP */
195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
196 /* Destination port of tunneling UDP */
197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
198 /* UDP Tunneling ID, NVGRE/GRE key */
199 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
200 /* Last ether type */
201 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
202 /* Tunneling outer destination IPv4 address */
203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
204 /* Tunneling outer destination IPv6 address */
205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
206 /* 1st word of flex payload */
207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
208 /* 2nd word of flex payload */
209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
210 /* 3rd word of flex payload */
211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
212 /* 4th word of flex payload */
213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
214 /* 5th word of flex payload */
215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
216 /* 6th word of flex payload */
217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
218 /* 7th word of flex payload */
219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
220 /* 8th word of flex payload */
221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
222 /* all 8 words flex payload */
223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
224 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
226 #define I40E_TRANSLATE_INSET 0
227 #define I40E_TRANSLATE_REG 1
229 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
230 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
231 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
232 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
234 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
236 /* PCI offset for querying capability */
237 #define PCI_DEV_CAP_REG 0xA4
238 /* PCI offset for enabling/disabling Extended Tag */
239 #define PCI_DEV_CTRL_REG 0xA8
240 /* Bit mask of Extended Tag capability */
241 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
242 /* Bit shift of Extended Tag enable/disable */
243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
244 /* Bit mask of Extended Tag enable/disable */
245 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
247 /* The max bandwidth of i40e is 40Gbps. */
248 #define I40E_QOS_BW_MAX 40000
249 /* The bandwidth should be the multiple of 50Mbps. */
250 #define I40E_QOS_BW_GRANULARITY 50
251 /* The min bandwidth weight is 1. */
252 #define I40E_QOS_BW_WEIGHT_MIN 1
253 /* The max bandwidth weight is 127. */
254 #define I40E_QOS_BW_WEIGHT_MAX 127
256 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
257 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
258 static int i40e_dev_configure(struct rte_eth_dev *dev);
259 static int i40e_dev_start(struct rte_eth_dev *dev);
260 static void i40e_dev_stop(struct rte_eth_dev *dev);
261 static void i40e_dev_close(struct rte_eth_dev *dev);
262 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
263 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
264 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
265 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
266 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
267 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
268 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
269 struct rte_eth_stats *stats);
270 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
271 struct rte_eth_xstat *xstats, unsigned n);
272 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
273 struct rte_eth_xstat_name *xstats_names,
275 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
276 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
280 static int i40e_fw_version_get(struct rte_eth_dev *dev,
281 char *fw_version, size_t fw_size);
282 static void i40e_dev_info_get(struct rte_eth_dev *dev,
283 struct rte_eth_dev_info *dev_info);
284 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
287 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
288 enum rte_vlan_type vlan_type,
290 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
291 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
294 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
295 static int i40e_dev_led_on(struct rte_eth_dev *dev);
296 static int i40e_dev_led_off(struct rte_eth_dev *dev);
297 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
298 struct rte_eth_fc_conf *fc_conf);
299 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
300 struct rte_eth_fc_conf *fc_conf);
301 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
302 struct rte_eth_pfc_conf *pfc_conf);
303 static void i40e_macaddr_add(struct rte_eth_dev *dev,
304 struct ether_addr *mac_addr,
307 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
308 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
309 struct rte_eth_rss_reta_entry64 *reta_conf,
311 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
312 struct rte_eth_rss_reta_entry64 *reta_conf,
315 static int i40e_get_cap(struct i40e_hw *hw);
316 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
317 static int i40e_pf_setup(struct i40e_pf *pf);
318 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
319 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
320 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
321 static int i40e_dcb_setup(struct rte_eth_dev *dev);
322 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
323 bool offset_loaded, uint64_t *offset, uint64_t *stat);
324 static void i40e_stat_update_48(struct i40e_hw *hw,
330 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
331 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
333 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
334 uint32_t base, uint32_t num);
335 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
336 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
338 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
340 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
341 static int i40e_veb_release(struct i40e_veb *veb);
342 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
343 struct i40e_vsi *vsi);
344 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
345 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
346 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
347 struct i40e_macvlan_filter *mv_f,
349 struct ether_addr *addr);
350 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
351 struct i40e_macvlan_filter *mv_f,
354 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
355 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
356 struct rte_eth_rss_conf *rss_conf);
357 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
358 struct rte_eth_rss_conf *rss_conf);
359 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
360 struct rte_eth_udp_tunnel *udp_tunnel);
361 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
362 struct rte_eth_udp_tunnel *udp_tunnel);
363 static void i40e_filter_input_set_init(struct i40e_pf *pf);
364 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
365 enum rte_filter_op filter_op,
367 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
368 enum rte_filter_type filter_type,
369 enum rte_filter_op filter_op,
371 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
372 struct rte_eth_dcb_info *dcb_info);
373 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
374 static void i40e_configure_registers(struct i40e_hw *hw);
375 static void i40e_hw_init(struct rte_eth_dev *dev);
376 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
377 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
378 struct rte_eth_mirror_conf *mirror_conf,
379 uint8_t sw_id, uint8_t on);
380 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
382 static int i40e_timesync_enable(struct rte_eth_dev *dev);
383 static int i40e_timesync_disable(struct rte_eth_dev *dev);
384 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
385 struct timespec *timestamp,
387 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
388 struct timespec *timestamp);
389 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
391 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
393 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
394 struct timespec *timestamp);
395 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
396 const struct timespec *timestamp);
398 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
400 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
403 static int i40e_get_regs(struct rte_eth_dev *dev,
404 struct rte_dev_reg_info *regs);
406 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
408 static int i40e_get_eeprom(struct rte_eth_dev *dev,
409 struct rte_dev_eeprom_info *eeprom);
411 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
412 struct ether_addr *mac_addr);
414 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
416 static int i40e_ethertype_filter_convert(
417 const struct rte_eth_ethertype_filter *input,
418 struct i40e_ethertype_filter *filter);
419 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
420 struct i40e_ethertype_filter *filter);
422 static int i40e_tunnel_filter_convert(
423 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
424 struct i40e_tunnel_filter *tunnel_filter);
425 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
426 struct i40e_tunnel_filter *tunnel_filter);
427 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
429 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
430 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
431 static void i40e_filter_restore(struct i40e_pf *pf);
433 int i40e_logtype_init;
434 int i40e_logtype_driver;
436 static const struct rte_pci_id pci_id_i40e_map[] = {
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
446 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
447 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
448 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
449 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
450 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
451 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
452 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
453 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
454 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
455 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
456 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
457 { .vendor_id = 0, /* sentinel */ },
460 static const struct eth_dev_ops i40e_eth_dev_ops = {
461 .dev_configure = i40e_dev_configure,
462 .dev_start = i40e_dev_start,
463 .dev_stop = i40e_dev_stop,
464 .dev_close = i40e_dev_close,
465 .promiscuous_enable = i40e_dev_promiscuous_enable,
466 .promiscuous_disable = i40e_dev_promiscuous_disable,
467 .allmulticast_enable = i40e_dev_allmulticast_enable,
468 .allmulticast_disable = i40e_dev_allmulticast_disable,
469 .dev_set_link_up = i40e_dev_set_link_up,
470 .dev_set_link_down = i40e_dev_set_link_down,
471 .link_update = i40e_dev_link_update,
472 .stats_get = i40e_dev_stats_get,
473 .xstats_get = i40e_dev_xstats_get,
474 .xstats_get_names = i40e_dev_xstats_get_names,
475 .stats_reset = i40e_dev_stats_reset,
476 .xstats_reset = i40e_dev_stats_reset,
477 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
478 .fw_version_get = i40e_fw_version_get,
479 .dev_infos_get = i40e_dev_info_get,
480 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
481 .vlan_filter_set = i40e_vlan_filter_set,
482 .vlan_tpid_set = i40e_vlan_tpid_set,
483 .vlan_offload_set = i40e_vlan_offload_set,
484 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
485 .vlan_pvid_set = i40e_vlan_pvid_set,
486 .rx_queue_start = i40e_dev_rx_queue_start,
487 .rx_queue_stop = i40e_dev_rx_queue_stop,
488 .tx_queue_start = i40e_dev_tx_queue_start,
489 .tx_queue_stop = i40e_dev_tx_queue_stop,
490 .rx_queue_setup = i40e_dev_rx_queue_setup,
491 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
492 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
493 .rx_queue_release = i40e_dev_rx_queue_release,
494 .rx_queue_count = i40e_dev_rx_queue_count,
495 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
496 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
497 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
498 .tx_queue_setup = i40e_dev_tx_queue_setup,
499 .tx_queue_release = i40e_dev_tx_queue_release,
500 .dev_led_on = i40e_dev_led_on,
501 .dev_led_off = i40e_dev_led_off,
502 .flow_ctrl_get = i40e_flow_ctrl_get,
503 .flow_ctrl_set = i40e_flow_ctrl_set,
504 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
505 .mac_addr_add = i40e_macaddr_add,
506 .mac_addr_remove = i40e_macaddr_remove,
507 .reta_update = i40e_dev_rss_reta_update,
508 .reta_query = i40e_dev_rss_reta_query,
509 .rss_hash_update = i40e_dev_rss_hash_update,
510 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
511 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
512 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
513 .filter_ctrl = i40e_dev_filter_ctrl,
514 .rxq_info_get = i40e_rxq_info_get,
515 .txq_info_get = i40e_txq_info_get,
516 .mirror_rule_set = i40e_mirror_rule_set,
517 .mirror_rule_reset = i40e_mirror_rule_reset,
518 .timesync_enable = i40e_timesync_enable,
519 .timesync_disable = i40e_timesync_disable,
520 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
521 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
522 .get_dcb_info = i40e_dev_get_dcb_info,
523 .timesync_adjust_time = i40e_timesync_adjust_time,
524 .timesync_read_time = i40e_timesync_read_time,
525 .timesync_write_time = i40e_timesync_write_time,
526 .get_reg = i40e_get_regs,
527 .get_eeprom_length = i40e_get_eeprom_length,
528 .get_eeprom = i40e_get_eeprom,
529 .mac_addr_set = i40e_set_default_mac_addr,
530 .mtu_set = i40e_dev_mtu_set,
533 /* store statistics names and its offset in stats structure */
534 struct rte_i40e_xstats_name_off {
535 char name[RTE_ETH_XSTATS_NAME_SIZE];
539 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
540 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
541 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
542 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
543 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
544 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
545 rx_unknown_protocol)},
546 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
547 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
548 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
549 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
552 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
553 sizeof(rte_i40e_stats_strings[0]))
555 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
556 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
557 tx_dropped_link_down)},
558 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
559 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
561 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
562 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
564 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
566 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
568 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
569 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
570 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
571 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
572 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
573 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
575 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
577 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
579 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
581 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
583 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
585 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
587 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
589 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
590 mac_short_packet_dropped)},
591 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
593 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
594 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
595 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
597 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
599 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
601 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
603 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
605 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
607 {"rx_flow_director_atr_match_packets",
608 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
609 {"rx_flow_director_sb_match_packets",
610 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
611 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
613 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
615 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
617 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
621 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
622 sizeof(rte_i40e_hw_port_strings[0]))
624 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
625 {"xon_packets", offsetof(struct i40e_hw_port_stats,
627 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
631 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
632 sizeof(rte_i40e_rxq_prio_strings[0]))
634 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
635 {"xon_packets", offsetof(struct i40e_hw_port_stats,
637 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
639 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
640 priority_xon_2_xoff)},
643 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
644 sizeof(rte_i40e_txq_prio_strings[0]))
646 static struct eth_driver rte_i40e_pmd = {
648 .id_table = pci_id_i40e_map,
649 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
650 .probe = rte_eth_dev_pci_probe,
651 .remove = rte_eth_dev_pci_remove,
653 .eth_dev_init = eth_i40e_dev_init,
654 .eth_dev_uninit = eth_i40e_dev_uninit,
655 .dev_private_size = sizeof(struct i40e_adapter),
659 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
660 struct rte_eth_link *link)
662 struct rte_eth_link *dst = link;
663 struct rte_eth_link *src = &(dev->data->dev_link);
665 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
666 *(uint64_t *)src) == 0)
673 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
674 struct rte_eth_link *link)
676 struct rte_eth_link *dst = &(dev->data->dev_link);
677 struct rte_eth_link *src = link;
679 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
680 *(uint64_t *)src) == 0)
686 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
687 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
688 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
690 #ifndef I40E_GLQF_ORT
691 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
693 #ifndef I40E_GLQF_PIT
694 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
696 #ifndef I40E_GLQF_L3_MAP
697 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
700 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
703 * Initialize registers for flexible payload, which should be set by NVM.
704 * This should be removed from code once it is fixed in NVM.
706 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
707 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
708 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
709 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
710 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
711 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
712 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
713 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
714 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
715 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
716 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
717 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
719 /* Initialize registers for parsing packet type of QinQ */
720 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
721 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
724 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
727 * Add a ethertype filter to drop all flow control frames transmitted
731 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
733 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
734 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
735 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
736 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
739 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
740 I40E_FLOW_CONTROL_ETHERTYPE, flags,
741 pf->main_vsi_seid, 0,
745 "Failed to add filter to drop flow control frames from VSIs.");
749 floating_veb_list_handler(__rte_unused const char *key,
750 const char *floating_veb_value,
754 unsigned int count = 0;
757 bool *vf_floating_veb = opaque;
759 while (isblank(*floating_veb_value))
760 floating_veb_value++;
762 /* Reset floating VEB configuration for VFs */
763 for (idx = 0; idx < I40E_MAX_VF; idx++)
764 vf_floating_veb[idx] = false;
768 while (isblank(*floating_veb_value))
769 floating_veb_value++;
770 if (*floating_veb_value == '\0')
773 idx = strtoul(floating_veb_value, &end, 10);
774 if (errno || end == NULL)
776 while (isblank(*end))
780 } else if ((*end == ';') || (*end == '\0')) {
782 if (min == I40E_MAX_VF)
784 if (max >= I40E_MAX_VF)
785 max = I40E_MAX_VF - 1;
786 for (idx = min; idx <= max; idx++) {
787 vf_floating_veb[idx] = true;
794 floating_veb_value = end + 1;
795 } while (*end != '\0');
804 config_vf_floating_veb(struct rte_devargs *devargs,
805 uint16_t floating_veb,
806 bool *vf_floating_veb)
808 struct rte_kvargs *kvlist;
810 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
814 /* All the VFs attach to the floating VEB by default
815 * when the floating VEB is enabled.
817 for (i = 0; i < I40E_MAX_VF; i++)
818 vf_floating_veb[i] = true;
823 kvlist = rte_kvargs_parse(devargs->args, NULL);
827 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
828 rte_kvargs_free(kvlist);
831 /* When the floating_veb_list parameter exists, all the VFs
832 * will attach to the legacy VEB firstly, then configure VFs
833 * to the floating VEB according to the floating_veb_list.
835 if (rte_kvargs_process(kvlist, floating_veb_list,
836 floating_veb_list_handler,
837 vf_floating_veb) < 0) {
838 rte_kvargs_free(kvlist);
841 rte_kvargs_free(kvlist);
845 i40e_check_floating_handler(__rte_unused const char *key,
847 __rte_unused void *opaque)
849 if (strcmp(value, "1"))
856 is_floating_veb_supported(struct rte_devargs *devargs)
858 struct rte_kvargs *kvlist;
859 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
864 kvlist = rte_kvargs_parse(devargs->args, NULL);
868 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
869 rte_kvargs_free(kvlist);
872 /* Floating VEB is enabled when there's key-value:
873 * enable_floating_veb=1
875 if (rte_kvargs_process(kvlist, floating_veb_key,
876 i40e_check_floating_handler, NULL) < 0) {
877 rte_kvargs_free(kvlist);
880 rte_kvargs_free(kvlist);
886 config_floating_veb(struct rte_eth_dev *dev)
888 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
889 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
890 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
892 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
894 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
896 is_floating_veb_supported(pci_dev->device.devargs);
897 config_vf_floating_veb(pci_dev->device.devargs,
899 pf->floating_veb_list);
901 pf->floating_veb = false;
905 #define I40E_L2_TAGS_S_TAG_SHIFT 1
906 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
909 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
911 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
912 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
913 char ethertype_hash_name[RTE_HASH_NAMESIZE];
916 struct rte_hash_parameters ethertype_hash_params = {
917 .name = ethertype_hash_name,
918 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
919 .key_len = sizeof(struct i40e_ethertype_filter_input),
920 .hash_func = rte_hash_crc,
921 .hash_func_init_val = 0,
922 .socket_id = rte_socket_id(),
925 /* Initialize ethertype filter rule list and hash */
926 TAILQ_INIT(ðertype_rule->ethertype_list);
927 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
928 "ethertype_%s", dev->data->name);
929 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
930 if (!ethertype_rule->hash_table) {
931 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
934 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
935 sizeof(struct i40e_ethertype_filter *) *
936 I40E_MAX_ETHERTYPE_FILTER_NUM,
938 if (!ethertype_rule->hash_map) {
940 "Failed to allocate memory for ethertype hash map!");
942 goto err_ethertype_hash_map_alloc;
947 err_ethertype_hash_map_alloc:
948 rte_hash_free(ethertype_rule->hash_table);
954 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
956 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
957 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
958 char tunnel_hash_name[RTE_HASH_NAMESIZE];
961 struct rte_hash_parameters tunnel_hash_params = {
962 .name = tunnel_hash_name,
963 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
964 .key_len = sizeof(struct i40e_tunnel_filter_input),
965 .hash_func = rte_hash_crc,
966 .hash_func_init_val = 0,
967 .socket_id = rte_socket_id(),
970 /* Initialize tunnel filter rule list and hash */
971 TAILQ_INIT(&tunnel_rule->tunnel_list);
972 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
973 "tunnel_%s", dev->data->name);
974 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
975 if (!tunnel_rule->hash_table) {
976 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
979 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
980 sizeof(struct i40e_tunnel_filter *) *
981 I40E_MAX_TUNNEL_FILTER_NUM,
983 if (!tunnel_rule->hash_map) {
985 "Failed to allocate memory for tunnel hash map!");
987 goto err_tunnel_hash_map_alloc;
992 err_tunnel_hash_map_alloc:
993 rte_hash_free(tunnel_rule->hash_table);
999 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1001 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1002 struct i40e_fdir_info *fdir_info = &pf->fdir;
1003 char fdir_hash_name[RTE_HASH_NAMESIZE];
1006 struct rte_hash_parameters fdir_hash_params = {
1007 .name = fdir_hash_name,
1008 .entries = I40E_MAX_FDIR_FILTER_NUM,
1009 .key_len = sizeof(struct rte_eth_fdir_input),
1010 .hash_func = rte_hash_crc,
1011 .hash_func_init_val = 0,
1012 .socket_id = rte_socket_id(),
1015 /* Initialize flow director filter rule list and hash */
1016 TAILQ_INIT(&fdir_info->fdir_list);
1017 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1018 "fdir_%s", dev->data->name);
1019 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1020 if (!fdir_info->hash_table) {
1021 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1024 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1025 sizeof(struct i40e_fdir_filter *) *
1026 I40E_MAX_FDIR_FILTER_NUM,
1028 if (!fdir_info->hash_map) {
1030 "Failed to allocate memory for fdir hash map!");
1032 goto err_fdir_hash_map_alloc;
1036 err_fdir_hash_map_alloc:
1037 rte_hash_free(fdir_info->hash_table);
1043 eth_i40e_dev_init(struct rte_eth_dev *dev)
1045 struct rte_pci_device *pci_dev;
1046 struct rte_intr_handle *intr_handle;
1047 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1048 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1049 struct i40e_vsi *vsi;
1052 uint8_t aq_fail = 0;
1054 PMD_INIT_FUNC_TRACE();
1056 dev->dev_ops = &i40e_eth_dev_ops;
1057 dev->rx_pkt_burst = i40e_recv_pkts;
1058 dev->tx_pkt_burst = i40e_xmit_pkts;
1059 dev->tx_pkt_prepare = i40e_prep_pkts;
1061 /* for secondary processes, we don't initialise any further as primary
1062 * has already done this work. Only check we don't need a different
1064 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1065 i40e_set_rx_function(dev);
1066 i40e_set_tx_function(dev);
1069 pci_dev = I40E_DEV_TO_PCI(dev);
1070 intr_handle = &pci_dev->intr_handle;
1072 rte_eth_copy_pci_info(dev, pci_dev);
1073 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1075 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1076 pf->adapter->eth_dev = dev;
1077 pf->dev_data = dev->data;
1079 hw->back = I40E_PF_TO_ADAPTER(pf);
1080 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1083 "Hardware is not available, as address is NULL");
1087 hw->vendor_id = pci_dev->id.vendor_id;
1088 hw->device_id = pci_dev->id.device_id;
1089 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1090 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1091 hw->bus.device = pci_dev->addr.devid;
1092 hw->bus.func = pci_dev->addr.function;
1093 hw->adapter_stopped = 0;
1095 /* Make sure all is clean before doing PF reset */
1098 /* Initialize the hardware */
1101 /* Reset here to make sure all is clean for each PF */
1102 ret = i40e_pf_reset(hw);
1104 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1108 /* Initialize the shared code (base driver) */
1109 ret = i40e_init_shared_code(hw);
1111 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1116 * To work around the NVM issue, initialize registers
1117 * for flexible payload and packet type of QinQ by
1118 * software. It should be removed once issues are fixed
1121 i40e_GLQF_reg_init(hw);
1123 /* Initialize the input set for filters (hash and fd) to default value */
1124 i40e_filter_input_set_init(pf);
1126 /* Initialize the parameters for adminq */
1127 i40e_init_adminq_parameter(hw);
1128 ret = i40e_init_adminq(hw);
1129 if (ret != I40E_SUCCESS) {
1130 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1133 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1134 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1135 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1136 ((hw->nvm.version >> 12) & 0xf),
1137 ((hw->nvm.version >> 4) & 0xff),
1138 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1140 /* initialise the L3_MAP register */
1141 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1144 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1146 /* Need the special FW version to support floating VEB */
1147 config_floating_veb(dev);
1148 /* Clear PXE mode */
1149 i40e_clear_pxe_mode(hw);
1150 ret = i40e_dev_sync_phy_type(hw);
1152 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1153 goto err_sync_phy_type;
1156 * On X710, performance number is far from the expectation on recent
1157 * firmware versions. The fix for this issue may not be integrated in
1158 * the following firmware version. So the workaround in software driver
1159 * is needed. It needs to modify the initial values of 3 internal only
1160 * registers. Note that the workaround can be removed when it is fixed
1161 * in firmware in the future.
1163 i40e_configure_registers(hw);
1165 /* Get hw capabilities */
1166 ret = i40e_get_cap(hw);
1167 if (ret != I40E_SUCCESS) {
1168 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1169 goto err_get_capabilities;
1172 /* Initialize parameters for PF */
1173 ret = i40e_pf_parameter_init(dev);
1175 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1176 goto err_parameter_init;
1179 /* Initialize the queue management */
1180 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1182 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1183 goto err_qp_pool_init;
1185 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1186 hw->func_caps.num_msix_vectors - 1);
1188 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1189 goto err_msix_pool_init;
1192 /* Initialize lan hmc */
1193 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1194 hw->func_caps.num_rx_qp, 0, 0);
1195 if (ret != I40E_SUCCESS) {
1196 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1197 goto err_init_lan_hmc;
1200 /* Configure lan hmc */
1201 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1202 if (ret != I40E_SUCCESS) {
1203 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1204 goto err_configure_lan_hmc;
1207 /* Get and check the mac address */
1208 i40e_get_mac_addr(hw, hw->mac.addr);
1209 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1210 PMD_INIT_LOG(ERR, "mac address is not valid");
1212 goto err_get_mac_addr;
1214 /* Copy the permanent MAC address */
1215 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1216 (struct ether_addr *) hw->mac.perm_addr);
1218 /* Disable flow control */
1219 hw->fc.requested_mode = I40E_FC_NONE;
1220 i40e_set_fc(hw, &aq_fail, TRUE);
1222 /* Set the global registers with default ether type value */
1223 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1224 if (ret != I40E_SUCCESS) {
1226 "Failed to set the default outer VLAN ether type");
1227 goto err_setup_pf_switch;
1230 /* PF setup, which includes VSI setup */
1231 ret = i40e_pf_setup(pf);
1233 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1234 goto err_setup_pf_switch;
1237 /* reset all stats of the device, including pf and main vsi */
1238 i40e_dev_stats_reset(dev);
1242 /* Disable double vlan by default */
1243 i40e_vsi_config_double_vlan(vsi, FALSE);
1245 /* Disable S-TAG identification when floating_veb is disabled */
1246 if (!pf->floating_veb) {
1247 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1248 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1249 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1250 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1254 if (!vsi->max_macaddrs)
1255 len = ETHER_ADDR_LEN;
1257 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1259 /* Should be after VSI initialized */
1260 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1261 if (!dev->data->mac_addrs) {
1263 "Failed to allocated memory for storing mac address");
1266 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1267 &dev->data->mac_addrs[0]);
1269 /* Init dcb to sw mode by default */
1270 ret = i40e_dcb_init_configure(dev, TRUE);
1271 if (ret != I40E_SUCCESS) {
1272 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1273 pf->flags &= ~I40E_FLAG_DCB;
1275 /* Update HW struct after DCB configuration */
1278 /* initialize pf host driver to setup SRIOV resource if applicable */
1279 i40e_pf_host_init(dev);
1281 /* register callback func to eal lib */
1282 rte_intr_callback_register(intr_handle,
1283 i40e_dev_interrupt_handler, dev);
1285 /* configure and enable device interrupt */
1286 i40e_pf_config_irq0(hw, TRUE);
1287 i40e_pf_enable_irq0(hw);
1289 /* enable uio intr after callback register */
1290 rte_intr_enable(intr_handle);
1292 * Add an ethertype filter to drop all flow control frames transmitted
1293 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1296 i40e_add_tx_flow_control_drop_filter(pf);
1298 /* Set the max frame size to 0x2600 by default,
1299 * in case other drivers changed the default value.
1301 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1303 /* initialize mirror rule list */
1304 TAILQ_INIT(&pf->mirror_list);
1306 ret = i40e_init_ethtype_filter_list(dev);
1308 goto err_init_ethtype_filter_list;
1309 ret = i40e_init_tunnel_filter_list(dev);
1311 goto err_init_tunnel_filter_list;
1312 ret = i40e_init_fdir_filter_list(dev);
1314 goto err_init_fdir_filter_list;
1318 err_init_fdir_filter_list:
1319 rte_free(pf->tunnel.hash_table);
1320 rte_free(pf->tunnel.hash_map);
1321 err_init_tunnel_filter_list:
1322 rte_free(pf->ethertype.hash_table);
1323 rte_free(pf->ethertype.hash_map);
1324 err_init_ethtype_filter_list:
1325 rte_free(dev->data->mac_addrs);
1327 i40e_vsi_release(pf->main_vsi);
1328 err_setup_pf_switch:
1330 err_configure_lan_hmc:
1331 (void)i40e_shutdown_lan_hmc(hw);
1333 i40e_res_pool_destroy(&pf->msix_pool);
1335 i40e_res_pool_destroy(&pf->qp_pool);
1338 err_get_capabilities:
1340 (void)i40e_shutdown_adminq(hw);
1346 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1348 struct i40e_ethertype_filter *p_ethertype;
1349 struct i40e_ethertype_rule *ethertype_rule;
1351 ethertype_rule = &pf->ethertype;
1352 /* Remove all ethertype filter rules and hash */
1353 if (ethertype_rule->hash_map)
1354 rte_free(ethertype_rule->hash_map);
1355 if (ethertype_rule->hash_table)
1356 rte_hash_free(ethertype_rule->hash_table);
1358 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1359 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1360 p_ethertype, rules);
1361 rte_free(p_ethertype);
1366 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1368 struct i40e_tunnel_filter *p_tunnel;
1369 struct i40e_tunnel_rule *tunnel_rule;
1371 tunnel_rule = &pf->tunnel;
1372 /* Remove all tunnel director rules and hash */
1373 if (tunnel_rule->hash_map)
1374 rte_free(tunnel_rule->hash_map);
1375 if (tunnel_rule->hash_table)
1376 rte_hash_free(tunnel_rule->hash_table);
1378 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1379 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1385 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1387 struct i40e_fdir_filter *p_fdir;
1388 struct i40e_fdir_info *fdir_info;
1390 fdir_info = &pf->fdir;
1391 /* Remove all flow director rules and hash */
1392 if (fdir_info->hash_map)
1393 rte_free(fdir_info->hash_map);
1394 if (fdir_info->hash_table)
1395 rte_hash_free(fdir_info->hash_table);
1397 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1398 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1404 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1407 struct rte_pci_device *pci_dev;
1408 struct rte_intr_handle *intr_handle;
1410 struct i40e_filter_control_settings settings;
1411 struct rte_flow *p_flow;
1413 uint8_t aq_fail = 0;
1415 PMD_INIT_FUNC_TRACE();
1417 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1420 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1421 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1422 pci_dev = I40E_DEV_TO_PCI(dev);
1423 intr_handle = &pci_dev->intr_handle;
1425 if (hw->adapter_stopped == 0)
1426 i40e_dev_close(dev);
1428 dev->dev_ops = NULL;
1429 dev->rx_pkt_burst = NULL;
1430 dev->tx_pkt_burst = NULL;
1432 /* Clear PXE mode */
1433 i40e_clear_pxe_mode(hw);
1435 /* Unconfigure filter control */
1436 memset(&settings, 0, sizeof(settings));
1437 ret = i40e_set_filter_control(hw, &settings);
1439 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1442 /* Disable flow control */
1443 hw->fc.requested_mode = I40E_FC_NONE;
1444 i40e_set_fc(hw, &aq_fail, TRUE);
1446 /* uninitialize pf host driver */
1447 i40e_pf_host_uninit(dev);
1449 rte_free(dev->data->mac_addrs);
1450 dev->data->mac_addrs = NULL;
1452 /* disable uio intr before callback unregister */
1453 rte_intr_disable(intr_handle);
1455 /* register callback func to eal lib */
1456 rte_intr_callback_unregister(intr_handle,
1457 i40e_dev_interrupt_handler, dev);
1459 i40e_rm_ethtype_filter_list(pf);
1460 i40e_rm_tunnel_filter_list(pf);
1461 i40e_rm_fdir_filter_list(pf);
1463 /* Remove all flows */
1464 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1465 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1473 i40e_dev_configure(struct rte_eth_dev *dev)
1475 struct i40e_adapter *ad =
1476 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1477 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1478 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1481 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1482 * bulk allocation or vector Rx preconditions we will reset it.
1484 ad->rx_bulk_alloc_allowed = true;
1485 ad->rx_vec_allowed = true;
1486 ad->tx_simple_allowed = true;
1487 ad->tx_vec_allowed = true;
1489 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1490 ret = i40e_fdir_setup(pf);
1491 if (ret != I40E_SUCCESS) {
1492 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1495 ret = i40e_fdir_configure(dev);
1497 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1501 i40e_fdir_teardown(pf);
1503 ret = i40e_dev_init_vlan(dev);
1508 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1509 * RSS setting have different requirements.
1510 * General PMD driver call sequence are NIC init, configure,
1511 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1512 * will try to lookup the VSI that specific queue belongs to if VMDQ
1513 * applicable. So, VMDQ setting has to be done before
1514 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1515 * For RSS setting, it will try to calculate actual configured RX queue
1516 * number, which will be available after rx_queue_setup(). dev_start()
1517 * function is good to place RSS setup.
1519 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1520 ret = i40e_vmdq_setup(dev);
1525 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1526 ret = i40e_dcb_setup(dev);
1528 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1533 TAILQ_INIT(&pf->flow_list);
1538 /* need to release vmdq resource if exists */
1539 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1540 i40e_vsi_release(pf->vmdq[i].vsi);
1541 pf->vmdq[i].vsi = NULL;
1546 /* need to release fdir resource if exists */
1547 i40e_fdir_teardown(pf);
1552 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1554 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1555 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1556 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1557 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1558 uint16_t msix_vect = vsi->msix_intr;
1561 for (i = 0; i < vsi->nb_qps; i++) {
1562 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1563 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1567 if (vsi->type != I40E_VSI_SRIOV) {
1568 if (!rte_intr_allow_others(intr_handle)) {
1569 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1570 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1572 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1575 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1576 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1578 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1583 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1584 vsi->user_param + (msix_vect - 1);
1586 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1587 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1589 I40E_WRITE_FLUSH(hw);
1593 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1594 int base_queue, int nb_queue)
1598 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1600 /* Bind all RX queues to allocated MSIX interrupt */
1601 for (i = 0; i < nb_queue; i++) {
1602 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1603 I40E_QINT_RQCTL_ITR_INDX_MASK |
1604 ((base_queue + i + 1) <<
1605 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1606 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1607 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1609 if (i == nb_queue - 1)
1610 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1611 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1614 /* Write first RX queue to Link list register as the head element */
1615 if (vsi->type != I40E_VSI_SRIOV) {
1617 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1619 if (msix_vect == I40E_MISC_VEC_ID) {
1620 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1622 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1624 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1626 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1629 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1631 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1633 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1635 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1642 if (msix_vect == I40E_MISC_VEC_ID) {
1644 I40E_VPINT_LNKLST0(vsi->user_param),
1646 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1648 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1650 /* num_msix_vectors_vf needs to minus irq0 */
1651 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1652 vsi->user_param + (msix_vect - 1);
1654 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1656 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1658 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1662 I40E_WRITE_FLUSH(hw);
1666 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1668 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1669 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1670 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1671 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1672 uint16_t msix_vect = vsi->msix_intr;
1673 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1674 uint16_t queue_idx = 0;
1679 for (i = 0; i < vsi->nb_qps; i++) {
1680 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1681 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1684 /* INTENA flag is not auto-cleared for interrupt */
1685 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1686 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1687 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1688 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1689 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1691 /* VF bind interrupt */
1692 if (vsi->type == I40E_VSI_SRIOV) {
1693 __vsi_queues_bind_intr(vsi, msix_vect,
1694 vsi->base_queue, vsi->nb_qps);
1698 /* PF & VMDq bind interrupt */
1699 if (rte_intr_dp_is_en(intr_handle)) {
1700 if (vsi->type == I40E_VSI_MAIN) {
1703 } else if (vsi->type == I40E_VSI_VMDQ2) {
1704 struct i40e_vsi *main_vsi =
1705 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1706 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1711 for (i = 0; i < vsi->nb_used_qps; i++) {
1713 if (!rte_intr_allow_others(intr_handle))
1714 /* allow to share MISC_VEC_ID */
1715 msix_vect = I40E_MISC_VEC_ID;
1717 /* no enough msix_vect, map all to one */
1718 __vsi_queues_bind_intr(vsi, msix_vect,
1719 vsi->base_queue + i,
1720 vsi->nb_used_qps - i);
1721 for (; !!record && i < vsi->nb_used_qps; i++)
1722 intr_handle->intr_vec[queue_idx + i] =
1726 /* 1:1 queue/msix_vect mapping */
1727 __vsi_queues_bind_intr(vsi, msix_vect,
1728 vsi->base_queue + i, 1);
1730 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1738 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1740 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1741 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1742 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1743 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1744 uint16_t interval = i40e_calc_itr_interval(\
1745 RTE_LIBRTE_I40E_ITR_INTERVAL);
1746 uint16_t msix_intr, i;
1748 if (rte_intr_allow_others(intr_handle))
1749 for (i = 0; i < vsi->nb_msix; i++) {
1750 msix_intr = vsi->msix_intr + i;
1751 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1752 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1753 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1754 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1756 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1759 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1760 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1761 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1762 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1764 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1766 I40E_WRITE_FLUSH(hw);
1770 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1772 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1773 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1774 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1775 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1776 uint16_t msix_intr, i;
1778 if (rte_intr_allow_others(intr_handle))
1779 for (i = 0; i < vsi->nb_msix; i++) {
1780 msix_intr = vsi->msix_intr + i;
1781 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1785 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1787 I40E_WRITE_FLUSH(hw);
1790 static inline uint8_t
1791 i40e_parse_link_speeds(uint16_t link_speeds)
1793 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1795 if (link_speeds & ETH_LINK_SPEED_40G)
1796 link_speed |= I40E_LINK_SPEED_40GB;
1797 if (link_speeds & ETH_LINK_SPEED_25G)
1798 link_speed |= I40E_LINK_SPEED_25GB;
1799 if (link_speeds & ETH_LINK_SPEED_20G)
1800 link_speed |= I40E_LINK_SPEED_20GB;
1801 if (link_speeds & ETH_LINK_SPEED_10G)
1802 link_speed |= I40E_LINK_SPEED_10GB;
1803 if (link_speeds & ETH_LINK_SPEED_1G)
1804 link_speed |= I40E_LINK_SPEED_1GB;
1805 if (link_speeds & ETH_LINK_SPEED_100M)
1806 link_speed |= I40E_LINK_SPEED_100MB;
1812 i40e_phy_conf_link(struct i40e_hw *hw,
1814 uint8_t force_speed)
1816 enum i40e_status_code status;
1817 struct i40e_aq_get_phy_abilities_resp phy_ab;
1818 struct i40e_aq_set_phy_config phy_conf;
1819 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1820 I40E_AQ_PHY_FLAG_PAUSE_RX |
1821 I40E_AQ_PHY_FLAG_PAUSE_RX |
1822 I40E_AQ_PHY_FLAG_LOW_POWER;
1823 const uint8_t advt = I40E_LINK_SPEED_40GB |
1824 I40E_LINK_SPEED_25GB |
1825 I40E_LINK_SPEED_10GB |
1826 I40E_LINK_SPEED_1GB |
1827 I40E_LINK_SPEED_100MB;
1831 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1836 memset(&phy_conf, 0, sizeof(phy_conf));
1838 /* bits 0-2 use the values from get_phy_abilities_resp */
1840 abilities |= phy_ab.abilities & mask;
1842 /* update ablities and speed */
1843 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1844 phy_conf.link_speed = advt;
1846 phy_conf.link_speed = force_speed;
1848 phy_conf.abilities = abilities;
1850 /* use get_phy_abilities_resp value for the rest */
1851 phy_conf.phy_type = phy_ab.phy_type;
1852 phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1853 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1854 phy_conf.eee_capability = phy_ab.eee_capability;
1855 phy_conf.eeer = phy_ab.eeer_val;
1856 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1858 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1859 phy_ab.abilities, phy_ab.link_speed);
1860 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1861 phy_conf.abilities, phy_conf.link_speed);
1863 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1867 return I40E_SUCCESS;
1871 i40e_apply_link_speed(struct rte_eth_dev *dev)
1874 uint8_t abilities = 0;
1875 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1876 struct rte_eth_conf *conf = &dev->data->dev_conf;
1878 speed = i40e_parse_link_speeds(conf->link_speeds);
1879 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1880 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1881 abilities |= I40E_AQ_PHY_AN_ENABLED;
1882 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1884 /* Skip changing speed on 40G interfaces, FW does not support */
1885 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1886 speed = I40E_LINK_SPEED_UNKNOWN;
1887 abilities |= I40E_AQ_PHY_AN_ENABLED;
1890 return i40e_phy_conf_link(hw, abilities, speed);
1894 i40e_dev_start(struct rte_eth_dev *dev)
1896 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1897 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1898 struct i40e_vsi *main_vsi = pf->main_vsi;
1900 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1901 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1902 uint32_t intr_vector = 0;
1903 struct i40e_vsi *vsi;
1905 hw->adapter_stopped = 0;
1907 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1908 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1909 dev->data->port_id);
1913 rte_intr_disable(intr_handle);
1915 if ((rte_intr_cap_multiple(intr_handle) ||
1916 !RTE_ETH_DEV_SRIOV(dev).active) &&
1917 dev->data->dev_conf.intr_conf.rxq != 0) {
1918 intr_vector = dev->data->nb_rx_queues;
1919 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1924 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1925 intr_handle->intr_vec =
1926 rte_zmalloc("intr_vec",
1927 dev->data->nb_rx_queues * sizeof(int),
1929 if (!intr_handle->intr_vec) {
1931 "Failed to allocate %d rx_queues intr_vec",
1932 dev->data->nb_rx_queues);
1937 /* Initialize VSI */
1938 ret = i40e_dev_rxtx_init(pf);
1939 if (ret != I40E_SUCCESS) {
1940 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1944 /* Map queues with MSIX interrupt */
1945 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1946 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1947 i40e_vsi_queues_bind_intr(main_vsi);
1948 i40e_vsi_enable_queues_intr(main_vsi);
1950 /* Map VMDQ VSI queues with MSIX interrupt */
1951 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1952 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1953 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1954 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1957 /* enable FDIR MSIX interrupt */
1958 if (pf->fdir.fdir_vsi) {
1959 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1960 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1963 /* Enable all queues which have been configured */
1964 ret = i40e_dev_switch_queues(pf, TRUE);
1965 if (ret != I40E_SUCCESS) {
1966 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1970 /* Enable receiving broadcast packets */
1971 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1972 if (ret != I40E_SUCCESS)
1973 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1975 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1976 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1978 if (ret != I40E_SUCCESS)
1979 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1982 /* Enable the VLAN promiscuous mode. */
1984 for (i = 0; i < pf->vf_num; i++) {
1985 vsi = pf->vfs[i].vsi;
1986 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1991 /* Apply link configure */
1992 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1993 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1994 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1995 ETH_LINK_SPEED_40G)) {
1996 PMD_DRV_LOG(ERR, "Invalid link setting");
1999 ret = i40e_apply_link_speed(dev);
2000 if (I40E_SUCCESS != ret) {
2001 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2005 if (!rte_intr_allow_others(intr_handle)) {
2006 rte_intr_callback_unregister(intr_handle,
2007 i40e_dev_interrupt_handler,
2009 /* configure and enable device interrupt */
2010 i40e_pf_config_irq0(hw, FALSE);
2011 i40e_pf_enable_irq0(hw);
2013 if (dev->data->dev_conf.intr_conf.lsc != 0)
2015 "lsc won't enable because of no intr multiplex");
2016 } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2017 ret = i40e_aq_set_phy_int_mask(hw,
2018 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2019 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2020 I40E_AQ_EVENT_MEDIA_NA), NULL);
2021 if (ret != I40E_SUCCESS)
2022 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2024 /* Call get_link_info aq commond to enable LSE */
2025 i40e_dev_link_update(dev, 0);
2028 /* enable uio intr after callback register */
2029 rte_intr_enable(intr_handle);
2031 i40e_filter_restore(pf);
2033 return I40E_SUCCESS;
2036 i40e_dev_switch_queues(pf, FALSE);
2037 i40e_dev_clear_queues(dev);
2043 i40e_dev_stop(struct rte_eth_dev *dev)
2045 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2046 struct i40e_vsi *main_vsi = pf->main_vsi;
2047 struct i40e_mirror_rule *p_mirror;
2048 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2049 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2052 /* Disable all queues */
2053 i40e_dev_switch_queues(pf, FALSE);
2055 /* un-map queues with interrupt registers */
2056 i40e_vsi_disable_queues_intr(main_vsi);
2057 i40e_vsi_queues_unbind_intr(main_vsi);
2059 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2060 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2061 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2064 if (pf->fdir.fdir_vsi) {
2065 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2066 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2068 /* Clear all queues and release memory */
2069 i40e_dev_clear_queues(dev);
2072 i40e_dev_set_link_down(dev);
2074 /* Remove all mirror rules */
2075 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2076 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2079 pf->nb_mirror_rule = 0;
2081 if (!rte_intr_allow_others(intr_handle))
2082 /* resume to the default handler */
2083 rte_intr_callback_register(intr_handle,
2084 i40e_dev_interrupt_handler,
2087 /* Clean datapath event and queue/vec mapping */
2088 rte_intr_efd_disable(intr_handle);
2089 if (intr_handle->intr_vec) {
2090 rte_free(intr_handle->intr_vec);
2091 intr_handle->intr_vec = NULL;
2096 i40e_dev_close(struct rte_eth_dev *dev)
2098 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2099 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2101 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2105 PMD_INIT_FUNC_TRACE();
2108 hw->adapter_stopped = 1;
2109 i40e_dev_free_queues(dev);
2111 /* Disable interrupt */
2112 i40e_pf_disable_irq0(hw);
2113 rte_intr_disable(intr_handle);
2115 /* shutdown and destroy the HMC */
2116 i40e_shutdown_lan_hmc(hw);
2118 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2119 i40e_vsi_release(pf->vmdq[i].vsi);
2120 pf->vmdq[i].vsi = NULL;
2125 /* release all the existing VSIs and VEBs */
2126 i40e_fdir_teardown(pf);
2127 i40e_vsi_release(pf->main_vsi);
2129 /* shutdown the adminq */
2130 i40e_aq_queue_shutdown(hw, true);
2131 i40e_shutdown_adminq(hw);
2133 i40e_res_pool_destroy(&pf->qp_pool);
2134 i40e_res_pool_destroy(&pf->msix_pool);
2136 /* force a PF reset to clean anything leftover */
2137 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2138 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2139 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2140 I40E_WRITE_FLUSH(hw);
2144 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2146 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2147 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2148 struct i40e_vsi *vsi = pf->main_vsi;
2151 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2153 if (status != I40E_SUCCESS)
2154 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2156 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2158 if (status != I40E_SUCCESS)
2159 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2164 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2166 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2167 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2168 struct i40e_vsi *vsi = pf->main_vsi;
2171 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2173 if (status != I40E_SUCCESS)
2174 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2176 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2178 if (status != I40E_SUCCESS)
2179 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2183 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2185 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2186 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2187 struct i40e_vsi *vsi = pf->main_vsi;
2190 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2191 if (ret != I40E_SUCCESS)
2192 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2196 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2198 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2199 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200 struct i40e_vsi *vsi = pf->main_vsi;
2203 if (dev->data->promiscuous == 1)
2204 return; /* must remain in all_multicast mode */
2206 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2207 vsi->seid, FALSE, NULL);
2208 if (ret != I40E_SUCCESS)
2209 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2213 * Set device link up.
2216 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2218 /* re-apply link speed setting */
2219 return i40e_apply_link_speed(dev);
2223 * Set device link down.
2226 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2228 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2229 uint8_t abilities = 0;
2230 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2232 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2233 return i40e_phy_conf_link(hw, abilities, speed);
2237 i40e_dev_link_update(struct rte_eth_dev *dev,
2238 int wait_to_complete)
2240 #define CHECK_INTERVAL 100 /* 100ms */
2241 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2242 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2243 struct i40e_link_status link_status;
2244 struct rte_eth_link link, old;
2246 unsigned rep_cnt = MAX_REPEAT_TIME;
2247 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2249 memset(&link, 0, sizeof(link));
2250 memset(&old, 0, sizeof(old));
2251 memset(&link_status, 0, sizeof(link_status));
2252 rte_i40e_dev_atomic_read_link_status(dev, &old);
2255 /* Get link status information from hardware */
2256 status = i40e_aq_get_link_info(hw, enable_lse,
2257 &link_status, NULL);
2258 if (status != I40E_SUCCESS) {
2259 link.link_speed = ETH_SPEED_NUM_100M;
2260 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2261 PMD_DRV_LOG(ERR, "Failed to get link info");
2265 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2266 if (!wait_to_complete || link.link_status)
2269 rte_delay_ms(CHECK_INTERVAL);
2270 } while (--rep_cnt);
2272 if (!link.link_status)
2275 /* i40e uses full duplex only */
2276 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2278 /* Parse the link status */
2279 switch (link_status.link_speed) {
2280 case I40E_LINK_SPEED_100MB:
2281 link.link_speed = ETH_SPEED_NUM_100M;
2283 case I40E_LINK_SPEED_1GB:
2284 link.link_speed = ETH_SPEED_NUM_1G;
2286 case I40E_LINK_SPEED_10GB:
2287 link.link_speed = ETH_SPEED_NUM_10G;
2289 case I40E_LINK_SPEED_20GB:
2290 link.link_speed = ETH_SPEED_NUM_20G;
2292 case I40E_LINK_SPEED_25GB:
2293 link.link_speed = ETH_SPEED_NUM_25G;
2295 case I40E_LINK_SPEED_40GB:
2296 link.link_speed = ETH_SPEED_NUM_40G;
2299 link.link_speed = ETH_SPEED_NUM_100M;
2303 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2304 ETH_LINK_SPEED_FIXED);
2307 rte_i40e_dev_atomic_write_link_status(dev, &link);
2308 if (link.link_status == old.link_status)
2314 /* Get all the statistics of a VSI */
2316 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2318 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2319 struct i40e_eth_stats *nes = &vsi->eth_stats;
2320 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2321 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2323 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2324 vsi->offset_loaded, &oes->rx_bytes,
2326 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2327 vsi->offset_loaded, &oes->rx_unicast,
2329 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2330 vsi->offset_loaded, &oes->rx_multicast,
2331 &nes->rx_multicast);
2332 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2333 vsi->offset_loaded, &oes->rx_broadcast,
2334 &nes->rx_broadcast);
2335 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2336 &oes->rx_discards, &nes->rx_discards);
2337 /* GLV_REPC not supported */
2338 /* GLV_RMPC not supported */
2339 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2340 &oes->rx_unknown_protocol,
2341 &nes->rx_unknown_protocol);
2342 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2343 vsi->offset_loaded, &oes->tx_bytes,
2345 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2346 vsi->offset_loaded, &oes->tx_unicast,
2348 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2349 vsi->offset_loaded, &oes->tx_multicast,
2350 &nes->tx_multicast);
2351 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2352 vsi->offset_loaded, &oes->tx_broadcast,
2353 &nes->tx_broadcast);
2354 /* GLV_TDPC not supported */
2355 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2356 &oes->tx_errors, &nes->tx_errors);
2357 vsi->offset_loaded = true;
2359 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2361 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2362 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2363 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2364 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2365 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2366 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2367 nes->rx_unknown_protocol);
2368 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2369 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2370 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2371 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2372 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2373 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2374 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2379 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2382 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2383 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2385 /* Get statistics of struct i40e_eth_stats */
2386 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2387 I40E_GLPRT_GORCL(hw->port),
2388 pf->offset_loaded, &os->eth.rx_bytes,
2390 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2391 I40E_GLPRT_UPRCL(hw->port),
2392 pf->offset_loaded, &os->eth.rx_unicast,
2393 &ns->eth.rx_unicast);
2394 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2395 I40E_GLPRT_MPRCL(hw->port),
2396 pf->offset_loaded, &os->eth.rx_multicast,
2397 &ns->eth.rx_multicast);
2398 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2399 I40E_GLPRT_BPRCL(hw->port),
2400 pf->offset_loaded, &os->eth.rx_broadcast,
2401 &ns->eth.rx_broadcast);
2402 /* Workaround: CRC size should not be included in byte statistics,
2403 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2405 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2406 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2408 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2409 pf->offset_loaded, &os->eth.rx_discards,
2410 &ns->eth.rx_discards);
2411 /* GLPRT_REPC not supported */
2412 /* GLPRT_RMPC not supported */
2413 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2415 &os->eth.rx_unknown_protocol,
2416 &ns->eth.rx_unknown_protocol);
2417 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2418 I40E_GLPRT_GOTCL(hw->port),
2419 pf->offset_loaded, &os->eth.tx_bytes,
2421 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2422 I40E_GLPRT_UPTCL(hw->port),
2423 pf->offset_loaded, &os->eth.tx_unicast,
2424 &ns->eth.tx_unicast);
2425 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2426 I40E_GLPRT_MPTCL(hw->port),
2427 pf->offset_loaded, &os->eth.tx_multicast,
2428 &ns->eth.tx_multicast);
2429 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2430 I40E_GLPRT_BPTCL(hw->port),
2431 pf->offset_loaded, &os->eth.tx_broadcast,
2432 &ns->eth.tx_broadcast);
2433 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2434 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2435 /* GLPRT_TEPC not supported */
2437 /* additional port specific stats */
2438 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2439 pf->offset_loaded, &os->tx_dropped_link_down,
2440 &ns->tx_dropped_link_down);
2441 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2442 pf->offset_loaded, &os->crc_errors,
2444 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2445 pf->offset_loaded, &os->illegal_bytes,
2446 &ns->illegal_bytes);
2447 /* GLPRT_ERRBC not supported */
2448 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2449 pf->offset_loaded, &os->mac_local_faults,
2450 &ns->mac_local_faults);
2451 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2452 pf->offset_loaded, &os->mac_remote_faults,
2453 &ns->mac_remote_faults);
2454 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2455 pf->offset_loaded, &os->rx_length_errors,
2456 &ns->rx_length_errors);
2457 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2458 pf->offset_loaded, &os->link_xon_rx,
2460 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2461 pf->offset_loaded, &os->link_xoff_rx,
2463 for (i = 0; i < 8; i++) {
2464 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2466 &os->priority_xon_rx[i],
2467 &ns->priority_xon_rx[i]);
2468 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2470 &os->priority_xoff_rx[i],
2471 &ns->priority_xoff_rx[i]);
2473 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2474 pf->offset_loaded, &os->link_xon_tx,
2476 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2477 pf->offset_loaded, &os->link_xoff_tx,
2479 for (i = 0; i < 8; i++) {
2480 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2482 &os->priority_xon_tx[i],
2483 &ns->priority_xon_tx[i]);
2484 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2486 &os->priority_xoff_tx[i],
2487 &ns->priority_xoff_tx[i]);
2488 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2490 &os->priority_xon_2_xoff[i],
2491 &ns->priority_xon_2_xoff[i]);
2493 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2494 I40E_GLPRT_PRC64L(hw->port),
2495 pf->offset_loaded, &os->rx_size_64,
2497 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2498 I40E_GLPRT_PRC127L(hw->port),
2499 pf->offset_loaded, &os->rx_size_127,
2501 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2502 I40E_GLPRT_PRC255L(hw->port),
2503 pf->offset_loaded, &os->rx_size_255,
2505 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2506 I40E_GLPRT_PRC511L(hw->port),
2507 pf->offset_loaded, &os->rx_size_511,
2509 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2510 I40E_GLPRT_PRC1023L(hw->port),
2511 pf->offset_loaded, &os->rx_size_1023,
2513 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2514 I40E_GLPRT_PRC1522L(hw->port),
2515 pf->offset_loaded, &os->rx_size_1522,
2517 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2518 I40E_GLPRT_PRC9522L(hw->port),
2519 pf->offset_loaded, &os->rx_size_big,
2521 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2522 pf->offset_loaded, &os->rx_undersize,
2524 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2525 pf->offset_loaded, &os->rx_fragments,
2527 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2528 pf->offset_loaded, &os->rx_oversize,
2530 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2531 pf->offset_loaded, &os->rx_jabber,
2533 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2534 I40E_GLPRT_PTC64L(hw->port),
2535 pf->offset_loaded, &os->tx_size_64,
2537 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2538 I40E_GLPRT_PTC127L(hw->port),
2539 pf->offset_loaded, &os->tx_size_127,
2541 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2542 I40E_GLPRT_PTC255L(hw->port),
2543 pf->offset_loaded, &os->tx_size_255,
2545 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2546 I40E_GLPRT_PTC511L(hw->port),
2547 pf->offset_loaded, &os->tx_size_511,
2549 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2550 I40E_GLPRT_PTC1023L(hw->port),
2551 pf->offset_loaded, &os->tx_size_1023,
2553 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2554 I40E_GLPRT_PTC1522L(hw->port),
2555 pf->offset_loaded, &os->tx_size_1522,
2557 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2558 I40E_GLPRT_PTC9522L(hw->port),
2559 pf->offset_loaded, &os->tx_size_big,
2561 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2563 &os->fd_sb_match, &ns->fd_sb_match);
2564 /* GLPRT_MSPDC not supported */
2565 /* GLPRT_XEC not supported */
2567 pf->offset_loaded = true;
2570 i40e_update_vsi_stats(pf->main_vsi);
2573 /* Get all statistics of a port */
2575 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2577 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2578 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2579 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2582 /* call read registers - updates values, now write them to struct */
2583 i40e_read_stats_registers(pf, hw);
2585 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2586 pf->main_vsi->eth_stats.rx_multicast +
2587 pf->main_vsi->eth_stats.rx_broadcast -
2588 pf->main_vsi->eth_stats.rx_discards;
2589 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2590 pf->main_vsi->eth_stats.tx_multicast +
2591 pf->main_vsi->eth_stats.tx_broadcast;
2592 stats->ibytes = ns->eth.rx_bytes;
2593 stats->obytes = ns->eth.tx_bytes;
2594 stats->oerrors = ns->eth.tx_errors +
2595 pf->main_vsi->eth_stats.tx_errors;
2598 stats->imissed = ns->eth.rx_discards +
2599 pf->main_vsi->eth_stats.rx_discards;
2600 stats->ierrors = ns->crc_errors +
2601 ns->rx_length_errors + ns->rx_undersize +
2602 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2604 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2605 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2606 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2607 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2608 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2609 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2610 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2611 ns->eth.rx_unknown_protocol);
2612 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2613 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2614 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2615 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2616 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2617 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2619 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2620 ns->tx_dropped_link_down);
2621 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2622 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2624 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2625 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2626 ns->mac_local_faults);
2627 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2628 ns->mac_remote_faults);
2629 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2630 ns->rx_length_errors);
2631 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2632 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2633 for (i = 0; i < 8; i++) {
2634 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2635 i, ns->priority_xon_rx[i]);
2636 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2637 i, ns->priority_xoff_rx[i]);
2639 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2640 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2641 for (i = 0; i < 8; i++) {
2642 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2643 i, ns->priority_xon_tx[i]);
2644 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2645 i, ns->priority_xoff_tx[i]);
2646 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2647 i, ns->priority_xon_2_xoff[i]);
2649 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2650 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2651 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2652 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2653 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2654 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2655 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2656 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2657 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2658 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2659 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2660 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2661 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2662 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2663 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2664 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2665 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2666 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2667 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2668 ns->mac_short_packet_dropped);
2669 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2670 ns->checksum_error);
2671 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2672 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2675 /* Reset the statistics */
2677 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2679 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2680 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2682 /* Mark PF and VSI stats to update the offset, aka "reset" */
2683 pf->offset_loaded = false;
2685 pf->main_vsi->offset_loaded = false;
2687 /* read the stats, reading current register values into offset */
2688 i40e_read_stats_registers(pf, hw);
2692 i40e_xstats_calc_num(void)
2694 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2695 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2696 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2699 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2700 struct rte_eth_xstat_name *xstats_names,
2701 __rte_unused unsigned limit)
2706 if (xstats_names == NULL)
2707 return i40e_xstats_calc_num();
2709 /* Note: limit checked in rte_eth_xstats_names() */
2711 /* Get stats from i40e_eth_stats struct */
2712 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2713 snprintf(xstats_names[count].name,
2714 sizeof(xstats_names[count].name),
2715 "%s", rte_i40e_stats_strings[i].name);
2719 /* Get individiual stats from i40e_hw_port struct */
2720 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2721 snprintf(xstats_names[count].name,
2722 sizeof(xstats_names[count].name),
2723 "%s", rte_i40e_hw_port_strings[i].name);
2727 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2728 for (prio = 0; prio < 8; prio++) {
2729 snprintf(xstats_names[count].name,
2730 sizeof(xstats_names[count].name),
2731 "rx_priority%u_%s", prio,
2732 rte_i40e_rxq_prio_strings[i].name);
2737 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2738 for (prio = 0; prio < 8; prio++) {
2739 snprintf(xstats_names[count].name,
2740 sizeof(xstats_names[count].name),
2741 "tx_priority%u_%s", prio,
2742 rte_i40e_txq_prio_strings[i].name);
2750 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2753 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2754 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2755 unsigned i, count, prio;
2756 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2758 count = i40e_xstats_calc_num();
2762 i40e_read_stats_registers(pf, hw);
2769 /* Get stats from i40e_eth_stats struct */
2770 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2771 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2772 rte_i40e_stats_strings[i].offset);
2773 xstats[count].id = count;
2777 /* Get individiual stats from i40e_hw_port struct */
2778 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2779 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2780 rte_i40e_hw_port_strings[i].offset);
2781 xstats[count].id = count;
2785 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2786 for (prio = 0; prio < 8; prio++) {
2787 xstats[count].value =
2788 *(uint64_t *)(((char *)hw_stats) +
2789 rte_i40e_rxq_prio_strings[i].offset +
2790 (sizeof(uint64_t) * prio));
2791 xstats[count].id = count;
2796 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2797 for (prio = 0; prio < 8; prio++) {
2798 xstats[count].value =
2799 *(uint64_t *)(((char *)hw_stats) +
2800 rte_i40e_txq_prio_strings[i].offset +
2801 (sizeof(uint64_t) * prio));
2802 xstats[count].id = count;
2811 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2812 __rte_unused uint16_t queue_id,
2813 __rte_unused uint8_t stat_idx,
2814 __rte_unused uint8_t is_rx)
2816 PMD_INIT_FUNC_TRACE();
2822 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2824 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2830 full_ver = hw->nvm.oem_ver;
2831 ver = (u8)(full_ver >> 24);
2832 build = (u16)((full_ver >> 8) & 0xffff);
2833 patch = (u8)(full_ver & 0xff);
2835 ret = snprintf(fw_version, fw_size,
2836 "%d.%d%d 0x%08x %d.%d.%d",
2837 ((hw->nvm.version >> 12) & 0xf),
2838 ((hw->nvm.version >> 4) & 0xff),
2839 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2842 ret += 1; /* add the size of '\0' */
2843 if (fw_size < (u32)ret)
2850 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2852 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2853 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2854 struct i40e_vsi *vsi = pf->main_vsi;
2855 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2857 dev_info->pci_dev = pci_dev;
2858 dev_info->max_rx_queues = vsi->nb_qps;
2859 dev_info->max_tx_queues = vsi->nb_qps;
2860 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2861 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2862 dev_info->max_mac_addrs = vsi->max_macaddrs;
2863 dev_info->max_vfs = pci_dev->max_vfs;
2864 dev_info->rx_offload_capa =
2865 DEV_RX_OFFLOAD_VLAN_STRIP |
2866 DEV_RX_OFFLOAD_QINQ_STRIP |
2867 DEV_RX_OFFLOAD_IPV4_CKSUM |
2868 DEV_RX_OFFLOAD_UDP_CKSUM |
2869 DEV_RX_OFFLOAD_TCP_CKSUM;
2870 dev_info->tx_offload_capa =
2871 DEV_TX_OFFLOAD_VLAN_INSERT |
2872 DEV_TX_OFFLOAD_QINQ_INSERT |
2873 DEV_TX_OFFLOAD_IPV4_CKSUM |
2874 DEV_TX_OFFLOAD_UDP_CKSUM |
2875 DEV_TX_OFFLOAD_TCP_CKSUM |
2876 DEV_TX_OFFLOAD_SCTP_CKSUM |
2877 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2878 DEV_TX_OFFLOAD_TCP_TSO |
2879 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2880 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2881 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2882 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2883 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2885 dev_info->reta_size = pf->hash_lut_size;
2886 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2888 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2890 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2891 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2892 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2894 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2898 dev_info->default_txconf = (struct rte_eth_txconf) {
2900 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2901 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2902 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2904 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2905 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2906 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2907 ETH_TXQ_FLAGS_NOOFFLOADS,
2910 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2911 .nb_max = I40E_MAX_RING_DESC,
2912 .nb_min = I40E_MIN_RING_DESC,
2913 .nb_align = I40E_ALIGN_RING_DESC,
2916 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2917 .nb_max = I40E_MAX_RING_DESC,
2918 .nb_min = I40E_MIN_RING_DESC,
2919 .nb_align = I40E_ALIGN_RING_DESC,
2920 .nb_seg_max = I40E_TX_MAX_SEG,
2921 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2924 if (pf->flags & I40E_FLAG_VMDQ) {
2925 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2926 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2927 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2928 pf->max_nb_vmdq_vsi;
2929 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2930 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2931 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2934 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2936 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2937 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2939 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2942 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2946 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2948 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2949 struct i40e_vsi *vsi = pf->main_vsi;
2950 PMD_INIT_FUNC_TRACE();
2953 return i40e_vsi_add_vlan(vsi, vlan_id);
2955 return i40e_vsi_delete_vlan(vsi, vlan_id);
2959 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2960 enum rte_vlan_type vlan_type,
2963 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2964 uint64_t reg_r = 0, reg_w = 0;
2965 uint16_t reg_id = 0;
2967 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2969 switch (vlan_type) {
2970 case ETH_VLAN_TYPE_OUTER:
2976 case ETH_VLAN_TYPE_INNER:
2982 "Unsupported vlan type in single vlan.");
2988 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2991 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2993 if (ret != I40E_SUCCESS) {
2995 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3001 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3004 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3005 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3006 if (reg_r == reg_w) {
3008 PMD_DRV_LOG(DEBUG, "No need to write");
3012 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3014 if (ret != I40E_SUCCESS) {
3017 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3022 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3029 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3031 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3032 struct i40e_vsi *vsi = pf->main_vsi;
3034 if (mask & ETH_VLAN_FILTER_MASK) {
3035 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3036 i40e_vsi_config_vlan_filter(vsi, TRUE);
3038 i40e_vsi_config_vlan_filter(vsi, FALSE);
3041 if (mask & ETH_VLAN_STRIP_MASK) {
3042 /* Enable or disable VLAN stripping */
3043 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3044 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3046 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3049 if (mask & ETH_VLAN_EXTEND_MASK) {
3050 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3051 i40e_vsi_config_double_vlan(vsi, TRUE);
3052 /* Set global registers with default ether type value */
3053 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3055 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3059 i40e_vsi_config_double_vlan(vsi, FALSE);
3064 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3065 __rte_unused uint16_t queue,
3066 __rte_unused int on)
3068 PMD_INIT_FUNC_TRACE();
3072 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3074 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3075 struct i40e_vsi *vsi = pf->main_vsi;
3076 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3077 struct i40e_vsi_vlan_pvid_info info;
3079 memset(&info, 0, sizeof(info));
3082 info.config.pvid = pvid;
3084 info.config.reject.tagged =
3085 data->dev_conf.txmode.hw_vlan_reject_tagged;
3086 info.config.reject.untagged =
3087 data->dev_conf.txmode.hw_vlan_reject_untagged;
3090 return i40e_vsi_vlan_pvid_set(vsi, &info);
3094 i40e_dev_led_on(struct rte_eth_dev *dev)
3096 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3097 uint32_t mode = i40e_led_get(hw);
3100 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3106 i40e_dev_led_off(struct rte_eth_dev *dev)
3108 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3109 uint32_t mode = i40e_led_get(hw);
3112 i40e_led_set(hw, 0, false);
3118 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3120 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3121 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3123 fc_conf->pause_time = pf->fc_conf.pause_time;
3124 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3125 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3127 /* Return current mode according to actual setting*/
3128 switch (hw->fc.current_mode) {
3130 fc_conf->mode = RTE_FC_FULL;
3132 case I40E_FC_TX_PAUSE:
3133 fc_conf->mode = RTE_FC_TX_PAUSE;
3135 case I40E_FC_RX_PAUSE:
3136 fc_conf->mode = RTE_FC_RX_PAUSE;
3140 fc_conf->mode = RTE_FC_NONE;
3147 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3149 uint32_t mflcn_reg, fctrl_reg, reg;
3150 uint32_t max_high_water;
3151 uint8_t i, aq_failure;
3155 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3156 [RTE_FC_NONE] = I40E_FC_NONE,
3157 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3158 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3159 [RTE_FC_FULL] = I40E_FC_FULL
3162 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3164 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3165 if ((fc_conf->high_water > max_high_water) ||
3166 (fc_conf->high_water < fc_conf->low_water)) {
3168 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3173 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3174 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3175 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3177 pf->fc_conf.pause_time = fc_conf->pause_time;
3178 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3179 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3181 PMD_INIT_FUNC_TRACE();
3183 /* All the link flow control related enable/disable register
3184 * configuration is handle by the F/W
3186 err = i40e_set_fc(hw, &aq_failure, true);
3190 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3191 /* Configure flow control refresh threshold,
3192 * the value for stat_tx_pause_refresh_timer[8]
3193 * is used for global pause operation.
3197 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3198 pf->fc_conf.pause_time);
3200 /* configure the timer value included in transmitted pause
3202 * the value for stat_tx_pause_quanta[8] is used for global
3205 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3206 pf->fc_conf.pause_time);
3208 fctrl_reg = I40E_READ_REG(hw,
3209 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3211 if (fc_conf->mac_ctrl_frame_fwd != 0)
3212 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3214 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3216 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3219 /* Configure pause time (2 TCs per register) */
3220 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3221 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3222 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3224 /* Configure flow control refresh threshold value */
3225 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3226 pf->fc_conf.pause_time / 2);
3228 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3230 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3231 *depending on configuration
3233 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3234 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3235 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3237 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3238 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3241 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3244 /* config the water marker both based on the packets and bytes */
3245 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3246 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3247 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3248 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3249 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3250 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3251 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3252 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3254 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3255 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3258 I40E_WRITE_FLUSH(hw);
3264 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3265 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3267 PMD_INIT_FUNC_TRACE();
3272 /* Add a MAC address, and update filters */
3274 i40e_macaddr_add(struct rte_eth_dev *dev,
3275 struct ether_addr *mac_addr,
3276 __rte_unused uint32_t index,
3279 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3280 struct i40e_mac_filter_info mac_filter;
3281 struct i40e_vsi *vsi;
3284 /* If VMDQ not enabled or configured, return */
3285 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3286 !pf->nb_cfg_vmdq_vsi)) {
3287 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3288 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3293 if (pool > pf->nb_cfg_vmdq_vsi) {
3294 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3295 pool, pf->nb_cfg_vmdq_vsi);
3299 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3300 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3301 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3303 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3308 vsi = pf->vmdq[pool - 1].vsi;
3310 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3311 if (ret != I40E_SUCCESS) {
3312 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3317 /* Remove a MAC address, and update filters */
3319 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3321 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3322 struct i40e_vsi *vsi;
3323 struct rte_eth_dev_data *data = dev->data;
3324 struct ether_addr *macaddr;
3329 macaddr = &(data->mac_addrs[index]);
3331 pool_sel = dev->data->mac_pool_sel[index];
3333 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3334 if (pool_sel & (1ULL << i)) {
3338 /* No VMDQ pool enabled or configured */
3339 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3340 (i > pf->nb_cfg_vmdq_vsi)) {
3342 "No VMDQ pool enabled/configured");
3345 vsi = pf->vmdq[i - 1].vsi;
3347 ret = i40e_vsi_delete_mac(vsi, macaddr);
3350 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3357 /* Set perfect match or hash match of MAC and VLAN for a VF */
3359 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3360 struct rte_eth_mac_filter *filter,
3364 struct i40e_mac_filter_info mac_filter;
3365 struct ether_addr old_mac;
3366 struct ether_addr *new_mac;
3367 struct i40e_pf_vf *vf = NULL;
3372 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3375 hw = I40E_PF_TO_HW(pf);
3377 if (filter == NULL) {
3378 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3382 new_mac = &filter->mac_addr;
3384 if (is_zero_ether_addr(new_mac)) {
3385 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3389 vf_id = filter->dst_id;
3391 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3392 PMD_DRV_LOG(ERR, "Invalid argument.");
3395 vf = &pf->vfs[vf_id];
3397 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3398 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3403 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3404 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3406 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3409 mac_filter.filter_type = filter->filter_type;
3410 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3411 if (ret != I40E_SUCCESS) {
3412 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3415 ether_addr_copy(new_mac, &pf->dev_addr);
3417 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3419 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3420 if (ret != I40E_SUCCESS) {
3421 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3425 /* Clear device address as it has been removed */
3426 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3427 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3433 /* MAC filter handle */
3435 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3438 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3439 struct rte_eth_mac_filter *filter;
3440 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3441 int ret = I40E_NOT_SUPPORTED;
3443 filter = (struct rte_eth_mac_filter *)(arg);
3445 switch (filter_op) {
3446 case RTE_ETH_FILTER_NOP:
3449 case RTE_ETH_FILTER_ADD:
3450 i40e_pf_disable_irq0(hw);
3452 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3453 i40e_pf_enable_irq0(hw);
3455 case RTE_ETH_FILTER_DELETE:
3456 i40e_pf_disable_irq0(hw);
3458 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3459 i40e_pf_enable_irq0(hw);
3462 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3463 ret = I40E_ERR_PARAM;
3471 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3473 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3474 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3480 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3481 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3484 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3488 uint32_t *lut_dw = (uint32_t *)lut;
3489 uint16_t i, lut_size_dw = lut_size / 4;
3491 for (i = 0; i < lut_size_dw; i++)
3492 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3499 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3508 pf = I40E_VSI_TO_PF(vsi);
3509 hw = I40E_VSI_TO_HW(vsi);
3511 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3512 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3515 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3519 uint32_t *lut_dw = (uint32_t *)lut;
3520 uint16_t i, lut_size_dw = lut_size / 4;
3522 for (i = 0; i < lut_size_dw; i++)
3523 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3524 I40E_WRITE_FLUSH(hw);
3531 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3532 struct rte_eth_rss_reta_entry64 *reta_conf,
3535 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3536 uint16_t i, lut_size = pf->hash_lut_size;
3537 uint16_t idx, shift;
3541 if (reta_size != lut_size ||
3542 reta_size > ETH_RSS_RETA_SIZE_512) {
3544 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3545 reta_size, lut_size);
3549 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3551 PMD_DRV_LOG(ERR, "No memory can be allocated");
3554 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3557 for (i = 0; i < reta_size; i++) {
3558 idx = i / RTE_RETA_GROUP_SIZE;
3559 shift = i % RTE_RETA_GROUP_SIZE;
3560 if (reta_conf[idx].mask & (1ULL << shift))
3561 lut[i] = reta_conf[idx].reta[shift];
3563 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3572 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3573 struct rte_eth_rss_reta_entry64 *reta_conf,
3576 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3577 uint16_t i, lut_size = pf->hash_lut_size;
3578 uint16_t idx, shift;
3582 if (reta_size != lut_size ||
3583 reta_size > ETH_RSS_RETA_SIZE_512) {
3585 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3586 reta_size, lut_size);
3590 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3592 PMD_DRV_LOG(ERR, "No memory can be allocated");
3596 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3599 for (i = 0; i < reta_size; i++) {
3600 idx = i / RTE_RETA_GROUP_SIZE;
3601 shift = i % RTE_RETA_GROUP_SIZE;
3602 if (reta_conf[idx].mask & (1ULL << shift))
3603 reta_conf[idx].reta[shift] = lut[i];
3613 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3614 * @hw: pointer to the HW structure
3615 * @mem: pointer to mem struct to fill out
3616 * @size: size of memory requested
3617 * @alignment: what to align the allocation to
3619 enum i40e_status_code
3620 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3621 struct i40e_dma_mem *mem,
3625 const struct rte_memzone *mz = NULL;
3626 char z_name[RTE_MEMZONE_NAMESIZE];
3629 return I40E_ERR_PARAM;
3631 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3632 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3633 alignment, RTE_PGSIZE_2M);
3635 return I40E_ERR_NO_MEMORY;
3639 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3640 mem->zone = (const void *)mz;
3642 "memzone %s allocated with physical address: %"PRIu64,
3645 return I40E_SUCCESS;
3649 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3650 * @hw: pointer to the HW structure
3651 * @mem: ptr to mem struct to free
3653 enum i40e_status_code
3654 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3655 struct i40e_dma_mem *mem)
3658 return I40E_ERR_PARAM;
3661 "memzone %s to be freed with physical address: %"PRIu64,
3662 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3663 rte_memzone_free((const struct rte_memzone *)mem->zone);
3668 return I40E_SUCCESS;
3672 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3673 * @hw: pointer to the HW structure
3674 * @mem: pointer to mem struct to fill out
3675 * @size: size of memory requested
3677 enum i40e_status_code
3678 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3679 struct i40e_virt_mem *mem,
3683 return I40E_ERR_PARAM;
3686 mem->va = rte_zmalloc("i40e", size, 0);
3689 return I40E_SUCCESS;
3691 return I40E_ERR_NO_MEMORY;
3695 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3696 * @hw: pointer to the HW structure
3697 * @mem: pointer to mem struct to free
3699 enum i40e_status_code
3700 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3701 struct i40e_virt_mem *mem)
3704 return I40E_ERR_PARAM;
3709 return I40E_SUCCESS;
3713 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3715 rte_spinlock_init(&sp->spinlock);
3719 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3721 rte_spinlock_lock(&sp->spinlock);
3725 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3727 rte_spinlock_unlock(&sp->spinlock);
3731 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3737 * Get the hardware capabilities, which will be parsed
3738 * and saved into struct i40e_hw.
3741 i40e_get_cap(struct i40e_hw *hw)
3743 struct i40e_aqc_list_capabilities_element_resp *buf;
3744 uint16_t len, size = 0;
3747 /* Calculate a huge enough buff for saving response data temporarily */
3748 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3749 I40E_MAX_CAP_ELE_NUM;
3750 buf = rte_zmalloc("i40e", len, 0);
3752 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3753 return I40E_ERR_NO_MEMORY;
3756 /* Get, parse the capabilities and save it to hw */
3757 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3758 i40e_aqc_opc_list_func_capabilities, NULL);
3759 if (ret != I40E_SUCCESS)
3760 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3762 /* Free the temporary buffer after being used */
3769 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3771 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3772 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3773 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3774 uint16_t qp_count = 0, vsi_count = 0;
3776 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3777 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3780 /* Add the parameter init for LFC */
3781 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3782 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3783 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3785 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3786 pf->max_num_vsi = hw->func_caps.num_vsis;
3787 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3788 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3789 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3791 /* FDir queue/VSI allocation */
3792 pf->fdir_qp_offset = 0;
3793 if (hw->func_caps.fd) {
3794 pf->flags |= I40E_FLAG_FDIR;
3795 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3797 pf->fdir_nb_qps = 0;
3799 qp_count += pf->fdir_nb_qps;
3802 /* LAN queue/VSI allocation */
3803 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3804 if (!hw->func_caps.rss) {
3807 pf->flags |= I40E_FLAG_RSS;
3808 if (hw->mac.type == I40E_MAC_X722)
3809 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3810 pf->lan_nb_qps = pf->lan_nb_qp_max;
3812 qp_count += pf->lan_nb_qps;
3815 /* VF queue/VSI allocation */
3816 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3817 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3818 pf->flags |= I40E_FLAG_SRIOV;
3819 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3820 pf->vf_num = pci_dev->max_vfs;
3822 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3823 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3828 qp_count += pf->vf_nb_qps * pf->vf_num;
3829 vsi_count += pf->vf_num;
3831 /* VMDq queue/VSI allocation */
3832 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3833 pf->vmdq_nb_qps = 0;
3834 pf->max_nb_vmdq_vsi = 0;
3835 if (hw->func_caps.vmdq) {
3836 if (qp_count < hw->func_caps.num_tx_qp &&
3837 vsi_count < hw->func_caps.num_vsis) {
3838 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3839 qp_count) / pf->vmdq_nb_qp_max;
3841 /* Limit the maximum number of VMDq vsi to the maximum
3842 * ethdev can support
3844 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3845 hw->func_caps.num_vsis - vsi_count);
3846 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3848 if (pf->max_nb_vmdq_vsi) {
3849 pf->flags |= I40E_FLAG_VMDQ;
3850 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3852 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3853 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3854 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3857 "No enough queues left for VMDq");
3860 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3863 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3864 vsi_count += pf->max_nb_vmdq_vsi;
3866 if (hw->func_caps.dcb)
3867 pf->flags |= I40E_FLAG_DCB;
3869 if (qp_count > hw->func_caps.num_tx_qp) {
3871 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3872 qp_count, hw->func_caps.num_tx_qp);
3875 if (vsi_count > hw->func_caps.num_vsis) {
3877 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3878 vsi_count, hw->func_caps.num_vsis);
3886 i40e_pf_get_switch_config(struct i40e_pf *pf)
3888 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3889 struct i40e_aqc_get_switch_config_resp *switch_config;
3890 struct i40e_aqc_switch_config_element_resp *element;
3891 uint16_t start_seid = 0, num_reported;
3894 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3895 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3896 if (!switch_config) {
3897 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3901 /* Get the switch configurations */
3902 ret = i40e_aq_get_switch_config(hw, switch_config,
3903 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3904 if (ret != I40E_SUCCESS) {
3905 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3908 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3909 if (num_reported != 1) { /* The number should be 1 */
3910 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3914 /* Parse the switch configuration elements */
3915 element = &(switch_config->element[0]);
3916 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3917 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3918 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3920 PMD_DRV_LOG(INFO, "Unknown element type");
3923 rte_free(switch_config);
3929 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3932 struct pool_entry *entry;
3934 if (pool == NULL || num == 0)
3937 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3938 if (entry == NULL) {
3939 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3943 /* queue heap initialize */
3944 pool->num_free = num;
3945 pool->num_alloc = 0;
3947 LIST_INIT(&pool->alloc_list);
3948 LIST_INIT(&pool->free_list);
3950 /* Initialize element */
3954 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3959 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3961 struct pool_entry *entry, *next_entry;
3966 for (entry = LIST_FIRST(&pool->alloc_list);
3967 entry && (next_entry = LIST_NEXT(entry, next), 1);
3968 entry = next_entry) {
3969 LIST_REMOVE(entry, next);
3973 for (entry = LIST_FIRST(&pool->free_list);
3974 entry && (next_entry = LIST_NEXT(entry, next), 1);
3975 entry = next_entry) {
3976 LIST_REMOVE(entry, next);
3981 pool->num_alloc = 0;
3983 LIST_INIT(&pool->alloc_list);
3984 LIST_INIT(&pool->free_list);
3988 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3991 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3992 uint32_t pool_offset;
3996 PMD_DRV_LOG(ERR, "Invalid parameter");
4000 pool_offset = base - pool->base;
4001 /* Lookup in alloc list */
4002 LIST_FOREACH(entry, &pool->alloc_list, next) {
4003 if (entry->base == pool_offset) {
4004 valid_entry = entry;
4005 LIST_REMOVE(entry, next);
4010 /* Not find, return */
4011 if (valid_entry == NULL) {
4012 PMD_DRV_LOG(ERR, "Failed to find entry");
4017 * Found it, move it to free list and try to merge.
4018 * In order to make merge easier, always sort it by qbase.
4019 * Find adjacent prev and last entries.
4022 LIST_FOREACH(entry, &pool->free_list, next) {
4023 if (entry->base > valid_entry->base) {
4031 /* Try to merge with next one*/
4033 /* Merge with next one */
4034 if (valid_entry->base + valid_entry->len == next->base) {
4035 next->base = valid_entry->base;
4036 next->len += valid_entry->len;
4037 rte_free(valid_entry);
4044 /* Merge with previous one */
4045 if (prev->base + prev->len == valid_entry->base) {
4046 prev->len += valid_entry->len;
4047 /* If it merge with next one, remove next node */
4049 LIST_REMOVE(valid_entry, next);
4050 rte_free(valid_entry);
4052 rte_free(valid_entry);
4058 /* Not find any entry to merge, insert */
4061 LIST_INSERT_AFTER(prev, valid_entry, next);
4062 else if (next != NULL)
4063 LIST_INSERT_BEFORE(next, valid_entry, next);
4064 else /* It's empty list, insert to head */
4065 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4068 pool->num_free += valid_entry->len;
4069 pool->num_alloc -= valid_entry->len;
4075 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4078 struct pool_entry *entry, *valid_entry;
4080 if (pool == NULL || num == 0) {
4081 PMD_DRV_LOG(ERR, "Invalid parameter");
4085 if (pool->num_free < num) {
4086 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4087 num, pool->num_free);
4092 /* Lookup in free list and find most fit one */
4093 LIST_FOREACH(entry, &pool->free_list, next) {
4094 if (entry->len >= num) {
4096 if (entry->len == num) {
4097 valid_entry = entry;
4100 if (valid_entry == NULL || valid_entry->len > entry->len)
4101 valid_entry = entry;
4105 /* Not find one to satisfy the request, return */
4106 if (valid_entry == NULL) {
4107 PMD_DRV_LOG(ERR, "No valid entry found");
4111 * The entry have equal queue number as requested,
4112 * remove it from alloc_list.
4114 if (valid_entry->len == num) {
4115 LIST_REMOVE(valid_entry, next);
4118 * The entry have more numbers than requested,
4119 * create a new entry for alloc_list and minus its
4120 * queue base and number in free_list.
4122 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4123 if (entry == NULL) {
4125 "Failed to allocate memory for resource pool");
4128 entry->base = valid_entry->base;
4130 valid_entry->base += num;
4131 valid_entry->len -= num;
4132 valid_entry = entry;
4135 /* Insert it into alloc list, not sorted */
4136 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4138 pool->num_free -= valid_entry->len;
4139 pool->num_alloc += valid_entry->len;
4141 return valid_entry->base + pool->base;
4145 * bitmap_is_subset - Check whether src2 is subset of src1
4148 bitmap_is_subset(uint8_t src1, uint8_t src2)
4150 return !((src1 ^ src2) & src2);
4153 static enum i40e_status_code
4154 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4156 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4158 /* If DCB is not supported, only default TC is supported */
4159 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4160 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4161 return I40E_NOT_SUPPORTED;
4164 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4166 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4167 hw->func_caps.enabled_tcmap, enabled_tcmap);
4168 return I40E_NOT_SUPPORTED;
4170 return I40E_SUCCESS;
4174 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4175 struct i40e_vsi_vlan_pvid_info *info)
4178 struct i40e_vsi_context ctxt;
4179 uint8_t vlan_flags = 0;
4182 if (vsi == NULL || info == NULL) {
4183 PMD_DRV_LOG(ERR, "invalid parameters");
4184 return I40E_ERR_PARAM;
4188 vsi->info.pvid = info->config.pvid;
4190 * If insert pvid is enabled, only tagged pkts are
4191 * allowed to be sent out.
4193 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4194 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4197 if (info->config.reject.tagged == 0)
4198 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4200 if (info->config.reject.untagged == 0)
4201 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4203 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4204 I40E_AQ_VSI_PVLAN_MODE_MASK);
4205 vsi->info.port_vlan_flags |= vlan_flags;
4206 vsi->info.valid_sections =
4207 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4208 memset(&ctxt, 0, sizeof(ctxt));
4209 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4210 ctxt.seid = vsi->seid;
4212 hw = I40E_VSI_TO_HW(vsi);
4213 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4214 if (ret != I40E_SUCCESS)
4215 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4221 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4223 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4225 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4227 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4228 if (ret != I40E_SUCCESS)
4232 PMD_DRV_LOG(ERR, "seid not valid");
4236 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4237 tc_bw_data.tc_valid_bits = enabled_tcmap;
4238 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4239 tc_bw_data.tc_bw_credits[i] =
4240 (enabled_tcmap & (1 << i)) ? 1 : 0;
4242 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4243 if (ret != I40E_SUCCESS) {
4244 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4248 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4249 sizeof(vsi->info.qs_handle));
4250 return I40E_SUCCESS;
4253 static enum i40e_status_code
4254 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4255 struct i40e_aqc_vsi_properties_data *info,
4256 uint8_t enabled_tcmap)
4258 enum i40e_status_code ret;
4259 int i, total_tc = 0;
4260 uint16_t qpnum_per_tc, bsf, qp_idx;
4262 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4263 if (ret != I40E_SUCCESS)
4266 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4267 if (enabled_tcmap & (1 << i))
4269 vsi->enabled_tc = enabled_tcmap;
4271 /* Number of queues per enabled TC */
4272 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4273 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4274 bsf = rte_bsf32(qpnum_per_tc);
4276 /* Adjust the queue number to actual queues that can be applied */
4277 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4278 vsi->nb_qps = qpnum_per_tc * total_tc;
4281 * Configure TC and queue mapping parameters, for enabled TC,
4282 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4283 * default queue will serve it.
4286 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4287 if (vsi->enabled_tc & (1 << i)) {
4288 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4289 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4290 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4291 qp_idx += qpnum_per_tc;
4293 info->tc_mapping[i] = 0;
4296 /* Associate queue number with VSI */
4297 if (vsi->type == I40E_VSI_SRIOV) {
4298 info->mapping_flags |=
4299 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4300 for (i = 0; i < vsi->nb_qps; i++)
4301 info->queue_mapping[i] =
4302 rte_cpu_to_le_16(vsi->base_queue + i);
4304 info->mapping_flags |=
4305 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4306 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4308 info->valid_sections |=
4309 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4311 return I40E_SUCCESS;
4315 i40e_veb_release(struct i40e_veb *veb)
4317 struct i40e_vsi *vsi;
4323 if (!TAILQ_EMPTY(&veb->head)) {
4324 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4327 /* associate_vsi field is NULL for floating VEB */
4328 if (veb->associate_vsi != NULL) {
4329 vsi = veb->associate_vsi;
4330 hw = I40E_VSI_TO_HW(vsi);
4332 vsi->uplink_seid = veb->uplink_seid;
4335 veb->associate_pf->main_vsi->floating_veb = NULL;
4336 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4339 i40e_aq_delete_element(hw, veb->seid, NULL);
4341 return I40E_SUCCESS;
4345 static struct i40e_veb *
4346 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4348 struct i40e_veb *veb;
4354 "veb setup failed, associated PF shouldn't null");
4357 hw = I40E_PF_TO_HW(pf);
4359 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4361 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4365 veb->associate_vsi = vsi;
4366 veb->associate_pf = pf;
4367 TAILQ_INIT(&veb->head);
4368 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4370 /* create floating veb if vsi is NULL */
4372 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4373 I40E_DEFAULT_TCMAP, false,
4374 &veb->seid, false, NULL);
4376 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4377 true, &veb->seid, false, NULL);
4380 if (ret != I40E_SUCCESS) {
4381 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4382 hw->aq.asq_last_status);
4385 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4387 /* get statistics index */
4388 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4389 &veb->stats_idx, NULL, NULL, NULL);
4390 if (ret != I40E_SUCCESS) {
4391 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4392 hw->aq.asq_last_status);
4395 /* Get VEB bandwidth, to be implemented */
4396 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4398 vsi->uplink_seid = veb->seid;
4407 i40e_vsi_release(struct i40e_vsi *vsi)
4411 struct i40e_vsi_list *vsi_list;
4414 struct i40e_mac_filter *f;
4415 uint16_t user_param;
4418 return I40E_SUCCESS;
4423 user_param = vsi->user_param;
4425 pf = I40E_VSI_TO_PF(vsi);
4426 hw = I40E_VSI_TO_HW(vsi);
4428 /* VSI has child to attach, release child first */
4430 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4431 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4434 i40e_veb_release(vsi->veb);
4437 if (vsi->floating_veb) {
4438 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4439 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4444 /* Remove all macvlan filters of the VSI */
4445 i40e_vsi_remove_all_macvlan_filter(vsi);
4446 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4449 if (vsi->type != I40E_VSI_MAIN &&
4450 ((vsi->type != I40E_VSI_SRIOV) ||
4451 !pf->floating_veb_list[user_param])) {
4452 /* Remove vsi from parent's sibling list */
4453 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4454 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4455 return I40E_ERR_PARAM;
4457 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4458 &vsi->sib_vsi_list, list);
4460 /* Remove all switch element of the VSI */
4461 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4462 if (ret != I40E_SUCCESS)
4463 PMD_DRV_LOG(ERR, "Failed to delete element");
4466 if ((vsi->type == I40E_VSI_SRIOV) &&
4467 pf->floating_veb_list[user_param]) {
4468 /* Remove vsi from parent's sibling list */
4469 if (vsi->parent_vsi == NULL ||
4470 vsi->parent_vsi->floating_veb == NULL) {
4471 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4472 return I40E_ERR_PARAM;
4474 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4475 &vsi->sib_vsi_list, list);
4477 /* Remove all switch element of the VSI */
4478 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4479 if (ret != I40E_SUCCESS)
4480 PMD_DRV_LOG(ERR, "Failed to delete element");
4483 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4485 if (vsi->type != I40E_VSI_SRIOV)
4486 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4489 return I40E_SUCCESS;
4493 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4495 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4496 struct i40e_aqc_remove_macvlan_element_data def_filter;
4497 struct i40e_mac_filter_info filter;
4500 if (vsi->type != I40E_VSI_MAIN)
4501 return I40E_ERR_CONFIG;
4502 memset(&def_filter, 0, sizeof(def_filter));
4503 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4505 def_filter.vlan_tag = 0;
4506 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4507 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4508 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4509 if (ret != I40E_SUCCESS) {
4510 struct i40e_mac_filter *f;
4511 struct ether_addr *mac;
4513 PMD_DRV_LOG(WARNING,
4514 "Cannot remove the default macvlan filter");
4515 /* It needs to add the permanent mac into mac list */
4516 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4518 PMD_DRV_LOG(ERR, "failed to allocate memory");
4519 return I40E_ERR_NO_MEMORY;
4521 mac = &f->mac_info.mac_addr;
4522 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4524 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4525 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4530 (void)rte_memcpy(&filter.mac_addr,
4531 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4532 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4533 return i40e_vsi_add_mac(vsi, &filter);
4537 * i40e_vsi_get_bw_config - Query VSI BW Information
4538 * @vsi: the VSI to be queried
4540 * Returns 0 on success, negative value on failure
4542 static enum i40e_status_code
4543 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4545 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4546 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4547 struct i40e_hw *hw = &vsi->adapter->hw;
4552 memset(&bw_config, 0, sizeof(bw_config));
4553 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4554 if (ret != I40E_SUCCESS) {
4555 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4556 hw->aq.asq_last_status);
4560 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4561 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4562 &ets_sla_config, NULL);
4563 if (ret != I40E_SUCCESS) {
4565 "VSI failed to get TC bandwdith configuration %u",
4566 hw->aq.asq_last_status);
4570 /* store and print out BW info */
4571 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4572 vsi->bw_info.bw_max = bw_config.max_bw;
4573 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4574 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4575 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4576 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4578 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4579 vsi->bw_info.bw_ets_share_credits[i] =
4580 ets_sla_config.share_credits[i];
4581 vsi->bw_info.bw_ets_credits[i] =
4582 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4583 /* 4 bits per TC, 4th bit is reserved */
4584 vsi->bw_info.bw_ets_max[i] =
4585 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4586 RTE_LEN2MASK(3, uint8_t));
4587 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4588 vsi->bw_info.bw_ets_share_credits[i]);
4589 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4590 vsi->bw_info.bw_ets_credits[i]);
4591 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4592 vsi->bw_info.bw_ets_max[i]);
4595 return I40E_SUCCESS;
4598 /* i40e_enable_pf_lb
4599 * @pf: pointer to the pf structure
4601 * allow loopback on pf
4604 i40e_enable_pf_lb(struct i40e_pf *pf)
4606 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4607 struct i40e_vsi_context ctxt;
4610 /* Use the FW API if FW >= v5.0 */
4611 if (hw->aq.fw_maj_ver < 5) {
4612 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4616 memset(&ctxt, 0, sizeof(ctxt));
4617 ctxt.seid = pf->main_vsi_seid;
4618 ctxt.pf_num = hw->pf_id;
4619 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4621 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4622 ret, hw->aq.asq_last_status);
4625 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4626 ctxt.info.valid_sections =
4627 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4628 ctxt.info.switch_id |=
4629 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4631 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4633 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4634 hw->aq.asq_last_status);
4639 i40e_vsi_setup(struct i40e_pf *pf,
4640 enum i40e_vsi_type type,
4641 struct i40e_vsi *uplink_vsi,
4642 uint16_t user_param)
4644 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4645 struct i40e_vsi *vsi;
4646 struct i40e_mac_filter_info filter;
4648 struct i40e_vsi_context ctxt;
4649 struct ether_addr broadcast =
4650 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4652 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4653 uplink_vsi == NULL) {
4655 "VSI setup failed, VSI link shouldn't be NULL");
4659 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4661 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4666 * 1.type is not MAIN and uplink vsi is not NULL
4667 * If uplink vsi didn't setup VEB, create one first under veb field
4668 * 2.type is SRIOV and the uplink is NULL
4669 * If floating VEB is NULL, create one veb under floating veb field
4672 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4673 uplink_vsi->veb == NULL) {
4674 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4676 if (uplink_vsi->veb == NULL) {
4677 PMD_DRV_LOG(ERR, "VEB setup failed");
4680 /* set ALLOWLOOPBACk on pf, when veb is created */
4681 i40e_enable_pf_lb(pf);
4684 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4685 pf->main_vsi->floating_veb == NULL) {
4686 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4688 if (pf->main_vsi->floating_veb == NULL) {
4689 PMD_DRV_LOG(ERR, "VEB setup failed");
4694 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4696 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4699 TAILQ_INIT(&vsi->mac_list);
4701 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4702 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4703 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4704 vsi->user_param = user_param;
4705 vsi->vlan_anti_spoof_on = 0;
4706 vsi->vlan_filter_on = 0;
4707 /* Allocate queues */
4708 switch (vsi->type) {
4709 case I40E_VSI_MAIN :
4710 vsi->nb_qps = pf->lan_nb_qps;
4712 case I40E_VSI_SRIOV :
4713 vsi->nb_qps = pf->vf_nb_qps;
4715 case I40E_VSI_VMDQ2:
4716 vsi->nb_qps = pf->vmdq_nb_qps;
4719 vsi->nb_qps = pf->fdir_nb_qps;
4725 * The filter status descriptor is reported in rx queue 0,
4726 * while the tx queue for fdir filter programming has no
4727 * such constraints, can be non-zero queues.
4728 * To simplify it, choose FDIR vsi use queue 0 pair.
4729 * To make sure it will use queue 0 pair, queue allocation
4730 * need be done before this function is called
4732 if (type != I40E_VSI_FDIR) {
4733 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4735 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4739 vsi->base_queue = ret;
4741 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4743 /* VF has MSIX interrupt in VF range, don't allocate here */
4744 if (type == I40E_VSI_MAIN) {
4745 ret = i40e_res_pool_alloc(&pf->msix_pool,
4746 RTE_MIN(vsi->nb_qps,
4747 RTE_MAX_RXTX_INTR_VEC_ID));
4749 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4751 goto fail_queue_alloc;
4753 vsi->msix_intr = ret;
4754 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4755 } else if (type != I40E_VSI_SRIOV) {
4756 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4758 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4759 goto fail_queue_alloc;
4761 vsi->msix_intr = ret;
4769 if (type == I40E_VSI_MAIN) {
4770 /* For main VSI, no need to add since it's default one */
4771 vsi->uplink_seid = pf->mac_seid;
4772 vsi->seid = pf->main_vsi_seid;
4773 /* Bind queues with specific MSIX interrupt */
4775 * Needs 2 interrupt at least, one for misc cause which will
4776 * enabled from OS side, Another for queues binding the
4777 * interrupt from device side only.
4780 /* Get default VSI parameters from hardware */
4781 memset(&ctxt, 0, sizeof(ctxt));
4782 ctxt.seid = vsi->seid;
4783 ctxt.pf_num = hw->pf_id;
4784 ctxt.uplink_seid = vsi->uplink_seid;
4786 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4787 if (ret != I40E_SUCCESS) {
4788 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4789 goto fail_msix_alloc;
4791 (void)rte_memcpy(&vsi->info, &ctxt.info,
4792 sizeof(struct i40e_aqc_vsi_properties_data));
4793 vsi->vsi_id = ctxt.vsi_number;
4794 vsi->info.valid_sections = 0;
4796 /* Configure tc, enabled TC0 only */
4797 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4799 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4800 goto fail_msix_alloc;
4803 /* TC, queue mapping */
4804 memset(&ctxt, 0, sizeof(ctxt));
4805 vsi->info.valid_sections |=
4806 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4807 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4808 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4809 (void)rte_memcpy(&ctxt.info, &vsi->info,
4810 sizeof(struct i40e_aqc_vsi_properties_data));
4811 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4812 I40E_DEFAULT_TCMAP);
4813 if (ret != I40E_SUCCESS) {
4815 "Failed to configure TC queue mapping");
4816 goto fail_msix_alloc;
4818 ctxt.seid = vsi->seid;
4819 ctxt.pf_num = hw->pf_id;
4820 ctxt.uplink_seid = vsi->uplink_seid;
4823 /* Update VSI parameters */
4824 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4825 if (ret != I40E_SUCCESS) {
4826 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4827 goto fail_msix_alloc;
4830 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4831 sizeof(vsi->info.tc_mapping));
4832 (void)rte_memcpy(&vsi->info.queue_mapping,
4833 &ctxt.info.queue_mapping,
4834 sizeof(vsi->info.queue_mapping));
4835 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4836 vsi->info.valid_sections = 0;
4838 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4842 * Updating default filter settings are necessary to prevent
4843 * reception of tagged packets.
4844 * Some old firmware configurations load a default macvlan
4845 * filter which accepts both tagged and untagged packets.
4846 * The updating is to use a normal filter instead if needed.
4847 * For NVM 4.2.2 or after, the updating is not needed anymore.
4848 * The firmware with correct configurations load the default
4849 * macvlan filter which is expected and cannot be removed.
4851 i40e_update_default_filter_setting(vsi);
4852 i40e_config_qinq(hw, vsi);
4853 } else if (type == I40E_VSI_SRIOV) {
4854 memset(&ctxt, 0, sizeof(ctxt));
4856 * For other VSI, the uplink_seid equals to uplink VSI's
4857 * uplink_seid since they share same VEB
4859 if (uplink_vsi == NULL)
4860 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4862 vsi->uplink_seid = uplink_vsi->uplink_seid;
4863 ctxt.pf_num = hw->pf_id;
4864 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4865 ctxt.uplink_seid = vsi->uplink_seid;
4866 ctxt.connection_type = 0x1;
4867 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4869 /* Use the VEB configuration if FW >= v5.0 */
4870 if (hw->aq.fw_maj_ver >= 5) {
4871 /* Configure switch ID */
4872 ctxt.info.valid_sections |=
4873 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4874 ctxt.info.switch_id =
4875 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4878 /* Configure port/vlan */
4879 ctxt.info.valid_sections |=
4880 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4881 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4882 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4883 hw->func_caps.enabled_tcmap);
4884 if (ret != I40E_SUCCESS) {
4886 "Failed to configure TC queue mapping");
4887 goto fail_msix_alloc;
4890 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4891 ctxt.info.valid_sections |=
4892 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4894 * Since VSI is not created yet, only configure parameter,
4895 * will add vsi below.
4898 i40e_config_qinq(hw, vsi);
4899 } else if (type == I40E_VSI_VMDQ2) {
4900 memset(&ctxt, 0, sizeof(ctxt));
4902 * For other VSI, the uplink_seid equals to uplink VSI's
4903 * uplink_seid since they share same VEB
4905 vsi->uplink_seid = uplink_vsi->uplink_seid;
4906 ctxt.pf_num = hw->pf_id;
4908 ctxt.uplink_seid = vsi->uplink_seid;
4909 ctxt.connection_type = 0x1;
4910 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4912 ctxt.info.valid_sections |=
4913 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4914 /* user_param carries flag to enable loop back */
4916 ctxt.info.switch_id =
4917 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4918 ctxt.info.switch_id |=
4919 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4922 /* Configure port/vlan */
4923 ctxt.info.valid_sections |=
4924 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4925 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4926 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4927 I40E_DEFAULT_TCMAP);
4928 if (ret != I40E_SUCCESS) {
4930 "Failed to configure TC queue mapping");
4931 goto fail_msix_alloc;
4933 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4934 ctxt.info.valid_sections |=
4935 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4936 } else if (type == I40E_VSI_FDIR) {
4937 memset(&ctxt, 0, sizeof(ctxt));
4938 vsi->uplink_seid = uplink_vsi->uplink_seid;
4939 ctxt.pf_num = hw->pf_id;
4941 ctxt.uplink_seid = vsi->uplink_seid;
4942 ctxt.connection_type = 0x1; /* regular data port */
4943 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4944 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4945 I40E_DEFAULT_TCMAP);
4946 if (ret != I40E_SUCCESS) {
4948 "Failed to configure TC queue mapping.");
4949 goto fail_msix_alloc;
4951 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4952 ctxt.info.valid_sections |=
4953 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4955 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4956 goto fail_msix_alloc;
4959 if (vsi->type != I40E_VSI_MAIN) {
4960 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4961 if (ret != I40E_SUCCESS) {
4962 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4963 hw->aq.asq_last_status);
4964 goto fail_msix_alloc;
4966 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4967 vsi->info.valid_sections = 0;
4968 vsi->seid = ctxt.seid;
4969 vsi->vsi_id = ctxt.vsi_number;
4970 vsi->sib_vsi_list.vsi = vsi;
4971 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4972 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4973 &vsi->sib_vsi_list, list);
4975 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4976 &vsi->sib_vsi_list, list);
4980 /* MAC/VLAN configuration */
4981 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4982 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4984 ret = i40e_vsi_add_mac(vsi, &filter);
4985 if (ret != I40E_SUCCESS) {
4986 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4987 goto fail_msix_alloc;
4990 /* Get VSI BW information */
4991 i40e_vsi_get_bw_config(vsi);
4994 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4996 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5002 /* Configure vlan filter on or off */
5004 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5007 struct i40e_mac_filter *f;
5009 struct i40e_mac_filter_info *mac_filter;
5010 enum rte_mac_filter_type desired_filter;
5011 int ret = I40E_SUCCESS;
5014 /* Filter to match MAC and VLAN */
5015 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5017 /* Filter to match only MAC */
5018 desired_filter = RTE_MAC_PERFECT_MATCH;
5023 mac_filter = rte_zmalloc("mac_filter_info_data",
5024 num * sizeof(*mac_filter), 0);
5025 if (mac_filter == NULL) {
5026 PMD_DRV_LOG(ERR, "failed to allocate memory");
5027 return I40E_ERR_NO_MEMORY;
5032 /* Remove all existing mac */
5033 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5034 mac_filter[i] = f->mac_info;
5035 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5037 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5038 on ? "enable" : "disable");
5044 /* Override with new filter */
5045 for (i = 0; i < num; i++) {
5046 mac_filter[i].filter_type = desired_filter;
5047 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5049 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5050 on ? "enable" : "disable");
5056 rte_free(mac_filter);
5060 /* Configure vlan stripping on or off */
5062 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5064 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5065 struct i40e_vsi_context ctxt;
5067 int ret = I40E_SUCCESS;
5069 /* Check if it has been already on or off */
5070 if (vsi->info.valid_sections &
5071 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5073 if ((vsi->info.port_vlan_flags &
5074 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5075 return 0; /* already on */
5077 if ((vsi->info.port_vlan_flags &
5078 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5079 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5080 return 0; /* already off */
5085 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5087 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5088 vsi->info.valid_sections =
5089 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5090 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5091 vsi->info.port_vlan_flags |= vlan_flags;
5092 ctxt.seid = vsi->seid;
5093 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5094 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5096 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5097 on ? "enable" : "disable");
5103 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5105 struct rte_eth_dev_data *data = dev->data;
5109 /* Apply vlan offload setting */
5110 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5111 i40e_vlan_offload_set(dev, mask);
5113 /* Apply double-vlan setting, not implemented yet */
5115 /* Apply pvid setting */
5116 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5117 data->dev_conf.txmode.hw_vlan_insert_pvid);
5119 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5125 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5127 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5129 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5133 i40e_update_flow_control(struct i40e_hw *hw)
5135 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5136 struct i40e_link_status link_status;
5137 uint32_t rxfc = 0, txfc = 0, reg;
5141 memset(&link_status, 0, sizeof(link_status));
5142 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5143 if (ret != I40E_SUCCESS) {
5144 PMD_DRV_LOG(ERR, "Failed to get link status information");
5145 goto write_reg; /* Disable flow control */
5148 an_info = hw->phy.link_info.an_info;
5149 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5150 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5151 ret = I40E_ERR_NOT_READY;
5152 goto write_reg; /* Disable flow control */
5155 * If link auto negotiation is enabled, flow control needs to
5156 * be configured according to it
5158 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5159 case I40E_LINK_PAUSE_RXTX:
5162 hw->fc.current_mode = I40E_FC_FULL;
5164 case I40E_AQ_LINK_PAUSE_RX:
5166 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5168 case I40E_AQ_LINK_PAUSE_TX:
5170 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5173 hw->fc.current_mode = I40E_FC_NONE;
5178 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5179 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5180 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5181 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5182 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5183 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5190 i40e_pf_setup(struct i40e_pf *pf)
5192 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5193 struct i40e_filter_control_settings settings;
5194 struct i40e_vsi *vsi;
5197 /* Clear all stats counters */
5198 pf->offset_loaded = FALSE;
5199 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5200 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5202 ret = i40e_pf_get_switch_config(pf);
5203 if (ret != I40E_SUCCESS) {
5204 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5207 if (pf->flags & I40E_FLAG_FDIR) {
5208 /* make queue allocated first, let FDIR use queue pair 0*/
5209 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5210 if (ret != I40E_FDIR_QUEUE_ID) {
5212 "queue allocation fails for FDIR: ret =%d",
5214 pf->flags &= ~I40E_FLAG_FDIR;
5217 /* main VSI setup */
5218 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5220 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5221 return I40E_ERR_NOT_READY;
5225 /* Configure filter control */
5226 memset(&settings, 0, sizeof(settings));
5227 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5228 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5229 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5230 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5232 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5233 hw->func_caps.rss_table_size);
5234 return I40E_ERR_PARAM;
5236 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5237 hw->func_caps.rss_table_size);
5238 pf->hash_lut_size = hw->func_caps.rss_table_size;
5240 /* Enable ethtype and macvlan filters */
5241 settings.enable_ethtype = TRUE;
5242 settings.enable_macvlan = TRUE;
5243 ret = i40e_set_filter_control(hw, &settings);
5245 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5248 /* Update flow control according to the auto negotiation */
5249 i40e_update_flow_control(hw);
5251 return I40E_SUCCESS;
5255 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5261 * Set or clear TX Queue Disable flags,
5262 * which is required by hardware.
5264 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5265 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5267 /* Wait until the request is finished */
5268 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5269 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5270 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5271 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5272 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5278 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5279 return I40E_SUCCESS; /* already on, skip next steps */
5281 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5282 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5284 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5285 return I40E_SUCCESS; /* already off, skip next steps */
5286 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5288 /* Write the register */
5289 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5290 /* Check the result */
5291 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5292 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5293 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5295 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5296 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5299 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5300 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5304 /* Check if it is timeout */
5305 if (j >= I40E_CHK_Q_ENA_COUNT) {
5306 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5307 (on ? "enable" : "disable"), q_idx);
5308 return I40E_ERR_TIMEOUT;
5311 return I40E_SUCCESS;
5314 /* Swith on or off the tx queues */
5316 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5318 struct rte_eth_dev_data *dev_data = pf->dev_data;
5319 struct i40e_tx_queue *txq;
5320 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5324 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5325 txq = dev_data->tx_queues[i];
5326 /* Don't operate the queue if not configured or
5327 * if starting only per queue */
5328 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5331 ret = i40e_dev_tx_queue_start(dev, i);
5333 ret = i40e_dev_tx_queue_stop(dev, i);
5334 if ( ret != I40E_SUCCESS)
5338 return I40E_SUCCESS;
5342 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5347 /* Wait until the request is finished */
5348 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5349 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5350 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5351 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5352 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5357 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5358 return I40E_SUCCESS; /* Already on, skip next steps */
5359 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5361 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5362 return I40E_SUCCESS; /* Already off, skip next steps */
5363 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5366 /* Write the register */
5367 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5368 /* Check the result */
5369 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5370 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5371 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5373 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5374 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5377 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5378 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5383 /* Check if it is timeout */
5384 if (j >= I40E_CHK_Q_ENA_COUNT) {
5385 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5386 (on ? "enable" : "disable"), q_idx);
5387 return I40E_ERR_TIMEOUT;
5390 return I40E_SUCCESS;
5392 /* Switch on or off the rx queues */
5394 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5396 struct rte_eth_dev_data *dev_data = pf->dev_data;
5397 struct i40e_rx_queue *rxq;
5398 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5402 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5403 rxq = dev_data->rx_queues[i];
5404 /* Don't operate the queue if not configured or
5405 * if starting only per queue */
5406 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5409 ret = i40e_dev_rx_queue_start(dev, i);
5411 ret = i40e_dev_rx_queue_stop(dev, i);
5412 if (ret != I40E_SUCCESS)
5416 return I40E_SUCCESS;
5419 /* Switch on or off all the rx/tx queues */
5421 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5426 /* enable rx queues before enabling tx queues */
5427 ret = i40e_dev_switch_rx_queues(pf, on);
5429 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5432 ret = i40e_dev_switch_tx_queues(pf, on);
5434 /* Stop tx queues before stopping rx queues */
5435 ret = i40e_dev_switch_tx_queues(pf, on);
5437 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5440 ret = i40e_dev_switch_rx_queues(pf, on);
5446 /* Initialize VSI for TX */
5448 i40e_dev_tx_init(struct i40e_pf *pf)
5450 struct rte_eth_dev_data *data = pf->dev_data;
5452 uint32_t ret = I40E_SUCCESS;
5453 struct i40e_tx_queue *txq;
5455 for (i = 0; i < data->nb_tx_queues; i++) {
5456 txq = data->tx_queues[i];
5457 if (!txq || !txq->q_set)
5459 ret = i40e_tx_queue_init(txq);
5460 if (ret != I40E_SUCCESS)
5463 if (ret == I40E_SUCCESS)
5464 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5470 /* Initialize VSI for RX */
5472 i40e_dev_rx_init(struct i40e_pf *pf)
5474 struct rte_eth_dev_data *data = pf->dev_data;
5475 int ret = I40E_SUCCESS;
5477 struct i40e_rx_queue *rxq;
5479 i40e_pf_config_mq_rx(pf);
5480 for (i = 0; i < data->nb_rx_queues; i++) {
5481 rxq = data->rx_queues[i];
5482 if (!rxq || !rxq->q_set)
5485 ret = i40e_rx_queue_init(rxq);
5486 if (ret != I40E_SUCCESS) {
5488 "Failed to do RX queue initialization");
5492 if (ret == I40E_SUCCESS)
5493 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5500 i40e_dev_rxtx_init(struct i40e_pf *pf)
5504 err = i40e_dev_tx_init(pf);
5506 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5509 err = i40e_dev_rx_init(pf);
5511 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5519 i40e_vmdq_setup(struct rte_eth_dev *dev)
5521 struct rte_eth_conf *conf = &dev->data->dev_conf;
5522 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5523 int i, err, conf_vsis, j, loop;
5524 struct i40e_vsi *vsi;
5525 struct i40e_vmdq_info *vmdq_info;
5526 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5527 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5530 * Disable interrupt to avoid message from VF. Furthermore, it will
5531 * avoid race condition in VSI creation/destroy.
5533 i40e_pf_disable_irq0(hw);
5535 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5536 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5540 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5541 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5542 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5543 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5544 pf->max_nb_vmdq_vsi);
5548 if (pf->vmdq != NULL) {
5549 PMD_INIT_LOG(INFO, "VMDQ already configured");
5553 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5554 sizeof(*vmdq_info) * conf_vsis, 0);
5556 if (pf->vmdq == NULL) {
5557 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5561 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5563 /* Create VMDQ VSI */
5564 for (i = 0; i < conf_vsis; i++) {
5565 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5566 vmdq_conf->enable_loop_back);
5568 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5572 vmdq_info = &pf->vmdq[i];
5574 vmdq_info->vsi = vsi;
5576 pf->nb_cfg_vmdq_vsi = conf_vsis;
5578 /* Configure Vlan */
5579 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5580 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5581 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5582 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5583 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5584 vmdq_conf->pool_map[i].vlan_id, j);
5586 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5587 vmdq_conf->pool_map[i].vlan_id);
5589 PMD_INIT_LOG(ERR, "Failed to add vlan");
5597 i40e_pf_enable_irq0(hw);
5602 for (i = 0; i < conf_vsis; i++)
5603 if (pf->vmdq[i].vsi == NULL)
5606 i40e_vsi_release(pf->vmdq[i].vsi);
5610 i40e_pf_enable_irq0(hw);
5615 i40e_stat_update_32(struct i40e_hw *hw,
5623 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5627 if (new_data >= *offset)
5628 *stat = (uint64_t)(new_data - *offset);
5630 *stat = (uint64_t)((new_data +
5631 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5635 i40e_stat_update_48(struct i40e_hw *hw,
5644 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5645 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5646 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5651 if (new_data >= *offset)
5652 *stat = new_data - *offset;
5654 *stat = (uint64_t)((new_data +
5655 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5657 *stat &= I40E_48_BIT_MASK;
5662 i40e_pf_disable_irq0(struct i40e_hw *hw)
5664 /* Disable all interrupt types */
5665 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5666 I40E_WRITE_FLUSH(hw);
5671 i40e_pf_enable_irq0(struct i40e_hw *hw)
5673 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5674 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5675 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5676 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5677 I40E_WRITE_FLUSH(hw);
5681 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5683 /* read pending request and disable first */
5684 i40e_pf_disable_irq0(hw);
5685 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5686 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5687 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5690 /* Link no queues with irq0 */
5691 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5692 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5696 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5698 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5699 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5702 uint32_t index, offset, val;
5707 * Try to find which VF trigger a reset, use absolute VF id to access
5708 * since the reg is global register.
5710 for (i = 0; i < pf->vf_num; i++) {
5711 abs_vf_id = hw->func_caps.vf_base_id + i;
5712 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5713 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5714 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5715 /* VFR event occured */
5716 if (val & (0x1 << offset)) {
5719 /* Clear the event first */
5720 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5722 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5724 * Only notify a VF reset event occured,
5725 * don't trigger another SW reset
5727 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5728 if (ret != I40E_SUCCESS)
5729 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5735 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5737 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5738 struct i40e_virtchnl_pf_event event;
5741 event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5742 event.event_data.link_event.link_status =
5743 dev->data->dev_link.link_status;
5744 event.event_data.link_event.link_speed =
5745 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5747 for (i = 0; i < pf->vf_num; i++)
5748 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5749 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5753 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5755 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5756 struct i40e_arq_event_info info;
5757 uint16_t pending, opcode;
5760 info.buf_len = I40E_AQ_BUF_SZ;
5761 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5762 if (!info.msg_buf) {
5763 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5769 ret = i40e_clean_arq_element(hw, &info, &pending);
5771 if (ret != I40E_SUCCESS) {
5773 "Failed to read msg from AdminQ, aq_err: %u",
5774 hw->aq.asq_last_status);
5777 opcode = rte_le_to_cpu_16(info.desc.opcode);
5780 case i40e_aqc_opc_send_msg_to_pf:
5781 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5782 i40e_pf_host_handle_vf_msg(dev,
5783 rte_le_to_cpu_16(info.desc.retval),
5784 rte_le_to_cpu_32(info.desc.cookie_high),
5785 rte_le_to_cpu_32(info.desc.cookie_low),
5789 case i40e_aqc_opc_get_link_status:
5790 ret = i40e_dev_link_update(dev, 0);
5792 i40e_notify_all_vfs_link_status(dev);
5793 _rte_eth_dev_callback_process(dev,
5794 RTE_ETH_EVENT_INTR_LSC, NULL);
5798 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5803 rte_free(info.msg_buf);
5807 * Interrupt handler triggered by NIC for handling
5808 * specific interrupt.
5811 * Pointer to interrupt handle.
5813 * The address of parameter (struct rte_eth_dev *) regsitered before.
5819 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5822 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5823 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5826 /* Disable interrupt */
5827 i40e_pf_disable_irq0(hw);
5829 /* read out interrupt causes */
5830 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5832 /* No interrupt event indicated */
5833 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5834 PMD_DRV_LOG(INFO, "No interrupt event");
5837 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5838 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5839 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5840 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5841 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5842 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5843 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5844 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5845 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5846 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5847 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5848 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5849 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5850 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5852 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5853 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5854 i40e_dev_handle_vfr_event(dev);
5856 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5857 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5858 i40e_dev_handle_aq_msg(dev);
5862 /* Enable interrupt */
5863 i40e_pf_enable_irq0(hw);
5864 rte_intr_enable(intr_handle);
5868 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5869 struct i40e_macvlan_filter *filter,
5872 int ele_num, ele_buff_size;
5873 int num, actual_num, i;
5875 int ret = I40E_SUCCESS;
5876 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5877 struct i40e_aqc_add_macvlan_element_data *req_list;
5879 if (filter == NULL || total == 0)
5880 return I40E_ERR_PARAM;
5881 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5882 ele_buff_size = hw->aq.asq_buf_size;
5884 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5885 if (req_list == NULL) {
5886 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5887 return I40E_ERR_NO_MEMORY;
5892 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5893 memset(req_list, 0, ele_buff_size);
5895 for (i = 0; i < actual_num; i++) {
5896 (void)rte_memcpy(req_list[i].mac_addr,
5897 &filter[num + i].macaddr, ETH_ADDR_LEN);
5898 req_list[i].vlan_tag =
5899 rte_cpu_to_le_16(filter[num + i].vlan_id);
5901 switch (filter[num + i].filter_type) {
5902 case RTE_MAC_PERFECT_MATCH:
5903 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5904 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5906 case RTE_MACVLAN_PERFECT_MATCH:
5907 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5909 case RTE_MAC_HASH_MATCH:
5910 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5911 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5913 case RTE_MACVLAN_HASH_MATCH:
5914 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5917 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5918 ret = I40E_ERR_PARAM;
5922 req_list[i].queue_number = 0;
5924 req_list[i].flags = rte_cpu_to_le_16(flags);
5927 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5929 if (ret != I40E_SUCCESS) {
5930 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5934 } while (num < total);
5942 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5943 struct i40e_macvlan_filter *filter,
5946 int ele_num, ele_buff_size;
5947 int num, actual_num, i;
5949 int ret = I40E_SUCCESS;
5950 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5951 struct i40e_aqc_remove_macvlan_element_data *req_list;
5953 if (filter == NULL || total == 0)
5954 return I40E_ERR_PARAM;
5956 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5957 ele_buff_size = hw->aq.asq_buf_size;
5959 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5960 if (req_list == NULL) {
5961 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5962 return I40E_ERR_NO_MEMORY;
5967 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5968 memset(req_list, 0, ele_buff_size);
5970 for (i = 0; i < actual_num; i++) {
5971 (void)rte_memcpy(req_list[i].mac_addr,
5972 &filter[num + i].macaddr, ETH_ADDR_LEN);
5973 req_list[i].vlan_tag =
5974 rte_cpu_to_le_16(filter[num + i].vlan_id);
5976 switch (filter[num + i].filter_type) {
5977 case RTE_MAC_PERFECT_MATCH:
5978 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5979 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5981 case RTE_MACVLAN_PERFECT_MATCH:
5982 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5984 case RTE_MAC_HASH_MATCH:
5985 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5986 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5988 case RTE_MACVLAN_HASH_MATCH:
5989 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5992 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5993 ret = I40E_ERR_PARAM;
5996 req_list[i].flags = rte_cpu_to_le_16(flags);
5999 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6001 if (ret != I40E_SUCCESS) {
6002 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6006 } while (num < total);
6013 /* Find out specific MAC filter */
6014 static struct i40e_mac_filter *
6015 i40e_find_mac_filter(struct i40e_vsi *vsi,
6016 struct ether_addr *macaddr)
6018 struct i40e_mac_filter *f;
6020 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6021 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6029 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6032 uint32_t vid_idx, vid_bit;
6034 if (vlan_id > ETH_VLAN_ID_MAX)
6037 vid_idx = I40E_VFTA_IDX(vlan_id);
6038 vid_bit = I40E_VFTA_BIT(vlan_id);
6040 if (vsi->vfta[vid_idx] & vid_bit)
6047 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6048 uint16_t vlan_id, bool on)
6050 uint32_t vid_idx, vid_bit;
6052 vid_idx = I40E_VFTA_IDX(vlan_id);
6053 vid_bit = I40E_VFTA_BIT(vlan_id);
6056 vsi->vfta[vid_idx] |= vid_bit;
6058 vsi->vfta[vid_idx] &= ~vid_bit;
6062 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6063 uint16_t vlan_id, bool on)
6065 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6066 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6069 if (vlan_id > ETH_VLAN_ID_MAX)
6072 i40e_store_vlan_filter(vsi, vlan_id, on);
6074 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6077 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6080 ret = i40e_aq_add_vlan(hw, vsi->seid,
6081 &vlan_data, 1, NULL);
6082 if (ret != I40E_SUCCESS)
6083 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6085 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6086 &vlan_data, 1, NULL);
6087 if (ret != I40E_SUCCESS)
6089 "Failed to remove vlan filter");
6094 * Find all vlan options for specific mac addr,
6095 * return with actual vlan found.
6098 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6099 struct i40e_macvlan_filter *mv_f,
6100 int num, struct ether_addr *addr)
6106 * Not to use i40e_find_vlan_filter to decrease the loop time,
6107 * although the code looks complex.
6109 if (num < vsi->vlan_num)
6110 return I40E_ERR_PARAM;
6113 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6115 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6116 if (vsi->vfta[j] & (1 << k)) {
6119 "vlan number doesn't match");
6120 return I40E_ERR_PARAM;
6122 (void)rte_memcpy(&mv_f[i].macaddr,
6123 addr, ETH_ADDR_LEN);
6125 j * I40E_UINT32_BIT_SIZE + k;
6131 return I40E_SUCCESS;
6135 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6136 struct i40e_macvlan_filter *mv_f,
6141 struct i40e_mac_filter *f;
6143 if (num < vsi->mac_num)
6144 return I40E_ERR_PARAM;
6146 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6148 PMD_DRV_LOG(ERR, "buffer number not match");
6149 return I40E_ERR_PARAM;
6151 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6153 mv_f[i].vlan_id = vlan;
6154 mv_f[i].filter_type = f->mac_info.filter_type;
6158 return I40E_SUCCESS;
6162 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6165 struct i40e_mac_filter *f;
6166 struct i40e_macvlan_filter *mv_f;
6167 int ret = I40E_SUCCESS;
6169 if (vsi == NULL || vsi->mac_num == 0)
6170 return I40E_ERR_PARAM;
6172 /* Case that no vlan is set */
6173 if (vsi->vlan_num == 0)
6176 num = vsi->mac_num * vsi->vlan_num;
6178 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6180 PMD_DRV_LOG(ERR, "failed to allocate memory");
6181 return I40E_ERR_NO_MEMORY;
6185 if (vsi->vlan_num == 0) {
6186 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6187 (void)rte_memcpy(&mv_f[i].macaddr,
6188 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6189 mv_f[i].filter_type = f->mac_info.filter_type;
6190 mv_f[i].vlan_id = 0;
6194 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6195 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6196 vsi->vlan_num, &f->mac_info.mac_addr);
6197 if (ret != I40E_SUCCESS)
6199 for (j = i; j < i + vsi->vlan_num; j++)
6200 mv_f[j].filter_type = f->mac_info.filter_type;
6205 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6213 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6215 struct i40e_macvlan_filter *mv_f;
6217 int ret = I40E_SUCCESS;
6219 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6220 return I40E_ERR_PARAM;
6222 /* If it's already set, just return */
6223 if (i40e_find_vlan_filter(vsi,vlan))
6224 return I40E_SUCCESS;
6226 mac_num = vsi->mac_num;
6229 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6230 return I40E_ERR_PARAM;
6233 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6236 PMD_DRV_LOG(ERR, "failed to allocate memory");
6237 return I40E_ERR_NO_MEMORY;
6240 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6242 if (ret != I40E_SUCCESS)
6245 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6247 if (ret != I40E_SUCCESS)
6250 i40e_set_vlan_filter(vsi, vlan, 1);
6260 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6262 struct i40e_macvlan_filter *mv_f;
6264 int ret = I40E_SUCCESS;
6267 * Vlan 0 is the generic filter for untagged packets
6268 * and can't be removed.
6270 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6271 return I40E_ERR_PARAM;
6273 /* If can't find it, just return */
6274 if (!i40e_find_vlan_filter(vsi, vlan))
6275 return I40E_ERR_PARAM;
6277 mac_num = vsi->mac_num;
6280 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6281 return I40E_ERR_PARAM;
6284 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6287 PMD_DRV_LOG(ERR, "failed to allocate memory");
6288 return I40E_ERR_NO_MEMORY;
6291 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6293 if (ret != I40E_SUCCESS)
6296 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6298 if (ret != I40E_SUCCESS)
6301 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6302 if (vsi->vlan_num == 1) {
6303 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6304 if (ret != I40E_SUCCESS)
6307 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6308 if (ret != I40E_SUCCESS)
6312 i40e_set_vlan_filter(vsi, vlan, 0);
6322 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6324 struct i40e_mac_filter *f;
6325 struct i40e_macvlan_filter *mv_f;
6326 int i, vlan_num = 0;
6327 int ret = I40E_SUCCESS;
6329 /* If it's add and we've config it, return */
6330 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6332 return I40E_SUCCESS;
6333 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6334 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6337 * If vlan_num is 0, that's the first time to add mac,
6338 * set mask for vlan_id 0.
6340 if (vsi->vlan_num == 0) {
6341 i40e_set_vlan_filter(vsi, 0, 1);
6344 vlan_num = vsi->vlan_num;
6345 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6346 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6349 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6351 PMD_DRV_LOG(ERR, "failed to allocate memory");
6352 return I40E_ERR_NO_MEMORY;
6355 for (i = 0; i < vlan_num; i++) {
6356 mv_f[i].filter_type = mac_filter->filter_type;
6357 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6361 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6362 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6363 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6364 &mac_filter->mac_addr);
6365 if (ret != I40E_SUCCESS)
6369 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6370 if (ret != I40E_SUCCESS)
6373 /* Add the mac addr into mac list */
6374 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6376 PMD_DRV_LOG(ERR, "failed to allocate memory");
6377 ret = I40E_ERR_NO_MEMORY;
6380 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6382 f->mac_info.filter_type = mac_filter->filter_type;
6383 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6394 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6396 struct i40e_mac_filter *f;
6397 struct i40e_macvlan_filter *mv_f;
6399 enum rte_mac_filter_type filter_type;
6400 int ret = I40E_SUCCESS;
6402 /* Can't find it, return an error */
6403 f = i40e_find_mac_filter(vsi, addr);
6405 return I40E_ERR_PARAM;
6407 vlan_num = vsi->vlan_num;
6408 filter_type = f->mac_info.filter_type;
6409 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6410 filter_type == RTE_MACVLAN_HASH_MATCH) {
6411 if (vlan_num == 0) {
6412 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6413 return I40E_ERR_PARAM;
6415 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6416 filter_type == RTE_MAC_HASH_MATCH)
6419 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6421 PMD_DRV_LOG(ERR, "failed to allocate memory");
6422 return I40E_ERR_NO_MEMORY;
6425 for (i = 0; i < vlan_num; i++) {
6426 mv_f[i].filter_type = filter_type;
6427 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6430 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6431 filter_type == RTE_MACVLAN_HASH_MATCH) {
6432 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6433 if (ret != I40E_SUCCESS)
6437 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6438 if (ret != I40E_SUCCESS)
6441 /* Remove the mac addr into mac list */
6442 TAILQ_REMOVE(&vsi->mac_list, f, next);
6452 /* Configure hash enable flags for RSS */
6454 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6461 if (flags & ETH_RSS_FRAG_IPV4)
6462 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6463 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6464 if (type == I40E_MAC_X722) {
6465 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6466 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6468 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6470 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6471 if (type == I40E_MAC_X722) {
6472 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6473 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6474 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6476 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6478 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6479 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6480 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6481 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6482 if (flags & ETH_RSS_FRAG_IPV6)
6483 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6484 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6485 if (type == I40E_MAC_X722) {
6486 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6487 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6489 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6491 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6492 if (type == I40E_MAC_X722) {
6493 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6494 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6495 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6497 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6499 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6500 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6501 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6502 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6503 if (flags & ETH_RSS_L2_PAYLOAD)
6504 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6509 /* Parse the hash enable flags */
6511 i40e_parse_hena(uint64_t flags)
6513 uint64_t rss_hf = 0;
6517 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6518 rss_hf |= ETH_RSS_FRAG_IPV4;
6519 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6520 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6521 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6522 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6523 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6524 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6525 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6526 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6527 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6528 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6529 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6530 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6531 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6532 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6533 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6534 rss_hf |= ETH_RSS_FRAG_IPV6;
6535 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6536 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6537 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6538 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6539 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6540 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6541 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6542 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6543 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6544 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6545 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6546 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6547 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6548 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6549 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6550 rss_hf |= ETH_RSS_L2_PAYLOAD;
6557 i40e_pf_disable_rss(struct i40e_pf *pf)
6559 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6562 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6563 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6564 if (hw->mac.type == I40E_MAC_X722)
6565 hena &= ~I40E_RSS_HENA_ALL_X722;
6567 hena &= ~I40E_RSS_HENA_ALL;
6568 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6569 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6570 I40E_WRITE_FLUSH(hw);
6574 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6576 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6577 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6580 if (!key || key_len == 0) {
6581 PMD_DRV_LOG(DEBUG, "No key to be configured");
6583 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6585 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6589 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6590 struct i40e_aqc_get_set_rss_key_data *key_dw =
6591 (struct i40e_aqc_get_set_rss_key_data *)key;
6593 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6595 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6597 uint32_t *hash_key = (uint32_t *)key;
6600 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6601 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6602 I40E_WRITE_FLUSH(hw);
6609 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6611 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6612 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6615 if (!key || !key_len)
6618 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6619 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6620 (struct i40e_aqc_get_set_rss_key_data *)key);
6622 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6626 uint32_t *key_dw = (uint32_t *)key;
6629 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6630 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6632 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6638 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6640 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6645 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6646 rss_conf->rss_key_len);
6650 rss_hf = rss_conf->rss_hf;
6651 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6652 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6653 if (hw->mac.type == I40E_MAC_X722)
6654 hena &= ~I40E_RSS_HENA_ALL_X722;
6656 hena &= ~I40E_RSS_HENA_ALL;
6657 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6658 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6659 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6660 I40E_WRITE_FLUSH(hw);
6666 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6667 struct rte_eth_rss_conf *rss_conf)
6669 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6670 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6671 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6674 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6675 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6676 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6677 ? I40E_RSS_HENA_ALL_X722
6678 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6679 if (rss_hf != 0) /* Enable RSS */
6681 return 0; /* Nothing to do */
6684 if (rss_hf == 0) /* Disable RSS */
6687 return i40e_hw_rss_hash_set(pf, rss_conf);
6691 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6692 struct rte_eth_rss_conf *rss_conf)
6694 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6695 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6698 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6699 &rss_conf->rss_key_len);
6701 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6702 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6703 rss_conf->rss_hf = i40e_parse_hena(hena);
6709 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6711 switch (filter_type) {
6712 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6713 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6715 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6716 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6718 case RTE_TUNNEL_FILTER_IMAC_TENID:
6719 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6721 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6722 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6724 case ETH_TUNNEL_FILTER_IMAC:
6725 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6727 case ETH_TUNNEL_FILTER_OIP:
6728 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6730 case ETH_TUNNEL_FILTER_IIP:
6731 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6734 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6741 /* Convert tunnel filter structure */
6743 i40e_tunnel_filter_convert(
6744 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6745 struct i40e_tunnel_filter *tunnel_filter)
6747 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6748 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6749 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6750 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6751 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6752 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6753 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6754 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6755 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6757 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6758 tunnel_filter->input.flags = cld_filter->element.flags;
6759 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6760 tunnel_filter->queue = cld_filter->element.queue_number;
6761 rte_memcpy(tunnel_filter->input.general_fields,
6762 cld_filter->general_fields,
6763 sizeof(cld_filter->general_fields));
6768 /* Check if there exists the tunnel filter */
6769 struct i40e_tunnel_filter *
6770 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6771 const struct i40e_tunnel_filter_input *input)
6775 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6779 return tunnel_rule->hash_map[ret];
6782 /* Add a tunnel filter into the SW list */
6784 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6785 struct i40e_tunnel_filter *tunnel_filter)
6787 struct i40e_tunnel_rule *rule = &pf->tunnel;
6790 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6793 "Failed to insert tunnel filter to hash table %d!",
6797 rule->hash_map[ret] = tunnel_filter;
6799 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6804 /* Delete a tunnel filter from the SW list */
6806 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6807 struct i40e_tunnel_filter_input *input)
6809 struct i40e_tunnel_rule *rule = &pf->tunnel;
6810 struct i40e_tunnel_filter *tunnel_filter;
6813 ret = rte_hash_del_key(rule->hash_table, input);
6816 "Failed to delete tunnel filter to hash table %d!",
6820 tunnel_filter = rule->hash_map[ret];
6821 rule->hash_map[ret] = NULL;
6823 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6824 rte_free(tunnel_filter);
6830 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6831 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6836 uint8_t i, tun_type = 0;
6837 /* internal varialbe to convert ipv6 byte order */
6838 uint32_t convert_ipv6[4];
6840 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6841 struct i40e_vsi *vsi = pf->main_vsi;
6842 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6843 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6844 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6845 struct i40e_tunnel_filter *tunnel, *node;
6846 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6848 cld_filter = rte_zmalloc("tunnel_filter",
6849 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6852 if (NULL == cld_filter) {
6853 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6856 pfilter = cld_filter;
6858 ether_addr_copy(&tunnel_filter->outer_mac,
6859 (struct ether_addr *)&pfilter->element.outer_mac);
6860 ether_addr_copy(&tunnel_filter->inner_mac,
6861 (struct ether_addr *)&pfilter->element.inner_mac);
6863 pfilter->element.inner_vlan =
6864 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6865 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6866 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6867 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6868 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6869 &rte_cpu_to_le_32(ipv4_addr),
6870 sizeof(pfilter->element.ipaddr.v4.data));
6872 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6873 for (i = 0; i < 4; i++) {
6875 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6877 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6879 sizeof(pfilter->element.ipaddr.v6.data));
6882 /* check tunneled type */
6883 switch (tunnel_filter->tunnel_type) {
6884 case RTE_TUNNEL_TYPE_VXLAN:
6885 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6887 case RTE_TUNNEL_TYPE_NVGRE:
6888 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6890 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6891 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6894 /* Other tunnel types is not supported. */
6895 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6896 rte_free(cld_filter);
6900 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6901 &pfilter->element.flags);
6903 rte_free(cld_filter);
6907 pfilter->element.flags |= rte_cpu_to_le_16(
6908 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6909 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6910 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6911 pfilter->element.queue_number =
6912 rte_cpu_to_le_16(tunnel_filter->queue_id);
6914 /* Check if there is the filter in SW list */
6915 memset(&check_filter, 0, sizeof(check_filter));
6916 i40e_tunnel_filter_convert(cld_filter, &check_filter);
6917 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6919 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6923 if (!add && !node) {
6924 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6929 ret = i40e_aq_add_cloud_filters(hw,
6930 vsi->seid, &cld_filter->element, 1);
6932 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6935 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6936 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6937 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6939 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6940 &cld_filter->element, 1);
6942 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6945 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6948 rte_free(cld_filter);
6952 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
6953 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
6954 #define I40E_TR_GENEVE_KEY_MASK 0x8
6955 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
6956 #define I40E_TR_GRE_KEY_MASK 0x400
6957 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
6958 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
6961 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
6963 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
6964 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
6965 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6966 enum i40e_status_code status = I40E_SUCCESS;
6968 memset(&filter_replace, 0,
6969 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
6970 memset(&filter_replace_buf, 0,
6971 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
6973 /* create L1 filter */
6974 filter_replace.old_filter_type =
6975 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
6976 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
6977 filter_replace.tr_bit = 0;
6979 /* Prepare the buffer, 3 entries */
6980 filter_replace_buf.data[0] =
6981 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
6982 filter_replace_buf.data[0] |=
6983 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6984 filter_replace_buf.data[2] = 0xFF;
6985 filter_replace_buf.data[3] = 0xFF;
6986 filter_replace_buf.data[4] =
6987 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
6988 filter_replace_buf.data[4] |=
6989 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6990 filter_replace_buf.data[7] = 0xF0;
6991 filter_replace_buf.data[8]
6992 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
6993 filter_replace_buf.data[8] |=
6994 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6995 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
6996 I40E_TR_GENEVE_KEY_MASK |
6997 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
6998 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
6999 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7000 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7002 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7003 &filter_replace_buf);
7008 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7010 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7011 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7012 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7013 enum i40e_status_code status = I40E_SUCCESS;
7016 memset(&filter_replace, 0,
7017 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7018 memset(&filter_replace_buf, 0,
7019 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7020 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7021 I40E_AQC_MIRROR_CLOUD_FILTER;
7022 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7023 filter_replace.new_filter_type =
7024 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7025 /* Prepare the buffer, 2 entries */
7026 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7027 filter_replace_buf.data[0] |=
7028 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7029 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7030 filter_replace_buf.data[4] |=
7031 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7032 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7033 &filter_replace_buf);
7038 memset(&filter_replace, 0,
7039 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7040 memset(&filter_replace_buf, 0,
7041 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7043 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7044 I40E_AQC_MIRROR_CLOUD_FILTER;
7045 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7046 filter_replace.new_filter_type =
7047 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7048 /* Prepare the buffer, 2 entries */
7049 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7050 filter_replace_buf.data[0] |=
7051 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7052 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7053 filter_replace_buf.data[4] |=
7054 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7056 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7057 &filter_replace_buf);
7062 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7063 struct i40e_tunnel_filter_conf *tunnel_filter,
7068 uint8_t i, tun_type = 0;
7069 /* internal variable to convert ipv6 byte order */
7070 uint32_t convert_ipv6[4];
7072 struct i40e_pf_vf *vf = NULL;
7073 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7074 struct i40e_vsi *vsi;
7075 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7076 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7077 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7078 struct i40e_tunnel_filter *tunnel, *node;
7079 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7081 bool big_buffer = 0;
7083 cld_filter = rte_zmalloc("tunnel_filter",
7084 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7087 if (cld_filter == NULL) {
7088 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7091 pfilter = cld_filter;
7093 ether_addr_copy(&tunnel_filter->outer_mac,
7094 (struct ether_addr *)&pfilter->element.outer_mac);
7095 ether_addr_copy(&tunnel_filter->inner_mac,
7096 (struct ether_addr *)&pfilter->element.inner_mac);
7098 pfilter->element.inner_vlan =
7099 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7100 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7101 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7102 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7103 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7104 &rte_cpu_to_le_32(ipv4_addr),
7105 sizeof(pfilter->element.ipaddr.v4.data));
7107 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7108 for (i = 0; i < 4; i++) {
7110 rte_cpu_to_le_32(rte_be_to_cpu_32(
7111 tunnel_filter->ip_addr.ipv6_addr[i]));
7113 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7115 sizeof(pfilter->element.ipaddr.v6.data));
7118 /* check tunneled type */
7119 switch (tunnel_filter->tunnel_type) {
7120 case I40E_TUNNEL_TYPE_VXLAN:
7121 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7123 case I40E_TUNNEL_TYPE_NVGRE:
7124 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7126 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7127 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7129 case I40E_TUNNEL_TYPE_MPLSoUDP:
7130 if (!pf->mpls_replace_flag) {
7131 i40e_replace_mpls_l1_filter(pf);
7132 i40e_replace_mpls_cloud_filter(pf);
7133 pf->mpls_replace_flag = 1;
7135 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7136 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7138 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7139 (teid_le & 0xF) << 12;
7140 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7143 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7145 case I40E_TUNNEL_TYPE_MPLSoGRE:
7146 if (!pf->mpls_replace_flag) {
7147 i40e_replace_mpls_l1_filter(pf);
7148 i40e_replace_mpls_cloud_filter(pf);
7149 pf->mpls_replace_flag = 1;
7151 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7152 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7154 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7155 (teid_le & 0xF) << 12;
7156 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7159 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7161 case I40E_TUNNEL_TYPE_QINQ:
7162 if (!pf->qinq_replace_flag) {
7163 ret = i40e_cloud_filter_qinq_create(pf);
7166 "Failed to create a qinq tunnel filter.");
7167 pf->qinq_replace_flag = 1;
7169 /* Add in the General fields the values of
7170 * the Outer and Inner VLAN
7171 * Big Buffer should be set, see changes in
7172 * i40e_aq_add_cloud_filters
7174 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7175 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7179 /* Other tunnel types is not supported. */
7180 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7181 rte_free(cld_filter);
7185 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7186 pfilter->element.flags =
7187 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7188 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7189 pfilter->element.flags =
7190 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7191 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7192 pfilter->element.flags |=
7193 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7195 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7196 &pfilter->element.flags);
7198 rte_free(cld_filter);
7203 pfilter->element.flags |= rte_cpu_to_le_16(
7204 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7205 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7206 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7207 pfilter->element.queue_number =
7208 rte_cpu_to_le_16(tunnel_filter->queue_id);
7210 if (!tunnel_filter->is_to_vf)
7213 if (tunnel_filter->vf_id >= pf->vf_num) {
7214 PMD_DRV_LOG(ERR, "Invalid argument.");
7217 vf = &pf->vfs[tunnel_filter->vf_id];
7221 /* Check if there is the filter in SW list */
7222 memset(&check_filter, 0, sizeof(check_filter));
7223 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7224 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7225 check_filter.vf_id = tunnel_filter->vf_id;
7226 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7228 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7232 if (!add && !node) {
7233 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7239 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7240 vsi->seid, cld_filter, 1);
7242 ret = i40e_aq_add_cloud_filters(hw,
7243 vsi->seid, &cld_filter->element, 1);
7245 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7248 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7249 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7250 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7253 ret = i40e_aq_remove_cloud_filters_big_buffer(
7254 hw, vsi->seid, cld_filter, 1);
7256 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7257 &cld_filter->element, 1);
7259 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7262 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7265 rte_free(cld_filter);
7270 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7274 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7275 if (pf->vxlan_ports[i] == port)
7283 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7287 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7289 idx = i40e_get_vxlan_port_idx(pf, port);
7291 /* Check if port already exists */
7293 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7297 /* Now check if there is space to add the new port */
7298 idx = i40e_get_vxlan_port_idx(pf, 0);
7301 "Maximum number of UDP ports reached, not adding port %d",
7306 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7309 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7313 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7316 /* New port: add it and mark its index in the bitmap */
7317 pf->vxlan_ports[idx] = port;
7318 pf->vxlan_bitmap |= (1 << idx);
7320 if (!(pf->flags & I40E_FLAG_VXLAN))
7321 pf->flags |= I40E_FLAG_VXLAN;
7327 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7330 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7332 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7333 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7337 idx = i40e_get_vxlan_port_idx(pf, port);
7340 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7344 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7345 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7349 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7352 pf->vxlan_ports[idx] = 0;
7353 pf->vxlan_bitmap &= ~(1 << idx);
7355 if (!pf->vxlan_bitmap)
7356 pf->flags &= ~I40E_FLAG_VXLAN;
7361 /* Add UDP tunneling port */
7363 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7364 struct rte_eth_udp_tunnel *udp_tunnel)
7367 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7369 if (udp_tunnel == NULL)
7372 switch (udp_tunnel->prot_type) {
7373 case RTE_TUNNEL_TYPE_VXLAN:
7374 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7377 case RTE_TUNNEL_TYPE_GENEVE:
7378 case RTE_TUNNEL_TYPE_TEREDO:
7379 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7384 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7392 /* Remove UDP tunneling port */
7394 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7395 struct rte_eth_udp_tunnel *udp_tunnel)
7398 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7400 if (udp_tunnel == NULL)
7403 switch (udp_tunnel->prot_type) {
7404 case RTE_TUNNEL_TYPE_VXLAN:
7405 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7407 case RTE_TUNNEL_TYPE_GENEVE:
7408 case RTE_TUNNEL_TYPE_TEREDO:
7409 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7413 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7421 /* Calculate the maximum number of contiguous PF queues that are configured */
7423 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7425 struct rte_eth_dev_data *data = pf->dev_data;
7427 struct i40e_rx_queue *rxq;
7430 for (i = 0; i < pf->lan_nb_qps; i++) {
7431 rxq = data->rx_queues[i];
7432 if (rxq && rxq->q_set)
7443 i40e_pf_config_rss(struct i40e_pf *pf)
7445 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7446 struct rte_eth_rss_conf rss_conf;
7447 uint32_t i, lut = 0;
7451 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7452 * It's necessary to calulate the actual PF queues that are configured.
7454 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7455 num = i40e_pf_calc_configured_queues_num(pf);
7457 num = pf->dev_data->nb_rx_queues;
7459 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7460 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7464 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7468 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7471 lut = (lut << 8) | (j & ((0x1 <<
7472 hw->func_caps.rss_table_entry_width) - 1));
7474 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7477 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7478 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7479 i40e_pf_disable_rss(pf);
7482 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7483 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7484 /* Random default keys */
7485 static uint32_t rss_key_default[] = {0x6b793944,
7486 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7487 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7488 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7490 rss_conf.rss_key = (uint8_t *)rss_key_default;
7491 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7495 return i40e_hw_rss_hash_set(pf, &rss_conf);
7499 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7500 struct rte_eth_tunnel_filter_conf *filter)
7502 if (pf == NULL || filter == NULL) {
7503 PMD_DRV_LOG(ERR, "Invalid parameter");
7507 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7508 PMD_DRV_LOG(ERR, "Invalid queue ID");
7512 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7513 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7517 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7518 (is_zero_ether_addr(&filter->outer_mac))) {
7519 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7523 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7524 (is_zero_ether_addr(&filter->inner_mac))) {
7525 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7532 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7533 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7535 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7540 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7541 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7544 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7545 } else if (len == 4) {
7546 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7548 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7553 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7560 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7561 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7567 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7574 switch (cfg->cfg_type) {
7575 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7576 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7579 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7587 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7588 enum rte_filter_op filter_op,
7591 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7592 int ret = I40E_ERR_PARAM;
7594 switch (filter_op) {
7595 case RTE_ETH_FILTER_SET:
7596 ret = i40e_dev_global_config_set(hw,
7597 (struct rte_eth_global_cfg *)arg);
7600 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7608 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7609 enum rte_filter_op filter_op,
7612 struct rte_eth_tunnel_filter_conf *filter;
7613 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7614 int ret = I40E_SUCCESS;
7616 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7618 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7619 return I40E_ERR_PARAM;
7621 switch (filter_op) {
7622 case RTE_ETH_FILTER_NOP:
7623 if (!(pf->flags & I40E_FLAG_VXLAN))
7624 ret = I40E_NOT_SUPPORTED;
7626 case RTE_ETH_FILTER_ADD:
7627 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7629 case RTE_ETH_FILTER_DELETE:
7630 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7633 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7634 ret = I40E_ERR_PARAM;
7642 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7645 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7648 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7649 ret = i40e_pf_config_rss(pf);
7651 i40e_pf_disable_rss(pf);
7656 /* Get the symmetric hash enable configurations per port */
7658 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7660 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7662 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7665 /* Set the symmetric hash enable configurations per port */
7667 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7669 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7672 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7674 "Symmetric hash has already been enabled");
7677 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7679 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7681 "Symmetric hash has already been disabled");
7684 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7686 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7687 I40E_WRITE_FLUSH(hw);
7691 * Get global configurations of hash function type and symmetric hash enable
7692 * per flow type (pctype). Note that global configuration means it affects all
7693 * the ports on the same NIC.
7696 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7697 struct rte_eth_hash_global_conf *g_cfg)
7699 uint32_t reg, mask = I40E_FLOW_TYPES;
7701 enum i40e_filter_pctype pctype;
7703 memset(g_cfg, 0, sizeof(*g_cfg));
7704 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7705 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7706 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7708 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7709 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7710 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7712 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7713 if (!(mask & (1UL << i)))
7715 mask &= ~(1UL << i);
7716 /* Bit set indicats the coresponding flow type is supported */
7717 g_cfg->valid_bit_mask[0] |= (1UL << i);
7718 /* if flowtype is invalid, continue */
7719 if (!I40E_VALID_FLOW(i))
7721 pctype = i40e_flowtype_to_pctype(i);
7722 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7723 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7724 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7731 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7734 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7736 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7737 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7738 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7739 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7745 * As i40e supports less than 32 flow types, only first 32 bits need to
7748 mask0 = g_cfg->valid_bit_mask[0];
7749 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7751 /* Check if any unsupported flow type configured */
7752 if ((mask0 | i40e_mask) ^ i40e_mask)
7755 if (g_cfg->valid_bit_mask[i])
7763 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7769 * Set global configurations of hash function type and symmetric hash enable
7770 * per flow type (pctype). Note any modifying global configuration will affect
7771 * all the ports on the same NIC.
7774 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7775 struct rte_eth_hash_global_conf *g_cfg)
7780 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7781 enum i40e_filter_pctype pctype;
7783 /* Check the input parameters */
7784 ret = i40e_hash_global_config_check(g_cfg);
7788 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7789 if (!(mask0 & (1UL << i)))
7791 mask0 &= ~(1UL << i);
7792 /* if flowtype is invalid, continue */
7793 if (!I40E_VALID_FLOW(i))
7795 pctype = i40e_flowtype_to_pctype(i);
7796 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7797 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7798 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7801 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7802 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7804 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7806 "Hash function already set to Toeplitz");
7809 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7810 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7812 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7814 "Hash function already set to Simple XOR");
7817 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7819 /* Use the default, and keep it as it is */
7822 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7825 I40E_WRITE_FLUSH(hw);
7831 * Valid input sets for hash and flow director filters per PCTYPE
7834 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7835 enum rte_filter_type filter)
7839 static const uint64_t valid_hash_inset_table[] = {
7840 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7841 I40E_INSET_DMAC | I40E_INSET_SMAC |
7842 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7843 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7844 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7845 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7846 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7847 I40E_INSET_FLEX_PAYLOAD,
7848 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7849 I40E_INSET_DMAC | I40E_INSET_SMAC |
7850 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7851 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7852 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7853 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7854 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7855 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7856 I40E_INSET_FLEX_PAYLOAD,
7857 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7858 I40E_INSET_DMAC | I40E_INSET_SMAC |
7859 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7860 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7861 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7862 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7863 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7864 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7865 I40E_INSET_FLEX_PAYLOAD,
7866 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7867 I40E_INSET_DMAC | I40E_INSET_SMAC |
7868 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7869 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7870 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7871 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7872 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7873 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7874 I40E_INSET_FLEX_PAYLOAD,
7875 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7876 I40E_INSET_DMAC | I40E_INSET_SMAC |
7877 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7878 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7879 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7880 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7881 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7882 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7883 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7884 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7885 I40E_INSET_DMAC | I40E_INSET_SMAC |
7886 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7887 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7888 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7889 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7890 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7891 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7892 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7893 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7894 I40E_INSET_DMAC | I40E_INSET_SMAC |
7895 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7896 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7897 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7898 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7899 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7900 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7901 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7902 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7903 I40E_INSET_DMAC | I40E_INSET_SMAC |
7904 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7905 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7906 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7907 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7908 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7909 I40E_INSET_FLEX_PAYLOAD,
7910 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7911 I40E_INSET_DMAC | I40E_INSET_SMAC |
7912 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7913 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7914 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7915 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7916 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7917 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7918 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7919 I40E_INSET_DMAC | I40E_INSET_SMAC |
7920 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7921 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7922 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7923 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7924 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7925 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7926 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7927 I40E_INSET_DMAC | I40E_INSET_SMAC |
7928 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7929 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7930 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7931 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7932 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7933 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7934 I40E_INSET_FLEX_PAYLOAD,
7935 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7936 I40E_INSET_DMAC | I40E_INSET_SMAC |
7937 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7938 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7939 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7940 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7941 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7942 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7943 I40E_INSET_FLEX_PAYLOAD,
7944 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7945 I40E_INSET_DMAC | I40E_INSET_SMAC |
7946 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7947 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7948 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7949 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7950 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7951 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7952 I40E_INSET_FLEX_PAYLOAD,
7953 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7954 I40E_INSET_DMAC | I40E_INSET_SMAC |
7955 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7956 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7957 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7958 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7959 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7960 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7961 I40E_INSET_FLEX_PAYLOAD,
7962 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7963 I40E_INSET_DMAC | I40E_INSET_SMAC |
7964 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7965 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7966 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7967 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7968 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7969 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7970 I40E_INSET_FLEX_PAYLOAD,
7971 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7972 I40E_INSET_DMAC | I40E_INSET_SMAC |
7973 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7974 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7975 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7976 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7977 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7978 I40E_INSET_FLEX_PAYLOAD,
7979 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7980 I40E_INSET_DMAC | I40E_INSET_SMAC |
7981 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7982 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7983 I40E_INSET_FLEX_PAYLOAD,
7987 * Flow director supports only fields defined in
7988 * union rte_eth_fdir_flow.
7990 static const uint64_t valid_fdir_inset_table[] = {
7991 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7992 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7993 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7994 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7995 I40E_INSET_IPV4_TTL,
7996 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7997 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7998 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7999 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8000 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8001 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8002 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8003 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8004 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8005 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8006 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8007 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8008 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8009 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8010 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8011 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8012 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8013 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8014 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8015 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8016 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8017 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8018 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8019 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8020 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8021 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8022 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8023 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8024 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8025 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8027 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8028 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8029 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8030 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8031 I40E_INSET_IPV4_TTL,
8032 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8033 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8034 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8035 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8036 I40E_INSET_IPV6_HOP_LIMIT,
8037 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8038 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8039 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8040 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8041 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8042 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8043 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8044 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8045 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8046 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8047 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8048 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8049 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8050 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8051 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8052 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8053 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8054 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8055 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8056 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8057 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8058 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8059 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8060 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8061 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8062 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8063 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8064 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8065 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8066 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8068 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8069 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8070 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8071 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8072 I40E_INSET_IPV6_HOP_LIMIT,
8073 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8074 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8075 I40E_INSET_LAST_ETHER_TYPE,
8078 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8080 if (filter == RTE_ETH_FILTER_HASH)
8081 valid = valid_hash_inset_table[pctype];
8083 valid = valid_fdir_inset_table[pctype];
8089 * Validate if the input set is allowed for a specific PCTYPE
8092 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8093 enum rte_filter_type filter, uint64_t inset)
8097 valid = i40e_get_valid_input_set(pctype, filter);
8098 if (inset & (~valid))
8104 /* default input set fields combination per pctype */
8106 i40e_get_default_input_set(uint16_t pctype)
8108 static const uint64_t default_inset_table[] = {
8109 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8110 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8111 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8112 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8113 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8114 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8115 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8116 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8117 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8118 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8119 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8120 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8121 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8122 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8123 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8124 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8125 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8126 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8127 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8128 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8130 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8131 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8132 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8133 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8134 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8135 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8136 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8137 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8138 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8139 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8140 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8141 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8142 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8143 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8144 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8145 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8146 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8147 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8148 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8149 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8150 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8151 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8153 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8154 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8155 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8156 I40E_INSET_LAST_ETHER_TYPE,
8159 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8162 return default_inset_table[pctype];
8166 * Parse the input set from index to logical bit masks
8169 i40e_parse_input_set(uint64_t *inset,
8170 enum i40e_filter_pctype pctype,
8171 enum rte_eth_input_set_field *field,
8177 static const struct {
8178 enum rte_eth_input_set_field field;
8180 } inset_convert_table[] = {
8181 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8182 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8183 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8184 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8185 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8186 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8187 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8188 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8189 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8190 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8191 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8192 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8193 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8194 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8195 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8196 I40E_INSET_IPV6_NEXT_HDR},
8197 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8198 I40E_INSET_IPV6_HOP_LIMIT},
8199 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8200 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8201 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8202 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8203 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8204 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8205 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8206 I40E_INSET_SCTP_VT},
8207 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8208 I40E_INSET_TUNNEL_DMAC},
8209 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8210 I40E_INSET_VLAN_TUNNEL},
8211 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8212 I40E_INSET_TUNNEL_ID},
8213 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8214 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8215 I40E_INSET_FLEX_PAYLOAD_W1},
8216 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8217 I40E_INSET_FLEX_PAYLOAD_W2},
8218 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8219 I40E_INSET_FLEX_PAYLOAD_W3},
8220 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8221 I40E_INSET_FLEX_PAYLOAD_W4},
8222 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8223 I40E_INSET_FLEX_PAYLOAD_W5},
8224 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8225 I40E_INSET_FLEX_PAYLOAD_W6},
8226 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8227 I40E_INSET_FLEX_PAYLOAD_W7},
8228 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8229 I40E_INSET_FLEX_PAYLOAD_W8},
8232 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8235 /* Only one item allowed for default or all */
8237 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8238 *inset = i40e_get_default_input_set(pctype);
8240 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8241 *inset = I40E_INSET_NONE;
8246 for (i = 0, *inset = 0; i < size; i++) {
8247 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8248 if (field[i] == inset_convert_table[j].field) {
8249 *inset |= inset_convert_table[j].inset;
8254 /* It contains unsupported input set, return immediately */
8255 if (j == RTE_DIM(inset_convert_table))
8263 * Translate the input set from bit masks to register aware bit masks
8267 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8277 static const struct inset_map inset_map_common[] = {
8278 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8279 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8280 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8281 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8282 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8283 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8284 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8285 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8286 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8287 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8288 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8289 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8290 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8291 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8292 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8293 {I40E_INSET_TUNNEL_DMAC,
8294 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8295 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8296 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8297 {I40E_INSET_TUNNEL_SRC_PORT,
8298 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8299 {I40E_INSET_TUNNEL_DST_PORT,
8300 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8301 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8302 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8303 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8304 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8305 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8306 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8307 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8308 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8309 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8312 /* some different registers map in x722*/
8313 static const struct inset_map inset_map_diff_x722[] = {
8314 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8315 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8316 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8317 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8320 static const struct inset_map inset_map_diff_not_x722[] = {
8321 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8322 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8323 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8324 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8330 /* Translate input set to register aware inset */
8331 if (type == I40E_MAC_X722) {
8332 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8333 if (input & inset_map_diff_x722[i].inset)
8334 val |= inset_map_diff_x722[i].inset_reg;
8337 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8338 if (input & inset_map_diff_not_x722[i].inset)
8339 val |= inset_map_diff_not_x722[i].inset_reg;
8343 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8344 if (input & inset_map_common[i].inset)
8345 val |= inset_map_common[i].inset_reg;
8352 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8355 uint64_t inset_need_mask = inset;
8357 static const struct {
8360 } inset_mask_map[] = {
8361 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8362 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8363 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8364 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8365 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8366 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8367 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8368 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8371 if (!inset || !mask || !nb_elem)
8374 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8375 /* Clear the inset bit, if no MASK is required,
8376 * for example proto + ttl
8378 if ((inset & inset_mask_map[i].inset) ==
8379 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8380 inset_need_mask &= ~inset_mask_map[i].inset;
8381 if (!inset_need_mask)
8384 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8385 if ((inset_need_mask & inset_mask_map[i].inset) ==
8386 inset_mask_map[i].inset) {
8387 if (idx >= nb_elem) {
8388 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8391 mask[idx] = inset_mask_map[i].mask;
8400 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8402 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8404 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8406 i40e_write_rx_ctl(hw, addr, val);
8407 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8408 (uint32_t)i40e_read_rx_ctl(hw, addr));
8412 i40e_filter_input_set_init(struct i40e_pf *pf)
8414 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8415 enum i40e_filter_pctype pctype;
8416 uint64_t input_set, inset_reg;
8417 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8420 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8421 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8422 if (hw->mac.type == I40E_MAC_X722) {
8423 if (!I40E_VALID_PCTYPE_X722(pctype))
8426 if (!I40E_VALID_PCTYPE(pctype))
8430 input_set = i40e_get_default_input_set(pctype);
8432 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8433 I40E_INSET_MASK_NUM_REG);
8436 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8439 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8440 (uint32_t)(inset_reg & UINT32_MAX));
8441 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8442 (uint32_t)((inset_reg >>
8443 I40E_32_BIT_WIDTH) & UINT32_MAX));
8444 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8445 (uint32_t)(inset_reg & UINT32_MAX));
8446 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8447 (uint32_t)((inset_reg >>
8448 I40E_32_BIT_WIDTH) & UINT32_MAX));
8450 for (i = 0; i < num; i++) {
8451 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8453 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8456 /*clear unused mask registers of the pctype */
8457 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8458 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8460 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8463 I40E_WRITE_FLUSH(hw);
8465 /* store the default input set */
8466 pf->hash_input_set[pctype] = input_set;
8467 pf->fdir.input_set[pctype] = input_set;
8472 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8473 struct rte_eth_input_set_conf *conf)
8475 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8476 enum i40e_filter_pctype pctype;
8477 uint64_t input_set, inset_reg = 0;
8478 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8482 PMD_DRV_LOG(ERR, "Invalid pointer");
8485 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8486 conf->op != RTE_ETH_INPUT_SET_ADD) {
8487 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8491 if (!I40E_VALID_FLOW(conf->flow_type)) {
8492 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8496 if (hw->mac.type == I40E_MAC_X722) {
8497 /* get translated pctype value in fd pctype register */
8498 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8499 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8502 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8504 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8507 PMD_DRV_LOG(ERR, "Failed to parse input set");
8510 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8512 PMD_DRV_LOG(ERR, "Invalid input set");
8515 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8516 /* get inset value in register */
8517 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8518 inset_reg <<= I40E_32_BIT_WIDTH;
8519 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8520 input_set |= pf->hash_input_set[pctype];
8522 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8523 I40E_INSET_MASK_NUM_REG);
8527 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8529 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8530 (uint32_t)(inset_reg & UINT32_MAX));
8531 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8532 (uint32_t)((inset_reg >>
8533 I40E_32_BIT_WIDTH) & UINT32_MAX));
8535 for (i = 0; i < num; i++)
8536 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8538 /*clear unused mask registers of the pctype */
8539 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8540 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8542 I40E_WRITE_FLUSH(hw);
8544 pf->hash_input_set[pctype] = input_set;
8549 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8550 struct rte_eth_input_set_conf *conf)
8552 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8553 enum i40e_filter_pctype pctype;
8554 uint64_t input_set, inset_reg = 0;
8555 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8559 PMD_DRV_LOG(ERR, "Invalid pointer");
8562 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8563 conf->op != RTE_ETH_INPUT_SET_ADD) {
8564 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8568 if (!I40E_VALID_FLOW(conf->flow_type)) {
8569 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8573 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8575 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8578 PMD_DRV_LOG(ERR, "Failed to parse input set");
8581 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8583 PMD_DRV_LOG(ERR, "Invalid input set");
8587 /* get inset value in register */
8588 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8589 inset_reg <<= I40E_32_BIT_WIDTH;
8590 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8592 /* Can not change the inset reg for flex payload for fdir,
8593 * it is done by writing I40E_PRTQF_FD_FLXINSET
8594 * in i40e_set_flex_mask_on_pctype.
8596 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8597 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8599 input_set |= pf->fdir.input_set[pctype];
8600 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8601 I40E_INSET_MASK_NUM_REG);
8605 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8607 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8608 (uint32_t)(inset_reg & UINT32_MAX));
8609 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8610 (uint32_t)((inset_reg >>
8611 I40E_32_BIT_WIDTH) & UINT32_MAX));
8613 for (i = 0; i < num; i++)
8614 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8616 /*clear unused mask registers of the pctype */
8617 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8618 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8620 I40E_WRITE_FLUSH(hw);
8622 pf->fdir.input_set[pctype] = input_set;
8627 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8632 PMD_DRV_LOG(ERR, "Invalid pointer");
8636 switch (info->info_type) {
8637 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8638 i40e_get_symmetric_hash_enable_per_port(hw,
8639 &(info->info.enable));
8641 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8642 ret = i40e_get_hash_filter_global_config(hw,
8643 &(info->info.global_conf));
8646 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8656 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8661 PMD_DRV_LOG(ERR, "Invalid pointer");
8665 switch (info->info_type) {
8666 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8667 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8669 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8670 ret = i40e_set_hash_filter_global_config(hw,
8671 &(info->info.global_conf));
8673 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8674 ret = i40e_hash_filter_inset_select(hw,
8675 &(info->info.input_set_conf));
8679 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8688 /* Operations for hash function */
8690 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8691 enum rte_filter_op filter_op,
8694 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8697 switch (filter_op) {
8698 case RTE_ETH_FILTER_NOP:
8700 case RTE_ETH_FILTER_GET:
8701 ret = i40e_hash_filter_get(hw,
8702 (struct rte_eth_hash_filter_info *)arg);
8704 case RTE_ETH_FILTER_SET:
8705 ret = i40e_hash_filter_set(hw,
8706 (struct rte_eth_hash_filter_info *)arg);
8709 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8718 /* Convert ethertype filter structure */
8720 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8721 struct i40e_ethertype_filter *filter)
8723 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8724 filter->input.ether_type = input->ether_type;
8725 filter->flags = input->flags;
8726 filter->queue = input->queue;
8731 /* Check if there exists the ehtertype filter */
8732 struct i40e_ethertype_filter *
8733 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8734 const struct i40e_ethertype_filter_input *input)
8738 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8742 return ethertype_rule->hash_map[ret];
8745 /* Add ethertype filter in SW list */
8747 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8748 struct i40e_ethertype_filter *filter)
8750 struct i40e_ethertype_rule *rule = &pf->ethertype;
8753 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8756 "Failed to insert ethertype filter"
8757 " to hash table %d!",
8761 rule->hash_map[ret] = filter;
8763 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8768 /* Delete ethertype filter in SW list */
8770 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8771 struct i40e_ethertype_filter_input *input)
8773 struct i40e_ethertype_rule *rule = &pf->ethertype;
8774 struct i40e_ethertype_filter *filter;
8777 ret = rte_hash_del_key(rule->hash_table, input);
8780 "Failed to delete ethertype filter"
8781 " to hash table %d!",
8785 filter = rule->hash_map[ret];
8786 rule->hash_map[ret] = NULL;
8788 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8795 * Configure ethertype filter, which can director packet by filtering
8796 * with mac address and ether_type or only ether_type
8799 i40e_ethertype_filter_set(struct i40e_pf *pf,
8800 struct rte_eth_ethertype_filter *filter,
8803 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8804 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8805 struct i40e_ethertype_filter *ethertype_filter, *node;
8806 struct i40e_ethertype_filter check_filter;
8807 struct i40e_control_filter_stats stats;
8811 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8812 PMD_DRV_LOG(ERR, "Invalid queue ID");
8815 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8816 filter->ether_type == ETHER_TYPE_IPv6) {
8818 "unsupported ether_type(0x%04x) in control packet filter.",
8819 filter->ether_type);
8822 if (filter->ether_type == ETHER_TYPE_VLAN)
8823 PMD_DRV_LOG(WARNING,
8824 "filter vlan ether_type in first tag is not supported.");
8826 /* Check if there is the filter in SW list */
8827 memset(&check_filter, 0, sizeof(check_filter));
8828 i40e_ethertype_filter_convert(filter, &check_filter);
8829 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8830 &check_filter.input);
8832 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8836 if (!add && !node) {
8837 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8841 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8842 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8843 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8844 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8845 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8847 memset(&stats, 0, sizeof(stats));
8848 ret = i40e_aq_add_rem_control_packet_filter(hw,
8849 filter->mac_addr.addr_bytes,
8850 filter->ether_type, flags,
8852 filter->queue, add, &stats, NULL);
8855 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8856 ret, stats.mac_etype_used, stats.etype_used,
8857 stats.mac_etype_free, stats.etype_free);
8861 /* Add or delete a filter in SW list */
8863 ethertype_filter = rte_zmalloc("ethertype_filter",
8864 sizeof(*ethertype_filter), 0);
8865 rte_memcpy(ethertype_filter, &check_filter,
8866 sizeof(check_filter));
8867 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8869 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8876 * Handle operations for ethertype filter.
8879 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8880 enum rte_filter_op filter_op,
8883 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8886 if (filter_op == RTE_ETH_FILTER_NOP)
8890 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8895 switch (filter_op) {
8896 case RTE_ETH_FILTER_ADD:
8897 ret = i40e_ethertype_filter_set(pf,
8898 (struct rte_eth_ethertype_filter *)arg,
8901 case RTE_ETH_FILTER_DELETE:
8902 ret = i40e_ethertype_filter_set(pf,
8903 (struct rte_eth_ethertype_filter *)arg,
8907 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8915 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8916 enum rte_filter_type filter_type,
8917 enum rte_filter_op filter_op,
8925 switch (filter_type) {
8926 case RTE_ETH_FILTER_NONE:
8927 /* For global configuration */
8928 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8930 case RTE_ETH_FILTER_HASH:
8931 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8933 case RTE_ETH_FILTER_MACVLAN:
8934 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8936 case RTE_ETH_FILTER_ETHERTYPE:
8937 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8939 case RTE_ETH_FILTER_TUNNEL:
8940 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8942 case RTE_ETH_FILTER_FDIR:
8943 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8945 case RTE_ETH_FILTER_GENERIC:
8946 if (filter_op != RTE_ETH_FILTER_GET)
8948 *(const void **)arg = &i40e_flow_ops;
8951 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8961 * Check and enable Extended Tag.
8962 * Enabling Extended Tag is important for 40G performance.
8965 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8967 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8971 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8974 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8978 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8979 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8984 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8987 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8991 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8992 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8995 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8996 ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8999 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9006 * As some registers wouldn't be reset unless a global hardware reset,
9007 * hardware initialization is needed to put those registers into an
9008 * expected initial state.
9011 i40e_hw_init(struct rte_eth_dev *dev)
9013 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9015 i40e_enable_extended_tag(dev);
9017 /* clear the PF Queue Filter control register */
9018 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9020 /* Disable symmetric hash per port */
9021 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9024 enum i40e_filter_pctype
9025 i40e_flowtype_to_pctype(uint16_t flow_type)
9027 static const enum i40e_filter_pctype pctype_table[] = {
9028 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9029 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9030 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9031 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9032 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9033 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9034 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9035 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9036 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9037 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9038 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9039 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9040 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9041 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9042 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9043 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9044 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9045 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9046 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9049 return pctype_table[flow_type];
9053 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9055 static const uint16_t flowtype_table[] = {
9056 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9057 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9058 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9059 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9060 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9061 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9062 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9063 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9064 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9065 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9066 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9067 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9068 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9069 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9070 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9071 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9072 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9073 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9074 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9075 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9076 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9077 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9078 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9079 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9080 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9081 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9082 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9083 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9084 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9085 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9086 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9089 return flowtype_table[pctype];
9093 * On X710, performance number is far from the expectation on recent firmware
9094 * versions; on XL710, performance number is also far from the expectation on
9095 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9096 * mode is enabled and port MAC address is equal to the packet destination MAC
9097 * address. The fix for this issue may not be integrated in the following
9098 * firmware version. So the workaround in software driver is needed. It needs
9099 * to modify the initial values of 3 internal only registers for both X710 and
9100 * XL710. Note that the values for X710 or XL710 could be different, and the
9101 * workaround can be removed when it is fixed in firmware in the future.
9104 /* For both X710 and XL710 */
9105 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
9106 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9108 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9109 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9112 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9113 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9116 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9118 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9119 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9122 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9124 enum i40e_status_code status;
9125 struct i40e_aq_get_phy_abilities_resp phy_ab;
9128 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9138 i40e_configure_registers(struct i40e_hw *hw)
9144 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9145 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9146 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9152 for (i = 0; i < RTE_DIM(reg_table); i++) {
9153 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9154 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9156 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9157 else /* For X710/XL710/XXV710 */
9159 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9162 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9163 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9165 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9166 else /* For X710/XL710/XXV710 */
9168 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9171 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9172 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9173 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9175 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9178 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9181 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9184 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9188 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9189 reg_table[i].addr, reg);
9190 if (reg == reg_table[i].val)
9193 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9194 reg_table[i].val, NULL);
9197 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9198 reg_table[i].val, reg_table[i].addr);
9201 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9202 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9206 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9207 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9208 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9209 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9211 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9216 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9217 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9221 /* Configure for double VLAN RX stripping */
9222 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9223 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9224 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9225 ret = i40e_aq_debug_write_register(hw,
9226 I40E_VSI_TSR(vsi->vsi_id),
9229 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9231 return I40E_ERR_CONFIG;
9235 /* Configure for double VLAN TX insertion */
9236 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9237 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9238 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9239 ret = i40e_aq_debug_write_register(hw,
9240 I40E_VSI_L2TAGSTXVALID(
9241 vsi->vsi_id), reg, NULL);
9244 "Failed to update VSI_L2TAGSTXVALID[%d]",
9246 return I40E_ERR_CONFIG;
9254 * i40e_aq_add_mirror_rule
9255 * @hw: pointer to the hardware structure
9256 * @seid: VEB seid to add mirror rule to
9257 * @dst_id: destination vsi seid
9258 * @entries: Buffer which contains the entities to be mirrored
9259 * @count: number of entities contained in the buffer
9260 * @rule_id:the rule_id of the rule to be added
9262 * Add a mirror rule for a given veb.
9265 static enum i40e_status_code
9266 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9267 uint16_t seid, uint16_t dst_id,
9268 uint16_t rule_type, uint16_t *entries,
9269 uint16_t count, uint16_t *rule_id)
9271 struct i40e_aq_desc desc;
9272 struct i40e_aqc_add_delete_mirror_rule cmd;
9273 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9274 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9277 enum i40e_status_code status;
9279 i40e_fill_default_direct_cmd_desc(&desc,
9280 i40e_aqc_opc_add_mirror_rule);
9281 memset(&cmd, 0, sizeof(cmd));
9283 buff_len = sizeof(uint16_t) * count;
9284 desc.datalen = rte_cpu_to_le_16(buff_len);
9286 desc.flags |= rte_cpu_to_le_16(
9287 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9288 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9289 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9290 cmd.num_entries = rte_cpu_to_le_16(count);
9291 cmd.seid = rte_cpu_to_le_16(seid);
9292 cmd.destination = rte_cpu_to_le_16(dst_id);
9294 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9295 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9297 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9298 hw->aq.asq_last_status, resp->rule_id,
9299 resp->mirror_rules_used, resp->mirror_rules_free);
9300 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9306 * i40e_aq_del_mirror_rule
9307 * @hw: pointer to the hardware structure
9308 * @seid: VEB seid to add mirror rule to
9309 * @entries: Buffer which contains the entities to be mirrored
9310 * @count: number of entities contained in the buffer
9311 * @rule_id:the rule_id of the rule to be delete
9313 * Delete a mirror rule for a given veb.
9316 static enum i40e_status_code
9317 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9318 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9319 uint16_t count, uint16_t rule_id)
9321 struct i40e_aq_desc desc;
9322 struct i40e_aqc_add_delete_mirror_rule cmd;
9323 uint16_t buff_len = 0;
9324 enum i40e_status_code status;
9327 i40e_fill_default_direct_cmd_desc(&desc,
9328 i40e_aqc_opc_delete_mirror_rule);
9329 memset(&cmd, 0, sizeof(cmd));
9330 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9331 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9333 cmd.num_entries = count;
9334 buff_len = sizeof(uint16_t) * count;
9335 desc.datalen = rte_cpu_to_le_16(buff_len);
9336 buff = (void *)entries;
9338 /* rule id is filled in destination field for deleting mirror rule */
9339 cmd.destination = rte_cpu_to_le_16(rule_id);
9341 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9342 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9343 cmd.seid = rte_cpu_to_le_16(seid);
9345 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9346 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9352 * i40e_mirror_rule_set
9353 * @dev: pointer to the hardware structure
9354 * @mirror_conf: mirror rule info
9355 * @sw_id: mirror rule's sw_id
9356 * @on: enable/disable
9358 * set a mirror rule.
9362 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9363 struct rte_eth_mirror_conf *mirror_conf,
9364 uint8_t sw_id, uint8_t on)
9366 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9367 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9368 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9369 struct i40e_mirror_rule *parent = NULL;
9370 uint16_t seid, dst_seid, rule_id;
9374 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9376 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9378 "mirror rule can not be configured without veb or vfs.");
9381 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9382 PMD_DRV_LOG(ERR, "mirror table is full.");
9385 if (mirror_conf->dst_pool > pf->vf_num) {
9386 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9387 mirror_conf->dst_pool);
9391 seid = pf->main_vsi->veb->seid;
9393 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9394 if (sw_id <= it->index) {
9400 if (mirr_rule && sw_id == mirr_rule->index) {
9402 PMD_DRV_LOG(ERR, "mirror rule exists.");
9405 ret = i40e_aq_del_mirror_rule(hw, seid,
9406 mirr_rule->rule_type,
9408 mirr_rule->num_entries, mirr_rule->id);
9411 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9412 ret, hw->aq.asq_last_status);
9415 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9416 rte_free(mirr_rule);
9417 pf->nb_mirror_rule--;
9421 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9425 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9426 sizeof(struct i40e_mirror_rule) , 0);
9428 PMD_DRV_LOG(ERR, "failed to allocate memory");
9429 return I40E_ERR_NO_MEMORY;
9431 switch (mirror_conf->rule_type) {
9432 case ETH_MIRROR_VLAN:
9433 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9434 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9435 mirr_rule->entries[j] =
9436 mirror_conf->vlan.vlan_id[i];
9441 PMD_DRV_LOG(ERR, "vlan is not specified.");
9442 rte_free(mirr_rule);
9445 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9447 case ETH_MIRROR_VIRTUAL_POOL_UP:
9448 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9449 /* check if the specified pool bit is out of range */
9450 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9451 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9452 rte_free(mirr_rule);
9455 for (i = 0, j = 0; i < pf->vf_num; i++) {
9456 if (mirror_conf->pool_mask & (1ULL << i)) {
9457 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9461 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9462 /* add pf vsi to entries */
9463 mirr_rule->entries[j] = pf->main_vsi_seid;
9467 PMD_DRV_LOG(ERR, "pool is not specified.");
9468 rte_free(mirr_rule);
9471 /* egress and ingress in aq commands means from switch but not port */
9472 mirr_rule->rule_type =
9473 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9474 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9475 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9477 case ETH_MIRROR_UPLINK_PORT:
9478 /* egress and ingress in aq commands means from switch but not port*/
9479 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9481 case ETH_MIRROR_DOWNLINK_PORT:
9482 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9485 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9486 mirror_conf->rule_type);
9487 rte_free(mirr_rule);
9491 /* If the dst_pool is equal to vf_num, consider it as PF */
9492 if (mirror_conf->dst_pool == pf->vf_num)
9493 dst_seid = pf->main_vsi_seid;
9495 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9497 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9498 mirr_rule->rule_type, mirr_rule->entries,
9502 "failed to add mirror rule: ret = %d, aq_err = %d.",
9503 ret, hw->aq.asq_last_status);
9504 rte_free(mirr_rule);
9508 mirr_rule->index = sw_id;
9509 mirr_rule->num_entries = j;
9510 mirr_rule->id = rule_id;
9511 mirr_rule->dst_vsi_seid = dst_seid;
9514 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9516 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9518 pf->nb_mirror_rule++;
9523 * i40e_mirror_rule_reset
9524 * @dev: pointer to the device
9525 * @sw_id: mirror rule's sw_id
9527 * reset a mirror rule.
9531 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9533 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9534 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9535 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9539 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9541 seid = pf->main_vsi->veb->seid;
9543 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9544 if (sw_id == it->index) {
9550 ret = i40e_aq_del_mirror_rule(hw, seid,
9551 mirr_rule->rule_type,
9553 mirr_rule->num_entries, mirr_rule->id);
9556 "failed to remove mirror rule: status = %d, aq_err = %d.",
9557 ret, hw->aq.asq_last_status);
9560 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9561 rte_free(mirr_rule);
9562 pf->nb_mirror_rule--;
9564 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9571 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9573 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9574 uint64_t systim_cycles;
9576 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9577 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9580 return systim_cycles;
9584 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9586 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9589 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9590 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9597 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9599 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9602 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9603 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9610 i40e_start_timecounters(struct rte_eth_dev *dev)
9612 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9613 struct i40e_adapter *adapter =
9614 (struct i40e_adapter *)dev->data->dev_private;
9615 struct rte_eth_link link;
9616 uint32_t tsync_inc_l;
9617 uint32_t tsync_inc_h;
9619 /* Get current link speed. */
9620 memset(&link, 0, sizeof(link));
9621 i40e_dev_link_update(dev, 1);
9622 rte_i40e_dev_atomic_read_link_status(dev, &link);
9624 switch (link.link_speed) {
9625 case ETH_SPEED_NUM_40G:
9626 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9627 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9629 case ETH_SPEED_NUM_10G:
9630 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9631 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9633 case ETH_SPEED_NUM_1G:
9634 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9635 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9642 /* Set the timesync increment value. */
9643 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9644 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9646 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9647 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9648 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9650 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9651 adapter->systime_tc.cc_shift = 0;
9652 adapter->systime_tc.nsec_mask = 0;
9654 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9655 adapter->rx_tstamp_tc.cc_shift = 0;
9656 adapter->rx_tstamp_tc.nsec_mask = 0;
9658 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9659 adapter->tx_tstamp_tc.cc_shift = 0;
9660 adapter->tx_tstamp_tc.nsec_mask = 0;
9664 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9666 struct i40e_adapter *adapter =
9667 (struct i40e_adapter *)dev->data->dev_private;
9669 adapter->systime_tc.nsec += delta;
9670 adapter->rx_tstamp_tc.nsec += delta;
9671 adapter->tx_tstamp_tc.nsec += delta;
9677 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9680 struct i40e_adapter *adapter =
9681 (struct i40e_adapter *)dev->data->dev_private;
9683 ns = rte_timespec_to_ns(ts);
9685 /* Set the timecounters to a new value. */
9686 adapter->systime_tc.nsec = ns;
9687 adapter->rx_tstamp_tc.nsec = ns;
9688 adapter->tx_tstamp_tc.nsec = ns;
9694 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9696 uint64_t ns, systime_cycles;
9697 struct i40e_adapter *adapter =
9698 (struct i40e_adapter *)dev->data->dev_private;
9700 systime_cycles = i40e_read_systime_cyclecounter(dev);
9701 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9702 *ts = rte_ns_to_timespec(ns);
9708 i40e_timesync_enable(struct rte_eth_dev *dev)
9710 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9711 uint32_t tsync_ctl_l;
9712 uint32_t tsync_ctl_h;
9714 /* Stop the timesync system time. */
9715 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9716 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9717 /* Reset the timesync system time value. */
9718 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9719 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9721 i40e_start_timecounters(dev);
9723 /* Clear timesync registers. */
9724 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9725 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9726 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9727 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9728 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9729 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9731 /* Enable timestamping of PTP packets. */
9732 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9733 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9735 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9736 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9737 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9739 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9740 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9746 i40e_timesync_disable(struct rte_eth_dev *dev)
9748 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9749 uint32_t tsync_ctl_l;
9750 uint32_t tsync_ctl_h;
9752 /* Disable timestamping of transmitted PTP packets. */
9753 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9754 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9756 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9757 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9759 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9760 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9762 /* Reset the timesync increment value. */
9763 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9764 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9770 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9771 struct timespec *timestamp, uint32_t flags)
9773 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9774 struct i40e_adapter *adapter =
9775 (struct i40e_adapter *)dev->data->dev_private;
9777 uint32_t sync_status;
9778 uint32_t index = flags & 0x03;
9779 uint64_t rx_tstamp_cycles;
9782 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9783 if ((sync_status & (1 << index)) == 0)
9786 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9787 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9788 *timestamp = rte_ns_to_timespec(ns);
9794 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9795 struct timespec *timestamp)
9797 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9798 struct i40e_adapter *adapter =
9799 (struct i40e_adapter *)dev->data->dev_private;
9801 uint32_t sync_status;
9802 uint64_t tx_tstamp_cycles;
9805 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9806 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9809 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9810 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9811 *timestamp = rte_ns_to_timespec(ns);
9817 * i40e_parse_dcb_configure - parse dcb configure from user
9818 * @dev: the device being configured
9819 * @dcb_cfg: pointer of the result of parse
9820 * @*tc_map: bit map of enabled traffic classes
9822 * Returns 0 on success, negative value on failure
9825 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9826 struct i40e_dcbx_config *dcb_cfg,
9829 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9830 uint8_t i, tc_bw, bw_lf;
9832 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9834 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9835 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9836 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9840 /* assume each tc has the same bw */
9841 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9842 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9843 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9844 /* to ensure the sum of tcbw is equal to 100 */
9845 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9846 for (i = 0; i < bw_lf; i++)
9847 dcb_cfg->etscfg.tcbwtable[i]++;
9849 /* assume each tc has the same Transmission Selection Algorithm */
9850 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9851 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9853 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9854 dcb_cfg->etscfg.prioritytable[i] =
9855 dcb_rx_conf->dcb_tc[i];
9857 /* FW needs one App to configure HW */
9858 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9859 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9860 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9861 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9863 if (dcb_rx_conf->nb_tcs == 0)
9864 *tc_map = 1; /* tc0 only */
9866 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9868 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9869 dcb_cfg->pfc.willing = 0;
9870 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9871 dcb_cfg->pfc.pfcenable = *tc_map;
9877 static enum i40e_status_code
9878 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9879 struct i40e_aqc_vsi_properties_data *info,
9880 uint8_t enabled_tcmap)
9882 enum i40e_status_code ret;
9883 int i, total_tc = 0;
9884 uint16_t qpnum_per_tc, bsf, qp_idx;
9885 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9886 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9887 uint16_t used_queues;
9889 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9890 if (ret != I40E_SUCCESS)
9893 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9894 if (enabled_tcmap & (1 << i))
9899 vsi->enabled_tc = enabled_tcmap;
9901 /* different VSI has different queues assigned */
9902 if (vsi->type == I40E_VSI_MAIN)
9903 used_queues = dev_data->nb_rx_queues -
9904 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9905 else if (vsi->type == I40E_VSI_VMDQ2)
9906 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9908 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9909 return I40E_ERR_NO_AVAILABLE_VSI;
9912 qpnum_per_tc = used_queues / total_tc;
9913 /* Number of queues per enabled TC */
9914 if (qpnum_per_tc == 0) {
9915 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9916 return I40E_ERR_INVALID_QP_ID;
9918 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9920 bsf = rte_bsf32(qpnum_per_tc);
9923 * Configure TC and queue mapping parameters, for enabled TC,
9924 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9925 * default queue will serve it.
9928 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9929 if (vsi->enabled_tc & (1 << i)) {
9930 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9931 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9932 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9933 qp_idx += qpnum_per_tc;
9935 info->tc_mapping[i] = 0;
9938 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9939 if (vsi->type == I40E_VSI_SRIOV) {
9940 info->mapping_flags |=
9941 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9942 for (i = 0; i < vsi->nb_qps; i++)
9943 info->queue_mapping[i] =
9944 rte_cpu_to_le_16(vsi->base_queue + i);
9946 info->mapping_flags |=
9947 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9948 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9950 info->valid_sections |=
9951 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9953 return I40E_SUCCESS;
9957 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9958 * @veb: VEB to be configured
9959 * @tc_map: enabled TC bitmap
9961 * Returns 0 on success, negative value on failure
9963 static enum i40e_status_code
9964 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9966 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9967 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9968 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9969 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9970 enum i40e_status_code ret = I40E_SUCCESS;
9974 /* Check if enabled_tc is same as existing or new TCs */
9975 if (veb->enabled_tc == tc_map)
9978 /* configure tc bandwidth */
9979 memset(&veb_bw, 0, sizeof(veb_bw));
9980 veb_bw.tc_valid_bits = tc_map;
9981 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9982 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9983 if (tc_map & BIT_ULL(i))
9984 veb_bw.tc_bw_share_credits[i] = 1;
9986 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9990 "AQ command Config switch_comp BW allocation per TC failed = %d",
9991 hw->aq.asq_last_status);
9995 memset(&ets_query, 0, sizeof(ets_query));
9996 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9998 if (ret != I40E_SUCCESS) {
10000 "Failed to get switch_comp ETS configuration %u",
10001 hw->aq.asq_last_status);
10004 memset(&bw_query, 0, sizeof(bw_query));
10005 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10007 if (ret != I40E_SUCCESS) {
10009 "Failed to get switch_comp bandwidth configuration %u",
10010 hw->aq.asq_last_status);
10014 /* store and print out BW info */
10015 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10016 veb->bw_info.bw_max = ets_query.tc_bw_max;
10017 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10018 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10019 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10020 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10021 I40E_16_BIT_WIDTH);
10022 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10023 veb->bw_info.bw_ets_share_credits[i] =
10024 bw_query.tc_bw_share_credits[i];
10025 veb->bw_info.bw_ets_credits[i] =
10026 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10027 /* 4 bits per TC, 4th bit is reserved */
10028 veb->bw_info.bw_ets_max[i] =
10029 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10030 RTE_LEN2MASK(3, uint8_t));
10031 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10032 veb->bw_info.bw_ets_share_credits[i]);
10033 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10034 veb->bw_info.bw_ets_credits[i]);
10035 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10036 veb->bw_info.bw_ets_max[i]);
10039 veb->enabled_tc = tc_map;
10046 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10047 * @vsi: VSI to be configured
10048 * @tc_map: enabled TC bitmap
10050 * Returns 0 on success, negative value on failure
10052 static enum i40e_status_code
10053 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10055 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10056 struct i40e_vsi_context ctxt;
10057 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10058 enum i40e_status_code ret = I40E_SUCCESS;
10061 /* Check if enabled_tc is same as existing or new TCs */
10062 if (vsi->enabled_tc == tc_map)
10065 /* configure tc bandwidth */
10066 memset(&bw_data, 0, sizeof(bw_data));
10067 bw_data.tc_valid_bits = tc_map;
10068 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10069 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10070 if (tc_map & BIT_ULL(i))
10071 bw_data.tc_bw_credits[i] = 1;
10073 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10076 "AQ command Config VSI BW allocation per TC failed = %d",
10077 hw->aq.asq_last_status);
10080 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10081 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10083 /* Update Queue Pairs Mapping for currently enabled UPs */
10084 ctxt.seid = vsi->seid;
10085 ctxt.pf_num = hw->pf_id;
10087 ctxt.uplink_seid = vsi->uplink_seid;
10088 ctxt.info = vsi->info;
10090 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10094 /* Update the VSI after updating the VSI queue-mapping information */
10095 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10097 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10098 hw->aq.asq_last_status);
10101 /* update the local VSI info with updated queue map */
10102 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10103 sizeof(vsi->info.tc_mapping));
10104 (void)rte_memcpy(&vsi->info.queue_mapping,
10105 &ctxt.info.queue_mapping,
10106 sizeof(vsi->info.queue_mapping));
10107 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10108 vsi->info.valid_sections = 0;
10110 /* query and update current VSI BW information */
10111 ret = i40e_vsi_get_bw_config(vsi);
10114 "Failed updating vsi bw info, err %s aq_err %s",
10115 i40e_stat_str(hw, ret),
10116 i40e_aq_str(hw, hw->aq.asq_last_status));
10120 vsi->enabled_tc = tc_map;
10127 * i40e_dcb_hw_configure - program the dcb setting to hw
10128 * @pf: pf the configuration is taken on
10129 * @new_cfg: new configuration
10130 * @tc_map: enabled TC bitmap
10132 * Returns 0 on success, negative value on failure
10134 static enum i40e_status_code
10135 i40e_dcb_hw_configure(struct i40e_pf *pf,
10136 struct i40e_dcbx_config *new_cfg,
10139 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10140 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10141 struct i40e_vsi *main_vsi = pf->main_vsi;
10142 struct i40e_vsi_list *vsi_list;
10143 enum i40e_status_code ret;
10147 /* Use the FW API if FW > v4.4*/
10148 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10149 (hw->aq.fw_maj_ver >= 5))) {
10151 "FW < v4.4, can not use FW LLDP API to configure DCB");
10152 return I40E_ERR_FIRMWARE_API_VERSION;
10155 /* Check if need reconfiguration */
10156 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10157 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10158 return I40E_SUCCESS;
10161 /* Copy the new config to the current config */
10162 *old_cfg = *new_cfg;
10163 old_cfg->etsrec = old_cfg->etscfg;
10164 ret = i40e_set_dcb_config(hw);
10166 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10167 i40e_stat_str(hw, ret),
10168 i40e_aq_str(hw, hw->aq.asq_last_status));
10171 /* set receive Arbiter to RR mode and ETS scheme by default */
10172 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10173 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10174 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10175 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10176 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10177 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10178 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10179 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10180 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10181 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10182 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10183 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10184 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10186 /* get local mib to check whether it is configured correctly */
10188 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10189 /* Get Local DCB Config */
10190 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10191 &hw->local_dcbx_config);
10193 /* if Veb is created, need to update TC of it at first */
10194 if (main_vsi->veb) {
10195 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10197 PMD_INIT_LOG(WARNING,
10198 "Failed configuring TC for VEB seid=%d",
10199 main_vsi->veb->seid);
10201 /* Update each VSI */
10202 i40e_vsi_config_tc(main_vsi, tc_map);
10203 if (main_vsi->veb) {
10204 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10205 /* Beside main VSI and VMDQ VSIs, only enable default
10206 * TC for other VSIs
10208 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10209 ret = i40e_vsi_config_tc(vsi_list->vsi,
10212 ret = i40e_vsi_config_tc(vsi_list->vsi,
10213 I40E_DEFAULT_TCMAP);
10215 PMD_INIT_LOG(WARNING,
10216 "Failed configuring TC for VSI seid=%d",
10217 vsi_list->vsi->seid);
10221 return I40E_SUCCESS;
10225 * i40e_dcb_init_configure - initial dcb config
10226 * @dev: device being configured
10227 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10229 * Returns 0 on success, negative value on failure
10232 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10234 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10235 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10238 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10239 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10243 /* DCB initialization:
10244 * Update DCB configuration from the Firmware and configure
10245 * LLDP MIB change event.
10247 if (sw_dcb == TRUE) {
10248 ret = i40e_init_dcb(hw);
10249 /* If lldp agent is stopped, the return value from
10250 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10251 * adminq status. Otherwise, it should return success.
10253 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10254 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10255 memset(&hw->local_dcbx_config, 0,
10256 sizeof(struct i40e_dcbx_config));
10257 /* set dcb default configuration */
10258 hw->local_dcbx_config.etscfg.willing = 0;
10259 hw->local_dcbx_config.etscfg.maxtcs = 0;
10260 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10261 hw->local_dcbx_config.etscfg.tsatable[0] =
10263 /* all UPs mapping to TC0 */
10264 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10265 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10266 hw->local_dcbx_config.etsrec =
10267 hw->local_dcbx_config.etscfg;
10268 hw->local_dcbx_config.pfc.willing = 0;
10269 hw->local_dcbx_config.pfc.pfccap =
10270 I40E_MAX_TRAFFIC_CLASS;
10271 hw->local_dcbx_config.pfc.pfcenable =
10272 I40E_DEFAULT_TCMAP;
10273 /* FW needs one App to configure HW */
10274 hw->local_dcbx_config.numapps = 1;
10275 hw->local_dcbx_config.app[0].selector =
10276 I40E_APP_SEL_ETHTYPE;
10277 hw->local_dcbx_config.app[0].priority = 3;
10278 hw->local_dcbx_config.app[0].protocolid =
10279 I40E_APP_PROTOID_FCOE;
10280 ret = i40e_set_dcb_config(hw);
10283 "default dcb config fails. err = %d, aq_err = %d.",
10284 ret, hw->aq.asq_last_status);
10289 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10290 ret, hw->aq.asq_last_status);
10294 ret = i40e_aq_start_lldp(hw, NULL);
10295 if (ret != I40E_SUCCESS)
10296 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10298 ret = i40e_init_dcb(hw);
10300 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10302 "HW doesn't support DCBX offload.");
10307 "DCBX configuration failed, err = %d, aq_err = %d.",
10308 ret, hw->aq.asq_last_status);
10316 * i40e_dcb_setup - setup dcb related config
10317 * @dev: device being configured
10319 * Returns 0 on success, negative value on failure
10322 i40e_dcb_setup(struct rte_eth_dev *dev)
10324 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10325 struct i40e_dcbx_config dcb_cfg;
10326 uint8_t tc_map = 0;
10329 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10330 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10334 if (pf->vf_num != 0)
10335 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10337 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10339 PMD_INIT_LOG(ERR, "invalid dcb config");
10342 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10344 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10352 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10353 struct rte_eth_dcb_info *dcb_info)
10355 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10356 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10357 struct i40e_vsi *vsi = pf->main_vsi;
10358 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10359 uint16_t bsf, tc_mapping;
10362 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10363 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10365 dcb_info->nb_tcs = 1;
10366 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10367 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10368 for (i = 0; i < dcb_info->nb_tcs; i++)
10369 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10371 /* get queue mapping if vmdq is disabled */
10372 if (!pf->nb_cfg_vmdq_vsi) {
10373 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10374 if (!(vsi->enabled_tc & (1 << i)))
10376 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10377 dcb_info->tc_queue.tc_rxq[j][i].base =
10378 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10379 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10380 dcb_info->tc_queue.tc_txq[j][i].base =
10381 dcb_info->tc_queue.tc_rxq[j][i].base;
10382 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10383 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10384 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10385 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10386 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10391 /* get queue mapping if vmdq is enabled */
10393 vsi = pf->vmdq[j].vsi;
10394 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10395 if (!(vsi->enabled_tc & (1 << i)))
10397 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10398 dcb_info->tc_queue.tc_rxq[j][i].base =
10399 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10400 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10401 dcb_info->tc_queue.tc_txq[j][i].base =
10402 dcb_info->tc_queue.tc_rxq[j][i].base;
10403 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10404 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10405 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10406 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10407 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10410 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10415 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10417 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10418 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10419 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10420 uint16_t interval =
10421 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10422 uint16_t msix_intr;
10424 msix_intr = intr_handle->intr_vec[queue_id];
10425 if (msix_intr == I40E_MISC_VEC_ID)
10426 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10427 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10428 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10429 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10431 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10434 I40E_PFINT_DYN_CTLN(msix_intr -
10435 I40E_RX_VEC_START),
10436 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10437 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10438 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10440 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10442 I40E_WRITE_FLUSH(hw);
10443 rte_intr_enable(&pci_dev->intr_handle);
10449 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10451 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10452 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10453 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10454 uint16_t msix_intr;
10456 msix_intr = intr_handle->intr_vec[queue_id];
10457 if (msix_intr == I40E_MISC_VEC_ID)
10458 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10461 I40E_PFINT_DYN_CTLN(msix_intr -
10462 I40E_RX_VEC_START),
10464 I40E_WRITE_FLUSH(hw);
10469 static int i40e_get_regs(struct rte_eth_dev *dev,
10470 struct rte_dev_reg_info *regs)
10472 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10473 uint32_t *ptr_data = regs->data;
10474 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10475 const struct i40e_reg_info *reg_info;
10477 if (ptr_data == NULL) {
10478 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10479 regs->width = sizeof(uint32_t);
10483 /* The first few registers have to be read using AQ operations */
10485 while (i40e_regs_adminq[reg_idx].name) {
10486 reg_info = &i40e_regs_adminq[reg_idx++];
10487 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10489 arr_idx2 <= reg_info->count2;
10491 reg_offset = arr_idx * reg_info->stride1 +
10492 arr_idx2 * reg_info->stride2;
10493 reg_offset += reg_info->base_addr;
10494 ptr_data[reg_offset >> 2] =
10495 i40e_read_rx_ctl(hw, reg_offset);
10499 /* The remaining registers can be read using primitives */
10501 while (i40e_regs_others[reg_idx].name) {
10502 reg_info = &i40e_regs_others[reg_idx++];
10503 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10505 arr_idx2 <= reg_info->count2;
10507 reg_offset = arr_idx * reg_info->stride1 +
10508 arr_idx2 * reg_info->stride2;
10509 reg_offset += reg_info->base_addr;
10510 ptr_data[reg_offset >> 2] =
10511 I40E_READ_REG(hw, reg_offset);
10518 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10520 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10522 /* Convert word count to byte count */
10523 return hw->nvm.sr_size << 1;
10526 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10527 struct rte_dev_eeprom_info *eeprom)
10529 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10530 uint16_t *data = eeprom->data;
10531 uint16_t offset, length, cnt_words;
10534 offset = eeprom->offset >> 1;
10535 length = eeprom->length >> 1;
10536 cnt_words = length;
10538 if (offset > hw->nvm.sr_size ||
10539 offset + length > hw->nvm.sr_size) {
10540 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10544 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10546 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10547 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10548 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10555 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10556 struct ether_addr *mac_addr)
10558 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10560 if (!is_valid_assigned_ether_addr(mac_addr)) {
10561 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10565 /* Flags: 0x3 updates port address */
10566 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10570 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10572 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10573 struct rte_eth_dev_data *dev_data = pf->dev_data;
10574 uint32_t frame_size = mtu + ETHER_HDR_LEN
10575 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10578 /* check if mtu is within the allowed range */
10579 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10582 /* mtu setting is forbidden if port is start */
10583 if (dev_data->dev_started) {
10584 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10585 dev_data->port_id);
10589 if (frame_size > ETHER_MAX_LEN)
10590 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10592 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10594 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10599 /* Restore ethertype filter */
10601 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10603 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10604 struct i40e_ethertype_filter_list
10605 *ethertype_list = &pf->ethertype.ethertype_list;
10606 struct i40e_ethertype_filter *f;
10607 struct i40e_control_filter_stats stats;
10610 TAILQ_FOREACH(f, ethertype_list, rules) {
10612 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10613 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10614 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10615 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10616 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10618 memset(&stats, 0, sizeof(stats));
10619 i40e_aq_add_rem_control_packet_filter(hw,
10620 f->input.mac_addr.addr_bytes,
10621 f->input.ether_type,
10622 flags, pf->main_vsi->seid,
10623 f->queue, 1, &stats, NULL);
10625 PMD_DRV_LOG(INFO, "Ethertype filter:"
10626 " mac_etype_used = %u, etype_used = %u,"
10627 " mac_etype_free = %u, etype_free = %u",
10628 stats.mac_etype_used, stats.etype_used,
10629 stats.mac_etype_free, stats.etype_free);
10632 /* Restore tunnel filter */
10634 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10636 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10637 struct i40e_vsi *vsi;
10638 struct i40e_pf_vf *vf;
10639 struct i40e_tunnel_filter_list
10640 *tunnel_list = &pf->tunnel.tunnel_list;
10641 struct i40e_tunnel_filter *f;
10642 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10643 bool big_buffer = 0;
10645 TAILQ_FOREACH(f, tunnel_list, rules) {
10647 vsi = pf->main_vsi;
10649 vf = &pf->vfs[f->vf_id];
10652 memset(&cld_filter, 0, sizeof(cld_filter));
10653 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10654 (struct ether_addr *)&cld_filter.element.outer_mac);
10655 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10656 (struct ether_addr *)&cld_filter.element.inner_mac);
10657 cld_filter.element.inner_vlan = f->input.inner_vlan;
10658 cld_filter.element.flags = f->input.flags;
10659 cld_filter.element.tenant_id = f->input.tenant_id;
10660 cld_filter.element.queue_number = f->queue;
10661 rte_memcpy(cld_filter.general_fields,
10662 f->input.general_fields,
10663 sizeof(f->input.general_fields));
10665 if (((f->input.flags &
10666 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10667 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10669 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10670 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10672 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10673 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10677 i40e_aq_add_cloud_filters_big_buffer(hw,
10678 vsi->seid, &cld_filter, 1);
10680 i40e_aq_add_cloud_filters(hw, vsi->seid,
10681 &cld_filter.element, 1);
10686 i40e_filter_restore(struct i40e_pf *pf)
10688 i40e_ethertype_filter_restore(pf);
10689 i40e_tunnel_filter_restore(pf);
10690 i40e_fdir_filter_restore(pf);
10694 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
10696 if (strcmp(dev->driver->pci_drv.driver.name,
10697 drv->pci_drv.driver.name))
10704 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10706 struct rte_eth_dev *dev;
10707 struct i40e_pf *pf;
10709 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10711 dev = &rte_eth_devices[port];
10713 if (!is_device_supported(dev, &rte_i40e_pmd))
10716 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10718 if (vf >= pf->vf_num || !pf->vfs) {
10719 PMD_DRV_LOG(ERR, "Invalid argument.");
10723 i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
10729 rte_pmd_i40e_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10731 struct rte_eth_dev *dev;
10732 struct i40e_pf *pf;
10733 struct i40e_vsi *vsi;
10734 struct i40e_hw *hw;
10735 struct i40e_vsi_context ctxt;
10738 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10740 dev = &rte_eth_devices[port];
10742 if (!is_device_supported(dev, &rte_i40e_pmd))
10745 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10747 if (vf_id >= pf->vf_num || !pf->vfs) {
10748 PMD_DRV_LOG(ERR, "Invalid argument.");
10752 vsi = pf->vfs[vf_id].vsi;
10754 PMD_DRV_LOG(ERR, "Invalid VSI.");
10758 /* Check if it has been already on or off */
10759 if (vsi->info.valid_sections &
10760 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
10762 if ((vsi->info.sec_flags &
10763 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
10764 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
10765 return 0; /* already on */
10767 if ((vsi->info.sec_flags &
10768 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
10769 return 0; /* already off */
10773 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10775 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10777 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10779 memset(&ctxt, 0, sizeof(ctxt));
10780 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10781 ctxt.seid = vsi->seid;
10783 hw = I40E_VSI_TO_HW(vsi);
10784 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10785 if (ret != I40E_SUCCESS) {
10787 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10794 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
10798 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10799 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
10802 for (j = 0; j < I40E_VFTA_SIZE; j++) {
10806 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
10807 if (!(vsi->vfta[j] & (1 << k)))
10810 vlan_id = j * I40E_UINT32_BIT_SIZE + k;
10814 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
10816 ret = i40e_aq_add_vlan(hw, vsi->seid,
10817 &vlan_data, 1, NULL);
10819 ret = i40e_aq_remove_vlan(hw, vsi->seid,
10820 &vlan_data, 1, NULL);
10821 if (ret != I40E_SUCCESS) {
10823 "Failed to add/rm vlan filter");
10829 return I40E_SUCCESS;
10833 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10835 struct rte_eth_dev *dev;
10836 struct i40e_pf *pf;
10837 struct i40e_vsi *vsi;
10838 struct i40e_hw *hw;
10839 struct i40e_vsi_context ctxt;
10842 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10844 dev = &rte_eth_devices[port];
10846 if (!is_device_supported(dev, &rte_i40e_pmd))
10849 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10851 if (vf_id >= pf->vf_num || !pf->vfs) {
10852 PMD_DRV_LOG(ERR, "Invalid argument.");
10856 vsi = pf->vfs[vf_id].vsi;
10858 PMD_DRV_LOG(ERR, "Invalid VSI.");
10862 /* Check if it has been already on or off */
10863 if (vsi->vlan_anti_spoof_on == on)
10864 return 0; /* already on or off */
10866 vsi->vlan_anti_spoof_on = on;
10867 if (!vsi->vlan_filter_on) {
10868 ret = i40e_add_rm_all_vlan_filter(vsi, on);
10870 PMD_DRV_LOG(ERR, "Failed to add/remove VLAN filters.");
10875 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10877 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10879 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10881 memset(&ctxt, 0, sizeof(ctxt));
10882 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10883 ctxt.seid = vsi->seid;
10885 hw = I40E_VSI_TO_HW(vsi);
10886 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10887 if (ret != I40E_SUCCESS) {
10889 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10896 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
10898 struct i40e_mac_filter *f;
10899 struct i40e_macvlan_filter *mv_f;
10901 enum rte_mac_filter_type filter_type;
10902 int ret = I40E_SUCCESS;
10905 /* remove all the MACs */
10906 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10907 vlan_num = vsi->vlan_num;
10908 filter_type = f->mac_info.filter_type;
10909 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10910 filter_type == RTE_MACVLAN_HASH_MATCH) {
10911 if (vlan_num == 0) {
10912 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
10913 return I40E_ERR_PARAM;
10915 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
10916 filter_type == RTE_MAC_HASH_MATCH)
10919 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10921 PMD_DRV_LOG(ERR, "failed to allocate memory");
10922 return I40E_ERR_NO_MEMORY;
10925 for (i = 0; i < vlan_num; i++) {
10926 mv_f[i].filter_type = filter_type;
10927 (void)rte_memcpy(&mv_f[i].macaddr,
10928 &f->mac_info.mac_addr,
10931 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10932 filter_type == RTE_MACVLAN_HASH_MATCH) {
10933 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10934 &f->mac_info.mac_addr);
10935 if (ret != I40E_SUCCESS) {
10941 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
10942 if (ret != I40E_SUCCESS) {
10948 ret = I40E_SUCCESS;
10955 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
10957 struct i40e_mac_filter *f;
10958 struct i40e_macvlan_filter *mv_f;
10959 int i, vlan_num = 0;
10960 int ret = I40E_SUCCESS;
10963 /* restore all the MACs */
10964 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10965 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
10966 (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
10968 * If vlan_num is 0, that's the first time to add mac,
10969 * set mask for vlan_id 0.
10971 if (vsi->vlan_num == 0) {
10972 i40e_set_vlan_filter(vsi, 0, 1);
10975 vlan_num = vsi->vlan_num;
10976 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
10977 (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
10980 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10982 PMD_DRV_LOG(ERR, "failed to allocate memory");
10983 return I40E_ERR_NO_MEMORY;
10986 for (i = 0; i < vlan_num; i++) {
10987 mv_f[i].filter_type = f->mac_info.filter_type;
10988 (void)rte_memcpy(&mv_f[i].macaddr,
10989 &f->mac_info.mac_addr,
10993 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10994 f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
10995 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10996 &f->mac_info.mac_addr);
10997 if (ret != I40E_SUCCESS) {
11003 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
11004 if (ret != I40E_SUCCESS) {
11010 ret = I40E_SUCCESS;
11017 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
11019 struct i40e_vsi_context ctxt;
11020 struct i40e_hw *hw;
11026 hw = I40E_VSI_TO_HW(vsi);
11028 /* Use the FW API if FW >= v5.0 */
11029 if (hw->aq.fw_maj_ver < 5) {
11030 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
11034 /* Check if it has been already on or off */
11035 if (vsi->info.valid_sections &
11036 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
11038 if ((vsi->info.switch_id &
11039 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
11040 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
11041 return 0; /* already on */
11043 if ((vsi->info.switch_id &
11044 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
11045 return 0; /* already off */
11049 /* remove all the MAC and VLAN first */
11050 ret = i40e_vsi_rm_mac_filter(vsi);
11052 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
11055 if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
11056 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
11058 PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
11063 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
11065 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
11067 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
11069 memset(&ctxt, 0, sizeof(ctxt));
11070 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11071 ctxt.seid = vsi->seid;
11073 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11074 if (ret != I40E_SUCCESS) {
11075 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11079 /* add all the MAC and VLAN back */
11080 ret = i40e_vsi_restore_mac_filter(vsi);
11083 if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
11084 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
11093 rte_pmd_i40e_set_tx_loopback(uint8_t port, uint8_t on)
11095 struct rte_eth_dev *dev;
11096 struct i40e_pf *pf;
11097 struct i40e_pf_vf *vf;
11098 struct i40e_vsi *vsi;
11102 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11104 dev = &rte_eth_devices[port];
11106 if (!is_device_supported(dev, &rte_i40e_pmd))
11109 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11111 /* setup PF TX loopback */
11112 vsi = pf->main_vsi;
11113 ret = i40e_vsi_set_tx_loopback(vsi, on);
11117 /* setup TX loopback for all the VFs */
11119 /* if no VF, do nothing. */
11123 for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
11124 vf = &pf->vfs[vf_id];
11127 ret = i40e_vsi_set_tx_loopback(vsi, on);
11136 rte_pmd_i40e_set_vf_unicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
11138 struct rte_eth_dev *dev;
11139 struct i40e_pf *pf;
11140 struct i40e_vsi *vsi;
11141 struct i40e_hw *hw;
11144 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11146 dev = &rte_eth_devices[port];
11148 if (!is_device_supported(dev, &rte_i40e_pmd))
11151 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11153 if (vf_id >= pf->vf_num || !pf->vfs) {
11154 PMD_DRV_LOG(ERR, "Invalid argument.");
11158 vsi = pf->vfs[vf_id].vsi;
11160 PMD_DRV_LOG(ERR, "Invalid VSI.");
11164 hw = I40E_VSI_TO_HW(vsi);
11166 ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
11168 if (ret != I40E_SUCCESS) {
11170 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
11177 rte_pmd_i40e_set_vf_multicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
11179 struct rte_eth_dev *dev;
11180 struct i40e_pf *pf;
11181 struct i40e_vsi *vsi;
11182 struct i40e_hw *hw;
11185 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11187 dev = &rte_eth_devices[port];
11189 if (!is_device_supported(dev, &rte_i40e_pmd))
11192 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11194 if (vf_id >= pf->vf_num || !pf->vfs) {
11195 PMD_DRV_LOG(ERR, "Invalid argument.");
11199 vsi = pf->vfs[vf_id].vsi;
11201 PMD_DRV_LOG(ERR, "Invalid VSI.");
11205 hw = I40E_VSI_TO_HW(vsi);
11207 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
11209 if (ret != I40E_SUCCESS) {
11211 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
11218 rte_pmd_i40e_set_vf_mac_addr(uint8_t port, uint16_t vf_id,
11219 struct ether_addr *mac_addr)
11221 struct i40e_mac_filter *f;
11222 struct rte_eth_dev *dev;
11223 struct i40e_pf_vf *vf;
11224 struct i40e_vsi *vsi;
11225 struct i40e_pf *pf;
11228 if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
11231 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11233 dev = &rte_eth_devices[port];
11235 if (!is_device_supported(dev, &rte_i40e_pmd))
11238 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11240 if (vf_id >= pf->vf_num || !pf->vfs)
11243 vf = &pf->vfs[vf_id];
11246 PMD_DRV_LOG(ERR, "Invalid VSI.");
11250 ether_addr_copy(mac_addr, &vf->mac_addr);
11252 /* Remove all existing mac */
11253 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
11254 i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
11259 /* Set vlan strip on/off for specific VF from host */
11261 rte_pmd_i40e_set_vf_vlan_stripq(uint8_t port, uint16_t vf_id, uint8_t on)
11263 struct rte_eth_dev *dev;
11264 struct i40e_pf *pf;
11265 struct i40e_vsi *vsi;
11268 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11270 dev = &rte_eth_devices[port];
11272 if (!is_device_supported(dev, &rte_i40e_pmd))
11275 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11277 if (vf_id >= pf->vf_num || !pf->vfs) {
11278 PMD_DRV_LOG(ERR, "Invalid argument.");
11282 vsi = pf->vfs[vf_id].vsi;
11287 ret = i40e_vsi_config_vlan_stripping(vsi, !!on);
11288 if (ret != I40E_SUCCESS) {
11290 PMD_DRV_LOG(ERR, "Failed to set VLAN stripping!");
11296 int rte_pmd_i40e_set_vf_vlan_insert(uint8_t port, uint16_t vf_id,
11299 struct rte_eth_dev *dev;
11300 struct i40e_pf *pf;
11301 struct i40e_hw *hw;
11302 struct i40e_vsi *vsi;
11303 struct i40e_vsi_context ctxt;
11306 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11308 if (vlan_id > ETHER_MAX_VLAN_ID) {
11309 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11313 dev = &rte_eth_devices[port];
11315 if (!is_device_supported(dev, &rte_i40e_pmd))
11318 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11319 hw = I40E_PF_TO_HW(pf);
11322 * return -ENODEV if SRIOV not enabled, VF number not configured
11323 * or no queue assigned.
11325 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11326 pf->vf_nb_qps == 0)
11329 if (vf_id >= pf->vf_num || !pf->vfs) {
11330 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11334 vsi = pf->vfs[vf_id].vsi;
11336 PMD_DRV_LOG(ERR, "Invalid VSI.");
11340 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11341 vsi->info.pvid = vlan_id;
11343 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
11345 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_INSERT_PVID;
11347 memset(&ctxt, 0, sizeof(ctxt));
11348 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11349 ctxt.seid = vsi->seid;
11351 hw = I40E_VSI_TO_HW(vsi);
11352 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11353 if (ret != I40E_SUCCESS) {
11355 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11361 int rte_pmd_i40e_set_vf_broadcast(uint8_t port, uint16_t vf_id,
11364 struct rte_eth_dev *dev;
11365 struct i40e_pf *pf;
11366 struct i40e_vsi *vsi;
11367 struct i40e_hw *hw;
11368 struct i40e_mac_filter_info filter;
11369 struct ether_addr broadcast = {
11370 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
11373 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11376 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11380 dev = &rte_eth_devices[port];
11382 if (!is_device_supported(dev, &rte_i40e_pmd))
11385 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11386 hw = I40E_PF_TO_HW(pf);
11388 if (vf_id >= pf->vf_num || !pf->vfs) {
11389 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11394 * return -ENODEV if SRIOV not enabled, VF number not configured
11395 * or no queue assigned.
11397 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11398 pf->vf_nb_qps == 0) {
11399 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11403 vsi = pf->vfs[vf_id].vsi;
11405 PMD_DRV_LOG(ERR, "Invalid VSI.");
11410 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
11411 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
11412 ret = i40e_vsi_add_mac(vsi, &filter);
11414 ret = i40e_vsi_delete_mac(vsi, &broadcast);
11417 if (ret != I40E_SUCCESS && ret != I40E_ERR_PARAM) {
11419 PMD_DRV_LOG(ERR, "Failed to set VSI broadcast");
11427 int rte_pmd_i40e_set_vf_vlan_tag(uint8_t port, uint16_t vf_id, uint8_t on)
11429 struct rte_eth_dev *dev;
11430 struct i40e_pf *pf;
11431 struct i40e_hw *hw;
11432 struct i40e_vsi *vsi;
11433 struct i40e_vsi_context ctxt;
11436 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11439 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11443 dev = &rte_eth_devices[port];
11445 if (!is_device_supported(dev, &rte_i40e_pmd))
11448 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11449 hw = I40E_PF_TO_HW(pf);
11452 * return -ENODEV if SRIOV not enabled, VF number not configured
11453 * or no queue assigned.
11455 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11456 pf->vf_nb_qps == 0) {
11457 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11461 if (vf_id >= pf->vf_num || !pf->vfs) {
11462 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11466 vsi = pf->vfs[vf_id].vsi;
11468 PMD_DRV_LOG(ERR, "Invalid VSI.");
11472 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11474 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11475 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11477 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11478 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11481 memset(&ctxt, 0, sizeof(ctxt));
11482 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11483 ctxt.seid = vsi->seid;
11485 hw = I40E_VSI_TO_HW(vsi);
11486 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11487 if (ret != I40E_SUCCESS) {
11489 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11496 i40e_vlan_filter_count(struct i40e_vsi *vsi)
11502 for (j = 0; j < I40E_VFTA_SIZE; j++) {
11506 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
11507 if (!(vsi->vfta[j] & (1 << k)))
11510 vlan_id = j * I40E_UINT32_BIT_SIZE + k;
11521 int rte_pmd_i40e_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,
11522 uint64_t vf_mask, uint8_t on)
11524 struct rte_eth_dev *dev;
11525 struct i40e_pf *pf;
11526 struct i40e_hw *hw;
11527 struct i40e_vsi *vsi;
11529 int ret = I40E_SUCCESS;
11531 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11533 dev = &rte_eth_devices[port];
11535 if (!is_device_supported(dev, &rte_i40e_pmd))
11538 if (vlan_id > ETHER_MAX_VLAN_ID || !vlan_id) {
11539 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11543 if (vf_mask == 0) {
11544 PMD_DRV_LOG(ERR, "No VF.");
11549 PMD_DRV_LOG(ERR, "on is should be 0 or 1.");
11553 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11554 hw = I40E_PF_TO_HW(pf);
11557 * return -ENODEV if SRIOV not enabled, VF number not configured
11558 * or no queue assigned.
11560 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11561 pf->vf_nb_qps == 0) {
11562 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11566 for (vf_idx = 0; vf_idx < pf->vf_num && ret == I40E_SUCCESS; vf_idx++) {
11567 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
11568 vsi = pf->vfs[vf_idx].vsi;
11570 if (!vsi->vlan_filter_on) {
11571 vsi->vlan_filter_on = true;
11572 i40e_aq_set_vsi_vlan_promisc(hw,
11576 if (!vsi->vlan_anti_spoof_on)
11577 i40e_add_rm_all_vlan_filter(
11580 ret = i40e_vsi_add_vlan(vsi, vlan_id);
11582 ret = i40e_vsi_delete_vlan(vsi, vlan_id);
11584 if (!i40e_vlan_filter_count(vsi)) {
11585 vsi->vlan_filter_on = false;
11586 i40e_aq_set_vsi_vlan_promisc(hw,
11595 if (ret != I40E_SUCCESS) {
11597 PMD_DRV_LOG(ERR, "Failed to set VF VLAN filter, on = %d", on);
11604 rte_pmd_i40e_get_vf_stats(uint8_t port,
11606 struct rte_eth_stats *stats)
11608 struct rte_eth_dev *dev;
11609 struct i40e_pf *pf;
11610 struct i40e_vsi *vsi;
11612 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11614 dev = &rte_eth_devices[port];
11616 if (!is_device_supported(dev, &rte_i40e_pmd))
11619 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11621 if (vf_id >= pf->vf_num || !pf->vfs) {
11622 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11626 vsi = pf->vfs[vf_id].vsi;
11628 PMD_DRV_LOG(ERR, "Invalid VSI.");
11632 i40e_update_vsi_stats(vsi);
11634 stats->ipackets = vsi->eth_stats.rx_unicast +
11635 vsi->eth_stats.rx_multicast +
11636 vsi->eth_stats.rx_broadcast;
11637 stats->opackets = vsi->eth_stats.tx_unicast +
11638 vsi->eth_stats.tx_multicast +
11639 vsi->eth_stats.tx_broadcast;
11640 stats->ibytes = vsi->eth_stats.rx_bytes;
11641 stats->obytes = vsi->eth_stats.tx_bytes;
11642 stats->ierrors = vsi->eth_stats.rx_discards;
11643 stats->oerrors = vsi->eth_stats.tx_errors + vsi->eth_stats.tx_discards;
11649 rte_pmd_i40e_reset_vf_stats(uint8_t port,
11652 struct rte_eth_dev *dev;
11653 struct i40e_pf *pf;
11654 struct i40e_vsi *vsi;
11656 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11658 dev = &rte_eth_devices[port];
11660 if (!is_device_supported(dev, &rte_i40e_pmd))
11663 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11665 if (vf_id >= pf->vf_num || !pf->vfs) {
11666 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11670 vsi = pf->vfs[vf_id].vsi;
11672 PMD_DRV_LOG(ERR, "Invalid VSI.");
11676 vsi->offset_loaded = false;
11677 i40e_update_vsi_stats(vsi);
11683 rte_pmd_i40e_set_vf_max_bw(uint8_t port, uint16_t vf_id, uint32_t bw)
11685 struct rte_eth_dev *dev;
11686 struct i40e_pf *pf;
11687 struct i40e_vsi *vsi;
11688 struct i40e_hw *hw;
11692 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11694 dev = &rte_eth_devices[port];
11696 if (!is_device_supported(dev, &rte_i40e_pmd))
11699 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11701 if (vf_id >= pf->vf_num || !pf->vfs) {
11702 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11706 vsi = pf->vfs[vf_id].vsi;
11708 PMD_DRV_LOG(ERR, "Invalid VSI.");
11712 if (bw > I40E_QOS_BW_MAX) {
11713 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
11718 if (bw % I40E_QOS_BW_GRANULARITY) {
11719 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
11720 I40E_QOS_BW_GRANULARITY);
11724 bw /= I40E_QOS_BW_GRANULARITY;
11726 hw = I40E_VSI_TO_HW(vsi);
11729 if (bw == vsi->bw_info.bw_limit) {
11731 "No change for VF max bandwidth. Nothing to do.");
11736 * VF bandwidth limitation and TC bandwidth limitation cannot be
11737 * enabled in parallel, quit if TC bandwidth limitation is enabled.
11739 * If bw is 0, means disable bandwidth limitation. Then no need to
11740 * check TC bandwidth limitation.
11743 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11744 if ((vsi->enabled_tc & BIT_ULL(i)) &&
11745 vsi->bw_info.bw_ets_credits[i])
11748 if (i != I40E_MAX_TRAFFIC_CLASS) {
11750 "TC max bandwidth has been set on this VF,"
11751 " please disable it first.");
11756 ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, (uint16_t)bw, 0, NULL);
11759 "Failed to set VF %d bandwidth, err(%d).",
11764 /* Store the configuration. */
11765 vsi->bw_info.bw_limit = (uint16_t)bw;
11766 vsi->bw_info.bw_max = 0;
11772 rte_pmd_i40e_set_vf_tc_bw_alloc(uint8_t port, uint16_t vf_id,
11773 uint8_t tc_num, uint8_t *bw_weight)
11775 struct rte_eth_dev *dev;
11776 struct i40e_pf *pf;
11777 struct i40e_vsi *vsi;
11778 struct i40e_hw *hw;
11779 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw;
11783 bool b_change = false;
11785 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11787 dev = &rte_eth_devices[port];
11789 if (!is_device_supported(dev, &rte_i40e_pmd))
11792 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11794 if (vf_id >= pf->vf_num || !pf->vfs) {
11795 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11799 vsi = pf->vfs[vf_id].vsi;
11801 PMD_DRV_LOG(ERR, "Invalid VSI.");
11805 if (tc_num > I40E_MAX_TRAFFIC_CLASS) {
11806 PMD_DRV_LOG(ERR, "TCs should be no more than %d.",
11807 I40E_MAX_TRAFFIC_CLASS);
11812 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11813 if (vsi->enabled_tc & BIT_ULL(i))
11816 if (sum != tc_num) {
11818 "Weight should be set for all %d enabled TCs.",
11824 for (i = 0; i < tc_num; i++) {
11825 if (!bw_weight[i]) {
11827 "The weight should be 1 at least.");
11830 sum += bw_weight[i];
11834 "The summary of the TC weight should be 100.");
11839 * Create the configuration for all the TCs.
11841 memset(&tc_bw, 0, sizeof(tc_bw));
11842 tc_bw.tc_valid_bits = vsi->enabled_tc;
11844 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11845 if (vsi->enabled_tc & BIT_ULL(i)) {
11846 if (bw_weight[j] !=
11847 vsi->bw_info.bw_ets_share_credits[i])
11850 tc_bw.tc_bw_credits[i] = bw_weight[j];
11858 "No change for TC allocated bandwidth."
11859 " Nothing to do.");
11863 hw = I40E_VSI_TO_HW(vsi);
11865 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw, NULL);
11868 "Failed to set VF %d TC bandwidth weight, err(%d).",
11873 /* Store the configuration. */
11875 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11876 if (vsi->enabled_tc & BIT_ULL(i)) {
11877 vsi->bw_info.bw_ets_share_credits[i] = bw_weight[j];
11886 rte_pmd_i40e_set_vf_tc_max_bw(uint8_t port, uint16_t vf_id,
11887 uint8_t tc_no, uint32_t bw)
11889 struct rte_eth_dev *dev;
11890 struct i40e_pf *pf;
11891 struct i40e_vsi *vsi;
11892 struct i40e_hw *hw;
11893 struct i40e_aqc_configure_vsi_ets_sla_bw_data tc_bw;
11897 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11899 dev = &rte_eth_devices[port];
11901 if (!is_device_supported(dev, &rte_i40e_pmd))
11904 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11906 if (vf_id >= pf->vf_num || !pf->vfs) {
11907 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11911 vsi = pf->vfs[vf_id].vsi;
11913 PMD_DRV_LOG(ERR, "Invalid VSI.");
11917 if (bw > I40E_QOS_BW_MAX) {
11918 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
11923 if (bw % I40E_QOS_BW_GRANULARITY) {
11924 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
11925 I40E_QOS_BW_GRANULARITY);
11929 bw /= I40E_QOS_BW_GRANULARITY;
11931 if (tc_no >= I40E_MAX_TRAFFIC_CLASS) {
11932 PMD_DRV_LOG(ERR, "TC No. should be less than %d.",
11933 I40E_MAX_TRAFFIC_CLASS);
11937 hw = I40E_VSI_TO_HW(vsi);
11939 if (!(vsi->enabled_tc & BIT_ULL(tc_no))) {
11940 PMD_DRV_LOG(ERR, "VF %d TC %d isn't enabled.",
11946 if (bw == vsi->bw_info.bw_ets_credits[tc_no]) {
11948 "No change for TC max bandwidth. Nothing to do.");
11953 * VF bandwidth limitation and TC bandwidth limitation cannot be
11954 * enabled in parallel, disable VF bandwidth limitation if it's
11956 * If bw is 0, means disable bandwidth limitation. Then no need to
11957 * care about VF bandwidth limitation configuration.
11959 if (bw && vsi->bw_info.bw_limit) {
11960 ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, 0, 0, NULL);
11963 "Failed to disable VF(%d)"
11964 " bandwidth limitation, err(%d).",
11970 "VF max bandwidth is disabled according"
11971 " to TC max bandwidth setting.");
11975 * Get all the TCs' info to create a whole picture.
11976 * Because the incremental change isn't permitted.
11978 memset(&tc_bw, 0, sizeof(tc_bw));
11979 tc_bw.tc_valid_bits = vsi->enabled_tc;
11980 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11981 if (vsi->enabled_tc & BIT_ULL(i)) {
11982 tc_bw.tc_bw_credits[i] =
11984 vsi->bw_info.bw_ets_credits[i]);
11987 tc_bw.tc_bw_credits[tc_no] = rte_cpu_to_le_16((uint16_t)bw);
11989 ret = i40e_aq_config_vsi_ets_sla_bw_limit(hw, vsi->seid, &tc_bw, NULL);
11992 "Failed to set VF %d TC %d max bandwidth, err(%d).",
11993 vf_id, tc_no, ret);
11997 /* Store the configuration. */
11998 vsi->bw_info.bw_ets_credits[tc_no] = (uint16_t)bw;
12004 rte_pmd_i40e_set_tc_strict_prio(uint8_t port, uint8_t tc_map)
12006 struct rte_eth_dev *dev;
12007 struct i40e_pf *pf;
12008 struct i40e_vsi *vsi;
12009 struct i40e_veb *veb;
12010 struct i40e_hw *hw;
12011 struct i40e_aqc_configure_switching_comp_ets_data ets_data;
12015 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12017 dev = &rte_eth_devices[port];
12019 if (!is_device_supported(dev, &rte_i40e_pmd))
12022 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12024 vsi = pf->main_vsi;
12026 PMD_DRV_LOG(ERR, "Invalid VSI.");
12032 PMD_DRV_LOG(ERR, "Invalid VEB.");
12036 if ((tc_map & veb->enabled_tc) != tc_map) {
12038 "TC bitmap isn't the subset of enabled TCs 0x%x.",
12043 if (tc_map == veb->strict_prio_tc) {
12044 PMD_DRV_LOG(INFO, "No change for TC bitmap. Nothing to do.");
12048 hw = I40E_VSI_TO_HW(vsi);
12050 /* Disable DCBx if it's the first time to set strict priority. */
12051 if (!veb->strict_prio_tc) {
12052 ret = i40e_aq_stop_lldp(hw, true, NULL);
12055 "Failed to disable DCBx as it's already"
12059 "DCBx is disabled according to strict"
12060 " priority setting.");
12063 memset(&ets_data, 0, sizeof(ets_data));
12064 ets_data.tc_valid_bits = veb->enabled_tc;
12065 ets_data.seepage = I40E_AQ_ETS_SEEPAGE_EN_MASK;
12066 ets_data.tc_strict_priority_flags = tc_map;
12067 /* Get all TCs' bandwidth. */
12068 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12069 if (veb->enabled_tc & BIT_ULL(i)) {
12070 /* For rubust, if bandwidth is 0, use 1 instead. */
12071 if (veb->bw_info.bw_ets_share_credits[i])
12072 ets_data.tc_bw_share_credits[i] =
12073 veb->bw_info.bw_ets_share_credits[i];
12075 ets_data.tc_bw_share_credits[i] =
12076 I40E_QOS_BW_WEIGHT_MIN;
12080 if (!veb->strict_prio_tc)
12081 ret = i40e_aq_config_switch_comp_ets(
12082 hw, veb->uplink_seid,
12083 &ets_data, i40e_aqc_opc_enable_switching_comp_ets,
12086 ret = i40e_aq_config_switch_comp_ets(
12087 hw, veb->uplink_seid,
12088 &ets_data, i40e_aqc_opc_modify_switching_comp_ets,
12091 ret = i40e_aq_config_switch_comp_ets(
12092 hw, veb->uplink_seid,
12093 &ets_data, i40e_aqc_opc_disable_switching_comp_ets,
12098 "Failed to set TCs' strict priority mode."
12103 veb->strict_prio_tc = tc_map;
12105 /* Enable DCBx again, if all the TCs' strict priority disabled. */
12107 ret = i40e_aq_start_lldp(hw, NULL);
12110 "Failed to enable DCBx, err(%d).", ret);
12115 "DCBx is enabled again according to strict"
12116 " priority setting.");
12122 #define I40E_PROFILE_INFO_SIZE 48
12123 #define I40E_MAX_PROFILE_NUM 16
12126 i40e_generate_profile_info_sec(char *name, struct i40e_ddp_version *version,
12127 uint32_t track_id, uint8_t *profile_info_sec,
12130 struct i40e_profile_section_header *sec = NULL;
12131 struct i40e_profile_info *pinfo;
12133 sec = (struct i40e_profile_section_header *)profile_info_sec;
12135 sec->data_end = sizeof(struct i40e_profile_section_header) +
12136 sizeof(struct i40e_profile_info);
12137 sec->section.type = SECTION_TYPE_INFO;
12138 sec->section.offset = sizeof(struct i40e_profile_section_header);
12139 sec->section.size = sizeof(struct i40e_profile_info);
12140 pinfo = (struct i40e_profile_info *)(profile_info_sec +
12141 sec->section.offset);
12142 pinfo->track_id = track_id;
12143 memcpy(pinfo->name, name, I40E_DDP_NAME_SIZE);
12144 memcpy(&pinfo->version, version, sizeof(struct i40e_ddp_version));
12146 pinfo->op = I40E_DDP_ADD_TRACKID;
12148 pinfo->op = I40E_DDP_REMOVE_TRACKID;
12151 static enum i40e_status_code
12152 i40e_add_rm_profile_info(struct i40e_hw *hw, uint8_t *profile_info_sec)
12154 enum i40e_status_code status = I40E_SUCCESS;
12155 struct i40e_profile_section_header *sec;
12157 uint32_t offset = 0;
12160 sec = (struct i40e_profile_section_header *)profile_info_sec;
12161 track_id = ((struct i40e_profile_info *)(profile_info_sec +
12162 sec->section.offset))->track_id;
12164 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
12165 track_id, &offset, &info, NULL);
12167 PMD_DRV_LOG(ERR, "Failed to add/remove profile info: "
12168 "offset %d, info %d",
12174 #define I40E_PROFILE_INFO_SIZE 48
12175 #define I40E_MAX_PROFILE_NUM 16
12177 /* Check if the profile info exists */
12179 i40e_check_profile_info(uint8_t port, uint8_t *profile_info_sec)
12181 struct rte_eth_dev *dev = &rte_eth_devices[port];
12182 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12184 struct rte_pmd_i40e_profile_list *p_list;
12185 struct rte_pmd_i40e_profile_info *pinfo, *p;
12189 buff = rte_zmalloc("pinfo_list",
12190 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4),
12193 PMD_DRV_LOG(ERR, "failed to allocate memory");
12197 ret = i40e_aq_get_ddp_list(hw, (void *)buff,
12198 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4),
12201 PMD_DRV_LOG(ERR, "Failed to get profile info list.");
12205 p_list = (struct rte_pmd_i40e_profile_list *)buff;
12206 pinfo = (struct rte_pmd_i40e_profile_info *)(profile_info_sec +
12207 sizeof(struct i40e_profile_section_header));
12208 for (i = 0; i < p_list->p_count; i++) {
12209 p = &p_list->p_info[i];
12210 if ((pinfo->track_id == p->track_id) &&
12211 !memcmp(&pinfo->version, &p->version,
12212 sizeof(struct i40e_ddp_version)) &&
12213 !memcmp(&pinfo->name, &p->name,
12214 I40E_DDP_NAME_SIZE)) {
12215 PMD_DRV_LOG(INFO, "Profile exists.");
12226 rte_pmd_i40e_process_ddp_package(uint8_t port, uint8_t *buff,
12228 enum rte_pmd_i40e_package_op op)
12230 struct rte_eth_dev *dev;
12231 struct i40e_hw *hw;
12232 struct i40e_package_header *pkg_hdr;
12233 struct i40e_generic_seg_header *profile_seg_hdr;
12234 struct i40e_generic_seg_header *metadata_seg_hdr;
12236 uint8_t *profile_info_sec;
12238 enum i40e_status_code status = I40E_SUCCESS;
12240 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12242 dev = &rte_eth_devices[port];
12244 if (!is_device_supported(dev, &rte_i40e_pmd))
12247 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12249 if (size < (sizeof(struct i40e_package_header) +
12250 sizeof(struct i40e_metadata_segment) +
12251 sizeof(uint32_t) * 2)) {
12252 PMD_DRV_LOG(ERR, "Buff is invalid.");
12256 pkg_hdr = (struct i40e_package_header *)buff;
12259 PMD_DRV_LOG(ERR, "Failed to fill the package structure");
12263 if (pkg_hdr->segment_count < 2) {
12264 PMD_DRV_LOG(ERR, "Segment_count should be 2 at least.");
12268 /* Find metadata segment */
12269 metadata_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_METADATA,
12271 if (!metadata_seg_hdr) {
12272 PMD_DRV_LOG(ERR, "Failed to find metadata segment header");
12275 track_id = ((struct i40e_metadata_segment *)metadata_seg_hdr)->track_id;
12277 /* Find profile segment */
12278 profile_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_I40E,
12280 if (!profile_seg_hdr) {
12281 PMD_DRV_LOG(ERR, "Failed to find profile segment header");
12285 profile_info_sec = rte_zmalloc("i40e_profile_info",
12286 sizeof(struct i40e_profile_section_header) +
12287 sizeof(struct i40e_profile_info),
12289 if (!profile_info_sec) {
12290 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12294 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12295 /* Check if the profile exists */
12296 i40e_generate_profile_info_sec(
12297 ((struct i40e_profile_segment *)profile_seg_hdr)->name,
12298 &((struct i40e_profile_segment *)profile_seg_hdr)->version,
12299 track_id, profile_info_sec, 1);
12300 is_exist = i40e_check_profile_info(port, profile_info_sec);
12301 if (is_exist > 0) {
12302 PMD_DRV_LOG(ERR, "Profile already exists.");
12303 rte_free(profile_info_sec);
12305 } else if (is_exist < 0) {
12306 PMD_DRV_LOG(ERR, "Failed to check profile.");
12307 rte_free(profile_info_sec);
12311 /* Write profile to HW */
12312 status = i40e_write_profile(hw,
12313 (struct i40e_profile_segment *)profile_seg_hdr,
12316 PMD_DRV_LOG(ERR, "Failed to write profile.");
12317 rte_free(profile_info_sec);
12321 /* Add profile info to info list */
12322 status = i40e_add_rm_profile_info(hw, profile_info_sec);
12324 PMD_DRV_LOG(ERR, "Failed to add profile info.");
12326 PMD_DRV_LOG(ERR, "Operation not supported.");
12328 rte_free(profile_info_sec);
12333 rte_pmd_i40e_get_ddp_list(uint8_t port, uint8_t *buff, uint32_t size)
12335 struct rte_eth_dev *dev;
12336 struct i40e_hw *hw;
12337 enum i40e_status_code status = I40E_SUCCESS;
12339 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12341 dev = &rte_eth_devices[port];
12343 if (!is_device_supported(dev, &rte_i40e_pmd))
12346 if (size < (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4))
12349 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12351 status = i40e_aq_get_ddp_list(hw, (void *)buff,
12357 /* Create a QinQ cloud filter
12359 * The Fortville NIC has limited resources for tunnel filters,
12360 * so we can only reuse existing filters.
12362 * In step 1 we define which Field Vector fields can be used for
12364 * As we do not have the inner tag defined as a field,
12365 * we have to define it first, by reusing one of L1 entries.
12367 * In step 2 we are replacing one of existing filter types with
12368 * a new one for QinQ.
12369 * As we reusing L1 and replacing L2, some of the default filter
12370 * types will disappear,which depends on L1 and L2 entries we reuse.
12372 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12374 * 1. Create L1 filter of outer vlan (12b) which will be in use
12375 * later when we define the cloud filter.
12376 * a. Valid_flags.replace_cloud = 0
12377 * b. Old_filter = 10 (Stag_Inner_Vlan)
12378 * c. New_filter = 0x10
12379 * d. TR bit = 0xff (optional, not used here)
12380 * e. Buffer – 2 entries:
12381 * i. Byte 0 = 8 (outer vlan FV index).
12383 * Byte 2-3 = 0x0fff
12384 * ii. Byte 0 = 37 (inner vlan FV index).
12386 * Byte 2-3 = 0x0fff
12389 * 2. Create cloud filter using two L1 filters entries: stag and
12390 * new filter(outer vlan+ inner vlan)
12391 * a. Valid_flags.replace_cloud = 1
12392 * b. Old_filter = 1 (instead of outer IP)
12393 * c. New_filter = 0x10
12394 * d. Buffer – 2 entries:
12395 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12396 * Byte 1-3 = 0 (rsv)
12397 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12398 * Byte 9-11 = 0 (rsv)
12401 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12403 int ret = -ENOTSUP;
12404 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12405 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12406 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12409 memset(&filter_replace, 0,
12410 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12411 memset(&filter_replace_buf, 0,
12412 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12414 /* create L1 filter */
12415 filter_replace.old_filter_type =
12416 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12417 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
12418 filter_replace.tr_bit = 0;
12420 /* Prepare the buffer, 2 entries */
12421 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12422 filter_replace_buf.data[0] |=
12423 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12424 /* Field Vector 12b mask */
12425 filter_replace_buf.data[2] = 0xff;
12426 filter_replace_buf.data[3] = 0x0f;
12427 filter_replace_buf.data[4] =
12428 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12429 filter_replace_buf.data[4] |=
12430 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12431 /* Field Vector 12b mask */
12432 filter_replace_buf.data[6] = 0xff;
12433 filter_replace_buf.data[7] = 0x0f;
12434 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12435 &filter_replace_buf);
12436 if (ret != I40E_SUCCESS)
12439 /* Apply the second L2 cloud filter */
12440 memset(&filter_replace, 0,
12441 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12442 memset(&filter_replace_buf, 0,
12443 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12445 /* create L2 filter, input for L2 filter will be L1 filter */
12446 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12447 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12448 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
12450 /* Prepare the buffer, 2 entries */
12451 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12452 filter_replace_buf.data[0] |=
12453 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12454 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
12455 filter_replace_buf.data[4] |=
12456 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12457 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12458 &filter_replace_buf);
12462 RTE_INIT(i40e_init_log);
12464 i40e_init_log(void)
12466 i40e_logtype_init = rte_log_register("pmd.i40e.init");
12467 if (i40e_logtype_init >= 0)
12468 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12469 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
12470 if (i40e_logtype_driver >= 0)
12471 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);