drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54 #include <rte_hash_crc.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_adminq_cmd.h"
  59 #include "base/i40e_type.h"
  60 #include "base/i40e_register.h"
  61 #include "base/i40e_dcb.h"
  62 #include "i40e_ethdev.h"
  63 #include "i40e_rxtx.h"
  64 #include "i40e_pf.h"
  65 #include "i40e_regs.h"
  66
  67 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  68 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  69
  70 #define I40E_CLEAR_PXE_WAIT_MS     200
  71
  72 /* Maximun number of capability elements */
  73 #define I40E_MAX_CAP_ELE_NUM       128
  74
  75 /* Wait count and inteval */
  76 #define I40E_CHK_Q_ENA_COUNT       1000
  77 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  78
  79 /* Maximun number of VSI */
  80 #define I40E_MAX_NUM_VSIS          (384UL)
  81
  82 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  83
  84 /* Flow control default timer */
  85 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  86
  87 /* Flow control default high water */
  88 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  89
  90 /* Flow control default low water */
  91 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  92
  93 /* Flow control enable fwd bit */
  94 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  95
  96 /* Receive Packet Buffer size */
  97 #define I40E_RXPBSIZE (968 * 1024)
  98
  99 /* Kilobytes shift */
 100 #define I40E_KILOSHIFT 10
 101
 102 /* Receive Average Packet Size in Byte*/
 103 #define I40E_PACKET_AVERAGE_SIZE 128
 104
 105 /* Mask of PF interrupt causes */
 106 #define I40E_PFINT_ICR0_ENA_MASK ( \
 107                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 108                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 110                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 111                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 112                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 116
 117 #define I40E_FLOW_TYPES ( \
 118         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 123         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 128         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 129
 130 /* Additional timesync values. */
 131 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA     0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 136 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 /**
 143  * Below are values for writing un-exposed registers suggested
 144  * by silicon experts
 145  */
 146 /* Destination MAC address */
 147 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 148 /* Source MAC address */
 149 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 150 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 151 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 152 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 154 /* Single VLAN tag in the inner L2 header */
 155 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 156 /* Source IPv4 address */
 157 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 158 /* Destination IPv4 address */
 159 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 160 /* Source IPv4 address for X722 */
 161 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 162 /* Destination IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 164 /* IPv4 Protocol for X722 */
 165 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 166 /* IPv4 Time to Live for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 168 /* IPv4 Type of Service (TOS) */
 169 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 170 /* IPv4 Protocol */
 171 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 172 /* IPv4 Time to Live */
 173 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 174 /* Source IPv6 address */
 175 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 176 /* Destination IPv6 address */
 177 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 178 /* IPv6 Traffic Class (TC) */
 179 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 180 /* IPv6 Next Header */
 181 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 182 /* IPv6 Hop Limit */
 183 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 184 /* Source L4 port */
 185 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 186 /* Destination L4 port */
 187 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 188 /* SCTP verification tag */
 189 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 190 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 191 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 192 /* Source port of tunneling UDP */
 193 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 194 /* Destination port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 196 /* UDP Tunneling ID, NVGRE/GRE key */
 197 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 198 /* Last ether type */
 199 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 200 /* Tunneling outer destination IPv4 address */
 201 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 202 /* Tunneling outer destination IPv6 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 204 /* 1st word of flex payload */
 205 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 206 /* 2nd word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 208 /* 3rd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 210 /* 4th word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 212 /* 5th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 214 /* 6th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 216 /* 7th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 218 /* 8th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 220 /* all 8 words flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 222 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 223
 224 #define I40E_TRANSLATE_INSET 0
 225 #define I40E_TRANSLATE_REG   1
 226
 227 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 228 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 229 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 230 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 231 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 232 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 233
 234 /* PCI offset for querying capability */
 235 #define PCI_DEV_CAP_REG            0xA4
 236 /* PCI offset for enabling/disabling Extended Tag */
 237 #define PCI_DEV_CTRL_REG           0xA8
 238 /* Bit mask of Extended Tag capability */
 239 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 240 /* Bit shift of Extended Tag enable/disable */
 241 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 242 /* Bit mask of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 244
 245 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 246 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 247 static int i40e_dev_configure(struct rte_eth_dev *dev);
 248 static int i40e_dev_start(struct rte_eth_dev *dev);
 249 static void i40e_dev_stop(struct rte_eth_dev *dev);
 250 static void i40e_dev_close(struct rte_eth_dev *dev);
 251 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 252 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 253 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 254 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 255 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 256 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 257 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 258                                struct rte_eth_stats *stats);
 259 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 260                                struct rte_eth_xstat *xstats, unsigned n);
 261 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 262                                      struct rte_eth_xstat_name *xstats_names,
 263                                      unsigned limit);
 264 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 265 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 266                                             uint16_t queue_id,
 267                                             uint8_t stat_idx,
 268                                             uint8_t is_rx);
 269 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 270                                 char *fw_version, size_t fw_size);
 271 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 272                               struct rte_eth_dev_info *dev_info);
 273 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 274                                 uint16_t vlan_id,
 275                                 int on);
 276 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 277                               enum rte_vlan_type vlan_type,
 278                               uint16_t tpid);
 279 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 280 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 281                                       uint16_t queue,
 282                                       int on);
 283 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 284 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 285 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 286 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 287                               struct rte_eth_fc_conf *fc_conf);
 288 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 289                               struct rte_eth_fc_conf *fc_conf);
 290 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 291                                        struct rte_eth_pfc_conf *pfc_conf);
 292 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 293                           struct ether_addr *mac_addr,
 294                           uint32_t index,
 295                           uint32_t pool);
 296 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 297 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 298                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 299                                     uint16_t reta_size);
 300 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 301                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 302                                    uint16_t reta_size);
 303
 304 static int i40e_get_cap(struct i40e_hw *hw);
 305 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 306 static int i40e_pf_setup(struct i40e_pf *pf);
 307 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 308 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 309 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 310 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 311 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 312                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 313 static void i40e_stat_update_48(struct i40e_hw *hw,
 314                                uint32_t hireg,
 315                                uint32_t loreg,
 316                                bool offset_loaded,
 317                                uint64_t *offset,
 318                                uint64_t *stat);
 319 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 320 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 321                                        void *param);
 322 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 323                                 uint32_t base, uint32_t num);
 324 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 325 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 326                         uint32_t base);
 327 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 328                         uint16_t num);
 329 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 330 static int i40e_veb_release(struct i40e_veb *veb);
 331 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 332                                                 struct i40e_vsi *vsi);
 333 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 334 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 335 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 336                                              struct i40e_macvlan_filter *mv_f,
 337                                              int num,
 338                                              struct ether_addr *addr);
 339 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 340                                              struct i40e_macvlan_filter *mv_f,
 341                                              int num,
 342                                              uint16_t vlan);
 343 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 344 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 345                                     struct rte_eth_rss_conf *rss_conf);
 346 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 347                                       struct rte_eth_rss_conf *rss_conf);
 348 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 349                                         struct rte_eth_udp_tunnel *udp_tunnel);
 350 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 351                                         struct rte_eth_udp_tunnel *udp_tunnel);
 352 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 353 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 354                                 enum rte_filter_op filter_op,
 355                                 void *arg);
 356 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 357                                 enum rte_filter_type filter_type,
 358                                 enum rte_filter_op filter_op,
 359                                 void *arg);
 360 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 361                                   struct rte_eth_dcb_info *dcb_info);
 362 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 363 static void i40e_configure_registers(struct i40e_hw *hw);
 364 static void i40e_hw_init(struct rte_eth_dev *dev);
 365 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 366 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 367                         struct rte_eth_mirror_conf *mirror_conf,
 368                         uint8_t sw_id, uint8_t on);
 369 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 370
 371 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 372 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 373 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 374                                            struct timespec *timestamp,
 375                                            uint32_t flags);
 376 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 377                                            struct timespec *timestamp);
 378 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 379
 380 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 381
 382 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 383                                    struct timespec *timestamp);
 384 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 385                                     const struct timespec *timestamp);
 386
 387 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 388                                          uint16_t queue_id);
 389 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 390                                           uint16_t queue_id);
 391
 392 static int i40e_get_regs(struct rte_eth_dev *dev,
 393                          struct rte_dev_reg_info *regs);
 394
 395 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 396
 397 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 398                            struct rte_dev_eeprom_info *eeprom);
 399
 400 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 401                                       struct ether_addr *mac_addr);
 402
 403 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 404
 405 static int i40e_ethertype_filter_convert(
 406         const struct rte_eth_ethertype_filter *input,
 407         struct i40e_ethertype_filter *filter);
 408 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 409                                    struct i40e_ethertype_filter *filter);
 410
 411 static int i40e_tunnel_filter_convert(
 412         struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter,
 413         struct i40e_tunnel_filter *tunnel_filter);
 414 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 415                                 struct i40e_tunnel_filter *tunnel_filter);
 416
 417 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 418 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 419 static void i40e_filter_restore(struct i40e_pf *pf);
 420
 421 static const struct rte_pci_id pci_id_i40e_map[] = {
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 442         { .vendor_id = 0, /* sentinel */ },
 443 };
 444
 445 static const struct eth_dev_ops i40e_eth_dev_ops = {
 446         .dev_configure                = i40e_dev_configure,
 447         .dev_start                    = i40e_dev_start,
 448         .dev_stop                     = i40e_dev_stop,
 449         .dev_close                    = i40e_dev_close,
 450         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 451         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 452         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 453         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 454         .dev_set_link_up              = i40e_dev_set_link_up,
 455         .dev_set_link_down            = i40e_dev_set_link_down,
 456         .link_update                  = i40e_dev_link_update,
 457         .stats_get                    = i40e_dev_stats_get,
 458         .xstats_get                   = i40e_dev_xstats_get,
 459         .xstats_get_names             = i40e_dev_xstats_get_names,
 460         .stats_reset                  = i40e_dev_stats_reset,
 461         .xstats_reset                 = i40e_dev_stats_reset,
 462         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 463         .fw_version_get               = i40e_fw_version_get,
 464         .dev_infos_get                = i40e_dev_info_get,
 465         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 466         .vlan_filter_set              = i40e_vlan_filter_set,
 467         .vlan_tpid_set                = i40e_vlan_tpid_set,
 468         .vlan_offload_set             = i40e_vlan_offload_set,
 469         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 470         .vlan_pvid_set                = i40e_vlan_pvid_set,
 471         .rx_queue_start               = i40e_dev_rx_queue_start,
 472         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 473         .tx_queue_start               = i40e_dev_tx_queue_start,
 474         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 475         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 476         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 477         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 478         .rx_queue_release             = i40e_dev_rx_queue_release,
 479         .rx_queue_count               = i40e_dev_rx_queue_count,
 480         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 481         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 482         .tx_queue_release             = i40e_dev_tx_queue_release,
 483         .dev_led_on                   = i40e_dev_led_on,
 484         .dev_led_off                  = i40e_dev_led_off,
 485         .flow_ctrl_get                = i40e_flow_ctrl_get,
 486         .flow_ctrl_set                = i40e_flow_ctrl_set,
 487         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 488         .mac_addr_add                 = i40e_macaddr_add,
 489         .mac_addr_remove              = i40e_macaddr_remove,
 490         .reta_update                  = i40e_dev_rss_reta_update,
 491         .reta_query                   = i40e_dev_rss_reta_query,
 492         .rss_hash_update              = i40e_dev_rss_hash_update,
 493         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 494         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 495         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 496         .filter_ctrl                  = i40e_dev_filter_ctrl,
 497         .rxq_info_get                 = i40e_rxq_info_get,
 498         .txq_info_get                 = i40e_txq_info_get,
 499         .mirror_rule_set              = i40e_mirror_rule_set,
 500         .mirror_rule_reset            = i40e_mirror_rule_reset,
 501         .timesync_enable              = i40e_timesync_enable,
 502         .timesync_disable             = i40e_timesync_disable,
 503         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 504         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 505         .get_dcb_info                 = i40e_dev_get_dcb_info,
 506         .timesync_adjust_time         = i40e_timesync_adjust_time,
 507         .timesync_read_time           = i40e_timesync_read_time,
 508         .timesync_write_time          = i40e_timesync_write_time,
 509         .get_reg                      = i40e_get_regs,
 510         .get_eeprom_length            = i40e_get_eeprom_length,
 511         .get_eeprom                   = i40e_get_eeprom,
 512         .mac_addr_set                 = i40e_set_default_mac_addr,
 513         .mtu_set                      = i40e_dev_mtu_set,
 514 };
 515
 516 /* store statistics names and its offset in stats structure */
 517 struct rte_i40e_xstats_name_off {
 518         char name[RTE_ETH_XSTATS_NAME_SIZE];
 519         unsigned offset;
 520 };
 521
 522 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 523         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 524         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 525         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 526         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 527         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 528                 rx_unknown_protocol)},
 529         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 530         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 531         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 532         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 533 };
 534
 535 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 536                 sizeof(rte_i40e_stats_strings[0]))
 537
 538 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 539         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 540                 tx_dropped_link_down)},
 541         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 542         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 543                 illegal_bytes)},
 544         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 545         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 546                 mac_local_faults)},
 547         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 548                 mac_remote_faults)},
 549         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 550                 rx_length_errors)},
 551         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 552         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 553         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 554         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 555         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 556         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 557                 rx_size_127)},
 558         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 559                 rx_size_255)},
 560         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 561                 rx_size_511)},
 562         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 563                 rx_size_1023)},
 564         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 565                 rx_size_1522)},
 566         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 567                 rx_size_big)},
 568         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 569                 rx_undersize)},
 570         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 571                 rx_oversize)},
 572         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 573                 mac_short_packet_dropped)},
 574         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 575                 rx_fragments)},
 576         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 577         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 578         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 579                 tx_size_127)},
 580         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 581                 tx_size_255)},
 582         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 583                 tx_size_511)},
 584         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 585                 tx_size_1023)},
 586         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 587                 tx_size_1522)},
 588         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 589                 tx_size_big)},
 590         {"rx_flow_director_atr_match_packets",
 591                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 592         {"rx_flow_director_sb_match_packets",
 593                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 594         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 595                 tx_lpi_status)},
 596         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 597                 rx_lpi_status)},
 598         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 599                 tx_lpi_count)},
 600         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 601                 rx_lpi_count)},
 602 };
 603
 604 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 605                 sizeof(rte_i40e_hw_port_strings[0]))
 606
 607 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 608         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 609                 priority_xon_rx)},
 610         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 611                 priority_xoff_rx)},
 612 };
 613
 614 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 615                 sizeof(rte_i40e_rxq_prio_strings[0]))
 616
 617 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 618         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 619                 priority_xon_tx)},
 620         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 621                 priority_xoff_tx)},
 622         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 623                 priority_xon_2_xoff)},
 624 };
 625
 626 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 627                 sizeof(rte_i40e_txq_prio_strings[0]))
 628
 629 static struct eth_driver rte_i40e_pmd = {
 630         .pci_drv = {
 631                 .id_table = pci_id_i40e_map,
 632                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 633                 .probe = rte_eth_dev_pci_probe,
 634                 .remove = rte_eth_dev_pci_remove,
 635         },
 636         .eth_dev_init = eth_i40e_dev_init,
 637         .eth_dev_uninit = eth_i40e_dev_uninit,
 638         .dev_private_size = sizeof(struct i40e_adapter),
 639 };
 640
 641 static inline int
 642 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 643                                      struct rte_eth_link *link)
 644 {
 645         struct rte_eth_link *dst = link;
 646         struct rte_eth_link *src = &(dev->data->dev_link);
 647
 648         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 649                                         *(uint64_t *)src) == 0)
 650                 return -1;
 651
 652         return 0;
 653 }
 654
 655 static inline int
 656 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 657                                       struct rte_eth_link *link)
 658 {
 659         struct rte_eth_link *dst = &(dev->data->dev_link);
 660         struct rte_eth_link *src = link;
 661
 662         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 663                                         *(uint64_t *)src) == 0)
 664                 return -1;
 665
 666         return 0;
 667 }
 668
 669 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 670 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 671 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 672
 673 #ifndef I40E_GLQF_ORT
 674 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 675 #endif
 676 #ifndef I40E_GLQF_PIT
 677 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 678 #endif
 679
 680 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 681 {
 682         /*
 683          * Initialize registers for flexible payload, which should be set by NVM.
 684          * This should be removed from code once it is fixed in NVM.
 685          */
 686         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 687         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 688         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 689         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 690         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 691         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 692         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 693         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 694         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 695         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 696         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 697         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 698
 699         /* Initialize registers for parsing packet type of QinQ */
 700         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 701         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 702 }
 703
 704 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 705
 706 /*
 707  * Add a ethertype filter to drop all flow control frames transmitted
 708  * from VSIs.
 709 */
 710 static void
 711 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 712 {
 713         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 714         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 715                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 716                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 717         int ret;
 718
 719         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 720                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 721                                 pf->main_vsi_seid, 0,
 722                                 TRUE, NULL, NULL);
 723         if (ret)
 724                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 725                                   " frames from VSIs.");
 726 }
 727
 728 static int
 729 floating_veb_list_handler(__rte_unused const char *key,
 730                           const char *floating_veb_value,
 731                           void *opaque)
 732 {
 733         int idx = 0;
 734         unsigned int count = 0;
 735         char *end = NULL;
 736         int min, max;
 737         bool *vf_floating_veb = opaque;
 738
 739         while (isblank(*floating_veb_value))
 740                 floating_veb_value++;
 741
 742         /* Reset floating VEB configuration for VFs */
 743         for (idx = 0; idx < I40E_MAX_VF; idx++)
 744                 vf_floating_veb[idx] = false;
 745
 746         min = I40E_MAX_VF;
 747         do {
 748                 while (isblank(*floating_veb_value))
 749                         floating_veb_value++;
 750                 if (*floating_veb_value == '\0')
 751                         return -1;
 752                 errno = 0;
 753                 idx = strtoul(floating_veb_value, &end, 10);
 754                 if (errno || end == NULL)
 755                         return -1;
 756                 while (isblank(*end))
 757                         end++;
 758                 if (*end == '-') {
 759                         min = idx;
 760                 } else if ((*end == ';') || (*end == '\0')) {
 761                         max = idx;
 762                         if (min == I40E_MAX_VF)
 763                                 min = idx;
 764                         if (max >= I40E_MAX_VF)
 765                                 max = I40E_MAX_VF - 1;
 766                         for (idx = min; idx <= max; idx++) {
 767                                 vf_floating_veb[idx] = true;
 768                                 count++;
 769                         }
 770                         min = I40E_MAX_VF;
 771                 } else {
 772                         return -1;
 773                 }
 774                 floating_veb_value = end + 1;
 775         } while (*end != '\0');
 776
 777         if (count == 0)
 778                 return -1;
 779
 780         return 0;
 781 }
 782
 783 static void
 784 config_vf_floating_veb(struct rte_devargs *devargs,
 785                        uint16_t floating_veb,
 786                        bool *vf_floating_veb)
 787 {
 788         struct rte_kvargs *kvlist;
 789         int i;
 790         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 791
 792         if (!floating_veb)
 793                 return;
 794         /* All the VFs attach to the floating VEB by default
 795          * when the floating VEB is enabled.
 796          */
 797         for (i = 0; i < I40E_MAX_VF; i++)
 798                 vf_floating_veb[i] = true;
 799
 800         if (devargs == NULL)
 801                 return;
 802
 803         kvlist = rte_kvargs_parse(devargs->args, NULL);
 804         if (kvlist == NULL)
 805                 return;
 806
 807         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 808                 rte_kvargs_free(kvlist);
 809                 return;
 810         }
 811         /* When the floating_veb_list parameter exists, all the VFs
 812          * will attach to the legacy VEB firstly, then configure VFs
 813          * to the floating VEB according to the floating_veb_list.
 814          */
 815         if (rte_kvargs_process(kvlist, floating_veb_list,
 816                                floating_veb_list_handler,
 817                                vf_floating_veb) < 0) {
 818                 rte_kvargs_free(kvlist);
 819                 return;
 820         }
 821         rte_kvargs_free(kvlist);
 822 }
 823
 824 static int
 825 i40e_check_floating_handler(__rte_unused const char *key,
 826                             const char *value,
 827                             __rte_unused void *opaque)
 828 {
 829         if (strcmp(value, "1"))
 830                 return -1;
 831
 832         return 0;
 833 }
 834
 835 static int
 836 is_floating_veb_supported(struct rte_devargs *devargs)
 837 {
 838         struct rte_kvargs *kvlist;
 839         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 840
 841         if (devargs == NULL)
 842                 return 0;
 843
 844         kvlist = rte_kvargs_parse(devargs->args, NULL);
 845         if (kvlist == NULL)
 846                 return 0;
 847
 848         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 849                 rte_kvargs_free(kvlist);
 850                 return 0;
 851         }
 852         /* Floating VEB is enabled when there's key-value:
 853          * enable_floating_veb=1
 854          */
 855         if (rte_kvargs_process(kvlist, floating_veb_key,
 856                                i40e_check_floating_handler, NULL) < 0) {
 857                 rte_kvargs_free(kvlist);
 858                 return 0;
 859         }
 860         rte_kvargs_free(kvlist);
 861
 862         return 1;
 863 }
 864
 865 static void
 866 config_floating_veb(struct rte_eth_dev *dev)
 867 {
 868         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 869         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 870         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 871
 872         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 873
 874         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 875                 pf->floating_veb =
 876                         is_floating_veb_supported(pci_dev->device.devargs);
 877                 config_vf_floating_veb(pci_dev->device.devargs,
 878                                        pf->floating_veb,
 879                                        pf->floating_veb_list);
 880         } else {
 881                 pf->floating_veb = false;
 882         }
 883 }
 884
 885 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 886 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 887
 888 static int
 889 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 890 {
 891         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 892         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 893         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 894         int ret;
 895
 896         struct rte_hash_parameters ethertype_hash_params = {
 897                 .name = ethertype_hash_name,
 898                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 899                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 900                 .hash_func = rte_hash_crc,
 901         };
 902
 903         /* Initialize ethertype filter rule list and hash */
 904         TAILQ_INIT(&ethertype_rule->ethertype_list);
 905         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 906                  "ethertype_%s", dev->data->name);
 907         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 908         if (!ethertype_rule->hash_table) {
 909                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 910                 return -EINVAL;
 911         }
 912         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 913                                        sizeof(struct i40e_ethertype_filter *) *
 914                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 915                                        0);
 916         if (!ethertype_rule->hash_map) {
 917                 PMD_INIT_LOG(ERR,
 918                              "Failed to allocate memory for ethertype hash map!");
 919                 ret = -ENOMEM;
 920                 goto err_ethertype_hash_map_alloc;
 921         }
 922
 923         return 0;
 924
 925 err_ethertype_hash_map_alloc:
 926         rte_hash_free(ethertype_rule->hash_table);
 927
 928         return ret;
 929 }
 930
 931 static int
 932 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 933 {
 934         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 935         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 936         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 937         int ret;
 938
 939         struct rte_hash_parameters tunnel_hash_params = {
 940                 .name = tunnel_hash_name,
 941                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 942                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 943                 .hash_func = rte_hash_crc,
 944         };
 945
 946         /* Initialize tunnel filter rule list and hash */
 947         TAILQ_INIT(&tunnel_rule->tunnel_list);
 948         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 949                  "tunnel_%s", dev->data->name);
 950         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 951         if (!tunnel_rule->hash_table) {
 952                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 953                 return -EINVAL;
 954         }
 955         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 956                                     sizeof(struct i40e_tunnel_filter *) *
 957                                     I40E_MAX_TUNNEL_FILTER_NUM,
 958                                     0);
 959         if (!tunnel_rule->hash_map) {
 960                 PMD_INIT_LOG(ERR,
 961                              "Failed to allocate memory for tunnel hash map!");
 962                 ret = -ENOMEM;
 963                 goto err_tunnel_hash_map_alloc;
 964         }
 965
 966         return 0;
 967
 968 err_tunnel_hash_map_alloc:
 969         rte_hash_free(tunnel_rule->hash_table);
 970
 971         return ret;
 972 }
 973
 974 static int
 975 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 976 {
 977         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 978         struct i40e_fdir_info *fdir_info = &pf->fdir;
 979         char fdir_hash_name[RTE_HASH_NAMESIZE];
 980         int ret;
 981
 982         struct rte_hash_parameters fdir_hash_params = {
 983                 .name = fdir_hash_name,
 984                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 985                 .key_len = sizeof(struct rte_eth_fdir_input),
 986                 .hash_func = rte_hash_crc,
 987         };
 988
 989         /* Initialize flow director filter rule list and hash */
 990         TAILQ_INIT(&fdir_info->fdir_list);
 991         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 992                  "fdir_%s", dev->data->name);
 993         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
 994         if (!fdir_info->hash_table) {
 995                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 996                 return -EINVAL;
 997         }
 998         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
 999                                           sizeof(struct i40e_fdir_filter *) *
1000                                           I40E_MAX_FDIR_FILTER_NUM,
1001                                           0);
1002         if (!fdir_info->hash_map) {
1003                 PMD_INIT_LOG(ERR,
1004                              "Failed to allocate memory for fdir hash map!");
1005                 ret = -ENOMEM;
1006                 goto err_fdir_hash_map_alloc;
1007         }
1008         return 0;
1009
1010 err_fdir_hash_map_alloc:
1011         rte_hash_free(fdir_info->hash_table);
1012
1013         return ret;
1014 }
1015
1016 static int
1017 eth_i40e_dev_init(struct rte_eth_dev *dev)
1018 {
1019         struct rte_pci_device *pci_dev;
1020         struct rte_intr_handle *intr_handle;
1021         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1022         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1023         struct i40e_vsi *vsi;
1024         int ret;
1025         uint32_t len;
1026         uint8_t aq_fail = 0;
1027
1028         PMD_INIT_FUNC_TRACE();
1029
1030         dev->dev_ops = &i40e_eth_dev_ops;
1031         dev->rx_pkt_burst = i40e_recv_pkts;
1032         dev->tx_pkt_burst = i40e_xmit_pkts;
1033         dev->tx_pkt_prepare = i40e_prep_pkts;
1034
1035         /* for secondary processes, we don't initialise any further as primary
1036          * has already done this work. Only check we don't need a different
1037          * RX function */
1038         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1039                 i40e_set_rx_function(dev);
1040                 i40e_set_tx_function(dev);
1041                 return 0;
1042         }
1043         pci_dev = I40E_DEV_TO_PCI(dev);
1044         intr_handle = &pci_dev->intr_handle;
1045
1046         rte_eth_copy_pci_info(dev, pci_dev);
1047         dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1048
1049         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1050         pf->adapter->eth_dev = dev;
1051         pf->dev_data = dev->data;
1052
1053         hw->back = I40E_PF_TO_ADAPTER(pf);
1054         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1055         if (!hw->hw_addr) {
1056                 PMD_INIT_LOG(ERR, "Hardware is not available, "
1057                              "as address is NULL");
1058                 return -ENODEV;
1059         }
1060
1061         hw->vendor_id = pci_dev->id.vendor_id;
1062         hw->device_id = pci_dev->id.device_id;
1063         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1064         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1065         hw->bus.device = pci_dev->addr.devid;
1066         hw->bus.func = pci_dev->addr.function;
1067         hw->adapter_stopped = 0;
1068
1069         /* Make sure all is clean before doing PF reset */
1070         i40e_clear_hw(hw);
1071
1072         /* Initialize the hardware */
1073         i40e_hw_init(dev);
1074
1075         /* Reset here to make sure all is clean for each PF */
1076         ret = i40e_pf_reset(hw);
1077         if (ret) {
1078                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1079                 return ret;
1080         }
1081
1082         /* Initialize the shared code (base driver) */
1083         ret = i40e_init_shared_code(hw);
1084         if (ret) {
1085                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1086                 return ret;
1087         }
1088
1089         /*
1090          * To work around the NVM issue, initialize registers
1091          * for flexible payload and packet type of QinQ by
1092          * software. It should be removed once issues are fixed
1093          * in NVM.
1094          */
1095         i40e_GLQF_reg_init(hw);
1096
1097         /* Initialize the input set for filters (hash and fd) to default value */
1098         i40e_filter_input_set_init(pf);
1099
1100         /* Initialize the parameters for adminq */
1101         i40e_init_adminq_parameter(hw);
1102         ret = i40e_init_adminq(hw);
1103         if (ret != I40E_SUCCESS) {
1104                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1105                 return -EIO;
1106         }
1107         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1108                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1109                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1110                      ((hw->nvm.version >> 12) & 0xf),
1111                      ((hw->nvm.version >> 4) & 0xff),
1112                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1113
1114         /* Need the special FW version to support floating VEB */
1115         config_floating_veb(dev);
1116         /* Clear PXE mode */
1117         i40e_clear_pxe_mode(hw);
1118         ret = i40e_dev_sync_phy_type(hw);
1119         if (ret) {
1120                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1121                 goto err_sync_phy_type;
1122         }
1123         /*
1124          * On X710, performance number is far from the expectation on recent
1125          * firmware versions. The fix for this issue may not be integrated in
1126          * the following firmware version. So the workaround in software driver
1127          * is needed. It needs to modify the initial values of 3 internal only
1128          * registers. Note that the workaround can be removed when it is fixed
1129          * in firmware in the future.
1130          */
1131         i40e_configure_registers(hw);
1132
1133         /* Get hw capabilities */
1134         ret = i40e_get_cap(hw);
1135         if (ret != I40E_SUCCESS) {
1136                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1137                 goto err_get_capabilities;
1138         }
1139
1140         /* Initialize parameters for PF */
1141         ret = i40e_pf_parameter_init(dev);
1142         if (ret != 0) {
1143                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1144                 goto err_parameter_init;
1145         }
1146
1147         /* Initialize the queue management */
1148         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1149         if (ret < 0) {
1150                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1151                 goto err_qp_pool_init;
1152         }
1153         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1154                                 hw->func_caps.num_msix_vectors - 1);
1155         if (ret < 0) {
1156                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1157                 goto err_msix_pool_init;
1158         }
1159
1160         /* Initialize lan hmc */
1161         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1162                                 hw->func_caps.num_rx_qp, 0, 0);
1163         if (ret != I40E_SUCCESS) {
1164                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1165                 goto err_init_lan_hmc;
1166         }
1167
1168         /* Configure lan hmc */
1169         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1170         if (ret != I40E_SUCCESS) {
1171                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1172                 goto err_configure_lan_hmc;
1173         }
1174
1175         /* Get and check the mac address */
1176         i40e_get_mac_addr(hw, hw->mac.addr);
1177         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1178                 PMD_INIT_LOG(ERR, "mac address is not valid");
1179                 ret = -EIO;
1180                 goto err_get_mac_addr;
1181         }
1182         /* Copy the permanent MAC address */
1183         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1184                         (struct ether_addr *) hw->mac.perm_addr);
1185
1186         /* Disable flow control */
1187         hw->fc.requested_mode = I40E_FC_NONE;
1188         i40e_set_fc(hw, &aq_fail, TRUE);
1189
1190         /* Set the global registers with default ether type value */
1191         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1192         if (ret != I40E_SUCCESS) {
1193                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1194                              "VLAN ether type");
1195                 goto err_setup_pf_switch;
1196         }
1197
1198         /* PF setup, which includes VSI setup */
1199         ret = i40e_pf_setup(pf);
1200         if (ret) {
1201                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1202                 goto err_setup_pf_switch;
1203         }
1204
1205         /* reset all stats of the device, including pf and main vsi */
1206         i40e_dev_stats_reset(dev);
1207
1208         vsi = pf->main_vsi;
1209
1210         /* Disable double vlan by default */
1211         i40e_vsi_config_double_vlan(vsi, FALSE);
1212
1213         /* Disable S-TAG identification when floating_veb is disabled */
1214         if (!pf->floating_veb) {
1215                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1216                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1217                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1218                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1219                 }
1220         }
1221
1222         if (!vsi->max_macaddrs)
1223                 len = ETHER_ADDR_LEN;
1224         else
1225                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1226
1227         /* Should be after VSI initialized */
1228         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1229         if (!dev->data->mac_addrs) {
1230                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1231                                         "for storing mac address");
1232                 goto err_mac_alloc;
1233         }
1234         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1235                                         &dev->data->mac_addrs[0]);
1236
1237         /* initialize pf host driver to setup SRIOV resource if applicable */
1238         i40e_pf_host_init(dev);
1239
1240         /* register callback func to eal lib */
1241         rte_intr_callback_register(intr_handle,
1242                                    i40e_dev_interrupt_handler, dev);
1243
1244         /* configure and enable device interrupt */
1245         i40e_pf_config_irq0(hw, TRUE);
1246         i40e_pf_enable_irq0(hw);
1247
1248         /* enable uio intr after callback register */
1249         rte_intr_enable(intr_handle);
1250         /*
1251          * Add an ethertype filter to drop all flow control frames transmitted
1252          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1253          * frames to wire.
1254          */
1255         i40e_add_tx_flow_control_drop_filter(pf);
1256
1257         /* Set the max frame size to 0x2600 by default,
1258          * in case other drivers changed the default value.
1259          */
1260         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1261
1262         /* initialize mirror rule list */
1263         TAILQ_INIT(&pf->mirror_list);
1264
1265         /* Init dcb to sw mode by default */
1266         ret = i40e_dcb_init_configure(dev, TRUE);
1267         if (ret != I40E_SUCCESS) {
1268                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1269                 pf->flags &= ~I40E_FLAG_DCB;
1270         }
1271
1272         ret = i40e_init_ethtype_filter_list(dev);
1273         if (ret < 0)
1274                 goto err_init_ethtype_filter_list;
1275         ret = i40e_init_tunnel_filter_list(dev);
1276         if (ret < 0)
1277                 goto err_init_tunnel_filter_list;
1278         ret = i40e_init_fdir_filter_list(dev);
1279         if (ret < 0)
1280                 goto err_init_fdir_filter_list;
1281
1282         return 0;
1283
1284 err_init_fdir_filter_list:
1285         rte_free(pf->tunnel.hash_table);
1286         rte_free(pf->tunnel.hash_map);
1287 err_init_tunnel_filter_list:
1288         rte_free(pf->ethertype.hash_table);
1289         rte_free(pf->ethertype.hash_map);
1290 err_init_ethtype_filter_list:
1291         rte_free(dev->data->mac_addrs);
1292 err_mac_alloc:
1293         i40e_vsi_release(pf->main_vsi);
1294 err_setup_pf_switch:
1295 err_get_mac_addr:
1296 err_configure_lan_hmc:
1297         (void)i40e_shutdown_lan_hmc(hw);
1298 err_init_lan_hmc:
1299         i40e_res_pool_destroy(&pf->msix_pool);
1300 err_msix_pool_init:
1301         i40e_res_pool_destroy(&pf->qp_pool);
1302 err_qp_pool_init:
1303 err_parameter_init:
1304 err_get_capabilities:
1305 err_sync_phy_type:
1306         (void)i40e_shutdown_adminq(hw);
1307
1308         return ret;
1309 }
1310
1311 static void
1312 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1313 {
1314         struct i40e_ethertype_filter *p_ethertype;
1315         struct i40e_ethertype_rule *ethertype_rule;
1316
1317         ethertype_rule = &pf->ethertype;
1318         /* Remove all ethertype filter rules and hash */
1319         if (ethertype_rule->hash_map)
1320                 rte_free(ethertype_rule->hash_map);
1321         if (ethertype_rule->hash_table)
1322                 rte_hash_free(ethertype_rule->hash_table);
1323
1324         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1325                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1326                              p_ethertype, rules);
1327                 rte_free(p_ethertype);
1328         }
1329 }
1330
1331 static void
1332 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1333 {
1334         struct i40e_tunnel_filter *p_tunnel;
1335         struct i40e_tunnel_rule *tunnel_rule;
1336
1337         tunnel_rule = &pf->tunnel;
1338         /* Remove all tunnel director rules and hash */
1339         if (tunnel_rule->hash_map)
1340                 rte_free(tunnel_rule->hash_map);
1341         if (tunnel_rule->hash_table)
1342                 rte_hash_free(tunnel_rule->hash_table);
1343
1344         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1345                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1346                 rte_free(p_tunnel);
1347         }
1348 }
1349
1350 static void
1351 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1352 {
1353         struct i40e_fdir_filter *p_fdir;
1354         struct i40e_fdir_info *fdir_info;
1355
1356         fdir_info = &pf->fdir;
1357         /* Remove all flow director rules and hash */
1358         if (fdir_info->hash_map)
1359                 rte_free(fdir_info->hash_map);
1360         if (fdir_info->hash_table)
1361                 rte_hash_free(fdir_info->hash_table);
1362
1363         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1364                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1365                 rte_free(p_fdir);
1366         }
1367 }
1368
1369 static int
1370 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1371 {
1372         struct i40e_pf *pf;
1373         struct rte_pci_device *pci_dev;
1374         struct rte_intr_handle *intr_handle;
1375         struct i40e_hw *hw;
1376         struct i40e_filter_control_settings settings;
1377         struct rte_flow *p_flow;
1378         int ret;
1379         uint8_t aq_fail = 0;
1380
1381         PMD_INIT_FUNC_TRACE();
1382
1383         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1384                 return 0;
1385
1386         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1387         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1388         pci_dev = I40E_DEV_TO_PCI(dev);
1389         intr_handle = &pci_dev->intr_handle;
1390
1391         if (hw->adapter_stopped == 0)
1392                 i40e_dev_close(dev);
1393
1394         dev->dev_ops = NULL;
1395         dev->rx_pkt_burst = NULL;
1396         dev->tx_pkt_burst = NULL;
1397
1398         /* Clear PXE mode */
1399         i40e_clear_pxe_mode(hw);
1400
1401         /* Unconfigure filter control */
1402         memset(&settings, 0, sizeof(settings));
1403         ret = i40e_set_filter_control(hw, &settings);
1404         if (ret)
1405                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1406                                         ret);
1407
1408         /* Disable flow control */
1409         hw->fc.requested_mode = I40E_FC_NONE;
1410         i40e_set_fc(hw, &aq_fail, TRUE);
1411
1412         /* uninitialize pf host driver */
1413         i40e_pf_host_uninit(dev);
1414
1415         rte_free(dev->data->mac_addrs);
1416         dev->data->mac_addrs = NULL;
1417
1418         /* disable uio intr before callback unregister */
1419         rte_intr_disable(intr_handle);
1420
1421         /* register callback func to eal lib */
1422         rte_intr_callback_unregister(intr_handle,
1423                                      i40e_dev_interrupt_handler, dev);
1424
1425         i40e_rm_ethtype_filter_list(pf);
1426         i40e_rm_tunnel_filter_list(pf);
1427         i40e_rm_fdir_filter_list(pf);
1428
1429         /* Remove all flows */
1430         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1431                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1432                 rte_free(p_flow);
1433         }
1434
1435         return 0;
1436 }
1437
1438 static int
1439 i40e_dev_configure(struct rte_eth_dev *dev)
1440 {
1441         struct i40e_adapter *ad =
1442                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1443         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1444         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1445         int i, ret;
1446
1447         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1448          * bulk allocation or vector Rx preconditions we will reset it.
1449          */
1450         ad->rx_bulk_alloc_allowed = true;
1451         ad->rx_vec_allowed = true;
1452         ad->tx_simple_allowed = true;
1453         ad->tx_vec_allowed = true;
1454
1455         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1456                 ret = i40e_fdir_setup(pf);
1457                 if (ret != I40E_SUCCESS) {
1458                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1459                         return -ENOTSUP;
1460                 }
1461                 ret = i40e_fdir_configure(dev);
1462                 if (ret < 0) {
1463                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1464                         goto err;
1465                 }
1466         } else
1467                 i40e_fdir_teardown(pf);
1468
1469         ret = i40e_dev_init_vlan(dev);
1470         if (ret < 0)
1471                 goto err;
1472
1473         /* VMDQ setup.
1474          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1475          *  RSS setting have different requirements.
1476          *  General PMD driver call sequence are NIC init, configure,
1477          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1478          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1479          *  applicable. So, VMDQ setting has to be done before
1480          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1481          *  For RSS setting, it will try to calculate actual configured RX queue
1482          *  number, which will be available after rx_queue_setup(). dev_start()
1483          *  function is good to place RSS setup.
1484          */
1485         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1486                 ret = i40e_vmdq_setup(dev);
1487                 if (ret)
1488                         goto err;
1489         }
1490
1491         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1492                 ret = i40e_dcb_setup(dev);
1493                 if (ret) {
1494                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1495                         goto err_dcb;
1496                 }
1497         }
1498
1499         TAILQ_INIT(&pf->flow_list);
1500
1501         return 0;
1502
1503 err_dcb:
1504         /* need to release vmdq resource if exists */
1505         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1506                 i40e_vsi_release(pf->vmdq[i].vsi);
1507                 pf->vmdq[i].vsi = NULL;
1508         }
1509         rte_free(pf->vmdq);
1510         pf->vmdq = NULL;
1511 err:
1512         /* need to release fdir resource if exists */
1513         i40e_fdir_teardown(pf);
1514         return ret;
1515 }
1516
1517 void
1518 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1519 {
1520         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1521         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1522         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1523         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1524         uint16_t msix_vect = vsi->msix_intr;
1525         uint16_t i;
1526
1527         for (i = 0; i < vsi->nb_qps; i++) {
1528                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1529                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1530                 rte_wmb();
1531         }
1532
1533         if (vsi->type != I40E_VSI_SRIOV) {
1534                 if (!rte_intr_allow_others(intr_handle)) {
1535                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1536                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1537                         I40E_WRITE_REG(hw,
1538                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1539                                        0);
1540                 } else {
1541                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1542                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1543                         I40E_WRITE_REG(hw,
1544                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1545                                                        msix_vect - 1), 0);
1546                 }
1547         } else {
1548                 uint32_t reg;
1549                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1550                         vsi->user_param + (msix_vect - 1);
1551
1552                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1553                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1554         }
1555         I40E_WRITE_FLUSH(hw);
1556 }
1557
1558 static void
1559 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1560                        int base_queue, int nb_queue)
1561 {
1562         int i;
1563         uint32_t val;
1564         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1565
1566         /* Bind all RX queues to allocated MSIX interrupt */
1567         for (i = 0; i < nb_queue; i++) {
1568                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1569                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1570                         ((base_queue + i + 1) <<
1571                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1572                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1573                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1574
1575                 if (i == nb_queue - 1)
1576                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1577                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1578         }
1579
1580         /* Write first RX queue to Link list register as the head element */
1581         if (vsi->type != I40E_VSI_SRIOV) {
1582                 uint16_t interval =
1583                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1584
1585                 if (msix_vect == I40E_MISC_VEC_ID) {
1586                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1587                                        (base_queue <<
1588                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1589                                        (0x0 <<
1590                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1591                         I40E_WRITE_REG(hw,
1592                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1593                                        interval);
1594                 } else {
1595                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1596                                        (base_queue <<
1597                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1598                                        (0x0 <<
1599                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1600                         I40E_WRITE_REG(hw,
1601                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1602                                                        msix_vect - 1),
1603                                        interval);
1604                 }
1605         } else {
1606                 uint32_t reg;
1607
1608                 if (msix_vect == I40E_MISC_VEC_ID) {
1609                         I40E_WRITE_REG(hw,
1610                                        I40E_VPINT_LNKLST0(vsi->user_param),
1611                                        (base_queue <<
1612                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1613                                        (0x0 <<
1614                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1615                 } else {
1616                         /* num_msix_vectors_vf needs to minus irq0 */
1617                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1618                                 vsi->user_param + (msix_vect - 1);
1619
1620                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1621                                        (base_queue <<
1622                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1623                                        (0x0 <<
1624                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1625                 }
1626         }
1627
1628         I40E_WRITE_FLUSH(hw);
1629 }
1630
1631 void
1632 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1633 {
1634         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1635         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1636         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1637         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1638         uint16_t msix_vect = vsi->msix_intr;
1639         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1640         uint16_t queue_idx = 0;
1641         int record = 0;
1642         uint32_t val;
1643         int i;
1644
1645         for (i = 0; i < vsi->nb_qps; i++) {
1646                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1647                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1648         }
1649
1650         /* INTENA flag is not auto-cleared for interrupt */
1651         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1652         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1653                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1654                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1655         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1656
1657         /* VF bind interrupt */
1658         if (vsi->type == I40E_VSI_SRIOV) {
1659                 __vsi_queues_bind_intr(vsi, msix_vect,
1660                                        vsi->base_queue, vsi->nb_qps);
1661                 return;
1662         }
1663
1664         /* PF & VMDq bind interrupt */
1665         if (rte_intr_dp_is_en(intr_handle)) {
1666                 if (vsi->type == I40E_VSI_MAIN) {
1667                         queue_idx = 0;
1668                         record = 1;
1669                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1670                         struct i40e_vsi *main_vsi =
1671                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1672                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1673                         record = 1;
1674                 }
1675         }
1676
1677         for (i = 0; i < vsi->nb_used_qps; i++) {
1678                 if (nb_msix <= 1) {
1679                         if (!rte_intr_allow_others(intr_handle))
1680                                 /* allow to share MISC_VEC_ID */
1681                                 msix_vect = I40E_MISC_VEC_ID;
1682
1683                         /* no enough msix_vect, map all to one */
1684                         __vsi_queues_bind_intr(vsi, msix_vect,
1685                                                vsi->base_queue + i,
1686                                                vsi->nb_used_qps - i);
1687                         for (; !!record && i < vsi->nb_used_qps; i++)
1688                                 intr_handle->intr_vec[queue_idx + i] =
1689                                         msix_vect;
1690                         break;
1691                 }
1692                 /* 1:1 queue/msix_vect mapping */
1693                 __vsi_queues_bind_intr(vsi, msix_vect,
1694                                        vsi->base_queue + i, 1);
1695                 if (!!record)
1696                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1697
1698                 msix_vect++;
1699                 nb_msix--;
1700         }
1701 }
1702
1703 static void
1704 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1705 {
1706         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1707         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1708         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1709         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1710         uint16_t interval = i40e_calc_itr_interval(\
1711                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1712         uint16_t msix_intr, i;
1713
1714         if (rte_intr_allow_others(intr_handle))
1715                 for (i = 0; i < vsi->nb_msix; i++) {
1716                         msix_intr = vsi->msix_intr + i;
1717                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1718                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1719                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1720                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1721                                 (interval <<
1722                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1723                 }
1724         else
1725                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1726                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1727                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1728                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1729                                (interval <<
1730                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1731
1732         I40E_WRITE_FLUSH(hw);
1733 }
1734
1735 static void
1736 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1737 {
1738         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1739         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1740         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1741         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1742         uint16_t msix_intr, i;
1743
1744         if (rte_intr_allow_others(intr_handle))
1745                 for (i = 0; i < vsi->nb_msix; i++) {
1746                         msix_intr = vsi->msix_intr + i;
1747                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1748                                        0);
1749                 }
1750         else
1751                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1752
1753         I40E_WRITE_FLUSH(hw);
1754 }
1755
1756 static inline uint8_t
1757 i40e_parse_link_speeds(uint16_t link_speeds)
1758 {
1759         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1760
1761         if (link_speeds & ETH_LINK_SPEED_40G)
1762                 link_speed |= I40E_LINK_SPEED_40GB;
1763         if (link_speeds & ETH_LINK_SPEED_25G)
1764                 link_speed |= I40E_LINK_SPEED_25GB;
1765         if (link_speeds & ETH_LINK_SPEED_20G)
1766                 link_speed |= I40E_LINK_SPEED_20GB;
1767         if (link_speeds & ETH_LINK_SPEED_10G)
1768                 link_speed |= I40E_LINK_SPEED_10GB;
1769         if (link_speeds & ETH_LINK_SPEED_1G)
1770                 link_speed |= I40E_LINK_SPEED_1GB;
1771         if (link_speeds & ETH_LINK_SPEED_100M)
1772                 link_speed |= I40E_LINK_SPEED_100MB;
1773
1774         return link_speed;
1775 }
1776
1777 static int
1778 i40e_phy_conf_link(struct i40e_hw *hw,
1779                    uint8_t abilities,
1780                    uint8_t force_speed)
1781 {
1782         enum i40e_status_code status;
1783         struct i40e_aq_get_phy_abilities_resp phy_ab;
1784         struct i40e_aq_set_phy_config phy_conf;
1785         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1786                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1787                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1788                         I40E_AQ_PHY_FLAG_LOW_POWER;
1789         const uint8_t advt = I40E_LINK_SPEED_40GB |
1790                         I40E_LINK_SPEED_25GB |
1791                         I40E_LINK_SPEED_10GB |
1792                         I40E_LINK_SPEED_1GB |
1793                         I40E_LINK_SPEED_100MB;
1794         int ret = -ENOTSUP;
1795
1796
1797         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1798                                               NULL);
1799         if (status)
1800                 return ret;
1801
1802         memset(&phy_conf, 0, sizeof(phy_conf));
1803
1804         /* bits 0-2 use the values from get_phy_abilities_resp */
1805         abilities &= ~mask;
1806         abilities |= phy_ab.abilities & mask;
1807
1808         /* update ablities and speed */
1809         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1810                 phy_conf.link_speed = advt;
1811         else
1812                 phy_conf.link_speed = force_speed;
1813
1814         phy_conf.abilities = abilities;
1815
1816         /* use get_phy_abilities_resp value for the rest */
1817         phy_conf.phy_type = phy_ab.phy_type;
1818         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1819         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1820         phy_conf.eee_capability = phy_ab.eee_capability;
1821         phy_conf.eeer = phy_ab.eeer_val;
1822         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1823
1824         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1825                     phy_ab.abilities, phy_ab.link_speed);
1826         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1827                     phy_conf.abilities, phy_conf.link_speed);
1828
1829         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1830         if (status)
1831                 return ret;
1832
1833         return I40E_SUCCESS;
1834 }
1835
1836 static int
1837 i40e_apply_link_speed(struct rte_eth_dev *dev)
1838 {
1839         uint8_t speed;
1840         uint8_t abilities = 0;
1841         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1842         struct rte_eth_conf *conf = &dev->data->dev_conf;
1843
1844         speed = i40e_parse_link_speeds(conf->link_speeds);
1845         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1846         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1847                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1848         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1849
1850         /* Skip changing speed on 40G interfaces, FW does not support */
1851         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1852                 speed =  I40E_LINK_SPEED_UNKNOWN;
1853                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1854         }
1855
1856         return i40e_phy_conf_link(hw, abilities, speed);
1857 }
1858
1859 static int
1860 i40e_dev_start(struct rte_eth_dev *dev)
1861 {
1862         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1863         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1864         struct i40e_vsi *main_vsi = pf->main_vsi;
1865         int ret, i;
1866         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1867         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1868         uint32_t intr_vector = 0;
1869
1870         hw->adapter_stopped = 0;
1871
1872         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1873                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1874                              dev->data->port_id);
1875                 return -EINVAL;
1876         }
1877
1878         rte_intr_disable(intr_handle);
1879
1880         if ((rte_intr_cap_multiple(intr_handle) ||
1881              !RTE_ETH_DEV_SRIOV(dev).active) &&
1882             dev->data->dev_conf.intr_conf.rxq != 0) {
1883                 intr_vector = dev->data->nb_rx_queues;
1884                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1885                         return -1;
1886         }
1887
1888         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1889                 intr_handle->intr_vec =
1890                         rte_zmalloc("intr_vec",
1891                                     dev->data->nb_rx_queues * sizeof(int),
1892                                     0);
1893                 if (!intr_handle->intr_vec) {
1894                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1895                                      " intr_vec\n", dev->data->nb_rx_queues);
1896                         return -ENOMEM;
1897                 }
1898         }
1899
1900         /* Initialize VSI */
1901         ret = i40e_dev_rxtx_init(pf);
1902         if (ret != I40E_SUCCESS) {
1903                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1904                 goto err_up;
1905         }
1906
1907         /* Map queues with MSIX interrupt */
1908         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1909                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1910         i40e_vsi_queues_bind_intr(main_vsi);
1911         i40e_vsi_enable_queues_intr(main_vsi);
1912
1913         /* Map VMDQ VSI queues with MSIX interrupt */
1914         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1915                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1916                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1917                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1918         }
1919
1920         /* enable FDIR MSIX interrupt */
1921         if (pf->fdir.fdir_vsi) {
1922                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1923                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1924         }
1925
1926         /* Enable all queues which have been configured */
1927         ret = i40e_dev_switch_queues(pf, TRUE);
1928         if (ret != I40E_SUCCESS) {
1929                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1930                 goto err_up;
1931         }
1932
1933         /* Enable receiving broadcast packets */
1934         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1935         if (ret != I40E_SUCCESS)
1936                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1937
1938         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1939                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1940                                                 true, NULL);
1941                 if (ret != I40E_SUCCESS)
1942                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1943         }
1944
1945         /* Apply link configure */
1946         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1947                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1948                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1949                                 ETH_LINK_SPEED_40G)) {
1950                 PMD_DRV_LOG(ERR, "Invalid link setting");
1951                 goto err_up;
1952         }
1953         ret = i40e_apply_link_speed(dev);
1954         if (I40E_SUCCESS != ret) {
1955                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1956                 goto err_up;
1957         }
1958
1959         if (!rte_intr_allow_others(intr_handle)) {
1960                 rte_intr_callback_unregister(intr_handle,
1961                                              i40e_dev_interrupt_handler,
1962                                              (void *)dev);
1963                 /* configure and enable device interrupt */
1964                 i40e_pf_config_irq0(hw, FALSE);
1965                 i40e_pf_enable_irq0(hw);
1966
1967                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1968                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1969                                      " no intr multiplex\n");
1970         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1971                 ret = i40e_aq_set_phy_int_mask(hw,
1972                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1973                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1974                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1975                 if (ret != I40E_SUCCESS)
1976                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1977
1978                 /* Call get_link_info aq commond to enable LSE */
1979                 i40e_dev_link_update(dev, 0);
1980         }
1981
1982         /* enable uio intr after callback register */
1983         rte_intr_enable(intr_handle);
1984
1985         i40e_filter_restore(pf);
1986
1987         return I40E_SUCCESS;
1988
1989 err_up:
1990         i40e_dev_switch_queues(pf, FALSE);
1991         i40e_dev_clear_queues(dev);
1992
1993         return ret;
1994 }
1995
1996 static void
1997 i40e_dev_stop(struct rte_eth_dev *dev)
1998 {
1999         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2000         struct i40e_vsi *main_vsi = pf->main_vsi;
2001         struct i40e_mirror_rule *p_mirror;
2002         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2003         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2004         int i;
2005
2006         /* Disable all queues */
2007         i40e_dev_switch_queues(pf, FALSE);
2008
2009         /* un-map queues with interrupt registers */
2010         i40e_vsi_disable_queues_intr(main_vsi);
2011         i40e_vsi_queues_unbind_intr(main_vsi);
2012
2013         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2014                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2015                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2016         }
2017
2018         if (pf->fdir.fdir_vsi) {
2019                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2020                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2021         }
2022         /* Clear all queues and release memory */
2023         i40e_dev_clear_queues(dev);
2024
2025         /* Set link down */
2026         i40e_dev_set_link_down(dev);
2027
2028         /* Remove all mirror rules */
2029         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2030                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2031                 rte_free(p_mirror);
2032         }
2033         pf->nb_mirror_rule = 0;
2034
2035         if (!rte_intr_allow_others(intr_handle))
2036                 /* resume to the default handler */
2037                 rte_intr_callback_register(intr_handle,
2038                                            i40e_dev_interrupt_handler,
2039                                            (void *)dev);
2040
2041         /* Clean datapath event and queue/vec mapping */
2042         rte_intr_efd_disable(intr_handle);
2043         if (intr_handle->intr_vec) {
2044                 rte_free(intr_handle->intr_vec);
2045                 intr_handle->intr_vec = NULL;
2046         }
2047 }
2048
2049 static void
2050 i40e_dev_close(struct rte_eth_dev *dev)
2051 {
2052         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2053         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2054         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2055         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2056         uint32_t reg;
2057         int i;
2058
2059         PMD_INIT_FUNC_TRACE();
2060
2061         i40e_dev_stop(dev);
2062         hw->adapter_stopped = 1;
2063         i40e_dev_free_queues(dev);
2064
2065         /* Disable interrupt */
2066         i40e_pf_disable_irq0(hw);
2067         rte_intr_disable(intr_handle);
2068
2069         /* shutdown and destroy the HMC */
2070         i40e_shutdown_lan_hmc(hw);
2071
2072         /* release all the existing VSIs and VEBs */
2073         i40e_fdir_teardown(pf);
2074         i40e_vsi_release(pf->main_vsi);
2075
2076         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2077                 i40e_vsi_release(pf->vmdq[i].vsi);
2078                 pf->vmdq[i].vsi = NULL;
2079         }
2080
2081         rte_free(pf->vmdq);
2082         pf->vmdq = NULL;
2083
2084         /* shutdown the adminq */
2085         i40e_aq_queue_shutdown(hw, true);
2086         i40e_shutdown_adminq(hw);
2087
2088         i40e_res_pool_destroy(&pf->qp_pool);
2089         i40e_res_pool_destroy(&pf->msix_pool);
2090
2091         /* force a PF reset to clean anything leftover */
2092         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2093         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2094                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2095         I40E_WRITE_FLUSH(hw);
2096 }
2097
2098 static void
2099 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2100 {
2101         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2102         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2103         struct i40e_vsi *vsi = pf->main_vsi;
2104         int status;
2105
2106         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2107                                                      true, NULL, true);
2108         if (status != I40E_SUCCESS)
2109                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2110
2111         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2112                                                         TRUE, NULL);
2113         if (status != I40E_SUCCESS)
2114                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2115
2116 }
2117
2118 static void
2119 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2120 {
2121         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2122         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2123         struct i40e_vsi *vsi = pf->main_vsi;
2124         int status;
2125
2126         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2127                                                      false, NULL, true);
2128         if (status != I40E_SUCCESS)
2129                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2130
2131         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2132                                                         false, NULL);
2133         if (status != I40E_SUCCESS)
2134                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2135 }
2136
2137 static void
2138 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2139 {
2140         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2141         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2142         struct i40e_vsi *vsi = pf->main_vsi;
2143         int ret;
2144
2145         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2146         if (ret != I40E_SUCCESS)
2147                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2148 }
2149
2150 static void
2151 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2152 {
2153         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2154         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2155         struct i40e_vsi *vsi = pf->main_vsi;
2156         int ret;
2157
2158         if (dev->data->promiscuous == 1)
2159                 return; /* must remain in all_multicast mode */
2160
2161         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2162                                 vsi->seid, FALSE, NULL);
2163         if (ret != I40E_SUCCESS)
2164                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2165 }
2166
2167 /*
2168  * Set device link up.
2169  */
2170 static int
2171 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2172 {
2173         /* re-apply link speed setting */
2174         return i40e_apply_link_speed(dev);
2175 }
2176
2177 /*
2178  * Set device link down.
2179  */
2180 static int
2181 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2182 {
2183         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2184         uint8_t abilities = 0;
2185         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2186
2187         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2188         return i40e_phy_conf_link(hw, abilities, speed);
2189 }
2190
2191 int
2192 i40e_dev_link_update(struct rte_eth_dev *dev,
2193                      int wait_to_complete)
2194 {
2195 #define CHECK_INTERVAL 100  /* 100ms */
2196 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2197         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2198         struct i40e_link_status link_status;
2199         struct rte_eth_link link, old;
2200         int status;
2201         unsigned rep_cnt = MAX_REPEAT_TIME;
2202         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2203
2204         memset(&link, 0, sizeof(link));
2205         memset(&old, 0, sizeof(old));
2206         memset(&link_status, 0, sizeof(link_status));
2207         rte_i40e_dev_atomic_read_link_status(dev, &old);
2208
2209         do {
2210                 /* Get link status information from hardware */
2211                 status = i40e_aq_get_link_info(hw, enable_lse,
2212                                                 &link_status, NULL);
2213                 if (status != I40E_SUCCESS) {
2214                         link.link_speed = ETH_SPEED_NUM_100M;
2215                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2216                         PMD_DRV_LOG(ERR, "Failed to get link info");
2217                         goto out;
2218                 }
2219
2220                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2221                 if (!wait_to_complete)
2222                         break;
2223
2224                 rte_delay_ms(CHECK_INTERVAL);
2225         } while (!link.link_status && rep_cnt--);
2226
2227         if (!link.link_status)
2228                 goto out;
2229
2230         /* i40e uses full duplex only */
2231         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2232
2233         /* Parse the link status */
2234         switch (link_status.link_speed) {
2235         case I40E_LINK_SPEED_100MB:
2236                 link.link_speed = ETH_SPEED_NUM_100M;
2237                 break;
2238         case I40E_LINK_SPEED_1GB:
2239                 link.link_speed = ETH_SPEED_NUM_1G;
2240                 break;
2241         case I40E_LINK_SPEED_10GB:
2242                 link.link_speed = ETH_SPEED_NUM_10G;
2243                 break;
2244         case I40E_LINK_SPEED_20GB:
2245                 link.link_speed = ETH_SPEED_NUM_20G;
2246                 break;
2247         case I40E_LINK_SPEED_25GB:
2248                 link.link_speed = ETH_SPEED_NUM_25G;
2249                 break;
2250         case I40E_LINK_SPEED_40GB:
2251                 link.link_speed = ETH_SPEED_NUM_40G;
2252                 break;
2253         default:
2254                 link.link_speed = ETH_SPEED_NUM_100M;
2255                 break;
2256         }
2257
2258         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2259                         ETH_LINK_SPEED_FIXED);
2260
2261 out:
2262         rte_i40e_dev_atomic_write_link_status(dev, &link);
2263         if (link.link_status == old.link_status)
2264                 return -1;
2265
2266         return 0;
2267 }
2268
2269 /* Get all the statistics of a VSI */
2270 void
2271 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2272 {
2273         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2274         struct i40e_eth_stats *nes = &vsi->eth_stats;
2275         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2276         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2277
2278         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2279                             vsi->offset_loaded, &oes->rx_bytes,
2280                             &nes->rx_bytes);
2281         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2282                             vsi->offset_loaded, &oes->rx_unicast,
2283                             &nes->rx_unicast);
2284         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2285                             vsi->offset_loaded, &oes->rx_multicast,
2286                             &nes->rx_multicast);
2287         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2288                             vsi->offset_loaded, &oes->rx_broadcast,
2289                             &nes->rx_broadcast);
2290         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2291                             &oes->rx_discards, &nes->rx_discards);
2292         /* GLV_REPC not supported */
2293         /* GLV_RMPC not supported */
2294         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2295                             &oes->rx_unknown_protocol,
2296                             &nes->rx_unknown_protocol);
2297         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2298                             vsi->offset_loaded, &oes->tx_bytes,
2299                             &nes->tx_bytes);
2300         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2301                             vsi->offset_loaded, &oes->tx_unicast,
2302                             &nes->tx_unicast);
2303         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2304                             vsi->offset_loaded, &oes->tx_multicast,
2305                             &nes->tx_multicast);
2306         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2307                             vsi->offset_loaded,  &oes->tx_broadcast,
2308                             &nes->tx_broadcast);
2309         /* GLV_TDPC not supported */
2310         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2311                             &oes->tx_errors, &nes->tx_errors);
2312         vsi->offset_loaded = true;
2313
2314         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2315                     vsi->vsi_id);
2316         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2317         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2318         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2319         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2320         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2321         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2322                     nes->rx_unknown_protocol);
2323         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2324         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2325         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2326         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2327         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2328         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2329         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2330                     vsi->vsi_id);
2331 }
2332
2333 static void
2334 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2335 {
2336         unsigned int i;
2337         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2338         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2339
2340         /* Get statistics of struct i40e_eth_stats */
2341         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2342                             I40E_GLPRT_GORCL(hw->port),
2343                             pf->offset_loaded, &os->eth.rx_bytes,
2344                             &ns->eth.rx_bytes);
2345         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2346                             I40E_GLPRT_UPRCL(hw->port),
2347                             pf->offset_loaded, &os->eth.rx_unicast,
2348                             &ns->eth.rx_unicast);
2349         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2350                             I40E_GLPRT_MPRCL(hw->port),
2351                             pf->offset_loaded, &os->eth.rx_multicast,
2352                             &ns->eth.rx_multicast);
2353         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2354                             I40E_GLPRT_BPRCL(hw->port),
2355                             pf->offset_loaded, &os->eth.rx_broadcast,
2356                             &ns->eth.rx_broadcast);
2357         /* Workaround: CRC size should not be included in byte statistics,
2358          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2359          */
2360         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2361                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2362
2363         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2364                             pf->offset_loaded, &os->eth.rx_discards,
2365                             &ns->eth.rx_discards);
2366         /* GLPRT_REPC not supported */
2367         /* GLPRT_RMPC not supported */
2368         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2369                             pf->offset_loaded,
2370                             &os->eth.rx_unknown_protocol,
2371                             &ns->eth.rx_unknown_protocol);
2372         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2373                             I40E_GLPRT_GOTCL(hw->port),
2374                             pf->offset_loaded, &os->eth.tx_bytes,
2375                             &ns->eth.tx_bytes);
2376         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2377                             I40E_GLPRT_UPTCL(hw->port),
2378                             pf->offset_loaded, &os->eth.tx_unicast,
2379                             &ns->eth.tx_unicast);
2380         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2381                             I40E_GLPRT_MPTCL(hw->port),
2382                             pf->offset_loaded, &os->eth.tx_multicast,
2383                             &ns->eth.tx_multicast);
2384         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2385                             I40E_GLPRT_BPTCL(hw->port),
2386                             pf->offset_loaded, &os->eth.tx_broadcast,
2387                             &ns->eth.tx_broadcast);
2388         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2389                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2390         /* GLPRT_TEPC not supported */
2391
2392         /* additional port specific stats */
2393         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2394                             pf->offset_loaded, &os->tx_dropped_link_down,
2395                             &ns->tx_dropped_link_down);
2396         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2397                             pf->offset_loaded, &os->crc_errors,
2398                             &ns->crc_errors);
2399         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2400                             pf->offset_loaded, &os->illegal_bytes,
2401                             &ns->illegal_bytes);
2402         /* GLPRT_ERRBC not supported */
2403         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2404                             pf->offset_loaded, &os->mac_local_faults,
2405                             &ns->mac_local_faults);
2406         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2407                             pf->offset_loaded, &os->mac_remote_faults,
2408                             &ns->mac_remote_faults);
2409         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2410                             pf->offset_loaded, &os->rx_length_errors,
2411                             &ns->rx_length_errors);
2412         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2413                             pf->offset_loaded, &os->link_xon_rx,
2414                             &ns->link_xon_rx);
2415         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2416                             pf->offset_loaded, &os->link_xoff_rx,
2417                             &ns->link_xoff_rx);
2418         for (i = 0; i < 8; i++) {
2419                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2420                                     pf->offset_loaded,
2421                                     &os->priority_xon_rx[i],
2422                                     &ns->priority_xon_rx[i]);
2423                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2424                                     pf->offset_loaded,
2425                                     &os->priority_xoff_rx[i],
2426                                     &ns->priority_xoff_rx[i]);
2427         }
2428         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2429                             pf->offset_loaded, &os->link_xon_tx,
2430                             &ns->link_xon_tx);
2431         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2432                             pf->offset_loaded, &os->link_xoff_tx,
2433                             &ns->link_xoff_tx);
2434         for (i = 0; i < 8; i++) {
2435                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2436                                     pf->offset_loaded,
2437                                     &os->priority_xon_tx[i],
2438                                     &ns->priority_xon_tx[i]);
2439                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2440                                     pf->offset_loaded,
2441                                     &os->priority_xoff_tx[i],
2442                                     &ns->priority_xoff_tx[i]);
2443                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2444                                     pf->offset_loaded,
2445                                     &os->priority_xon_2_xoff[i],
2446                                     &ns->priority_xon_2_xoff[i]);
2447         }
2448         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2449                             I40E_GLPRT_PRC64L(hw->port),
2450                             pf->offset_loaded, &os->rx_size_64,
2451                             &ns->rx_size_64);
2452         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2453                             I40E_GLPRT_PRC127L(hw->port),
2454                             pf->offset_loaded, &os->rx_size_127,
2455                             &ns->rx_size_127);
2456         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2457                             I40E_GLPRT_PRC255L(hw->port),
2458                             pf->offset_loaded, &os->rx_size_255,
2459                             &ns->rx_size_255);
2460         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2461                             I40E_GLPRT_PRC511L(hw->port),
2462                             pf->offset_loaded, &os->rx_size_511,
2463                             &ns->rx_size_511);
2464         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2465                             I40E_GLPRT_PRC1023L(hw->port),
2466                             pf->offset_loaded, &os->rx_size_1023,
2467                             &ns->rx_size_1023);
2468         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2469                             I40E_GLPRT_PRC1522L(hw->port),
2470                             pf->offset_loaded, &os->rx_size_1522,
2471                             &ns->rx_size_1522);
2472         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2473                             I40E_GLPRT_PRC9522L(hw->port),
2474                             pf->offset_loaded, &os->rx_size_big,
2475                             &ns->rx_size_big);
2476         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2477                             pf->offset_loaded, &os->rx_undersize,
2478                             &ns->rx_undersize);
2479         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2480                             pf->offset_loaded, &os->rx_fragments,
2481                             &ns->rx_fragments);
2482         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2483                             pf->offset_loaded, &os->rx_oversize,
2484                             &ns->rx_oversize);
2485         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2486                             pf->offset_loaded, &os->rx_jabber,
2487                             &ns->rx_jabber);
2488         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2489                             I40E_GLPRT_PTC64L(hw->port),
2490                             pf->offset_loaded, &os->tx_size_64,
2491                             &ns->tx_size_64);
2492         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2493                             I40E_GLPRT_PTC127L(hw->port),
2494                             pf->offset_loaded, &os->tx_size_127,
2495                             &ns->tx_size_127);
2496         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2497                             I40E_GLPRT_PTC255L(hw->port),
2498                             pf->offset_loaded, &os->tx_size_255,
2499                             &ns->tx_size_255);
2500         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2501                             I40E_GLPRT_PTC511L(hw->port),
2502                             pf->offset_loaded, &os->tx_size_511,
2503                             &ns->tx_size_511);
2504         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2505                             I40E_GLPRT_PTC1023L(hw->port),
2506                             pf->offset_loaded, &os->tx_size_1023,
2507                             &ns->tx_size_1023);
2508         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2509                             I40E_GLPRT_PTC1522L(hw->port),
2510                             pf->offset_loaded, &os->tx_size_1522,
2511                             &ns->tx_size_1522);
2512         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2513                             I40E_GLPRT_PTC9522L(hw->port),
2514                             pf->offset_loaded, &os->tx_size_big,
2515                             &ns->tx_size_big);
2516         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2517                            pf->offset_loaded,
2518                            &os->fd_sb_match, &ns->fd_sb_match);
2519         /* GLPRT_MSPDC not supported */
2520         /* GLPRT_XEC not supported */
2521
2522         pf->offset_loaded = true;
2523
2524         if (pf->main_vsi)
2525                 i40e_update_vsi_stats(pf->main_vsi);
2526 }
2527
2528 /* Get all statistics of a port */
2529 static void
2530 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2531 {
2532         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2533         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2534         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2535         unsigned i;
2536
2537         /* call read registers - updates values, now write them to struct */
2538         i40e_read_stats_registers(pf, hw);
2539
2540         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2541                         pf->main_vsi->eth_stats.rx_multicast +
2542                         pf->main_vsi->eth_stats.rx_broadcast -
2543                         pf->main_vsi->eth_stats.rx_discards;
2544         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2545                         pf->main_vsi->eth_stats.tx_multicast +
2546                         pf->main_vsi->eth_stats.tx_broadcast;
2547         stats->ibytes   = ns->eth.rx_bytes;
2548         stats->obytes   = ns->eth.tx_bytes;
2549         stats->oerrors  = ns->eth.tx_errors +
2550                         pf->main_vsi->eth_stats.tx_errors;
2551
2552         /* Rx Errors */
2553         stats->imissed  = ns->eth.rx_discards +
2554                         pf->main_vsi->eth_stats.rx_discards;
2555         stats->ierrors  = ns->crc_errors +
2556                         ns->rx_length_errors + ns->rx_undersize +
2557                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2558
2559         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2560         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2561         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2562         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2563         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2564         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2565         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2566                     ns->eth.rx_unknown_protocol);
2567         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2568         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2569         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2570         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2571         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2572         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2573
2574         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2575                     ns->tx_dropped_link_down);
2576         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2577         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2578                     ns->illegal_bytes);
2579         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2580         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2581                     ns->mac_local_faults);
2582         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2583                     ns->mac_remote_faults);
2584         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2585                     ns->rx_length_errors);
2586         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2587         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2588         for (i = 0; i < 8; i++) {
2589                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2590                                 i, ns->priority_xon_rx[i]);
2591                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2592                                 i, ns->priority_xoff_rx[i]);
2593         }
2594         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2595         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2596         for (i = 0; i < 8; i++) {
2597                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2598                                 i, ns->priority_xon_tx[i]);
2599                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2600                                 i, ns->priority_xoff_tx[i]);
2601                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2602                                 i, ns->priority_xon_2_xoff[i]);
2603         }
2604         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2605         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2606         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2607         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2608         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2609         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2610         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2611         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2612         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2613         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2614         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2615         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2616         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2617         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2618         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2619         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2620         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2621         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2622         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2623                         ns->mac_short_packet_dropped);
2624         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2625                     ns->checksum_error);
2626         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2627         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2628 }
2629
2630 /* Reset the statistics */
2631 static void
2632 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2633 {
2634         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2635         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2636
2637         /* Mark PF and VSI stats to update the offset, aka "reset" */
2638         pf->offset_loaded = false;
2639         if (pf->main_vsi)
2640                 pf->main_vsi->offset_loaded = false;
2641
2642         /* read the stats, reading current register values into offset */
2643         i40e_read_stats_registers(pf, hw);
2644 }
2645
2646 static uint32_t
2647 i40e_xstats_calc_num(void)
2648 {
2649         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2650                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2651                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2652 }
2653
2654 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2655                                      struct rte_eth_xstat_name *xstats_names,
2656                                      __rte_unused unsigned limit)
2657 {
2658         unsigned count = 0;
2659         unsigned i, prio;
2660
2661         if (xstats_names == NULL)
2662                 return i40e_xstats_calc_num();
2663
2664         /* Note: limit checked in rte_eth_xstats_names() */
2665
2666         /* Get stats from i40e_eth_stats struct */
2667         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2668                 snprintf(xstats_names[count].name,
2669                          sizeof(xstats_names[count].name),
2670                          "%s", rte_i40e_stats_strings[i].name);
2671                 count++;
2672         }
2673
2674         /* Get individiual stats from i40e_hw_port struct */
2675         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2676                 snprintf(xstats_names[count].name,
2677                         sizeof(xstats_names[count].name),
2678                          "%s", rte_i40e_hw_port_strings[i].name);
2679                 count++;
2680         }
2681
2682         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2683                 for (prio = 0; prio < 8; prio++) {
2684                         snprintf(xstats_names[count].name,
2685                                  sizeof(xstats_names[count].name),
2686                                  "rx_priority%u_%s", prio,
2687                                  rte_i40e_rxq_prio_strings[i].name);
2688                         count++;
2689                 }
2690         }
2691
2692         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2693                 for (prio = 0; prio < 8; prio++) {
2694                         snprintf(xstats_names[count].name,
2695                                  sizeof(xstats_names[count].name),
2696                                  "tx_priority%u_%s", prio,
2697                                  rte_i40e_txq_prio_strings[i].name);
2698                         count++;
2699                 }
2700         }
2701         return count;
2702 }
2703
2704 static int
2705 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2706                     unsigned n)
2707 {
2708         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2709         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2710         unsigned i, count, prio;
2711         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2712
2713         count = i40e_xstats_calc_num();
2714         if (n < count)
2715                 return count;
2716
2717         i40e_read_stats_registers(pf, hw);
2718
2719         if (xstats == NULL)
2720                 return 0;
2721
2722         count = 0;
2723
2724         /* Get stats from i40e_eth_stats struct */
2725         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2726                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2727                         rte_i40e_stats_strings[i].offset);
2728                 xstats[count].id = count;
2729                 count++;
2730         }
2731
2732         /* Get individiual stats from i40e_hw_port struct */
2733         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2734                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2735                         rte_i40e_hw_port_strings[i].offset);
2736                 xstats[count].id = count;
2737                 count++;
2738         }
2739
2740         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2741                 for (prio = 0; prio < 8; prio++) {
2742                         xstats[count].value =
2743                                 *(uint64_t *)(((char *)hw_stats) +
2744                                 rte_i40e_rxq_prio_strings[i].offset +
2745                                 (sizeof(uint64_t) * prio));
2746                         xstats[count].id = count;
2747                         count++;
2748                 }
2749         }
2750
2751         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2752                 for (prio = 0; prio < 8; prio++) {
2753                         xstats[count].value =
2754                                 *(uint64_t *)(((char *)hw_stats) +
2755                                 rte_i40e_txq_prio_strings[i].offset +
2756                                 (sizeof(uint64_t) * prio));
2757                         xstats[count].id = count;
2758                         count++;
2759                 }
2760         }
2761
2762         return count;
2763 }
2764
2765 static int
2766 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2767                                  __rte_unused uint16_t queue_id,
2768                                  __rte_unused uint8_t stat_idx,
2769                                  __rte_unused uint8_t is_rx)
2770 {
2771         PMD_INIT_FUNC_TRACE();
2772
2773         return -ENOSYS;
2774 }
2775
2776 static int
2777 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2778 {
2779         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2780         u32 full_ver;
2781         u8 ver, patch;
2782         u16 build;
2783         int ret;
2784
2785         full_ver = hw->nvm.oem_ver;
2786         ver = (u8)(full_ver >> 24);
2787         build = (u16)((full_ver >> 8) & 0xffff);
2788         patch = (u8)(full_ver & 0xff);
2789
2790         ret = snprintf(fw_version, fw_size,
2791                  "%d.%d%d 0x%08x %d.%d.%d",
2792                  ((hw->nvm.version >> 12) & 0xf),
2793                  ((hw->nvm.version >> 4) & 0xff),
2794                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2795                  ver, build, patch);
2796
2797         ret += 1; /* add the size of '\0' */
2798         if (fw_size < (u32)ret)
2799                 return ret;
2800         else
2801                 return 0;
2802 }
2803
2804 static void
2805 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2806 {
2807         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2808         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2809         struct i40e_vsi *vsi = pf->main_vsi;
2810         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2811
2812         dev_info->pci_dev = pci_dev;
2813         dev_info->max_rx_queues = vsi->nb_qps;
2814         dev_info->max_tx_queues = vsi->nb_qps;
2815         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2816         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2817         dev_info->max_mac_addrs = vsi->max_macaddrs;
2818         dev_info->max_vfs = pci_dev->max_vfs;
2819         dev_info->rx_offload_capa =
2820                 DEV_RX_OFFLOAD_VLAN_STRIP |
2821                 DEV_RX_OFFLOAD_QINQ_STRIP |
2822                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2823                 DEV_RX_OFFLOAD_UDP_CKSUM |
2824                 DEV_RX_OFFLOAD_TCP_CKSUM;
2825         dev_info->tx_offload_capa =
2826                 DEV_TX_OFFLOAD_VLAN_INSERT |
2827                 DEV_TX_OFFLOAD_QINQ_INSERT |
2828                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2829                 DEV_TX_OFFLOAD_UDP_CKSUM |
2830                 DEV_TX_OFFLOAD_TCP_CKSUM |
2831                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2832                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2833                 DEV_TX_OFFLOAD_TCP_TSO |
2834                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2835                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2836                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2837                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2838         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2839                                                 sizeof(uint32_t);
2840         dev_info->reta_size = pf->hash_lut_size;
2841         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2842
2843         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2844                 .rx_thresh = {
2845                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2846                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2847                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2848                 },
2849                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2850                 .rx_drop_en = 0,
2851         };
2852
2853         dev_info->default_txconf = (struct rte_eth_txconf) {
2854                 .tx_thresh = {
2855                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2856                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2857                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2858                 },
2859                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2860                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2861                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2862                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2863         };
2864
2865         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2866                 .nb_max = I40E_MAX_RING_DESC,
2867                 .nb_min = I40E_MIN_RING_DESC,
2868                 .nb_align = I40E_ALIGN_RING_DESC,
2869         };
2870
2871         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2872                 .nb_max = I40E_MAX_RING_DESC,
2873                 .nb_min = I40E_MIN_RING_DESC,
2874                 .nb_align = I40E_ALIGN_RING_DESC,
2875                 .nb_seg_max = I40E_TX_MAX_SEG,
2876                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2877         };
2878
2879         if (pf->flags & I40E_FLAG_VMDQ) {
2880                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2881                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2882                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2883                                                 pf->max_nb_vmdq_vsi;
2884                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2885                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2886                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2887         }
2888
2889         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2890                 /* For XL710 */
2891                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2892         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2893                 /* For XXV710 */
2894                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2895         else
2896                 /* For X710 */
2897                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2898 }
2899
2900 static int
2901 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2902 {
2903         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2904         struct i40e_vsi *vsi = pf->main_vsi;
2905         PMD_INIT_FUNC_TRACE();
2906
2907         if (on)
2908                 return i40e_vsi_add_vlan(vsi, vlan_id);
2909         else
2910                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2911 }
2912
2913 static int
2914 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2915                    enum rte_vlan_type vlan_type,
2916                    uint16_t tpid)
2917 {
2918         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2919         uint64_t reg_r = 0, reg_w = 0;
2920         uint16_t reg_id = 0;
2921         int ret = 0;
2922         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2923
2924         switch (vlan_type) {
2925         case ETH_VLAN_TYPE_OUTER:
2926                 if (qinq)
2927                         reg_id = 2;
2928                 else
2929                         reg_id = 3;
2930                 break;
2931         case ETH_VLAN_TYPE_INNER:
2932                 if (qinq)
2933                         reg_id = 3;
2934                 else {
2935                         ret = -EINVAL;
2936                         PMD_DRV_LOG(ERR,
2937                                 "Unsupported vlan type in single vlan.\n");
2938                         return ret;
2939                 }
2940                 break;
2941         default:
2942                 ret = -EINVAL;
2943                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2944                 return ret;
2945         }
2946         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2947                                           &reg_r, NULL);
2948         if (ret != I40E_SUCCESS) {
2949                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2950                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2951                 ret = -EIO;
2952                 return ret;
2953         }
2954         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2955                     "0x%08"PRIx64"", reg_id, reg_r);
2956
2957         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2958         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2959         if (reg_r == reg_w) {
2960                 ret = 0;
2961                 PMD_DRV_LOG(DEBUG, "No need to write");
2962                 return ret;
2963         }
2964
2965         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2966                                            reg_w, NULL);
2967         if (ret != I40E_SUCCESS) {
2968                 ret = -EIO;
2969                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2970                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2971                 return ret;
2972         }
2973         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2974                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2975
2976         return ret;
2977 }
2978
2979 static void
2980 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2981 {
2982         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2983         struct i40e_vsi *vsi = pf->main_vsi;
2984
2985         if (mask & ETH_VLAN_FILTER_MASK) {
2986                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2987                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2988                 else
2989                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2990         }
2991
2992         if (mask & ETH_VLAN_STRIP_MASK) {
2993                 /* Enable or disable VLAN stripping */
2994                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2995                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2996                 else
2997                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2998         }
2999
3000         if (mask & ETH_VLAN_EXTEND_MASK) {
3001                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3002                         i40e_vsi_config_double_vlan(vsi, TRUE);
3003                         /* Set global registers with default ether type value */
3004                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3005                                            ETHER_TYPE_VLAN);
3006                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3007                                            ETHER_TYPE_VLAN);
3008                 }
3009                 else
3010                         i40e_vsi_config_double_vlan(vsi, FALSE);
3011         }
3012 }
3013
3014 static void
3015 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3016                           __rte_unused uint16_t queue,
3017                           __rte_unused int on)
3018 {
3019         PMD_INIT_FUNC_TRACE();
3020 }
3021
3022 static int
3023 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3024 {
3025         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3026         struct i40e_vsi *vsi = pf->main_vsi;
3027         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3028         struct i40e_vsi_vlan_pvid_info info;
3029
3030         memset(&info, 0, sizeof(info));
3031         info.on = on;
3032         if (info.on)
3033                 info.config.pvid = pvid;
3034         else {
3035                 info.config.reject.tagged =
3036                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3037                 info.config.reject.untagged =
3038                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3039         }
3040
3041         return i40e_vsi_vlan_pvid_set(vsi, &info);
3042 }
3043
3044 static int
3045 i40e_dev_led_on(struct rte_eth_dev *dev)
3046 {
3047         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3048         uint32_t mode = i40e_led_get(hw);
3049
3050         if (mode == 0)
3051                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3052
3053         return 0;
3054 }
3055
3056 static int
3057 i40e_dev_led_off(struct rte_eth_dev *dev)
3058 {
3059         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3060         uint32_t mode = i40e_led_get(hw);
3061
3062         if (mode != 0)
3063                 i40e_led_set(hw, 0, false);
3064
3065         return 0;
3066 }
3067
3068 static int
3069 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3070 {
3071         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3072         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3073
3074         fc_conf->pause_time = pf->fc_conf.pause_time;
3075         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3076         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3077
3078          /* Return current mode according to actual setting*/
3079         switch (hw->fc.current_mode) {
3080         case I40E_FC_FULL:
3081                 fc_conf->mode = RTE_FC_FULL;
3082                 break;
3083         case I40E_FC_TX_PAUSE:
3084                 fc_conf->mode = RTE_FC_TX_PAUSE;
3085                 break;
3086         case I40E_FC_RX_PAUSE:
3087                 fc_conf->mode = RTE_FC_RX_PAUSE;
3088                 break;
3089         case I40E_FC_NONE:
3090         default:
3091                 fc_conf->mode = RTE_FC_NONE;
3092         };
3093
3094         return 0;
3095 }
3096
3097 static int
3098 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3099 {
3100         uint32_t mflcn_reg, fctrl_reg, reg;
3101         uint32_t max_high_water;
3102         uint8_t i, aq_failure;
3103         int err;
3104         struct i40e_hw *hw;
3105         struct i40e_pf *pf;
3106         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3107                 [RTE_FC_NONE] = I40E_FC_NONE,
3108                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3109                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3110                 [RTE_FC_FULL] = I40E_FC_FULL
3111         };
3112
3113         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3114
3115         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3116         if ((fc_conf->high_water > max_high_water) ||
3117                         (fc_conf->high_water < fc_conf->low_water)) {
3118                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
3119                         "High_water must <= %d.", max_high_water);
3120                 return -EINVAL;
3121         }
3122
3123         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3124         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3125         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3126
3127         pf->fc_conf.pause_time = fc_conf->pause_time;
3128         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3129         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3130
3131         PMD_INIT_FUNC_TRACE();
3132
3133         /* All the link flow control related enable/disable register
3134          * configuration is handle by the F/W
3135          */
3136         err = i40e_set_fc(hw, &aq_failure, true);
3137         if (err < 0)
3138                 return -ENOSYS;
3139
3140         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3141                 /* Configure flow control refresh threshold,
3142                  * the value for stat_tx_pause_refresh_timer[8]
3143                  * is used for global pause operation.
3144                  */
3145
3146                 I40E_WRITE_REG(hw,
3147                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3148                                pf->fc_conf.pause_time);
3149
3150                 /* configure the timer value included in transmitted pause
3151                  * frame,
3152                  * the value for stat_tx_pause_quanta[8] is used for global
3153                  * pause operation
3154                  */
3155                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3156                                pf->fc_conf.pause_time);
3157
3158                 fctrl_reg = I40E_READ_REG(hw,
3159                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3160
3161                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3162                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3163                 else
3164                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3165
3166                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3167                                fctrl_reg);
3168         } else {
3169                 /* Configure pause time (2 TCs per register) */
3170                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3171                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3172                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3173
3174                 /* Configure flow control refresh threshold value */
3175                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3176                                pf->fc_conf.pause_time / 2);
3177
3178                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3179
3180                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3181                  *depending on configuration
3182                  */
3183                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3184                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3185                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3186                 } else {
3187                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3188                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3189                 }
3190
3191                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3192         }
3193
3194         /* config the water marker both based on the packets and bytes */
3195         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3196                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3197                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3198         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3199                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3200                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3201         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3202                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3203                        << I40E_KILOSHIFT);
3204         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3205                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3206                        << I40E_KILOSHIFT);
3207
3208         I40E_WRITE_FLUSH(hw);
3209
3210         return 0;
3211 }
3212
3213 static int
3214 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3215                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3216 {
3217         PMD_INIT_FUNC_TRACE();
3218
3219         return -ENOSYS;
3220 }
3221
3222 /* Add a MAC address, and update filters */
3223 static void
3224 i40e_macaddr_add(struct rte_eth_dev *dev,
3225                  struct ether_addr *mac_addr,
3226                  __rte_unused uint32_t index,
3227                  uint32_t pool)
3228 {
3229         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3230         struct i40e_mac_filter_info mac_filter;
3231         struct i40e_vsi *vsi;
3232         int ret;
3233
3234         /* If VMDQ not enabled or configured, return */
3235         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3236                           !pf->nb_cfg_vmdq_vsi)) {
3237                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3238                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3239                         pool);
3240                 return;
3241         }
3242
3243         if (pool > pf->nb_cfg_vmdq_vsi) {
3244                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3245                                 pool, pf->nb_cfg_vmdq_vsi);
3246                 return;
3247         }
3248
3249         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3250         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3251                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3252         else
3253                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3254
3255         if (pool == 0)
3256                 vsi = pf->main_vsi;
3257         else
3258                 vsi = pf->vmdq[pool - 1].vsi;
3259
3260         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3261         if (ret != I40E_SUCCESS) {
3262                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3263                 return;
3264         }
3265 }
3266
3267 /* Remove a MAC address, and update filters */
3268 static void
3269 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3270 {
3271         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3272         struct i40e_vsi *vsi;
3273         struct rte_eth_dev_data *data = dev->data;
3274         struct ether_addr *macaddr;
3275         int ret;
3276         uint32_t i;
3277         uint64_t pool_sel;
3278
3279         macaddr = &(data->mac_addrs[index]);
3280
3281         pool_sel = dev->data->mac_pool_sel[index];
3282
3283         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3284                 if (pool_sel & (1ULL << i)) {
3285                         if (i == 0)
3286                                 vsi = pf->main_vsi;
3287                         else {
3288                                 /* No VMDQ pool enabled or configured */
3289                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3290                                         (i > pf->nb_cfg_vmdq_vsi)) {
3291                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3292                                                         "/configured");
3293                                         return;
3294                                 }
3295                                 vsi = pf->vmdq[i - 1].vsi;
3296                         }
3297                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3298
3299                         if (ret) {
3300                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3301                                 return;
3302                         }
3303                 }
3304         }
3305 }
3306
3307 /* Set perfect match or hash match of MAC and VLAN for a VF */
3308 static int
3309 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3310                  struct rte_eth_mac_filter *filter,
3311                  bool add)
3312 {
3313         struct i40e_hw *hw;
3314         struct i40e_mac_filter_info mac_filter;
3315         struct ether_addr old_mac;
3316         struct ether_addr *new_mac;
3317         struct i40e_pf_vf *vf = NULL;
3318         uint16_t vf_id;
3319         int ret;
3320
3321         if (pf == NULL) {
3322                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3323                 return -EINVAL;
3324         }
3325         hw = I40E_PF_TO_HW(pf);
3326
3327         if (filter == NULL) {
3328                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3329                 return -EINVAL;
3330         }
3331
3332         new_mac = &filter->mac_addr;
3333
3334         if (is_zero_ether_addr(new_mac)) {
3335                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3336                 return -EINVAL;
3337         }
3338
3339         vf_id = filter->dst_id;
3340
3341         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3342                 PMD_DRV_LOG(ERR, "Invalid argument.");
3343                 return -EINVAL;
3344         }
3345         vf = &pf->vfs[vf_id];
3346
3347         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3348                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3349                 return -EINVAL;
3350         }
3351
3352         if (add) {
3353                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3354                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3355                                 ETHER_ADDR_LEN);
3356                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3357                                  ETHER_ADDR_LEN);
3358
3359                 mac_filter.filter_type = filter->filter_type;
3360                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3361                 if (ret != I40E_SUCCESS) {
3362                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3363                         return -1;
3364                 }
3365                 ether_addr_copy(new_mac, &pf->dev_addr);
3366         } else {
3367                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3368                                 ETHER_ADDR_LEN);
3369                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3370                 if (ret != I40E_SUCCESS) {
3371                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3372                         return -1;
3373                 }
3374
3375                 /* Clear device address as it has been removed */
3376                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3377                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3378         }
3379
3380         return 0;
3381 }
3382
3383 /* MAC filter handle */
3384 static int
3385 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3386                 void *arg)
3387 {
3388         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3389         struct rte_eth_mac_filter *filter;
3390         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3391         int ret = I40E_NOT_SUPPORTED;
3392
3393         filter = (struct rte_eth_mac_filter *)(arg);
3394
3395         switch (filter_op) {
3396         case RTE_ETH_FILTER_NOP:
3397                 ret = I40E_SUCCESS;
3398                 break;
3399         case RTE_ETH_FILTER_ADD:
3400                 i40e_pf_disable_irq0(hw);
3401                 if (filter->is_vf)
3402                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3403                 i40e_pf_enable_irq0(hw);
3404                 break;
3405         case RTE_ETH_FILTER_DELETE:
3406                 i40e_pf_disable_irq0(hw);
3407                 if (filter->is_vf)
3408                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3409                 i40e_pf_enable_irq0(hw);
3410                 break;
3411         default:
3412                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3413                 ret = I40E_ERR_PARAM;
3414                 break;
3415         }
3416
3417         return ret;
3418 }
3419
3420 static int
3421 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3422 {
3423         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3424         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3425         int ret;
3426
3427         if (!lut)
3428                 return -EINVAL;
3429
3430         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3431                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3432                                           lut, lut_size);
3433                 if (ret) {
3434                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3435                         return ret;
3436                 }
3437         } else {
3438                 uint32_t *lut_dw = (uint32_t *)lut;
3439                 uint16_t i, lut_size_dw = lut_size / 4;
3440
3441                 for (i = 0; i < lut_size_dw; i++)
3442                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3443         }
3444
3445         return 0;
3446 }
3447
3448 static int
3449 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3450 {
3451         struct i40e_pf *pf;
3452         struct i40e_hw *hw;
3453         int ret;
3454
3455         if (!vsi || !lut)
3456                 return -EINVAL;
3457
3458         pf = I40E_VSI_TO_PF(vsi);
3459         hw = I40E_VSI_TO_HW(vsi);
3460
3461         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3462                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3463                                           lut, lut_size);
3464                 if (ret) {
3465                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3466                         return ret;
3467                 }
3468         } else {
3469                 uint32_t *lut_dw = (uint32_t *)lut;
3470                 uint16_t i, lut_size_dw = lut_size / 4;
3471
3472                 for (i = 0; i < lut_size_dw; i++)
3473                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3474                 I40E_WRITE_FLUSH(hw);
3475         }
3476
3477         return 0;
3478 }
3479
3480 static int
3481 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3482                          struct rte_eth_rss_reta_entry64 *reta_conf,
3483                          uint16_t reta_size)
3484 {
3485         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3486         uint16_t i, lut_size = pf->hash_lut_size;
3487         uint16_t idx, shift;
3488         uint8_t *lut;
3489         int ret;
3490
3491         if (reta_size != lut_size ||
3492                 reta_size > ETH_RSS_RETA_SIZE_512) {
3493                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3494                         "(%d) doesn't match the number hardware can supported "
3495                                         "(%d)\n", reta_size, lut_size);
3496                 return -EINVAL;
3497         }
3498
3499         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3500         if (!lut) {
3501                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3502                 return -ENOMEM;
3503         }
3504         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3505         if (ret)
3506                 goto out;
3507         for (i = 0; i < reta_size; i++) {
3508                 idx = i / RTE_RETA_GROUP_SIZE;
3509                 shift = i % RTE_RETA_GROUP_SIZE;
3510                 if (reta_conf[idx].mask & (1ULL << shift))
3511                         lut[i] = reta_conf[idx].reta[shift];
3512         }
3513         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3514
3515 out:
3516         rte_free(lut);
3517
3518         return ret;
3519 }
3520
3521 static int
3522 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3523                         struct rte_eth_rss_reta_entry64 *reta_conf,
3524                         uint16_t reta_size)
3525 {
3526         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3527         uint16_t i, lut_size = pf->hash_lut_size;
3528         uint16_t idx, shift;
3529         uint8_t *lut;
3530         int ret;
3531
3532         if (reta_size != lut_size ||
3533                 reta_size > ETH_RSS_RETA_SIZE_512) {
3534                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3535                         "(%d) doesn't match the number hardware can supported "
3536                                         "(%d)\n", reta_size, lut_size);
3537                 return -EINVAL;
3538         }
3539
3540         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3541         if (!lut) {
3542                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3543                 return -ENOMEM;
3544         }
3545
3546         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3547         if (ret)
3548                 goto out;
3549         for (i = 0; i < reta_size; i++) {
3550                 idx = i / RTE_RETA_GROUP_SIZE;
3551                 shift = i % RTE_RETA_GROUP_SIZE;
3552                 if (reta_conf[idx].mask & (1ULL << shift))
3553                         reta_conf[idx].reta[shift] = lut[i];
3554         }
3555
3556 out:
3557         rte_free(lut);
3558
3559         return ret;
3560 }
3561
3562 /**
3563  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3564  * @hw:   pointer to the HW structure
3565  * @mem:  pointer to mem struct to fill out
3566  * @size: size of memory requested
3567  * @alignment: what to align the allocation to
3568  **/
3569 enum i40e_status_code
3570 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3571                         struct i40e_dma_mem *mem,
3572                         u64 size,
3573                         u32 alignment)
3574 {
3575         const struct rte_memzone *mz = NULL;
3576         char z_name[RTE_MEMZONE_NAMESIZE];
3577
3578         if (!mem)
3579                 return I40E_ERR_PARAM;
3580
3581         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3582         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3583                                          alignment, RTE_PGSIZE_2M);
3584         if (!mz)
3585                 return I40E_ERR_NO_MEMORY;
3586
3587         mem->size = size;
3588         mem->va = mz->addr;
3589         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3590         mem->zone = (const void *)mz;
3591         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3592                     "%"PRIu64, mz->name, mem->pa);
3593
3594         return I40E_SUCCESS;
3595 }
3596
3597 /**
3598  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3599  * @hw:   pointer to the HW structure
3600  * @mem:  ptr to mem struct to free
3601  **/
3602 enum i40e_status_code
3603 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3604                     struct i40e_dma_mem *mem)
3605 {
3606         if (!mem)
3607                 return I40E_ERR_PARAM;
3608
3609         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3610                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3611                     mem->pa);
3612         rte_memzone_free((const struct rte_memzone *)mem->zone);
3613         mem->zone = NULL;
3614         mem->va = NULL;
3615         mem->pa = (u64)0;
3616
3617         return I40E_SUCCESS;
3618 }
3619
3620 /**
3621  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3622  * @hw:   pointer to the HW structure
3623  * @mem:  pointer to mem struct to fill out
3624  * @size: size of memory requested
3625  **/
3626 enum i40e_status_code
3627 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3628                          struct i40e_virt_mem *mem,
3629                          u32 size)
3630 {
3631         if (!mem)
3632                 return I40E_ERR_PARAM;
3633
3634         mem->size = size;
3635         mem->va = rte_zmalloc("i40e", size, 0);
3636
3637         if (mem->va)
3638                 return I40E_SUCCESS;
3639         else
3640                 return I40E_ERR_NO_MEMORY;
3641 }
3642
3643 /**
3644  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3645  * @hw:   pointer to the HW structure
3646  * @mem:  pointer to mem struct to free
3647  **/
3648 enum i40e_status_code
3649 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3650                      struct i40e_virt_mem *mem)
3651 {
3652         if (!mem)
3653                 return I40E_ERR_PARAM;
3654
3655         rte_free(mem->va);
3656         mem->va = NULL;
3657
3658         return I40E_SUCCESS;
3659 }
3660
3661 void
3662 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3663 {
3664         rte_spinlock_init(&sp->spinlock);
3665 }
3666
3667 void
3668 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3669 {
3670         rte_spinlock_lock(&sp->spinlock);
3671 }
3672
3673 void
3674 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3675 {
3676         rte_spinlock_unlock(&sp->spinlock);
3677 }
3678
3679 void
3680 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3681 {
3682         return;
3683 }
3684
3685 /**
3686  * Get the hardware capabilities, which will be parsed
3687  * and saved into struct i40e_hw.
3688  */
3689 static int
3690 i40e_get_cap(struct i40e_hw *hw)
3691 {
3692         struct i40e_aqc_list_capabilities_element_resp *buf;
3693         uint16_t len, size = 0;
3694         int ret;
3695
3696         /* Calculate a huge enough buff for saving response data temporarily */
3697         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3698                                                 I40E_MAX_CAP_ELE_NUM;
3699         buf = rte_zmalloc("i40e", len, 0);
3700         if (!buf) {
3701                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3702                 return I40E_ERR_NO_MEMORY;
3703         }
3704
3705         /* Get, parse the capabilities and save it to hw */
3706         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3707                         i40e_aqc_opc_list_func_capabilities, NULL);
3708         if (ret != I40E_SUCCESS)
3709                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3710
3711         /* Free the temporary buffer after being used */
3712         rte_free(buf);
3713
3714         return ret;
3715 }
3716
3717 static int
3718 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3719 {
3720         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3721         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3722         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3723         uint16_t qp_count = 0, vsi_count = 0;
3724
3725         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3726                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3727                 return -EINVAL;
3728         }
3729         /* Add the parameter init for LFC */
3730         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3731         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3732         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3733
3734         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3735         pf->max_num_vsi = hw->func_caps.num_vsis;
3736         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3737         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3738         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3739
3740         /* FDir queue/VSI allocation */
3741         pf->fdir_qp_offset = 0;
3742         if (hw->func_caps.fd) {
3743                 pf->flags |= I40E_FLAG_FDIR;
3744                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3745         } else {
3746                 pf->fdir_nb_qps = 0;
3747         }
3748         qp_count += pf->fdir_nb_qps;
3749         vsi_count += 1;
3750
3751         /* LAN queue/VSI allocation */
3752         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3753         if (!hw->func_caps.rss) {
3754                 pf->lan_nb_qps = 1;
3755         } else {
3756                 pf->flags |= I40E_FLAG_RSS;
3757                 if (hw->mac.type == I40E_MAC_X722)
3758                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3759                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3760         }
3761         qp_count += pf->lan_nb_qps;
3762         vsi_count += 1;
3763
3764         /* VF queue/VSI allocation */
3765         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3766         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3767                 pf->flags |= I40E_FLAG_SRIOV;
3768                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3769                 pf->vf_num = pci_dev->max_vfs;
3770                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3771                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3772                             pf->vf_nb_qps * pf->vf_num);
3773         } else {
3774                 pf->vf_nb_qps = 0;
3775                 pf->vf_num = 0;
3776         }
3777         qp_count += pf->vf_nb_qps * pf->vf_num;
3778         vsi_count += pf->vf_num;
3779
3780         /* VMDq queue/VSI allocation */
3781         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3782         pf->vmdq_nb_qps = 0;
3783         pf->max_nb_vmdq_vsi = 0;
3784         if (hw->func_caps.vmdq) {
3785                 if (qp_count < hw->func_caps.num_tx_qp &&
3786                         vsi_count < hw->func_caps.num_vsis) {
3787                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3788                                 qp_count) / pf->vmdq_nb_qp_max;
3789
3790                         /* Limit the maximum number of VMDq vsi to the maximum
3791                          * ethdev can support
3792                          */
3793                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3794                                 hw->func_caps.num_vsis - vsi_count);
3795                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3796                                 ETH_64_POOLS);
3797                         if (pf->max_nb_vmdq_vsi) {
3798                                 pf->flags |= I40E_FLAG_VMDQ;
3799                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3800                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3801                                             "per VMDQ VSI, in total %u queues",
3802                                             pf->max_nb_vmdq_vsi,
3803                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3804                                             pf->max_nb_vmdq_vsi);
3805                         } else {
3806                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3807                                             "VMDq");
3808                         }
3809                 } else {
3810                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3811                 }
3812         }
3813         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3814         vsi_count += pf->max_nb_vmdq_vsi;
3815
3816         if (hw->func_caps.dcb)
3817                 pf->flags |= I40E_FLAG_DCB;
3818
3819         if (qp_count > hw->func_caps.num_tx_qp) {
3820                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3821                             "the hardware maximum %u", qp_count,
3822                             hw->func_caps.num_tx_qp);
3823                 return -EINVAL;
3824         }
3825         if (vsi_count > hw->func_caps.num_vsis) {
3826                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3827                             "the hardware maximum %u", vsi_count,
3828                             hw->func_caps.num_vsis);
3829                 return -EINVAL;
3830         }
3831
3832         return 0;
3833 }
3834
3835 static int
3836 i40e_pf_get_switch_config(struct i40e_pf *pf)
3837 {
3838         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3839         struct i40e_aqc_get_switch_config_resp *switch_config;
3840         struct i40e_aqc_switch_config_element_resp *element;
3841         uint16_t start_seid = 0, num_reported;
3842         int ret;
3843
3844         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3845                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3846         if (!switch_config) {
3847                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3848                 return -ENOMEM;
3849         }
3850
3851         /* Get the switch configurations */
3852         ret = i40e_aq_get_switch_config(hw, switch_config,
3853                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3854         if (ret != I40E_SUCCESS) {
3855                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3856                 goto fail;
3857         }
3858         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3859         if (num_reported != 1) { /* The number should be 1 */
3860                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3861                 goto fail;
3862         }
3863
3864         /* Parse the switch configuration elements */
3865         element = &(switch_config->element[0]);
3866         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3867                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3868                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3869         } else
3870                 PMD_DRV_LOG(INFO, "Unknown element type");
3871
3872 fail:
3873         rte_free(switch_config);
3874
3875         return ret;
3876 }
3877
3878 static int
3879 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3880                         uint32_t num)
3881 {
3882         struct pool_entry *entry;
3883
3884         if (pool == NULL || num == 0)
3885                 return -EINVAL;
3886
3887         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3888         if (entry == NULL) {
3889                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3890                 return -ENOMEM;
3891         }
3892
3893         /* queue heap initialize */
3894         pool->num_free = num;
3895         pool->num_alloc = 0;
3896         pool->base = base;
3897         LIST_INIT(&pool->alloc_list);
3898         LIST_INIT(&pool->free_list);
3899
3900         /* Initialize element  */
3901         entry->base = 0;
3902         entry->len = num;
3903
3904         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3905         return 0;
3906 }
3907
3908 static void
3909 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3910 {
3911         struct pool_entry *entry, *next_entry;
3912
3913         if (pool == NULL)
3914                 return;
3915
3916         for (entry = LIST_FIRST(&pool->alloc_list);
3917                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3918                         entry = next_entry) {
3919                 LIST_REMOVE(entry, next);
3920                 rte_free(entry);
3921         }
3922
3923         for (entry = LIST_FIRST(&pool->free_list);
3924                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3925                         entry = next_entry) {
3926                 LIST_REMOVE(entry, next);
3927                 rte_free(entry);
3928         }
3929
3930         pool->num_free = 0;
3931         pool->num_alloc = 0;
3932         pool->base = 0;
3933         LIST_INIT(&pool->alloc_list);
3934         LIST_INIT(&pool->free_list);
3935 }
3936
3937 static int
3938 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3939                        uint32_t base)
3940 {
3941         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3942         uint32_t pool_offset;
3943         int insert;
3944
3945         if (pool == NULL) {
3946                 PMD_DRV_LOG(ERR, "Invalid parameter");
3947                 return -EINVAL;
3948         }
3949
3950         pool_offset = base - pool->base;
3951         /* Lookup in alloc list */
3952         LIST_FOREACH(entry, &pool->alloc_list, next) {
3953                 if (entry->base == pool_offset) {
3954                         valid_entry = entry;
3955                         LIST_REMOVE(entry, next);
3956                         break;
3957                 }
3958         }
3959
3960         /* Not find, return */
3961         if (valid_entry == NULL) {
3962                 PMD_DRV_LOG(ERR, "Failed to find entry");
3963                 return -EINVAL;
3964         }
3965
3966         /**
3967          * Found it, move it to free list  and try to merge.
3968          * In order to make merge easier, always sort it by qbase.
3969          * Find adjacent prev and last entries.
3970          */
3971         prev = next = NULL;
3972         LIST_FOREACH(entry, &pool->free_list, next) {
3973                 if (entry->base > valid_entry->base) {
3974                         next = entry;
3975                         break;
3976                 }
3977                 prev = entry;
3978         }
3979
3980         insert = 0;
3981         /* Try to merge with next one*/
3982         if (next != NULL) {
3983                 /* Merge with next one */
3984                 if (valid_entry->base + valid_entry->len == next->base) {
3985                         next->base = valid_entry->base;
3986                         next->len += valid_entry->len;
3987                         rte_free(valid_entry);
3988                         valid_entry = next;
3989                         insert = 1;
3990                 }
3991         }
3992
3993         if (prev != NULL) {
3994                 /* Merge with previous one */
3995                 if (prev->base + prev->len == valid_entry->base) {
3996                         prev->len += valid_entry->len;
3997                         /* If it merge with next one, remove next node */
3998                         if (insert == 1) {
3999                                 LIST_REMOVE(valid_entry, next);
4000                                 rte_free(valid_entry);
4001                         } else {
4002                                 rte_free(valid_entry);
4003                                 insert = 1;
4004                         }
4005                 }
4006         }
4007
4008         /* Not find any entry to merge, insert */
4009         if (insert == 0) {
4010                 if (prev != NULL)
4011                         LIST_INSERT_AFTER(prev, valid_entry, next);
4012                 else if (next != NULL)
4013                         LIST_INSERT_BEFORE(next, valid_entry, next);
4014                 else /* It's empty list, insert to head */
4015                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4016         }
4017
4018         pool->num_free += valid_entry->len;
4019         pool->num_alloc -= valid_entry->len;
4020
4021         return 0;
4022 }
4023
4024 static int
4025 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4026                        uint16_t num)
4027 {
4028         struct pool_entry *entry, *valid_entry;
4029
4030         if (pool == NULL || num == 0) {
4031                 PMD_DRV_LOG(ERR, "Invalid parameter");
4032                 return -EINVAL;
4033         }
4034
4035         if (pool->num_free < num) {
4036                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4037                             num, pool->num_free);
4038                 return -ENOMEM;
4039         }
4040
4041         valid_entry = NULL;
4042         /* Lookup  in free list and find most fit one */
4043         LIST_FOREACH(entry, &pool->free_list, next) {
4044                 if (entry->len >= num) {
4045                         /* Find best one */
4046                         if (entry->len == num) {
4047                                 valid_entry = entry;
4048                                 break;
4049                         }
4050                         if (valid_entry == NULL || valid_entry->len > entry->len)
4051                                 valid_entry = entry;
4052                 }
4053         }
4054
4055         /* Not find one to satisfy the request, return */
4056         if (valid_entry == NULL) {
4057                 PMD_DRV_LOG(ERR, "No valid entry found");
4058                 return -ENOMEM;
4059         }
4060         /**
4061          * The entry have equal queue number as requested,
4062          * remove it from alloc_list.
4063          */
4064         if (valid_entry->len == num) {
4065                 LIST_REMOVE(valid_entry, next);
4066         } else {
4067                 /**
4068                  * The entry have more numbers than requested,
4069                  * create a new entry for alloc_list and minus its
4070                  * queue base and number in free_list.
4071                  */
4072                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4073                 if (entry == NULL) {
4074                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
4075                                     "resource pool");
4076                         return -ENOMEM;
4077                 }
4078                 entry->base = valid_entry->base;
4079                 entry->len = num;
4080                 valid_entry->base += num;
4081                 valid_entry->len -= num;
4082                 valid_entry = entry;
4083         }
4084
4085         /* Insert it into alloc list, not sorted */
4086         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4087
4088         pool->num_free -= valid_entry->len;
4089         pool->num_alloc += valid_entry->len;
4090
4091         return valid_entry->base + pool->base;
4092 }
4093
4094 /**
4095  * bitmap_is_subset - Check whether src2 is subset of src1
4096  **/
4097 static inline int
4098 bitmap_is_subset(uint8_t src1, uint8_t src2)
4099 {
4100         return !((src1 ^ src2) & src2);
4101 }
4102
4103 static enum i40e_status_code
4104 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4105 {
4106         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4107
4108         /* If DCB is not supported, only default TC is supported */
4109         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4110                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4111                 return I40E_NOT_SUPPORTED;
4112         }
4113
4114         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4115                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
4116                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
4117                             enabled_tcmap);
4118                 return I40E_NOT_SUPPORTED;
4119         }
4120         return I40E_SUCCESS;
4121 }
4122
4123 int
4124 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4125                                 struct i40e_vsi_vlan_pvid_info *info)
4126 {
4127         struct i40e_hw *hw;
4128         struct i40e_vsi_context ctxt;
4129         uint8_t vlan_flags = 0;
4130         int ret;
4131
4132         if (vsi == NULL || info == NULL) {
4133                 PMD_DRV_LOG(ERR, "invalid parameters");
4134                 return I40E_ERR_PARAM;
4135         }
4136
4137         if (info->on) {
4138                 vsi->info.pvid = info->config.pvid;
4139                 /**
4140                  * If insert pvid is enabled, only tagged pkts are
4141                  * allowed to be sent out.
4142                  */
4143                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4144                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4145         } else {
4146                 vsi->info.pvid = 0;
4147                 if (info->config.reject.tagged == 0)
4148                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4149
4150                 if (info->config.reject.untagged == 0)
4151                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4152         }
4153         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4154                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4155         vsi->info.port_vlan_flags |= vlan_flags;
4156         vsi->info.valid_sections =
4157                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4158         memset(&ctxt, 0, sizeof(ctxt));
4159         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4160         ctxt.seid = vsi->seid;
4161
4162         hw = I40E_VSI_TO_HW(vsi);
4163         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4164         if (ret != I40E_SUCCESS)
4165                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4166
4167         return ret;
4168 }
4169
4170 static int
4171 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4172 {
4173         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4174         int i, ret;
4175         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4176
4177         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4178         if (ret != I40E_SUCCESS)
4179                 return ret;
4180
4181         if (!vsi->seid) {
4182                 PMD_DRV_LOG(ERR, "seid not valid");
4183                 return -EINVAL;
4184         }
4185
4186         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4187         tc_bw_data.tc_valid_bits = enabled_tcmap;
4188         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4189                 tc_bw_data.tc_bw_credits[i] =
4190                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4191
4192         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4193         if (ret != I40E_SUCCESS) {
4194                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4195                 return ret;
4196         }
4197
4198         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4199                                         sizeof(vsi->info.qs_handle));
4200         return I40E_SUCCESS;
4201 }
4202
4203 static enum i40e_status_code
4204 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4205                                  struct i40e_aqc_vsi_properties_data *info,
4206                                  uint8_t enabled_tcmap)
4207 {
4208         enum i40e_status_code ret;
4209         int i, total_tc = 0;
4210         uint16_t qpnum_per_tc, bsf, qp_idx;
4211
4212         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4213         if (ret != I40E_SUCCESS)
4214                 return ret;
4215
4216         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4217                 if (enabled_tcmap & (1 << i))
4218                         total_tc++;
4219         vsi->enabled_tc = enabled_tcmap;
4220
4221         /* Number of queues per enabled TC */
4222         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4223         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4224         bsf = rte_bsf32(qpnum_per_tc);
4225
4226         /* Adjust the queue number to actual queues that can be applied */
4227         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4228                 vsi->nb_qps = qpnum_per_tc * total_tc;
4229
4230         /**
4231          * Configure TC and queue mapping parameters, for enabled TC,
4232          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4233          * default queue will serve it.
4234          */
4235         qp_idx = 0;
4236         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4237                 if (vsi->enabled_tc & (1 << i)) {
4238                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4239                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4240                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4241                         qp_idx += qpnum_per_tc;
4242                 } else
4243                         info->tc_mapping[i] = 0;
4244         }
4245
4246         /* Associate queue number with VSI */
4247         if (vsi->type == I40E_VSI_SRIOV) {
4248                 info->mapping_flags |=
4249                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4250                 for (i = 0; i < vsi->nb_qps; i++)
4251                         info->queue_mapping[i] =
4252                                 rte_cpu_to_le_16(vsi->base_queue + i);
4253         } else {
4254                 info->mapping_flags |=
4255                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4256                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4257         }
4258         info->valid_sections |=
4259                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4260
4261         return I40E_SUCCESS;
4262 }
4263
4264 static int
4265 i40e_veb_release(struct i40e_veb *veb)
4266 {
4267         struct i40e_vsi *vsi;
4268         struct i40e_hw *hw;
4269
4270         if (veb == NULL)
4271                 return -EINVAL;
4272
4273         if (!TAILQ_EMPTY(&veb->head)) {
4274                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4275                 return -EACCES;
4276         }
4277         /* associate_vsi field is NULL for floating VEB */
4278         if (veb->associate_vsi != NULL) {
4279                 vsi = veb->associate_vsi;
4280                 hw = I40E_VSI_TO_HW(vsi);
4281
4282                 vsi->uplink_seid = veb->uplink_seid;
4283                 vsi->veb = NULL;
4284         } else {
4285                 veb->associate_pf->main_vsi->floating_veb = NULL;
4286                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4287         }
4288
4289         i40e_aq_delete_element(hw, veb->seid, NULL);
4290         rte_free(veb);
4291         return I40E_SUCCESS;
4292 }
4293
4294 /* Setup a veb */
4295 static struct i40e_veb *
4296 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4297 {
4298         struct i40e_veb *veb;
4299         int ret;
4300         struct i40e_hw *hw;
4301
4302         if (pf == NULL) {
4303                 PMD_DRV_LOG(ERR,
4304                             "veb setup failed, associated PF shouldn't null");
4305                 return NULL;
4306         }
4307         hw = I40E_PF_TO_HW(pf);
4308
4309         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4310         if (!veb) {
4311                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4312                 goto fail;
4313         }
4314
4315         veb->associate_vsi = vsi;
4316         veb->associate_pf = pf;
4317         TAILQ_INIT(&veb->head);
4318         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4319
4320         /* create floating veb if vsi is NULL */
4321         if (vsi != NULL) {
4322                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4323                                       I40E_DEFAULT_TCMAP, false,
4324                                       &veb->seid, false, NULL);
4325         } else {
4326                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4327                                       true, &veb->seid, false, NULL);
4328         }
4329
4330         if (ret != I40E_SUCCESS) {
4331                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4332                             hw->aq.asq_last_status);
4333                 goto fail;
4334         }
4335
4336         /* get statistics index */
4337         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4338                                 &veb->stats_idx, NULL, NULL, NULL);
4339         if (ret != I40E_SUCCESS) {
4340                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4341                             hw->aq.asq_last_status);
4342                 goto fail;
4343         }
4344         /* Get VEB bandwidth, to be implemented */
4345         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4346         if (vsi)
4347                 vsi->uplink_seid = veb->seid;
4348
4349         return veb;
4350 fail:
4351         rte_free(veb);
4352         return NULL;
4353 }
4354
4355 int
4356 i40e_vsi_release(struct i40e_vsi *vsi)
4357 {
4358         struct i40e_pf *pf;
4359         struct i40e_hw *hw;
4360         struct i40e_vsi_list *vsi_list;
4361         void *temp;
4362         int ret;
4363         struct i40e_mac_filter *f;
4364         uint16_t user_param;
4365
4366         if (!vsi)
4367                 return I40E_SUCCESS;
4368
4369         user_param = vsi->user_param;
4370
4371         pf = I40E_VSI_TO_PF(vsi);
4372         hw = I40E_VSI_TO_HW(vsi);
4373
4374         /* VSI has child to attach, release child first */
4375         if (vsi->veb) {
4376                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4377                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4378                                 return -1;
4379                 }
4380                 i40e_veb_release(vsi->veb);
4381         }
4382
4383         if (vsi->floating_veb) {
4384                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4385                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4386                                 return -1;
4387                 }
4388         }
4389
4390         /* Remove all macvlan filters of the VSI */
4391         i40e_vsi_remove_all_macvlan_filter(vsi);
4392         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4393                 rte_free(f);
4394
4395         if (vsi->type != I40E_VSI_MAIN &&
4396             ((vsi->type != I40E_VSI_SRIOV) ||
4397             !pf->floating_veb_list[user_param])) {
4398                 /* Remove vsi from parent's sibling list */
4399                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4400                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4401                         return I40E_ERR_PARAM;
4402                 }
4403                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4404                                 &vsi->sib_vsi_list, list);
4405
4406                 /* Remove all switch element of the VSI */
4407                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4408                 if (ret != I40E_SUCCESS)
4409                         PMD_DRV_LOG(ERR, "Failed to delete element");
4410         }
4411
4412         if ((vsi->type == I40E_VSI_SRIOV) &&
4413             pf->floating_veb_list[user_param]) {
4414                 /* Remove vsi from parent's sibling list */
4415                 if (vsi->parent_vsi == NULL ||
4416                     vsi->parent_vsi->floating_veb == NULL) {
4417                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4418                         return I40E_ERR_PARAM;
4419                 }
4420                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4421                              &vsi->sib_vsi_list, list);
4422
4423                 /* Remove all switch element of the VSI */
4424                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4425                 if (ret != I40E_SUCCESS)
4426                         PMD_DRV_LOG(ERR, "Failed to delete element");
4427         }
4428
4429         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4430
4431         if (vsi->type != I40E_VSI_SRIOV)
4432                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4433         rte_free(vsi);
4434
4435         return I40E_SUCCESS;
4436 }
4437
4438 static int
4439 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4440 {
4441         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4442         struct i40e_aqc_remove_macvlan_element_data def_filter;
4443         struct i40e_mac_filter_info filter;
4444         int ret;
4445
4446         if (vsi->type != I40E_VSI_MAIN)
4447                 return I40E_ERR_CONFIG;
4448         memset(&def_filter, 0, sizeof(def_filter));
4449         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4450                                         ETH_ADDR_LEN);
4451         def_filter.vlan_tag = 0;
4452         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4453                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4454         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4455         if (ret != I40E_SUCCESS) {
4456                 struct i40e_mac_filter *f;
4457                 struct ether_addr *mac;
4458
4459                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4460                             "macvlan filter");
4461                 /* It needs to add the permanent mac into mac list */
4462                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4463                 if (f == NULL) {
4464                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4465                         return I40E_ERR_NO_MEMORY;
4466                 }
4467                 mac = &f->mac_info.mac_addr;
4468                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4469                                 ETH_ADDR_LEN);
4470                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4471                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4472                 vsi->mac_num++;
4473
4474                 return ret;
4475         }
4476         (void)rte_memcpy(&filter.mac_addr,
4477                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4478         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4479         return i40e_vsi_add_mac(vsi, &filter);
4480 }
4481
4482 /*
4483  * i40e_vsi_get_bw_config - Query VSI BW Information
4484  * @vsi: the VSI to be queried
4485  *
4486  * Returns 0 on success, negative value on failure
4487  */
4488 static enum i40e_status_code
4489 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4490 {
4491         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4492         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4493         struct i40e_hw *hw = &vsi->adapter->hw;
4494         i40e_status ret;
4495         int i;
4496         uint32_t bw_max;
4497
4498         memset(&bw_config, 0, sizeof(bw_config));
4499         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4500         if (ret != I40E_SUCCESS) {
4501                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4502                             hw->aq.asq_last_status);
4503                 return ret;
4504         }
4505
4506         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4507         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4508                                         &ets_sla_config, NULL);
4509         if (ret != I40E_SUCCESS) {
4510                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4511                             "configuration %u", hw->aq.asq_last_status);
4512                 return ret;
4513         }
4514
4515         /* store and print out BW info */
4516         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4517         vsi->bw_info.bw_max = bw_config.max_bw;
4518         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4519         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4520         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4521                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4522                      I40E_16_BIT_WIDTH);
4523         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4524                 vsi->bw_info.bw_ets_share_credits[i] =
4525                                 ets_sla_config.share_credits[i];
4526                 vsi->bw_info.bw_ets_credits[i] =
4527                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4528                 /* 4 bits per TC, 4th bit is reserved */
4529                 vsi->bw_info.bw_ets_max[i] =
4530                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4531                                   RTE_LEN2MASK(3, uint8_t));
4532                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4533                             vsi->bw_info.bw_ets_share_credits[i]);
4534                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4535                             vsi->bw_info.bw_ets_credits[i]);
4536                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4537                             vsi->bw_info.bw_ets_max[i]);
4538         }
4539
4540         return I40E_SUCCESS;
4541 }
4542
4543 /* i40e_enable_pf_lb
4544  * @pf: pointer to the pf structure
4545  *
4546  * allow loopback on pf
4547  */
4548 static inline void
4549 i40e_enable_pf_lb(struct i40e_pf *pf)
4550 {
4551         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4552         struct i40e_vsi_context ctxt;
4553         int ret;
4554
4555         /* Use the FW API if FW >= v5.0 */
4556         if (hw->aq.fw_maj_ver < 5) {
4557                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4558                 return;
4559         }
4560
4561         memset(&ctxt, 0, sizeof(ctxt));
4562         ctxt.seid = pf->main_vsi_seid;
4563         ctxt.pf_num = hw->pf_id;
4564         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4565         if (ret) {
4566                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4567                             ret, hw->aq.asq_last_status);
4568                 return;
4569         }
4570         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4571         ctxt.info.valid_sections =
4572                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4573         ctxt.info.switch_id |=
4574                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4575
4576         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4577         if (ret)
4578                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4579                             hw->aq.asq_last_status);
4580 }
4581
4582 /* Setup a VSI */
4583 struct i40e_vsi *
4584 i40e_vsi_setup(struct i40e_pf *pf,
4585                enum i40e_vsi_type type,
4586                struct i40e_vsi *uplink_vsi,
4587                uint16_t user_param)
4588 {
4589         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4590         struct i40e_vsi *vsi;
4591         struct i40e_mac_filter_info filter;
4592         int ret;
4593         struct i40e_vsi_context ctxt;
4594         struct ether_addr broadcast =
4595                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4596
4597         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4598             uplink_vsi == NULL) {
4599                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4600                             "VSI link shouldn't be NULL");
4601                 return NULL;
4602         }
4603
4604         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4605                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4606                             "uplink VSI should be NULL");
4607                 return NULL;
4608         }
4609
4610         /* two situations
4611          * 1.type is not MAIN and uplink vsi is not NULL
4612          * If uplink vsi didn't setup VEB, create one first under veb field
4613          * 2.type is SRIOV and the uplink is NULL
4614          * If floating VEB is NULL, create one veb under floating veb field
4615          */
4616
4617         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4618             uplink_vsi->veb == NULL) {
4619                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4620
4621                 if (uplink_vsi->veb == NULL) {
4622                         PMD_DRV_LOG(ERR, "VEB setup failed");
4623                         return NULL;
4624                 }
4625                 /* set ALLOWLOOPBACk on pf, when veb is created */
4626                 i40e_enable_pf_lb(pf);
4627         }
4628
4629         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4630             pf->main_vsi->floating_veb == NULL) {
4631                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4632
4633                 if (pf->main_vsi->floating_veb == NULL) {
4634                         PMD_DRV_LOG(ERR, "VEB setup failed");
4635                         return NULL;
4636                 }
4637         }
4638
4639         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4640         if (!vsi) {
4641                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4642                 return NULL;
4643         }
4644         TAILQ_INIT(&vsi->mac_list);
4645         vsi->type = type;
4646         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4647         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4648         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4649         vsi->user_param = user_param;
4650         /* Allocate queues */
4651         switch (vsi->type) {
4652         case I40E_VSI_MAIN  :
4653                 vsi->nb_qps = pf->lan_nb_qps;
4654                 break;
4655         case I40E_VSI_SRIOV :
4656                 vsi->nb_qps = pf->vf_nb_qps;
4657                 break;
4658         case I40E_VSI_VMDQ2:
4659                 vsi->nb_qps = pf->vmdq_nb_qps;
4660                 break;
4661         case I40E_VSI_FDIR:
4662                 vsi->nb_qps = pf->fdir_nb_qps;
4663                 break;
4664         default:
4665                 goto fail_mem;
4666         }
4667         /*
4668          * The filter status descriptor is reported in rx queue 0,
4669          * while the tx queue for fdir filter programming has no
4670          * such constraints, can be non-zero queues.
4671          * To simplify it, choose FDIR vsi use queue 0 pair.
4672          * To make sure it will use queue 0 pair, queue allocation
4673          * need be done before this function is called
4674          */
4675         if (type != I40E_VSI_FDIR) {
4676                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4677                         if (ret < 0) {
4678                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4679                                                 vsi->seid, ret);
4680                                 goto fail_mem;
4681                         }
4682                         vsi->base_queue = ret;
4683         } else
4684                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4685
4686         /* VF has MSIX interrupt in VF range, don't allocate here */
4687         if (type == I40E_VSI_MAIN) {
4688                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4689                                           RTE_MIN(vsi->nb_qps,
4690                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4691                 if (ret < 0) {
4692                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4693                                     vsi->seid, ret);
4694                         goto fail_queue_alloc;
4695                 }
4696                 vsi->msix_intr = ret;
4697                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4698         } else if (type != I40E_VSI_SRIOV) {
4699                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4700                 if (ret < 0) {
4701                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4702                         goto fail_queue_alloc;
4703                 }
4704                 vsi->msix_intr = ret;
4705                 vsi->nb_msix = 1;
4706         } else {
4707                 vsi->msix_intr = 0;
4708                 vsi->nb_msix = 0;
4709         }
4710
4711         /* Add VSI */
4712         if (type == I40E_VSI_MAIN) {
4713                 /* For main VSI, no need to add since it's default one */
4714                 vsi->uplink_seid = pf->mac_seid;
4715                 vsi->seid = pf->main_vsi_seid;
4716                 /* Bind queues with specific MSIX interrupt */
4717                 /**
4718                  * Needs 2 interrupt at least, one for misc cause which will
4719                  * enabled from OS side, Another for queues binding the
4720                  * interrupt from device side only.
4721                  */
4722
4723                 /* Get default VSI parameters from hardware */
4724                 memset(&ctxt, 0, sizeof(ctxt));
4725                 ctxt.seid = vsi->seid;
4726                 ctxt.pf_num = hw->pf_id;
4727                 ctxt.uplink_seid = vsi->uplink_seid;
4728                 ctxt.vf_num = 0;
4729                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4730                 if (ret != I40E_SUCCESS) {
4731                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4732                         goto fail_msix_alloc;
4733                 }
4734                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4735                         sizeof(struct i40e_aqc_vsi_properties_data));
4736                 vsi->vsi_id = ctxt.vsi_number;
4737                 vsi->info.valid_sections = 0;
4738
4739                 /* Configure tc, enabled TC0 only */
4740                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4741                         I40E_SUCCESS) {
4742                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4743                         goto fail_msix_alloc;
4744                 }
4745
4746                 /* TC, queue mapping */
4747                 memset(&ctxt, 0, sizeof(ctxt));
4748                 vsi->info.valid_sections |=
4749                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4750                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4751                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4752                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4753                         sizeof(struct i40e_aqc_vsi_properties_data));
4754                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4755                                                 I40E_DEFAULT_TCMAP);
4756                 if (ret != I40E_SUCCESS) {
4757                         PMD_DRV_LOG(ERR, "Failed to configure "
4758                                     "TC queue mapping");
4759                         goto fail_msix_alloc;
4760                 }
4761                 ctxt.seid = vsi->seid;
4762                 ctxt.pf_num = hw->pf_id;
4763                 ctxt.uplink_seid = vsi->uplink_seid;
4764                 ctxt.vf_num = 0;
4765
4766                 /* Update VSI parameters */
4767                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4768                 if (ret != I40E_SUCCESS) {
4769                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4770                         goto fail_msix_alloc;
4771                 }
4772
4773                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4774                                                 sizeof(vsi->info.tc_mapping));
4775                 (void)rte_memcpy(&vsi->info.queue_mapping,
4776                                 &ctxt.info.queue_mapping,
4777                         sizeof(vsi->info.queue_mapping));
4778                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4779                 vsi->info.valid_sections = 0;
4780
4781                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4782                                 ETH_ADDR_LEN);
4783
4784                 /**
4785                  * Updating default filter settings are necessary to prevent
4786                  * reception of tagged packets.
4787                  * Some old firmware configurations load a default macvlan
4788                  * filter which accepts both tagged and untagged packets.
4789                  * The updating is to use a normal filter instead if needed.
4790                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4791                  * The firmware with correct configurations load the default
4792                  * macvlan filter which is expected and cannot be removed.
4793                  */
4794                 i40e_update_default_filter_setting(vsi);
4795                 i40e_config_qinq(hw, vsi);
4796         } else if (type == I40E_VSI_SRIOV) {
4797                 memset(&ctxt, 0, sizeof(ctxt));
4798                 /**
4799                  * For other VSI, the uplink_seid equals to uplink VSI's
4800                  * uplink_seid since they share same VEB
4801                  */
4802                 if (uplink_vsi == NULL)
4803                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4804                 else
4805                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4806                 ctxt.pf_num = hw->pf_id;
4807                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4808                 ctxt.uplink_seid = vsi->uplink_seid;
4809                 ctxt.connection_type = 0x1;
4810                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4811
4812                 /* Use the VEB configuration if FW >= v5.0 */
4813                 if (hw->aq.fw_maj_ver >= 5) {
4814                         /* Configure switch ID */
4815                         ctxt.info.valid_sections |=
4816                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4817                         ctxt.info.switch_id =
4818                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4819                 }
4820
4821                 /* Configure port/vlan */
4822                 ctxt.info.valid_sections |=
4823                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4824                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4825                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4826                                                 I40E_DEFAULT_TCMAP);
4827                 if (ret != I40E_SUCCESS) {
4828                         PMD_DRV_LOG(ERR, "Failed to configure "
4829                                     "TC queue mapping");
4830                         goto fail_msix_alloc;
4831                 }
4832                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4833                 ctxt.info.valid_sections |=
4834                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4835                 /**
4836                  * Since VSI is not created yet, only configure parameter,
4837                  * will add vsi below.
4838                  */
4839
4840                 i40e_config_qinq(hw, vsi);
4841         } else if (type == I40E_VSI_VMDQ2) {
4842                 memset(&ctxt, 0, sizeof(ctxt));
4843                 /*
4844                  * For other VSI, the uplink_seid equals to uplink VSI's
4845                  * uplink_seid since they share same VEB
4846                  */
4847                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4848                 ctxt.pf_num = hw->pf_id;
4849                 ctxt.vf_num = 0;
4850                 ctxt.uplink_seid = vsi->uplink_seid;
4851                 ctxt.connection_type = 0x1;
4852                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4853
4854                 ctxt.info.valid_sections |=
4855                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4856                 /* user_param carries flag to enable loop back */
4857                 if (user_param) {
4858                         ctxt.info.switch_id =
4859                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4860                         ctxt.info.switch_id |=
4861                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4862                 }
4863
4864                 /* Configure port/vlan */
4865                 ctxt.info.valid_sections |=
4866                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4867                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4868                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4869                                                 I40E_DEFAULT_TCMAP);
4870                 if (ret != I40E_SUCCESS) {
4871                         PMD_DRV_LOG(ERR, "Failed to configure "
4872                                         "TC queue mapping");
4873                         goto fail_msix_alloc;
4874                 }
4875                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4876                 ctxt.info.valid_sections |=
4877                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4878         } else if (type == I40E_VSI_FDIR) {
4879                 memset(&ctxt, 0, sizeof(ctxt));
4880                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4881                 ctxt.pf_num = hw->pf_id;
4882                 ctxt.vf_num = 0;
4883                 ctxt.uplink_seid = vsi->uplink_seid;
4884                 ctxt.connection_type = 0x1;     /* regular data port */
4885                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4886                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4887                                                 I40E_DEFAULT_TCMAP);
4888                 if (ret != I40E_SUCCESS) {
4889                         PMD_DRV_LOG(ERR, "Failed to configure "
4890                                         "TC queue mapping.");
4891                         goto fail_msix_alloc;
4892                 }
4893                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4894                 ctxt.info.valid_sections |=
4895                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4896         } else {
4897                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4898                 goto fail_msix_alloc;
4899         }
4900
4901         if (vsi->type != I40E_VSI_MAIN) {
4902                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4903                 if (ret != I40E_SUCCESS) {
4904                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4905                                     hw->aq.asq_last_status);
4906                         goto fail_msix_alloc;
4907                 }
4908                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4909                 vsi->info.valid_sections = 0;
4910                 vsi->seid = ctxt.seid;
4911                 vsi->vsi_id = ctxt.vsi_number;
4912                 vsi->sib_vsi_list.vsi = vsi;
4913                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4914                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4915                                           &vsi->sib_vsi_list, list);
4916                 } else {
4917                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4918                                           &vsi->sib_vsi_list, list);
4919                 }
4920         }
4921
4922         /* MAC/VLAN configuration */
4923         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4924         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4925
4926         ret = i40e_vsi_add_mac(vsi, &filter);
4927         if (ret != I40E_SUCCESS) {
4928                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4929                 goto fail_msix_alloc;
4930         }
4931
4932         /* Get VSI BW information */
4933         i40e_vsi_get_bw_config(vsi);
4934         return vsi;
4935 fail_msix_alloc:
4936         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4937 fail_queue_alloc:
4938         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4939 fail_mem:
4940         rte_free(vsi);
4941         return NULL;
4942 }
4943
4944 /* Configure vlan filter on or off */
4945 int
4946 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4947 {
4948         int i, num;
4949         struct i40e_mac_filter *f;
4950         void *temp;
4951         struct i40e_mac_filter_info *mac_filter;
4952         enum rte_mac_filter_type desired_filter;
4953         int ret = I40E_SUCCESS;
4954
4955         if (on) {
4956                 /* Filter to match MAC and VLAN */
4957                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4958         } else {
4959                 /* Filter to match only MAC */
4960                 desired_filter = RTE_MAC_PERFECT_MATCH;
4961         }
4962
4963         num = vsi->mac_num;
4964
4965         mac_filter = rte_zmalloc("mac_filter_info_data",
4966                                  num * sizeof(*mac_filter), 0);
4967         if (mac_filter == NULL) {
4968                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4969                 return I40E_ERR_NO_MEMORY;
4970         }
4971
4972         i = 0;
4973
4974         /* Remove all existing mac */
4975         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4976                 mac_filter[i] = f->mac_info;
4977                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4978                 if (ret) {
4979                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4980                                     on ? "enable" : "disable");
4981                         goto DONE;
4982                 }
4983                 i++;
4984         }
4985
4986         /* Override with new filter */
4987         for (i = 0; i < num; i++) {
4988                 mac_filter[i].filter_type = desired_filter;
4989                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4990                 if (ret) {
4991                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4992                                     on ? "enable" : "disable");
4993                         goto DONE;
4994                 }
4995         }
4996
4997 DONE:
4998         rte_free(mac_filter);
4999         return ret;
5000 }
5001
5002 /* Configure vlan stripping on or off */
5003 int
5004 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5005 {
5006         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5007         struct i40e_vsi_context ctxt;
5008         uint8_t vlan_flags;
5009         int ret = I40E_SUCCESS;
5010
5011         /* Check if it has been already on or off */
5012         if (vsi->info.valid_sections &
5013                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5014                 if (on) {
5015                         if ((vsi->info.port_vlan_flags &
5016                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5017                                 return 0; /* already on */
5018                 } else {
5019                         if ((vsi->info.port_vlan_flags &
5020                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5021                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5022                                 return 0; /* already off */
5023                 }
5024         }
5025
5026         if (on)
5027                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5028         else
5029                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5030         vsi->info.valid_sections =
5031                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5032         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5033         vsi->info.port_vlan_flags |= vlan_flags;
5034         ctxt.seid = vsi->seid;
5035         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5036         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5037         if (ret)
5038                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5039                             on ? "enable" : "disable");
5040
5041         return ret;
5042 }
5043
5044 static int
5045 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5046 {
5047         struct rte_eth_dev_data *data = dev->data;
5048         int ret;
5049         int mask = 0;
5050
5051         /* Apply vlan offload setting */
5052         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5053         i40e_vlan_offload_set(dev, mask);
5054
5055         /* Apply double-vlan setting, not implemented yet */
5056
5057         /* Apply pvid setting */
5058         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5059                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5060         if (ret)
5061                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5062
5063         return ret;
5064 }
5065
5066 static int
5067 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5068 {
5069         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5070
5071         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5072 }
5073
5074 static int
5075 i40e_update_flow_control(struct i40e_hw *hw)
5076 {
5077 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5078         struct i40e_link_status link_status;
5079         uint32_t rxfc = 0, txfc = 0, reg;
5080         uint8_t an_info;
5081         int ret;
5082
5083         memset(&link_status, 0, sizeof(link_status));
5084         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5085         if (ret != I40E_SUCCESS) {
5086                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5087                 goto write_reg; /* Disable flow control */
5088         }
5089
5090         an_info = hw->phy.link_info.an_info;
5091         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5092                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5093                 ret = I40E_ERR_NOT_READY;
5094                 goto write_reg; /* Disable flow control */
5095         }
5096         /**
5097          * If link auto negotiation is enabled, flow control needs to
5098          * be configured according to it
5099          */
5100         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5101         case I40E_LINK_PAUSE_RXTX:
5102                 rxfc = 1;
5103                 txfc = 1;
5104                 hw->fc.current_mode = I40E_FC_FULL;
5105                 break;
5106         case I40E_AQ_LINK_PAUSE_RX:
5107                 rxfc = 1;
5108                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5109                 break;
5110         case I40E_AQ_LINK_PAUSE_TX:
5111                 txfc = 1;
5112                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5113                 break;
5114         default:
5115                 hw->fc.current_mode = I40E_FC_NONE;
5116                 break;
5117         }
5118
5119 write_reg:
5120         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5121                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5122         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5123         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5124         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5125         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5126
5127         return ret;
5128 }
5129
5130 /* PF setup */
5131 static int
5132 i40e_pf_setup(struct i40e_pf *pf)
5133 {
5134         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5135         struct i40e_filter_control_settings settings;
5136         struct i40e_vsi *vsi;
5137         int ret;
5138
5139         /* Clear all stats counters */
5140         pf->offset_loaded = FALSE;
5141         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5142         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5143
5144         ret = i40e_pf_get_switch_config(pf);
5145         if (ret != I40E_SUCCESS) {
5146                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5147                 return ret;
5148         }
5149         if (pf->flags & I40E_FLAG_FDIR) {
5150                 /* make queue allocated first, let FDIR use queue pair 0*/
5151                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5152                 if (ret != I40E_FDIR_QUEUE_ID) {
5153                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
5154                                     " ret =%d", ret);
5155                         pf->flags &= ~I40E_FLAG_FDIR;
5156                 }
5157         }
5158         /*  main VSI setup */
5159         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5160         if (!vsi) {
5161                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5162                 return I40E_ERR_NOT_READY;
5163         }
5164         pf->main_vsi = vsi;
5165
5166         /* Configure filter control */
5167         memset(&settings, 0, sizeof(settings));
5168         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5169                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5170         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5171                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5172         else {
5173                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
5174                                                 hw->func_caps.rss_table_size);
5175                 return I40E_ERR_PARAM;
5176         }
5177         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
5178                         "size: %u\n", hw->func_caps.rss_table_size);
5179         pf->hash_lut_size = hw->func_caps.rss_table_size;
5180
5181         /* Enable ethtype and macvlan filters */
5182         settings.enable_ethtype = TRUE;
5183         settings.enable_macvlan = TRUE;
5184         ret = i40e_set_filter_control(hw, &settings);
5185         if (ret)
5186                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5187                                                                 ret);
5188
5189         /* Update flow control according to the auto negotiation */
5190         i40e_update_flow_control(hw);
5191
5192         return I40E_SUCCESS;
5193 }
5194
5195 int
5196 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5197 {
5198         uint32_t reg;
5199         uint16_t j;
5200
5201         /**
5202          * Set or clear TX Queue Disable flags,
5203          * which is required by hardware.
5204          */
5205         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5206         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5207
5208         /* Wait until the request is finished */
5209         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5210                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5211                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5212                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5213                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5214                                                         & 0x1))) {
5215                         break;
5216                 }
5217         }
5218         if (on) {
5219                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5220                         return I40E_SUCCESS; /* already on, skip next steps */
5221
5222                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5223                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5224         } else {
5225                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5226                         return I40E_SUCCESS; /* already off, skip next steps */
5227                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5228         }
5229         /* Write the register */
5230         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5231         /* Check the result */
5232         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5233                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5234                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5235                 if (on) {
5236                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5237                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5238                                 break;
5239                 } else {
5240                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5241                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5242                                 break;
5243                 }
5244         }
5245         /* Check if it is timeout */
5246         if (j >= I40E_CHK_Q_ENA_COUNT) {
5247                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5248                             (on ? "enable" : "disable"), q_idx);
5249                 return I40E_ERR_TIMEOUT;
5250         }
5251
5252         return I40E_SUCCESS;
5253 }
5254
5255 /* Swith on or off the tx queues */
5256 static int
5257 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5258 {
5259         struct rte_eth_dev_data *dev_data = pf->dev_data;
5260         struct i40e_tx_queue *txq;
5261         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5262         uint16_t i;
5263         int ret;
5264
5265         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5266                 txq = dev_data->tx_queues[i];
5267                 /* Don't operate the queue if not configured or
5268                  * if starting only per queue */
5269                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5270                         continue;
5271                 if (on)
5272                         ret = i40e_dev_tx_queue_start(dev, i);
5273                 else
5274                         ret = i40e_dev_tx_queue_stop(dev, i);
5275                 if ( ret != I40E_SUCCESS)
5276                         return ret;
5277         }
5278
5279         return I40E_SUCCESS;
5280 }
5281
5282 int
5283 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5284 {
5285         uint32_t reg;
5286         uint16_t j;
5287
5288         /* Wait until the request is finished */
5289         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5290                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5291                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5292                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5293                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5294                         break;
5295         }
5296
5297         if (on) {
5298                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5299                         return I40E_SUCCESS; /* Already on, skip next steps */
5300                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5301         } else {
5302                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5303                         return I40E_SUCCESS; /* Already off, skip next steps */
5304                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5305         }
5306
5307         /* Write the register */
5308         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5309         /* Check the result */
5310         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5311                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5312                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5313                 if (on) {
5314                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5315                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5316                                 break;
5317                 } else {
5318                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5319                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5320                                 break;
5321                 }
5322         }
5323
5324         /* Check if it is timeout */
5325         if (j >= I40E_CHK_Q_ENA_COUNT) {
5326                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5327                             (on ? "enable" : "disable"), q_idx);
5328                 return I40E_ERR_TIMEOUT;
5329         }
5330
5331         return I40E_SUCCESS;
5332 }
5333 /* Switch on or off the rx queues */
5334 static int
5335 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5336 {
5337         struct rte_eth_dev_data *dev_data = pf->dev_data;
5338         struct i40e_rx_queue *rxq;
5339         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5340         uint16_t i;
5341         int ret;
5342
5343         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5344                 rxq = dev_data->rx_queues[i];
5345                 /* Don't operate the queue if not configured or
5346                  * if starting only per queue */
5347                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5348                         continue;
5349                 if (on)
5350                         ret = i40e_dev_rx_queue_start(dev, i);
5351                 else
5352                         ret = i40e_dev_rx_queue_stop(dev, i);
5353                 if (ret != I40E_SUCCESS)
5354                         return ret;
5355         }
5356
5357         return I40E_SUCCESS;
5358 }
5359
5360 /* Switch on or off all the rx/tx queues */
5361 int
5362 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5363 {
5364         int ret;
5365
5366         if (on) {
5367                 /* enable rx queues before enabling tx queues */
5368                 ret = i40e_dev_switch_rx_queues(pf, on);
5369                 if (ret) {
5370                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5371                         return ret;
5372                 }
5373                 ret = i40e_dev_switch_tx_queues(pf, on);
5374         } else {
5375                 /* Stop tx queues before stopping rx queues */
5376                 ret = i40e_dev_switch_tx_queues(pf, on);
5377                 if (ret) {
5378                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5379                         return ret;
5380                 }
5381                 ret = i40e_dev_switch_rx_queues(pf, on);
5382         }
5383
5384         return ret;
5385 }
5386
5387 /* Initialize VSI for TX */
5388 static int
5389 i40e_dev_tx_init(struct i40e_pf *pf)
5390 {
5391         struct rte_eth_dev_data *data = pf->dev_data;
5392         uint16_t i;
5393         uint32_t ret = I40E_SUCCESS;
5394         struct i40e_tx_queue *txq;
5395
5396         for (i = 0; i < data->nb_tx_queues; i++) {
5397                 txq = data->tx_queues[i];
5398                 if (!txq || !txq->q_set)
5399                         continue;
5400                 ret = i40e_tx_queue_init(txq);
5401                 if (ret != I40E_SUCCESS)
5402                         break;
5403         }
5404         if (ret == I40E_SUCCESS)
5405                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5406                                      ->eth_dev);
5407
5408         return ret;
5409 }
5410
5411 /* Initialize VSI for RX */
5412 static int
5413 i40e_dev_rx_init(struct i40e_pf *pf)
5414 {
5415         struct rte_eth_dev_data *data = pf->dev_data;
5416         int ret = I40E_SUCCESS;
5417         uint16_t i;
5418         struct i40e_rx_queue *rxq;
5419
5420         i40e_pf_config_mq_rx(pf);
5421         for (i = 0; i < data->nb_rx_queues; i++) {
5422                 rxq = data->rx_queues[i];
5423                 if (!rxq || !rxq->q_set)
5424                         continue;
5425
5426                 ret = i40e_rx_queue_init(rxq);
5427                 if (ret != I40E_SUCCESS) {
5428                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5429                                     "initialization");
5430                         break;
5431                 }
5432         }
5433         if (ret == I40E_SUCCESS)
5434                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5435                                      ->eth_dev);
5436
5437         return ret;
5438 }
5439
5440 static int
5441 i40e_dev_rxtx_init(struct i40e_pf *pf)
5442 {
5443         int err;
5444
5445         err = i40e_dev_tx_init(pf);
5446         if (err) {
5447                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5448                 return err;
5449         }
5450         err = i40e_dev_rx_init(pf);
5451         if (err) {
5452                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5453                 return err;
5454         }
5455
5456         return err;
5457 }
5458
5459 static int
5460 i40e_vmdq_setup(struct rte_eth_dev *dev)
5461 {
5462         struct rte_eth_conf *conf = &dev->data->dev_conf;
5463         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5464         int i, err, conf_vsis, j, loop;
5465         struct i40e_vsi *vsi;
5466         struct i40e_vmdq_info *vmdq_info;
5467         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5468         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5469
5470         /*
5471          * Disable interrupt to avoid message from VF. Furthermore, it will
5472          * avoid race condition in VSI creation/destroy.
5473          */
5474         i40e_pf_disable_irq0(hw);
5475
5476         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5477                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5478                 return -ENOTSUP;
5479         }
5480
5481         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5482         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5483                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5484                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5485                         pf->max_nb_vmdq_vsi);
5486                 return -ENOTSUP;
5487         }
5488
5489         if (pf->vmdq != NULL) {
5490                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5491                 return 0;
5492         }
5493
5494         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5495                                 sizeof(*vmdq_info) * conf_vsis, 0);
5496
5497         if (pf->vmdq == NULL) {
5498                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5499                 return -ENOMEM;
5500         }
5501
5502         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5503
5504         /* Create VMDQ VSI */
5505         for (i = 0; i < conf_vsis; i++) {
5506                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5507                                 vmdq_conf->enable_loop_back);
5508                 if (vsi == NULL) {
5509                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5510                         err = -1;
5511                         goto err_vsi_setup;
5512                 }
5513                 vmdq_info = &pf->vmdq[i];
5514                 vmdq_info->pf = pf;
5515                 vmdq_info->vsi = vsi;
5516         }
5517         pf->nb_cfg_vmdq_vsi = conf_vsis;
5518
5519         /* Configure Vlan */
5520         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5521         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5522                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5523                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5524                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5525                                         vmdq_conf->pool_map[i].vlan_id, j);
5526
5527                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5528                                                 vmdq_conf->pool_map[i].vlan_id);
5529                                 if (err) {
5530                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5531                                         err = -1;
5532                                         goto err_vsi_setup;
5533                                 }
5534                         }
5535                 }
5536         }
5537
5538         i40e_pf_enable_irq0(hw);
5539
5540         return 0;
5541
5542 err_vsi_setup:
5543         for (i = 0; i < conf_vsis; i++)
5544                 if (pf->vmdq[i].vsi == NULL)
5545                         break;
5546                 else
5547                         i40e_vsi_release(pf->vmdq[i].vsi);
5548
5549         rte_free(pf->vmdq);
5550         pf->vmdq = NULL;
5551         i40e_pf_enable_irq0(hw);
5552         return err;
5553 }
5554
5555 static void
5556 i40e_stat_update_32(struct i40e_hw *hw,
5557                    uint32_t reg,
5558                    bool offset_loaded,
5559                    uint64_t *offset,
5560                    uint64_t *stat)
5561 {
5562         uint64_t new_data;
5563
5564         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5565         if (!offset_loaded)
5566                 *offset = new_data;
5567
5568         if (new_data >= *offset)
5569                 *stat = (uint64_t)(new_data - *offset);
5570         else
5571                 *stat = (uint64_t)((new_data +
5572                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5573 }
5574
5575 static void
5576 i40e_stat_update_48(struct i40e_hw *hw,
5577                    uint32_t hireg,
5578                    uint32_t loreg,
5579                    bool offset_loaded,
5580                    uint64_t *offset,
5581                    uint64_t *stat)
5582 {
5583         uint64_t new_data;
5584
5585         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5586         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5587                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5588
5589         if (!offset_loaded)
5590                 *offset = new_data;
5591
5592         if (new_data >= *offset)
5593                 *stat = new_data - *offset;
5594         else
5595                 *stat = (uint64_t)((new_data +
5596                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5597
5598         *stat &= I40E_48_BIT_MASK;
5599 }
5600
5601 /* Disable IRQ0 */
5602 void
5603 i40e_pf_disable_irq0(struct i40e_hw *hw)
5604 {
5605         /* Disable all interrupt types */
5606         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5607         I40E_WRITE_FLUSH(hw);
5608 }
5609
5610 /* Enable IRQ0 */
5611 void
5612 i40e_pf_enable_irq0(struct i40e_hw *hw)
5613 {
5614         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5615                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5616                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5617                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5618         I40E_WRITE_FLUSH(hw);
5619 }
5620
5621 static void
5622 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5623 {
5624         /* read pending request and disable first */
5625         i40e_pf_disable_irq0(hw);
5626         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5627         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5628                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5629
5630         if (no_queue)
5631                 /* Link no queues with irq0 */
5632                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5633                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5634 }
5635
5636 static void
5637 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5638 {
5639         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5640         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5641         int i;
5642         uint16_t abs_vf_id;
5643         uint32_t index, offset, val;
5644
5645         if (!pf->vfs)
5646                 return;
5647         /**
5648          * Try to find which VF trigger a reset, use absolute VF id to access
5649          * since the reg is global register.
5650          */
5651         for (i = 0; i < pf->vf_num; i++) {
5652                 abs_vf_id = hw->func_caps.vf_base_id + i;
5653                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5654                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5655                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5656                 /* VFR event occured */
5657                 if (val & (0x1 << offset)) {
5658                         int ret;
5659
5660                         /* Clear the event first */
5661                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5662                                                         (0x1 << offset));
5663                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5664                         /**
5665                          * Only notify a VF reset event occured,
5666                          * don't trigger another SW reset
5667                          */
5668                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5669                         if (ret != I40E_SUCCESS)
5670                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5671                 }
5672         }
5673 }
5674
5675 static void
5676 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5677 {
5678         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5679         struct i40e_virtchnl_pf_event event;
5680         int i;
5681
5682         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5683         event.event_data.link_event.link_status =
5684                 dev->data->dev_link.link_status;
5685         event.event_data.link_event.link_speed =
5686                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5687
5688         for (i = 0; i < pf->vf_num; i++)
5689                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5690                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5691 }
5692
5693 static void
5694 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5695 {
5696         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5697         struct i40e_arq_event_info info;
5698         uint16_t pending, opcode;
5699         int ret;
5700
5701         info.buf_len = I40E_AQ_BUF_SZ;
5702         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5703         if (!info.msg_buf) {
5704                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5705                 return;
5706         }
5707
5708         pending = 1;
5709         while (pending) {
5710                 ret = i40e_clean_arq_element(hw, &info, &pending);
5711
5712                 if (ret != I40E_SUCCESS) {
5713                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5714                                     "aq_err: %u", hw->aq.asq_last_status);
5715                         break;
5716                 }
5717                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5718
5719                 switch (opcode) {
5720                 case i40e_aqc_opc_send_msg_to_pf:
5721                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5722                         i40e_pf_host_handle_vf_msg(dev,
5723                                         rte_le_to_cpu_16(info.desc.retval),
5724                                         rte_le_to_cpu_32(info.desc.cookie_high),
5725                                         rte_le_to_cpu_32(info.desc.cookie_low),
5726                                         info.msg_buf,
5727                                         info.msg_len);
5728                         break;
5729                 case i40e_aqc_opc_get_link_status:
5730                         ret = i40e_dev_link_update(dev, 0);
5731                         if (!ret) {
5732                                 i40e_notify_all_vfs_link_status(dev);
5733                                 _rte_eth_dev_callback_process(dev,
5734                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5735                         }
5736                         break;
5737                 default:
5738                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5739                                     opcode);
5740                         break;
5741                 }
5742         }
5743         rte_free(info.msg_buf);
5744 }
5745
5746 /**
5747  * Interrupt handler triggered by NIC  for handling
5748  * specific interrupt.
5749  *
5750  * @param handle
5751  *  Pointer to interrupt handle.
5752  * @param param
5753  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5754  *
5755  * @return
5756  *  void
5757  */
5758 static void
5759 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5760                            void *param)
5761 {
5762         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5763         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5764         uint32_t icr0;
5765
5766         /* Disable interrupt */
5767         i40e_pf_disable_irq0(hw);
5768
5769         /* read out interrupt causes */
5770         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5771
5772         /* No interrupt event indicated */
5773         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5774                 PMD_DRV_LOG(INFO, "No interrupt event");
5775                 goto done;
5776         }
5777 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5778         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5779                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5780         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5781                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5782         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5783                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5784         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5785                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5786         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5787                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5788         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5789                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5790         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5791                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5792 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5793
5794         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5795                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5796                 i40e_dev_handle_vfr_event(dev);
5797         }
5798         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5799                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5800                 i40e_dev_handle_aq_msg(dev);
5801         }
5802
5803 done:
5804         /* Enable interrupt */
5805         i40e_pf_enable_irq0(hw);
5806         rte_intr_enable(intr_handle);
5807 }
5808
5809 static int
5810 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5811                          struct i40e_macvlan_filter *filter,
5812                          int total)
5813 {
5814         int ele_num, ele_buff_size;
5815         int num, actual_num, i;
5816         uint16_t flags;
5817         int ret = I40E_SUCCESS;
5818         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5819         struct i40e_aqc_add_macvlan_element_data *req_list;
5820
5821         if (filter == NULL  || total == 0)
5822                 return I40E_ERR_PARAM;
5823         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5824         ele_buff_size = hw->aq.asq_buf_size;
5825
5826         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5827         if (req_list == NULL) {
5828                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5829                 return I40E_ERR_NO_MEMORY;
5830         }
5831
5832         num = 0;
5833         do {
5834                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5835                 memset(req_list, 0, ele_buff_size);
5836
5837                 for (i = 0; i < actual_num; i++) {
5838                         (void)rte_memcpy(req_list[i].mac_addr,
5839                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5840                         req_list[i].vlan_tag =
5841                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5842
5843                         switch (filter[num + i].filter_type) {
5844                         case RTE_MAC_PERFECT_MATCH:
5845                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5846                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5847                                 break;
5848                         case RTE_MACVLAN_PERFECT_MATCH:
5849                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5850                                 break;
5851                         case RTE_MAC_HASH_MATCH:
5852                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5853                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5854                                 break;
5855                         case RTE_MACVLAN_HASH_MATCH:
5856                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5857                                 break;
5858                         default:
5859                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5860                                 ret = I40E_ERR_PARAM;
5861                                 goto DONE;
5862                         }
5863
5864                         req_list[i].queue_number = 0;
5865
5866                         req_list[i].flags = rte_cpu_to_le_16(flags);
5867                 }
5868
5869                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5870                                                 actual_num, NULL);
5871                 if (ret != I40E_SUCCESS) {
5872                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5873                         goto DONE;
5874                 }
5875                 num += actual_num;
5876         } while (num < total);
5877
5878 DONE:
5879         rte_free(req_list);
5880         return ret;
5881 }
5882
5883 static int
5884 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5885                             struct i40e_macvlan_filter *filter,
5886                             int total)
5887 {
5888         int ele_num, ele_buff_size;
5889         int num, actual_num, i;
5890         uint16_t flags;
5891         int ret = I40E_SUCCESS;
5892         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5893         struct i40e_aqc_remove_macvlan_element_data *req_list;
5894
5895         if (filter == NULL  || total == 0)
5896                 return I40E_ERR_PARAM;
5897
5898         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5899         ele_buff_size = hw->aq.asq_buf_size;
5900
5901         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5902         if (req_list == NULL) {
5903                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5904                 return I40E_ERR_NO_MEMORY;
5905         }
5906
5907         num = 0;
5908         do {
5909                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5910                 memset(req_list, 0, ele_buff_size);
5911
5912                 for (i = 0; i < actual_num; i++) {
5913                         (void)rte_memcpy(req_list[i].mac_addr,
5914                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5915                         req_list[i].vlan_tag =
5916                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5917
5918                         switch (filter[num + i].filter_type) {
5919                         case RTE_MAC_PERFECT_MATCH:
5920                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5921                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5922                                 break;
5923                         case RTE_MACVLAN_PERFECT_MATCH:
5924                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5925                                 break;
5926                         case RTE_MAC_HASH_MATCH:
5927                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5928                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5929                                 break;
5930                         case RTE_MACVLAN_HASH_MATCH:
5931                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5932                                 break;
5933                         default:
5934                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5935                                 ret = I40E_ERR_PARAM;
5936                                 goto DONE;
5937                         }
5938                         req_list[i].flags = rte_cpu_to_le_16(flags);
5939                 }
5940
5941                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5942                                                 actual_num, NULL);
5943                 if (ret != I40E_SUCCESS) {
5944                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5945                         goto DONE;
5946                 }
5947                 num += actual_num;
5948         } while (num < total);
5949
5950 DONE:
5951         rte_free(req_list);
5952         return ret;
5953 }
5954
5955 /* Find out specific MAC filter */
5956 static struct i40e_mac_filter *
5957 i40e_find_mac_filter(struct i40e_vsi *vsi,
5958                          struct ether_addr *macaddr)
5959 {
5960         struct i40e_mac_filter *f;
5961
5962         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5963                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5964                         return f;
5965         }
5966
5967         return NULL;
5968 }
5969
5970 static bool
5971 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5972                          uint16_t vlan_id)
5973 {
5974         uint32_t vid_idx, vid_bit;
5975
5976         if (vlan_id > ETH_VLAN_ID_MAX)
5977                 return 0;
5978
5979         vid_idx = I40E_VFTA_IDX(vlan_id);
5980         vid_bit = I40E_VFTA_BIT(vlan_id);
5981
5982         if (vsi->vfta[vid_idx] & vid_bit)
5983                 return 1;
5984         else
5985                 return 0;
5986 }
5987
5988 static void
5989 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5990                          uint16_t vlan_id, bool on)
5991 {
5992         uint32_t vid_idx, vid_bit;
5993
5994         if (vlan_id > ETH_VLAN_ID_MAX)
5995                 return;
5996
5997         vid_idx = I40E_VFTA_IDX(vlan_id);
5998         vid_bit = I40E_VFTA_BIT(vlan_id);
5999
6000         if (on)
6001                 vsi->vfta[vid_idx] |= vid_bit;
6002         else
6003                 vsi->vfta[vid_idx] &= ~vid_bit;
6004 }
6005
6006 /**
6007  * Find all vlan options for specific mac addr,
6008  * return with actual vlan found.
6009  */
6010 static inline int
6011 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6012                            struct i40e_macvlan_filter *mv_f,
6013                            int num, struct ether_addr *addr)
6014 {
6015         int i;
6016         uint32_t j, k;
6017
6018         /**
6019          * Not to use i40e_find_vlan_filter to decrease the loop time,
6020          * although the code looks complex.
6021           */
6022         if (num < vsi->vlan_num)
6023                 return I40E_ERR_PARAM;
6024
6025         i = 0;
6026         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6027                 if (vsi->vfta[j]) {
6028                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6029                                 if (vsi->vfta[j] & (1 << k)) {
6030                                         if (i > num - 1) {
6031                                                 PMD_DRV_LOG(ERR, "vlan number "
6032                                                             "not match");
6033                                                 return I40E_ERR_PARAM;
6034                                         }
6035                                         (void)rte_memcpy(&mv_f[i].macaddr,
6036                                                         addr, ETH_ADDR_LEN);
6037                                         mv_f[i].vlan_id =
6038                                                 j * I40E_UINT32_BIT_SIZE + k;
6039                                         i++;
6040                                 }
6041                         }
6042                 }
6043         }
6044         return I40E_SUCCESS;
6045 }
6046
6047 static inline int
6048 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6049                            struct i40e_macvlan_filter *mv_f,
6050                            int num,
6051                            uint16_t vlan)
6052 {
6053         int i = 0;
6054         struct i40e_mac_filter *f;
6055
6056         if (num < vsi->mac_num)
6057                 return I40E_ERR_PARAM;
6058
6059         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6060                 if (i > num - 1) {
6061                         PMD_DRV_LOG(ERR, "buffer number not match");
6062                         return I40E_ERR_PARAM;
6063                 }
6064                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6065                                 ETH_ADDR_LEN);
6066                 mv_f[i].vlan_id = vlan;
6067                 mv_f[i].filter_type = f->mac_info.filter_type;
6068                 i++;
6069         }
6070
6071         return I40E_SUCCESS;
6072 }
6073
6074 static int
6075 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6076 {
6077         int i, num;
6078         struct i40e_mac_filter *f;
6079         struct i40e_macvlan_filter *mv_f;
6080         int ret = I40E_SUCCESS;
6081
6082         if (vsi == NULL || vsi->mac_num == 0)
6083                 return I40E_ERR_PARAM;
6084
6085         /* Case that no vlan is set */
6086         if (vsi->vlan_num == 0)
6087                 num = vsi->mac_num;
6088         else
6089                 num = vsi->mac_num * vsi->vlan_num;
6090
6091         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6092         if (mv_f == NULL) {
6093                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6094                 return I40E_ERR_NO_MEMORY;
6095         }
6096
6097         i = 0;
6098         if (vsi->vlan_num == 0) {
6099                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6100                         (void)rte_memcpy(&mv_f[i].macaddr,
6101                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6102                         mv_f[i].vlan_id = 0;
6103                         i++;
6104                 }
6105         } else {
6106                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6107                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6108                                         vsi->vlan_num, &f->mac_info.mac_addr);
6109                         if (ret != I40E_SUCCESS)
6110                                 goto DONE;
6111                         i += vsi->vlan_num;
6112                 }
6113         }
6114
6115         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6116 DONE:
6117         rte_free(mv_f);
6118
6119         return ret;
6120 }
6121
6122 int
6123 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6124 {
6125         struct i40e_macvlan_filter *mv_f;
6126         int mac_num;
6127         int ret = I40E_SUCCESS;
6128
6129         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6130                 return I40E_ERR_PARAM;
6131
6132         /* If it's already set, just return */
6133         if (i40e_find_vlan_filter(vsi,vlan))
6134                 return I40E_SUCCESS;
6135
6136         mac_num = vsi->mac_num;
6137
6138         if (mac_num == 0) {
6139                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6140                 return I40E_ERR_PARAM;
6141         }
6142
6143         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6144
6145         if (mv_f == NULL) {
6146                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6147                 return I40E_ERR_NO_MEMORY;
6148         }
6149
6150         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6151
6152         if (ret != I40E_SUCCESS)
6153                 goto DONE;
6154
6155         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6156
6157         if (ret != I40E_SUCCESS)
6158                 goto DONE;
6159
6160         i40e_set_vlan_filter(vsi, vlan, 1);
6161
6162         vsi->vlan_num++;
6163         ret = I40E_SUCCESS;
6164 DONE:
6165         rte_free(mv_f);
6166         return ret;
6167 }
6168
6169 int
6170 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6171 {
6172         struct i40e_macvlan_filter *mv_f;
6173         int mac_num;
6174         int ret = I40E_SUCCESS;
6175
6176         /**
6177          * Vlan 0 is the generic filter for untagged packets
6178          * and can't be removed.
6179          */
6180         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6181                 return I40E_ERR_PARAM;
6182
6183         /* If can't find it, just return */
6184         if (!i40e_find_vlan_filter(vsi, vlan))
6185                 return I40E_ERR_PARAM;
6186
6187         mac_num = vsi->mac_num;
6188
6189         if (mac_num == 0) {
6190                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6191                 return I40E_ERR_PARAM;
6192         }
6193
6194         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6195
6196         if (mv_f == NULL) {
6197                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6198                 return I40E_ERR_NO_MEMORY;
6199         }
6200
6201         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6202
6203         if (ret != I40E_SUCCESS)
6204                 goto DONE;
6205
6206         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6207
6208         if (ret != I40E_SUCCESS)
6209                 goto DONE;
6210
6211         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6212         if (vsi->vlan_num == 1) {
6213                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6214                 if (ret != I40E_SUCCESS)
6215                         goto DONE;
6216
6217                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6218                 if (ret != I40E_SUCCESS)
6219                         goto DONE;
6220         }
6221
6222         i40e_set_vlan_filter(vsi, vlan, 0);
6223
6224         vsi->vlan_num--;
6225         ret = I40E_SUCCESS;
6226 DONE:
6227         rte_free(mv_f);
6228         return ret;
6229 }
6230
6231 int
6232 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6233 {
6234         struct i40e_mac_filter *f;
6235         struct i40e_macvlan_filter *mv_f;
6236         int i, vlan_num = 0;
6237         int ret = I40E_SUCCESS;
6238
6239         /* If it's add and we've config it, return */
6240         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6241         if (f != NULL)
6242                 return I40E_SUCCESS;
6243         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6244                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6245
6246                 /**
6247                  * If vlan_num is 0, that's the first time to add mac,
6248                  * set mask for vlan_id 0.
6249                  */
6250                 if (vsi->vlan_num == 0) {
6251                         i40e_set_vlan_filter(vsi, 0, 1);
6252                         vsi->vlan_num = 1;
6253                 }
6254                 vlan_num = vsi->vlan_num;
6255         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6256                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6257                 vlan_num = 1;
6258
6259         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6260         if (mv_f == NULL) {
6261                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6262                 return I40E_ERR_NO_MEMORY;
6263         }
6264
6265         for (i = 0; i < vlan_num; i++) {
6266                 mv_f[i].filter_type = mac_filter->filter_type;
6267                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6268                                 ETH_ADDR_LEN);
6269         }
6270
6271         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6272                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6273                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6274                                         &mac_filter->mac_addr);
6275                 if (ret != I40E_SUCCESS)
6276                         goto DONE;
6277         }
6278
6279         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6280         if (ret != I40E_SUCCESS)
6281                 goto DONE;
6282
6283         /* Add the mac addr into mac list */
6284         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6285         if (f == NULL) {
6286                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6287                 ret = I40E_ERR_NO_MEMORY;
6288                 goto DONE;
6289         }
6290         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6291                         ETH_ADDR_LEN);
6292         f->mac_info.filter_type = mac_filter->filter_type;
6293         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6294         vsi->mac_num++;
6295
6296         ret = I40E_SUCCESS;
6297 DONE:
6298         rte_free(mv_f);
6299
6300         return ret;
6301 }
6302
6303 int
6304 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6305 {
6306         struct i40e_mac_filter *f;
6307         struct i40e_macvlan_filter *mv_f;
6308         int i, vlan_num;
6309         enum rte_mac_filter_type filter_type;
6310         int ret = I40E_SUCCESS;
6311
6312         /* Can't find it, return an error */
6313         f = i40e_find_mac_filter(vsi, addr);
6314         if (f == NULL)
6315                 return I40E_ERR_PARAM;
6316
6317         vlan_num = vsi->vlan_num;
6318         filter_type = f->mac_info.filter_type;
6319         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6320                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6321                 if (vlan_num == 0) {
6322                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6323                         return I40E_ERR_PARAM;
6324                 }
6325         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6326                         filter_type == RTE_MAC_HASH_MATCH)
6327                 vlan_num = 1;
6328
6329         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6330         if (mv_f == NULL) {
6331                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6332                 return I40E_ERR_NO_MEMORY;
6333         }
6334
6335         for (i = 0; i < vlan_num; i++) {
6336                 mv_f[i].filter_type = filter_type;
6337                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6338                                 ETH_ADDR_LEN);
6339         }
6340         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6341                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6342                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6343                 if (ret != I40E_SUCCESS)
6344                         goto DONE;
6345         }
6346
6347         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6348         if (ret != I40E_SUCCESS)
6349                 goto DONE;
6350
6351         /* Remove the mac addr into mac list */
6352         TAILQ_REMOVE(&vsi->mac_list, f, next);
6353         rte_free(f);
6354         vsi->mac_num--;
6355
6356         ret = I40E_SUCCESS;
6357 DONE:
6358         rte_free(mv_f);
6359         return ret;
6360 }
6361
6362 /* Configure hash enable flags for RSS */
6363 uint64_t
6364 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6365 {
6366         uint64_t hena = 0;
6367
6368         if (!flags)
6369                 return hena;
6370
6371         if (flags & ETH_RSS_FRAG_IPV4)
6372                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6373         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6374                 if (type == I40E_MAC_X722) {
6375                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6376                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6377                 } else
6378                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6379         }
6380         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6381                 if (type == I40E_MAC_X722) {
6382                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6383                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6384                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6385                 } else
6386                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6387         }
6388         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6389                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6390         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6391                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6392         if (flags & ETH_RSS_FRAG_IPV6)
6393                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6394         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6395                 if (type == I40E_MAC_X722) {
6396                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6397                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6398                 } else
6399                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6400         }
6401         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6402                 if (type == I40E_MAC_X722) {
6403                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6404                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6405                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6406                 } else
6407                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6408         }
6409         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6410                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6411         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6412                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6413         if (flags & ETH_RSS_L2_PAYLOAD)
6414                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6415
6416         return hena;
6417 }
6418
6419 /* Parse the hash enable flags */
6420 uint64_t
6421 i40e_parse_hena(uint64_t flags)
6422 {
6423         uint64_t rss_hf = 0;
6424
6425         if (!flags)
6426                 return rss_hf;
6427         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6428                 rss_hf |= ETH_RSS_FRAG_IPV4;
6429         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6430                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6431         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6432                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6433         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6434                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6435         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6436                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6437         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6438                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6439         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6440                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6441         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6442                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6443         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6444                 rss_hf |= ETH_RSS_FRAG_IPV6;
6445         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6446                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6447         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6448                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6449         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6450                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6451         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6452                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6453         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6454                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6455         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6456                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6457         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6458                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6459         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6460                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6461
6462         return rss_hf;
6463 }
6464
6465 /* Disable RSS */
6466 static void
6467 i40e_pf_disable_rss(struct i40e_pf *pf)
6468 {
6469         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6470         uint64_t hena;
6471
6472         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6473         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6474         if (hw->mac.type == I40E_MAC_X722)
6475                 hena &= ~I40E_RSS_HENA_ALL_X722;
6476         else
6477                 hena &= ~I40E_RSS_HENA_ALL;
6478         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6479         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6480         I40E_WRITE_FLUSH(hw);
6481 }
6482
6483 static int
6484 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6485 {
6486         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6487         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6488         int ret = 0;
6489
6490         if (!key || key_len == 0) {
6491                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6492                 return 0;
6493         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6494                 sizeof(uint32_t)) {
6495                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6496                 return -EINVAL;
6497         }
6498
6499         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6500                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6501                         (struct i40e_aqc_get_set_rss_key_data *)key;
6502
6503                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6504                 if (ret)
6505                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6506                                      "via AQ");
6507         } else {
6508                 uint32_t *hash_key = (uint32_t *)key;
6509                 uint16_t i;
6510
6511                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6512                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6513                 I40E_WRITE_FLUSH(hw);
6514         }
6515
6516         return ret;
6517 }
6518
6519 static int
6520 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6521 {
6522         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6523         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6524         int ret;
6525
6526         if (!key || !key_len)
6527                 return -EINVAL;
6528
6529         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6530                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6531                         (struct i40e_aqc_get_set_rss_key_data *)key);
6532                 if (ret) {
6533                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6534                         return ret;
6535                 }
6536         } else {
6537                 uint32_t *key_dw = (uint32_t *)key;
6538                 uint16_t i;
6539
6540                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6541                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6542         }
6543         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6544
6545         return 0;
6546 }
6547
6548 static int
6549 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6550 {
6551         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6552         uint64_t rss_hf;
6553         uint64_t hena;
6554         int ret;
6555
6556         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6557                                rss_conf->rss_key_len);
6558         if (ret)
6559                 return ret;
6560
6561         rss_hf = rss_conf->rss_hf;
6562         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6563         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6564         if (hw->mac.type == I40E_MAC_X722)
6565                 hena &= ~I40E_RSS_HENA_ALL_X722;
6566         else
6567                 hena &= ~I40E_RSS_HENA_ALL;
6568         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6569         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6570         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6571         I40E_WRITE_FLUSH(hw);
6572
6573         return 0;
6574 }
6575
6576 static int
6577 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6578                          struct rte_eth_rss_conf *rss_conf)
6579 {
6580         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6581         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6582         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6583         uint64_t hena;
6584
6585         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6586         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6587         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6588                  ? I40E_RSS_HENA_ALL_X722
6589                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6590                 if (rss_hf != 0) /* Enable RSS */
6591                         return -EINVAL;
6592                 return 0; /* Nothing to do */
6593         }
6594         /* RSS enabled */
6595         if (rss_hf == 0) /* Disable RSS */
6596                 return -EINVAL;
6597
6598         return i40e_hw_rss_hash_set(pf, rss_conf);
6599 }
6600
6601 static int
6602 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6603                            struct rte_eth_rss_conf *rss_conf)
6604 {
6605         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6606         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6607         uint64_t hena;
6608
6609         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6610                          &rss_conf->rss_key_len);
6611
6612         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6613         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6614         rss_conf->rss_hf = i40e_parse_hena(hena);
6615
6616         return 0;
6617 }
6618
6619 static int
6620 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6621 {
6622         switch (filter_type) {
6623         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6624                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6625                 break;
6626         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6627                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6628                 break;
6629         case RTE_TUNNEL_FILTER_IMAC_TENID:
6630                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6631                 break;
6632         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6633                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6634                 break;
6635         case ETH_TUNNEL_FILTER_IMAC:
6636                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6637                 break;
6638         case ETH_TUNNEL_FILTER_OIP:
6639                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6640                 break;
6641         case ETH_TUNNEL_FILTER_IIP:
6642                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6643                 break;
6644         default:
6645                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6646                 return -EINVAL;
6647         }
6648
6649         return 0;
6650 }
6651
6652 /* Convert tunnel filter structure */
6653 static int
6654 i40e_tunnel_filter_convert(struct i40e_aqc_add_remove_cloud_filters_element_data
6655                            *cld_filter,
6656                            struct i40e_tunnel_filter *tunnel_filter)
6657 {
6658         ether_addr_copy((struct ether_addr *)&cld_filter->outer_mac,
6659                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6660         ether_addr_copy((struct ether_addr *)&cld_filter->inner_mac,
6661                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6662         tunnel_filter->input.inner_vlan = cld_filter->inner_vlan;
6663         tunnel_filter->input.flags = cld_filter->flags;
6664         tunnel_filter->input.tenant_id = cld_filter->tenant_id;
6665         tunnel_filter->queue = cld_filter->queue_number;
6666
6667         return 0;
6668 }
6669
6670 /* Check if there exists the tunnel filter */
6671 struct i40e_tunnel_filter *
6672 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6673                              const struct i40e_tunnel_filter_input *input)
6674 {
6675         int ret;
6676
6677         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6678         if (ret < 0)
6679                 return NULL;
6680
6681         return tunnel_rule->hash_map[ret];
6682 }
6683
6684 /* Add a tunnel filter into the SW list */
6685 static int
6686 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6687                              struct i40e_tunnel_filter *tunnel_filter)
6688 {
6689         struct i40e_tunnel_rule *rule = &pf->tunnel;
6690         int ret;
6691
6692         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6693         if (ret < 0) {
6694                 PMD_DRV_LOG(ERR,
6695                             "Failed to insert tunnel filter to hash table %d!",
6696                             ret);
6697                 return ret;
6698         }
6699         rule->hash_map[ret] = tunnel_filter;
6700
6701         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6702
6703         return 0;
6704 }
6705
6706 /* Delete a tunnel filter from the SW list */
6707 int
6708 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6709                           struct i40e_tunnel_filter_input *input)
6710 {
6711         struct i40e_tunnel_rule *rule = &pf->tunnel;
6712         struct i40e_tunnel_filter *tunnel_filter;
6713         int ret;
6714
6715         ret = rte_hash_del_key(rule->hash_table, input);
6716         if (ret < 0) {
6717                 PMD_DRV_LOG(ERR,
6718                             "Failed to delete tunnel filter to hash table %d!",
6719                             ret);
6720                 return ret;
6721         }
6722         tunnel_filter = rule->hash_map[ret];
6723         rule->hash_map[ret] = NULL;
6724
6725         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6726         rte_free(tunnel_filter);
6727
6728         return 0;
6729 }
6730
6731 int
6732 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6733                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6734                         uint8_t add)
6735 {
6736         uint16_t ip_type;
6737         uint32_t ipv4_addr;
6738         uint8_t i, tun_type = 0;
6739         /* internal varialbe to convert ipv6 byte order */
6740         uint32_t convert_ipv6[4];
6741         int val, ret = 0;
6742         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6743         struct i40e_vsi *vsi = pf->main_vsi;
6744         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6745         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6746         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6747         struct i40e_tunnel_filter *tunnel, *node;
6748         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6749
6750         cld_filter = rte_zmalloc("tunnel_filter",
6751                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6752                 0);
6753
6754         if (NULL == cld_filter) {
6755                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6756                 return -EINVAL;
6757         }
6758         pfilter = cld_filter;
6759
6760         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6761         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6762
6763         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6764         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6765                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6766                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6767                 rte_memcpy(&pfilter->ipaddr.v4.data,
6768                                 &rte_cpu_to_le_32(ipv4_addr),
6769                                 sizeof(pfilter->ipaddr.v4.data));
6770         } else {
6771                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6772                 for (i = 0; i < 4; i++) {
6773                         convert_ipv6[i] =
6774                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6775                 }
6776                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6777                                 sizeof(pfilter->ipaddr.v6.data));
6778         }
6779
6780         /* check tunneled type */
6781         switch (tunnel_filter->tunnel_type) {
6782         case RTE_TUNNEL_TYPE_VXLAN:
6783                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6784                 break;
6785         case RTE_TUNNEL_TYPE_NVGRE:
6786                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6787                 break;
6788         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6789                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6790                 break;
6791         default:
6792                 /* Other tunnel types is not supported. */
6793                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6794                 rte_free(cld_filter);
6795                 return -EINVAL;
6796         }
6797
6798         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6799                                                 &pfilter->flags);
6800         if (val < 0) {
6801                 rte_free(cld_filter);
6802                 return -EINVAL;
6803         }
6804
6805         pfilter->flags |= rte_cpu_to_le_16(
6806                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6807                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6808         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6809         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6810
6811         /* Check if there is the filter in SW list */
6812         memset(&check_filter, 0, sizeof(check_filter));
6813         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6814         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6815         if (add && node) {
6816                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6817                 return -EINVAL;
6818         }
6819
6820         if (!add && !node) {
6821                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6822                 return -EINVAL;
6823         }
6824
6825         if (add) {
6826                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6827                 if (ret < 0) {
6828                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6829                         return ret;
6830                 }
6831                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6832                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6833                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6834         } else {
6835                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6836                                                    cld_filter, 1);
6837                 if (ret < 0) {
6838                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6839                         return ret;
6840                 }
6841                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6842         }
6843
6844         rte_free(cld_filter);
6845         return ret;
6846 }
6847
6848 static int
6849 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6850 {
6851         uint8_t i;
6852
6853         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6854                 if (pf->vxlan_ports[i] == port)
6855                         return i;
6856         }
6857
6858         return -1;
6859 }
6860
6861 static int
6862 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6863 {
6864         int  idx, ret;
6865         uint8_t filter_idx;
6866         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6867
6868         idx = i40e_get_vxlan_port_idx(pf, port);
6869
6870         /* Check if port already exists */
6871         if (idx >= 0) {
6872                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6873                 return -EINVAL;
6874         }
6875
6876         /* Now check if there is space to add the new port */
6877         idx = i40e_get_vxlan_port_idx(pf, 0);
6878         if (idx < 0) {
6879                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6880                         "not adding port %d", port);
6881                 return -ENOSPC;
6882         }
6883
6884         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6885                                         &filter_idx, NULL);
6886         if (ret < 0) {
6887                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6888                 return -1;
6889         }
6890
6891         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6892                          port,  filter_idx);
6893
6894         /* New port: add it and mark its index in the bitmap */
6895         pf->vxlan_ports[idx] = port;
6896         pf->vxlan_bitmap |= (1 << idx);
6897
6898         if (!(pf->flags & I40E_FLAG_VXLAN))
6899                 pf->flags |= I40E_FLAG_VXLAN;
6900
6901         return 0;
6902 }
6903
6904 static int
6905 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6906 {
6907         int idx;
6908         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6909
6910         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6911                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6912                 return -EINVAL;
6913         }
6914
6915         idx = i40e_get_vxlan_port_idx(pf, port);
6916
6917         if (idx < 0) {
6918                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6919                 return -EINVAL;
6920         }
6921
6922         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6923                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6924                 return -1;
6925         }
6926
6927         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6928                         port, idx);
6929
6930         pf->vxlan_ports[idx] = 0;
6931         pf->vxlan_bitmap &= ~(1 << idx);
6932
6933         if (!pf->vxlan_bitmap)
6934                 pf->flags &= ~I40E_FLAG_VXLAN;
6935
6936         return 0;
6937 }
6938
6939 /* Add UDP tunneling port */
6940 static int
6941 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6942                              struct rte_eth_udp_tunnel *udp_tunnel)
6943 {
6944         int ret = 0;
6945         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6946
6947         if (udp_tunnel == NULL)
6948                 return -EINVAL;
6949
6950         switch (udp_tunnel->prot_type) {
6951         case RTE_TUNNEL_TYPE_VXLAN:
6952                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6953                 break;
6954
6955         case RTE_TUNNEL_TYPE_GENEVE:
6956         case RTE_TUNNEL_TYPE_TEREDO:
6957                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6958                 ret = -1;
6959                 break;
6960
6961         default:
6962                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6963                 ret = -1;
6964                 break;
6965         }
6966
6967         return ret;
6968 }
6969
6970 /* Remove UDP tunneling port */
6971 static int
6972 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6973                              struct rte_eth_udp_tunnel *udp_tunnel)
6974 {
6975         int ret = 0;
6976         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6977
6978         if (udp_tunnel == NULL)
6979                 return -EINVAL;
6980
6981         switch (udp_tunnel->prot_type) {
6982         case RTE_TUNNEL_TYPE_VXLAN:
6983                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6984                 break;
6985         case RTE_TUNNEL_TYPE_GENEVE:
6986         case RTE_TUNNEL_TYPE_TEREDO:
6987                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6988                 ret = -1;
6989                 break;
6990         default:
6991                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6992                 ret = -1;
6993                 break;
6994         }
6995
6996         return ret;
6997 }
6998
6999 /* Calculate the maximum number of contiguous PF queues that are configured */
7000 static int
7001 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7002 {
7003         struct rte_eth_dev_data *data = pf->dev_data;
7004         int i, num;
7005         struct i40e_rx_queue *rxq;
7006
7007         num = 0;
7008         for (i = 0; i < pf->lan_nb_qps; i++) {
7009                 rxq = data->rx_queues[i];
7010                 if (rxq && rxq->q_set)
7011                         num++;
7012                 else
7013                         break;
7014         }
7015
7016         return num;
7017 }
7018
7019 /* Configure RSS */
7020 static int
7021 i40e_pf_config_rss(struct i40e_pf *pf)
7022 {
7023         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7024         struct rte_eth_rss_conf rss_conf;
7025         uint32_t i, lut = 0;
7026         uint16_t j, num;
7027
7028         /*
7029          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7030          * It's necessary to calulate the actual PF queues that are configured.
7031          */
7032         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7033                 num = i40e_pf_calc_configured_queues_num(pf);
7034         else
7035                 num = pf->dev_data->nb_rx_queues;
7036
7037         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7038         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7039                         num);
7040
7041         if (num == 0) {
7042                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7043                 return -ENOTSUP;
7044         }
7045
7046         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7047                 if (j == num)
7048                         j = 0;
7049                 lut = (lut << 8) | (j & ((0x1 <<
7050                         hw->func_caps.rss_table_entry_width) - 1));
7051                 if ((i & 3) == 3)
7052                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7053         }
7054
7055         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7056         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7057                 i40e_pf_disable_rss(pf);
7058                 return 0;
7059         }
7060         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7061                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7062                 /* Random default keys */
7063                 static uint32_t rss_key_default[] = {0x6b793944,
7064                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7065                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7066                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7067
7068                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7069                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7070                                                         sizeof(uint32_t);
7071         }
7072
7073         return i40e_hw_rss_hash_set(pf, &rss_conf);
7074 }
7075
7076 static int
7077 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7078                                struct rte_eth_tunnel_filter_conf *filter)
7079 {
7080         if (pf == NULL || filter == NULL) {
7081                 PMD_DRV_LOG(ERR, "Invalid parameter");
7082                 return -EINVAL;
7083         }
7084
7085         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7086                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7087                 return -EINVAL;
7088         }
7089
7090         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7091                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7092                 return -EINVAL;
7093         }
7094
7095         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7096                 (is_zero_ether_addr(&filter->outer_mac))) {
7097                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7098                 return -EINVAL;
7099         }
7100
7101         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7102                 (is_zero_ether_addr(&filter->inner_mac))) {
7103                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7104                 return -EINVAL;
7105         }
7106
7107         return 0;
7108 }
7109
7110 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7111 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7112 static int
7113 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7114 {
7115         uint32_t val, reg;
7116         int ret = -EINVAL;
7117
7118         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7119         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
7120
7121         if (len == 3) {
7122                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7123         } else if (len == 4) {
7124                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7125         } else {
7126                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7127                 return ret;
7128         }
7129
7130         if (reg != val) {
7131                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7132                                                    reg, NULL);
7133                 if (ret != 0)
7134                         return ret;
7135         } else {
7136                 ret = 0;
7137         }
7138         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
7139                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7140
7141         return ret;
7142 }
7143
7144 static int
7145 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7146 {
7147         int ret = -EINVAL;
7148
7149         if (!hw || !cfg)
7150                 return -EINVAL;
7151
7152         switch (cfg->cfg_type) {
7153         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7154                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7155                 break;
7156         default:
7157                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7158                 break;
7159         }
7160
7161         return ret;
7162 }
7163
7164 static int
7165 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7166                                enum rte_filter_op filter_op,
7167                                void *arg)
7168 {
7169         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7170         int ret = I40E_ERR_PARAM;
7171
7172         switch (filter_op) {
7173         case RTE_ETH_FILTER_SET:
7174                 ret = i40e_dev_global_config_set(hw,
7175                         (struct rte_eth_global_cfg *)arg);
7176                 break;
7177         default:
7178                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7179                 break;
7180         }
7181
7182         return ret;
7183 }
7184
7185 static int
7186 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7187                           enum rte_filter_op filter_op,
7188                           void *arg)
7189 {
7190         struct rte_eth_tunnel_filter_conf *filter;
7191         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7192         int ret = I40E_SUCCESS;
7193
7194         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7195
7196         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7197                 return I40E_ERR_PARAM;
7198
7199         switch (filter_op) {
7200         case RTE_ETH_FILTER_NOP:
7201                 if (!(pf->flags & I40E_FLAG_VXLAN))
7202                         ret = I40E_NOT_SUPPORTED;
7203                 break;
7204         case RTE_ETH_FILTER_ADD:
7205                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7206                 break;
7207         case RTE_ETH_FILTER_DELETE:
7208                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7209                 break;
7210         default:
7211                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7212                 ret = I40E_ERR_PARAM;
7213                 break;
7214         }
7215
7216         return ret;
7217 }
7218
7219 static int
7220 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7221 {
7222         int ret = 0;
7223         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7224
7225         /* RSS setup */
7226         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7227                 ret = i40e_pf_config_rss(pf);
7228         else
7229                 i40e_pf_disable_rss(pf);
7230
7231         return ret;
7232 }
7233
7234 /* Get the symmetric hash enable configurations per port */
7235 static void
7236 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7237 {
7238         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7239
7240         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7241 }
7242
7243 /* Set the symmetric hash enable configurations per port */
7244 static void
7245 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7246 {
7247         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7248
7249         if (enable > 0) {
7250                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7251                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
7252                                                         "been enabled");
7253                         return;
7254                 }
7255                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7256         } else {
7257                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7258                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
7259                                                         "been disabled");
7260                         return;
7261                 }
7262                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7263         }
7264         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7265         I40E_WRITE_FLUSH(hw);
7266 }
7267
7268 /*
7269  * Get global configurations of hash function type and symmetric hash enable
7270  * per flow type (pctype). Note that global configuration means it affects all
7271  * the ports on the same NIC.
7272  */
7273 static int
7274 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7275                                    struct rte_eth_hash_global_conf *g_cfg)
7276 {
7277         uint32_t reg, mask = I40E_FLOW_TYPES;
7278         uint16_t i;
7279         enum i40e_filter_pctype pctype;
7280
7281         memset(g_cfg, 0, sizeof(*g_cfg));
7282         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7283         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7284                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7285         else
7286                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7287         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7288                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7289
7290         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7291                 if (!(mask & (1UL << i)))
7292                         continue;
7293                 mask &= ~(1UL << i);
7294                 /* Bit set indicats the coresponding flow type is supported */
7295                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7296                 /* if flowtype is invalid, continue */
7297                 if (!I40E_VALID_FLOW(i))
7298                         continue;
7299                 pctype = i40e_flowtype_to_pctype(i);
7300                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7301                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7302                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7303         }
7304
7305         return 0;
7306 }
7307
7308 static int
7309 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7310 {
7311         uint32_t i;
7312         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7313
7314         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7315                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7316                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7317                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7318                                                 g_cfg->hash_func);
7319                 return -EINVAL;
7320         }
7321
7322         /*
7323          * As i40e supports less than 32 flow types, only first 32 bits need to
7324          * be checked.
7325          */
7326         mask0 = g_cfg->valid_bit_mask[0];
7327         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7328                 if (i == 0) {
7329                         /* Check if any unsupported flow type configured */
7330                         if ((mask0 | i40e_mask) ^ i40e_mask)
7331                                 goto mask_err;
7332                 } else {
7333                         if (g_cfg->valid_bit_mask[i])
7334                                 goto mask_err;
7335                 }
7336         }
7337
7338         return 0;
7339
7340 mask_err:
7341         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7342
7343         return -EINVAL;
7344 }
7345
7346 /*
7347  * Set global configurations of hash function type and symmetric hash enable
7348  * per flow type (pctype). Note any modifying global configuration will affect
7349  * all the ports on the same NIC.
7350  */
7351 static int
7352 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7353                                    struct rte_eth_hash_global_conf *g_cfg)
7354 {
7355         int ret;
7356         uint16_t i;
7357         uint32_t reg;
7358         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7359         enum i40e_filter_pctype pctype;
7360
7361         /* Check the input parameters */
7362         ret = i40e_hash_global_config_check(g_cfg);
7363         if (ret < 0)
7364                 return ret;
7365
7366         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7367                 if (!(mask0 & (1UL << i)))
7368                         continue;
7369                 mask0 &= ~(1UL << i);
7370                 /* if flowtype is invalid, continue */
7371                 if (!I40E_VALID_FLOW(i))
7372                         continue;
7373                 pctype = i40e_flowtype_to_pctype(i);
7374                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7375                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7376                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7377         }
7378
7379         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7380         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7381                 /* Toeplitz */
7382                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7383                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7384                                                                 "Toeplitz");
7385                         goto out;
7386                 }
7387                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7388         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7389                 /* Simple XOR */
7390                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7391                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7392                                                         "Simple XOR");
7393                         goto out;
7394                 }
7395                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7396         } else
7397                 /* Use the default, and keep it as it is */
7398                 goto out;
7399
7400         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7401
7402 out:
7403         I40E_WRITE_FLUSH(hw);
7404
7405         return 0;
7406 }
7407
7408 /**
7409  * Valid input sets for hash and flow director filters per PCTYPE
7410  */
7411 static uint64_t
7412 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7413                 enum rte_filter_type filter)
7414 {
7415         uint64_t valid;
7416
7417         static const uint64_t valid_hash_inset_table[] = {
7418                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7419                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7420                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7421                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7422                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7423                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7424                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7425                         I40E_INSET_FLEX_PAYLOAD,
7426                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7427                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7428                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7429                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7430                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7431                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7432                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7433                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7434                         I40E_INSET_FLEX_PAYLOAD,
7435                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7436                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7437                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7438                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7439                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7440                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7441                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7442                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7443                         I40E_INSET_FLEX_PAYLOAD,
7444                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7445                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7446                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7447                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7448                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7449                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7450                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7451                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7452                         I40E_INSET_FLEX_PAYLOAD,
7453                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7454                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7455                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7456                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7457                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7458                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7459                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7460                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7461                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7462                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7463                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7464                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7465                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7466                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7467                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7468                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7469                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7470                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7471                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7472                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7473                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7474                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7475                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7476                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7477                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7478                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7479                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7480                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7481                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7482                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7483                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7484                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7485                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7486                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7487                         I40E_INSET_FLEX_PAYLOAD,
7488                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7489                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7490                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7491                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7492                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7493                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7494                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7495                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7496                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7497                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7498                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7499                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7500                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7501                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7502                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7503                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7504                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7505                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7506                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7507                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7508                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7509                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7510                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7511                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7512                         I40E_INSET_FLEX_PAYLOAD,
7513                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7514                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7515                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7516                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7517                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7518                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7519                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7520                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7521                         I40E_INSET_FLEX_PAYLOAD,
7522                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7523                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7524                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7525                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7526                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7527                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7528                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7529                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7530                         I40E_INSET_FLEX_PAYLOAD,
7531                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7532                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7533                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7534                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7535                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7536                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7537                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7538                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7539                         I40E_INSET_FLEX_PAYLOAD,
7540                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7541                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7542                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7543                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7544                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7545                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7546                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7547                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7548                         I40E_INSET_FLEX_PAYLOAD,
7549                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7550                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7551                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7552                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7553                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7554                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7555                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7556                         I40E_INSET_FLEX_PAYLOAD,
7557                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7558                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7559                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7560                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7561                         I40E_INSET_FLEX_PAYLOAD,
7562         };
7563
7564         /**
7565          * Flow director supports only fields defined in
7566          * union rte_eth_fdir_flow.
7567          */
7568         static const uint64_t valid_fdir_inset_table[] = {
7569                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7570                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7571                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7572                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7573                 I40E_INSET_IPV4_TTL,
7574                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7575                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7576                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7577                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7578                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7579                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7580                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7581                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7582                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7583                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7584                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7585                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7586                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7587                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7588                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7589                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7590                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7591                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7592                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7593                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7594                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7595                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7596                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7597                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7598                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7599                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7600                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7601                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7602                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7603                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7604                 I40E_INSET_SCTP_VT,
7605                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7606                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7607                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7608                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7609                 I40E_INSET_IPV4_TTL,
7610                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7611                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7612                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7613                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7614                 I40E_INSET_IPV6_HOP_LIMIT,
7615                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7616                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7617                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7618                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7619                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7620                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7621                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7622                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7623                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7624                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7625                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7626                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7627                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7628                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7629                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7630                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7631                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7632                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7633                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7634                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7635                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7636                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7637                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7638                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7639                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7640                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7641                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7642                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7643                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7644                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7645                 I40E_INSET_SCTP_VT,
7646                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7647                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7648                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7649                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7650                 I40E_INSET_IPV6_HOP_LIMIT,
7651                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7652                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7653                 I40E_INSET_LAST_ETHER_TYPE,
7654         };
7655
7656         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7657                 return 0;
7658         if (filter == RTE_ETH_FILTER_HASH)
7659                 valid = valid_hash_inset_table[pctype];
7660         else
7661                 valid = valid_fdir_inset_table[pctype];
7662
7663         return valid;
7664 }
7665
7666 /**
7667  * Validate if the input set is allowed for a specific PCTYPE
7668  */
7669 static int
7670 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7671                 enum rte_filter_type filter, uint64_t inset)
7672 {
7673         uint64_t valid;
7674
7675         valid = i40e_get_valid_input_set(pctype, filter);
7676         if (inset & (~valid))
7677                 return -EINVAL;
7678
7679         return 0;
7680 }
7681
7682 /* default input set fields combination per pctype */
7683 uint64_t
7684 i40e_get_default_input_set(uint16_t pctype)
7685 {
7686         static const uint64_t default_inset_table[] = {
7687                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7688                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7689                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7690                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7691                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7692                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7693                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7694                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7695                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7696                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7697                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7698                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7699                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7700                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7701                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7702                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7703                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7704                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7705                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7706                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7707                         I40E_INSET_SCTP_VT,
7708                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7709                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7710                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7711                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7712                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7713                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7714                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7715                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7716                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7717                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7718                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7719                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7720                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7721                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7722                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7723                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7724                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7725                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7726                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7727                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7728                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7729                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7730                         I40E_INSET_SCTP_VT,
7731                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7732                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7733                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7734                         I40E_INSET_LAST_ETHER_TYPE,
7735         };
7736
7737         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7738                 return 0;
7739
7740         return default_inset_table[pctype];
7741 }
7742
7743 /**
7744  * Parse the input set from index to logical bit masks
7745  */
7746 static int
7747 i40e_parse_input_set(uint64_t *inset,
7748                      enum i40e_filter_pctype pctype,
7749                      enum rte_eth_input_set_field *field,
7750                      uint16_t size)
7751 {
7752         uint16_t i, j;
7753         int ret = -EINVAL;
7754
7755         static const struct {
7756                 enum rte_eth_input_set_field field;
7757                 uint64_t inset;
7758         } inset_convert_table[] = {
7759                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7760                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7761                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7762                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7763                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7764                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7765                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7766                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7767                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7768                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7769                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7770                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7771                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7772                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7773                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7774                         I40E_INSET_IPV6_NEXT_HDR},
7775                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7776                         I40E_INSET_IPV6_HOP_LIMIT},
7777                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7778                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7779                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7780                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7781                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7782                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7783                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7784                         I40E_INSET_SCTP_VT},
7785                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7786                         I40E_INSET_TUNNEL_DMAC},
7787                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7788                         I40E_INSET_VLAN_TUNNEL},
7789                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7790                         I40E_INSET_TUNNEL_ID},
7791                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7792                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7793                         I40E_INSET_FLEX_PAYLOAD_W1},
7794                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7795                         I40E_INSET_FLEX_PAYLOAD_W2},
7796                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7797                         I40E_INSET_FLEX_PAYLOAD_W3},
7798                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7799                         I40E_INSET_FLEX_PAYLOAD_W4},
7800                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7801                         I40E_INSET_FLEX_PAYLOAD_W5},
7802                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7803                         I40E_INSET_FLEX_PAYLOAD_W6},
7804                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7805                         I40E_INSET_FLEX_PAYLOAD_W7},
7806                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7807                         I40E_INSET_FLEX_PAYLOAD_W8},
7808         };
7809
7810         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7811                 return ret;
7812
7813         /* Only one item allowed for default or all */
7814         if (size == 1) {
7815                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7816                         *inset = i40e_get_default_input_set(pctype);
7817                         return 0;
7818                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7819                         *inset = I40E_INSET_NONE;
7820                         return 0;
7821                 }
7822         }
7823
7824         for (i = 0, *inset = 0; i < size; i++) {
7825                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7826                         if (field[i] == inset_convert_table[j].field) {
7827                                 *inset |= inset_convert_table[j].inset;
7828                                 break;
7829                         }
7830                 }
7831
7832                 /* It contains unsupported input set, return immediately */
7833                 if (j == RTE_DIM(inset_convert_table))
7834                         return ret;
7835         }
7836
7837         return 0;
7838 }
7839
7840 /**
7841  * Translate the input set from bit masks to register aware bit masks
7842  * and vice versa
7843  */
7844 static uint64_t
7845 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7846 {
7847         uint64_t val = 0;
7848         uint16_t i;
7849
7850         struct inset_map {
7851                 uint64_t inset;
7852                 uint64_t inset_reg;
7853         };
7854
7855         static const struct inset_map inset_map_common[] = {
7856                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7857                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7858                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7859                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7860                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7861                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7862                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7863                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7864                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7865                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7866                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7867                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7868                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7869                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7870                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7871                 {I40E_INSET_TUNNEL_DMAC,
7872                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7873                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7874                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7875                 {I40E_INSET_TUNNEL_SRC_PORT,
7876                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7877                 {I40E_INSET_TUNNEL_DST_PORT,
7878                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7879                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7880                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7881                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7882                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7883                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7884                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7885                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7886                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7887                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7888         };
7889
7890     /* some different registers map in x722*/
7891         static const struct inset_map inset_map_diff_x722[] = {
7892                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7893                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7894                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7895                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7896         };
7897
7898         static const struct inset_map inset_map_diff_not_x722[] = {
7899                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7900                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7901                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7902                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7903         };
7904
7905         if (input == 0)
7906                 return val;
7907
7908         /* Translate input set to register aware inset */
7909         if (type == I40E_MAC_X722) {
7910                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7911                         if (input & inset_map_diff_x722[i].inset)
7912                                 val |= inset_map_diff_x722[i].inset_reg;
7913                 }
7914         } else {
7915                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7916                         if (input & inset_map_diff_not_x722[i].inset)
7917                                 val |= inset_map_diff_not_x722[i].inset_reg;
7918                 }
7919         }
7920
7921         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7922                 if (input & inset_map_common[i].inset)
7923                         val |= inset_map_common[i].inset_reg;
7924         }
7925
7926         return val;
7927 }
7928
7929 static int
7930 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7931 {
7932         uint8_t i, idx = 0;
7933         uint64_t inset_need_mask = inset;
7934
7935         static const struct {
7936                 uint64_t inset;
7937                 uint32_t mask;
7938         } inset_mask_map[] = {
7939                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7940                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7941                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7942                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7943                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7944                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7945                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7946                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7947         };
7948
7949         if (!inset || !mask || !nb_elem)
7950                 return 0;
7951
7952         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7953                 /* Clear the inset bit, if no MASK is required,
7954                  * for example proto + ttl
7955                  */
7956                 if ((inset & inset_mask_map[i].inset) ==
7957                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7958                         inset_need_mask &= ~inset_mask_map[i].inset;
7959                 if (!inset_need_mask)
7960                         return 0;
7961         }
7962         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7963                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7964                     inset_mask_map[i].inset) {
7965                         if (idx >= nb_elem) {
7966                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7967                                 return -EINVAL;
7968                         }
7969                         mask[idx] = inset_mask_map[i].mask;
7970                         idx++;
7971                 }
7972         }
7973
7974         return idx;
7975 }
7976
7977 static void
7978 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7979 {
7980         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7981
7982         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7983         if (reg != val)
7984                 i40e_write_rx_ctl(hw, addr, val);
7985         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7986                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7987 }
7988
7989 static void
7990 i40e_filter_input_set_init(struct i40e_pf *pf)
7991 {
7992         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7993         enum i40e_filter_pctype pctype;
7994         uint64_t input_set, inset_reg;
7995         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7996         int num, i;
7997
7998         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7999              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8000                 if (hw->mac.type == I40E_MAC_X722) {
8001                         if (!I40E_VALID_PCTYPE_X722(pctype))
8002                                 continue;
8003                 } else {
8004                         if (!I40E_VALID_PCTYPE(pctype))
8005                                 continue;
8006                 }
8007
8008                 input_set = i40e_get_default_input_set(pctype);
8009
8010                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8011                                                    I40E_INSET_MASK_NUM_REG);
8012                 if (num < 0)
8013                         return;
8014                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8015                                         input_set);
8016
8017                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8018                                       (uint32_t)(inset_reg & UINT32_MAX));
8019                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8020                                      (uint32_t)((inset_reg >>
8021                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8022                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8023                                       (uint32_t)(inset_reg & UINT32_MAX));
8024                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8025                                      (uint32_t)((inset_reg >>
8026                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8027
8028                 for (i = 0; i < num; i++) {
8029                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8030                                              mask_reg[i]);
8031                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8032                                              mask_reg[i]);
8033                 }
8034                 /*clear unused mask registers of the pctype */
8035                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8036                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8037                                              0);
8038                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8039                                              0);
8040                 }
8041                 I40E_WRITE_FLUSH(hw);
8042
8043                 /* store the default input set */
8044                 pf->hash_input_set[pctype] = input_set;
8045                 pf->fdir.input_set[pctype] = input_set;
8046         }
8047 }
8048
8049 int
8050 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8051                          struct rte_eth_input_set_conf *conf)
8052 {
8053         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8054         enum i40e_filter_pctype pctype;
8055         uint64_t input_set, inset_reg = 0;
8056         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8057         int ret, i, num;
8058
8059         if (!conf) {
8060                 PMD_DRV_LOG(ERR, "Invalid pointer");
8061                 return -EFAULT;
8062         }
8063         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8064             conf->op != RTE_ETH_INPUT_SET_ADD) {
8065                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8066                 return -EINVAL;
8067         }
8068
8069         if (!I40E_VALID_FLOW(conf->flow_type)) {
8070                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8071                 return -EINVAL;
8072         }
8073
8074         if (hw->mac.type == I40E_MAC_X722) {
8075                 /* get translated pctype value in fd pctype register */
8076                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8077                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8078                         conf->flow_type)));
8079         } else
8080                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8081
8082         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8083                                    conf->inset_size);
8084         if (ret) {
8085                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8086                 return -EINVAL;
8087         }
8088         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8089                                     input_set) != 0) {
8090                 PMD_DRV_LOG(ERR, "Invalid input set");
8091                 return -EINVAL;
8092         }
8093         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8094                 /* get inset value in register */
8095                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8096                 inset_reg <<= I40E_32_BIT_WIDTH;
8097                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8098                 input_set |= pf->hash_input_set[pctype];
8099         }
8100         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8101                                            I40E_INSET_MASK_NUM_REG);
8102         if (num < 0)
8103                 return -EINVAL;
8104
8105         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8106
8107         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8108                               (uint32_t)(inset_reg & UINT32_MAX));
8109         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8110                              (uint32_t)((inset_reg >>
8111                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8112
8113         for (i = 0; i < num; i++)
8114                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8115                                      mask_reg[i]);
8116         /*clear unused mask registers of the pctype */
8117         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8118                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8119                                      0);
8120         I40E_WRITE_FLUSH(hw);
8121
8122         pf->hash_input_set[pctype] = input_set;
8123         return 0;
8124 }
8125
8126 int
8127 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8128                          struct rte_eth_input_set_conf *conf)
8129 {
8130         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8131         enum i40e_filter_pctype pctype;
8132         uint64_t input_set, inset_reg = 0;
8133         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8134         int ret, i, num;
8135
8136         if (!hw || !conf) {
8137                 PMD_DRV_LOG(ERR, "Invalid pointer");
8138                 return -EFAULT;
8139         }
8140         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8141             conf->op != RTE_ETH_INPUT_SET_ADD) {
8142                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8143                 return -EINVAL;
8144         }
8145
8146         if (!I40E_VALID_FLOW(conf->flow_type)) {
8147                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8148                 return -EINVAL;
8149         }
8150
8151         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8152
8153         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8154                                    conf->inset_size);
8155         if (ret) {
8156                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8157                 return -EINVAL;
8158         }
8159         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8160                                     input_set) != 0) {
8161                 PMD_DRV_LOG(ERR, "Invalid input set");
8162                 return -EINVAL;
8163         }
8164
8165         /* get inset value in register */
8166         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8167         inset_reg <<= I40E_32_BIT_WIDTH;
8168         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8169
8170         /* Can not change the inset reg for flex payload for fdir,
8171          * it is done by writing I40E_PRTQF_FD_FLXINSET
8172          * in i40e_set_flex_mask_on_pctype.
8173          */
8174         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8175                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8176         else
8177                 input_set |= pf->fdir.input_set[pctype];
8178         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8179                                            I40E_INSET_MASK_NUM_REG);
8180         if (num < 0)
8181                 return -EINVAL;
8182
8183         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8184
8185         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8186                               (uint32_t)(inset_reg & UINT32_MAX));
8187         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8188                              (uint32_t)((inset_reg >>
8189                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8190
8191         for (i = 0; i < num; i++)
8192                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8193                                      mask_reg[i]);
8194         /*clear unused mask registers of the pctype */
8195         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8196                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8197                                      0);
8198         I40E_WRITE_FLUSH(hw);
8199
8200         pf->fdir.input_set[pctype] = input_set;
8201         return 0;
8202 }
8203
8204 static int
8205 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8206 {
8207         int ret = 0;
8208
8209         if (!hw || !info) {
8210                 PMD_DRV_LOG(ERR, "Invalid pointer");
8211                 return -EFAULT;
8212         }
8213
8214         switch (info->info_type) {
8215         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8216                 i40e_get_symmetric_hash_enable_per_port(hw,
8217                                         &(info->info.enable));
8218                 break;
8219         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8220                 ret = i40e_get_hash_filter_global_config(hw,
8221                                 &(info->info.global_conf));
8222                 break;
8223         default:
8224                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8225                                                         info->info_type);
8226                 ret = -EINVAL;
8227                 break;
8228         }
8229
8230         return ret;
8231 }
8232
8233 static int
8234 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8235 {
8236         int ret = 0;
8237
8238         if (!hw || !info) {
8239                 PMD_DRV_LOG(ERR, "Invalid pointer");
8240                 return -EFAULT;
8241         }
8242
8243         switch (info->info_type) {
8244         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8245                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8246                 break;
8247         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8248                 ret = i40e_set_hash_filter_global_config(hw,
8249                                 &(info->info.global_conf));
8250                 break;
8251         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8252                 ret = i40e_hash_filter_inset_select(hw,
8253                                                &(info->info.input_set_conf));
8254                 break;
8255
8256         default:
8257                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8258                                                         info->info_type);
8259                 ret = -EINVAL;
8260                 break;
8261         }
8262
8263         return ret;
8264 }
8265
8266 /* Operations for hash function */
8267 static int
8268 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8269                       enum rte_filter_op filter_op,
8270                       void *arg)
8271 {
8272         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8273         int ret = 0;
8274
8275         switch (filter_op) {
8276         case RTE_ETH_FILTER_NOP:
8277                 break;
8278         case RTE_ETH_FILTER_GET:
8279                 ret = i40e_hash_filter_get(hw,
8280                         (struct rte_eth_hash_filter_info *)arg);
8281                 break;
8282         case RTE_ETH_FILTER_SET:
8283                 ret = i40e_hash_filter_set(hw,
8284                         (struct rte_eth_hash_filter_info *)arg);
8285                 break;
8286         default:
8287                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8288                                                                 filter_op);
8289                 ret = -ENOTSUP;
8290                 break;
8291         }
8292
8293         return ret;
8294 }
8295
8296 /* Convert ethertype filter structure */
8297 static int
8298 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8299                               struct i40e_ethertype_filter *filter)
8300 {
8301         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8302         filter->input.ether_type = input->ether_type;
8303         filter->flags = input->flags;
8304         filter->queue = input->queue;
8305
8306         return 0;
8307 }
8308
8309 /* Check if there exists the ehtertype filter */
8310 struct i40e_ethertype_filter *
8311 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8312                                 const struct i40e_ethertype_filter_input *input)
8313 {
8314         int ret;
8315
8316         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8317         if (ret < 0)
8318                 return NULL;
8319
8320         return ethertype_rule->hash_map[ret];
8321 }
8322
8323 /* Add ethertype filter in SW list */
8324 static int
8325 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8326                                 struct i40e_ethertype_filter *filter)
8327 {
8328         struct i40e_ethertype_rule *rule = &pf->ethertype;
8329         int ret;
8330
8331         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8332         if (ret < 0) {
8333                 PMD_DRV_LOG(ERR,
8334                             "Failed to insert ethertype filter"
8335                             " to hash table %d!",
8336                             ret);
8337                 return ret;
8338         }
8339         rule->hash_map[ret] = filter;
8340
8341         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8342
8343         return 0;
8344 }
8345
8346 /* Delete ethertype filter in SW list */
8347 int
8348 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8349                              struct i40e_ethertype_filter_input *input)
8350 {
8351         struct i40e_ethertype_rule *rule = &pf->ethertype;
8352         struct i40e_ethertype_filter *filter;
8353         int ret;
8354
8355         ret = rte_hash_del_key(rule->hash_table, input);
8356         if (ret < 0) {
8357                 PMD_DRV_LOG(ERR,
8358                             "Failed to delete ethertype filter"
8359                             " to hash table %d!",
8360                             ret);
8361                 return ret;
8362         }
8363         filter = rule->hash_map[ret];
8364         rule->hash_map[ret] = NULL;
8365
8366         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8367         rte_free(filter);
8368
8369         return 0;
8370 }
8371
8372 /*
8373  * Configure ethertype filter, which can director packet by filtering
8374  * with mac address and ether_type or only ether_type
8375  */
8376 int
8377 i40e_ethertype_filter_set(struct i40e_pf *pf,
8378                         struct rte_eth_ethertype_filter *filter,
8379                         bool add)
8380 {
8381         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8382         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8383         struct i40e_ethertype_filter *ethertype_filter, *node;
8384         struct i40e_ethertype_filter check_filter;
8385         struct i40e_control_filter_stats stats;
8386         uint16_t flags = 0;
8387         int ret;
8388
8389         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8390                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8391                 return -EINVAL;
8392         }
8393         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8394                 filter->ether_type == ETHER_TYPE_IPv6) {
8395                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8396                         " control packet filter.", filter->ether_type);
8397                 return -EINVAL;
8398         }
8399         if (filter->ether_type == ETHER_TYPE_VLAN)
8400                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8401                         " not supported.");
8402
8403         /* Check if there is the filter in SW list */
8404         memset(&check_filter, 0, sizeof(check_filter));
8405         i40e_ethertype_filter_convert(filter, &check_filter);
8406         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8407                                                &check_filter.input);
8408         if (add && node) {
8409                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8410                 return -EINVAL;
8411         }
8412
8413         if (!add && !node) {
8414                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8415                 return -EINVAL;
8416         }
8417
8418         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8419                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8420         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8421                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8422         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8423
8424         memset(&stats, 0, sizeof(stats));
8425         ret = i40e_aq_add_rem_control_packet_filter(hw,
8426                         filter->mac_addr.addr_bytes,
8427                         filter->ether_type, flags,
8428                         pf->main_vsi->seid,
8429                         filter->queue, add, &stats, NULL);
8430
8431         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8432                          " mac_etype_used = %u, etype_used = %u,"
8433                          " mac_etype_free = %u, etype_free = %u\n",
8434                          ret, stats.mac_etype_used, stats.etype_used,
8435                          stats.mac_etype_free, stats.etype_free);
8436         if (ret < 0)
8437                 return -ENOSYS;
8438
8439         /* Add or delete a filter in SW list */
8440         if (add) {
8441                 ethertype_filter = rte_zmalloc("ethertype_filter",
8442                                        sizeof(*ethertype_filter), 0);
8443                 rte_memcpy(ethertype_filter, &check_filter,
8444                            sizeof(check_filter));
8445                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8446         } else {
8447                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8448         }
8449
8450         return ret;
8451 }
8452
8453 /*
8454  * Handle operations for ethertype filter.
8455  */
8456 static int
8457 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8458                                 enum rte_filter_op filter_op,
8459                                 void *arg)
8460 {
8461         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8462         int ret = 0;
8463
8464         if (filter_op == RTE_ETH_FILTER_NOP)
8465                 return ret;
8466
8467         if (arg == NULL) {
8468                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8469                             filter_op);
8470                 return -EINVAL;
8471         }
8472
8473         switch (filter_op) {
8474         case RTE_ETH_FILTER_ADD:
8475                 ret = i40e_ethertype_filter_set(pf,
8476                         (struct rte_eth_ethertype_filter *)arg,
8477                         TRUE);
8478                 break;
8479         case RTE_ETH_FILTER_DELETE:
8480                 ret = i40e_ethertype_filter_set(pf,
8481                         (struct rte_eth_ethertype_filter *)arg,
8482                         FALSE);
8483                 break;
8484         default:
8485                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8486                 ret = -ENOSYS;
8487                 break;
8488         }
8489         return ret;
8490 }
8491
8492 static int
8493 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8494                      enum rte_filter_type filter_type,
8495                      enum rte_filter_op filter_op,
8496                      void *arg)
8497 {
8498         int ret = 0;
8499
8500         if (dev == NULL)
8501                 return -EINVAL;
8502
8503         switch (filter_type) {
8504         case RTE_ETH_FILTER_NONE:
8505                 /* For global configuration */
8506                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8507                 break;
8508         case RTE_ETH_FILTER_HASH:
8509                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8510                 break;
8511         case RTE_ETH_FILTER_MACVLAN:
8512                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8513                 break;
8514         case RTE_ETH_FILTER_ETHERTYPE:
8515                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8516                 break;
8517         case RTE_ETH_FILTER_TUNNEL:
8518                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8519                 break;
8520         case RTE_ETH_FILTER_FDIR:
8521                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8522                 break;
8523         case RTE_ETH_FILTER_GENERIC:
8524                 if (filter_op != RTE_ETH_FILTER_GET)
8525                         return -EINVAL;
8526                 *(const void **)arg = &i40e_flow_ops;
8527                 break;
8528         default:
8529                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8530                                                         filter_type);
8531                 ret = -EINVAL;
8532                 break;
8533         }
8534
8535         return ret;
8536 }
8537
8538 /*
8539  * Check and enable Extended Tag.
8540  * Enabling Extended Tag is important for 40G performance.
8541  */
8542 static void
8543 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8544 {
8545         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8546         uint32_t buf = 0;
8547         int ret;
8548
8549         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8550                                       PCI_DEV_CAP_REG);
8551         if (ret < 0) {
8552                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8553                             PCI_DEV_CAP_REG);
8554                 return;
8555         }
8556         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8557                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8558                 return;
8559         }
8560
8561         buf = 0;
8562         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8563                                       PCI_DEV_CTRL_REG);
8564         if (ret < 0) {
8565                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8566                             PCI_DEV_CTRL_REG);
8567                 return;
8568         }
8569         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8570                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8571                 return;
8572         }
8573         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8574         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8575                                        PCI_DEV_CTRL_REG);
8576         if (ret < 0) {
8577                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8578                             PCI_DEV_CTRL_REG);
8579                 return;
8580         }
8581 }
8582
8583 /*
8584  * As some registers wouldn't be reset unless a global hardware reset,
8585  * hardware initialization is needed to put those registers into an
8586  * expected initial state.
8587  */
8588 static void
8589 i40e_hw_init(struct rte_eth_dev *dev)
8590 {
8591         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8592
8593         i40e_enable_extended_tag(dev);
8594
8595         /* clear the PF Queue Filter control register */
8596         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8597
8598         /* Disable symmetric hash per port */
8599         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8600 }
8601
8602 enum i40e_filter_pctype
8603 i40e_flowtype_to_pctype(uint16_t flow_type)
8604 {
8605         static const enum i40e_filter_pctype pctype_table[] = {
8606                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8607                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8608                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8609                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8610                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8611                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8612                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8613                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8614                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8615                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8616                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8617                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8618                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8619                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8620                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8621                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8622                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8623                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8624                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8625         };
8626
8627         return pctype_table[flow_type];
8628 }
8629
8630 uint16_t
8631 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8632 {
8633         static const uint16_t flowtype_table[] = {
8634                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8635                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8636                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8637                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8638                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8639                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8640                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8641                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8642                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8643                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8644                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8645                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8646                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8647                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8648                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8649                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8650                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8651                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8652                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8653                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8654                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8655                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8656                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8657                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8658                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8659                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8660                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8661                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8662                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8663                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8664                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8665         };
8666
8667         return flowtype_table[pctype];
8668 }
8669
8670 /*
8671  * On X710, performance number is far from the expectation on recent firmware
8672  * versions; on XL710, performance number is also far from the expectation on
8673  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8674  * mode is enabled and port MAC address is equal to the packet destination MAC
8675  * address. The fix for this issue may not be integrated in the following
8676  * firmware version. So the workaround in software driver is needed. It needs
8677  * to modify the initial values of 3 internal only registers for both X710 and
8678  * XL710. Note that the values for X710 or XL710 could be different, and the
8679  * workaround can be removed when it is fixed in firmware in the future.
8680  */
8681
8682 /* For both X710 and XL710 */
8683 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8684 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8685
8686 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8687 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8688
8689 /* For X710 */
8690 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8691 /* For XL710 */
8692 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8693 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8694
8695 static int
8696 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8697 {
8698         enum i40e_status_code status;
8699         struct i40e_aq_get_phy_abilities_resp phy_ab;
8700         int ret = -ENOTSUP;
8701
8702         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8703                                               NULL);
8704
8705         if (status)
8706                 return ret;
8707
8708         return 0;
8709 }
8710
8711
8712 static void
8713 i40e_configure_registers(struct i40e_hw *hw)
8714 {
8715         static struct {
8716                 uint32_t addr;
8717                 uint64_t val;
8718         } reg_table[] = {
8719                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8720                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8721                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8722         };
8723         uint64_t reg;
8724         uint32_t i;
8725         int ret;
8726
8727         for (i = 0; i < RTE_DIM(reg_table); i++) {
8728                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8729                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8730                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8731                                 reg_table[i].val =
8732                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8733                         else /* For X710 */
8734                                 reg_table[i].val =
8735                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8736                 }
8737
8738                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8739                                                         &reg, NULL);
8740                 if (ret < 0) {
8741                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8742                                                         reg_table[i].addr);
8743                         break;
8744                 }
8745                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8746                                                 reg_table[i].addr, reg);
8747                 if (reg == reg_table[i].val)
8748                         continue;
8749
8750                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8751                                                 reg_table[i].val, NULL);
8752                 if (ret < 0) {
8753                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8754                                 "address of 0x%"PRIx32, reg_table[i].val,
8755                                                         reg_table[i].addr);
8756                         break;
8757                 }
8758                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8759                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8760         }
8761 }
8762
8763 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8764 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8765 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8766 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8767 static int
8768 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8769 {
8770         uint32_t reg;
8771         int ret;
8772
8773         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8774                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8775                 return -EINVAL;
8776         }
8777
8778         /* Configure for double VLAN RX stripping */
8779         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8780         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8781                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8782                 ret = i40e_aq_debug_write_register(hw,
8783                                                    I40E_VSI_TSR(vsi->vsi_id),
8784                                                    reg, NULL);
8785                 if (ret < 0) {
8786                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8787                                     vsi->vsi_id);
8788                         return I40E_ERR_CONFIG;
8789                 }
8790         }
8791
8792         /* Configure for double VLAN TX insertion */
8793         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8794         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8795                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8796                 ret = i40e_aq_debug_write_register(hw,
8797                                                    I40E_VSI_L2TAGSTXVALID(
8798                                                    vsi->vsi_id), reg, NULL);
8799                 if (ret < 0) {
8800                         PMD_DRV_LOG(ERR, "Failed to update "
8801                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8802                         return I40E_ERR_CONFIG;
8803                 }
8804         }
8805
8806         return 0;
8807 }
8808
8809 /**
8810  * i40e_aq_add_mirror_rule
8811  * @hw: pointer to the hardware structure
8812  * @seid: VEB seid to add mirror rule to
8813  * @dst_id: destination vsi seid
8814  * @entries: Buffer which contains the entities to be mirrored
8815  * @count: number of entities contained in the buffer
8816  * @rule_id:the rule_id of the rule to be added
8817  *
8818  * Add a mirror rule for a given veb.
8819  *
8820  **/
8821 static enum i40e_status_code
8822 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8823                         uint16_t seid, uint16_t dst_id,
8824                         uint16_t rule_type, uint16_t *entries,
8825                         uint16_t count, uint16_t *rule_id)
8826 {
8827         struct i40e_aq_desc desc;
8828         struct i40e_aqc_add_delete_mirror_rule cmd;
8829         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8830                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8831                 &desc.params.raw;
8832         uint16_t buff_len;
8833         enum i40e_status_code status;
8834
8835         i40e_fill_default_direct_cmd_desc(&desc,
8836                                           i40e_aqc_opc_add_mirror_rule);
8837         memset(&cmd, 0, sizeof(cmd));
8838
8839         buff_len = sizeof(uint16_t) * count;
8840         desc.datalen = rte_cpu_to_le_16(buff_len);
8841         if (buff_len > 0)
8842                 desc.flags |= rte_cpu_to_le_16(
8843                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8844         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8845                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8846         cmd.num_entries = rte_cpu_to_le_16(count);
8847         cmd.seid = rte_cpu_to_le_16(seid);
8848         cmd.destination = rte_cpu_to_le_16(dst_id);
8849
8850         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8851         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8852         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8853                          "rule_id = %u"
8854                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8855                          hw->aq.asq_last_status, resp->rule_id,
8856                          resp->mirror_rules_used, resp->mirror_rules_free);
8857         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8858
8859         return status;
8860 }
8861
8862 /**
8863  * i40e_aq_del_mirror_rule
8864  * @hw: pointer to the hardware structure
8865  * @seid: VEB seid to add mirror rule to
8866  * @entries: Buffer which contains the entities to be mirrored
8867  * @count: number of entities contained in the buffer
8868  * @rule_id:the rule_id of the rule to be delete
8869  *
8870  * Delete a mirror rule for a given veb.
8871  *
8872  **/
8873 static enum i40e_status_code
8874 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8875                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8876                 uint16_t count, uint16_t rule_id)
8877 {
8878         struct i40e_aq_desc desc;
8879         struct i40e_aqc_add_delete_mirror_rule cmd;
8880         uint16_t buff_len = 0;
8881         enum i40e_status_code status;
8882         void *buff = NULL;
8883
8884         i40e_fill_default_direct_cmd_desc(&desc,
8885                                           i40e_aqc_opc_delete_mirror_rule);
8886         memset(&cmd, 0, sizeof(cmd));
8887         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8888                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8889                                                           I40E_AQ_FLAG_RD));
8890                 cmd.num_entries = count;
8891                 buff_len = sizeof(uint16_t) * count;
8892                 desc.datalen = rte_cpu_to_le_16(buff_len);
8893                 buff = (void *)entries;
8894         } else
8895                 /* rule id is filled in destination field for deleting mirror rule */
8896                 cmd.destination = rte_cpu_to_le_16(rule_id);
8897
8898         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8899                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8900         cmd.seid = rte_cpu_to_le_16(seid);
8901
8902         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8903         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8904
8905         return status;
8906 }
8907
8908 /**
8909  * i40e_mirror_rule_set
8910  * @dev: pointer to the hardware structure
8911  * @mirror_conf: mirror rule info
8912  * @sw_id: mirror rule's sw_id
8913  * @on: enable/disable
8914  *
8915  * set a mirror rule.
8916  *
8917  **/
8918 static int
8919 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8920                         struct rte_eth_mirror_conf *mirror_conf,
8921                         uint8_t sw_id, uint8_t on)
8922 {
8923         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8924         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8925         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8926         struct i40e_mirror_rule *parent = NULL;
8927         uint16_t seid, dst_seid, rule_id;
8928         uint16_t i, j = 0;
8929         int ret;
8930
8931         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8932
8933         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8934                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8935                         " without veb or vfs.");
8936                 return -ENOSYS;
8937         }
8938         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8939                 PMD_DRV_LOG(ERR, "mirror table is full.");
8940                 return -ENOSPC;
8941         }
8942         if (mirror_conf->dst_pool > pf->vf_num) {
8943                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8944                                  mirror_conf->dst_pool);
8945                 return -EINVAL;
8946         }
8947
8948         seid = pf->main_vsi->veb->seid;
8949
8950         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8951                 if (sw_id <= it->index) {
8952                         mirr_rule = it;
8953                         break;
8954                 }
8955                 parent = it;
8956         }
8957         if (mirr_rule && sw_id == mirr_rule->index) {
8958                 if (on) {
8959                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8960                         return -EEXIST;
8961                 } else {
8962                         ret = i40e_aq_del_mirror_rule(hw, seid,
8963                                         mirr_rule->rule_type,
8964                                         mirr_rule->entries,
8965                                         mirr_rule->num_entries, mirr_rule->id);
8966                         if (ret < 0) {
8967                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8968                                                    " ret = %d, aq_err = %d.",
8969                                                    ret, hw->aq.asq_last_status);
8970                                 return -ENOSYS;
8971                         }
8972                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8973                         rte_free(mirr_rule);
8974                         pf->nb_mirror_rule--;
8975                         return 0;
8976                 }
8977         } else if (!on) {
8978                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8979                 return -ENOENT;
8980         }
8981
8982         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8983                                 sizeof(struct i40e_mirror_rule) , 0);
8984         if (!mirr_rule) {
8985                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8986                 return I40E_ERR_NO_MEMORY;
8987         }
8988         switch (mirror_conf->rule_type) {
8989         case ETH_MIRROR_VLAN:
8990                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8991                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8992                                 mirr_rule->entries[j] =
8993                                         mirror_conf->vlan.vlan_id[i];
8994                                 j++;
8995                         }
8996                 }
8997                 if (j == 0) {
8998                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8999                         rte_free(mirr_rule);
9000                         return -EINVAL;
9001                 }
9002                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9003                 break;
9004         case ETH_MIRROR_VIRTUAL_POOL_UP:
9005         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9006                 /* check if the specified pool bit is out of range */
9007                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9008                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9009                         rte_free(mirr_rule);
9010                         return -EINVAL;
9011                 }
9012                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9013                         if (mirror_conf->pool_mask & (1ULL << i)) {
9014                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9015                                 j++;
9016                         }
9017                 }
9018                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9019                         /* add pf vsi to entries */
9020                         mirr_rule->entries[j] = pf->main_vsi_seid;
9021                         j++;
9022                 }
9023                 if (j == 0) {
9024                         PMD_DRV_LOG(ERR, "pool is not specified.");
9025                         rte_free(mirr_rule);
9026                         return -EINVAL;
9027                 }
9028                 /* egress and ingress in aq commands means from switch but not port */
9029                 mirr_rule->rule_type =
9030                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9031                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9032                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9033                 break;
9034         case ETH_MIRROR_UPLINK_PORT:
9035                 /* egress and ingress in aq commands means from switch but not port*/
9036                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9037                 break;
9038         case ETH_MIRROR_DOWNLINK_PORT:
9039                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9040                 break;
9041         default:
9042                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9043                         mirror_conf->rule_type);
9044                 rte_free(mirr_rule);
9045                 return -EINVAL;
9046         }
9047
9048         /* If the dst_pool is equal to vf_num, consider it as PF */
9049         if (mirror_conf->dst_pool == pf->vf_num)
9050                 dst_seid = pf->main_vsi_seid;
9051         else
9052                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9053
9054         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9055                                       mirr_rule->rule_type, mirr_rule->entries,
9056                                       j, &rule_id);
9057         if (ret < 0) {
9058                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
9059                                    " ret = %d, aq_err = %d.",
9060                                    ret, hw->aq.asq_last_status);
9061                 rte_free(mirr_rule);
9062                 return -ENOSYS;
9063         }
9064
9065         mirr_rule->index = sw_id;
9066         mirr_rule->num_entries = j;
9067         mirr_rule->id = rule_id;
9068         mirr_rule->dst_vsi_seid = dst_seid;
9069
9070         if (parent)
9071                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9072         else
9073                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9074
9075         pf->nb_mirror_rule++;
9076         return 0;
9077 }
9078
9079 /**
9080  * i40e_mirror_rule_reset
9081  * @dev: pointer to the device
9082  * @sw_id: mirror rule's sw_id
9083  *
9084  * reset a mirror rule.
9085  *
9086  **/
9087 static int
9088 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9089 {
9090         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9091         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9092         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9093         uint16_t seid;
9094         int ret;
9095
9096         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9097
9098         seid = pf->main_vsi->veb->seid;
9099
9100         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9101                 if (sw_id == it->index) {
9102                         mirr_rule = it;
9103                         break;
9104                 }
9105         }
9106         if (mirr_rule) {
9107                 ret = i40e_aq_del_mirror_rule(hw, seid,
9108                                 mirr_rule->rule_type,
9109                                 mirr_rule->entries,
9110                                 mirr_rule->num_entries, mirr_rule->id);
9111                 if (ret < 0) {
9112                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
9113                                            " status = %d, aq_err = %d.",
9114                                            ret, hw->aq.asq_last_status);
9115                         return -ENOSYS;
9116                 }
9117                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9118                 rte_free(mirr_rule);
9119                 pf->nb_mirror_rule--;
9120         } else {
9121                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9122                 return -ENOENT;
9123         }
9124         return 0;
9125 }
9126
9127 static uint64_t
9128 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9129 {
9130         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9131         uint64_t systim_cycles;
9132
9133         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9134         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9135                         << 32;
9136
9137         return systim_cycles;
9138 }
9139
9140 static uint64_t
9141 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9142 {
9143         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9144         uint64_t rx_tstamp;
9145
9146         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9147         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9148                         << 32;
9149
9150         return rx_tstamp;
9151 }
9152
9153 static uint64_t
9154 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9155 {
9156         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9157         uint64_t tx_tstamp;
9158
9159         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9160         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9161                         << 32;
9162
9163         return tx_tstamp;
9164 }
9165
9166 static void
9167 i40e_start_timecounters(struct rte_eth_dev *dev)
9168 {
9169         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9170         struct i40e_adapter *adapter =
9171                         (struct i40e_adapter *)dev->data->dev_private;
9172         struct rte_eth_link link;
9173         uint32_t tsync_inc_l;
9174         uint32_t tsync_inc_h;
9175
9176         /* Get current link speed. */
9177         memset(&link, 0, sizeof(link));
9178         i40e_dev_link_update(dev, 1);
9179         rte_i40e_dev_atomic_read_link_status(dev, &link);
9180
9181         switch (link.link_speed) {
9182         case ETH_SPEED_NUM_40G:
9183                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9184                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9185                 break;
9186         case ETH_SPEED_NUM_10G:
9187                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9188                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9189                 break;
9190         case ETH_SPEED_NUM_1G:
9191                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9192                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9193                 break;
9194         default:
9195                 tsync_inc_l = 0x0;
9196                 tsync_inc_h = 0x0;
9197         }
9198
9199         /* Set the timesync increment value. */
9200         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9201         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9202
9203         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9204         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9205         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9206
9207         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9208         adapter->systime_tc.cc_shift = 0;
9209         adapter->systime_tc.nsec_mask = 0;
9210
9211         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9212         adapter->rx_tstamp_tc.cc_shift = 0;
9213         adapter->rx_tstamp_tc.nsec_mask = 0;
9214
9215         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9216         adapter->tx_tstamp_tc.cc_shift = 0;
9217         adapter->tx_tstamp_tc.nsec_mask = 0;
9218 }
9219
9220 static int
9221 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9222 {
9223         struct i40e_adapter *adapter =
9224                         (struct i40e_adapter *)dev->data->dev_private;
9225
9226         adapter->systime_tc.nsec += delta;
9227         adapter->rx_tstamp_tc.nsec += delta;
9228         adapter->tx_tstamp_tc.nsec += delta;
9229
9230         return 0;
9231 }
9232
9233 static int
9234 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9235 {
9236         uint64_t ns;
9237         struct i40e_adapter *adapter =
9238                         (struct i40e_adapter *)dev->data->dev_private;
9239
9240         ns = rte_timespec_to_ns(ts);
9241
9242         /* Set the timecounters to a new value. */
9243         adapter->systime_tc.nsec = ns;
9244         adapter->rx_tstamp_tc.nsec = ns;
9245         adapter->tx_tstamp_tc.nsec = ns;
9246
9247         return 0;
9248 }
9249
9250 static int
9251 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9252 {
9253         uint64_t ns, systime_cycles;
9254         struct i40e_adapter *adapter =
9255                         (struct i40e_adapter *)dev->data->dev_private;
9256
9257         systime_cycles = i40e_read_systime_cyclecounter(dev);
9258         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9259         *ts = rte_ns_to_timespec(ns);
9260
9261         return 0;
9262 }
9263
9264 static int
9265 i40e_timesync_enable(struct rte_eth_dev *dev)
9266 {
9267         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9268         uint32_t tsync_ctl_l;
9269         uint32_t tsync_ctl_h;
9270
9271         /* Stop the timesync system time. */
9272         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9273         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9274         /* Reset the timesync system time value. */
9275         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9276         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9277
9278         i40e_start_timecounters(dev);
9279
9280         /* Clear timesync registers. */
9281         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9282         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9283         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9284         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9285         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9286         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9287
9288         /* Enable timestamping of PTP packets. */
9289         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9290         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9291
9292         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9293         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9294         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9295
9296         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9297         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9298
9299         return 0;
9300 }
9301
9302 static int
9303 i40e_timesync_disable(struct rte_eth_dev *dev)
9304 {
9305         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9306         uint32_t tsync_ctl_l;
9307         uint32_t tsync_ctl_h;
9308
9309         /* Disable timestamping of transmitted PTP packets. */
9310         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9311         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9312
9313         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9314         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9315
9316         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9317         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9318
9319         /* Reset the timesync increment value. */
9320         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9321         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9322
9323         return 0;
9324 }
9325
9326 static int
9327 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9328                                 struct timespec *timestamp, uint32_t flags)
9329 {
9330         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9331         struct i40e_adapter *adapter =
9332                 (struct i40e_adapter *)dev->data->dev_private;
9333
9334         uint32_t sync_status;
9335         uint32_t index = flags & 0x03;
9336         uint64_t rx_tstamp_cycles;
9337         uint64_t ns;
9338
9339         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9340         if ((sync_status & (1 << index)) == 0)
9341                 return -EINVAL;
9342
9343         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9344         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9345         *timestamp = rte_ns_to_timespec(ns);
9346
9347         return 0;
9348 }
9349
9350 static int
9351 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9352                                 struct timespec *timestamp)
9353 {
9354         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9355         struct i40e_adapter *adapter =
9356                 (struct i40e_adapter *)dev->data->dev_private;
9357
9358         uint32_t sync_status;
9359         uint64_t tx_tstamp_cycles;
9360         uint64_t ns;
9361
9362         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9363         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9364                 return -EINVAL;
9365
9366         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9367         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9368         *timestamp = rte_ns_to_timespec(ns);
9369
9370         return 0;
9371 }
9372
9373 /*
9374  * i40e_parse_dcb_configure - parse dcb configure from user
9375  * @dev: the device being configured
9376  * @dcb_cfg: pointer of the result of parse
9377  * @*tc_map: bit map of enabled traffic classes
9378  *
9379  * Returns 0 on success, negative value on failure
9380  */
9381 static int
9382 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9383                          struct i40e_dcbx_config *dcb_cfg,
9384                          uint8_t *tc_map)
9385 {
9386         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9387         uint8_t i, tc_bw, bw_lf;
9388
9389         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9390
9391         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9392         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9393                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9394                 return -EINVAL;
9395         }
9396
9397         /* assume each tc has the same bw */
9398         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9399         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9400                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9401         /* to ensure the sum of tcbw is equal to 100 */
9402         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9403         for (i = 0; i < bw_lf; i++)
9404                 dcb_cfg->etscfg.tcbwtable[i]++;
9405
9406         /* assume each tc has the same Transmission Selection Algorithm */
9407         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9408                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9409
9410         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9411                 dcb_cfg->etscfg.prioritytable[i] =
9412                                 dcb_rx_conf->dcb_tc[i];
9413
9414         /* FW needs one App to configure HW */
9415         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9416         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9417         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9418         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9419
9420         if (dcb_rx_conf->nb_tcs == 0)
9421                 *tc_map = 1; /* tc0 only */
9422         else
9423                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9424
9425         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9426                 dcb_cfg->pfc.willing = 0;
9427                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9428                 dcb_cfg->pfc.pfcenable = *tc_map;
9429         }
9430         return 0;
9431 }
9432
9433
9434 static enum i40e_status_code
9435 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9436                               struct i40e_aqc_vsi_properties_data *info,
9437                               uint8_t enabled_tcmap)
9438 {
9439         enum i40e_status_code ret;
9440         int i, total_tc = 0;
9441         uint16_t qpnum_per_tc, bsf, qp_idx;
9442         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9443         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9444         uint16_t used_queues;
9445
9446         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9447         if (ret != I40E_SUCCESS)
9448                 return ret;
9449
9450         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9451                 if (enabled_tcmap & (1 << i))
9452                         total_tc++;
9453         }
9454         if (total_tc == 0)
9455                 total_tc = 1;
9456         vsi->enabled_tc = enabled_tcmap;
9457
9458         /* different VSI has different queues assigned */
9459         if (vsi->type == I40E_VSI_MAIN)
9460                 used_queues = dev_data->nb_rx_queues -
9461                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9462         else if (vsi->type == I40E_VSI_VMDQ2)
9463                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9464         else {
9465                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9466                 return I40E_ERR_NO_AVAILABLE_VSI;
9467         }
9468
9469         qpnum_per_tc = used_queues / total_tc;
9470         /* Number of queues per enabled TC */
9471         if (qpnum_per_tc == 0) {
9472                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9473                 return I40E_ERR_INVALID_QP_ID;
9474         }
9475         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9476                                 I40E_MAX_Q_PER_TC);
9477         bsf = rte_bsf32(qpnum_per_tc);
9478
9479         /**
9480          * Configure TC and queue mapping parameters, for enabled TC,
9481          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9482          * default queue will serve it.
9483          */
9484         qp_idx = 0;
9485         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9486                 if (vsi->enabled_tc & (1 << i)) {
9487                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9488                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9489                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9490                         qp_idx += qpnum_per_tc;
9491                 } else
9492                         info->tc_mapping[i] = 0;
9493         }
9494
9495         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9496         if (vsi->type == I40E_VSI_SRIOV) {
9497                 info->mapping_flags |=
9498                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9499                 for (i = 0; i < vsi->nb_qps; i++)
9500                         info->queue_mapping[i] =
9501                                 rte_cpu_to_le_16(vsi->base_queue + i);
9502         } else {
9503                 info->mapping_flags |=
9504                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9505                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9506         }
9507         info->valid_sections |=
9508                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9509
9510         return I40E_SUCCESS;
9511 }
9512
9513 /*
9514  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9515  * @veb: VEB to be configured
9516  * @tc_map: enabled TC bitmap
9517  *
9518  * Returns 0 on success, negative value on failure
9519  */
9520 static enum i40e_status_code
9521 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9522 {
9523         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9524         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9525         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9526         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9527         enum i40e_status_code ret = I40E_SUCCESS;
9528         int i;
9529         uint32_t bw_max;
9530
9531         /* Check if enabled_tc is same as existing or new TCs */
9532         if (veb->enabled_tc == tc_map)
9533                 return ret;
9534
9535         /* configure tc bandwidth */
9536         memset(&veb_bw, 0, sizeof(veb_bw));
9537         veb_bw.tc_valid_bits = tc_map;
9538         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9539         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9540                 if (tc_map & BIT_ULL(i))
9541                         veb_bw.tc_bw_share_credits[i] = 1;
9542         }
9543         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9544                                                    &veb_bw, NULL);
9545         if (ret) {
9546                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9547                                   " per TC failed = %d",
9548                                   hw->aq.asq_last_status);
9549                 return ret;
9550         }
9551
9552         memset(&ets_query, 0, sizeof(ets_query));
9553         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9554                                                    &ets_query, NULL);
9555         if (ret != I40E_SUCCESS) {
9556                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9557                                  " configuration %u", hw->aq.asq_last_status);
9558                 return ret;
9559         }
9560         memset(&bw_query, 0, sizeof(bw_query));
9561         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9562                                                   &bw_query, NULL);
9563         if (ret != I40E_SUCCESS) {
9564                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9565                                  " configuration %u", hw->aq.asq_last_status);
9566                 return ret;
9567         }
9568
9569         /* store and print out BW info */
9570         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9571         veb->bw_info.bw_max = ets_query.tc_bw_max;
9572         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9573         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9574         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9575                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9576                      I40E_16_BIT_WIDTH);
9577         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9578                 veb->bw_info.bw_ets_share_credits[i] =
9579                                 bw_query.tc_bw_share_credits[i];
9580                 veb->bw_info.bw_ets_credits[i] =
9581                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9582                 /* 4 bits per TC, 4th bit is reserved */
9583                 veb->bw_info.bw_ets_max[i] =
9584                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9585                                   RTE_LEN2MASK(3, uint8_t));
9586                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9587                             veb->bw_info.bw_ets_share_credits[i]);
9588                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9589                             veb->bw_info.bw_ets_credits[i]);
9590                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9591                             veb->bw_info.bw_ets_max[i]);
9592         }
9593
9594         veb->enabled_tc = tc_map;
9595
9596         return ret;
9597 }
9598
9599
9600 /*
9601  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9602  * @vsi: VSI to be configured
9603  * @tc_map: enabled TC bitmap
9604  *
9605  * Returns 0 on success, negative value on failure
9606  */
9607 static enum i40e_status_code
9608 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9609 {
9610         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9611         struct i40e_vsi_context ctxt;
9612         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9613         enum i40e_status_code ret = I40E_SUCCESS;
9614         int i;
9615
9616         /* Check if enabled_tc is same as existing or new TCs */
9617         if (vsi->enabled_tc == tc_map)
9618                 return ret;
9619
9620         /* configure tc bandwidth */
9621         memset(&bw_data, 0, sizeof(bw_data));
9622         bw_data.tc_valid_bits = tc_map;
9623         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9624         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9625                 if (tc_map & BIT_ULL(i))
9626                         bw_data.tc_bw_credits[i] = 1;
9627         }
9628         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9629         if (ret) {
9630                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9631                         " per TC failed = %d",
9632                         hw->aq.asq_last_status);
9633                 goto out;
9634         }
9635         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9636                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9637
9638         /* Update Queue Pairs Mapping for currently enabled UPs */
9639         ctxt.seid = vsi->seid;
9640         ctxt.pf_num = hw->pf_id;
9641         ctxt.vf_num = 0;
9642         ctxt.uplink_seid = vsi->uplink_seid;
9643         ctxt.info = vsi->info;
9644         i40e_get_cap(hw);
9645         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9646         if (ret)
9647                 goto out;
9648
9649         /* Update the VSI after updating the VSI queue-mapping information */
9650         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9651         if (ret) {
9652                 PMD_INIT_LOG(ERR, "Failed to configure "
9653                             "TC queue mapping = %d",
9654                             hw->aq.asq_last_status);
9655                 goto out;
9656         }
9657         /* update the local VSI info with updated queue map */
9658         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9659                                         sizeof(vsi->info.tc_mapping));
9660         (void)rte_memcpy(&vsi->info.queue_mapping,
9661                         &ctxt.info.queue_mapping,
9662                 sizeof(vsi->info.queue_mapping));
9663         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9664         vsi->info.valid_sections = 0;
9665
9666         /* query and update current VSI BW information */
9667         ret = i40e_vsi_get_bw_config(vsi);
9668         if (ret) {
9669                 PMD_INIT_LOG(ERR,
9670                          "Failed updating vsi bw info, err %s aq_err %s",
9671                          i40e_stat_str(hw, ret),
9672                          i40e_aq_str(hw, hw->aq.asq_last_status));
9673                 goto out;
9674         }
9675
9676         vsi->enabled_tc = tc_map;
9677
9678 out:
9679         return ret;
9680 }
9681
9682 /*
9683  * i40e_dcb_hw_configure - program the dcb setting to hw
9684  * @pf: pf the configuration is taken on
9685  * @new_cfg: new configuration
9686  * @tc_map: enabled TC bitmap
9687  *
9688  * Returns 0 on success, negative value on failure
9689  */
9690 static enum i40e_status_code
9691 i40e_dcb_hw_configure(struct i40e_pf *pf,
9692                       struct i40e_dcbx_config *new_cfg,
9693                       uint8_t tc_map)
9694 {
9695         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9696         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9697         struct i40e_vsi *main_vsi = pf->main_vsi;
9698         struct i40e_vsi_list *vsi_list;
9699         enum i40e_status_code ret;
9700         int i;
9701         uint32_t val;
9702
9703         /* Use the FW API if FW > v4.4*/
9704         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9705               (hw->aq.fw_maj_ver >= 5))) {
9706                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9707                                   " to configure DCB");
9708                 return I40E_ERR_FIRMWARE_API_VERSION;
9709         }
9710
9711         /* Check if need reconfiguration */
9712         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9713                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9714                 return I40E_SUCCESS;
9715         }
9716
9717         /* Copy the new config to the current config */
9718         *old_cfg = *new_cfg;
9719         old_cfg->etsrec = old_cfg->etscfg;
9720         ret = i40e_set_dcb_config(hw);
9721         if (ret) {
9722                 PMD_INIT_LOG(ERR,
9723                          "Set DCB Config failed, err %s aq_err %s\n",
9724                          i40e_stat_str(hw, ret),
9725                          i40e_aq_str(hw, hw->aq.asq_last_status));
9726                 return ret;
9727         }
9728         /* set receive Arbiter to RR mode and ETS scheme by default */
9729         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9730                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9731                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9732                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9733                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9734                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9735                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9736                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9737                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9738                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9739                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9740                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9741                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9742         }
9743         /* get local mib to check whether it is configured correctly */
9744         /* IEEE mode */
9745         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9746         /* Get Local DCB Config */
9747         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9748                                      &hw->local_dcbx_config);
9749
9750         /* if Veb is created, need to update TC of it at first */
9751         if (main_vsi->veb) {
9752                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9753                 if (ret)
9754                         PMD_INIT_LOG(WARNING,
9755                                  "Failed configuring TC for VEB seid=%d\n",
9756                                  main_vsi->veb->seid);
9757         }
9758         /* Update each VSI */
9759         i40e_vsi_config_tc(main_vsi, tc_map);
9760         if (main_vsi->veb) {
9761                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9762                         /* Beside main VSI and VMDQ VSIs, only enable default
9763                          * TC for other VSIs
9764                          */
9765                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9766                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9767                                                          tc_map);
9768                         else
9769                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9770                                                          I40E_DEFAULT_TCMAP);
9771                         if (ret)
9772                                 PMD_INIT_LOG(WARNING,
9773                                          "Failed configuring TC for VSI seid=%d\n",
9774                                          vsi_list->vsi->seid);
9775                         /* continue */
9776                 }
9777         }
9778         return I40E_SUCCESS;
9779 }
9780
9781 /*
9782  * i40e_dcb_init_configure - initial dcb config
9783  * @dev: device being configured
9784  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9785  *
9786  * Returns 0 on success, negative value on failure
9787  */
9788 static int
9789 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9790 {
9791         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9792         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9793         int ret = 0;
9794
9795         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9796                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9797                 return -ENOTSUP;
9798         }
9799
9800         /* DCB initialization:
9801          * Update DCB configuration from the Firmware and configure
9802          * LLDP MIB change event.
9803          */
9804         if (sw_dcb == TRUE) {
9805                 ret = i40e_init_dcb(hw);
9806                 /* If lldp agent is stopped, the return value from
9807                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9808                  * adminq status. Otherwise, it should return success.
9809                  */
9810                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9811                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9812                         memset(&hw->local_dcbx_config, 0,
9813                                 sizeof(struct i40e_dcbx_config));
9814                         /* set dcb default configuration */
9815                         hw->local_dcbx_config.etscfg.willing = 0;
9816                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9817                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9818                         hw->local_dcbx_config.etscfg.tsatable[0] =
9819                                                 I40E_IEEE_TSA_ETS;
9820                         hw->local_dcbx_config.etsrec =
9821                                 hw->local_dcbx_config.etscfg;
9822                         hw->local_dcbx_config.pfc.willing = 0;
9823                         hw->local_dcbx_config.pfc.pfccap =
9824                                                 I40E_MAX_TRAFFIC_CLASS;
9825                         /* FW needs one App to configure HW */
9826                         hw->local_dcbx_config.numapps = 1;
9827                         hw->local_dcbx_config.app[0].selector =
9828                                                 I40E_APP_SEL_ETHTYPE;
9829                         hw->local_dcbx_config.app[0].priority = 3;
9830                         hw->local_dcbx_config.app[0].protocolid =
9831                                                 I40E_APP_PROTOID_FCOE;
9832                         ret = i40e_set_dcb_config(hw);
9833                         if (ret) {
9834                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9835                                         " err = %d, aq_err = %d.", ret,
9836                                           hw->aq.asq_last_status);
9837                                 return -ENOSYS;
9838                         }
9839                 } else {
9840                         PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9841                                           " err = %d, aq_err = %d.", ret,
9842                                           hw->aq.asq_last_status);
9843                         return -ENOTSUP;
9844                 }
9845         } else {
9846                 ret = i40e_aq_start_lldp(hw, NULL);
9847                 if (ret != I40E_SUCCESS)
9848                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9849
9850                 ret = i40e_init_dcb(hw);
9851                 if (!ret) {
9852                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9853                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9854                                                   " DCBX offload.");
9855                                 return -ENOTSUP;
9856                         }
9857                 } else {
9858                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9859                                           " aq_err = %d.", ret,
9860                                           hw->aq.asq_last_status);
9861                         return -ENOTSUP;
9862                 }
9863         }
9864         return 0;
9865 }
9866
9867 /*
9868  * i40e_dcb_setup - setup dcb related config
9869  * @dev: device being configured
9870  *
9871  * Returns 0 on success, negative value on failure
9872  */
9873 static int
9874 i40e_dcb_setup(struct rte_eth_dev *dev)
9875 {
9876         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9877         struct i40e_dcbx_config dcb_cfg;
9878         uint8_t tc_map = 0;
9879         int ret = 0;
9880
9881         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9882                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9883                 return -ENOTSUP;
9884         }
9885
9886         if (pf->vf_num != 0)
9887                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9888
9889         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9890         if (ret) {
9891                 PMD_INIT_LOG(ERR, "invalid dcb config");
9892                 return -EINVAL;
9893         }
9894         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9895         if (ret) {
9896                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9897                 return -ENOSYS;
9898         }
9899
9900         return 0;
9901 }
9902
9903 static int
9904 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9905                       struct rte_eth_dcb_info *dcb_info)
9906 {
9907         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9908         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9909         struct i40e_vsi *vsi = pf->main_vsi;
9910         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9911         uint16_t bsf, tc_mapping;
9912         int i, j = 0;
9913
9914         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9915                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9916         else
9917                 dcb_info->nb_tcs = 1;
9918         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9919                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9920         for (i = 0; i < dcb_info->nb_tcs; i++)
9921                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9922
9923         /* get queue mapping if vmdq is disabled */
9924         if (!pf->nb_cfg_vmdq_vsi) {
9925                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9926                         if (!(vsi->enabled_tc & (1 << i)))
9927                                 continue;
9928                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9929                         dcb_info->tc_queue.tc_rxq[j][i].base =
9930                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9931                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9932                         dcb_info->tc_queue.tc_txq[j][i].base =
9933                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9934                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9935                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9936                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9937                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9938                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9939                 }
9940                 return 0;
9941         }
9942
9943         /* get queue mapping if vmdq is enabled */
9944         do {
9945                 vsi = pf->vmdq[j].vsi;
9946                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9947                         if (!(vsi->enabled_tc & (1 << i)))
9948                                 continue;
9949                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9950                         dcb_info->tc_queue.tc_rxq[j][i].base =
9951                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9952                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9953                         dcb_info->tc_queue.tc_txq[j][i].base =
9954                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9955                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9956                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9957                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9958                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9959                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9960                 }
9961                 j++;
9962         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9963         return 0;
9964 }
9965
9966 static int
9967 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9968 {
9969         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9970         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
9971         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9972         uint16_t interval =
9973                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9974         uint16_t msix_intr;
9975
9976         msix_intr = intr_handle->intr_vec[queue_id];
9977         if (msix_intr == I40E_MISC_VEC_ID)
9978                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9979                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9980                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9981                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9982                                (interval <<
9983                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9984         else
9985                 I40E_WRITE_REG(hw,
9986                                I40E_PFINT_DYN_CTLN(msix_intr -
9987                                                    I40E_RX_VEC_START),
9988                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9989                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9990                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9991                                (interval <<
9992                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9993
9994         I40E_WRITE_FLUSH(hw);
9995         rte_intr_enable(&pci_dev->intr_handle);
9996
9997         return 0;
9998 }
9999
10000 static int
10001 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10002 {
10003         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10004         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10005         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10006         uint16_t msix_intr;
10007
10008         msix_intr = intr_handle->intr_vec[queue_id];
10009         if (msix_intr == I40E_MISC_VEC_ID)
10010                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10011         else
10012                 I40E_WRITE_REG(hw,
10013                                I40E_PFINT_DYN_CTLN(msix_intr -
10014                                                    I40E_RX_VEC_START),
10015                                0);
10016         I40E_WRITE_FLUSH(hw);
10017
10018         return 0;
10019 }
10020
10021 static int i40e_get_regs(struct rte_eth_dev *dev,
10022                          struct rte_dev_reg_info *regs)
10023 {
10024         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10025         uint32_t *ptr_data = regs->data;
10026         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10027         const struct i40e_reg_info *reg_info;
10028
10029         if (ptr_data == NULL) {
10030                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10031                 regs->width = sizeof(uint32_t);
10032                 return 0;
10033         }
10034
10035         /* The first few registers have to be read using AQ operations */
10036         reg_idx = 0;
10037         while (i40e_regs_adminq[reg_idx].name) {
10038                 reg_info = &i40e_regs_adminq[reg_idx++];
10039                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10040                         for (arr_idx2 = 0;
10041                                         arr_idx2 <= reg_info->count2;
10042                                         arr_idx2++) {
10043                                 reg_offset = arr_idx * reg_info->stride1 +
10044                                         arr_idx2 * reg_info->stride2;
10045                                 reg_offset += reg_info->base_addr;
10046                                 ptr_data[reg_offset >> 2] =
10047                                         i40e_read_rx_ctl(hw, reg_offset);
10048                         }
10049         }
10050
10051         /* The remaining registers can be read using primitives */
10052         reg_idx = 0;
10053         while (i40e_regs_others[reg_idx].name) {
10054                 reg_info = &i40e_regs_others[reg_idx++];
10055                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10056                         for (arr_idx2 = 0;
10057                                         arr_idx2 <= reg_info->count2;
10058                                         arr_idx2++) {
10059                                 reg_offset = arr_idx * reg_info->stride1 +
10060                                         arr_idx2 * reg_info->stride2;
10061                                 reg_offset += reg_info->base_addr;
10062                                 ptr_data[reg_offset >> 2] =
10063                                         I40E_READ_REG(hw, reg_offset);
10064                         }
10065         }
10066
10067         return 0;
10068 }
10069
10070 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10071 {
10072         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10073
10074         /* Convert word count to byte count */
10075         return hw->nvm.sr_size << 1;
10076 }
10077
10078 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10079                            struct rte_dev_eeprom_info *eeprom)
10080 {
10081         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10082         uint16_t *data = eeprom->data;
10083         uint16_t offset, length, cnt_words;
10084         int ret_code;
10085
10086         offset = eeprom->offset >> 1;
10087         length = eeprom->length >> 1;
10088         cnt_words = length;
10089
10090         if (offset > hw->nvm.sr_size ||
10091                 offset + length > hw->nvm.sr_size) {
10092                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10093                 return -EINVAL;
10094         }
10095
10096         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10097
10098         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10099         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10100                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10101                 return -EIO;
10102         }
10103
10104         return 0;
10105 }
10106
10107 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10108                                       struct ether_addr *mac_addr)
10109 {
10110         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10111
10112         if (!is_valid_assigned_ether_addr(mac_addr)) {
10113                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10114                 return;
10115         }
10116
10117         /* Flags: 0x3 updates port address */
10118         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10119 }
10120
10121 static int
10122 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10123 {
10124         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10125         struct rte_eth_dev_data *dev_data = pf->dev_data;
10126         uint32_t frame_size = mtu + ETHER_HDR_LEN
10127                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10128         int ret = 0;
10129
10130         /* check if mtu is within the allowed range */
10131         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10132                 return -EINVAL;
10133
10134         /* mtu setting is forbidden if port is start */
10135         if (dev_data->dev_started) {
10136                 PMD_DRV_LOG(ERR,
10137                             "port %d must be stopped before configuration\n",
10138                             dev_data->port_id);
10139                 return -EBUSY;
10140         }
10141
10142         if (frame_size > ETHER_MAX_LEN)
10143                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10144         else
10145                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10146
10147         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10148
10149         return ret;
10150 }
10151
10152 /* Restore ethertype filter */
10153 static void
10154 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10155 {
10156         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10157         struct i40e_ethertype_filter_list
10158                 *ethertype_list = &pf->ethertype.ethertype_list;
10159         struct i40e_ethertype_filter *f;
10160         struct i40e_control_filter_stats stats;
10161         uint16_t flags;
10162
10163         TAILQ_FOREACH(f, ethertype_list, rules) {
10164                 flags = 0;
10165                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10166                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10167                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10168                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10169                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10170
10171                 memset(&stats, 0, sizeof(stats));
10172                 i40e_aq_add_rem_control_packet_filter(hw,
10173                                             f->input.mac_addr.addr_bytes,
10174                                             f->input.ether_type,
10175                                             flags, pf->main_vsi->seid,
10176                                             f->queue, 1, &stats, NULL);
10177         }
10178         PMD_DRV_LOG(INFO, "Ethertype filter:"
10179                     " mac_etype_used = %u, etype_used = %u,"
10180                     " mac_etype_free = %u, etype_free = %u\n",
10181                     stats.mac_etype_used, stats.etype_used,
10182                     stats.mac_etype_free, stats.etype_free);
10183 }
10184
10185 /* Restore tunnel filter */
10186 static void
10187 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10188 {
10189         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10190         struct i40e_vsi *vsi = pf->main_vsi;
10191         struct i40e_tunnel_filter_list
10192                 *tunnel_list = &pf->tunnel.tunnel_list;
10193         struct i40e_tunnel_filter *f;
10194         struct i40e_aqc_add_remove_cloud_filters_element_data cld_filter;
10195
10196         TAILQ_FOREACH(f, tunnel_list, rules) {
10197                 memset(&cld_filter, 0, sizeof(cld_filter));
10198                 rte_memcpy(&cld_filter, &f->input, sizeof(f->input));
10199                 cld_filter.queue_number = f->queue;
10200                 i40e_aq_add_cloud_filters(hw, vsi->seid, &cld_filter, 1);
10201         }
10202 }
10203
10204 static void
10205 i40e_filter_restore(struct i40e_pf *pf)
10206 {
10207         i40e_ethertype_filter_restore(pf);
10208         i40e_tunnel_filter_restore(pf);
10209         i40e_fdir_filter_restore(pf);
10210 }