drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68 #include "rte_pmd_i40e.h"
  69
  70 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  71 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  72
  73 #define I40E_CLEAR_PXE_WAIT_MS     200
  74
  75 /* Maximun number of capability elements */
  76 #define I40E_MAX_CAP_ELE_NUM       128
  77
  78 /* Wait count and interval */
  79 #define I40E_CHK_Q_ENA_COUNT       1000
  80 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  81
  82 /* Maximun number of VSI */
  83 #define I40E_MAX_NUM_VSIS          (384UL)
  84
  85 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  86
  87 /* Flow control default timer */
  88 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  89
  90 /* Flow control enable fwd bit */
  91 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  92
  93 /* Receive Packet Buffer size */
  94 #define I40E_RXPBSIZE (968 * 1024)
  95
  96 /* Kilobytes shift */
  97 #define I40E_KILOSHIFT 10
  98
  99 /* Flow control default high water */
 100 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
 101
 102 /* Flow control default low water */
 103 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
 104
 105 /* Receive Average Packet Size in Byte*/
 106 #define I40E_PACKET_AVERAGE_SIZE 128
 107
 108 /* Mask of PF interrupt causes */
 109 #define I40E_PFINT_ICR0_ENA_MASK ( \
 110                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 112                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 114                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 115                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 118                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 119
 120 #define I40E_FLOW_TYPES ( \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 130         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 131         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 132
 133 /* Additional timesync values. */
 134 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 135 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 136 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 137 #define I40E_PRTTSYN_TSYNENA     0x80000000
 138 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 139 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define I40E_MAX_PERCENT            100
 142 #define I40E_DEFAULT_DCB_APP_NUM    1
 143 #define I40E_DEFAULT_DCB_APP_PRIO   3
 144
 145 /**
 146  * Below are values for writing un-exposed registers suggested
 147  * by silicon experts
 148  */
 149 /* Destination MAC address */
 150 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 151 /* Source MAC address */
 152 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 153 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 154 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 155 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 156 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 157 /* Single VLAN tag in the inner L2 header */
 158 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 159 /* Source IPv4 address */
 160 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 161 /* Destination IPv4 address */
 162 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 163 /* Source IPv4 address for X722 */
 164 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 165 /* Destination IPv4 address for X722 */
 166 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 167 /* IPv4 Protocol for X722 */
 168 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 169 /* IPv4 Time to Live for X722 */
 170 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 171 /* IPv4 Type of Service (TOS) */
 172 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 173 /* IPv4 Protocol */
 174 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 175 /* IPv4 Time to Live */
 176 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 177 /* Source IPv6 address */
 178 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 179 /* Destination IPv6 address */
 180 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 181 /* IPv6 Traffic Class (TC) */
 182 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 183 /* IPv6 Next Header */
 184 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 185 /* IPv6 Hop Limit */
 186 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 187 /* Source L4 port */
 188 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 189 /* Destination L4 port */
 190 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 191 /* SCTP verification tag */
 192 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 193 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 194 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 195 /* Source port of tunneling UDP */
 196 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 197 /* Destination port of tunneling UDP */
 198 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 199 /* UDP Tunneling ID, NVGRE/GRE key */
 200 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 201 /* Last ether type */
 202 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 203 /* Tunneling outer destination IPv4 address */
 204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 205 /* Tunneling outer destination IPv6 address */
 206 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 207 /* 1st word of flex payload */
 208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 209 /* 2nd word of flex payload */
 210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 211 /* 3rd word of flex payload */
 212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 213 /* 4th word of flex payload */
 214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 215 /* 5th word of flex payload */
 216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 217 /* 6th word of flex payload */
 218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 219 /* 7th word of flex payload */
 220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 221 /* 8th word of flex payload */
 222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 223 /* all 8 words flex payload */
 224 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 225 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 226
 227 #define I40E_TRANSLATE_INSET 0
 228 #define I40E_TRANSLATE_REG   1
 229
 230 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 231 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 232 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 233 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 234 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 235 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 236
 237 /* PCI offset for querying capability */
 238 #define PCI_DEV_CAP_REG            0xA4
 239 /* PCI offset for enabling/disabling Extended Tag */
 240 #define PCI_DEV_CTRL_REG           0xA8
 241 /* Bit mask of Extended Tag capability */
 242 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 243 /* Bit shift of Extended Tag enable/disable */
 244 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 245 /* Bit mask of Extended Tag enable/disable */
 246 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 247
 248 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 249 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 250 static int i40e_dev_configure(struct rte_eth_dev *dev);
 251 static int i40e_dev_start(struct rte_eth_dev *dev);
 252 static void i40e_dev_stop(struct rte_eth_dev *dev);
 253 static void i40e_dev_close(struct rte_eth_dev *dev);
 254 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 255 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 256 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 257 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 258 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 259 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 260 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 261 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 262                                struct rte_eth_stats *stats);
 263 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 264                                struct rte_eth_xstat *xstats, unsigned n);
 265 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 266                                      struct rte_eth_xstat_name *xstats_names,
 267                                      unsigned limit);
 268 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 269 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 270                                             uint16_t queue_id,
 271                                             uint8_t stat_idx,
 272                                             uint8_t is_rx);
 273 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 274                                 char *fw_version, size_t fw_size);
 275 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 276                               struct rte_eth_dev_info *dev_info);
 277 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 278                                 uint16_t vlan_id,
 279                                 int on);
 280 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 281                               enum rte_vlan_type vlan_type,
 282                               uint16_t tpid);
 283 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 284 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 285                                       uint16_t queue,
 286                                       int on);
 287 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 288 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 289 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 290 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 291                               struct rte_eth_fc_conf *fc_conf);
 292 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 293                               struct rte_eth_fc_conf *fc_conf);
 294 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 295                                        struct rte_eth_pfc_conf *pfc_conf);
 296 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 297                             struct ether_addr *mac_addr,
 298                             uint32_t index,
 299                             uint32_t pool);
 300 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 301 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 302                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 303                                     uint16_t reta_size);
 304 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 305                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 306                                    uint16_t reta_size);
 307
 308 static int i40e_get_cap(struct i40e_hw *hw);
 309 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 310 static int i40e_pf_setup(struct i40e_pf *pf);
 311 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 312 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 313 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 314 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 315 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 316                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 317 static void i40e_stat_update_48(struct i40e_hw *hw,
 318                                uint32_t hireg,
 319                                uint32_t loreg,
 320                                bool offset_loaded,
 321                                uint64_t *offset,
 322                                uint64_t *stat);
 323 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 324 static void i40e_dev_interrupt_handler(void *param);
 325 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 326                                 uint32_t base, uint32_t num);
 327 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 328 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 329                         uint32_t base);
 330 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 331                         uint16_t num);
 332 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 333 static int i40e_veb_release(struct i40e_veb *veb);
 334 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 335                                                 struct i40e_vsi *vsi);
 336 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 337 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 338 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 339                                              struct i40e_macvlan_filter *mv_f,
 340                                              int num,
 341                                              uint16_t vlan);
 342 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 343 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 344                                     struct rte_eth_rss_conf *rss_conf);
 345 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 346                                       struct rte_eth_rss_conf *rss_conf);
 347 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 348                                         struct rte_eth_udp_tunnel *udp_tunnel);
 349 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 350                                         struct rte_eth_udp_tunnel *udp_tunnel);
 351 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 352 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 353                                 enum rte_filter_op filter_op,
 354                                 void *arg);
 355 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 356                                 enum rte_filter_type filter_type,
 357                                 enum rte_filter_op filter_op,
 358                                 void *arg);
 359 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 360                                   struct rte_eth_dcb_info *dcb_info);
 361 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 362 static void i40e_configure_registers(struct i40e_hw *hw);
 363 static void i40e_hw_init(struct rte_eth_dev *dev);
 364 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 365 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 366                                                      uint16_t seid,
 367                                                      uint16_t rule_type,
 368                                                      uint16_t *entries,
 369                                                      uint16_t count,
 370                                                      uint16_t rule_id);
 371 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 372                         struct rte_eth_mirror_conf *mirror_conf,
 373                         uint8_t sw_id, uint8_t on);
 374 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 375
 376 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 377 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 378 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 379                                            struct timespec *timestamp,
 380                                            uint32_t flags);
 381 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 382                                            struct timespec *timestamp);
 383 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 384
 385 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 386
 387 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 388                                    struct timespec *timestamp);
 389 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 390                                     const struct timespec *timestamp);
 391
 392 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 393                                          uint16_t queue_id);
 394 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 395                                           uint16_t queue_id);
 396
 397 static int i40e_get_regs(struct rte_eth_dev *dev,
 398                          struct rte_dev_reg_info *regs);
 399
 400 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 401
 402 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 403                            struct rte_dev_eeprom_info *eeprom);
 404
 405 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 406                                       struct ether_addr *mac_addr);
 407
 408 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 409
 410 static int i40e_ethertype_filter_convert(
 411         const struct rte_eth_ethertype_filter *input,
 412         struct i40e_ethertype_filter *filter);
 413 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 414                                    struct i40e_ethertype_filter *filter);
 415
 416 static int i40e_tunnel_filter_convert(
 417         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 418         struct i40e_tunnel_filter *tunnel_filter);
 419 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 420                                 struct i40e_tunnel_filter *tunnel_filter);
 421 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 422
 423 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 424 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 425 static void i40e_filter_restore(struct i40e_pf *pf);
 426 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 427
 428 int i40e_logtype_init;
 429 int i40e_logtype_driver;
 430
 431 static const struct rte_pci_id pci_id_i40e_map[] = {
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 445         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 446         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 447         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 448         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 449         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 450         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 451         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 452         { .vendor_id = 0, /* sentinel */ },
 453 };
 454
 455 static const struct eth_dev_ops i40e_eth_dev_ops = {
 456         .dev_configure                = i40e_dev_configure,
 457         .dev_start                    = i40e_dev_start,
 458         .dev_stop                     = i40e_dev_stop,
 459         .dev_close                    = i40e_dev_close,
 460         .dev_reset                    = i40e_dev_reset,
 461         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 462         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 463         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 464         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 465         .dev_set_link_up              = i40e_dev_set_link_up,
 466         .dev_set_link_down            = i40e_dev_set_link_down,
 467         .link_update                  = i40e_dev_link_update,
 468         .stats_get                    = i40e_dev_stats_get,
 469         .xstats_get                   = i40e_dev_xstats_get,
 470         .xstats_get_names             = i40e_dev_xstats_get_names,
 471         .stats_reset                  = i40e_dev_stats_reset,
 472         .xstats_reset                 = i40e_dev_stats_reset,
 473         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 474         .fw_version_get               = i40e_fw_version_get,
 475         .dev_infos_get                = i40e_dev_info_get,
 476         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 477         .vlan_filter_set              = i40e_vlan_filter_set,
 478         .vlan_tpid_set                = i40e_vlan_tpid_set,
 479         .vlan_offload_set             = i40e_vlan_offload_set,
 480         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 481         .vlan_pvid_set                = i40e_vlan_pvid_set,
 482         .rx_queue_start               = i40e_dev_rx_queue_start,
 483         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 484         .tx_queue_start               = i40e_dev_tx_queue_start,
 485         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 486         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 487         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 488         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 489         .rx_queue_release             = i40e_dev_rx_queue_release,
 490         .rx_queue_count               = i40e_dev_rx_queue_count,
 491         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 492         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 493         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 494         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 495         .tx_queue_release             = i40e_dev_tx_queue_release,
 496         .dev_led_on                   = i40e_dev_led_on,
 497         .dev_led_off                  = i40e_dev_led_off,
 498         .flow_ctrl_get                = i40e_flow_ctrl_get,
 499         .flow_ctrl_set                = i40e_flow_ctrl_set,
 500         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 501         .mac_addr_add                 = i40e_macaddr_add,
 502         .mac_addr_remove              = i40e_macaddr_remove,
 503         .reta_update                  = i40e_dev_rss_reta_update,
 504         .reta_query                   = i40e_dev_rss_reta_query,
 505         .rss_hash_update              = i40e_dev_rss_hash_update,
 506         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 507         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 508         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 509         .filter_ctrl                  = i40e_dev_filter_ctrl,
 510         .rxq_info_get                 = i40e_rxq_info_get,
 511         .txq_info_get                 = i40e_txq_info_get,
 512         .mirror_rule_set              = i40e_mirror_rule_set,
 513         .mirror_rule_reset            = i40e_mirror_rule_reset,
 514         .timesync_enable              = i40e_timesync_enable,
 515         .timesync_disable             = i40e_timesync_disable,
 516         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 517         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 518         .get_dcb_info                 = i40e_dev_get_dcb_info,
 519         .timesync_adjust_time         = i40e_timesync_adjust_time,
 520         .timesync_read_time           = i40e_timesync_read_time,
 521         .timesync_write_time          = i40e_timesync_write_time,
 522         .get_reg                      = i40e_get_regs,
 523         .get_eeprom_length            = i40e_get_eeprom_length,
 524         .get_eeprom                   = i40e_get_eeprom,
 525         .mac_addr_set                 = i40e_set_default_mac_addr,
 526         .mtu_set                      = i40e_dev_mtu_set,
 527         .tm_ops_get                   = i40e_tm_ops_get,
 528 };
 529
 530 /* store statistics names and its offset in stats structure */
 531 struct rte_i40e_xstats_name_off {
 532         char name[RTE_ETH_XSTATS_NAME_SIZE];
 533         unsigned offset;
 534 };
 535
 536 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 537         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 538         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 539         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 540         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 541         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 542                 rx_unknown_protocol)},
 543         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 544         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 545         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 546         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 547 };
 548
 549 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 550                 sizeof(rte_i40e_stats_strings[0]))
 551
 552 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 553         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 554                 tx_dropped_link_down)},
 555         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 556         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 557                 illegal_bytes)},
 558         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 559         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 560                 mac_local_faults)},
 561         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 562                 mac_remote_faults)},
 563         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 564                 rx_length_errors)},
 565         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 566         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 567         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 568         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 569         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 570         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 571                 rx_size_127)},
 572         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 573                 rx_size_255)},
 574         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 575                 rx_size_511)},
 576         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 577                 rx_size_1023)},
 578         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 579                 rx_size_1522)},
 580         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 581                 rx_size_big)},
 582         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 583                 rx_undersize)},
 584         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 585                 rx_oversize)},
 586         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 587                 mac_short_packet_dropped)},
 588         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 589                 rx_fragments)},
 590         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 591         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 592         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 593                 tx_size_127)},
 594         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 595                 tx_size_255)},
 596         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 597                 tx_size_511)},
 598         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 599                 tx_size_1023)},
 600         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 601                 tx_size_1522)},
 602         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 603                 tx_size_big)},
 604         {"rx_flow_director_atr_match_packets",
 605                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 606         {"rx_flow_director_sb_match_packets",
 607                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 608         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 609                 tx_lpi_status)},
 610         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 611                 rx_lpi_status)},
 612         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 613                 tx_lpi_count)},
 614         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 615                 rx_lpi_count)},
 616 };
 617
 618 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 619                 sizeof(rte_i40e_hw_port_strings[0]))
 620
 621 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 622         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 623                 priority_xon_rx)},
 624         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 625                 priority_xoff_rx)},
 626 };
 627
 628 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 629                 sizeof(rte_i40e_rxq_prio_strings[0]))
 630
 631 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 632         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 633                 priority_xon_tx)},
 634         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 635                 priority_xoff_tx)},
 636         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 637                 priority_xon_2_xoff)},
 638 };
 639
 640 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 641                 sizeof(rte_i40e_txq_prio_strings[0]))
 642
 643 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 644         struct rte_pci_device *pci_dev)
 645 {
 646         return rte_eth_dev_pci_generic_probe(pci_dev,
 647                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 648 }
 649
 650 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 651 {
 652         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 653 }
 654
 655 static struct rte_pci_driver rte_i40e_pmd = {
 656         .id_table = pci_id_i40e_map,
 657         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 658         .probe = eth_i40e_pci_probe,
 659         .remove = eth_i40e_pci_remove,
 660 };
 661
 662 static inline int
 663 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 664                                      struct rte_eth_link *link)
 665 {
 666         struct rte_eth_link *dst = link;
 667         struct rte_eth_link *src = &(dev->data->dev_link);
 668
 669         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 670                                         *(uint64_t *)src) == 0)
 671                 return -1;
 672
 673         return 0;
 674 }
 675
 676 static inline int
 677 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 678                                       struct rte_eth_link *link)
 679 {
 680         struct rte_eth_link *dst = &(dev->data->dev_link);
 681         struct rte_eth_link *src = link;
 682
 683         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 684                                         *(uint64_t *)src) == 0)
 685                 return -1;
 686
 687         return 0;
 688 }
 689
 690 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 691 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 692 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 693
 694 #ifndef I40E_GLQF_ORT
 695 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 696 #endif
 697 #ifndef I40E_GLQF_PIT
 698 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 699 #endif
 700 #ifndef I40E_GLQF_L3_MAP
 701 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 702 #endif
 703
 704 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 705 {
 706         /*
 707          * Initialize registers for flexible payload, which should be set by NVM.
 708          * This should be removed from code once it is fixed in NVM.
 709          */
 710         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 711         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 712         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 713         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 714         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 715         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 716         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 717         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 718         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 719         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 720         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 721         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 722
 723         /* Initialize registers for parsing packet type of QinQ */
 724         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 725         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 726 }
 727
 728 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 729
 730 /*
 731  * Add a ethertype filter to drop all flow control frames transmitted
 732  * from VSIs.
 733 */
 734 static void
 735 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 736 {
 737         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 738         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 739                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 740                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 741         int ret;
 742
 743         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 744                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 745                                 pf->main_vsi_seid, 0,
 746                                 TRUE, NULL, NULL);
 747         if (ret)
 748                 PMD_INIT_LOG(ERR,
 749                         "Failed to add filter to drop flow control frames from VSIs.");
 750 }
 751
 752 static int
 753 floating_veb_list_handler(__rte_unused const char *key,
 754                           const char *floating_veb_value,
 755                           void *opaque)
 756 {
 757         int idx = 0;
 758         unsigned int count = 0;
 759         char *end = NULL;
 760         int min, max;
 761         bool *vf_floating_veb = opaque;
 762
 763         while (isblank(*floating_veb_value))
 764                 floating_veb_value++;
 765
 766         /* Reset floating VEB configuration for VFs */
 767         for (idx = 0; idx < I40E_MAX_VF; idx++)
 768                 vf_floating_veb[idx] = false;
 769
 770         min = I40E_MAX_VF;
 771         do {
 772                 while (isblank(*floating_veb_value))
 773                         floating_veb_value++;
 774                 if (*floating_veb_value == '\0')
 775                         return -1;
 776                 errno = 0;
 777                 idx = strtoul(floating_veb_value, &end, 10);
 778                 if (errno || end == NULL)
 779                         return -1;
 780                 while (isblank(*end))
 781                         end++;
 782                 if (*end == '-') {
 783                         min = idx;
 784                 } else if ((*end == ';') || (*end == '\0')) {
 785                         max = idx;
 786                         if (min == I40E_MAX_VF)
 787                                 min = idx;
 788                         if (max >= I40E_MAX_VF)
 789                                 max = I40E_MAX_VF - 1;
 790                         for (idx = min; idx <= max; idx++) {
 791                                 vf_floating_veb[idx] = true;
 792                                 count++;
 793                         }
 794                         min = I40E_MAX_VF;
 795                 } else {
 796                         return -1;
 797                 }
 798                 floating_veb_value = end + 1;
 799         } while (*end != '\0');
 800
 801         if (count == 0)
 802                 return -1;
 803
 804         return 0;
 805 }
 806
 807 static void
 808 config_vf_floating_veb(struct rte_devargs *devargs,
 809                        uint16_t floating_veb,
 810                        bool *vf_floating_veb)
 811 {
 812         struct rte_kvargs *kvlist;
 813         int i;
 814         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 815
 816         if (!floating_veb)
 817                 return;
 818         /* All the VFs attach to the floating VEB by default
 819          * when the floating VEB is enabled.
 820          */
 821         for (i = 0; i < I40E_MAX_VF; i++)
 822                 vf_floating_veb[i] = true;
 823
 824         if (devargs == NULL)
 825                 return;
 826
 827         kvlist = rte_kvargs_parse(devargs->args, NULL);
 828         if (kvlist == NULL)
 829                 return;
 830
 831         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 832                 rte_kvargs_free(kvlist);
 833                 return;
 834         }
 835         /* When the floating_veb_list parameter exists, all the VFs
 836          * will attach to the legacy VEB firstly, then configure VFs
 837          * to the floating VEB according to the floating_veb_list.
 838          */
 839         if (rte_kvargs_process(kvlist, floating_veb_list,
 840                                floating_veb_list_handler,
 841                                vf_floating_veb) < 0) {
 842                 rte_kvargs_free(kvlist);
 843                 return;
 844         }
 845         rte_kvargs_free(kvlist);
 846 }
 847
 848 static int
 849 i40e_check_floating_handler(__rte_unused const char *key,
 850                             const char *value,
 851                             __rte_unused void *opaque)
 852 {
 853         if (strcmp(value, "1"))
 854                 return -1;
 855
 856         return 0;
 857 }
 858
 859 static int
 860 is_floating_veb_supported(struct rte_devargs *devargs)
 861 {
 862         struct rte_kvargs *kvlist;
 863         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 864
 865         if (devargs == NULL)
 866                 return 0;
 867
 868         kvlist = rte_kvargs_parse(devargs->args, NULL);
 869         if (kvlist == NULL)
 870                 return 0;
 871
 872         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 873                 rte_kvargs_free(kvlist);
 874                 return 0;
 875         }
 876         /* Floating VEB is enabled when there's key-value:
 877          * enable_floating_veb=1
 878          */
 879         if (rte_kvargs_process(kvlist, floating_veb_key,
 880                                i40e_check_floating_handler, NULL) < 0) {
 881                 rte_kvargs_free(kvlist);
 882                 return 0;
 883         }
 884         rte_kvargs_free(kvlist);
 885
 886         return 1;
 887 }
 888
 889 static void
 890 config_floating_veb(struct rte_eth_dev *dev)
 891 {
 892         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 893         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 894         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 895
 896         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 897
 898         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 899                 pf->floating_veb =
 900                         is_floating_veb_supported(pci_dev->device.devargs);
 901                 config_vf_floating_veb(pci_dev->device.devargs,
 902                                        pf->floating_veb,
 903                                        pf->floating_veb_list);
 904         } else {
 905                 pf->floating_veb = false;
 906         }
 907 }
 908
 909 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 910 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 911
 912 static int
 913 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 914 {
 915         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 916         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 917         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 918         int ret;
 919
 920         struct rte_hash_parameters ethertype_hash_params = {
 921                 .name = ethertype_hash_name,
 922                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 923                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 924                 .hash_func = rte_hash_crc,
 925                 .hash_func_init_val = 0,
 926                 .socket_id = rte_socket_id(),
 927         };
 928
 929         /* Initialize ethertype filter rule list and hash */
 930         TAILQ_INIT(&ethertype_rule->ethertype_list);
 931         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 932                  "ethertype_%s", dev->device->name);
 933         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 934         if (!ethertype_rule->hash_table) {
 935                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 936                 return -EINVAL;
 937         }
 938         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 939                                        sizeof(struct i40e_ethertype_filter *) *
 940                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 941                                        0);
 942         if (!ethertype_rule->hash_map) {
 943                 PMD_INIT_LOG(ERR,
 944                              "Failed to allocate memory for ethertype hash map!");
 945                 ret = -ENOMEM;
 946                 goto err_ethertype_hash_map_alloc;
 947         }
 948
 949         return 0;
 950
 951 err_ethertype_hash_map_alloc:
 952         rte_hash_free(ethertype_rule->hash_table);
 953
 954         return ret;
 955 }
 956
 957 static int
 958 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 959 {
 960         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 961         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 962         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 963         int ret;
 964
 965         struct rte_hash_parameters tunnel_hash_params = {
 966                 .name = tunnel_hash_name,
 967                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 968                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 969                 .hash_func = rte_hash_crc,
 970                 .hash_func_init_val = 0,
 971                 .socket_id = rte_socket_id(),
 972         };
 973
 974         /* Initialize tunnel filter rule list and hash */
 975         TAILQ_INIT(&tunnel_rule->tunnel_list);
 976         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 977                  "tunnel_%s", dev->device->name);
 978         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 979         if (!tunnel_rule->hash_table) {
 980                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 981                 return -EINVAL;
 982         }
 983         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 984                                     sizeof(struct i40e_tunnel_filter *) *
 985                                     I40E_MAX_TUNNEL_FILTER_NUM,
 986                                     0);
 987         if (!tunnel_rule->hash_map) {
 988                 PMD_INIT_LOG(ERR,
 989                              "Failed to allocate memory for tunnel hash map!");
 990                 ret = -ENOMEM;
 991                 goto err_tunnel_hash_map_alloc;
 992         }
 993
 994         return 0;
 995
 996 err_tunnel_hash_map_alloc:
 997         rte_hash_free(tunnel_rule->hash_table);
 998
 999         return ret;
1000 }
1001
1002 static int
1003 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1004 {
1005         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1006         struct i40e_fdir_info *fdir_info = &pf->fdir;
1007         char fdir_hash_name[RTE_HASH_NAMESIZE];
1008         int ret;
1009
1010         struct rte_hash_parameters fdir_hash_params = {
1011                 .name = fdir_hash_name,
1012                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1013                 .key_len = sizeof(struct rte_eth_fdir_input),
1014                 .hash_func = rte_hash_crc,
1015                 .hash_func_init_val = 0,
1016                 .socket_id = rte_socket_id(),
1017         };
1018
1019         /* Initialize flow director filter rule list and hash */
1020         TAILQ_INIT(&fdir_info->fdir_list);
1021         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1022                  "fdir_%s", dev->device->name);
1023         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1024         if (!fdir_info->hash_table) {
1025                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1026                 return -EINVAL;
1027         }
1028         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1029                                           sizeof(struct i40e_fdir_filter *) *
1030                                           I40E_MAX_FDIR_FILTER_NUM,
1031                                           0);
1032         if (!fdir_info->hash_map) {
1033                 PMD_INIT_LOG(ERR,
1034                              "Failed to allocate memory for fdir hash map!");
1035                 ret = -ENOMEM;
1036                 goto err_fdir_hash_map_alloc;
1037         }
1038         return 0;
1039
1040 err_fdir_hash_map_alloc:
1041         rte_hash_free(fdir_info->hash_table);
1042
1043         return ret;
1044 }
1045
1046 static void
1047 i40e_init_customized_info(struct i40e_pf *pf)
1048 {
1049         int i;
1050
1051         /* Initialize customized pctype */
1052         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1053                 pf->customized_pctype[i].index = i;
1054                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1055                 pf->customized_pctype[i].valid = false;
1056         }
1057
1058         pf->gtp_support = false;
1059 }
1060
1061 static int
1062 eth_i40e_dev_init(struct rte_eth_dev *dev)
1063 {
1064         struct rte_pci_device *pci_dev;
1065         struct rte_intr_handle *intr_handle;
1066         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1067         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1068         struct i40e_vsi *vsi;
1069         int ret;
1070         uint32_t len;
1071         uint8_t aq_fail = 0;
1072
1073         PMD_INIT_FUNC_TRACE();
1074
1075         dev->dev_ops = &i40e_eth_dev_ops;
1076         dev->rx_pkt_burst = i40e_recv_pkts;
1077         dev->tx_pkt_burst = i40e_xmit_pkts;
1078         dev->tx_pkt_prepare = i40e_prep_pkts;
1079
1080         /* for secondary processes, we don't initialise any further as primary
1081          * has already done this work. Only check we don't need a different
1082          * RX function */
1083         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1084                 i40e_set_rx_function(dev);
1085                 i40e_set_tx_function(dev);
1086                 return 0;
1087         }
1088         i40e_set_default_ptype_table(dev);
1089         i40e_set_default_pctype_table(dev);
1090         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1091         intr_handle = &pci_dev->intr_handle;
1092
1093         rte_eth_copy_pci_info(dev, pci_dev);
1094         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1095
1096         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1097         pf->adapter->eth_dev = dev;
1098         pf->dev_data = dev->data;
1099
1100         hw->back = I40E_PF_TO_ADAPTER(pf);
1101         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1102         if (!hw->hw_addr) {
1103                 PMD_INIT_LOG(ERR,
1104                         "Hardware is not available, as address is NULL");
1105                 return -ENODEV;
1106         }
1107
1108         hw->vendor_id = pci_dev->id.vendor_id;
1109         hw->device_id = pci_dev->id.device_id;
1110         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1111         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1112         hw->bus.device = pci_dev->addr.devid;
1113         hw->bus.func = pci_dev->addr.function;
1114         hw->adapter_stopped = 0;
1115
1116         /* Make sure all is clean before doing PF reset */
1117         i40e_clear_hw(hw);
1118
1119         /* Initialize the hardware */
1120         i40e_hw_init(dev);
1121
1122         /* Reset here to make sure all is clean for each PF */
1123         ret = i40e_pf_reset(hw);
1124         if (ret) {
1125                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1126                 return ret;
1127         }
1128
1129         /* Initialize the shared code (base driver) */
1130         ret = i40e_init_shared_code(hw);
1131         if (ret) {
1132                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1133                 return ret;
1134         }
1135
1136         /*
1137          * To work around the NVM issue, initialize registers
1138          * for flexible payload and packet type of QinQ by
1139          * software. It should be removed once issues are fixed
1140          * in NVM.
1141          */
1142         i40e_GLQF_reg_init(hw);
1143
1144         /* Initialize the input set for filters (hash and fd) to default value */
1145         i40e_filter_input_set_init(pf);
1146
1147         /* Initialize the parameters for adminq */
1148         i40e_init_adminq_parameter(hw);
1149         ret = i40e_init_adminq(hw);
1150         if (ret != I40E_SUCCESS) {
1151                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1152                 return -EIO;
1153         }
1154         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1155                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1156                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1157                      ((hw->nvm.version >> 12) & 0xf),
1158                      ((hw->nvm.version >> 4) & 0xff),
1159                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1160
1161         /* initialise the L3_MAP register */
1162         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1163                                    0x00000028,  NULL);
1164         if (ret)
1165                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1166
1167         /* Need the special FW version to support floating VEB */
1168         config_floating_veb(dev);
1169         /* Clear PXE mode */
1170         i40e_clear_pxe_mode(hw);
1171         i40e_dev_sync_phy_type(hw);
1172
1173         /*
1174          * On X710, performance number is far from the expectation on recent
1175          * firmware versions. The fix for this issue may not be integrated in
1176          * the following firmware version. So the workaround in software driver
1177          * is needed. It needs to modify the initial values of 3 internal only
1178          * registers. Note that the workaround can be removed when it is fixed
1179          * in firmware in the future.
1180          */
1181         i40e_configure_registers(hw);
1182
1183         /* Get hw capabilities */
1184         ret = i40e_get_cap(hw);
1185         if (ret != I40E_SUCCESS) {
1186                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1187                 goto err_get_capabilities;
1188         }
1189
1190         /* Initialize parameters for PF */
1191         ret = i40e_pf_parameter_init(dev);
1192         if (ret != 0) {
1193                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1194                 goto err_parameter_init;
1195         }
1196
1197         /* Initialize the queue management */
1198         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1199         if (ret < 0) {
1200                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1201                 goto err_qp_pool_init;
1202         }
1203         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1204                                 hw->func_caps.num_msix_vectors - 1);
1205         if (ret < 0) {
1206                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1207                 goto err_msix_pool_init;
1208         }
1209
1210         /* Initialize lan hmc */
1211         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1212                                 hw->func_caps.num_rx_qp, 0, 0);
1213         if (ret != I40E_SUCCESS) {
1214                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1215                 goto err_init_lan_hmc;
1216         }
1217
1218         /* Configure lan hmc */
1219         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1220         if (ret != I40E_SUCCESS) {
1221                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1222                 goto err_configure_lan_hmc;
1223         }
1224
1225         /* Get and check the mac address */
1226         i40e_get_mac_addr(hw, hw->mac.addr);
1227         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1228                 PMD_INIT_LOG(ERR, "mac address is not valid");
1229                 ret = -EIO;
1230                 goto err_get_mac_addr;
1231         }
1232         /* Copy the permanent MAC address */
1233         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1234                         (struct ether_addr *) hw->mac.perm_addr);
1235
1236         /* Disable flow control */
1237         hw->fc.requested_mode = I40E_FC_NONE;
1238         i40e_set_fc(hw, &aq_fail, TRUE);
1239
1240         /* Set the global registers with default ether type value */
1241         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1242         if (ret != I40E_SUCCESS) {
1243                 PMD_INIT_LOG(ERR,
1244                         "Failed to set the default outer VLAN ether type");
1245                 goto err_setup_pf_switch;
1246         }
1247
1248         /* PF setup, which includes VSI setup */
1249         ret = i40e_pf_setup(pf);
1250         if (ret) {
1251                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1252                 goto err_setup_pf_switch;
1253         }
1254
1255         /* reset all stats of the device, including pf and main vsi */
1256         i40e_dev_stats_reset(dev);
1257
1258         vsi = pf->main_vsi;
1259
1260         /* Disable double vlan by default */
1261         i40e_vsi_config_double_vlan(vsi, FALSE);
1262
1263         /* Disable S-TAG identification when floating_veb is disabled */
1264         if (!pf->floating_veb) {
1265                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1266                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1267                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1268                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1269                 }
1270         }
1271
1272         if (!vsi->max_macaddrs)
1273                 len = ETHER_ADDR_LEN;
1274         else
1275                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1276
1277         /* Should be after VSI initialized */
1278         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1279         if (!dev->data->mac_addrs) {
1280                 PMD_INIT_LOG(ERR,
1281                         "Failed to allocated memory for storing mac address");
1282                 goto err_mac_alloc;
1283         }
1284         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1285                                         &dev->data->mac_addrs[0]);
1286
1287         /* Init dcb to sw mode by default */
1288         ret = i40e_dcb_init_configure(dev, TRUE);
1289         if (ret != I40E_SUCCESS) {
1290                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1291                 pf->flags &= ~I40E_FLAG_DCB;
1292         }
1293         /* Update HW struct after DCB configuration */
1294         i40e_get_cap(hw);
1295
1296         /* initialize pf host driver to setup SRIOV resource if applicable */
1297         i40e_pf_host_init(dev);
1298
1299         /* register callback func to eal lib */
1300         rte_intr_callback_register(intr_handle,
1301                                    i40e_dev_interrupt_handler, dev);
1302
1303         /* configure and enable device interrupt */
1304         i40e_pf_config_irq0(hw, TRUE);
1305         i40e_pf_enable_irq0(hw);
1306
1307         /* enable uio intr after callback register */
1308         rte_intr_enable(intr_handle);
1309         /*
1310          * Add an ethertype filter to drop all flow control frames transmitted
1311          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1312          * frames to wire.
1313          */
1314         i40e_add_tx_flow_control_drop_filter(pf);
1315
1316         /* Set the max frame size to 0x2600 by default,
1317          * in case other drivers changed the default value.
1318          */
1319         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1320
1321         /* initialize mirror rule list */
1322         TAILQ_INIT(&pf->mirror_list);
1323
1324         /* initialize Traffic Manager configuration */
1325         i40e_tm_conf_init(dev);
1326
1327         /* Initialize customized information */
1328         i40e_init_customized_info(pf);
1329
1330         ret = i40e_init_ethtype_filter_list(dev);
1331         if (ret < 0)
1332                 goto err_init_ethtype_filter_list;
1333         ret = i40e_init_tunnel_filter_list(dev);
1334         if (ret < 0)
1335                 goto err_init_tunnel_filter_list;
1336         ret = i40e_init_fdir_filter_list(dev);
1337         if (ret < 0)
1338                 goto err_init_fdir_filter_list;
1339
1340         return 0;
1341
1342 err_init_fdir_filter_list:
1343         rte_free(pf->tunnel.hash_table);
1344         rte_free(pf->tunnel.hash_map);
1345 err_init_tunnel_filter_list:
1346         rte_free(pf->ethertype.hash_table);
1347         rte_free(pf->ethertype.hash_map);
1348 err_init_ethtype_filter_list:
1349         rte_free(dev->data->mac_addrs);
1350 err_mac_alloc:
1351         i40e_vsi_release(pf->main_vsi);
1352 err_setup_pf_switch:
1353 err_get_mac_addr:
1354 err_configure_lan_hmc:
1355         (void)i40e_shutdown_lan_hmc(hw);
1356 err_init_lan_hmc:
1357         i40e_res_pool_destroy(&pf->msix_pool);
1358 err_msix_pool_init:
1359         i40e_res_pool_destroy(&pf->qp_pool);
1360 err_qp_pool_init:
1361 err_parameter_init:
1362 err_get_capabilities:
1363         (void)i40e_shutdown_adminq(hw);
1364
1365         return ret;
1366 }
1367
1368 static void
1369 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1370 {
1371         struct i40e_ethertype_filter *p_ethertype;
1372         struct i40e_ethertype_rule *ethertype_rule;
1373
1374         ethertype_rule = &pf->ethertype;
1375         /* Remove all ethertype filter rules and hash */
1376         if (ethertype_rule->hash_map)
1377                 rte_free(ethertype_rule->hash_map);
1378         if (ethertype_rule->hash_table)
1379                 rte_hash_free(ethertype_rule->hash_table);
1380
1381         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1382                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1383                              p_ethertype, rules);
1384                 rte_free(p_ethertype);
1385         }
1386 }
1387
1388 static void
1389 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1390 {
1391         struct i40e_tunnel_filter *p_tunnel;
1392         struct i40e_tunnel_rule *tunnel_rule;
1393
1394         tunnel_rule = &pf->tunnel;
1395         /* Remove all tunnel director rules and hash */
1396         if (tunnel_rule->hash_map)
1397                 rte_free(tunnel_rule->hash_map);
1398         if (tunnel_rule->hash_table)
1399                 rte_hash_free(tunnel_rule->hash_table);
1400
1401         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1402                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1403                 rte_free(p_tunnel);
1404         }
1405 }
1406
1407 static void
1408 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1409 {
1410         struct i40e_fdir_filter *p_fdir;
1411         struct i40e_fdir_info *fdir_info;
1412
1413         fdir_info = &pf->fdir;
1414         /* Remove all flow director rules and hash */
1415         if (fdir_info->hash_map)
1416                 rte_free(fdir_info->hash_map);
1417         if (fdir_info->hash_table)
1418                 rte_hash_free(fdir_info->hash_table);
1419
1420         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1421                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1422                 rte_free(p_fdir);
1423         }
1424 }
1425
1426 static int
1427 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1428 {
1429         struct i40e_pf *pf;
1430         struct rte_pci_device *pci_dev;
1431         struct rte_intr_handle *intr_handle;
1432         struct i40e_hw *hw;
1433         struct i40e_filter_control_settings settings;
1434         struct rte_flow *p_flow;
1435         int ret;
1436         uint8_t aq_fail = 0;
1437
1438         PMD_INIT_FUNC_TRACE();
1439
1440         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1441                 return 0;
1442
1443         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1444         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1445         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1446         intr_handle = &pci_dev->intr_handle;
1447
1448         if (hw->adapter_stopped == 0)
1449                 i40e_dev_close(dev);
1450
1451         dev->dev_ops = NULL;
1452         dev->rx_pkt_burst = NULL;
1453         dev->tx_pkt_burst = NULL;
1454
1455         /* Clear PXE mode */
1456         i40e_clear_pxe_mode(hw);
1457
1458         /* Unconfigure filter control */
1459         memset(&settings, 0, sizeof(settings));
1460         ret = i40e_set_filter_control(hw, &settings);
1461         if (ret)
1462                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1463                                         ret);
1464
1465         /* Disable flow control */
1466         hw->fc.requested_mode = I40E_FC_NONE;
1467         i40e_set_fc(hw, &aq_fail, TRUE);
1468
1469         /* uninitialize pf host driver */
1470         i40e_pf_host_uninit(dev);
1471
1472         rte_free(dev->data->mac_addrs);
1473         dev->data->mac_addrs = NULL;
1474
1475         /* disable uio intr before callback unregister */
1476         rte_intr_disable(intr_handle);
1477
1478         /* register callback func to eal lib */
1479         rte_intr_callback_unregister(intr_handle,
1480                                      i40e_dev_interrupt_handler, dev);
1481
1482         i40e_rm_ethtype_filter_list(pf);
1483         i40e_rm_tunnel_filter_list(pf);
1484         i40e_rm_fdir_filter_list(pf);
1485
1486         /* Remove all flows */
1487         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1488                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1489                 rte_free(p_flow);
1490         }
1491
1492         /* Remove all Traffic Manager configuration */
1493         i40e_tm_conf_uninit(dev);
1494
1495         return 0;
1496 }
1497
1498 static int
1499 i40e_dev_configure(struct rte_eth_dev *dev)
1500 {
1501         struct i40e_adapter *ad =
1502                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1503         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1504         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1505         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1506         int i, ret;
1507
1508         ret = i40e_dev_sync_phy_type(hw);
1509         if (ret)
1510                 return ret;
1511
1512         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1513          * bulk allocation or vector Rx preconditions we will reset it.
1514          */
1515         ad->rx_bulk_alloc_allowed = true;
1516         ad->rx_vec_allowed = true;
1517         ad->tx_simple_allowed = true;
1518         ad->tx_vec_allowed = true;
1519
1520         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1521                 ret = i40e_fdir_setup(pf);
1522                 if (ret != I40E_SUCCESS) {
1523                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1524                         return -ENOTSUP;
1525                 }
1526                 ret = i40e_fdir_configure(dev);
1527                 if (ret < 0) {
1528                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1529                         goto err;
1530                 }
1531         } else
1532                 i40e_fdir_teardown(pf);
1533
1534         ret = i40e_dev_init_vlan(dev);
1535         if (ret < 0)
1536                 goto err;
1537
1538         /* VMDQ setup.
1539          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1540          *  RSS setting have different requirements.
1541          *  General PMD driver call sequence are NIC init, configure,
1542          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1543          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1544          *  applicable. So, VMDQ setting has to be done before
1545          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1546          *  For RSS setting, it will try to calculate actual configured RX queue
1547          *  number, which will be available after rx_queue_setup(). dev_start()
1548          *  function is good to place RSS setup.
1549          */
1550         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1551                 ret = i40e_vmdq_setup(dev);
1552                 if (ret)
1553                         goto err;
1554         }
1555
1556         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1557                 ret = i40e_dcb_setup(dev);
1558                 if (ret) {
1559                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1560                         goto err_dcb;
1561                 }
1562         }
1563
1564         TAILQ_INIT(&pf->flow_list);
1565
1566         return 0;
1567
1568 err_dcb:
1569         /* need to release vmdq resource if exists */
1570         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1571                 i40e_vsi_release(pf->vmdq[i].vsi);
1572                 pf->vmdq[i].vsi = NULL;
1573         }
1574         rte_free(pf->vmdq);
1575         pf->vmdq = NULL;
1576 err:
1577         /* need to release fdir resource if exists */
1578         i40e_fdir_teardown(pf);
1579         return ret;
1580 }
1581
1582 void
1583 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1584 {
1585         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1586         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1587         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1588         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1589         uint16_t msix_vect = vsi->msix_intr;
1590         uint16_t i;
1591
1592         for (i = 0; i < vsi->nb_qps; i++) {
1593                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1594                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1595                 rte_wmb();
1596         }
1597
1598         if (vsi->type != I40E_VSI_SRIOV) {
1599                 if (!rte_intr_allow_others(intr_handle)) {
1600                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1601                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1602                         I40E_WRITE_REG(hw,
1603                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1604                                        0);
1605                 } else {
1606                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1607                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1608                         I40E_WRITE_REG(hw,
1609                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1610                                                        msix_vect - 1), 0);
1611                 }
1612         } else {
1613                 uint32_t reg;
1614                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1615                         vsi->user_param + (msix_vect - 1);
1616
1617                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1618                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1619         }
1620         I40E_WRITE_FLUSH(hw);
1621 }
1622
1623 static void
1624 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1625                        int base_queue, int nb_queue,
1626                        uint16_t itr_idx)
1627 {
1628         int i;
1629         uint32_t val;
1630         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1631
1632         /* Bind all RX queues to allocated MSIX interrupt */
1633         for (i = 0; i < nb_queue; i++) {
1634                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1635                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1636                         ((base_queue + i + 1) <<
1637                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1638                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1639                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1640
1641                 if (i == nb_queue - 1)
1642                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1643                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1644         }
1645
1646         /* Write first RX queue to Link list register as the head element */
1647         if (vsi->type != I40E_VSI_SRIOV) {
1648                 uint16_t interval =
1649                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1650
1651                 if (msix_vect == I40E_MISC_VEC_ID) {
1652                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1653                                        (base_queue <<
1654                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1655                                        (0x0 <<
1656                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1657                         I40E_WRITE_REG(hw,
1658                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1659                                        interval);
1660                 } else {
1661                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1662                                        (base_queue <<
1663                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1664                                        (0x0 <<
1665                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1666                         I40E_WRITE_REG(hw,
1667                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1668                                                        msix_vect - 1),
1669                                        interval);
1670                 }
1671         } else {
1672                 uint32_t reg;
1673
1674                 if (msix_vect == I40E_MISC_VEC_ID) {
1675                         I40E_WRITE_REG(hw,
1676                                        I40E_VPINT_LNKLST0(vsi->user_param),
1677                                        (base_queue <<
1678                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1679                                        (0x0 <<
1680                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1681                 } else {
1682                         /* num_msix_vectors_vf needs to minus irq0 */
1683                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1684                                 vsi->user_param + (msix_vect - 1);
1685
1686                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1687                                        (base_queue <<
1688                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1689                                        (0x0 <<
1690                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1691                 }
1692         }
1693
1694         I40E_WRITE_FLUSH(hw);
1695 }
1696
1697 void
1698 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1699 {
1700         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1701         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1702         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1703         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1704         uint16_t msix_vect = vsi->msix_intr;
1705         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1706         uint16_t queue_idx = 0;
1707         int record = 0;
1708         uint32_t val;
1709         int i;
1710
1711         for (i = 0; i < vsi->nb_qps; i++) {
1712                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1713                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1714         }
1715
1716         /* INTENA flag is not auto-cleared for interrupt */
1717         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1718         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1719                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1720                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1721         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1722
1723         /* VF bind interrupt */
1724         if (vsi->type == I40E_VSI_SRIOV) {
1725                 __vsi_queues_bind_intr(vsi, msix_vect,
1726                                        vsi->base_queue, vsi->nb_qps,
1727                                        itr_idx);
1728                 return;
1729         }
1730
1731         /* PF & VMDq bind interrupt */
1732         if (rte_intr_dp_is_en(intr_handle)) {
1733                 if (vsi->type == I40E_VSI_MAIN) {
1734                         queue_idx = 0;
1735                         record = 1;
1736                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1737                         struct i40e_vsi *main_vsi =
1738                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1739                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1740                         record = 1;
1741                 }
1742         }
1743
1744         for (i = 0; i < vsi->nb_used_qps; i++) {
1745                 if (nb_msix <= 1) {
1746                         if (!rte_intr_allow_others(intr_handle))
1747                                 /* allow to share MISC_VEC_ID */
1748                                 msix_vect = I40E_MISC_VEC_ID;
1749
1750                         /* no enough msix_vect, map all to one */
1751                         __vsi_queues_bind_intr(vsi, msix_vect,
1752                                                vsi->base_queue + i,
1753                                                vsi->nb_used_qps - i,
1754                                                itr_idx);
1755                         for (; !!record && i < vsi->nb_used_qps; i++)
1756                                 intr_handle->intr_vec[queue_idx + i] =
1757                                         msix_vect;
1758                         break;
1759                 }
1760                 /* 1:1 queue/msix_vect mapping */
1761                 __vsi_queues_bind_intr(vsi, msix_vect,
1762                                        vsi->base_queue + i, 1,
1763                                        itr_idx);
1764                 if (!!record)
1765                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1766
1767                 msix_vect++;
1768                 nb_msix--;
1769         }
1770 }
1771
1772 static void
1773 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1774 {
1775         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1776         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1777         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1778         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1779         uint16_t interval = i40e_calc_itr_interval(\
1780                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1781         uint16_t msix_intr, i;
1782
1783         if (rte_intr_allow_others(intr_handle))
1784                 for (i = 0; i < vsi->nb_msix; i++) {
1785                         msix_intr = vsi->msix_intr + i;
1786                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1787                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1788                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1789                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1790                                 (interval <<
1791                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1792                 }
1793         else
1794                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1795                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1796                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1797                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1798                                (interval <<
1799                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1800
1801         I40E_WRITE_FLUSH(hw);
1802 }
1803
1804 static void
1805 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1806 {
1807         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1808         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1809         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1810         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1811         uint16_t msix_intr, i;
1812
1813         if (rte_intr_allow_others(intr_handle))
1814                 for (i = 0; i < vsi->nb_msix; i++) {
1815                         msix_intr = vsi->msix_intr + i;
1816                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1817                                        0);
1818                 }
1819         else
1820                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1821
1822         I40E_WRITE_FLUSH(hw);
1823 }
1824
1825 static inline uint8_t
1826 i40e_parse_link_speeds(uint16_t link_speeds)
1827 {
1828         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1829
1830         if (link_speeds & ETH_LINK_SPEED_40G)
1831                 link_speed |= I40E_LINK_SPEED_40GB;
1832         if (link_speeds & ETH_LINK_SPEED_25G)
1833                 link_speed |= I40E_LINK_SPEED_25GB;
1834         if (link_speeds & ETH_LINK_SPEED_20G)
1835                 link_speed |= I40E_LINK_SPEED_20GB;
1836         if (link_speeds & ETH_LINK_SPEED_10G)
1837                 link_speed |= I40E_LINK_SPEED_10GB;
1838         if (link_speeds & ETH_LINK_SPEED_1G)
1839                 link_speed |= I40E_LINK_SPEED_1GB;
1840         if (link_speeds & ETH_LINK_SPEED_100M)
1841                 link_speed |= I40E_LINK_SPEED_100MB;
1842
1843         return link_speed;
1844 }
1845
1846 static int
1847 i40e_phy_conf_link(struct i40e_hw *hw,
1848                    uint8_t abilities,
1849                    uint8_t force_speed,
1850                    bool is_up)
1851 {
1852         enum i40e_status_code status;
1853         struct i40e_aq_get_phy_abilities_resp phy_ab;
1854         struct i40e_aq_set_phy_config phy_conf;
1855         enum i40e_aq_phy_type cnt;
1856         uint32_t phy_type_mask = 0;
1857
1858         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1859                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1860                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1861                         I40E_AQ_PHY_FLAG_LOW_POWER;
1862         const uint8_t advt = I40E_LINK_SPEED_40GB |
1863                         I40E_LINK_SPEED_25GB |
1864                         I40E_LINK_SPEED_10GB |
1865                         I40E_LINK_SPEED_1GB |
1866                         I40E_LINK_SPEED_100MB;
1867         int ret = -ENOTSUP;
1868
1869
1870         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1871                                               NULL);
1872         if (status)
1873                 return ret;
1874
1875         /* If link already up, no need to set up again */
1876         if (is_up && phy_ab.phy_type != 0)
1877                 return I40E_SUCCESS;
1878
1879         memset(&phy_conf, 0, sizeof(phy_conf));
1880
1881         /* bits 0-2 use the values from get_phy_abilities_resp */
1882         abilities &= ~mask;
1883         abilities |= phy_ab.abilities & mask;
1884
1885         /* update ablities and speed */
1886         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1887                 phy_conf.link_speed = advt;
1888         else
1889                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1890
1891         phy_conf.abilities = abilities;
1892
1893
1894
1895         /* To enable link, phy_type mask needs to include each type */
1896         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1897                 phy_type_mask |= 1 << cnt;
1898
1899         /* use get_phy_abilities_resp value for the rest */
1900         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1901         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1902                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1903                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1904         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1905         phy_conf.eee_capability = phy_ab.eee_capability;
1906         phy_conf.eeer = phy_ab.eeer_val;
1907         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1908
1909         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1910                     phy_ab.abilities, phy_ab.link_speed);
1911         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1912                     phy_conf.abilities, phy_conf.link_speed);
1913
1914         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1915         if (status)
1916                 return ret;
1917
1918         return I40E_SUCCESS;
1919 }
1920
1921 static int
1922 i40e_apply_link_speed(struct rte_eth_dev *dev)
1923 {
1924         uint8_t speed;
1925         uint8_t abilities = 0;
1926         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1927         struct rte_eth_conf *conf = &dev->data->dev_conf;
1928
1929         speed = i40e_parse_link_speeds(conf->link_speeds);
1930         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1931         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1932                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1933         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1934
1935         return i40e_phy_conf_link(hw, abilities, speed, true);
1936 }
1937
1938 static int
1939 i40e_dev_start(struct rte_eth_dev *dev)
1940 {
1941         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1942         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1943         struct i40e_vsi *main_vsi = pf->main_vsi;
1944         int ret, i;
1945         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1946         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1947         uint32_t intr_vector = 0;
1948         struct i40e_vsi *vsi;
1949
1950         hw->adapter_stopped = 0;
1951
1952         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1953                 PMD_INIT_LOG(ERR,
1954                 "Invalid link_speeds for port %u, autonegotiation disabled",
1955                               dev->data->port_id);
1956                 return -EINVAL;
1957         }
1958
1959         rte_intr_disable(intr_handle);
1960
1961         if ((rte_intr_cap_multiple(intr_handle) ||
1962              !RTE_ETH_DEV_SRIOV(dev).active) &&
1963             dev->data->dev_conf.intr_conf.rxq != 0) {
1964                 intr_vector = dev->data->nb_rx_queues;
1965                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1966                 if (ret)
1967                         return ret;
1968         }
1969
1970         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1971                 intr_handle->intr_vec =
1972                         rte_zmalloc("intr_vec",
1973                                     dev->data->nb_rx_queues * sizeof(int),
1974                                     0);
1975                 if (!intr_handle->intr_vec) {
1976                         PMD_INIT_LOG(ERR,
1977                                 "Failed to allocate %d rx_queues intr_vec",
1978                                 dev->data->nb_rx_queues);
1979                         return -ENOMEM;
1980                 }
1981         }
1982
1983         /* Initialize VSI */
1984         ret = i40e_dev_rxtx_init(pf);
1985         if (ret != I40E_SUCCESS) {
1986                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1987                 goto err_up;
1988         }
1989
1990         /* Map queues with MSIX interrupt */
1991         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1992                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1993         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1994         i40e_vsi_enable_queues_intr(main_vsi);
1995
1996         /* Map VMDQ VSI queues with MSIX interrupt */
1997         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1998                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1999                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2000                                           I40E_ITR_INDEX_DEFAULT);
2001                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2002         }
2003
2004         /* enable FDIR MSIX interrupt */
2005         if (pf->fdir.fdir_vsi) {
2006                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2007                                           I40E_ITR_INDEX_NONE);
2008                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2009         }
2010
2011         /* Enable all queues which have been configured */
2012         ret = i40e_dev_switch_queues(pf, TRUE);
2013         if (ret != I40E_SUCCESS) {
2014                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2015                 goto err_up;
2016         }
2017
2018         /* Enable receiving broadcast packets */
2019         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2020         if (ret != I40E_SUCCESS)
2021                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2022
2023         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2024                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2025                                                 true, NULL);
2026                 if (ret != I40E_SUCCESS)
2027                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2028         }
2029
2030         /* Enable the VLAN promiscuous mode. */
2031         if (pf->vfs) {
2032                 for (i = 0; i < pf->vf_num; i++) {
2033                         vsi = pf->vfs[i].vsi;
2034                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2035                                                      true, NULL);
2036                 }
2037         }
2038
2039         /* Apply link configure */
2040         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2041                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2042                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2043                                 ETH_LINK_SPEED_40G)) {
2044                 PMD_DRV_LOG(ERR, "Invalid link setting");
2045                 goto err_up;
2046         }
2047         ret = i40e_apply_link_speed(dev);
2048         if (I40E_SUCCESS != ret) {
2049                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2050                 goto err_up;
2051         }
2052
2053         if (!rte_intr_allow_others(intr_handle)) {
2054                 rte_intr_callback_unregister(intr_handle,
2055                                              i40e_dev_interrupt_handler,
2056                                              (void *)dev);
2057                 /* configure and enable device interrupt */
2058                 i40e_pf_config_irq0(hw, FALSE);
2059                 i40e_pf_enable_irq0(hw);
2060
2061                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2062                         PMD_INIT_LOG(INFO,
2063                                 "lsc won't enable because of no intr multiplex");
2064         } else {
2065                 ret = i40e_aq_set_phy_int_mask(hw,
2066                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2067                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2068                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2069                 if (ret != I40E_SUCCESS)
2070                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2071
2072                 /* Call get_link_info aq commond to enable/disable LSE */
2073                 i40e_dev_link_update(dev, 0);
2074         }
2075
2076         /* enable uio intr after callback register */
2077         rte_intr_enable(intr_handle);
2078
2079         i40e_filter_restore(pf);
2080
2081         if (pf->tm_conf.root && !pf->tm_conf.committed)
2082                 PMD_DRV_LOG(WARNING,
2083                             "please call hierarchy_commit() "
2084                             "before starting the port");
2085
2086         return I40E_SUCCESS;
2087
2088 err_up:
2089         i40e_dev_switch_queues(pf, FALSE);
2090         i40e_dev_clear_queues(dev);
2091
2092         return ret;
2093 }
2094
2095 static void
2096 i40e_dev_stop(struct rte_eth_dev *dev)
2097 {
2098         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2099         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100         struct i40e_vsi *main_vsi = pf->main_vsi;
2101         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2102         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2103         int i;
2104
2105         if (hw->adapter_stopped == 1)
2106                 return;
2107         /* Disable all queues */
2108         i40e_dev_switch_queues(pf, FALSE);
2109
2110         /* un-map queues with interrupt registers */
2111         i40e_vsi_disable_queues_intr(main_vsi);
2112         i40e_vsi_queues_unbind_intr(main_vsi);
2113
2114         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2115                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2116                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2117         }
2118
2119         if (pf->fdir.fdir_vsi) {
2120                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2121                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2122         }
2123         /* Clear all queues and release memory */
2124         i40e_dev_clear_queues(dev);
2125
2126         /* Set link down */
2127         i40e_dev_set_link_down(dev);
2128
2129         if (!rte_intr_allow_others(intr_handle))
2130                 /* resume to the default handler */
2131                 rte_intr_callback_register(intr_handle,
2132                                            i40e_dev_interrupt_handler,
2133                                            (void *)dev);
2134
2135         /* Clean datapath event and queue/vec mapping */
2136         rte_intr_efd_disable(intr_handle);
2137         if (intr_handle->intr_vec) {
2138                 rte_free(intr_handle->intr_vec);
2139                 intr_handle->intr_vec = NULL;
2140         }
2141
2142         /* reset hierarchy commit */
2143         pf->tm_conf.committed = false;
2144
2145         hw->adapter_stopped = 1;
2146 }
2147
2148 static void
2149 i40e_dev_close(struct rte_eth_dev *dev)
2150 {
2151         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2152         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2153         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2154         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2155         struct i40e_mirror_rule *p_mirror;
2156         uint32_t reg;
2157         int i;
2158         int ret;
2159
2160         PMD_INIT_FUNC_TRACE();
2161
2162         i40e_dev_stop(dev);
2163
2164         /* Remove all mirror rules */
2165         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2166                 ret = i40e_aq_del_mirror_rule(hw,
2167                                               pf->main_vsi->veb->seid,
2168                                               p_mirror->rule_type,
2169                                               p_mirror->entries,
2170                                               p_mirror->num_entries,
2171                                               p_mirror->id);
2172                 if (ret < 0)
2173                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2174                                     "status = %d, aq_err = %d.", ret,
2175                                     hw->aq.asq_last_status);
2176
2177                 /* remove mirror software resource anyway */
2178                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2179                 rte_free(p_mirror);
2180                 pf->nb_mirror_rule--;
2181         }
2182
2183         i40e_dev_free_queues(dev);
2184
2185         /* Disable interrupt */
2186         i40e_pf_disable_irq0(hw);
2187         rte_intr_disable(intr_handle);
2188
2189         /* shutdown and destroy the HMC */
2190         i40e_shutdown_lan_hmc(hw);
2191
2192         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2193                 i40e_vsi_release(pf->vmdq[i].vsi);
2194                 pf->vmdq[i].vsi = NULL;
2195         }
2196         rte_free(pf->vmdq);
2197         pf->vmdq = NULL;
2198
2199         /* release all the existing VSIs and VEBs */
2200         i40e_fdir_teardown(pf);
2201         i40e_vsi_release(pf->main_vsi);
2202
2203         /* shutdown the adminq */
2204         i40e_aq_queue_shutdown(hw, true);
2205         i40e_shutdown_adminq(hw);
2206
2207         i40e_res_pool_destroy(&pf->qp_pool);
2208         i40e_res_pool_destroy(&pf->msix_pool);
2209
2210         /* force a PF reset to clean anything leftover */
2211         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2212         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2213                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2214         I40E_WRITE_FLUSH(hw);
2215 }
2216
2217 /*
2218  * Reset PF device only to re-initialize resources in PMD layer
2219  */
2220 static int
2221 i40e_dev_reset(struct rte_eth_dev *dev)
2222 {
2223         int ret;
2224
2225         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2226          * its VF to make them align with it. The detailed notification
2227          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2228          * To avoid unexpected behavior in VF, currently reset of PF with
2229          * SR-IOV activation is not supported. It might be supported later.
2230          */
2231         if (dev->data->sriov.active)
2232                 return -ENOTSUP;
2233
2234         ret = eth_i40e_dev_uninit(dev);
2235         if (ret)
2236                 return ret;
2237
2238         ret = eth_i40e_dev_init(dev);
2239
2240         return ret;
2241 }
2242
2243 static void
2244 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2245 {
2246         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2247         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2248         struct i40e_vsi *vsi = pf->main_vsi;
2249         int status;
2250
2251         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2252                                                      true, NULL, true);
2253         if (status != I40E_SUCCESS)
2254                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2255
2256         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2257                                                         TRUE, NULL);
2258         if (status != I40E_SUCCESS)
2259                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2260
2261 }
2262
2263 static void
2264 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2265 {
2266         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2267         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2268         struct i40e_vsi *vsi = pf->main_vsi;
2269         int status;
2270
2271         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2272                                                      false, NULL, true);
2273         if (status != I40E_SUCCESS)
2274                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2275
2276         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2277                                                         false, NULL);
2278         if (status != I40E_SUCCESS)
2279                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2280 }
2281
2282 static void
2283 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2284 {
2285         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2286         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2287         struct i40e_vsi *vsi = pf->main_vsi;
2288         int ret;
2289
2290         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2291         if (ret != I40E_SUCCESS)
2292                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2293 }
2294
2295 static void
2296 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2297 {
2298         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2299         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2300         struct i40e_vsi *vsi = pf->main_vsi;
2301         int ret;
2302
2303         if (dev->data->promiscuous == 1)
2304                 return; /* must remain in all_multicast mode */
2305
2306         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2307                                 vsi->seid, FALSE, NULL);
2308         if (ret != I40E_SUCCESS)
2309                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2310 }
2311
2312 /*
2313  * Set device link up.
2314  */
2315 static int
2316 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2317 {
2318         /* re-apply link speed setting */
2319         return i40e_apply_link_speed(dev);
2320 }
2321
2322 /*
2323  * Set device link down.
2324  */
2325 static int
2326 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2327 {
2328         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2329         uint8_t abilities = 0;
2330         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2331
2332         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2333         return i40e_phy_conf_link(hw, abilities, speed, false);
2334 }
2335
2336 int
2337 i40e_dev_link_update(struct rte_eth_dev *dev,
2338                      int wait_to_complete)
2339 {
2340 #define CHECK_INTERVAL 100  /* 100ms */
2341 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2342         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2343         struct i40e_link_status link_status;
2344         struct rte_eth_link link, old;
2345         int status;
2346         unsigned rep_cnt = MAX_REPEAT_TIME;
2347         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2348
2349         memset(&link, 0, sizeof(link));
2350         memset(&old, 0, sizeof(old));
2351         memset(&link_status, 0, sizeof(link_status));
2352         rte_i40e_dev_atomic_read_link_status(dev, &old);
2353
2354         do {
2355                 /* Get link status information from hardware */
2356                 status = i40e_aq_get_link_info(hw, enable_lse,
2357                                                 &link_status, NULL);
2358                 if (status != I40E_SUCCESS) {
2359                         link.link_speed = ETH_SPEED_NUM_100M;
2360                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2361                         PMD_DRV_LOG(ERR, "Failed to get link info");
2362                         goto out;
2363                 }
2364
2365                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2366                 if (!wait_to_complete || link.link_status)
2367                         break;
2368
2369                 rte_delay_ms(CHECK_INTERVAL);
2370         } while (--rep_cnt);
2371
2372         if (!link.link_status)
2373                 goto out;
2374
2375         /* i40e uses full duplex only */
2376         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2377
2378         /* Parse the link status */
2379         switch (link_status.link_speed) {
2380         case I40E_LINK_SPEED_100MB:
2381                 link.link_speed = ETH_SPEED_NUM_100M;
2382                 break;
2383         case I40E_LINK_SPEED_1GB:
2384                 link.link_speed = ETH_SPEED_NUM_1G;
2385                 break;
2386         case I40E_LINK_SPEED_10GB:
2387                 link.link_speed = ETH_SPEED_NUM_10G;
2388                 break;
2389         case I40E_LINK_SPEED_20GB:
2390                 link.link_speed = ETH_SPEED_NUM_20G;
2391                 break;
2392         case I40E_LINK_SPEED_25GB:
2393                 link.link_speed = ETH_SPEED_NUM_25G;
2394                 break;
2395         case I40E_LINK_SPEED_40GB:
2396                 link.link_speed = ETH_SPEED_NUM_40G;
2397                 break;
2398         default:
2399                 link.link_speed = ETH_SPEED_NUM_100M;
2400                 break;
2401         }
2402
2403         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2404                         ETH_LINK_SPEED_FIXED);
2405
2406 out:
2407         rte_i40e_dev_atomic_write_link_status(dev, &link);
2408         if (link.link_status == old.link_status)
2409                 return -1;
2410
2411         i40e_notify_all_vfs_link_status(dev);
2412
2413         return 0;
2414 }
2415
2416 /* Get all the statistics of a VSI */
2417 void
2418 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2419 {
2420         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2421         struct i40e_eth_stats *nes = &vsi->eth_stats;
2422         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2423         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2424
2425         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2426                             vsi->offset_loaded, &oes->rx_bytes,
2427                             &nes->rx_bytes);
2428         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2429                             vsi->offset_loaded, &oes->rx_unicast,
2430                             &nes->rx_unicast);
2431         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2432                             vsi->offset_loaded, &oes->rx_multicast,
2433                             &nes->rx_multicast);
2434         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2435                             vsi->offset_loaded, &oes->rx_broadcast,
2436                             &nes->rx_broadcast);
2437         /* exclude CRC bytes */
2438         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2439                 nes->rx_broadcast) * ETHER_CRC_LEN;
2440
2441         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2442                             &oes->rx_discards, &nes->rx_discards);
2443         /* GLV_REPC not supported */
2444         /* GLV_RMPC not supported */
2445         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2446                             &oes->rx_unknown_protocol,
2447                             &nes->rx_unknown_protocol);
2448         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2449                             vsi->offset_loaded, &oes->tx_bytes,
2450                             &nes->tx_bytes);
2451         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2452                             vsi->offset_loaded, &oes->tx_unicast,
2453                             &nes->tx_unicast);
2454         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2455                             vsi->offset_loaded, &oes->tx_multicast,
2456                             &nes->tx_multicast);
2457         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2458                             vsi->offset_loaded,  &oes->tx_broadcast,
2459                             &nes->tx_broadcast);
2460         /* GLV_TDPC not supported */
2461         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2462                             &oes->tx_errors, &nes->tx_errors);
2463         vsi->offset_loaded = true;
2464
2465         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2466                     vsi->vsi_id);
2467         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2468         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2469         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2470         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2471         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2472         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2473                     nes->rx_unknown_protocol);
2474         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2475         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2476         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2477         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2478         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2479         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2480         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2481                     vsi->vsi_id);
2482 }
2483
2484 static void
2485 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2486 {
2487         unsigned int i;
2488         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2489         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2490
2491         /* Get rx/tx bytes of internal transfer packets */
2492         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2493                         I40E_GLV_GORCL(hw->port),
2494                         pf->offset_loaded,
2495                         &pf->internal_stats_offset.rx_bytes,
2496                         &pf->internal_stats.rx_bytes);
2497
2498         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2499                         I40E_GLV_GOTCL(hw->port),
2500                         pf->offset_loaded,
2501                         &pf->internal_stats_offset.tx_bytes,
2502                         &pf->internal_stats.tx_bytes);
2503         /* Get total internal rx packet count */
2504         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2505                             I40E_GLV_UPRCL(hw->port),
2506                             pf->offset_loaded,
2507                             &pf->internal_stats_offset.rx_unicast,
2508                             &pf->internal_stats.rx_unicast);
2509         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2510                             I40E_GLV_MPRCL(hw->port),
2511                             pf->offset_loaded,
2512                             &pf->internal_stats_offset.rx_multicast,
2513                             &pf->internal_stats.rx_multicast);
2514         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2515                             I40E_GLV_BPRCL(hw->port),
2516                             pf->offset_loaded,
2517                             &pf->internal_stats_offset.rx_broadcast,
2518                             &pf->internal_stats.rx_broadcast);
2519
2520         /* exclude CRC size */
2521         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2522                 pf->internal_stats.rx_multicast +
2523                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2524
2525         /* Get statistics of struct i40e_eth_stats */
2526         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2527                             I40E_GLPRT_GORCL(hw->port),
2528                             pf->offset_loaded, &os->eth.rx_bytes,
2529                             &ns->eth.rx_bytes);
2530         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2531                             I40E_GLPRT_UPRCL(hw->port),
2532                             pf->offset_loaded, &os->eth.rx_unicast,
2533                             &ns->eth.rx_unicast);
2534         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2535                             I40E_GLPRT_MPRCL(hw->port),
2536                             pf->offset_loaded, &os->eth.rx_multicast,
2537                             &ns->eth.rx_multicast);
2538         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2539                             I40E_GLPRT_BPRCL(hw->port),
2540                             pf->offset_loaded, &os->eth.rx_broadcast,
2541                             &ns->eth.rx_broadcast);
2542         /* Workaround: CRC size should not be included in byte statistics,
2543          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2544          */
2545         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2546                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2547
2548         /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2549          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2550          * value.
2551          */
2552         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2553                 ns->eth.rx_bytes = 0;
2554         /* exlude internal rx bytes */
2555         else
2556                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2557
2558         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2559                             pf->offset_loaded, &os->eth.rx_discards,
2560                             &ns->eth.rx_discards);
2561         /* GLPRT_REPC not supported */
2562         /* GLPRT_RMPC not supported */
2563         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2564                             pf->offset_loaded,
2565                             &os->eth.rx_unknown_protocol,
2566                             &ns->eth.rx_unknown_protocol);
2567         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2568                             I40E_GLPRT_GOTCL(hw->port),
2569                             pf->offset_loaded, &os->eth.tx_bytes,
2570                             &ns->eth.tx_bytes);
2571         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2572                             I40E_GLPRT_UPTCL(hw->port),
2573                             pf->offset_loaded, &os->eth.tx_unicast,
2574                             &ns->eth.tx_unicast);
2575         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2576                             I40E_GLPRT_MPTCL(hw->port),
2577                             pf->offset_loaded, &os->eth.tx_multicast,
2578                             &ns->eth.tx_multicast);
2579         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2580                             I40E_GLPRT_BPTCL(hw->port),
2581                             pf->offset_loaded, &os->eth.tx_broadcast,
2582                             &ns->eth.tx_broadcast);
2583         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2584                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2585
2586         /* exclude internal tx bytes */
2587         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2588                 ns->eth.tx_bytes = 0;
2589         else
2590                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2591
2592         /* GLPRT_TEPC not supported */
2593
2594         /* additional port specific stats */
2595         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2596                             pf->offset_loaded, &os->tx_dropped_link_down,
2597                             &ns->tx_dropped_link_down);
2598         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2599                             pf->offset_loaded, &os->crc_errors,
2600                             &ns->crc_errors);
2601         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2602                             pf->offset_loaded, &os->illegal_bytes,
2603                             &ns->illegal_bytes);
2604         /* GLPRT_ERRBC not supported */
2605         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2606                             pf->offset_loaded, &os->mac_local_faults,
2607                             &ns->mac_local_faults);
2608         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2609                             pf->offset_loaded, &os->mac_remote_faults,
2610                             &ns->mac_remote_faults);
2611         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2612                             pf->offset_loaded, &os->rx_length_errors,
2613                             &ns->rx_length_errors);
2614         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2615                             pf->offset_loaded, &os->link_xon_rx,
2616                             &ns->link_xon_rx);
2617         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2618                             pf->offset_loaded, &os->link_xoff_rx,
2619                             &ns->link_xoff_rx);
2620         for (i = 0; i < 8; i++) {
2621                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2622                                     pf->offset_loaded,
2623                                     &os->priority_xon_rx[i],
2624                                     &ns->priority_xon_rx[i]);
2625                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2626                                     pf->offset_loaded,
2627                                     &os->priority_xoff_rx[i],
2628                                     &ns->priority_xoff_rx[i]);
2629         }
2630         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2631                             pf->offset_loaded, &os->link_xon_tx,
2632                             &ns->link_xon_tx);
2633         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2634                             pf->offset_loaded, &os->link_xoff_tx,
2635                             &ns->link_xoff_tx);
2636         for (i = 0; i < 8; i++) {
2637                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2638                                     pf->offset_loaded,
2639                                     &os->priority_xon_tx[i],
2640                                     &ns->priority_xon_tx[i]);
2641                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2642                                     pf->offset_loaded,
2643                                     &os->priority_xoff_tx[i],
2644                                     &ns->priority_xoff_tx[i]);
2645                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2646                                     pf->offset_loaded,
2647                                     &os->priority_xon_2_xoff[i],
2648                                     &ns->priority_xon_2_xoff[i]);
2649         }
2650         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2651                             I40E_GLPRT_PRC64L(hw->port),
2652                             pf->offset_loaded, &os->rx_size_64,
2653                             &ns->rx_size_64);
2654         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2655                             I40E_GLPRT_PRC127L(hw->port),
2656                             pf->offset_loaded, &os->rx_size_127,
2657                             &ns->rx_size_127);
2658         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2659                             I40E_GLPRT_PRC255L(hw->port),
2660                             pf->offset_loaded, &os->rx_size_255,
2661                             &ns->rx_size_255);
2662         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2663                             I40E_GLPRT_PRC511L(hw->port),
2664                             pf->offset_loaded, &os->rx_size_511,
2665                             &ns->rx_size_511);
2666         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2667                             I40E_GLPRT_PRC1023L(hw->port),
2668                             pf->offset_loaded, &os->rx_size_1023,
2669                             &ns->rx_size_1023);
2670         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2671                             I40E_GLPRT_PRC1522L(hw->port),
2672                             pf->offset_loaded, &os->rx_size_1522,
2673                             &ns->rx_size_1522);
2674         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2675                             I40E_GLPRT_PRC9522L(hw->port),
2676                             pf->offset_loaded, &os->rx_size_big,
2677                             &ns->rx_size_big);
2678         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2679                             pf->offset_loaded, &os->rx_undersize,
2680                             &ns->rx_undersize);
2681         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2682                             pf->offset_loaded, &os->rx_fragments,
2683                             &ns->rx_fragments);
2684         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2685                             pf->offset_loaded, &os->rx_oversize,
2686                             &ns->rx_oversize);
2687         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2688                             pf->offset_loaded, &os->rx_jabber,
2689                             &ns->rx_jabber);
2690         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2691                             I40E_GLPRT_PTC64L(hw->port),
2692                             pf->offset_loaded, &os->tx_size_64,
2693                             &ns->tx_size_64);
2694         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2695                             I40E_GLPRT_PTC127L(hw->port),
2696                             pf->offset_loaded, &os->tx_size_127,
2697                             &ns->tx_size_127);
2698         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2699                             I40E_GLPRT_PTC255L(hw->port),
2700                             pf->offset_loaded, &os->tx_size_255,
2701                             &ns->tx_size_255);
2702         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2703                             I40E_GLPRT_PTC511L(hw->port),
2704                             pf->offset_loaded, &os->tx_size_511,
2705                             &ns->tx_size_511);
2706         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2707                             I40E_GLPRT_PTC1023L(hw->port),
2708                             pf->offset_loaded, &os->tx_size_1023,
2709                             &ns->tx_size_1023);
2710         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2711                             I40E_GLPRT_PTC1522L(hw->port),
2712                             pf->offset_loaded, &os->tx_size_1522,
2713                             &ns->tx_size_1522);
2714         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2715                             I40E_GLPRT_PTC9522L(hw->port),
2716                             pf->offset_loaded, &os->tx_size_big,
2717                             &ns->tx_size_big);
2718         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2719                            pf->offset_loaded,
2720                            &os->fd_sb_match, &ns->fd_sb_match);
2721         /* GLPRT_MSPDC not supported */
2722         /* GLPRT_XEC not supported */
2723
2724         pf->offset_loaded = true;
2725
2726         if (pf->main_vsi)
2727                 i40e_update_vsi_stats(pf->main_vsi);
2728 }
2729
2730 /* Get all statistics of a port */
2731 static int
2732 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2733 {
2734         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2735         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2736         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2737         unsigned i;
2738
2739         /* call read registers - updates values, now write them to struct */
2740         i40e_read_stats_registers(pf, hw);
2741
2742         stats->ipackets = ns->eth.rx_unicast +
2743                         ns->eth.rx_multicast +
2744                         ns->eth.rx_broadcast -
2745                         ns->eth.rx_discards -
2746                         pf->main_vsi->eth_stats.rx_discards;
2747         stats->opackets = ns->eth.tx_unicast +
2748                         ns->eth.tx_multicast +
2749                         ns->eth.tx_broadcast;
2750         stats->ibytes   = ns->eth.rx_bytes;
2751         stats->obytes   = ns->eth.tx_bytes;
2752         stats->oerrors  = ns->eth.tx_errors +
2753                         pf->main_vsi->eth_stats.tx_errors;
2754
2755         /* Rx Errors */
2756         stats->imissed  = ns->eth.rx_discards +
2757                         pf->main_vsi->eth_stats.rx_discards;
2758         stats->ierrors  = ns->crc_errors +
2759                         ns->rx_length_errors + ns->rx_undersize +
2760                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2761
2762         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2763         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2764         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2765         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2766         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2767         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2768         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2769                     ns->eth.rx_unknown_protocol);
2770         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2771         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2772         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2773         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2774         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2775         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2776
2777         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2778                     ns->tx_dropped_link_down);
2779         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2780         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2781                     ns->illegal_bytes);
2782         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2783         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2784                     ns->mac_local_faults);
2785         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2786                     ns->mac_remote_faults);
2787         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2788                     ns->rx_length_errors);
2789         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2790         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2791         for (i = 0; i < 8; i++) {
2792                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2793                                 i, ns->priority_xon_rx[i]);
2794                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2795                                 i, ns->priority_xoff_rx[i]);
2796         }
2797         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2798         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2799         for (i = 0; i < 8; i++) {
2800                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2801                                 i, ns->priority_xon_tx[i]);
2802                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2803                                 i, ns->priority_xoff_tx[i]);
2804                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2805                                 i, ns->priority_xon_2_xoff[i]);
2806         }
2807         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2808         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2809         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2810         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2811         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2812         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2813         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2814         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2815         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2816         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2817         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2818         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2819         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2820         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2821         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2822         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2823         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2824         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2825         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2826                         ns->mac_short_packet_dropped);
2827         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2828                     ns->checksum_error);
2829         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2830         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2831         return 0;
2832 }
2833
2834 /* Reset the statistics */
2835 static void
2836 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2837 {
2838         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2839         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2840
2841         /* Mark PF and VSI stats to update the offset, aka "reset" */
2842         pf->offset_loaded = false;
2843         if (pf->main_vsi)
2844                 pf->main_vsi->offset_loaded = false;
2845
2846         /* read the stats, reading current register values into offset */
2847         i40e_read_stats_registers(pf, hw);
2848 }
2849
2850 static uint32_t
2851 i40e_xstats_calc_num(void)
2852 {
2853         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2854                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2855                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2856 }
2857
2858 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2859                                      struct rte_eth_xstat_name *xstats_names,
2860                                      __rte_unused unsigned limit)
2861 {
2862         unsigned count = 0;
2863         unsigned i, prio;
2864
2865         if (xstats_names == NULL)
2866                 return i40e_xstats_calc_num();
2867
2868         /* Note: limit checked in rte_eth_xstats_names() */
2869
2870         /* Get stats from i40e_eth_stats struct */
2871         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2872                 snprintf(xstats_names[count].name,
2873                          sizeof(xstats_names[count].name),
2874                          "%s", rte_i40e_stats_strings[i].name);
2875                 count++;
2876         }
2877
2878         /* Get individiual stats from i40e_hw_port struct */
2879         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2880                 snprintf(xstats_names[count].name,
2881                         sizeof(xstats_names[count].name),
2882                          "%s", rte_i40e_hw_port_strings[i].name);
2883                 count++;
2884         }
2885
2886         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2887                 for (prio = 0; prio < 8; prio++) {
2888                         snprintf(xstats_names[count].name,
2889                                  sizeof(xstats_names[count].name),
2890                                  "rx_priority%u_%s", prio,
2891                                  rte_i40e_rxq_prio_strings[i].name);
2892                         count++;
2893                 }
2894         }
2895
2896         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2897                 for (prio = 0; prio < 8; prio++) {
2898                         snprintf(xstats_names[count].name,
2899                                  sizeof(xstats_names[count].name),
2900                                  "tx_priority%u_%s", prio,
2901                                  rte_i40e_txq_prio_strings[i].name);
2902                         count++;
2903                 }
2904         }
2905         return count;
2906 }
2907
2908 static int
2909 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2910                     unsigned n)
2911 {
2912         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2913         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2914         unsigned i, count, prio;
2915         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2916
2917         count = i40e_xstats_calc_num();
2918         if (n < count)
2919                 return count;
2920
2921         i40e_read_stats_registers(pf, hw);
2922
2923         if (xstats == NULL)
2924                 return 0;
2925
2926         count = 0;
2927
2928         /* Get stats from i40e_eth_stats struct */
2929         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2930                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2931                         rte_i40e_stats_strings[i].offset);
2932                 xstats[count].id = count;
2933                 count++;
2934         }
2935
2936         /* Get individiual stats from i40e_hw_port struct */
2937         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2938                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2939                         rte_i40e_hw_port_strings[i].offset);
2940                 xstats[count].id = count;
2941                 count++;
2942         }
2943
2944         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2945                 for (prio = 0; prio < 8; prio++) {
2946                         xstats[count].value =
2947                                 *(uint64_t *)(((char *)hw_stats) +
2948                                 rte_i40e_rxq_prio_strings[i].offset +
2949                                 (sizeof(uint64_t) * prio));
2950                         xstats[count].id = count;
2951                         count++;
2952                 }
2953         }
2954
2955         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2956                 for (prio = 0; prio < 8; prio++) {
2957                         xstats[count].value =
2958                                 *(uint64_t *)(((char *)hw_stats) +
2959                                 rte_i40e_txq_prio_strings[i].offset +
2960                                 (sizeof(uint64_t) * prio));
2961                         xstats[count].id = count;
2962                         count++;
2963                 }
2964         }
2965
2966         return count;
2967 }
2968
2969 static int
2970 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2971                                  __rte_unused uint16_t queue_id,
2972                                  __rte_unused uint8_t stat_idx,
2973                                  __rte_unused uint8_t is_rx)
2974 {
2975         PMD_INIT_FUNC_TRACE();
2976
2977         return -ENOSYS;
2978 }
2979
2980 static int
2981 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2982 {
2983         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2984         u32 full_ver;
2985         u8 ver, patch;
2986         u16 build;
2987         int ret;
2988
2989         full_ver = hw->nvm.oem_ver;
2990         ver = (u8)(full_ver >> 24);
2991         build = (u16)((full_ver >> 8) & 0xffff);
2992         patch = (u8)(full_ver & 0xff);
2993
2994         ret = snprintf(fw_version, fw_size,
2995                  "%d.%d%d 0x%08x %d.%d.%d",
2996                  ((hw->nvm.version >> 12) & 0xf),
2997                  ((hw->nvm.version >> 4) & 0xff),
2998                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2999                  ver, build, patch);
3000
3001         ret += 1; /* add the size of '\0' */
3002         if (fw_size < (u32)ret)
3003                 return ret;
3004         else
3005                 return 0;
3006 }
3007
3008 static void
3009 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3010 {
3011         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3012         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3013         struct i40e_vsi *vsi = pf->main_vsi;
3014         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3015
3016         dev_info->pci_dev = pci_dev;
3017         dev_info->max_rx_queues = vsi->nb_qps;
3018         dev_info->max_tx_queues = vsi->nb_qps;
3019         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3020         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3021         dev_info->max_mac_addrs = vsi->max_macaddrs;
3022         dev_info->max_vfs = pci_dev->max_vfs;
3023         dev_info->rx_offload_capa =
3024                 DEV_RX_OFFLOAD_VLAN_STRIP |
3025                 DEV_RX_OFFLOAD_QINQ_STRIP |
3026                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3027                 DEV_RX_OFFLOAD_UDP_CKSUM |
3028                 DEV_RX_OFFLOAD_TCP_CKSUM;
3029         dev_info->tx_offload_capa =
3030                 DEV_TX_OFFLOAD_VLAN_INSERT |
3031                 DEV_TX_OFFLOAD_QINQ_INSERT |
3032                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3033                 DEV_TX_OFFLOAD_UDP_CKSUM |
3034                 DEV_TX_OFFLOAD_TCP_CKSUM |
3035                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3036                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3037                 DEV_TX_OFFLOAD_TCP_TSO |
3038                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3039                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3040                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3041                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3042         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3043                                                 sizeof(uint32_t);
3044         dev_info->reta_size = pf->hash_lut_size;
3045         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3046
3047         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3048                 .rx_thresh = {
3049                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3050                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3051                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3052                 },
3053                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3054                 .rx_drop_en = 0,
3055         };
3056
3057         dev_info->default_txconf = (struct rte_eth_txconf) {
3058                 .tx_thresh = {
3059                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3060                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3061                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3062                 },
3063                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3064                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3065                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3066                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3067         };
3068
3069         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3070                 .nb_max = I40E_MAX_RING_DESC,
3071                 .nb_min = I40E_MIN_RING_DESC,
3072                 .nb_align = I40E_ALIGN_RING_DESC,
3073         };
3074
3075         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3076                 .nb_max = I40E_MAX_RING_DESC,
3077                 .nb_min = I40E_MIN_RING_DESC,
3078                 .nb_align = I40E_ALIGN_RING_DESC,
3079                 .nb_seg_max = I40E_TX_MAX_SEG,
3080                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3081         };
3082
3083         if (pf->flags & I40E_FLAG_VMDQ) {
3084                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3085                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3086                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3087                                                 pf->max_nb_vmdq_vsi;
3088                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3089                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3090                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3091         }
3092
3093         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3094                 /* For XL710 */
3095                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3096         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3097                 /* For XXV710 */
3098                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3099         else
3100                 /* For X710 */
3101                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3102 }
3103
3104 static int
3105 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3106 {
3107         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3108         struct i40e_vsi *vsi = pf->main_vsi;
3109         PMD_INIT_FUNC_TRACE();
3110
3111         if (on)
3112                 return i40e_vsi_add_vlan(vsi, vlan_id);
3113         else
3114                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3115 }
3116
3117 static int
3118 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3119                                 enum rte_vlan_type vlan_type,
3120                                 uint16_t tpid, int qinq)
3121 {
3122         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3123         uint64_t reg_r = 0;
3124         uint64_t reg_w = 0;
3125         uint16_t reg_id = 3;
3126         int ret;
3127
3128         if (qinq) {
3129                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3130                         reg_id = 2;
3131         }
3132
3133         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3134                                           &reg_r, NULL);
3135         if (ret != I40E_SUCCESS) {
3136                 PMD_DRV_LOG(ERR,
3137                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3138                            reg_id);
3139                 return -EIO;
3140         }
3141         PMD_DRV_LOG(DEBUG,
3142                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3143                     reg_id, reg_r);
3144
3145         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3146         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3147         if (reg_r == reg_w) {
3148                 PMD_DRV_LOG(DEBUG, "No need to write");
3149                 return 0;
3150         }
3151
3152         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3153                                            reg_w, NULL);
3154         if (ret != I40E_SUCCESS) {
3155                 PMD_DRV_LOG(ERR,
3156                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3157                             reg_id);
3158                 return -EIO;
3159         }
3160         PMD_DRV_LOG(DEBUG,
3161                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3162                     reg_w, reg_id);
3163
3164         return 0;
3165 }
3166
3167 static int
3168 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3169                    enum rte_vlan_type vlan_type,
3170                    uint16_t tpid)
3171 {
3172         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3173         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3174         int ret = 0;
3175
3176         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3177              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3178             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3179                 PMD_DRV_LOG(ERR,
3180                             "Unsupported vlan type.");
3181                 return -EINVAL;
3182         }
3183         /* 802.1ad frames ability is added in NVM API 1.7*/
3184         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3185                 if (qinq) {
3186                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3187                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3188                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3189                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3190                 } else {
3191                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3192                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3193                 }
3194                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3195                 if (ret != I40E_SUCCESS) {
3196                         PMD_DRV_LOG(ERR,
3197                                     "Set switch config failed aq_err: %d",
3198                                     hw->aq.asq_last_status);
3199                         ret = -EIO;
3200                 }
3201         } else
3202                 /* If NVM API < 1.7, keep the register setting */
3203                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3204                                                       tpid, qinq);
3205
3206         return ret;
3207 }
3208
3209 static void
3210 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3211 {
3212         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3213         struct i40e_vsi *vsi = pf->main_vsi;
3214
3215         if (mask & ETH_VLAN_FILTER_MASK) {
3216                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3217                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3218                 else
3219                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3220         }
3221
3222         if (mask & ETH_VLAN_STRIP_MASK) {
3223                 /* Enable or disable VLAN stripping */
3224                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3225                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3226                 else
3227                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3228         }
3229
3230         if (mask & ETH_VLAN_EXTEND_MASK) {
3231                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3232                         i40e_vsi_config_double_vlan(vsi, TRUE);
3233                         /* Set global registers with default ethertype. */
3234                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3235                                            ETHER_TYPE_VLAN);
3236                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3237                                            ETHER_TYPE_VLAN);
3238                 }
3239                 else
3240                         i40e_vsi_config_double_vlan(vsi, FALSE);
3241         }
3242 }
3243
3244 static void
3245 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3246                           __rte_unused uint16_t queue,
3247                           __rte_unused int on)
3248 {
3249         PMD_INIT_FUNC_TRACE();
3250 }
3251
3252 static int
3253 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3254 {
3255         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3256         struct i40e_vsi *vsi = pf->main_vsi;
3257         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3258         struct i40e_vsi_vlan_pvid_info info;
3259
3260         memset(&info, 0, sizeof(info));
3261         info.on = on;
3262         if (info.on)
3263                 info.config.pvid = pvid;
3264         else {
3265                 info.config.reject.tagged =
3266                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3267                 info.config.reject.untagged =
3268                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3269         }
3270
3271         return i40e_vsi_vlan_pvid_set(vsi, &info);
3272 }
3273
3274 static int
3275 i40e_dev_led_on(struct rte_eth_dev *dev)
3276 {
3277         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3278         uint32_t mode = i40e_led_get(hw);
3279
3280         if (mode == 0)
3281                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3282
3283         return 0;
3284 }
3285
3286 static int
3287 i40e_dev_led_off(struct rte_eth_dev *dev)
3288 {
3289         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3290         uint32_t mode = i40e_led_get(hw);
3291
3292         if (mode != 0)
3293                 i40e_led_set(hw, 0, false);
3294
3295         return 0;
3296 }
3297
3298 static int
3299 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3300 {
3301         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3302         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3303
3304         fc_conf->pause_time = pf->fc_conf.pause_time;
3305
3306         /* read out from register, in case they are modified by other port */
3307         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3308                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3309         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3310                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3311
3312         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3313         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3314
3315          /* Return current mode according to actual setting*/
3316         switch (hw->fc.current_mode) {
3317         case I40E_FC_FULL:
3318                 fc_conf->mode = RTE_FC_FULL;
3319                 break;
3320         case I40E_FC_TX_PAUSE:
3321                 fc_conf->mode = RTE_FC_TX_PAUSE;
3322                 break;
3323         case I40E_FC_RX_PAUSE:
3324                 fc_conf->mode = RTE_FC_RX_PAUSE;
3325                 break;
3326         case I40E_FC_NONE:
3327         default:
3328                 fc_conf->mode = RTE_FC_NONE;
3329         };
3330
3331         return 0;
3332 }
3333
3334 static int
3335 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3336 {
3337         uint32_t mflcn_reg, fctrl_reg, reg;
3338         uint32_t max_high_water;
3339         uint8_t i, aq_failure;
3340         int err;
3341         struct i40e_hw *hw;
3342         struct i40e_pf *pf;
3343         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3344                 [RTE_FC_NONE] = I40E_FC_NONE,
3345                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3346                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3347                 [RTE_FC_FULL] = I40E_FC_FULL
3348         };
3349
3350         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3351
3352         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3353         if ((fc_conf->high_water > max_high_water) ||
3354                         (fc_conf->high_water < fc_conf->low_water)) {
3355                 PMD_INIT_LOG(ERR,
3356                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3357                         max_high_water);
3358                 return -EINVAL;
3359         }
3360
3361         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3362         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3363         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3364
3365         pf->fc_conf.pause_time = fc_conf->pause_time;
3366         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3367         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3368
3369         PMD_INIT_FUNC_TRACE();
3370
3371         /* All the link flow control related enable/disable register
3372          * configuration is handle by the F/W
3373          */
3374         err = i40e_set_fc(hw, &aq_failure, true);
3375         if (err < 0)
3376                 return -ENOSYS;
3377
3378         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3379                 /* Configure flow control refresh threshold,
3380                  * the value for stat_tx_pause_refresh_timer[8]
3381                  * is used for global pause operation.
3382                  */
3383
3384                 I40E_WRITE_REG(hw,
3385                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3386                                pf->fc_conf.pause_time);
3387
3388                 /* configure the timer value included in transmitted pause
3389                  * frame,
3390                  * the value for stat_tx_pause_quanta[8] is used for global
3391                  * pause operation
3392                  */
3393                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3394                                pf->fc_conf.pause_time);
3395
3396                 fctrl_reg = I40E_READ_REG(hw,
3397                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3398
3399                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3400                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3401                 else
3402                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3403
3404                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3405                                fctrl_reg);
3406         } else {
3407                 /* Configure pause time (2 TCs per register) */
3408                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3409                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3410                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3411
3412                 /* Configure flow control refresh threshold value */
3413                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3414                                pf->fc_conf.pause_time / 2);
3415
3416                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3417
3418                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3419                  *depending on configuration
3420                  */
3421                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3422                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3423                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3424                 } else {
3425                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3426                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3427                 }
3428
3429                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3430         }
3431
3432         /* config the water marker both based on the packets and bytes */
3433         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3434                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3435                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3436         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3437                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3438                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3439         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3440                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3441                        << I40E_KILOSHIFT);
3442         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3443                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3444                        << I40E_KILOSHIFT);
3445
3446         I40E_WRITE_FLUSH(hw);
3447
3448         return 0;
3449 }
3450
3451 static int
3452 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3453                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3454 {
3455         PMD_INIT_FUNC_TRACE();
3456
3457         return -ENOSYS;
3458 }
3459
3460 /* Add a MAC address, and update filters */
3461 static int
3462 i40e_macaddr_add(struct rte_eth_dev *dev,
3463                  struct ether_addr *mac_addr,
3464                  __rte_unused uint32_t index,
3465                  uint32_t pool)
3466 {
3467         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3468         struct i40e_mac_filter_info mac_filter;
3469         struct i40e_vsi *vsi;
3470         int ret;
3471
3472         /* If VMDQ not enabled or configured, return */
3473         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3474                           !pf->nb_cfg_vmdq_vsi)) {
3475                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3476                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3477                         pool);
3478                 return -ENOTSUP;
3479         }
3480
3481         if (pool > pf->nb_cfg_vmdq_vsi) {
3482                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3483                                 pool, pf->nb_cfg_vmdq_vsi);
3484                 return -EINVAL;
3485         }
3486
3487         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3488         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3489                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3490         else
3491                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3492
3493         if (pool == 0)
3494                 vsi = pf->main_vsi;
3495         else
3496                 vsi = pf->vmdq[pool - 1].vsi;
3497
3498         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3499         if (ret != I40E_SUCCESS) {
3500                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3501                 return -ENODEV;
3502         }
3503         return 0;
3504 }
3505
3506 /* Remove a MAC address, and update filters */
3507 static void
3508 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3509 {
3510         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3511         struct i40e_vsi *vsi;
3512         struct rte_eth_dev_data *data = dev->data;
3513         struct ether_addr *macaddr;
3514         int ret;
3515         uint32_t i;
3516         uint64_t pool_sel;
3517
3518         macaddr = &(data->mac_addrs[index]);
3519
3520         pool_sel = dev->data->mac_pool_sel[index];
3521
3522         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3523                 if (pool_sel & (1ULL << i)) {
3524                         if (i == 0)
3525                                 vsi = pf->main_vsi;
3526                         else {
3527                                 /* No VMDQ pool enabled or configured */
3528                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3529                                         (i > pf->nb_cfg_vmdq_vsi)) {
3530                                         PMD_DRV_LOG(ERR,
3531                                                 "No VMDQ pool enabled/configured");
3532                                         return;
3533                                 }
3534                                 vsi = pf->vmdq[i - 1].vsi;
3535                         }
3536                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3537
3538                         if (ret) {
3539                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3540                                 return;
3541                         }
3542                 }
3543         }
3544 }
3545
3546 /* Set perfect match or hash match of MAC and VLAN for a VF */
3547 static int
3548 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3549                  struct rte_eth_mac_filter *filter,
3550                  bool add)
3551 {
3552         struct i40e_hw *hw;
3553         struct i40e_mac_filter_info mac_filter;
3554         struct ether_addr old_mac;
3555         struct ether_addr *new_mac;
3556         struct i40e_pf_vf *vf = NULL;
3557         uint16_t vf_id;
3558         int ret;
3559
3560         if (pf == NULL) {
3561                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3562                 return -EINVAL;
3563         }
3564         hw = I40E_PF_TO_HW(pf);
3565
3566         if (filter == NULL) {
3567                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3568                 return -EINVAL;
3569         }
3570
3571         new_mac = &filter->mac_addr;
3572
3573         if (is_zero_ether_addr(new_mac)) {
3574                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3575                 return -EINVAL;
3576         }
3577
3578         vf_id = filter->dst_id;
3579
3580         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3581                 PMD_DRV_LOG(ERR, "Invalid argument.");
3582                 return -EINVAL;
3583         }
3584         vf = &pf->vfs[vf_id];
3585
3586         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3587                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3588                 return -EINVAL;
3589         }
3590
3591         if (add) {
3592                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3593                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3594                                 ETHER_ADDR_LEN);
3595                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3596                                  ETHER_ADDR_LEN);
3597
3598                 mac_filter.filter_type = filter->filter_type;
3599                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3600                 if (ret != I40E_SUCCESS) {
3601                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3602                         return -1;
3603                 }
3604                 ether_addr_copy(new_mac, &pf->dev_addr);
3605         } else {
3606                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3607                                 ETHER_ADDR_LEN);
3608                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3609                 if (ret != I40E_SUCCESS) {
3610                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3611                         return -1;
3612                 }
3613
3614                 /* Clear device address as it has been removed */
3615                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3616                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3617         }
3618
3619         return 0;
3620 }
3621
3622 /* MAC filter handle */
3623 static int
3624 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3625                 void *arg)
3626 {
3627         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3628         struct rte_eth_mac_filter *filter;
3629         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3630         int ret = I40E_NOT_SUPPORTED;
3631
3632         filter = (struct rte_eth_mac_filter *)(arg);
3633
3634         switch (filter_op) {
3635         case RTE_ETH_FILTER_NOP:
3636                 ret = I40E_SUCCESS;
3637                 break;
3638         case RTE_ETH_FILTER_ADD:
3639                 i40e_pf_disable_irq0(hw);
3640                 if (filter->is_vf)
3641                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3642                 i40e_pf_enable_irq0(hw);
3643                 break;
3644         case RTE_ETH_FILTER_DELETE:
3645                 i40e_pf_disable_irq0(hw);
3646                 if (filter->is_vf)
3647                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3648                 i40e_pf_enable_irq0(hw);
3649                 break;
3650         default:
3651                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3652                 ret = I40E_ERR_PARAM;
3653                 break;
3654         }
3655
3656         return ret;
3657 }
3658
3659 static int
3660 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3661 {
3662         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3663         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3664         int ret;
3665
3666         if (!lut)
3667                 return -EINVAL;
3668
3669         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3670                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3671                                           lut, lut_size);
3672                 if (ret) {
3673                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3674                         return ret;
3675                 }
3676         } else {
3677                 uint32_t *lut_dw = (uint32_t *)lut;
3678                 uint16_t i, lut_size_dw = lut_size / 4;
3679
3680                 for (i = 0; i < lut_size_dw; i++)
3681                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3682         }
3683
3684         return 0;
3685 }
3686
3687 static int
3688 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3689 {
3690         struct i40e_pf *pf;
3691         struct i40e_hw *hw;
3692         int ret;
3693
3694         if (!vsi || !lut)
3695                 return -EINVAL;
3696
3697         pf = I40E_VSI_TO_PF(vsi);
3698         hw = I40E_VSI_TO_HW(vsi);
3699
3700         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3701                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3702                                           lut, lut_size);
3703                 if (ret) {
3704                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3705                         return ret;
3706                 }
3707         } else {
3708                 uint32_t *lut_dw = (uint32_t *)lut;
3709                 uint16_t i, lut_size_dw = lut_size / 4;
3710
3711                 for (i = 0; i < lut_size_dw; i++)
3712                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3713                 I40E_WRITE_FLUSH(hw);
3714         }
3715
3716         return 0;
3717 }
3718
3719 static int
3720 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3721                          struct rte_eth_rss_reta_entry64 *reta_conf,
3722                          uint16_t reta_size)
3723 {
3724         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3725         uint16_t i, lut_size = pf->hash_lut_size;
3726         uint16_t idx, shift;
3727         uint8_t *lut;
3728         int ret;
3729
3730         if (reta_size != lut_size ||
3731                 reta_size > ETH_RSS_RETA_SIZE_512) {
3732                 PMD_DRV_LOG(ERR,
3733                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3734                         reta_size, lut_size);
3735                 return -EINVAL;
3736         }
3737
3738         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3739         if (!lut) {
3740                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3741                 return -ENOMEM;
3742         }
3743         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3744         if (ret)
3745                 goto out;
3746         for (i = 0; i < reta_size; i++) {
3747                 idx = i / RTE_RETA_GROUP_SIZE;
3748                 shift = i % RTE_RETA_GROUP_SIZE;
3749                 if (reta_conf[idx].mask & (1ULL << shift))
3750                         lut[i] = reta_conf[idx].reta[shift];
3751         }
3752         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3753
3754 out:
3755         rte_free(lut);
3756
3757         return ret;
3758 }
3759
3760 static int
3761 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3762                         struct rte_eth_rss_reta_entry64 *reta_conf,
3763                         uint16_t reta_size)
3764 {
3765         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3766         uint16_t i, lut_size = pf->hash_lut_size;
3767         uint16_t idx, shift;
3768         uint8_t *lut;
3769         int ret;
3770
3771         if (reta_size != lut_size ||
3772                 reta_size > ETH_RSS_RETA_SIZE_512) {
3773                 PMD_DRV_LOG(ERR,
3774                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3775                         reta_size, lut_size);
3776                 return -EINVAL;
3777         }
3778
3779         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3780         if (!lut) {
3781                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3782                 return -ENOMEM;
3783         }
3784
3785         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3786         if (ret)
3787                 goto out;
3788         for (i = 0; i < reta_size; i++) {
3789                 idx = i / RTE_RETA_GROUP_SIZE;
3790                 shift = i % RTE_RETA_GROUP_SIZE;
3791                 if (reta_conf[idx].mask & (1ULL << shift))
3792                         reta_conf[idx].reta[shift] = lut[i];
3793         }
3794
3795 out:
3796         rte_free(lut);
3797
3798         return ret;
3799 }
3800
3801 /**
3802  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3803  * @hw:   pointer to the HW structure
3804  * @mem:  pointer to mem struct to fill out
3805  * @size: size of memory requested
3806  * @alignment: what to align the allocation to
3807  **/
3808 enum i40e_status_code
3809 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3810                         struct i40e_dma_mem *mem,
3811                         u64 size,
3812                         u32 alignment)
3813 {
3814         const struct rte_memzone *mz = NULL;
3815         char z_name[RTE_MEMZONE_NAMESIZE];
3816
3817         if (!mem)
3818                 return I40E_ERR_PARAM;
3819
3820         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3821         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3822                                          alignment, RTE_PGSIZE_2M);
3823         if (!mz)
3824                 return I40E_ERR_NO_MEMORY;
3825
3826         mem->size = size;
3827         mem->va = mz->addr;
3828         mem->pa = mz->phys_addr;
3829         mem->zone = (const void *)mz;
3830         PMD_DRV_LOG(DEBUG,
3831                 "memzone %s allocated with physical address: %"PRIu64,
3832                 mz->name, mem->pa);
3833
3834         return I40E_SUCCESS;
3835 }
3836
3837 /**
3838  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3839  * @hw:   pointer to the HW structure
3840  * @mem:  ptr to mem struct to free
3841  **/
3842 enum i40e_status_code
3843 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3844                     struct i40e_dma_mem *mem)
3845 {
3846         if (!mem)
3847                 return I40E_ERR_PARAM;
3848
3849         PMD_DRV_LOG(DEBUG,
3850                 "memzone %s to be freed with physical address: %"PRIu64,
3851                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3852         rte_memzone_free((const struct rte_memzone *)mem->zone);
3853         mem->zone = NULL;
3854         mem->va = NULL;
3855         mem->pa = (u64)0;
3856
3857         return I40E_SUCCESS;
3858 }
3859
3860 /**
3861  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3862  * @hw:   pointer to the HW structure
3863  * @mem:  pointer to mem struct to fill out
3864  * @size: size of memory requested
3865  **/
3866 enum i40e_status_code
3867 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3868                          struct i40e_virt_mem *mem,
3869                          u32 size)
3870 {
3871         if (!mem)
3872                 return I40E_ERR_PARAM;
3873
3874         mem->size = size;
3875         mem->va = rte_zmalloc("i40e", size, 0);
3876
3877         if (mem->va)
3878                 return I40E_SUCCESS;
3879         else
3880                 return I40E_ERR_NO_MEMORY;
3881 }
3882
3883 /**
3884  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3885  * @hw:   pointer to the HW structure
3886  * @mem:  pointer to mem struct to free
3887  **/
3888 enum i40e_status_code
3889 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3890                      struct i40e_virt_mem *mem)
3891 {
3892         if (!mem)
3893                 return I40E_ERR_PARAM;
3894
3895         rte_free(mem->va);
3896         mem->va = NULL;
3897
3898         return I40E_SUCCESS;
3899 }
3900
3901 void
3902 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3903 {
3904         rte_spinlock_init(&sp->spinlock);
3905 }
3906
3907 void
3908 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3909 {
3910         rte_spinlock_lock(&sp->spinlock);
3911 }
3912
3913 void
3914 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3915 {
3916         rte_spinlock_unlock(&sp->spinlock);
3917 }
3918
3919 void
3920 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3921 {
3922         return;
3923 }
3924
3925 /**
3926  * Get the hardware capabilities, which will be parsed
3927  * and saved into struct i40e_hw.
3928  */
3929 static int
3930 i40e_get_cap(struct i40e_hw *hw)
3931 {
3932         struct i40e_aqc_list_capabilities_element_resp *buf;
3933         uint16_t len, size = 0;
3934         int ret;
3935
3936         /* Calculate a huge enough buff for saving response data temporarily */
3937         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3938                                                 I40E_MAX_CAP_ELE_NUM;
3939         buf = rte_zmalloc("i40e", len, 0);
3940         if (!buf) {
3941                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3942                 return I40E_ERR_NO_MEMORY;
3943         }
3944
3945         /* Get, parse the capabilities and save it to hw */
3946         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3947                         i40e_aqc_opc_list_func_capabilities, NULL);
3948         if (ret != I40E_SUCCESS)
3949                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3950
3951         /* Free the temporary buffer after being used */
3952         rte_free(buf);
3953
3954         return ret;
3955 }
3956
3957 static int
3958 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3959 {
3960         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3961         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3962         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3963         uint16_t qp_count = 0, vsi_count = 0;
3964
3965         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3966                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3967                 return -EINVAL;
3968         }
3969         /* Add the parameter init for LFC */
3970         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3971         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3972         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3973
3974         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3975         pf->max_num_vsi = hw->func_caps.num_vsis;
3976         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3977         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3978         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3979
3980         /* FDir queue/VSI allocation */
3981         pf->fdir_qp_offset = 0;
3982         if (hw->func_caps.fd) {
3983                 pf->flags |= I40E_FLAG_FDIR;
3984                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3985         } else {
3986                 pf->fdir_nb_qps = 0;
3987         }
3988         qp_count += pf->fdir_nb_qps;
3989         vsi_count += 1;
3990
3991         /* LAN queue/VSI allocation */
3992         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3993         if (!hw->func_caps.rss) {
3994                 pf->lan_nb_qps = 1;
3995         } else {
3996                 pf->flags |= I40E_FLAG_RSS;
3997                 if (hw->mac.type == I40E_MAC_X722)
3998                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3999                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4000         }
4001         qp_count += pf->lan_nb_qps;
4002         vsi_count += 1;
4003
4004         /* VF queue/VSI allocation */
4005         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4006         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4007                 pf->flags |= I40E_FLAG_SRIOV;
4008                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4009                 pf->vf_num = pci_dev->max_vfs;
4010                 PMD_DRV_LOG(DEBUG,
4011                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4012                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4013         } else {
4014                 pf->vf_nb_qps = 0;
4015                 pf->vf_num = 0;
4016         }
4017         qp_count += pf->vf_nb_qps * pf->vf_num;
4018         vsi_count += pf->vf_num;
4019
4020         /* VMDq queue/VSI allocation */
4021         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4022         pf->vmdq_nb_qps = 0;
4023         pf->max_nb_vmdq_vsi = 0;
4024         if (hw->func_caps.vmdq) {
4025                 if (qp_count < hw->func_caps.num_tx_qp &&
4026                         vsi_count < hw->func_caps.num_vsis) {
4027                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4028                                 qp_count) / pf->vmdq_nb_qp_max;
4029
4030                         /* Limit the maximum number of VMDq vsi to the maximum
4031                          * ethdev can support
4032                          */
4033                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4034                                 hw->func_caps.num_vsis - vsi_count);
4035                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4036                                 ETH_64_POOLS);
4037                         if (pf->max_nb_vmdq_vsi) {
4038                                 pf->flags |= I40E_FLAG_VMDQ;
4039                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4040                                 PMD_DRV_LOG(DEBUG,
4041                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4042                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4043                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4044                         } else {
4045                                 PMD_DRV_LOG(INFO,
4046                                         "No enough queues left for VMDq");
4047                         }
4048                 } else {
4049                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4050                 }
4051         }
4052         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4053         vsi_count += pf->max_nb_vmdq_vsi;
4054
4055         if (hw->func_caps.dcb)
4056                 pf->flags |= I40E_FLAG_DCB;
4057
4058         if (qp_count > hw->func_caps.num_tx_qp) {
4059                 PMD_DRV_LOG(ERR,
4060                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4061                         qp_count, hw->func_caps.num_tx_qp);
4062                 return -EINVAL;
4063         }
4064         if (vsi_count > hw->func_caps.num_vsis) {
4065                 PMD_DRV_LOG(ERR,
4066                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4067                         vsi_count, hw->func_caps.num_vsis);
4068                 return -EINVAL;
4069         }
4070
4071         return 0;
4072 }
4073
4074 static int
4075 i40e_pf_get_switch_config(struct i40e_pf *pf)
4076 {
4077         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4078         struct i40e_aqc_get_switch_config_resp *switch_config;
4079         struct i40e_aqc_switch_config_element_resp *element;
4080         uint16_t start_seid = 0, num_reported;
4081         int ret;
4082
4083         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4084                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4085         if (!switch_config) {
4086                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4087                 return -ENOMEM;
4088         }
4089
4090         /* Get the switch configurations */
4091         ret = i40e_aq_get_switch_config(hw, switch_config,
4092                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4093         if (ret != I40E_SUCCESS) {
4094                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4095                 goto fail;
4096         }
4097         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4098         if (num_reported != 1) { /* The number should be 1 */
4099                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4100                 goto fail;
4101         }
4102
4103         /* Parse the switch configuration elements */
4104         element = &(switch_config->element[0]);
4105         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4106                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4107                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4108         } else
4109                 PMD_DRV_LOG(INFO, "Unknown element type");
4110
4111 fail:
4112         rte_free(switch_config);
4113
4114         return ret;
4115 }
4116
4117 static int
4118 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4119                         uint32_t num)
4120 {
4121         struct pool_entry *entry;
4122
4123         if (pool == NULL || num == 0)
4124                 return -EINVAL;
4125
4126         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4127         if (entry == NULL) {
4128                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4129                 return -ENOMEM;
4130         }
4131
4132         /* queue heap initialize */
4133         pool->num_free = num;
4134         pool->num_alloc = 0;
4135         pool->base = base;
4136         LIST_INIT(&pool->alloc_list);
4137         LIST_INIT(&pool->free_list);
4138
4139         /* Initialize element  */
4140         entry->base = 0;
4141         entry->len = num;
4142
4143         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4144         return 0;
4145 }
4146
4147 static void
4148 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4149 {
4150         struct pool_entry *entry, *next_entry;
4151
4152         if (pool == NULL)
4153                 return;
4154
4155         for (entry = LIST_FIRST(&pool->alloc_list);
4156                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4157                         entry = next_entry) {
4158                 LIST_REMOVE(entry, next);
4159                 rte_free(entry);
4160         }
4161
4162         for (entry = LIST_FIRST(&pool->free_list);
4163                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4164                         entry = next_entry) {
4165                 LIST_REMOVE(entry, next);
4166                 rte_free(entry);
4167         }
4168
4169         pool->num_free = 0;
4170         pool->num_alloc = 0;
4171         pool->base = 0;
4172         LIST_INIT(&pool->alloc_list);
4173         LIST_INIT(&pool->free_list);
4174 }
4175
4176 static int
4177 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4178                        uint32_t base)
4179 {
4180         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4181         uint32_t pool_offset;
4182         int insert;
4183
4184         if (pool == NULL) {
4185                 PMD_DRV_LOG(ERR, "Invalid parameter");
4186                 return -EINVAL;
4187         }
4188
4189         pool_offset = base - pool->base;
4190         /* Lookup in alloc list */
4191         LIST_FOREACH(entry, &pool->alloc_list, next) {
4192                 if (entry->base == pool_offset) {
4193                         valid_entry = entry;
4194                         LIST_REMOVE(entry, next);
4195                         break;
4196                 }
4197         }
4198
4199         /* Not find, return */
4200         if (valid_entry == NULL) {
4201                 PMD_DRV_LOG(ERR, "Failed to find entry");
4202                 return -EINVAL;
4203         }
4204
4205         /**
4206          * Found it, move it to free list  and try to merge.
4207          * In order to make merge easier, always sort it by qbase.
4208          * Find adjacent prev and last entries.
4209          */
4210         prev = next = NULL;
4211         LIST_FOREACH(entry, &pool->free_list, next) {
4212                 if (entry->base > valid_entry->base) {
4213                         next = entry;
4214                         break;
4215                 }
4216                 prev = entry;
4217         }
4218
4219         insert = 0;
4220         /* Try to merge with next one*/
4221         if (next != NULL) {
4222                 /* Merge with next one */
4223                 if (valid_entry->base + valid_entry->len == next->base) {
4224                         next->base = valid_entry->base;
4225                         next->len += valid_entry->len;
4226                         rte_free(valid_entry);
4227                         valid_entry = next;
4228                         insert = 1;
4229                 }
4230         }
4231
4232         if (prev != NULL) {
4233                 /* Merge with previous one */
4234                 if (prev->base + prev->len == valid_entry->base) {
4235                         prev->len += valid_entry->len;
4236                         /* If it merge with next one, remove next node */
4237                         if (insert == 1) {
4238                                 LIST_REMOVE(valid_entry, next);
4239                                 rte_free(valid_entry);
4240                         } else {
4241                                 rte_free(valid_entry);
4242                                 insert = 1;
4243                         }
4244                 }
4245         }
4246
4247         /* Not find any entry to merge, insert */
4248         if (insert == 0) {
4249                 if (prev != NULL)
4250                         LIST_INSERT_AFTER(prev, valid_entry, next);
4251                 else if (next != NULL)
4252                         LIST_INSERT_BEFORE(next, valid_entry, next);
4253                 else /* It's empty list, insert to head */
4254                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4255         }
4256
4257         pool->num_free += valid_entry->len;
4258         pool->num_alloc -= valid_entry->len;
4259
4260         return 0;
4261 }
4262
4263 static int
4264 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4265                        uint16_t num)
4266 {
4267         struct pool_entry *entry, *valid_entry;
4268
4269         if (pool == NULL || num == 0) {
4270                 PMD_DRV_LOG(ERR, "Invalid parameter");
4271                 return -EINVAL;
4272         }
4273
4274         if (pool->num_free < num) {
4275                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4276                             num, pool->num_free);
4277                 return -ENOMEM;
4278         }
4279
4280         valid_entry = NULL;
4281         /* Lookup  in free list and find most fit one */
4282         LIST_FOREACH(entry, &pool->free_list, next) {
4283                 if (entry->len >= num) {
4284                         /* Find best one */
4285                         if (entry->len == num) {
4286                                 valid_entry = entry;
4287                                 break;
4288                         }
4289                         if (valid_entry == NULL || valid_entry->len > entry->len)
4290                                 valid_entry = entry;
4291                 }
4292         }
4293
4294         /* Not find one to satisfy the request, return */
4295         if (valid_entry == NULL) {
4296                 PMD_DRV_LOG(ERR, "No valid entry found");
4297                 return -ENOMEM;
4298         }
4299         /**
4300          * The entry have equal queue number as requested,
4301          * remove it from alloc_list.
4302          */
4303         if (valid_entry->len == num) {
4304                 LIST_REMOVE(valid_entry, next);
4305         } else {
4306                 /**
4307                  * The entry have more numbers than requested,
4308                  * create a new entry for alloc_list and minus its
4309                  * queue base and number in free_list.
4310                  */
4311                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4312                 if (entry == NULL) {
4313                         PMD_DRV_LOG(ERR,
4314                                 "Failed to allocate memory for resource pool");
4315                         return -ENOMEM;
4316                 }
4317                 entry->base = valid_entry->base;
4318                 entry->len = num;
4319                 valid_entry->base += num;
4320                 valid_entry->len -= num;
4321                 valid_entry = entry;
4322         }
4323
4324         /* Insert it into alloc list, not sorted */
4325         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4326
4327         pool->num_free -= valid_entry->len;
4328         pool->num_alloc += valid_entry->len;
4329
4330         return valid_entry->base + pool->base;
4331 }
4332
4333 /**
4334  * bitmap_is_subset - Check whether src2 is subset of src1
4335  **/
4336 static inline int
4337 bitmap_is_subset(uint8_t src1, uint8_t src2)
4338 {
4339         return !((src1 ^ src2) & src2);
4340 }
4341
4342 static enum i40e_status_code
4343 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4344 {
4345         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4346
4347         /* If DCB is not supported, only default TC is supported */
4348         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4349                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4350                 return I40E_NOT_SUPPORTED;
4351         }
4352
4353         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4354                 PMD_DRV_LOG(ERR,
4355                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4356                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4357                 return I40E_NOT_SUPPORTED;
4358         }
4359         return I40E_SUCCESS;
4360 }
4361
4362 int
4363 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4364                                 struct i40e_vsi_vlan_pvid_info *info)
4365 {
4366         struct i40e_hw *hw;
4367         struct i40e_vsi_context ctxt;
4368         uint8_t vlan_flags = 0;
4369         int ret;
4370
4371         if (vsi == NULL || info == NULL) {
4372                 PMD_DRV_LOG(ERR, "invalid parameters");
4373                 return I40E_ERR_PARAM;
4374         }
4375
4376         if (info->on) {
4377                 vsi->info.pvid = info->config.pvid;
4378                 /**
4379                  * If insert pvid is enabled, only tagged pkts are
4380                  * allowed to be sent out.
4381                  */
4382                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4383                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4384         } else {
4385                 vsi->info.pvid = 0;
4386                 if (info->config.reject.tagged == 0)
4387                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4388
4389                 if (info->config.reject.untagged == 0)
4390                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4391         }
4392         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4393                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4394         vsi->info.port_vlan_flags |= vlan_flags;
4395         vsi->info.valid_sections =
4396                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4397         memset(&ctxt, 0, sizeof(ctxt));
4398         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4399         ctxt.seid = vsi->seid;
4400
4401         hw = I40E_VSI_TO_HW(vsi);
4402         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4403         if (ret != I40E_SUCCESS)
4404                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4405
4406         return ret;
4407 }
4408
4409 static int
4410 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4411 {
4412         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4413         int i, ret;
4414         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4415
4416         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4417         if (ret != I40E_SUCCESS)
4418                 return ret;
4419
4420         if (!vsi->seid) {
4421                 PMD_DRV_LOG(ERR, "seid not valid");
4422                 return -EINVAL;
4423         }
4424
4425         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4426         tc_bw_data.tc_valid_bits = enabled_tcmap;
4427         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4428                 tc_bw_data.tc_bw_credits[i] =
4429                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4430
4431         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4432         if (ret != I40E_SUCCESS) {
4433                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4434                 return ret;
4435         }
4436
4437         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4438                                         sizeof(vsi->info.qs_handle));
4439         return I40E_SUCCESS;
4440 }
4441
4442 static enum i40e_status_code
4443 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4444                                  struct i40e_aqc_vsi_properties_data *info,
4445                                  uint8_t enabled_tcmap)
4446 {
4447         enum i40e_status_code ret;
4448         int i, total_tc = 0;
4449         uint16_t qpnum_per_tc, bsf, qp_idx;
4450
4451         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4452         if (ret != I40E_SUCCESS)
4453                 return ret;
4454
4455         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4456                 if (enabled_tcmap & (1 << i))
4457                         total_tc++;
4458         if (total_tc == 0)
4459                 total_tc = 1;
4460         vsi->enabled_tc = enabled_tcmap;
4461
4462         /* Number of queues per enabled TC */
4463         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4464         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4465         bsf = rte_bsf32(qpnum_per_tc);
4466
4467         /* Adjust the queue number to actual queues that can be applied */
4468         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4469                 vsi->nb_qps = qpnum_per_tc * total_tc;
4470
4471         /**
4472          * Configure TC and queue mapping parameters, for enabled TC,
4473          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4474          * default queue will serve it.
4475          */
4476         qp_idx = 0;
4477         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4478                 if (vsi->enabled_tc & (1 << i)) {
4479                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4480                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4481                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4482                         qp_idx += qpnum_per_tc;
4483                 } else
4484                         info->tc_mapping[i] = 0;
4485         }
4486
4487         /* Associate queue number with VSI */
4488         if (vsi->type == I40E_VSI_SRIOV) {
4489                 info->mapping_flags |=
4490                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4491                 for (i = 0; i < vsi->nb_qps; i++)
4492                         info->queue_mapping[i] =
4493                                 rte_cpu_to_le_16(vsi->base_queue + i);
4494         } else {
4495                 info->mapping_flags |=
4496                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4497                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4498         }
4499         info->valid_sections |=
4500                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4501
4502         return I40E_SUCCESS;
4503 }
4504
4505 static int
4506 i40e_veb_release(struct i40e_veb *veb)
4507 {
4508         struct i40e_vsi *vsi;
4509         struct i40e_hw *hw;
4510
4511         if (veb == NULL)
4512                 return -EINVAL;
4513
4514         if (!TAILQ_EMPTY(&veb->head)) {
4515                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4516                 return -EACCES;
4517         }
4518         /* associate_vsi field is NULL for floating VEB */
4519         if (veb->associate_vsi != NULL) {
4520                 vsi = veb->associate_vsi;
4521                 hw = I40E_VSI_TO_HW(vsi);
4522
4523                 vsi->uplink_seid = veb->uplink_seid;
4524                 vsi->veb = NULL;
4525         } else {
4526                 veb->associate_pf->main_vsi->floating_veb = NULL;
4527                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4528         }
4529
4530         i40e_aq_delete_element(hw, veb->seid, NULL);
4531         rte_free(veb);
4532         return I40E_SUCCESS;
4533 }
4534
4535 /* Setup a veb */
4536 static struct i40e_veb *
4537 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4538 {
4539         struct i40e_veb *veb;
4540         int ret;
4541         struct i40e_hw *hw;
4542
4543         if (pf == NULL) {
4544                 PMD_DRV_LOG(ERR,
4545                             "veb setup failed, associated PF shouldn't null");
4546                 return NULL;
4547         }
4548         hw = I40E_PF_TO_HW(pf);
4549
4550         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4551         if (!veb) {
4552                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4553                 goto fail;
4554         }
4555
4556         veb->associate_vsi = vsi;
4557         veb->associate_pf = pf;
4558         TAILQ_INIT(&veb->head);
4559         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4560
4561         /* create floating veb if vsi is NULL */
4562         if (vsi != NULL) {
4563                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4564                                       I40E_DEFAULT_TCMAP, false,
4565                                       &veb->seid, false, NULL);
4566         } else {
4567                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4568                                       true, &veb->seid, false, NULL);
4569         }
4570
4571         if (ret != I40E_SUCCESS) {
4572                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4573                             hw->aq.asq_last_status);
4574                 goto fail;
4575         }
4576         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4577
4578         /* get statistics index */
4579         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4580                                 &veb->stats_idx, NULL, NULL, NULL);
4581         if (ret != I40E_SUCCESS) {
4582                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4583                             hw->aq.asq_last_status);
4584                 goto fail;
4585         }
4586         /* Get VEB bandwidth, to be implemented */
4587         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4588         if (vsi)
4589                 vsi->uplink_seid = veb->seid;
4590
4591         return veb;
4592 fail:
4593         rte_free(veb);
4594         return NULL;
4595 }
4596
4597 int
4598 i40e_vsi_release(struct i40e_vsi *vsi)
4599 {
4600         struct i40e_pf *pf;
4601         struct i40e_hw *hw;
4602         struct i40e_vsi_list *vsi_list;
4603         void *temp;
4604         int ret;
4605         struct i40e_mac_filter *f;
4606         uint16_t user_param;
4607
4608         if (!vsi)
4609                 return I40E_SUCCESS;
4610
4611         if (!vsi->adapter)
4612                 return -EFAULT;
4613
4614         user_param = vsi->user_param;
4615
4616         pf = I40E_VSI_TO_PF(vsi);
4617         hw = I40E_VSI_TO_HW(vsi);
4618
4619         /* VSI has child to attach, release child first */
4620         if (vsi->veb) {
4621                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4622                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4623                                 return -1;
4624                 }
4625                 i40e_veb_release(vsi->veb);
4626         }
4627
4628         if (vsi->floating_veb) {
4629                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4630                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4631                                 return -1;
4632                 }
4633         }
4634
4635         /* Remove all macvlan filters of the VSI */
4636         i40e_vsi_remove_all_macvlan_filter(vsi);
4637         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4638                 rte_free(f);
4639
4640         if (vsi->type != I40E_VSI_MAIN &&
4641             ((vsi->type != I40E_VSI_SRIOV) ||
4642             !pf->floating_veb_list[user_param])) {
4643                 /* Remove vsi from parent's sibling list */
4644                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4645                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4646                         return I40E_ERR_PARAM;
4647                 }
4648                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4649                                 &vsi->sib_vsi_list, list);
4650
4651                 /* Remove all switch element of the VSI */
4652                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4653                 if (ret != I40E_SUCCESS)
4654                         PMD_DRV_LOG(ERR, "Failed to delete element");
4655         }
4656
4657         if ((vsi->type == I40E_VSI_SRIOV) &&
4658             pf->floating_veb_list[user_param]) {
4659                 /* Remove vsi from parent's sibling list */
4660                 if (vsi->parent_vsi == NULL ||
4661                     vsi->parent_vsi->floating_veb == NULL) {
4662                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4663                         return I40E_ERR_PARAM;
4664                 }
4665                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4666                              &vsi->sib_vsi_list, list);
4667
4668                 /* Remove all switch element of the VSI */
4669                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4670                 if (ret != I40E_SUCCESS)
4671                         PMD_DRV_LOG(ERR, "Failed to delete element");
4672         }
4673
4674         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4675
4676         if (vsi->type != I40E_VSI_SRIOV)
4677                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4678         rte_free(vsi);
4679
4680         return I40E_SUCCESS;
4681 }
4682
4683 static int
4684 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4685 {
4686         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4687         struct i40e_aqc_remove_macvlan_element_data def_filter;
4688         struct i40e_mac_filter_info filter;
4689         int ret;
4690
4691         if (vsi->type != I40E_VSI_MAIN)
4692                 return I40E_ERR_CONFIG;
4693         memset(&def_filter, 0, sizeof(def_filter));
4694         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4695                                         ETH_ADDR_LEN);
4696         def_filter.vlan_tag = 0;
4697         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4698                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4699         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4700         if (ret != I40E_SUCCESS) {
4701                 struct i40e_mac_filter *f;
4702                 struct ether_addr *mac;
4703
4704                 PMD_DRV_LOG(DEBUG,
4705                             "Cannot remove the default macvlan filter");
4706                 /* It needs to add the permanent mac into mac list */
4707                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4708                 if (f == NULL) {
4709                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4710                         return I40E_ERR_NO_MEMORY;
4711                 }
4712                 mac = &f->mac_info.mac_addr;
4713                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4714                                 ETH_ADDR_LEN);
4715                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4716                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4717                 vsi->mac_num++;
4718
4719                 return ret;
4720         }
4721         rte_memcpy(&filter.mac_addr,
4722                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4723         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4724         return i40e_vsi_add_mac(vsi, &filter);
4725 }
4726
4727 /*
4728  * i40e_vsi_get_bw_config - Query VSI BW Information
4729  * @vsi: the VSI to be queried
4730  *
4731  * Returns 0 on success, negative value on failure
4732  */
4733 static enum i40e_status_code
4734 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4735 {
4736         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4737         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4738         struct i40e_hw *hw = &vsi->adapter->hw;
4739         i40e_status ret;
4740         int i;
4741         uint32_t bw_max;
4742
4743         memset(&bw_config, 0, sizeof(bw_config));
4744         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4745         if (ret != I40E_SUCCESS) {
4746                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4747                             hw->aq.asq_last_status);
4748                 return ret;
4749         }
4750
4751         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4752         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4753                                         &ets_sla_config, NULL);
4754         if (ret != I40E_SUCCESS) {
4755                 PMD_DRV_LOG(ERR,
4756                         "VSI failed to get TC bandwdith configuration %u",
4757                         hw->aq.asq_last_status);
4758                 return ret;
4759         }
4760
4761         /* store and print out BW info */
4762         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4763         vsi->bw_info.bw_max = bw_config.max_bw;
4764         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4765         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4766         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4767                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4768                      I40E_16_BIT_WIDTH);
4769         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4770                 vsi->bw_info.bw_ets_share_credits[i] =
4771                                 ets_sla_config.share_credits[i];
4772                 vsi->bw_info.bw_ets_credits[i] =
4773                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4774                 /* 4 bits per TC, 4th bit is reserved */
4775                 vsi->bw_info.bw_ets_max[i] =
4776                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4777                                   RTE_LEN2MASK(3, uint8_t));
4778                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4779                             vsi->bw_info.bw_ets_share_credits[i]);
4780                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4781                             vsi->bw_info.bw_ets_credits[i]);
4782                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4783                             vsi->bw_info.bw_ets_max[i]);
4784         }
4785
4786         return I40E_SUCCESS;
4787 }
4788
4789 /* i40e_enable_pf_lb
4790  * @pf: pointer to the pf structure
4791  *
4792  * allow loopback on pf
4793  */
4794 static inline void
4795 i40e_enable_pf_lb(struct i40e_pf *pf)
4796 {
4797         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4798         struct i40e_vsi_context ctxt;
4799         int ret;
4800
4801         /* Use the FW API if FW >= v5.0 */
4802         if (hw->aq.fw_maj_ver < 5) {
4803                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4804                 return;
4805         }
4806
4807         memset(&ctxt, 0, sizeof(ctxt));
4808         ctxt.seid = pf->main_vsi_seid;
4809         ctxt.pf_num = hw->pf_id;
4810         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4811         if (ret) {
4812                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4813                             ret, hw->aq.asq_last_status);
4814                 return;
4815         }
4816         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4817         ctxt.info.valid_sections =
4818                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4819         ctxt.info.switch_id |=
4820                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4821
4822         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4823         if (ret)
4824                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4825                             hw->aq.asq_last_status);
4826 }
4827
4828 /* Setup a VSI */
4829 struct i40e_vsi *
4830 i40e_vsi_setup(struct i40e_pf *pf,
4831                enum i40e_vsi_type type,
4832                struct i40e_vsi *uplink_vsi,
4833                uint16_t user_param)
4834 {
4835         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4836         struct i40e_vsi *vsi;
4837         struct i40e_mac_filter_info filter;
4838         int ret;
4839         struct i40e_vsi_context ctxt;
4840         struct ether_addr broadcast =
4841                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4842
4843         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4844             uplink_vsi == NULL) {
4845                 PMD_DRV_LOG(ERR,
4846                         "VSI setup failed, VSI link shouldn't be NULL");
4847                 return NULL;
4848         }
4849
4850         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4851                 PMD_DRV_LOG(ERR,
4852                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4853                 return NULL;
4854         }
4855
4856         /* two situations
4857          * 1.type is not MAIN and uplink vsi is not NULL
4858          * If uplink vsi didn't setup VEB, create one first under veb field
4859          * 2.type is SRIOV and the uplink is NULL
4860          * If floating VEB is NULL, create one veb under floating veb field
4861          */
4862
4863         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4864             uplink_vsi->veb == NULL) {
4865                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4866
4867                 if (uplink_vsi->veb == NULL) {
4868                         PMD_DRV_LOG(ERR, "VEB setup failed");
4869                         return NULL;
4870                 }
4871                 /* set ALLOWLOOPBACk on pf, when veb is created */
4872                 i40e_enable_pf_lb(pf);
4873         }
4874
4875         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4876             pf->main_vsi->floating_veb == NULL) {
4877                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4878
4879                 if (pf->main_vsi->floating_veb == NULL) {
4880                         PMD_DRV_LOG(ERR, "VEB setup failed");
4881                         return NULL;
4882                 }
4883         }
4884
4885         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4886         if (!vsi) {
4887                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4888                 return NULL;
4889         }
4890         TAILQ_INIT(&vsi->mac_list);
4891         vsi->type = type;
4892         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4893         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4894         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4895         vsi->user_param = user_param;
4896         vsi->vlan_anti_spoof_on = 0;
4897         vsi->vlan_filter_on = 0;
4898         /* Allocate queues */
4899         switch (vsi->type) {
4900         case I40E_VSI_MAIN  :
4901                 vsi->nb_qps = pf->lan_nb_qps;
4902                 break;
4903         case I40E_VSI_SRIOV :
4904                 vsi->nb_qps = pf->vf_nb_qps;
4905                 break;
4906         case I40E_VSI_VMDQ2:
4907                 vsi->nb_qps = pf->vmdq_nb_qps;
4908                 break;
4909         case I40E_VSI_FDIR:
4910                 vsi->nb_qps = pf->fdir_nb_qps;
4911                 break;
4912         default:
4913                 goto fail_mem;
4914         }
4915         /*
4916          * The filter status descriptor is reported in rx queue 0,
4917          * while the tx queue for fdir filter programming has no
4918          * such constraints, can be non-zero queues.
4919          * To simplify it, choose FDIR vsi use queue 0 pair.
4920          * To make sure it will use queue 0 pair, queue allocation
4921          * need be done before this function is called
4922          */
4923         if (type != I40E_VSI_FDIR) {
4924                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4925                         if (ret < 0) {
4926                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4927                                                 vsi->seid, ret);
4928                                 goto fail_mem;
4929                         }
4930                         vsi->base_queue = ret;
4931         } else
4932                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4933
4934         /* VF has MSIX interrupt in VF range, don't allocate here */
4935         if (type == I40E_VSI_MAIN) {
4936                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4937                                           RTE_MIN(vsi->nb_qps,
4938                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4939                 if (ret < 0) {
4940                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4941                                     vsi->seid, ret);
4942                         goto fail_queue_alloc;
4943                 }
4944                 vsi->msix_intr = ret;
4945                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4946         } else if (type != I40E_VSI_SRIOV) {
4947                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4948                 if (ret < 0) {
4949                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4950                         goto fail_queue_alloc;
4951                 }
4952                 vsi->msix_intr = ret;
4953                 vsi->nb_msix = 1;
4954         } else {
4955                 vsi->msix_intr = 0;
4956                 vsi->nb_msix = 0;
4957         }
4958
4959         /* Add VSI */
4960         if (type == I40E_VSI_MAIN) {
4961                 /* For main VSI, no need to add since it's default one */
4962                 vsi->uplink_seid = pf->mac_seid;
4963                 vsi->seid = pf->main_vsi_seid;
4964                 /* Bind queues with specific MSIX interrupt */
4965                 /**
4966                  * Needs 2 interrupt at least, one for misc cause which will
4967                  * enabled from OS side, Another for queues binding the
4968                  * interrupt from device side only.
4969                  */
4970
4971                 /* Get default VSI parameters from hardware */
4972                 memset(&ctxt, 0, sizeof(ctxt));
4973                 ctxt.seid = vsi->seid;
4974                 ctxt.pf_num = hw->pf_id;
4975                 ctxt.uplink_seid = vsi->uplink_seid;
4976                 ctxt.vf_num = 0;
4977                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4978                 if (ret != I40E_SUCCESS) {
4979                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4980                         goto fail_msix_alloc;
4981                 }
4982                 rte_memcpy(&vsi->info, &ctxt.info,
4983                         sizeof(struct i40e_aqc_vsi_properties_data));
4984                 vsi->vsi_id = ctxt.vsi_number;
4985                 vsi->info.valid_sections = 0;
4986
4987                 /* Configure tc, enabled TC0 only */
4988                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4989                         I40E_SUCCESS) {
4990                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4991                         goto fail_msix_alloc;
4992                 }
4993
4994                 /* TC, queue mapping */
4995                 memset(&ctxt, 0, sizeof(ctxt));
4996                 vsi->info.valid_sections |=
4997                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4998                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4999                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5000                 rte_memcpy(&ctxt.info, &vsi->info,
5001                         sizeof(struct i40e_aqc_vsi_properties_data));
5002                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5003                                                 I40E_DEFAULT_TCMAP);
5004                 if (ret != I40E_SUCCESS) {
5005                         PMD_DRV_LOG(ERR,
5006                                 "Failed to configure TC queue mapping");
5007                         goto fail_msix_alloc;
5008                 }
5009                 ctxt.seid = vsi->seid;
5010                 ctxt.pf_num = hw->pf_id;
5011                 ctxt.uplink_seid = vsi->uplink_seid;
5012                 ctxt.vf_num = 0;
5013
5014                 /* Update VSI parameters */
5015                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5016                 if (ret != I40E_SUCCESS) {
5017                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5018                         goto fail_msix_alloc;
5019                 }
5020
5021                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5022                                                 sizeof(vsi->info.tc_mapping));
5023                 rte_memcpy(&vsi->info.queue_mapping,
5024                                 &ctxt.info.queue_mapping,
5025                         sizeof(vsi->info.queue_mapping));
5026                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5027                 vsi->info.valid_sections = 0;
5028
5029                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5030                                 ETH_ADDR_LEN);
5031
5032                 /**
5033                  * Updating default filter settings are necessary to prevent
5034                  * reception of tagged packets.
5035                  * Some old firmware configurations load a default macvlan
5036                  * filter which accepts both tagged and untagged packets.
5037                  * The updating is to use a normal filter instead if needed.
5038                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5039                  * The firmware with correct configurations load the default
5040                  * macvlan filter which is expected and cannot be removed.
5041                  */
5042                 i40e_update_default_filter_setting(vsi);
5043                 i40e_config_qinq(hw, vsi);
5044         } else if (type == I40E_VSI_SRIOV) {
5045                 memset(&ctxt, 0, sizeof(ctxt));
5046                 /**
5047                  * For other VSI, the uplink_seid equals to uplink VSI's
5048                  * uplink_seid since they share same VEB
5049                  */
5050                 if (uplink_vsi == NULL)
5051                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5052                 else
5053                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5054                 ctxt.pf_num = hw->pf_id;
5055                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5056                 ctxt.uplink_seid = vsi->uplink_seid;
5057                 ctxt.connection_type = 0x1;
5058                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5059
5060                 /* Use the VEB configuration if FW >= v5.0 */
5061                 if (hw->aq.fw_maj_ver >= 5) {
5062                         /* Configure switch ID */
5063                         ctxt.info.valid_sections |=
5064                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5065                         ctxt.info.switch_id =
5066                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5067                 }
5068
5069                 /* Configure port/vlan */
5070                 ctxt.info.valid_sections |=
5071                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5072                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5073                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5074                                                 hw->func_caps.enabled_tcmap);
5075                 if (ret != I40E_SUCCESS) {
5076                         PMD_DRV_LOG(ERR,
5077                                 "Failed to configure TC queue mapping");
5078                         goto fail_msix_alloc;
5079                 }
5080
5081                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5082                 ctxt.info.valid_sections |=
5083                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5084                 /**
5085                  * Since VSI is not created yet, only configure parameter,
5086                  * will add vsi below.
5087                  */
5088
5089                 i40e_config_qinq(hw, vsi);
5090         } else if (type == I40E_VSI_VMDQ2) {
5091                 memset(&ctxt, 0, sizeof(ctxt));
5092                 /*
5093                  * For other VSI, the uplink_seid equals to uplink VSI's
5094                  * uplink_seid since they share same VEB
5095                  */
5096                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5097                 ctxt.pf_num = hw->pf_id;
5098                 ctxt.vf_num = 0;
5099                 ctxt.uplink_seid = vsi->uplink_seid;
5100                 ctxt.connection_type = 0x1;
5101                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5102
5103                 ctxt.info.valid_sections |=
5104                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5105                 /* user_param carries flag to enable loop back */
5106                 if (user_param) {
5107                         ctxt.info.switch_id =
5108                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5109                         ctxt.info.switch_id |=
5110                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5111                 }
5112
5113                 /* Configure port/vlan */
5114                 ctxt.info.valid_sections |=
5115                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5116                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5117                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5118                                                 I40E_DEFAULT_TCMAP);
5119                 if (ret != I40E_SUCCESS) {
5120                         PMD_DRV_LOG(ERR,
5121                                 "Failed to configure TC queue mapping");
5122                         goto fail_msix_alloc;
5123                 }
5124                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5125                 ctxt.info.valid_sections |=
5126                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5127         } else if (type == I40E_VSI_FDIR) {
5128                 memset(&ctxt, 0, sizeof(ctxt));
5129                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5130                 ctxt.pf_num = hw->pf_id;
5131                 ctxt.vf_num = 0;
5132                 ctxt.uplink_seid = vsi->uplink_seid;
5133                 ctxt.connection_type = 0x1;     /* regular data port */
5134                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5135                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5136                                                 I40E_DEFAULT_TCMAP);
5137                 if (ret != I40E_SUCCESS) {
5138                         PMD_DRV_LOG(ERR,
5139                                 "Failed to configure TC queue mapping.");
5140                         goto fail_msix_alloc;
5141                 }
5142                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5143                 ctxt.info.valid_sections |=
5144                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5145         } else {
5146                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5147                 goto fail_msix_alloc;
5148         }
5149
5150         if (vsi->type != I40E_VSI_MAIN) {
5151                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5152                 if (ret != I40E_SUCCESS) {
5153                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5154                                     hw->aq.asq_last_status);
5155                         goto fail_msix_alloc;
5156                 }
5157                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5158                 vsi->info.valid_sections = 0;
5159                 vsi->seid = ctxt.seid;
5160                 vsi->vsi_id = ctxt.vsi_number;
5161                 vsi->sib_vsi_list.vsi = vsi;
5162                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5163                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5164                                           &vsi->sib_vsi_list, list);
5165                 } else {
5166                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5167                                           &vsi->sib_vsi_list, list);
5168                 }
5169         }
5170
5171         /* MAC/VLAN configuration */
5172         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5173         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5174
5175         ret = i40e_vsi_add_mac(vsi, &filter);
5176         if (ret != I40E_SUCCESS) {
5177                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5178                 goto fail_msix_alloc;
5179         }
5180
5181         /* Get VSI BW information */
5182         i40e_vsi_get_bw_config(vsi);
5183         return vsi;
5184 fail_msix_alloc:
5185         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5186 fail_queue_alloc:
5187         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5188 fail_mem:
5189         rte_free(vsi);
5190         return NULL;
5191 }
5192
5193 /* Configure vlan filter on or off */
5194 int
5195 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5196 {
5197         int i, num;
5198         struct i40e_mac_filter *f;
5199         void *temp;
5200         struct i40e_mac_filter_info *mac_filter;
5201         enum rte_mac_filter_type desired_filter;
5202         int ret = I40E_SUCCESS;
5203
5204         if (on) {
5205                 /* Filter to match MAC and VLAN */
5206                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5207         } else {
5208                 /* Filter to match only MAC */
5209                 desired_filter = RTE_MAC_PERFECT_MATCH;
5210         }
5211
5212         num = vsi->mac_num;
5213
5214         mac_filter = rte_zmalloc("mac_filter_info_data",
5215                                  num * sizeof(*mac_filter), 0);
5216         if (mac_filter == NULL) {
5217                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5218                 return I40E_ERR_NO_MEMORY;
5219         }
5220
5221         i = 0;
5222
5223         /* Remove all existing mac */
5224         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5225                 mac_filter[i] = f->mac_info;
5226                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5227                 if (ret) {
5228                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5229                                     on ? "enable" : "disable");
5230                         goto DONE;
5231                 }
5232                 i++;
5233         }
5234
5235         /* Override with new filter */
5236         for (i = 0; i < num; i++) {
5237                 mac_filter[i].filter_type = desired_filter;
5238                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5239                 if (ret) {
5240                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5241                                     on ? "enable" : "disable");
5242                         goto DONE;
5243                 }
5244         }
5245
5246 DONE:
5247         rte_free(mac_filter);
5248         return ret;
5249 }
5250
5251 /* Configure vlan stripping on or off */
5252 int
5253 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5254 {
5255         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5256         struct i40e_vsi_context ctxt;
5257         uint8_t vlan_flags;
5258         int ret = I40E_SUCCESS;
5259
5260         /* Check if it has been already on or off */
5261         if (vsi->info.valid_sections &
5262                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5263                 if (on) {
5264                         if ((vsi->info.port_vlan_flags &
5265                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5266                                 return 0; /* already on */
5267                 } else {
5268                         if ((vsi->info.port_vlan_flags &
5269                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5270                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5271                                 return 0; /* already off */
5272                 }
5273         }
5274
5275         if (on)
5276                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5277         else
5278                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5279         vsi->info.valid_sections =
5280                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5281         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5282         vsi->info.port_vlan_flags |= vlan_flags;
5283         ctxt.seid = vsi->seid;
5284         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5285         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5286         if (ret)
5287                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5288                             on ? "enable" : "disable");
5289
5290         return ret;
5291 }
5292
5293 static int
5294 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5295 {
5296         struct rte_eth_dev_data *data = dev->data;
5297         int ret;
5298         int mask = 0;
5299
5300         /* Apply vlan offload setting */
5301         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5302         i40e_vlan_offload_set(dev, mask);
5303
5304         /* Apply double-vlan setting, not implemented yet */
5305
5306         /* Apply pvid setting */
5307         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5308                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5309         if (ret)
5310                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5311
5312         return ret;
5313 }
5314
5315 static int
5316 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5317 {
5318         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5319
5320         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5321 }
5322
5323 static int
5324 i40e_update_flow_control(struct i40e_hw *hw)
5325 {
5326 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5327         struct i40e_link_status link_status;
5328         uint32_t rxfc = 0, txfc = 0, reg;
5329         uint8_t an_info;
5330         int ret;
5331
5332         memset(&link_status, 0, sizeof(link_status));
5333         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5334         if (ret != I40E_SUCCESS) {
5335                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5336                 goto write_reg; /* Disable flow control */
5337         }
5338
5339         an_info = hw->phy.link_info.an_info;
5340         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5341                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5342                 ret = I40E_ERR_NOT_READY;
5343                 goto write_reg; /* Disable flow control */
5344         }
5345         /**
5346          * If link auto negotiation is enabled, flow control needs to
5347          * be configured according to it
5348          */
5349         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5350         case I40E_LINK_PAUSE_RXTX:
5351                 rxfc = 1;
5352                 txfc = 1;
5353                 hw->fc.current_mode = I40E_FC_FULL;
5354                 break;
5355         case I40E_AQ_LINK_PAUSE_RX:
5356                 rxfc = 1;
5357                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5358                 break;
5359         case I40E_AQ_LINK_PAUSE_TX:
5360                 txfc = 1;
5361                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5362                 break;
5363         default:
5364                 hw->fc.current_mode = I40E_FC_NONE;
5365                 break;
5366         }
5367
5368 write_reg:
5369         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5370                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5371         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5372         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5373         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5374         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5375
5376         return ret;
5377 }
5378
5379 /* PF setup */
5380 static int
5381 i40e_pf_setup(struct i40e_pf *pf)
5382 {
5383         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5384         struct i40e_filter_control_settings settings;
5385         struct i40e_vsi *vsi;
5386         int ret;
5387
5388         /* Clear all stats counters */
5389         pf->offset_loaded = FALSE;
5390         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5391         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5392         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5393         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5394
5395         ret = i40e_pf_get_switch_config(pf);
5396         if (ret != I40E_SUCCESS) {
5397                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5398                 return ret;
5399         }
5400         if (pf->flags & I40E_FLAG_FDIR) {
5401                 /* make queue allocated first, let FDIR use queue pair 0*/
5402                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5403                 if (ret != I40E_FDIR_QUEUE_ID) {
5404                         PMD_DRV_LOG(ERR,
5405                                 "queue allocation fails for FDIR: ret =%d",
5406                                 ret);
5407                         pf->flags &= ~I40E_FLAG_FDIR;
5408                 }
5409         }
5410         /*  main VSI setup */
5411         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5412         if (!vsi) {
5413                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5414                 return I40E_ERR_NOT_READY;
5415         }
5416         pf->main_vsi = vsi;
5417
5418         /* Configure filter control */
5419         memset(&settings, 0, sizeof(settings));
5420         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5421                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5422         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5423                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5424         else {
5425                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5426                         hw->func_caps.rss_table_size);
5427                 return I40E_ERR_PARAM;
5428         }
5429         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5430                 hw->func_caps.rss_table_size);
5431         pf->hash_lut_size = hw->func_caps.rss_table_size;
5432
5433         /* Enable ethtype and macvlan filters */
5434         settings.enable_ethtype = TRUE;
5435         settings.enable_macvlan = TRUE;
5436         ret = i40e_set_filter_control(hw, &settings);
5437         if (ret)
5438                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5439                                                                 ret);
5440
5441         /* Update flow control according to the auto negotiation */
5442         i40e_update_flow_control(hw);
5443
5444         return I40E_SUCCESS;
5445 }
5446
5447 int
5448 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5449 {
5450         uint32_t reg;
5451         uint16_t j;
5452
5453         /**
5454          * Set or clear TX Queue Disable flags,
5455          * which is required by hardware.
5456          */
5457         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5458         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5459
5460         /* Wait until the request is finished */
5461         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5462                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5463                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5464                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5465                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5466                                                         & 0x1))) {
5467                         break;
5468                 }
5469         }
5470         if (on) {
5471                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5472                         return I40E_SUCCESS; /* already on, skip next steps */
5473
5474                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5475                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5476         } else {
5477                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5478                         return I40E_SUCCESS; /* already off, skip next steps */
5479                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5480         }
5481         /* Write the register */
5482         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5483         /* Check the result */
5484         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5485                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5486                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5487                 if (on) {
5488                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5489                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5490                                 break;
5491                 } else {
5492                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5493                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5494                                 break;
5495                 }
5496         }
5497         /* Check if it is timeout */
5498         if (j >= I40E_CHK_Q_ENA_COUNT) {
5499                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5500                             (on ? "enable" : "disable"), q_idx);
5501                 return I40E_ERR_TIMEOUT;
5502         }
5503
5504         return I40E_SUCCESS;
5505 }
5506
5507 /* Swith on or off the tx queues */
5508 static int
5509 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5510 {
5511         struct rte_eth_dev_data *dev_data = pf->dev_data;
5512         struct i40e_tx_queue *txq;
5513         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5514         uint16_t i;
5515         int ret;
5516
5517         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5518                 txq = dev_data->tx_queues[i];
5519                 /* Don't operate the queue if not configured or
5520                  * if starting only per queue */
5521                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5522                         continue;
5523                 if (on)
5524                         ret = i40e_dev_tx_queue_start(dev, i);
5525                 else
5526                         ret = i40e_dev_tx_queue_stop(dev, i);
5527                 if ( ret != I40E_SUCCESS)
5528                         return ret;
5529         }
5530
5531         return I40E_SUCCESS;
5532 }
5533
5534 int
5535 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5536 {
5537         uint32_t reg;
5538         uint16_t j;
5539
5540         /* Wait until the request is finished */
5541         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5542                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5543                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5544                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5545                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5546                         break;
5547         }
5548
5549         if (on) {
5550                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5551                         return I40E_SUCCESS; /* Already on, skip next steps */
5552                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5553         } else {
5554                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5555                         return I40E_SUCCESS; /* Already off, skip next steps */
5556                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5557         }
5558
5559         /* Write the register */
5560         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5561         /* Check the result */
5562         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5563                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5564                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5565                 if (on) {
5566                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5567                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5568                                 break;
5569                 } else {
5570                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5571                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5572                                 break;
5573                 }
5574         }
5575
5576         /* Check if it is timeout */
5577         if (j >= I40E_CHK_Q_ENA_COUNT) {
5578                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5579                             (on ? "enable" : "disable"), q_idx);
5580                 return I40E_ERR_TIMEOUT;
5581         }
5582
5583         return I40E_SUCCESS;
5584 }
5585 /* Switch on or off the rx queues */
5586 static int
5587 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5588 {
5589         struct rte_eth_dev_data *dev_data = pf->dev_data;
5590         struct i40e_rx_queue *rxq;
5591         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5592         uint16_t i;
5593         int ret;
5594
5595         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5596                 rxq = dev_data->rx_queues[i];
5597                 /* Don't operate the queue if not configured or
5598                  * if starting only per queue */
5599                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5600                         continue;
5601                 if (on)
5602                         ret = i40e_dev_rx_queue_start(dev, i);
5603                 else
5604                         ret = i40e_dev_rx_queue_stop(dev, i);
5605                 if (ret != I40E_SUCCESS)
5606                         return ret;
5607         }
5608
5609         return I40E_SUCCESS;
5610 }
5611
5612 /* Switch on or off all the rx/tx queues */
5613 int
5614 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5615 {
5616         int ret;
5617
5618         if (on) {
5619                 /* enable rx queues before enabling tx queues */
5620                 ret = i40e_dev_switch_rx_queues(pf, on);
5621                 if (ret) {
5622                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5623                         return ret;
5624                 }
5625                 ret = i40e_dev_switch_tx_queues(pf, on);
5626         } else {
5627                 /* Stop tx queues before stopping rx queues */
5628                 ret = i40e_dev_switch_tx_queues(pf, on);
5629                 if (ret) {
5630                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5631                         return ret;
5632                 }
5633                 ret = i40e_dev_switch_rx_queues(pf, on);
5634         }
5635
5636         return ret;
5637 }
5638
5639 /* Initialize VSI for TX */
5640 static int
5641 i40e_dev_tx_init(struct i40e_pf *pf)
5642 {
5643         struct rte_eth_dev_data *data = pf->dev_data;
5644         uint16_t i;
5645         uint32_t ret = I40E_SUCCESS;
5646         struct i40e_tx_queue *txq;
5647
5648         for (i = 0; i < data->nb_tx_queues; i++) {
5649                 txq = data->tx_queues[i];
5650                 if (!txq || !txq->q_set)
5651                         continue;
5652                 ret = i40e_tx_queue_init(txq);
5653                 if (ret != I40E_SUCCESS)
5654                         break;
5655         }
5656         if (ret == I40E_SUCCESS)
5657                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5658                                      ->eth_dev);
5659
5660         return ret;
5661 }
5662
5663 /* Initialize VSI for RX */
5664 static int
5665 i40e_dev_rx_init(struct i40e_pf *pf)
5666 {
5667         struct rte_eth_dev_data *data = pf->dev_data;
5668         int ret = I40E_SUCCESS;
5669         uint16_t i;
5670         struct i40e_rx_queue *rxq;
5671
5672         i40e_pf_config_mq_rx(pf);
5673         for (i = 0; i < data->nb_rx_queues; i++) {
5674                 rxq = data->rx_queues[i];
5675                 if (!rxq || !rxq->q_set)
5676                         continue;
5677
5678                 ret = i40e_rx_queue_init(rxq);
5679                 if (ret != I40E_SUCCESS) {
5680                         PMD_DRV_LOG(ERR,
5681                                 "Failed to do RX queue initialization");
5682                         break;
5683                 }
5684         }
5685         if (ret == I40E_SUCCESS)
5686                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5687                                      ->eth_dev);
5688
5689         return ret;
5690 }
5691
5692 static int
5693 i40e_dev_rxtx_init(struct i40e_pf *pf)
5694 {
5695         int err;
5696
5697         err = i40e_dev_tx_init(pf);
5698         if (err) {
5699                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5700                 return err;
5701         }
5702         err = i40e_dev_rx_init(pf);
5703         if (err) {
5704                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5705                 return err;
5706         }
5707
5708         return err;
5709 }
5710
5711 static int
5712 i40e_vmdq_setup(struct rte_eth_dev *dev)
5713 {
5714         struct rte_eth_conf *conf = &dev->data->dev_conf;
5715         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5716         int i, err, conf_vsis, j, loop;
5717         struct i40e_vsi *vsi;
5718         struct i40e_vmdq_info *vmdq_info;
5719         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5720         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5721
5722         /*
5723          * Disable interrupt to avoid message from VF. Furthermore, it will
5724          * avoid race condition in VSI creation/destroy.
5725          */
5726         i40e_pf_disable_irq0(hw);
5727
5728         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5729                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5730                 return -ENOTSUP;
5731         }
5732
5733         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5734         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5735                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5736                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5737                         pf->max_nb_vmdq_vsi);
5738                 return -ENOTSUP;
5739         }
5740
5741         if (pf->vmdq != NULL) {
5742                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5743                 return 0;
5744         }
5745
5746         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5747                                 sizeof(*vmdq_info) * conf_vsis, 0);
5748
5749         if (pf->vmdq == NULL) {
5750                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5751                 return -ENOMEM;
5752         }
5753
5754         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5755
5756         /* Create VMDQ VSI */
5757         for (i = 0; i < conf_vsis; i++) {
5758                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5759                                 vmdq_conf->enable_loop_back);
5760                 if (vsi == NULL) {
5761                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5762                         err = -1;
5763                         goto err_vsi_setup;
5764                 }
5765                 vmdq_info = &pf->vmdq[i];
5766                 vmdq_info->pf = pf;
5767                 vmdq_info->vsi = vsi;
5768         }
5769         pf->nb_cfg_vmdq_vsi = conf_vsis;
5770
5771         /* Configure Vlan */
5772         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5773         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5774                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5775                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5776                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5777                                         vmdq_conf->pool_map[i].vlan_id, j);
5778
5779                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5780                                                 vmdq_conf->pool_map[i].vlan_id);
5781                                 if (err) {
5782                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5783                                         err = -1;
5784                                         goto err_vsi_setup;
5785                                 }
5786                         }
5787                 }
5788         }
5789
5790         i40e_pf_enable_irq0(hw);
5791
5792         return 0;
5793
5794 err_vsi_setup:
5795         for (i = 0; i < conf_vsis; i++)
5796                 if (pf->vmdq[i].vsi == NULL)
5797                         break;
5798                 else
5799                         i40e_vsi_release(pf->vmdq[i].vsi);
5800
5801         rte_free(pf->vmdq);
5802         pf->vmdq = NULL;
5803         i40e_pf_enable_irq0(hw);
5804         return err;
5805 }
5806
5807 static void
5808 i40e_stat_update_32(struct i40e_hw *hw,
5809                    uint32_t reg,
5810                    bool offset_loaded,
5811                    uint64_t *offset,
5812                    uint64_t *stat)
5813 {
5814         uint64_t new_data;
5815
5816         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5817         if (!offset_loaded)
5818                 *offset = new_data;
5819
5820         if (new_data >= *offset)
5821                 *stat = (uint64_t)(new_data - *offset);
5822         else
5823                 *stat = (uint64_t)((new_data +
5824                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5825 }
5826
5827 static void
5828 i40e_stat_update_48(struct i40e_hw *hw,
5829                    uint32_t hireg,
5830                    uint32_t loreg,
5831                    bool offset_loaded,
5832                    uint64_t *offset,
5833                    uint64_t *stat)
5834 {
5835         uint64_t new_data;
5836
5837         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5838         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5839                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5840
5841         if (!offset_loaded)
5842                 *offset = new_data;
5843
5844         if (new_data >= *offset)
5845                 *stat = new_data - *offset;
5846         else
5847                 *stat = (uint64_t)((new_data +
5848                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5849
5850         *stat &= I40E_48_BIT_MASK;
5851 }
5852
5853 /* Disable IRQ0 */
5854 void
5855 i40e_pf_disable_irq0(struct i40e_hw *hw)
5856 {
5857         /* Disable all interrupt types */
5858         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5859         I40E_WRITE_FLUSH(hw);
5860 }
5861
5862 /* Enable IRQ0 */
5863 void
5864 i40e_pf_enable_irq0(struct i40e_hw *hw)
5865 {
5866         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5867                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5868                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5869                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5870         I40E_WRITE_FLUSH(hw);
5871 }
5872
5873 static void
5874 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5875 {
5876         /* read pending request and disable first */
5877         i40e_pf_disable_irq0(hw);
5878         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5879         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5880                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5881
5882         if (no_queue)
5883                 /* Link no queues with irq0 */
5884                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5885                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5886 }
5887
5888 static void
5889 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5890 {
5891         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5892         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5893         int i;
5894         uint16_t abs_vf_id;
5895         uint32_t index, offset, val;
5896
5897         if (!pf->vfs)
5898                 return;
5899         /**
5900          * Try to find which VF trigger a reset, use absolute VF id to access
5901          * since the reg is global register.
5902          */
5903         for (i = 0; i < pf->vf_num; i++) {
5904                 abs_vf_id = hw->func_caps.vf_base_id + i;
5905                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5906                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5907                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5908                 /* VFR event occurred */
5909                 if (val & (0x1 << offset)) {
5910                         int ret;
5911
5912                         /* Clear the event first */
5913                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5914                                                         (0x1 << offset));
5915                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5916                         /**
5917                          * Only notify a VF reset event occurred,
5918                          * don't trigger another SW reset
5919                          */
5920                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5921                         if (ret != I40E_SUCCESS)
5922                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5923                 }
5924         }
5925 }
5926
5927 static void
5928 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5929 {
5930         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5931         int i;
5932
5933         for (i = 0; i < pf->vf_num; i++)
5934                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5935 }
5936
5937 static void
5938 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5939 {
5940         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5941         struct i40e_arq_event_info info;
5942         uint16_t pending, opcode;
5943         int ret;
5944
5945         info.buf_len = I40E_AQ_BUF_SZ;
5946         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5947         if (!info.msg_buf) {
5948                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5949                 return;
5950         }
5951
5952         pending = 1;
5953         while (pending) {
5954                 ret = i40e_clean_arq_element(hw, &info, &pending);
5955
5956                 if (ret != I40E_SUCCESS) {
5957                         PMD_DRV_LOG(INFO,
5958                                 "Failed to read msg from AdminQ, aq_err: %u",
5959                                 hw->aq.asq_last_status);
5960                         break;
5961                 }
5962                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5963
5964                 switch (opcode) {
5965                 case i40e_aqc_opc_send_msg_to_pf:
5966                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5967                         i40e_pf_host_handle_vf_msg(dev,
5968                                         rte_le_to_cpu_16(info.desc.retval),
5969                                         rte_le_to_cpu_32(info.desc.cookie_high),
5970                                         rte_le_to_cpu_32(info.desc.cookie_low),
5971                                         info.msg_buf,
5972                                         info.msg_len);
5973                         break;
5974                 case i40e_aqc_opc_get_link_status:
5975                         ret = i40e_dev_link_update(dev, 0);
5976                         if (!ret)
5977                                 _rte_eth_dev_callback_process(dev,
5978                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5979                         break;
5980                 default:
5981                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5982                                     opcode);
5983                         break;
5984                 }
5985         }
5986         rte_free(info.msg_buf);
5987 }
5988
5989 /**
5990  * Interrupt handler triggered by NIC  for handling
5991  * specific interrupt.
5992  *
5993  * @param handle
5994  *  Pointer to interrupt handle.
5995  * @param param
5996  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5997  *
5998  * @return
5999  *  void
6000  */
6001 static void
6002 i40e_dev_interrupt_handler(void *param)
6003 {
6004         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6005         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6006         uint32_t icr0;
6007
6008         /* Disable interrupt */
6009         i40e_pf_disable_irq0(hw);
6010
6011         /* read out interrupt causes */
6012         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6013
6014         /* No interrupt event indicated */
6015         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6016                 PMD_DRV_LOG(INFO, "No interrupt event");
6017                 goto done;
6018         }
6019         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6020                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6021         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6022                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6023         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6024                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6025         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6026                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6027         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6028                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6029         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6030                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6031         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6032                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6033
6034         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6035                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6036                 i40e_dev_handle_vfr_event(dev);
6037         }
6038         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6039                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6040                 i40e_dev_handle_aq_msg(dev);
6041         }
6042
6043 done:
6044         /* Enable interrupt */
6045         i40e_pf_enable_irq0(hw);
6046         rte_intr_enable(dev->intr_handle);
6047 }
6048
6049 int
6050 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6051                          struct i40e_macvlan_filter *filter,
6052                          int total)
6053 {
6054         int ele_num, ele_buff_size;
6055         int num, actual_num, i;
6056         uint16_t flags;
6057         int ret = I40E_SUCCESS;
6058         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6059         struct i40e_aqc_add_macvlan_element_data *req_list;
6060
6061         if (filter == NULL  || total == 0)
6062                 return I40E_ERR_PARAM;
6063         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6064         ele_buff_size = hw->aq.asq_buf_size;
6065
6066         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6067         if (req_list == NULL) {
6068                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6069                 return I40E_ERR_NO_MEMORY;
6070         }
6071
6072         num = 0;
6073         do {
6074                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6075                 memset(req_list, 0, ele_buff_size);
6076
6077                 for (i = 0; i < actual_num; i++) {
6078                         rte_memcpy(req_list[i].mac_addr,
6079                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6080                         req_list[i].vlan_tag =
6081                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6082
6083                         switch (filter[num + i].filter_type) {
6084                         case RTE_MAC_PERFECT_MATCH:
6085                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6086                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6087                                 break;
6088                         case RTE_MACVLAN_PERFECT_MATCH:
6089                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6090                                 break;
6091                         case RTE_MAC_HASH_MATCH:
6092                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6093                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6094                                 break;
6095                         case RTE_MACVLAN_HASH_MATCH:
6096                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6097                                 break;
6098                         default:
6099                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6100                                 ret = I40E_ERR_PARAM;
6101                                 goto DONE;
6102                         }
6103
6104                         req_list[i].queue_number = 0;
6105
6106                         req_list[i].flags = rte_cpu_to_le_16(flags);
6107                 }
6108
6109                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6110                                                 actual_num, NULL);
6111                 if (ret != I40E_SUCCESS) {
6112                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6113                         goto DONE;
6114                 }
6115                 num += actual_num;
6116         } while (num < total);
6117
6118 DONE:
6119         rte_free(req_list);
6120         return ret;
6121 }
6122
6123 int
6124 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6125                             struct i40e_macvlan_filter *filter,
6126                             int total)
6127 {
6128         int ele_num, ele_buff_size;
6129         int num, actual_num, i;
6130         uint16_t flags;
6131         int ret = I40E_SUCCESS;
6132         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6133         struct i40e_aqc_remove_macvlan_element_data *req_list;
6134
6135         if (filter == NULL  || total == 0)
6136                 return I40E_ERR_PARAM;
6137
6138         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6139         ele_buff_size = hw->aq.asq_buf_size;
6140
6141         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6142         if (req_list == NULL) {
6143                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6144                 return I40E_ERR_NO_MEMORY;
6145         }
6146
6147         num = 0;
6148         do {
6149                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6150                 memset(req_list, 0, ele_buff_size);
6151
6152                 for (i = 0; i < actual_num; i++) {
6153                         rte_memcpy(req_list[i].mac_addr,
6154                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6155                         req_list[i].vlan_tag =
6156                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6157
6158                         switch (filter[num + i].filter_type) {
6159                         case RTE_MAC_PERFECT_MATCH:
6160                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6161                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6162                                 break;
6163                         case RTE_MACVLAN_PERFECT_MATCH:
6164                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6165                                 break;
6166                         case RTE_MAC_HASH_MATCH:
6167                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6168                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6169                                 break;
6170                         case RTE_MACVLAN_HASH_MATCH:
6171                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6172                                 break;
6173                         default:
6174                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6175                                 ret = I40E_ERR_PARAM;
6176                                 goto DONE;
6177                         }
6178                         req_list[i].flags = rte_cpu_to_le_16(flags);
6179                 }
6180
6181                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6182                                                 actual_num, NULL);
6183                 if (ret != I40E_SUCCESS) {
6184                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6185                         goto DONE;
6186                 }
6187                 num += actual_num;
6188         } while (num < total);
6189
6190 DONE:
6191         rte_free(req_list);
6192         return ret;
6193 }
6194
6195 /* Find out specific MAC filter */
6196 static struct i40e_mac_filter *
6197 i40e_find_mac_filter(struct i40e_vsi *vsi,
6198                          struct ether_addr *macaddr)
6199 {
6200         struct i40e_mac_filter *f;
6201
6202         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6203                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6204                         return f;
6205         }
6206
6207         return NULL;
6208 }
6209
6210 static bool
6211 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6212                          uint16_t vlan_id)
6213 {
6214         uint32_t vid_idx, vid_bit;
6215
6216         if (vlan_id > ETH_VLAN_ID_MAX)
6217                 return 0;
6218
6219         vid_idx = I40E_VFTA_IDX(vlan_id);
6220         vid_bit = I40E_VFTA_BIT(vlan_id);
6221
6222         if (vsi->vfta[vid_idx] & vid_bit)
6223                 return 1;
6224         else
6225                 return 0;
6226 }
6227
6228 static void
6229 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6230                        uint16_t vlan_id, bool on)
6231 {
6232         uint32_t vid_idx, vid_bit;
6233
6234         vid_idx = I40E_VFTA_IDX(vlan_id);
6235         vid_bit = I40E_VFTA_BIT(vlan_id);
6236
6237         if (on)
6238                 vsi->vfta[vid_idx] |= vid_bit;
6239         else
6240                 vsi->vfta[vid_idx] &= ~vid_bit;
6241 }
6242
6243 void
6244 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6245                      uint16_t vlan_id, bool on)
6246 {
6247         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6248         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6249         int ret;
6250
6251         if (vlan_id > ETH_VLAN_ID_MAX)
6252                 return;
6253
6254         i40e_store_vlan_filter(vsi, vlan_id, on);
6255
6256         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6257                 return;
6258
6259         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6260
6261         if (on) {
6262                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6263                                        &vlan_data, 1, NULL);
6264                 if (ret != I40E_SUCCESS)
6265                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6266         } else {
6267                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6268                                           &vlan_data, 1, NULL);
6269                 if (ret != I40E_SUCCESS)
6270                         PMD_DRV_LOG(ERR,
6271                                     "Failed to remove vlan filter");
6272         }
6273 }
6274
6275 /**
6276  * Find all vlan options for specific mac addr,
6277  * return with actual vlan found.
6278  */
6279 int
6280 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6281                            struct i40e_macvlan_filter *mv_f,
6282                            int num, struct ether_addr *addr)
6283 {
6284         int i;
6285         uint32_t j, k;
6286
6287         /**
6288          * Not to use i40e_find_vlan_filter to decrease the loop time,
6289          * although the code looks complex.
6290           */
6291         if (num < vsi->vlan_num)
6292                 return I40E_ERR_PARAM;
6293
6294         i = 0;
6295         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6296                 if (vsi->vfta[j]) {
6297                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6298                                 if (vsi->vfta[j] & (1 << k)) {
6299                                         if (i > num - 1) {
6300                                                 PMD_DRV_LOG(ERR,
6301                                                         "vlan number doesn't match");
6302                                                 return I40E_ERR_PARAM;
6303                                         }
6304                                         rte_memcpy(&mv_f[i].macaddr,
6305                                                         addr, ETH_ADDR_LEN);
6306                                         mv_f[i].vlan_id =
6307                                                 j * I40E_UINT32_BIT_SIZE + k;
6308                                         i++;
6309                                 }
6310                         }
6311                 }
6312         }
6313         return I40E_SUCCESS;
6314 }
6315
6316 static inline int
6317 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6318                            struct i40e_macvlan_filter *mv_f,
6319                            int num,
6320                            uint16_t vlan)
6321 {
6322         int i = 0;
6323         struct i40e_mac_filter *f;
6324
6325         if (num < vsi->mac_num)
6326                 return I40E_ERR_PARAM;
6327
6328         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6329                 if (i > num - 1) {
6330                         PMD_DRV_LOG(ERR, "buffer number not match");
6331                         return I40E_ERR_PARAM;
6332                 }
6333                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6334                                 ETH_ADDR_LEN);
6335                 mv_f[i].vlan_id = vlan;
6336                 mv_f[i].filter_type = f->mac_info.filter_type;
6337                 i++;
6338         }
6339
6340         return I40E_SUCCESS;
6341 }
6342
6343 static int
6344 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6345 {
6346         int i, j, num;
6347         struct i40e_mac_filter *f;
6348         struct i40e_macvlan_filter *mv_f;
6349         int ret = I40E_SUCCESS;
6350
6351         if (vsi == NULL || vsi->mac_num == 0)
6352                 return I40E_ERR_PARAM;
6353
6354         /* Case that no vlan is set */
6355         if (vsi->vlan_num == 0)
6356                 num = vsi->mac_num;
6357         else
6358                 num = vsi->mac_num * vsi->vlan_num;
6359
6360         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6361         if (mv_f == NULL) {
6362                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6363                 return I40E_ERR_NO_MEMORY;
6364         }
6365
6366         i = 0;
6367         if (vsi->vlan_num == 0) {
6368                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6369                         rte_memcpy(&mv_f[i].macaddr,
6370                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6371                         mv_f[i].filter_type = f->mac_info.filter_type;
6372                         mv_f[i].vlan_id = 0;
6373                         i++;
6374                 }
6375         } else {
6376                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6377                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6378                                         vsi->vlan_num, &f->mac_info.mac_addr);
6379                         if (ret != I40E_SUCCESS)
6380                                 goto DONE;
6381                         for (j = i; j < i + vsi->vlan_num; j++)
6382                                 mv_f[j].filter_type = f->mac_info.filter_type;
6383                         i += vsi->vlan_num;
6384                 }
6385         }
6386
6387         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6388 DONE:
6389         rte_free(mv_f);
6390
6391         return ret;
6392 }
6393
6394 int
6395 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6396 {
6397         struct i40e_macvlan_filter *mv_f;
6398         int mac_num;
6399         int ret = I40E_SUCCESS;
6400
6401         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6402                 return I40E_ERR_PARAM;
6403
6404         /* If it's already set, just return */
6405         if (i40e_find_vlan_filter(vsi,vlan))
6406                 return I40E_SUCCESS;
6407
6408         mac_num = vsi->mac_num;
6409
6410         if (mac_num == 0) {
6411                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6412                 return I40E_ERR_PARAM;
6413         }
6414
6415         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6416
6417         if (mv_f == NULL) {
6418                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6419                 return I40E_ERR_NO_MEMORY;
6420         }
6421
6422         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6423
6424         if (ret != I40E_SUCCESS)
6425                 goto DONE;
6426
6427         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6428
6429         if (ret != I40E_SUCCESS)
6430                 goto DONE;
6431
6432         i40e_set_vlan_filter(vsi, vlan, 1);
6433
6434         vsi->vlan_num++;
6435         ret = I40E_SUCCESS;
6436 DONE:
6437         rte_free(mv_f);
6438         return ret;
6439 }
6440
6441 int
6442 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6443 {
6444         struct i40e_macvlan_filter *mv_f;
6445         int mac_num;
6446         int ret = I40E_SUCCESS;
6447
6448         /**
6449          * Vlan 0 is the generic filter for untagged packets
6450          * and can't be removed.
6451          */
6452         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6453                 return I40E_ERR_PARAM;
6454
6455         /* If can't find it, just return */
6456         if (!i40e_find_vlan_filter(vsi, vlan))
6457                 return I40E_ERR_PARAM;
6458
6459         mac_num = vsi->mac_num;
6460
6461         if (mac_num == 0) {
6462                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6463                 return I40E_ERR_PARAM;
6464         }
6465
6466         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6467
6468         if (mv_f == NULL) {
6469                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6470                 return I40E_ERR_NO_MEMORY;
6471         }
6472
6473         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6474
6475         if (ret != I40E_SUCCESS)
6476                 goto DONE;
6477
6478         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6479
6480         if (ret != I40E_SUCCESS)
6481                 goto DONE;
6482
6483         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6484         if (vsi->vlan_num == 1) {
6485                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6486                 if (ret != I40E_SUCCESS)
6487                         goto DONE;
6488
6489                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6490                 if (ret != I40E_SUCCESS)
6491                         goto DONE;
6492         }
6493
6494         i40e_set_vlan_filter(vsi, vlan, 0);
6495
6496         vsi->vlan_num--;
6497         ret = I40E_SUCCESS;
6498 DONE:
6499         rte_free(mv_f);
6500         return ret;
6501 }
6502
6503 int
6504 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6505 {
6506         struct i40e_mac_filter *f;
6507         struct i40e_macvlan_filter *mv_f;
6508         int i, vlan_num = 0;
6509         int ret = I40E_SUCCESS;
6510
6511         /* If it's add and we've config it, return */
6512         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6513         if (f != NULL)
6514                 return I40E_SUCCESS;
6515         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6516                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6517
6518                 /**
6519                  * If vlan_num is 0, that's the first time to add mac,
6520                  * set mask for vlan_id 0.
6521                  */
6522                 if (vsi->vlan_num == 0) {
6523                         i40e_set_vlan_filter(vsi, 0, 1);
6524                         vsi->vlan_num = 1;
6525                 }
6526                 vlan_num = vsi->vlan_num;
6527         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6528                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6529                 vlan_num = 1;
6530
6531         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6532         if (mv_f == NULL) {
6533                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6534                 return I40E_ERR_NO_MEMORY;
6535         }
6536
6537         for (i = 0; i < vlan_num; i++) {
6538                 mv_f[i].filter_type = mac_filter->filter_type;
6539                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6540                                 ETH_ADDR_LEN);
6541         }
6542
6543         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6544                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6545                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6546                                         &mac_filter->mac_addr);
6547                 if (ret != I40E_SUCCESS)
6548                         goto DONE;
6549         }
6550
6551         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6552         if (ret != I40E_SUCCESS)
6553                 goto DONE;
6554
6555         /* Add the mac addr into mac list */
6556         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6557         if (f == NULL) {
6558                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6559                 ret = I40E_ERR_NO_MEMORY;
6560                 goto DONE;
6561         }
6562         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6563                         ETH_ADDR_LEN);
6564         f->mac_info.filter_type = mac_filter->filter_type;
6565         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6566         vsi->mac_num++;
6567
6568         ret = I40E_SUCCESS;
6569 DONE:
6570         rte_free(mv_f);
6571
6572         return ret;
6573 }
6574
6575 int
6576 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6577 {
6578         struct i40e_mac_filter *f;
6579         struct i40e_macvlan_filter *mv_f;
6580         int i, vlan_num;
6581         enum rte_mac_filter_type filter_type;
6582         int ret = I40E_SUCCESS;
6583
6584         /* Can't find it, return an error */
6585         f = i40e_find_mac_filter(vsi, addr);
6586         if (f == NULL)
6587                 return I40E_ERR_PARAM;
6588
6589         vlan_num = vsi->vlan_num;
6590         filter_type = f->mac_info.filter_type;
6591         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6592                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6593                 if (vlan_num == 0) {
6594                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6595                         return I40E_ERR_PARAM;
6596                 }
6597         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6598                         filter_type == RTE_MAC_HASH_MATCH)
6599                 vlan_num = 1;
6600
6601         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6602         if (mv_f == NULL) {
6603                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6604                 return I40E_ERR_NO_MEMORY;
6605         }
6606
6607         for (i = 0; i < vlan_num; i++) {
6608                 mv_f[i].filter_type = filter_type;
6609                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6610                                 ETH_ADDR_LEN);
6611         }
6612         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6613                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6614                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6615                 if (ret != I40E_SUCCESS)
6616                         goto DONE;
6617         }
6618
6619         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6620         if (ret != I40E_SUCCESS)
6621                 goto DONE;
6622
6623         /* Remove the mac addr into mac list */
6624         TAILQ_REMOVE(&vsi->mac_list, f, next);
6625         rte_free(f);
6626         vsi->mac_num--;
6627
6628         ret = I40E_SUCCESS;
6629 DONE:
6630         rte_free(mv_f);
6631         return ret;
6632 }
6633
6634 /* Configure hash enable flags for RSS */
6635 uint64_t
6636 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6637 {
6638         uint64_t hena = 0;
6639         int i;
6640
6641         if (!flags)
6642                 return hena;
6643
6644         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6645                 if (flags & (1ULL << i))
6646                         hena |= adapter->pctypes_tbl[i];
6647         }
6648
6649         return hena;
6650 }
6651
6652 /* Parse the hash enable flags */
6653 uint64_t
6654 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6655 {
6656         uint64_t rss_hf = 0;
6657
6658         if (!flags)
6659                 return rss_hf;
6660         int i;
6661
6662         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6663                 if (flags & adapter->pctypes_tbl[i])
6664                         rss_hf |= (1ULL << i);
6665         }
6666         return rss_hf;
6667 }
6668
6669 /* Disable RSS */
6670 static void
6671 i40e_pf_disable_rss(struct i40e_pf *pf)
6672 {
6673         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6674
6675         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6676         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6677         I40E_WRITE_FLUSH(hw);
6678 }
6679
6680 static int
6681 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6682 {
6683         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6684         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6685         int ret = 0;
6686
6687         if (!key || key_len == 0) {
6688                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6689                 return 0;
6690         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6691                 sizeof(uint32_t)) {
6692                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6693                 return -EINVAL;
6694         }
6695
6696         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6697                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6698                         (struct i40e_aqc_get_set_rss_key_data *)key;
6699
6700                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6701                 if (ret)
6702                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6703         } else {
6704                 uint32_t *hash_key = (uint32_t *)key;
6705                 uint16_t i;
6706
6707                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6708                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6709                 I40E_WRITE_FLUSH(hw);
6710         }
6711
6712         return ret;
6713 }
6714
6715 static int
6716 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6717 {
6718         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6719         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6720         int ret;
6721
6722         if (!key || !key_len)
6723                 return -EINVAL;
6724
6725         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6726                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6727                         (struct i40e_aqc_get_set_rss_key_data *)key);
6728                 if (ret) {
6729                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6730                         return ret;
6731                 }
6732         } else {
6733                 uint32_t *key_dw = (uint32_t *)key;
6734                 uint16_t i;
6735
6736                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6737                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6738         }
6739         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6740
6741         return 0;
6742 }
6743
6744 static int
6745 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6746 {
6747         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6748         uint64_t hena;
6749         int ret;
6750
6751         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6752                                rss_conf->rss_key_len);
6753         if (ret)
6754                 return ret;
6755
6756         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6757         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6758         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6759         I40E_WRITE_FLUSH(hw);
6760
6761         return 0;
6762 }
6763
6764 static int
6765 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6766                          struct rte_eth_rss_conf *rss_conf)
6767 {
6768         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6769         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6770         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6771         uint64_t hena;
6772
6773         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6774         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6775
6776         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6777                 if (rss_hf != 0) /* Enable RSS */
6778                         return -EINVAL;
6779                 return 0; /* Nothing to do */
6780         }
6781         /* RSS enabled */
6782         if (rss_hf == 0) /* Disable RSS */
6783                 return -EINVAL;
6784
6785         return i40e_hw_rss_hash_set(pf, rss_conf);
6786 }
6787
6788 static int
6789 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6790                            struct rte_eth_rss_conf *rss_conf)
6791 {
6792         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6793         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6794         uint64_t hena;
6795
6796         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6797                          &rss_conf->rss_key_len);
6798
6799         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6800         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6801         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6802
6803         return 0;
6804 }
6805
6806 static int
6807 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6808 {
6809         switch (filter_type) {
6810         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6811                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6812                 break;
6813         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6814                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6815                 break;
6816         case RTE_TUNNEL_FILTER_IMAC_TENID:
6817                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6818                 break;
6819         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6820                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6821                 break;
6822         case ETH_TUNNEL_FILTER_IMAC:
6823                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6824                 break;
6825         case ETH_TUNNEL_FILTER_OIP:
6826                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6827                 break;
6828         case ETH_TUNNEL_FILTER_IIP:
6829                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6830                 break;
6831         default:
6832                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6833                 return -EINVAL;
6834         }
6835
6836         return 0;
6837 }
6838
6839 /* Convert tunnel filter structure */
6840 static int
6841 i40e_tunnel_filter_convert(
6842         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6843         struct i40e_tunnel_filter *tunnel_filter)
6844 {
6845         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6846                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6847         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6848                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6849         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6850         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6851              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6852             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6853                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6854         else
6855                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6856         tunnel_filter->input.flags = cld_filter->element.flags;
6857         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6858         tunnel_filter->queue = cld_filter->element.queue_number;
6859         rte_memcpy(tunnel_filter->input.general_fields,
6860                    cld_filter->general_fields,
6861                    sizeof(cld_filter->general_fields));
6862
6863         return 0;
6864 }
6865
6866 /* Check if there exists the tunnel filter */
6867 struct i40e_tunnel_filter *
6868 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6869                              const struct i40e_tunnel_filter_input *input)
6870 {
6871         int ret;
6872
6873         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6874         if (ret < 0)
6875                 return NULL;
6876
6877         return tunnel_rule->hash_map[ret];
6878 }
6879
6880 /* Add a tunnel filter into the SW list */
6881 static int
6882 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6883                              struct i40e_tunnel_filter *tunnel_filter)
6884 {
6885         struct i40e_tunnel_rule *rule = &pf->tunnel;
6886         int ret;
6887
6888         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6889         if (ret < 0) {
6890                 PMD_DRV_LOG(ERR,
6891                             "Failed to insert tunnel filter to hash table %d!",
6892                             ret);
6893                 return ret;
6894         }
6895         rule->hash_map[ret] = tunnel_filter;
6896
6897         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6898
6899         return 0;
6900 }
6901
6902 /* Delete a tunnel filter from the SW list */
6903 int
6904 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6905                           struct i40e_tunnel_filter_input *input)
6906 {
6907         struct i40e_tunnel_rule *rule = &pf->tunnel;
6908         struct i40e_tunnel_filter *tunnel_filter;
6909         int ret;
6910
6911         ret = rte_hash_del_key(rule->hash_table, input);
6912         if (ret < 0) {
6913                 PMD_DRV_LOG(ERR,
6914                             "Failed to delete tunnel filter to hash table %d!",
6915                             ret);
6916                 return ret;
6917         }
6918         tunnel_filter = rule->hash_map[ret];
6919         rule->hash_map[ret] = NULL;
6920
6921         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6922         rte_free(tunnel_filter);
6923
6924         return 0;
6925 }
6926
6927 int
6928 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6929                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6930                         uint8_t add)
6931 {
6932         uint16_t ip_type;
6933         uint32_t ipv4_addr;
6934         uint8_t i, tun_type = 0;
6935         /* internal varialbe to convert ipv6 byte order */
6936         uint32_t convert_ipv6[4];
6937         int val, ret = 0;
6938         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6939         struct i40e_vsi *vsi = pf->main_vsi;
6940         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6941         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6942         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6943         struct i40e_tunnel_filter *tunnel, *node;
6944         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6945
6946         cld_filter = rte_zmalloc("tunnel_filter",
6947                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6948         0);
6949
6950         if (NULL == cld_filter) {
6951                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6952                 return -ENOMEM;
6953         }
6954         pfilter = cld_filter;
6955
6956         ether_addr_copy(&tunnel_filter->outer_mac,
6957                         (struct ether_addr *)&pfilter->element.outer_mac);
6958         ether_addr_copy(&tunnel_filter->inner_mac,
6959                         (struct ether_addr *)&pfilter->element.inner_mac);
6960
6961         pfilter->element.inner_vlan =
6962                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6963         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6964                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6965                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6966                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6967                                 &rte_cpu_to_le_32(ipv4_addr),
6968                                 sizeof(pfilter->element.ipaddr.v4.data));
6969         } else {
6970                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6971                 for (i = 0; i < 4; i++) {
6972                         convert_ipv6[i] =
6973                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6974                 }
6975                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6976                            &convert_ipv6,
6977                            sizeof(pfilter->element.ipaddr.v6.data));
6978         }
6979
6980         /* check tunneled type */
6981         switch (tunnel_filter->tunnel_type) {
6982         case RTE_TUNNEL_TYPE_VXLAN:
6983                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6984                 break;
6985         case RTE_TUNNEL_TYPE_NVGRE:
6986                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6987                 break;
6988         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6989                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6990                 break;
6991         default:
6992                 /* Other tunnel types is not supported. */
6993                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6994                 rte_free(cld_filter);
6995                 return -EINVAL;
6996         }
6997
6998         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6999                                        &pfilter->element.flags);
7000         if (val < 0) {
7001                 rte_free(cld_filter);
7002                 return -EINVAL;
7003         }
7004
7005         pfilter->element.flags |= rte_cpu_to_le_16(
7006                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7007                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7008         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7009         pfilter->element.queue_number =
7010                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7011
7012         /* Check if there is the filter in SW list */
7013         memset(&check_filter, 0, sizeof(check_filter));
7014         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7015         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7016         if (add && node) {
7017                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7018                 return -EINVAL;
7019         }
7020
7021         if (!add && !node) {
7022                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7023                 return -EINVAL;
7024         }
7025
7026         if (add) {
7027                 ret = i40e_aq_add_cloud_filters(hw,
7028                                         vsi->seid, &cld_filter->element, 1);
7029                 if (ret < 0) {
7030                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7031                         return -ENOTSUP;
7032                 }
7033                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7034                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7035                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7036         } else {
7037                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7038                                                    &cld_filter->element, 1);
7039                 if (ret < 0) {
7040                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7041                         return -ENOTSUP;
7042                 }
7043                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7044         }
7045
7046         rte_free(cld_filter);
7047         return ret;
7048 }
7049
7050 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7051 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7052 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7053 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7054 #define I40E_TR_GRE_KEY_MASK                    0x400
7055 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7056 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7057
7058 static enum
7059 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7060 {
7061         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7062         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7063         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7064         enum i40e_status_code status = I40E_SUCCESS;
7065
7066         memset(&filter_replace, 0,
7067                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7068         memset(&filter_replace_buf, 0,
7069                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7070
7071         /* create L1 filter */
7072         filter_replace.old_filter_type =
7073                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7074         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7075         filter_replace.tr_bit = 0;
7076
7077         /* Prepare the buffer, 3 entries */
7078         filter_replace_buf.data[0] =
7079                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7080         filter_replace_buf.data[0] |=
7081                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7082         filter_replace_buf.data[2] = 0xFF;
7083         filter_replace_buf.data[3] = 0xFF;
7084         filter_replace_buf.data[4] =
7085                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7086         filter_replace_buf.data[4] |=
7087                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7088         filter_replace_buf.data[7] = 0xF0;
7089         filter_replace_buf.data[8]
7090                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7091         filter_replace_buf.data[8] |=
7092                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7093         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7094                 I40E_TR_GENEVE_KEY_MASK |
7095                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7096         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7097                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7098                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7099
7100         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7101                                                &filter_replace_buf);
7102         return status;
7103 }
7104
7105 static enum
7106 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7107 {
7108         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7109         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7110         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7111         enum i40e_status_code status = I40E_SUCCESS;
7112
7113         /* For MPLSoUDP */
7114         memset(&filter_replace, 0,
7115                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7116         memset(&filter_replace_buf, 0,
7117                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7118         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7119                 I40E_AQC_MIRROR_CLOUD_FILTER;
7120         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7121         filter_replace.new_filter_type =
7122                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7123         /* Prepare the buffer, 2 entries */
7124         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7125         filter_replace_buf.data[0] |=
7126                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7127         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7128         filter_replace_buf.data[4] |=
7129                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7130         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7131                                                &filter_replace_buf);
7132         if (status < 0)
7133                 return status;
7134
7135         /* For MPLSoGRE */
7136         memset(&filter_replace, 0,
7137                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7138         memset(&filter_replace_buf, 0,
7139                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7140
7141         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7142                 I40E_AQC_MIRROR_CLOUD_FILTER;
7143         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7144         filter_replace.new_filter_type =
7145                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7146         /* Prepare the buffer, 2 entries */
7147         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7148         filter_replace_buf.data[0] |=
7149                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7150         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7151         filter_replace_buf.data[4] |=
7152                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7153
7154         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7155                                                &filter_replace_buf);
7156         return status;
7157 }
7158
7159 static enum i40e_status_code
7160 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7161 {
7162         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7163         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7164         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7165         enum i40e_status_code status = I40E_SUCCESS;
7166
7167         /* For GTP-C */
7168         memset(&filter_replace, 0,
7169                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7170         memset(&filter_replace_buf, 0,
7171                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7172         /* create L1 filter */
7173         filter_replace.old_filter_type =
7174                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7175         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7176         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7177                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7178         /* Prepare the buffer, 2 entries */
7179         filter_replace_buf.data[0] =
7180                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7181         filter_replace_buf.data[0] |=
7182                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7183         filter_replace_buf.data[2] = 0xFF;
7184         filter_replace_buf.data[3] = 0xFF;
7185         filter_replace_buf.data[4] =
7186                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7187         filter_replace_buf.data[4] |=
7188                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7189         filter_replace_buf.data[6] = 0xFF;
7190         filter_replace_buf.data[7] = 0xFF;
7191         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7192                                                &filter_replace_buf);
7193         if (status < 0)
7194                 return status;
7195
7196         /* for GTP-U */
7197         memset(&filter_replace, 0,
7198                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7199         memset(&filter_replace_buf, 0,
7200                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7201         /* create L1 filter */
7202         filter_replace.old_filter_type =
7203                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7204         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7205         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7206                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7207         /* Prepare the buffer, 2 entries */
7208         filter_replace_buf.data[0] =
7209                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7210         filter_replace_buf.data[0] |=
7211                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7212         filter_replace_buf.data[2] = 0xFF;
7213         filter_replace_buf.data[3] = 0xFF;
7214         filter_replace_buf.data[4] =
7215                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7216         filter_replace_buf.data[4] |=
7217                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7218         filter_replace_buf.data[6] = 0xFF;
7219         filter_replace_buf.data[7] = 0xFF;
7220
7221         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7222                                                &filter_replace_buf);
7223         return status;
7224 }
7225
7226 static enum
7227 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7228 {
7229         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7230         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7231         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7232         enum i40e_status_code status = I40E_SUCCESS;
7233
7234         /* for GTP-C */
7235         memset(&filter_replace, 0,
7236                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7237         memset(&filter_replace_buf, 0,
7238                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7239         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7240         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7241         filter_replace.new_filter_type =
7242                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7243         /* Prepare the buffer, 2 entries */
7244         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7245         filter_replace_buf.data[0] |=
7246                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7247         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7248         filter_replace_buf.data[4] |=
7249                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7250         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7251                                                &filter_replace_buf);
7252         if (status < 0)
7253                 return status;
7254
7255         /* for GTP-U */
7256         memset(&filter_replace, 0,
7257                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7258         memset(&filter_replace_buf, 0,
7259                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7260         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7261         filter_replace.old_filter_type =
7262                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7263         filter_replace.new_filter_type =
7264                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7265         /* Prepare the buffer, 2 entries */
7266         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7267         filter_replace_buf.data[0] |=
7268                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7269         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7270         filter_replace_buf.data[4] |=
7271                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7272
7273         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7274                                                &filter_replace_buf);
7275         return status;
7276 }
7277
7278 int
7279 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7280                       struct i40e_tunnel_filter_conf *tunnel_filter,
7281                       uint8_t add)
7282 {
7283         uint16_t ip_type;
7284         uint32_t ipv4_addr;
7285         uint8_t i, tun_type = 0;
7286         /* internal variable to convert ipv6 byte order */
7287         uint32_t convert_ipv6[4];
7288         int val, ret = 0;
7289         struct i40e_pf_vf *vf = NULL;
7290         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7291         struct i40e_vsi *vsi;
7292         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7293         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7294         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7295         struct i40e_tunnel_filter *tunnel, *node;
7296         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7297         uint32_t teid_le;
7298         bool big_buffer = 0;
7299
7300         cld_filter = rte_zmalloc("tunnel_filter",
7301                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7302                          0);
7303
7304         if (cld_filter == NULL) {
7305                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7306                 return -ENOMEM;
7307         }
7308         pfilter = cld_filter;
7309
7310         ether_addr_copy(&tunnel_filter->outer_mac,
7311                         (struct ether_addr *)&pfilter->element.outer_mac);
7312         ether_addr_copy(&tunnel_filter->inner_mac,
7313                         (struct ether_addr *)&pfilter->element.inner_mac);
7314
7315         pfilter->element.inner_vlan =
7316                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7317         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7318                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7319                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7320                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7321                                 &rte_cpu_to_le_32(ipv4_addr),
7322                                 sizeof(pfilter->element.ipaddr.v4.data));
7323         } else {
7324                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7325                 for (i = 0; i < 4; i++) {
7326                         convert_ipv6[i] =
7327                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7328                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7329                 }
7330                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7331                            &convert_ipv6,
7332                            sizeof(pfilter->element.ipaddr.v6.data));
7333         }
7334
7335         /* check tunneled type */
7336         switch (tunnel_filter->tunnel_type) {
7337         case I40E_TUNNEL_TYPE_VXLAN:
7338                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7339                 break;
7340         case I40E_TUNNEL_TYPE_NVGRE:
7341                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7342                 break;
7343         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7344                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7345                 break;
7346         case I40E_TUNNEL_TYPE_MPLSoUDP:
7347                 if (!pf->mpls_replace_flag) {
7348                         i40e_replace_mpls_l1_filter(pf);
7349                         i40e_replace_mpls_cloud_filter(pf);
7350                         pf->mpls_replace_flag = 1;
7351                 }
7352                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7353                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7354                         teid_le >> 4;
7355                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7356                         (teid_le & 0xF) << 12;
7357                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7358                         0x40;
7359                 big_buffer = 1;
7360                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7361                 break;
7362         case I40E_TUNNEL_TYPE_MPLSoGRE:
7363                 if (!pf->mpls_replace_flag) {
7364                         i40e_replace_mpls_l1_filter(pf);
7365                         i40e_replace_mpls_cloud_filter(pf);
7366                         pf->mpls_replace_flag = 1;
7367                 }
7368                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7369                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7370                         teid_le >> 4;
7371                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7372                         (teid_le & 0xF) << 12;
7373                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7374                         0x0;
7375                 big_buffer = 1;
7376                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7377                 break;
7378         case I40E_TUNNEL_TYPE_GTPC:
7379                 if (!pf->gtp_replace_flag) {
7380                         i40e_replace_gtp_l1_filter(pf);
7381                         i40e_replace_gtp_cloud_filter(pf);
7382                         pf->gtp_replace_flag = 1;
7383                 }
7384                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7385                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7386                         (teid_le >> 16) & 0xFFFF;
7387                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7388                         teid_le & 0xFFFF;
7389                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7390                         0x0;
7391                 big_buffer = 1;
7392                 break;
7393         case I40E_TUNNEL_TYPE_GTPU:
7394                 if (!pf->gtp_replace_flag) {
7395                         i40e_replace_gtp_l1_filter(pf);
7396                         i40e_replace_gtp_cloud_filter(pf);
7397                         pf->gtp_replace_flag = 1;
7398                 }
7399                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7400                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7401                         (teid_le >> 16) & 0xFFFF;
7402                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7403                         teid_le & 0xFFFF;
7404                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7405                         0x0;
7406                 big_buffer = 1;
7407                 break;
7408         case I40E_TUNNEL_TYPE_QINQ:
7409                 if (!pf->qinq_replace_flag) {
7410                         ret = i40e_cloud_filter_qinq_create(pf);
7411                         if (ret < 0)
7412                                 PMD_DRV_LOG(DEBUG,
7413                                             "QinQ tunnel filter already created.");
7414                         pf->qinq_replace_flag = 1;
7415                 }
7416                 /*      Add in the General fields the values of
7417                  *      the Outer and Inner VLAN
7418                  *      Big Buffer should be set, see changes in
7419                  *      i40e_aq_add_cloud_filters
7420                  */
7421                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7422                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7423                 big_buffer = 1;
7424                 break;
7425         default:
7426                 /* Other tunnel types is not supported. */
7427                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7428                 rte_free(cld_filter);
7429                 return -EINVAL;
7430         }
7431
7432         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7433                 pfilter->element.flags =
7434                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7435         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7436                 pfilter->element.flags =
7437                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7438         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7439                 pfilter->element.flags =
7440                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7441         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7442                 pfilter->element.flags =
7443                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7444         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7445                 pfilter->element.flags |=
7446                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7447         else {
7448                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7449                                                 &pfilter->element.flags);
7450                 if (val < 0) {
7451                         rte_free(cld_filter);
7452                         return -EINVAL;
7453                 }
7454         }
7455
7456         pfilter->element.flags |= rte_cpu_to_le_16(
7457                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7458                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7459         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7460         pfilter->element.queue_number =
7461                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7462
7463         if (!tunnel_filter->is_to_vf)
7464                 vsi = pf->main_vsi;
7465         else {
7466                 if (tunnel_filter->vf_id >= pf->vf_num) {
7467                         PMD_DRV_LOG(ERR, "Invalid argument.");
7468                         return -EINVAL;
7469                 }
7470                 vf = &pf->vfs[tunnel_filter->vf_id];
7471                 vsi = vf->vsi;
7472         }
7473
7474         /* Check if there is the filter in SW list */
7475         memset(&check_filter, 0, sizeof(check_filter));
7476         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7477         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7478         check_filter.vf_id = tunnel_filter->vf_id;
7479         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7480         if (add && node) {
7481                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7482                 return -EINVAL;
7483         }
7484
7485         if (!add && !node) {
7486                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7487                 return -EINVAL;
7488         }
7489
7490         if (add) {
7491                 if (big_buffer)
7492                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7493                                                    vsi->seid, cld_filter, 1);
7494                 else
7495                         ret = i40e_aq_add_cloud_filters(hw,
7496                                         vsi->seid, &cld_filter->element, 1);
7497                 if (ret < 0) {
7498                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7499                         return -ENOTSUP;
7500                 }
7501                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7502                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7503                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7504         } else {
7505                 if (big_buffer)
7506                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7507                                 hw, vsi->seid, cld_filter, 1);
7508                 else
7509                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7510                                                    &cld_filter->element, 1);
7511                 if (ret < 0) {
7512                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7513                         return -ENOTSUP;
7514                 }
7515                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7516         }
7517
7518         rte_free(cld_filter);
7519         return ret;
7520 }
7521
7522 static int
7523 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7524 {
7525         uint8_t i;
7526
7527         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7528                 if (pf->vxlan_ports[i] == port)
7529                         return i;
7530         }
7531
7532         return -1;
7533 }
7534
7535 static int
7536 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7537 {
7538         int  idx, ret;
7539         uint8_t filter_idx;
7540         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7541
7542         idx = i40e_get_vxlan_port_idx(pf, port);
7543
7544         /* Check if port already exists */
7545         if (idx >= 0) {
7546                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7547                 return -EINVAL;
7548         }
7549
7550         /* Now check if there is space to add the new port */
7551         idx = i40e_get_vxlan_port_idx(pf, 0);
7552         if (idx < 0) {
7553                 PMD_DRV_LOG(ERR,
7554                         "Maximum number of UDP ports reached, not adding port %d",
7555                         port);
7556                 return -ENOSPC;
7557         }
7558
7559         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7560                                         &filter_idx, NULL);
7561         if (ret < 0) {
7562                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7563                 return -1;
7564         }
7565
7566         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7567                          port,  filter_idx);
7568
7569         /* New port: add it and mark its index in the bitmap */
7570         pf->vxlan_ports[idx] = port;
7571         pf->vxlan_bitmap |= (1 << idx);
7572
7573         if (!(pf->flags & I40E_FLAG_VXLAN))
7574                 pf->flags |= I40E_FLAG_VXLAN;
7575
7576         return 0;
7577 }
7578
7579 static int
7580 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7581 {
7582         int idx;
7583         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7584
7585         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7586                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7587                 return -EINVAL;
7588         }
7589
7590         idx = i40e_get_vxlan_port_idx(pf, port);
7591
7592         if (idx < 0) {
7593                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7594                 return -EINVAL;
7595         }
7596
7597         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7598                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7599                 return -1;
7600         }
7601
7602         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7603                         port, idx);
7604
7605         pf->vxlan_ports[idx] = 0;
7606         pf->vxlan_bitmap &= ~(1 << idx);
7607
7608         if (!pf->vxlan_bitmap)
7609                 pf->flags &= ~I40E_FLAG_VXLAN;
7610
7611         return 0;
7612 }
7613
7614 /* Add UDP tunneling port */
7615 static int
7616 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7617                              struct rte_eth_udp_tunnel *udp_tunnel)
7618 {
7619         int ret = 0;
7620         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7621
7622         if (udp_tunnel == NULL)
7623                 return -EINVAL;
7624
7625         switch (udp_tunnel->prot_type) {
7626         case RTE_TUNNEL_TYPE_VXLAN:
7627                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7628                 break;
7629
7630         case RTE_TUNNEL_TYPE_GENEVE:
7631         case RTE_TUNNEL_TYPE_TEREDO:
7632                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7633                 ret = -1;
7634                 break;
7635
7636         default:
7637                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7638                 ret = -1;
7639                 break;
7640         }
7641
7642         return ret;
7643 }
7644
7645 /* Remove UDP tunneling port */
7646 static int
7647 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7648                              struct rte_eth_udp_tunnel *udp_tunnel)
7649 {
7650         int ret = 0;
7651         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7652
7653         if (udp_tunnel == NULL)
7654                 return -EINVAL;
7655
7656         switch (udp_tunnel->prot_type) {
7657         case RTE_TUNNEL_TYPE_VXLAN:
7658                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7659                 break;
7660         case RTE_TUNNEL_TYPE_GENEVE:
7661         case RTE_TUNNEL_TYPE_TEREDO:
7662                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7663                 ret = -1;
7664                 break;
7665         default:
7666                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7667                 ret = -1;
7668                 break;
7669         }
7670
7671         return ret;
7672 }
7673
7674 /* Calculate the maximum number of contiguous PF queues that are configured */
7675 static int
7676 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7677 {
7678         struct rte_eth_dev_data *data = pf->dev_data;
7679         int i, num;
7680         struct i40e_rx_queue *rxq;
7681
7682         num = 0;
7683         for (i = 0; i < pf->lan_nb_qps; i++) {
7684                 rxq = data->rx_queues[i];
7685                 if (rxq && rxq->q_set)
7686                         num++;
7687                 else
7688                         break;
7689         }
7690
7691         return num;
7692 }
7693
7694 /* Configure RSS */
7695 static int
7696 i40e_pf_config_rss(struct i40e_pf *pf)
7697 {
7698         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7699         struct rte_eth_rss_conf rss_conf;
7700         uint32_t i, lut = 0;
7701         uint16_t j, num;
7702
7703         /*
7704          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7705          * It's necessary to calculate the actual PF queues that are configured.
7706          */
7707         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7708                 num = i40e_pf_calc_configured_queues_num(pf);
7709         else
7710                 num = pf->dev_data->nb_rx_queues;
7711
7712         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7713         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7714                         num);
7715
7716         if (num == 0) {
7717                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7718                 return -ENOTSUP;
7719         }
7720
7721         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7722                 if (j == num)
7723                         j = 0;
7724                 lut = (lut << 8) | (j & ((0x1 <<
7725                         hw->func_caps.rss_table_entry_width) - 1));
7726                 if ((i & 3) == 3)
7727                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7728         }
7729
7730         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7731         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7732                 i40e_pf_disable_rss(pf);
7733                 return 0;
7734         }
7735         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7736                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7737                 /* Random default keys */
7738                 static uint32_t rss_key_default[] = {0x6b793944,
7739                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7740                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7741                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7742
7743                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7744                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7745                                                         sizeof(uint32_t);
7746         }
7747
7748         return i40e_hw_rss_hash_set(pf, &rss_conf);
7749 }
7750
7751 static int
7752 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7753                                struct rte_eth_tunnel_filter_conf *filter)
7754 {
7755         if (pf == NULL || filter == NULL) {
7756                 PMD_DRV_LOG(ERR, "Invalid parameter");
7757                 return -EINVAL;
7758         }
7759
7760         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7761                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7762                 return -EINVAL;
7763         }
7764
7765         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7766                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7767                 return -EINVAL;
7768         }
7769
7770         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7771                 (is_zero_ether_addr(&filter->outer_mac))) {
7772                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7773                 return -EINVAL;
7774         }
7775
7776         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7777                 (is_zero_ether_addr(&filter->inner_mac))) {
7778                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7779                 return -EINVAL;
7780         }
7781
7782         return 0;
7783 }
7784
7785 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7786 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7787 static int
7788 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7789 {
7790         uint32_t val, reg;
7791         int ret = -EINVAL;
7792
7793         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7794         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7795
7796         if (len == 3) {
7797                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7798         } else if (len == 4) {
7799                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7800         } else {
7801                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7802                 return ret;
7803         }
7804
7805         if (reg != val) {
7806                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7807                                                    reg, NULL);
7808                 if (ret != 0)
7809                         return ret;
7810         } else {
7811                 ret = 0;
7812         }
7813         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7814                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7815
7816         return ret;
7817 }
7818
7819 static int
7820 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7821 {
7822         int ret = -EINVAL;
7823
7824         if (!hw || !cfg)
7825                 return -EINVAL;
7826
7827         switch (cfg->cfg_type) {
7828         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7829                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7830                 break;
7831         default:
7832                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7833                 break;
7834         }
7835
7836         return ret;
7837 }
7838
7839 static int
7840 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7841                                enum rte_filter_op filter_op,
7842                                void *arg)
7843 {
7844         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7845         int ret = I40E_ERR_PARAM;
7846
7847         switch (filter_op) {
7848         case RTE_ETH_FILTER_SET:
7849                 ret = i40e_dev_global_config_set(hw,
7850                         (struct rte_eth_global_cfg *)arg);
7851                 break;
7852         default:
7853                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7854                 break;
7855         }
7856
7857         return ret;
7858 }
7859
7860 static int
7861 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7862                           enum rte_filter_op filter_op,
7863                           void *arg)
7864 {
7865         struct rte_eth_tunnel_filter_conf *filter;
7866         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7867         int ret = I40E_SUCCESS;
7868
7869         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7870
7871         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7872                 return I40E_ERR_PARAM;
7873
7874         switch (filter_op) {
7875         case RTE_ETH_FILTER_NOP:
7876                 if (!(pf->flags & I40E_FLAG_VXLAN))
7877                         ret = I40E_NOT_SUPPORTED;
7878                 break;
7879         case RTE_ETH_FILTER_ADD:
7880                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7881                 break;
7882         case RTE_ETH_FILTER_DELETE:
7883                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7884                 break;
7885         default:
7886                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7887                 ret = I40E_ERR_PARAM;
7888                 break;
7889         }
7890
7891         return ret;
7892 }
7893
7894 static int
7895 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7896 {
7897         int ret = 0;
7898         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7899
7900         /* RSS setup */
7901         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7902                 ret = i40e_pf_config_rss(pf);
7903         else
7904                 i40e_pf_disable_rss(pf);
7905
7906         return ret;
7907 }
7908
7909 /* Get the symmetric hash enable configurations per port */
7910 static void
7911 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7912 {
7913         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7914
7915         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7916 }
7917
7918 /* Set the symmetric hash enable configurations per port */
7919 static void
7920 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7921 {
7922         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7923
7924         if (enable > 0) {
7925                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7926                         PMD_DRV_LOG(INFO,
7927                                 "Symmetric hash has already been enabled");
7928                         return;
7929                 }
7930                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7931         } else {
7932                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7933                         PMD_DRV_LOG(INFO,
7934                                 "Symmetric hash has already been disabled");
7935                         return;
7936                 }
7937                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7938         }
7939         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7940         I40E_WRITE_FLUSH(hw);
7941 }
7942
7943 /*
7944  * Get global configurations of hash function type and symmetric hash enable
7945  * per flow type (pctype). Note that global configuration means it affects all
7946  * the ports on the same NIC.
7947  */
7948 static int
7949 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7950                                    struct rte_eth_hash_global_conf *g_cfg)
7951 {
7952         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
7953         uint32_t reg;
7954         uint16_t i, j;
7955
7956         memset(g_cfg, 0, sizeof(*g_cfg));
7957         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7958         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7959                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7960         else
7961                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7962         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7963                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7964
7965         /*
7966          * We work only with lowest 32 bits which is not correct, but to work
7967          * properly the valid_bit_mask size should be increased up to 64 bits
7968          * and this will brake ABI. This modification will be done in next
7969          * release
7970          */
7971         g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
7972
7973         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
7974                 if (!adapter->pctypes_tbl[i])
7975                         continue;
7976                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
7977                      j < I40E_FILTER_PCTYPE_MAX; j++) {
7978                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
7979                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
7980                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
7981                                         g_cfg->sym_hash_enable_mask[0] |=
7982                                                                 (1UL << i);
7983                                 }
7984                         }
7985                 }
7986         }
7987
7988         return 0;
7989 }
7990
7991 static int
7992 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
7993                               const struct rte_eth_hash_global_conf *g_cfg)
7994 {
7995         uint32_t i;
7996         uint32_t mask0, i40e_mask = adapter->flow_types_mask;
7997
7998         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7999                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8000                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8001                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8002                                                 g_cfg->hash_func);
8003                 return -EINVAL;
8004         }
8005
8006         /*
8007          * As i40e supports less than 32 flow types, only first 32 bits need to
8008          * be checked.
8009          */
8010         mask0 = g_cfg->valid_bit_mask[0];
8011         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8012                 if (i == 0) {
8013                         /* Check if any unsupported flow type configured */
8014                         if ((mask0 | i40e_mask) ^ i40e_mask)
8015                                 goto mask_err;
8016                 } else {
8017                         if (g_cfg->valid_bit_mask[i])
8018                                 goto mask_err;
8019                 }
8020         }
8021
8022         return 0;
8023
8024 mask_err:
8025         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8026
8027         return -EINVAL;
8028 }
8029
8030 /*
8031  * Set global configurations of hash function type and symmetric hash enable
8032  * per flow type (pctype). Note any modifying global configuration will affect
8033  * all the ports on the same NIC.
8034  */
8035 static int
8036 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8037                                    struct rte_eth_hash_global_conf *g_cfg)
8038 {
8039         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8040         int ret;
8041         uint16_t i, j;
8042         uint32_t reg;
8043         /*
8044          * We work only with lowest 32 bits which is not correct, but to work
8045          * properly the valid_bit_mask size should be increased up to 64 bits
8046          * and this will brake ABI. This modification will be done in next
8047          * release
8048          */
8049         uint32_t mask0 = g_cfg->valid_bit_mask[0] &
8050                                         (uint32_t)adapter->flow_types_mask;
8051
8052         /* Check the input parameters */
8053         ret = i40e_hash_global_config_check(adapter, g_cfg);
8054         if (ret < 0)
8055                 return ret;
8056
8057         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
8058                 if (mask0 & (1UL << i)) {
8059                         reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
8060                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8061
8062                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8063                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8064                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8065                                         i40e_write_rx_ctl(hw,
8066                                                           I40E_GLQF_HSYM(j),
8067                                                           reg);
8068                         }
8069                 }
8070         }
8071
8072         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8073         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8074                 /* Toeplitz */
8075                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8076                         PMD_DRV_LOG(DEBUG,
8077                                 "Hash function already set to Toeplitz");
8078                         goto out;
8079                 }
8080                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8081         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8082                 /* Simple XOR */
8083                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8084                         PMD_DRV_LOG(DEBUG,
8085                                 "Hash function already set to Simple XOR");
8086                         goto out;
8087                 }
8088                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8089         } else
8090                 /* Use the default, and keep it as it is */
8091                 goto out;
8092
8093         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8094
8095 out:
8096         I40E_WRITE_FLUSH(hw);
8097
8098         return 0;
8099 }
8100
8101 /**
8102  * Valid input sets for hash and flow director filters per PCTYPE
8103  */
8104 static uint64_t
8105 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8106                 enum rte_filter_type filter)
8107 {
8108         uint64_t valid;
8109
8110         static const uint64_t valid_hash_inset_table[] = {
8111                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8112                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8113                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8114                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8115                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8116                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8117                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8118                         I40E_INSET_FLEX_PAYLOAD,
8119                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8120                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8121                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8122                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8123                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8124                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8125                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8126                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8127                         I40E_INSET_FLEX_PAYLOAD,
8128                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8129                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8130                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8131                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8132                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8133                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8134                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8135                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8136                         I40E_INSET_FLEX_PAYLOAD,
8137                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8138                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8139                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8140                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8141                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8142                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8143                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8144                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8145                         I40E_INSET_FLEX_PAYLOAD,
8146                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8147                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8148                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8149                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8150                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8151                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8152                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8153                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8154                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8155                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8156                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8157                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8158                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8159                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8160                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8161                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8162                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8163                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8164                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8165                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8166                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8167                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8168                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8169                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8170                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8171                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8172                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8173                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8174                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8175                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8176                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8177                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8178                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8179                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8180                         I40E_INSET_FLEX_PAYLOAD,
8181                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8182                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8183                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8184                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8185                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8186                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8187                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8188                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8189                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8190                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8191                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8192                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8193                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8194                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8195                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8196                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8197                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8198                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8199                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8200                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8201                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8202                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8203                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8204                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8205                         I40E_INSET_FLEX_PAYLOAD,
8206                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8207                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8208                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8209                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8210                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8211                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8212                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8213                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8214                         I40E_INSET_FLEX_PAYLOAD,
8215                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8216                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8217                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8218                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8219                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8220                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8221                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8222                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8223                         I40E_INSET_FLEX_PAYLOAD,
8224                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8225                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8226                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8227                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8228                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8229                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8230                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8231                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8232                         I40E_INSET_FLEX_PAYLOAD,
8233                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8234                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8235                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8236                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8237                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8238                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8239                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8240                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8241                         I40E_INSET_FLEX_PAYLOAD,
8242                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8243                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8244                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8245                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8246                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8247                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8248                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8249                         I40E_INSET_FLEX_PAYLOAD,
8250                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8251                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8252                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8253                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8254                         I40E_INSET_FLEX_PAYLOAD,
8255         };
8256
8257         /**
8258          * Flow director supports only fields defined in
8259          * union rte_eth_fdir_flow.
8260          */
8261         static const uint64_t valid_fdir_inset_table[] = {
8262                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8263                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8264                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8265                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8266                 I40E_INSET_IPV4_TTL,
8267                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8268                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8269                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8270                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8271                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8272                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8273                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8274                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8275                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8276                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8277                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8278                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8279                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8280                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8281                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8282                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8283                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8284                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8285                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8286                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8287                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8288                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8289                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8290                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8291                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8292                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8293                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8294                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8295                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8296                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8297                 I40E_INSET_SCTP_VT,
8298                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8299                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8300                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8301                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8302                 I40E_INSET_IPV4_TTL,
8303                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8304                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8305                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8306                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8307                 I40E_INSET_IPV6_HOP_LIMIT,
8308                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8309                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8310                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8311                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8312                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8313                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8314                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8315                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8316                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8317                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8318                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8319                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8320                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8321                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8322                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8323                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8324                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8325                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8326                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8327                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8328                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8329                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8330                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8331                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8332                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8333                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8334                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8335                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8336                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8337                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8338                 I40E_INSET_SCTP_VT,
8339                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8340                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8341                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8342                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8343                 I40E_INSET_IPV6_HOP_LIMIT,
8344                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8345                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8346                 I40E_INSET_LAST_ETHER_TYPE,
8347         };
8348
8349         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8350                 return 0;
8351         if (filter == RTE_ETH_FILTER_HASH)
8352                 valid = valid_hash_inset_table[pctype];
8353         else
8354                 valid = valid_fdir_inset_table[pctype];
8355
8356         return valid;
8357 }
8358
8359 /**
8360  * Validate if the input set is allowed for a specific PCTYPE
8361  */
8362 int
8363 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8364                 enum rte_filter_type filter, uint64_t inset)
8365 {
8366         uint64_t valid;
8367
8368         valid = i40e_get_valid_input_set(pctype, filter);
8369         if (inset & (~valid))
8370                 return -EINVAL;
8371
8372         return 0;
8373 }
8374
8375 /* default input set fields combination per pctype */
8376 uint64_t
8377 i40e_get_default_input_set(uint16_t pctype)
8378 {
8379         static const uint64_t default_inset_table[] = {
8380                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8381                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8382                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8383                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8384                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8385                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8386                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8387                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8388                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8389                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8390                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8391                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8392                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8393                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8394                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8395                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8396                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8397                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8398                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8399                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8400                         I40E_INSET_SCTP_VT,
8401                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8402                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8403                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8404                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8405                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8406                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8407                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8408                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8409                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8410                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8411                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8412                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8413                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8414                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8415                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8416                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8417                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8418                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8419                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8420                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8421                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8422                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8423                         I40E_INSET_SCTP_VT,
8424                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8425                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8426                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8427                         I40E_INSET_LAST_ETHER_TYPE,
8428         };
8429
8430         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8431                 return 0;
8432
8433         return default_inset_table[pctype];
8434 }
8435
8436 /**
8437  * Parse the input set from index to logical bit masks
8438  */
8439 static int
8440 i40e_parse_input_set(uint64_t *inset,
8441                      enum i40e_filter_pctype pctype,
8442                      enum rte_eth_input_set_field *field,
8443                      uint16_t size)
8444 {
8445         uint16_t i, j;
8446         int ret = -EINVAL;
8447
8448         static const struct {
8449                 enum rte_eth_input_set_field field;
8450                 uint64_t inset;
8451         } inset_convert_table[] = {
8452                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8453                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8454                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8455                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8456                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8457                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8458                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8459                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8460                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8461                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8462                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8463                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8464                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8465                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8466                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8467                         I40E_INSET_IPV6_NEXT_HDR},
8468                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8469                         I40E_INSET_IPV6_HOP_LIMIT},
8470                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8471                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8472                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8473                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8474                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8475                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8476                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8477                         I40E_INSET_SCTP_VT},
8478                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8479                         I40E_INSET_TUNNEL_DMAC},
8480                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8481                         I40E_INSET_VLAN_TUNNEL},
8482                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8483                         I40E_INSET_TUNNEL_ID},
8484                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8485                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8486                         I40E_INSET_FLEX_PAYLOAD_W1},
8487                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8488                         I40E_INSET_FLEX_PAYLOAD_W2},
8489                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8490                         I40E_INSET_FLEX_PAYLOAD_W3},
8491                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8492                         I40E_INSET_FLEX_PAYLOAD_W4},
8493                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8494                         I40E_INSET_FLEX_PAYLOAD_W5},
8495                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8496                         I40E_INSET_FLEX_PAYLOAD_W6},
8497                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8498                         I40E_INSET_FLEX_PAYLOAD_W7},
8499                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8500                         I40E_INSET_FLEX_PAYLOAD_W8},
8501         };
8502
8503         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8504                 return ret;
8505
8506         /* Only one item allowed for default or all */
8507         if (size == 1) {
8508                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8509                         *inset = i40e_get_default_input_set(pctype);
8510                         return 0;
8511                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8512                         *inset = I40E_INSET_NONE;
8513                         return 0;
8514                 }
8515         }
8516
8517         for (i = 0, *inset = 0; i < size; i++) {
8518                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8519                         if (field[i] == inset_convert_table[j].field) {
8520                                 *inset |= inset_convert_table[j].inset;
8521                                 break;
8522                         }
8523                 }
8524
8525                 /* It contains unsupported input set, return immediately */
8526                 if (j == RTE_DIM(inset_convert_table))
8527                         return ret;
8528         }
8529
8530         return 0;
8531 }
8532
8533 /**
8534  * Translate the input set from bit masks to register aware bit masks
8535  * and vice versa
8536  */
8537 uint64_t
8538 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8539 {
8540         uint64_t val = 0;
8541         uint16_t i;
8542
8543         struct inset_map {
8544                 uint64_t inset;
8545                 uint64_t inset_reg;
8546         };
8547
8548         static const struct inset_map inset_map_common[] = {
8549                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8550                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8551                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8552                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8553                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8554                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8555                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8556                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8557                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8558                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8559                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8560                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8561                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8562                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8563                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8564                 {I40E_INSET_TUNNEL_DMAC,
8565                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8566                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8567                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8568                 {I40E_INSET_TUNNEL_SRC_PORT,
8569                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8570                 {I40E_INSET_TUNNEL_DST_PORT,
8571                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8572                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8573                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8574                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8575                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8576                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8577                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8578                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8579                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8580                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8581         };
8582
8583     /* some different registers map in x722*/
8584         static const struct inset_map inset_map_diff_x722[] = {
8585                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8586                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8587                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8588                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8589         };
8590
8591         static const struct inset_map inset_map_diff_not_x722[] = {
8592                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8593                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8594                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8595                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8596         };
8597
8598         if (input == 0)
8599                 return val;
8600
8601         /* Translate input set to register aware inset */
8602         if (type == I40E_MAC_X722) {
8603                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8604                         if (input & inset_map_diff_x722[i].inset)
8605                                 val |= inset_map_diff_x722[i].inset_reg;
8606                 }
8607         } else {
8608                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8609                         if (input & inset_map_diff_not_x722[i].inset)
8610                                 val |= inset_map_diff_not_x722[i].inset_reg;
8611                 }
8612         }
8613
8614         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8615                 if (input & inset_map_common[i].inset)
8616                         val |= inset_map_common[i].inset_reg;
8617         }
8618
8619         return val;
8620 }
8621
8622 int
8623 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8624 {
8625         uint8_t i, idx = 0;
8626         uint64_t inset_need_mask = inset;
8627
8628         static const struct {
8629                 uint64_t inset;
8630                 uint32_t mask;
8631         } inset_mask_map[] = {
8632                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8633                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8634                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8635                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8636                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8637                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8638                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8639                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8640         };
8641
8642         if (!inset || !mask || !nb_elem)
8643                 return 0;
8644
8645         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8646                 /* Clear the inset bit, if no MASK is required,
8647                  * for example proto + ttl
8648                  */
8649                 if ((inset & inset_mask_map[i].inset) ==
8650                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8651                         inset_need_mask &= ~inset_mask_map[i].inset;
8652                 if (!inset_need_mask)
8653                         return 0;
8654         }
8655         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8656                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8657                     inset_mask_map[i].inset) {
8658                         if (idx >= nb_elem) {
8659                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8660                                 return -EINVAL;
8661                         }
8662                         mask[idx] = inset_mask_map[i].mask;
8663                         idx++;
8664                 }
8665         }
8666
8667         return idx;
8668 }
8669
8670 void
8671 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8672 {
8673         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8674
8675         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8676         if (reg != val)
8677                 i40e_write_rx_ctl(hw, addr, val);
8678         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8679                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8680 }
8681
8682 static void
8683 i40e_filter_input_set_init(struct i40e_pf *pf)
8684 {
8685         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8686         enum i40e_filter_pctype pctype;
8687         uint64_t input_set, inset_reg;
8688         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8689         int num, i;
8690         uint16_t flow_type;
8691
8692         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8693              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8694                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8695
8696                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8697                         continue;
8698
8699                 input_set = i40e_get_default_input_set(pctype);
8700
8701                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8702                                                    I40E_INSET_MASK_NUM_REG);
8703                 if (num < 0)
8704                         return;
8705                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8706                                         input_set);
8707
8708                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8709                                       (uint32_t)(inset_reg & UINT32_MAX));
8710                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8711                                      (uint32_t)((inset_reg >>
8712                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8713                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8714                                       (uint32_t)(inset_reg & UINT32_MAX));
8715                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8716                                      (uint32_t)((inset_reg >>
8717                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8718
8719                 for (i = 0; i < num; i++) {
8720                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8721                                              mask_reg[i]);
8722                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8723                                              mask_reg[i]);
8724                 }
8725                 /*clear unused mask registers of the pctype */
8726                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8727                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8728                                              0);
8729                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8730                                              0);
8731                 }
8732                 I40E_WRITE_FLUSH(hw);
8733
8734                 /* store the default input set */
8735                 pf->hash_input_set[pctype] = input_set;
8736                 pf->fdir.input_set[pctype] = input_set;
8737         }
8738 }
8739
8740 int
8741 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8742                          struct rte_eth_input_set_conf *conf)
8743 {
8744         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8745         enum i40e_filter_pctype pctype;
8746         uint64_t input_set, inset_reg = 0;
8747         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8748         int ret, i, num;
8749
8750         if (!conf) {
8751                 PMD_DRV_LOG(ERR, "Invalid pointer");
8752                 return -EFAULT;
8753         }
8754         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8755             conf->op != RTE_ETH_INPUT_SET_ADD) {
8756                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8757                 return -EINVAL;
8758         }
8759
8760         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8761         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8762                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8763                 return -EINVAL;
8764         }
8765
8766         if (hw->mac.type == I40E_MAC_X722) {
8767                 /* get translated pctype value in fd pctype register */
8768                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8769                         I40E_GLQF_FD_PCTYPES((int)pctype));
8770         }
8771
8772         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8773                                    conf->inset_size);
8774         if (ret) {
8775                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8776                 return -EINVAL;
8777         }
8778
8779         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8780                 /* get inset value in register */
8781                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8782                 inset_reg <<= I40E_32_BIT_WIDTH;
8783                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8784                 input_set |= pf->hash_input_set[pctype];
8785         }
8786         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8787                                            I40E_INSET_MASK_NUM_REG);
8788         if (num < 0)
8789                 return -EINVAL;
8790
8791         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8792
8793         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8794                               (uint32_t)(inset_reg & UINT32_MAX));
8795         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8796                              (uint32_t)((inset_reg >>
8797                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8798
8799         for (i = 0; i < num; i++)
8800                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8801                                      mask_reg[i]);
8802         /*clear unused mask registers of the pctype */
8803         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8804                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8805                                      0);
8806         I40E_WRITE_FLUSH(hw);
8807
8808         pf->hash_input_set[pctype] = input_set;
8809         return 0;
8810 }
8811
8812 int
8813 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8814                          struct rte_eth_input_set_conf *conf)
8815 {
8816         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8817         enum i40e_filter_pctype pctype;
8818         uint64_t input_set, inset_reg = 0;
8819         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8820         int ret, i, num;
8821
8822         if (!hw || !conf) {
8823                 PMD_DRV_LOG(ERR, "Invalid pointer");
8824                 return -EFAULT;
8825         }
8826         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8827             conf->op != RTE_ETH_INPUT_SET_ADD) {
8828                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8829                 return -EINVAL;
8830         }
8831
8832         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8833
8834         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8835                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8836                 return -EINVAL;
8837         }
8838
8839         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8840                                    conf->inset_size);
8841         if (ret) {
8842                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8843                 return -EINVAL;
8844         }
8845
8846         /* get inset value in register */
8847         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8848         inset_reg <<= I40E_32_BIT_WIDTH;
8849         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8850
8851         /* Can not change the inset reg for flex payload for fdir,
8852          * it is done by writing I40E_PRTQF_FD_FLXINSET
8853          * in i40e_set_flex_mask_on_pctype.
8854          */
8855         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8856                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8857         else
8858                 input_set |= pf->fdir.input_set[pctype];
8859         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8860                                            I40E_INSET_MASK_NUM_REG);
8861         if (num < 0)
8862                 return -EINVAL;
8863
8864         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8865
8866         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8867                               (uint32_t)(inset_reg & UINT32_MAX));
8868         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8869                              (uint32_t)((inset_reg >>
8870                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8871
8872         for (i = 0; i < num; i++)
8873                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8874                                      mask_reg[i]);
8875         /*clear unused mask registers of the pctype */
8876         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8877                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8878                                      0);
8879         I40E_WRITE_FLUSH(hw);
8880
8881         pf->fdir.input_set[pctype] = input_set;
8882         return 0;
8883 }
8884
8885 static int
8886 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8887 {
8888         int ret = 0;
8889
8890         if (!hw || !info) {
8891                 PMD_DRV_LOG(ERR, "Invalid pointer");
8892                 return -EFAULT;
8893         }
8894
8895         switch (info->info_type) {
8896         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8897                 i40e_get_symmetric_hash_enable_per_port(hw,
8898                                         &(info->info.enable));
8899                 break;
8900         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8901                 ret = i40e_get_hash_filter_global_config(hw,
8902                                 &(info->info.global_conf));
8903                 break;
8904         default:
8905                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8906                                                         info->info_type);
8907                 ret = -EINVAL;
8908                 break;
8909         }
8910
8911         return ret;
8912 }
8913
8914 static int
8915 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8916 {
8917         int ret = 0;
8918
8919         if (!hw || !info) {
8920                 PMD_DRV_LOG(ERR, "Invalid pointer");
8921                 return -EFAULT;
8922         }
8923
8924         switch (info->info_type) {
8925         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8926                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8927                 break;
8928         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8929                 ret = i40e_set_hash_filter_global_config(hw,
8930                                 &(info->info.global_conf));
8931                 break;
8932         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8933                 ret = i40e_hash_filter_inset_select(hw,
8934                                                &(info->info.input_set_conf));
8935                 break;
8936
8937         default:
8938                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8939                                                         info->info_type);
8940                 ret = -EINVAL;
8941                 break;
8942         }
8943
8944         return ret;
8945 }
8946
8947 /* Operations for hash function */
8948 static int
8949 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8950                       enum rte_filter_op filter_op,
8951                       void *arg)
8952 {
8953         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8954         int ret = 0;
8955
8956         switch (filter_op) {
8957         case RTE_ETH_FILTER_NOP:
8958                 break;
8959         case RTE_ETH_FILTER_GET:
8960                 ret = i40e_hash_filter_get(hw,
8961                         (struct rte_eth_hash_filter_info *)arg);
8962                 break;
8963         case RTE_ETH_FILTER_SET:
8964                 ret = i40e_hash_filter_set(hw,
8965                         (struct rte_eth_hash_filter_info *)arg);
8966                 break;
8967         default:
8968                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8969                                                                 filter_op);
8970                 ret = -ENOTSUP;
8971                 break;
8972         }
8973
8974         return ret;
8975 }
8976
8977 /* Convert ethertype filter structure */
8978 static int
8979 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8980                               struct i40e_ethertype_filter *filter)
8981 {
8982         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8983         filter->input.ether_type = input->ether_type;
8984         filter->flags = input->flags;
8985         filter->queue = input->queue;
8986
8987         return 0;
8988 }
8989
8990 /* Check if there exists the ehtertype filter */
8991 struct i40e_ethertype_filter *
8992 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8993                                 const struct i40e_ethertype_filter_input *input)
8994 {
8995         int ret;
8996
8997         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8998         if (ret < 0)
8999                 return NULL;
9000
9001         return ethertype_rule->hash_map[ret];
9002 }
9003
9004 /* Add ethertype filter in SW list */
9005 static int
9006 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9007                                 struct i40e_ethertype_filter *filter)
9008 {
9009         struct i40e_ethertype_rule *rule = &pf->ethertype;
9010         int ret;
9011
9012         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9013         if (ret < 0) {
9014                 PMD_DRV_LOG(ERR,
9015                             "Failed to insert ethertype filter"
9016                             " to hash table %d!",
9017                             ret);
9018                 return ret;
9019         }
9020         rule->hash_map[ret] = filter;
9021
9022         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9023
9024         return 0;
9025 }
9026
9027 /* Delete ethertype filter in SW list */
9028 int
9029 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9030                              struct i40e_ethertype_filter_input *input)
9031 {
9032         struct i40e_ethertype_rule *rule = &pf->ethertype;
9033         struct i40e_ethertype_filter *filter;
9034         int ret;
9035
9036         ret = rte_hash_del_key(rule->hash_table, input);
9037         if (ret < 0) {
9038                 PMD_DRV_LOG(ERR,
9039                             "Failed to delete ethertype filter"
9040                             " to hash table %d!",
9041                             ret);
9042                 return ret;
9043         }
9044         filter = rule->hash_map[ret];
9045         rule->hash_map[ret] = NULL;
9046
9047         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9048         rte_free(filter);
9049
9050         return 0;
9051 }
9052
9053 /*
9054  * Configure ethertype filter, which can director packet by filtering
9055  * with mac address and ether_type or only ether_type
9056  */
9057 int
9058 i40e_ethertype_filter_set(struct i40e_pf *pf,
9059                         struct rte_eth_ethertype_filter *filter,
9060                         bool add)
9061 {
9062         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9063         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9064         struct i40e_ethertype_filter *ethertype_filter, *node;
9065         struct i40e_ethertype_filter check_filter;
9066         struct i40e_control_filter_stats stats;
9067         uint16_t flags = 0;
9068         int ret;
9069
9070         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9071                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9072                 return -EINVAL;
9073         }
9074         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9075                 filter->ether_type == ETHER_TYPE_IPv6) {
9076                 PMD_DRV_LOG(ERR,
9077                         "unsupported ether_type(0x%04x) in control packet filter.",
9078                         filter->ether_type);
9079                 return -EINVAL;
9080         }
9081         if (filter->ether_type == ETHER_TYPE_VLAN)
9082                 PMD_DRV_LOG(WARNING,
9083                         "filter vlan ether_type in first tag is not supported.");
9084
9085         /* Check if there is the filter in SW list */
9086         memset(&check_filter, 0, sizeof(check_filter));
9087         i40e_ethertype_filter_convert(filter, &check_filter);
9088         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9089                                                &check_filter.input);
9090         if (add && node) {
9091                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9092                 return -EINVAL;
9093         }
9094
9095         if (!add && !node) {
9096                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9097                 return -EINVAL;
9098         }
9099
9100         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9101                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9102         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9103                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9104         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9105
9106         memset(&stats, 0, sizeof(stats));
9107         ret = i40e_aq_add_rem_control_packet_filter(hw,
9108                         filter->mac_addr.addr_bytes,
9109                         filter->ether_type, flags,
9110                         pf->main_vsi->seid,
9111                         filter->queue, add, &stats, NULL);
9112
9113         PMD_DRV_LOG(INFO,
9114                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9115                 ret, stats.mac_etype_used, stats.etype_used,
9116                 stats.mac_etype_free, stats.etype_free);
9117         if (ret < 0)
9118                 return -ENOSYS;
9119
9120         /* Add or delete a filter in SW list */
9121         if (add) {
9122                 ethertype_filter = rte_zmalloc("ethertype_filter",
9123                                        sizeof(*ethertype_filter), 0);
9124                 rte_memcpy(ethertype_filter, &check_filter,
9125                            sizeof(check_filter));
9126                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9127         } else {
9128                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9129         }
9130
9131         return ret;
9132 }
9133
9134 /*
9135  * Handle operations for ethertype filter.
9136  */
9137 static int
9138 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9139                                 enum rte_filter_op filter_op,
9140                                 void *arg)
9141 {
9142         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9143         int ret = 0;
9144
9145         if (filter_op == RTE_ETH_FILTER_NOP)
9146                 return ret;
9147
9148         if (arg == NULL) {
9149                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9150                             filter_op);
9151                 return -EINVAL;
9152         }
9153
9154         switch (filter_op) {
9155         case RTE_ETH_FILTER_ADD:
9156                 ret = i40e_ethertype_filter_set(pf,
9157                         (struct rte_eth_ethertype_filter *)arg,
9158                         TRUE);
9159                 break;
9160         case RTE_ETH_FILTER_DELETE:
9161                 ret = i40e_ethertype_filter_set(pf,
9162                         (struct rte_eth_ethertype_filter *)arg,
9163                         FALSE);
9164                 break;
9165         default:
9166                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9167                 ret = -ENOSYS;
9168                 break;
9169         }
9170         return ret;
9171 }
9172
9173 static int
9174 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9175                      enum rte_filter_type filter_type,
9176                      enum rte_filter_op filter_op,
9177                      void *arg)
9178 {
9179         int ret = 0;
9180
9181         if (dev == NULL)
9182                 return -EINVAL;
9183
9184         switch (filter_type) {
9185         case RTE_ETH_FILTER_NONE:
9186                 /* For global configuration */
9187                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9188                 break;
9189         case RTE_ETH_FILTER_HASH:
9190                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9191                 break;
9192         case RTE_ETH_FILTER_MACVLAN:
9193                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9194                 break;
9195         case RTE_ETH_FILTER_ETHERTYPE:
9196                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9197                 break;
9198         case RTE_ETH_FILTER_TUNNEL:
9199                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9200                 break;
9201         case RTE_ETH_FILTER_FDIR:
9202                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9203                 break;
9204         case RTE_ETH_FILTER_GENERIC:
9205                 if (filter_op != RTE_ETH_FILTER_GET)
9206                         return -EINVAL;
9207                 *(const void **)arg = &i40e_flow_ops;
9208                 break;
9209         default:
9210                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9211                                                         filter_type);
9212                 ret = -EINVAL;
9213                 break;
9214         }
9215
9216         return ret;
9217 }
9218
9219 /*
9220  * Check and enable Extended Tag.
9221  * Enabling Extended Tag is important for 40G performance.
9222  */
9223 static void
9224 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9225 {
9226         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9227         uint32_t buf = 0;
9228         int ret;
9229
9230         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9231                                       PCI_DEV_CAP_REG);
9232         if (ret < 0) {
9233                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9234                             PCI_DEV_CAP_REG);
9235                 return;
9236         }
9237         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9238                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9239                 return;
9240         }
9241
9242         buf = 0;
9243         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9244                                       PCI_DEV_CTRL_REG);
9245         if (ret < 0) {
9246                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9247                             PCI_DEV_CTRL_REG);
9248                 return;
9249         }
9250         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9251                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9252                 return;
9253         }
9254         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9255         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9256                                        PCI_DEV_CTRL_REG);
9257         if (ret < 0) {
9258                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9259                             PCI_DEV_CTRL_REG);
9260                 return;
9261         }
9262 }
9263
9264 /*
9265  * As some registers wouldn't be reset unless a global hardware reset,
9266  * hardware initialization is needed to put those registers into an
9267  * expected initial state.
9268  */
9269 static void
9270 i40e_hw_init(struct rte_eth_dev *dev)
9271 {
9272         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9273
9274         i40e_enable_extended_tag(dev);
9275
9276         /* clear the PF Queue Filter control register */
9277         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9278
9279         /* Disable symmetric hash per port */
9280         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9281 }
9282
9283 /*
9284  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9285  * however this function will return only one highest pctype index,
9286  * which is not quite correct. This is known problem of i40e driver
9287  * and needs to be fixed later.
9288  */
9289 enum i40e_filter_pctype
9290 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9291 {
9292         int i;
9293         uint64_t pctype_mask;
9294
9295         if (flow_type < I40E_FLOW_TYPE_MAX) {
9296                 pctype_mask = adapter->pctypes_tbl[flow_type];
9297                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9298                         if (pctype_mask & (1ULL << i))
9299                                 return (enum i40e_filter_pctype)i;
9300                 }
9301         }
9302         return I40E_FILTER_PCTYPE_INVALID;
9303 }
9304
9305 uint16_t
9306 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9307                         enum i40e_filter_pctype pctype)
9308 {
9309         uint16_t flowtype;
9310         uint64_t pctype_mask = 1ULL << pctype;
9311
9312         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9313              flowtype++) {
9314                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9315                         return flowtype;
9316         }
9317
9318         return RTE_ETH_FLOW_UNKNOWN;
9319 }
9320
9321 /*
9322  * On X710, performance number is far from the expectation on recent firmware
9323  * versions; on XL710, performance number is also far from the expectation on
9324  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9325  * mode is enabled and port MAC address is equal to the packet destination MAC
9326  * address. The fix for this issue may not be integrated in the following
9327  * firmware version. So the workaround in software driver is needed. It needs
9328  * to modify the initial values of 3 internal only registers for both X710 and
9329  * XL710. Note that the values for X710 or XL710 could be different, and the
9330  * workaround can be removed when it is fixed in firmware in the future.
9331  */
9332
9333 /* For both X710 and XL710 */
9334 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9335 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x20000200
9336 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9337
9338 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9339 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9340
9341 /* For X722 */
9342 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9343 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9344
9345 /* For X710 */
9346 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9347 /* For XL710 */
9348 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9349 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9350
9351 static int
9352 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9353 {
9354         enum i40e_status_code status;
9355         struct i40e_aq_get_phy_abilities_resp phy_ab;
9356         int ret = -ENOTSUP;
9357         int retries = 0;
9358
9359         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9360                                               NULL);
9361
9362         while (status) {
9363                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9364                         status);
9365                 retries++;
9366                 rte_delay_us(100000);
9367                 if  (retries < 5)
9368                         status = i40e_aq_get_phy_capabilities(hw, false,
9369                                         true, &phy_ab, NULL);
9370                 else
9371                         return ret;
9372         }
9373         return 0;
9374 }
9375
9376 static void
9377 i40e_configure_registers(struct i40e_hw *hw)
9378 {
9379         static struct {
9380                 uint32_t addr;
9381                 uint64_t val;
9382         } reg_table[] = {
9383                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9384                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9385                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9386         };
9387         uint64_t reg;
9388         uint32_t i;
9389         int ret;
9390
9391         for (i = 0; i < RTE_DIM(reg_table); i++) {
9392                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9393                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9394                                 reg_table[i].val =
9395                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9396                         else /* For X710/XL710/XXV710 */
9397                                 if (hw->aq.fw_maj_ver < 6)
9398                                         reg_table[i].val =
9399                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9400                                 else
9401                                         reg_table[i].val =
9402                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9403                 }
9404
9405                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9406                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9407                                 reg_table[i].val =
9408                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9409                         else /* For X710/XL710/XXV710 */
9410                                 reg_table[i].val =
9411                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9412                 }
9413
9414                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9415                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9416                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9417                                 reg_table[i].val =
9418                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9419                         else /* For X710 */
9420                                 reg_table[i].val =
9421                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9422                 }
9423
9424                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9425                                                         &reg, NULL);
9426                 if (ret < 0) {
9427                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9428                                                         reg_table[i].addr);
9429                         break;
9430                 }
9431                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9432                                                 reg_table[i].addr, reg);
9433                 if (reg == reg_table[i].val)
9434                         continue;
9435
9436                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9437                                                 reg_table[i].val, NULL);
9438                 if (ret < 0) {
9439                         PMD_DRV_LOG(ERR,
9440                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9441                                 reg_table[i].val, reg_table[i].addr);
9442                         break;
9443                 }
9444                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9445                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9446         }
9447 }
9448
9449 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9450 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9451 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9452 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9453 static int
9454 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9455 {
9456         uint32_t reg;
9457         int ret;
9458
9459         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9460                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9461                 return -EINVAL;
9462         }
9463
9464         /* Configure for double VLAN RX stripping */
9465         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9466         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9467                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9468                 ret = i40e_aq_debug_write_register(hw,
9469                                                    I40E_VSI_TSR(vsi->vsi_id),
9470                                                    reg, NULL);
9471                 if (ret < 0) {
9472                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9473                                     vsi->vsi_id);
9474                         return I40E_ERR_CONFIG;
9475                 }
9476         }
9477
9478         /* Configure for double VLAN TX insertion */
9479         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9480         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9481                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9482                 ret = i40e_aq_debug_write_register(hw,
9483                                                    I40E_VSI_L2TAGSTXVALID(
9484                                                    vsi->vsi_id), reg, NULL);
9485                 if (ret < 0) {
9486                         PMD_DRV_LOG(ERR,
9487                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9488                                 vsi->vsi_id);
9489                         return I40E_ERR_CONFIG;
9490                 }
9491         }
9492
9493         return 0;
9494 }
9495
9496 /**
9497  * i40e_aq_add_mirror_rule
9498  * @hw: pointer to the hardware structure
9499  * @seid: VEB seid to add mirror rule to
9500  * @dst_id: destination vsi seid
9501  * @entries: Buffer which contains the entities to be mirrored
9502  * @count: number of entities contained in the buffer
9503  * @rule_id:the rule_id of the rule to be added
9504  *
9505  * Add a mirror rule for a given veb.
9506  *
9507  **/
9508 static enum i40e_status_code
9509 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9510                         uint16_t seid, uint16_t dst_id,
9511                         uint16_t rule_type, uint16_t *entries,
9512                         uint16_t count, uint16_t *rule_id)
9513 {
9514         struct i40e_aq_desc desc;
9515         struct i40e_aqc_add_delete_mirror_rule cmd;
9516         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9517                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9518                 &desc.params.raw;
9519         uint16_t buff_len;
9520         enum i40e_status_code status;
9521
9522         i40e_fill_default_direct_cmd_desc(&desc,
9523                                           i40e_aqc_opc_add_mirror_rule);
9524         memset(&cmd, 0, sizeof(cmd));
9525
9526         buff_len = sizeof(uint16_t) * count;
9527         desc.datalen = rte_cpu_to_le_16(buff_len);
9528         if (buff_len > 0)
9529                 desc.flags |= rte_cpu_to_le_16(
9530                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9531         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9532                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9533         cmd.num_entries = rte_cpu_to_le_16(count);
9534         cmd.seid = rte_cpu_to_le_16(seid);
9535         cmd.destination = rte_cpu_to_le_16(dst_id);
9536
9537         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9538         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9539         PMD_DRV_LOG(INFO,
9540                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9541                 hw->aq.asq_last_status, resp->rule_id,
9542                 resp->mirror_rules_used, resp->mirror_rules_free);
9543         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9544
9545         return status;
9546 }
9547
9548 /**
9549  * i40e_aq_del_mirror_rule
9550  * @hw: pointer to the hardware structure
9551  * @seid: VEB seid to add mirror rule to
9552  * @entries: Buffer which contains the entities to be mirrored
9553  * @count: number of entities contained in the buffer
9554  * @rule_id:the rule_id of the rule to be delete
9555  *
9556  * Delete a mirror rule for a given veb.
9557  *
9558  **/
9559 static enum i40e_status_code
9560 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9561                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9562                 uint16_t count, uint16_t rule_id)
9563 {
9564         struct i40e_aq_desc desc;
9565         struct i40e_aqc_add_delete_mirror_rule cmd;
9566         uint16_t buff_len = 0;
9567         enum i40e_status_code status;
9568         void *buff = NULL;
9569
9570         i40e_fill_default_direct_cmd_desc(&desc,
9571                                           i40e_aqc_opc_delete_mirror_rule);
9572         memset(&cmd, 0, sizeof(cmd));
9573         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9574                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9575                                                           I40E_AQ_FLAG_RD));
9576                 cmd.num_entries = count;
9577                 buff_len = sizeof(uint16_t) * count;
9578                 desc.datalen = rte_cpu_to_le_16(buff_len);
9579                 buff = (void *)entries;
9580         } else
9581                 /* rule id is filled in destination field for deleting mirror rule */
9582                 cmd.destination = rte_cpu_to_le_16(rule_id);
9583
9584         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9585                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9586         cmd.seid = rte_cpu_to_le_16(seid);
9587
9588         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9589         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9590
9591         return status;
9592 }
9593
9594 /**
9595  * i40e_mirror_rule_set
9596  * @dev: pointer to the hardware structure
9597  * @mirror_conf: mirror rule info
9598  * @sw_id: mirror rule's sw_id
9599  * @on: enable/disable
9600  *
9601  * set a mirror rule.
9602  *
9603  **/
9604 static int
9605 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9606                         struct rte_eth_mirror_conf *mirror_conf,
9607                         uint8_t sw_id, uint8_t on)
9608 {
9609         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9610         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9611         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9612         struct i40e_mirror_rule *parent = NULL;
9613         uint16_t seid, dst_seid, rule_id;
9614         uint16_t i, j = 0;
9615         int ret;
9616
9617         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9618
9619         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9620                 PMD_DRV_LOG(ERR,
9621                         "mirror rule can not be configured without veb or vfs.");
9622                 return -ENOSYS;
9623         }
9624         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9625                 PMD_DRV_LOG(ERR, "mirror table is full.");
9626                 return -ENOSPC;
9627         }
9628         if (mirror_conf->dst_pool > pf->vf_num) {
9629                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9630                                  mirror_conf->dst_pool);
9631                 return -EINVAL;
9632         }
9633
9634         seid = pf->main_vsi->veb->seid;
9635
9636         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9637                 if (sw_id <= it->index) {
9638                         mirr_rule = it;
9639                         break;
9640                 }
9641                 parent = it;
9642         }
9643         if (mirr_rule && sw_id == mirr_rule->index) {
9644                 if (on) {
9645                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9646                         return -EEXIST;
9647                 } else {
9648                         ret = i40e_aq_del_mirror_rule(hw, seid,
9649                                         mirr_rule->rule_type,
9650                                         mirr_rule->entries,
9651                                         mirr_rule->num_entries, mirr_rule->id);
9652                         if (ret < 0) {
9653                                 PMD_DRV_LOG(ERR,
9654                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9655                                         ret, hw->aq.asq_last_status);
9656                                 return -ENOSYS;
9657                         }
9658                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9659                         rte_free(mirr_rule);
9660                         pf->nb_mirror_rule--;
9661                         return 0;
9662                 }
9663         } else if (!on) {
9664                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9665                 return -ENOENT;
9666         }
9667
9668         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9669                                 sizeof(struct i40e_mirror_rule) , 0);
9670         if (!mirr_rule) {
9671                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9672                 return I40E_ERR_NO_MEMORY;
9673         }
9674         switch (mirror_conf->rule_type) {
9675         case ETH_MIRROR_VLAN:
9676                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9677                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9678                                 mirr_rule->entries[j] =
9679                                         mirror_conf->vlan.vlan_id[i];
9680                                 j++;
9681                         }
9682                 }
9683                 if (j == 0) {
9684                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9685                         rte_free(mirr_rule);
9686                         return -EINVAL;
9687                 }
9688                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9689                 break;
9690         case ETH_MIRROR_VIRTUAL_POOL_UP:
9691         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9692                 /* check if the specified pool bit is out of range */
9693                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9694                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9695                         rte_free(mirr_rule);
9696                         return -EINVAL;
9697                 }
9698                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9699                         if (mirror_conf->pool_mask & (1ULL << i)) {
9700                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9701                                 j++;
9702                         }
9703                 }
9704                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9705                         /* add pf vsi to entries */
9706                         mirr_rule->entries[j] = pf->main_vsi_seid;
9707                         j++;
9708                 }
9709                 if (j == 0) {
9710                         PMD_DRV_LOG(ERR, "pool is not specified.");
9711                         rte_free(mirr_rule);
9712                         return -EINVAL;
9713                 }
9714                 /* egress and ingress in aq commands means from switch but not port */
9715                 mirr_rule->rule_type =
9716                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9717                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9718                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9719                 break;
9720         case ETH_MIRROR_UPLINK_PORT:
9721                 /* egress and ingress in aq commands means from switch but not port*/
9722                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9723                 break;
9724         case ETH_MIRROR_DOWNLINK_PORT:
9725                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9726                 break;
9727         default:
9728                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9729                         mirror_conf->rule_type);
9730                 rte_free(mirr_rule);
9731                 return -EINVAL;
9732         }
9733
9734         /* If the dst_pool is equal to vf_num, consider it as PF */
9735         if (mirror_conf->dst_pool == pf->vf_num)
9736                 dst_seid = pf->main_vsi_seid;
9737         else
9738                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9739
9740         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9741                                       mirr_rule->rule_type, mirr_rule->entries,
9742                                       j, &rule_id);
9743         if (ret < 0) {
9744                 PMD_DRV_LOG(ERR,
9745                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9746                         ret, hw->aq.asq_last_status);
9747                 rte_free(mirr_rule);
9748                 return -ENOSYS;
9749         }
9750
9751         mirr_rule->index = sw_id;
9752         mirr_rule->num_entries = j;
9753         mirr_rule->id = rule_id;
9754         mirr_rule->dst_vsi_seid = dst_seid;
9755
9756         if (parent)
9757                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9758         else
9759                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9760
9761         pf->nb_mirror_rule++;
9762         return 0;
9763 }
9764
9765 /**
9766  * i40e_mirror_rule_reset
9767  * @dev: pointer to the device
9768  * @sw_id: mirror rule's sw_id
9769  *
9770  * reset a mirror rule.
9771  *
9772  **/
9773 static int
9774 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9775 {
9776         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9777         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9778         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9779         uint16_t seid;
9780         int ret;
9781
9782         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9783
9784         seid = pf->main_vsi->veb->seid;
9785
9786         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9787                 if (sw_id == it->index) {
9788                         mirr_rule = it;
9789                         break;
9790                 }
9791         }
9792         if (mirr_rule) {
9793                 ret = i40e_aq_del_mirror_rule(hw, seid,
9794                                 mirr_rule->rule_type,
9795                                 mirr_rule->entries,
9796                                 mirr_rule->num_entries, mirr_rule->id);
9797                 if (ret < 0) {
9798                         PMD_DRV_LOG(ERR,
9799                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9800                                 ret, hw->aq.asq_last_status);
9801                         return -ENOSYS;
9802                 }
9803                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9804                 rte_free(mirr_rule);
9805                 pf->nb_mirror_rule--;
9806         } else {
9807                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9808                 return -ENOENT;
9809         }
9810         return 0;
9811 }
9812
9813 static uint64_t
9814 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9815 {
9816         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9817         uint64_t systim_cycles;
9818
9819         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9820         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9821                         << 32;
9822
9823         return systim_cycles;
9824 }
9825
9826 static uint64_t
9827 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9828 {
9829         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9830         uint64_t rx_tstamp;
9831
9832         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9833         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9834                         << 32;
9835
9836         return rx_tstamp;
9837 }
9838
9839 static uint64_t
9840 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9841 {
9842         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9843         uint64_t tx_tstamp;
9844
9845         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9846         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9847                         << 32;
9848
9849         return tx_tstamp;
9850 }
9851
9852 static void
9853 i40e_start_timecounters(struct rte_eth_dev *dev)
9854 {
9855         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9856         struct i40e_adapter *adapter =
9857                         (struct i40e_adapter *)dev->data->dev_private;
9858         struct rte_eth_link link;
9859         uint32_t tsync_inc_l;
9860         uint32_t tsync_inc_h;
9861
9862         /* Get current link speed. */
9863         memset(&link, 0, sizeof(link));
9864         i40e_dev_link_update(dev, 1);
9865         rte_i40e_dev_atomic_read_link_status(dev, &link);
9866
9867         switch (link.link_speed) {
9868         case ETH_SPEED_NUM_40G:
9869                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9870                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9871                 break;
9872         case ETH_SPEED_NUM_10G:
9873                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9874                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9875                 break;
9876         case ETH_SPEED_NUM_1G:
9877                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9878                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9879                 break;
9880         default:
9881                 tsync_inc_l = 0x0;
9882                 tsync_inc_h = 0x0;
9883         }
9884
9885         /* Set the timesync increment value. */
9886         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9887         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9888
9889         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9890         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9891         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9892
9893         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9894         adapter->systime_tc.cc_shift = 0;
9895         adapter->systime_tc.nsec_mask = 0;
9896
9897         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9898         adapter->rx_tstamp_tc.cc_shift = 0;
9899         adapter->rx_tstamp_tc.nsec_mask = 0;
9900
9901         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9902         adapter->tx_tstamp_tc.cc_shift = 0;
9903         adapter->tx_tstamp_tc.nsec_mask = 0;
9904 }
9905
9906 static int
9907 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9908 {
9909         struct i40e_adapter *adapter =
9910                         (struct i40e_adapter *)dev->data->dev_private;
9911
9912         adapter->systime_tc.nsec += delta;
9913         adapter->rx_tstamp_tc.nsec += delta;
9914         adapter->tx_tstamp_tc.nsec += delta;
9915
9916         return 0;
9917 }
9918
9919 static int
9920 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9921 {
9922         uint64_t ns;
9923         struct i40e_adapter *adapter =
9924                         (struct i40e_adapter *)dev->data->dev_private;
9925
9926         ns = rte_timespec_to_ns(ts);
9927
9928         /* Set the timecounters to a new value. */
9929         adapter->systime_tc.nsec = ns;
9930         adapter->rx_tstamp_tc.nsec = ns;
9931         adapter->tx_tstamp_tc.nsec = ns;
9932
9933         return 0;
9934 }
9935
9936 static int
9937 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9938 {
9939         uint64_t ns, systime_cycles;
9940         struct i40e_adapter *adapter =
9941                         (struct i40e_adapter *)dev->data->dev_private;
9942
9943         systime_cycles = i40e_read_systime_cyclecounter(dev);
9944         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9945         *ts = rte_ns_to_timespec(ns);
9946
9947         return 0;
9948 }
9949
9950 static int
9951 i40e_timesync_enable(struct rte_eth_dev *dev)
9952 {
9953         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9954         uint32_t tsync_ctl_l;
9955         uint32_t tsync_ctl_h;
9956
9957         /* Stop the timesync system time. */
9958         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9959         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9960         /* Reset the timesync system time value. */
9961         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9962         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9963
9964         i40e_start_timecounters(dev);
9965
9966         /* Clear timesync registers. */
9967         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9968         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9969         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9970         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9971         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9972         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9973
9974         /* Enable timestamping of PTP packets. */
9975         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9976         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9977
9978         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9979         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9980         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9981
9982         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9983         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9984
9985         return 0;
9986 }
9987
9988 static int
9989 i40e_timesync_disable(struct rte_eth_dev *dev)
9990 {
9991         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9992         uint32_t tsync_ctl_l;
9993         uint32_t tsync_ctl_h;
9994
9995         /* Disable timestamping of transmitted PTP packets. */
9996         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9997         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9998
9999         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10000         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10001
10002         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10003         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10004
10005         /* Reset the timesync increment value. */
10006         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10007         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10008
10009         return 0;
10010 }
10011
10012 static int
10013 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10014                                 struct timespec *timestamp, uint32_t flags)
10015 {
10016         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10017         struct i40e_adapter *adapter =
10018                 (struct i40e_adapter *)dev->data->dev_private;
10019
10020         uint32_t sync_status;
10021         uint32_t index = flags & 0x03;
10022         uint64_t rx_tstamp_cycles;
10023         uint64_t ns;
10024
10025         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10026         if ((sync_status & (1 << index)) == 0)
10027                 return -EINVAL;
10028
10029         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10030         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10031         *timestamp = rte_ns_to_timespec(ns);
10032
10033         return 0;
10034 }
10035
10036 static int
10037 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10038                                 struct timespec *timestamp)
10039 {
10040         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10041         struct i40e_adapter *adapter =
10042                 (struct i40e_adapter *)dev->data->dev_private;
10043
10044         uint32_t sync_status;
10045         uint64_t tx_tstamp_cycles;
10046         uint64_t ns;
10047
10048         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10049         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10050                 return -EINVAL;
10051
10052         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10053         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10054         *timestamp = rte_ns_to_timespec(ns);
10055
10056         return 0;
10057 }
10058
10059 /*
10060  * i40e_parse_dcb_configure - parse dcb configure from user
10061  * @dev: the device being configured
10062  * @dcb_cfg: pointer of the result of parse
10063  * @*tc_map: bit map of enabled traffic classes
10064  *
10065  * Returns 0 on success, negative value on failure
10066  */
10067 static int
10068 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10069                          struct i40e_dcbx_config *dcb_cfg,
10070                          uint8_t *tc_map)
10071 {
10072         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10073         uint8_t i, tc_bw, bw_lf;
10074
10075         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10076
10077         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10078         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10079                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10080                 return -EINVAL;
10081         }
10082
10083         /* assume each tc has the same bw */
10084         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10085         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10086                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10087         /* to ensure the sum of tcbw is equal to 100 */
10088         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10089         for (i = 0; i < bw_lf; i++)
10090                 dcb_cfg->etscfg.tcbwtable[i]++;
10091
10092         /* assume each tc has the same Transmission Selection Algorithm */
10093         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10094                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10095
10096         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10097                 dcb_cfg->etscfg.prioritytable[i] =
10098                                 dcb_rx_conf->dcb_tc[i];
10099
10100         /* FW needs one App to configure HW */
10101         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10102         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10103         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10104         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10105
10106         if (dcb_rx_conf->nb_tcs == 0)
10107                 *tc_map = 1; /* tc0 only */
10108         else
10109                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10110
10111         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10112                 dcb_cfg->pfc.willing = 0;
10113                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10114                 dcb_cfg->pfc.pfcenable = *tc_map;
10115         }
10116         return 0;
10117 }
10118
10119
10120 static enum i40e_status_code
10121 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10122                               struct i40e_aqc_vsi_properties_data *info,
10123                               uint8_t enabled_tcmap)
10124 {
10125         enum i40e_status_code ret;
10126         int i, total_tc = 0;
10127         uint16_t qpnum_per_tc, bsf, qp_idx;
10128         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10129         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10130         uint16_t used_queues;
10131
10132         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10133         if (ret != I40E_SUCCESS)
10134                 return ret;
10135
10136         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10137                 if (enabled_tcmap & (1 << i))
10138                         total_tc++;
10139         }
10140         if (total_tc == 0)
10141                 total_tc = 1;
10142         vsi->enabled_tc = enabled_tcmap;
10143
10144         /* different VSI has different queues assigned */
10145         if (vsi->type == I40E_VSI_MAIN)
10146                 used_queues = dev_data->nb_rx_queues -
10147                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10148         else if (vsi->type == I40E_VSI_VMDQ2)
10149                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10150         else {
10151                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10152                 return I40E_ERR_NO_AVAILABLE_VSI;
10153         }
10154
10155         qpnum_per_tc = used_queues / total_tc;
10156         /* Number of queues per enabled TC */
10157         if (qpnum_per_tc == 0) {
10158                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10159                 return I40E_ERR_INVALID_QP_ID;
10160         }
10161         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10162                                 I40E_MAX_Q_PER_TC);
10163         bsf = rte_bsf32(qpnum_per_tc);
10164
10165         /**
10166          * Configure TC and queue mapping parameters, for enabled TC,
10167          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10168          * default queue will serve it.
10169          */
10170         qp_idx = 0;
10171         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10172                 if (vsi->enabled_tc & (1 << i)) {
10173                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10174                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10175                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10176                         qp_idx += qpnum_per_tc;
10177                 } else
10178                         info->tc_mapping[i] = 0;
10179         }
10180
10181         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10182         if (vsi->type == I40E_VSI_SRIOV) {
10183                 info->mapping_flags |=
10184                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10185                 for (i = 0; i < vsi->nb_qps; i++)
10186                         info->queue_mapping[i] =
10187                                 rte_cpu_to_le_16(vsi->base_queue + i);
10188         } else {
10189                 info->mapping_flags |=
10190                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10191                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10192         }
10193         info->valid_sections |=
10194                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10195
10196         return I40E_SUCCESS;
10197 }
10198
10199 /*
10200  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10201  * @veb: VEB to be configured
10202  * @tc_map: enabled TC bitmap
10203  *
10204  * Returns 0 on success, negative value on failure
10205  */
10206 static enum i40e_status_code
10207 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10208 {
10209         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10210         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10211         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10212         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10213         enum i40e_status_code ret = I40E_SUCCESS;
10214         int i;
10215         uint32_t bw_max;
10216
10217         /* Check if enabled_tc is same as existing or new TCs */
10218         if (veb->enabled_tc == tc_map)
10219                 return ret;
10220
10221         /* configure tc bandwidth */
10222         memset(&veb_bw, 0, sizeof(veb_bw));
10223         veb_bw.tc_valid_bits = tc_map;
10224         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10225         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10226                 if (tc_map & BIT_ULL(i))
10227                         veb_bw.tc_bw_share_credits[i] = 1;
10228         }
10229         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10230                                                    &veb_bw, NULL);
10231         if (ret) {
10232                 PMD_INIT_LOG(ERR,
10233                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10234                         hw->aq.asq_last_status);
10235                 return ret;
10236         }
10237
10238         memset(&ets_query, 0, sizeof(ets_query));
10239         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10240                                                    &ets_query, NULL);
10241         if (ret != I40E_SUCCESS) {
10242                 PMD_DRV_LOG(ERR,
10243                         "Failed to get switch_comp ETS configuration %u",
10244                         hw->aq.asq_last_status);
10245                 return ret;
10246         }
10247         memset(&bw_query, 0, sizeof(bw_query));
10248         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10249                                                   &bw_query, NULL);
10250         if (ret != I40E_SUCCESS) {
10251                 PMD_DRV_LOG(ERR,
10252                         "Failed to get switch_comp bandwidth configuration %u",
10253                         hw->aq.asq_last_status);
10254                 return ret;
10255         }
10256
10257         /* store and print out BW info */
10258         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10259         veb->bw_info.bw_max = ets_query.tc_bw_max;
10260         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10261         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10262         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10263                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10264                      I40E_16_BIT_WIDTH);
10265         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10266                 veb->bw_info.bw_ets_share_credits[i] =
10267                                 bw_query.tc_bw_share_credits[i];
10268                 veb->bw_info.bw_ets_credits[i] =
10269                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10270                 /* 4 bits per TC, 4th bit is reserved */
10271                 veb->bw_info.bw_ets_max[i] =
10272                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10273                                   RTE_LEN2MASK(3, uint8_t));
10274                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10275                             veb->bw_info.bw_ets_share_credits[i]);
10276                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10277                             veb->bw_info.bw_ets_credits[i]);
10278                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10279                             veb->bw_info.bw_ets_max[i]);
10280         }
10281
10282         veb->enabled_tc = tc_map;
10283
10284         return ret;
10285 }
10286
10287
10288 /*
10289  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10290  * @vsi: VSI to be configured
10291  * @tc_map: enabled TC bitmap
10292  *
10293  * Returns 0 on success, negative value on failure
10294  */
10295 static enum i40e_status_code
10296 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10297 {
10298         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10299         struct i40e_vsi_context ctxt;
10300         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10301         enum i40e_status_code ret = I40E_SUCCESS;
10302         int i;
10303
10304         /* Check if enabled_tc is same as existing or new TCs */
10305         if (vsi->enabled_tc == tc_map)
10306                 return ret;
10307
10308         /* configure tc bandwidth */
10309         memset(&bw_data, 0, sizeof(bw_data));
10310         bw_data.tc_valid_bits = tc_map;
10311         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10312         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10313                 if (tc_map & BIT_ULL(i))
10314                         bw_data.tc_bw_credits[i] = 1;
10315         }
10316         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10317         if (ret) {
10318                 PMD_INIT_LOG(ERR,
10319                         "AQ command Config VSI BW allocation per TC failed = %d",
10320                         hw->aq.asq_last_status);
10321                 goto out;
10322         }
10323         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10324                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10325
10326         /* Update Queue Pairs Mapping for currently enabled UPs */
10327         ctxt.seid = vsi->seid;
10328         ctxt.pf_num = hw->pf_id;
10329         ctxt.vf_num = 0;
10330         ctxt.uplink_seid = vsi->uplink_seid;
10331         ctxt.info = vsi->info;
10332         i40e_get_cap(hw);
10333         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10334         if (ret)
10335                 goto out;
10336
10337         /* Update the VSI after updating the VSI queue-mapping information */
10338         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10339         if (ret) {
10340                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10341                         hw->aq.asq_last_status);
10342                 goto out;
10343         }
10344         /* update the local VSI info with updated queue map */
10345         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10346                                         sizeof(vsi->info.tc_mapping));
10347         rte_memcpy(&vsi->info.queue_mapping,
10348                         &ctxt.info.queue_mapping,
10349                 sizeof(vsi->info.queue_mapping));
10350         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10351         vsi->info.valid_sections = 0;
10352
10353         /* query and update current VSI BW information */
10354         ret = i40e_vsi_get_bw_config(vsi);
10355         if (ret) {
10356                 PMD_INIT_LOG(ERR,
10357                          "Failed updating vsi bw info, err %s aq_err %s",
10358                          i40e_stat_str(hw, ret),
10359                          i40e_aq_str(hw, hw->aq.asq_last_status));
10360                 goto out;
10361         }
10362
10363         vsi->enabled_tc = tc_map;
10364
10365 out:
10366         return ret;
10367 }
10368
10369 /*
10370  * i40e_dcb_hw_configure - program the dcb setting to hw
10371  * @pf: pf the configuration is taken on
10372  * @new_cfg: new configuration
10373  * @tc_map: enabled TC bitmap
10374  *
10375  * Returns 0 on success, negative value on failure
10376  */
10377 static enum i40e_status_code
10378 i40e_dcb_hw_configure(struct i40e_pf *pf,
10379                       struct i40e_dcbx_config *new_cfg,
10380                       uint8_t tc_map)
10381 {
10382         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10383         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10384         struct i40e_vsi *main_vsi = pf->main_vsi;
10385         struct i40e_vsi_list *vsi_list;
10386         enum i40e_status_code ret;
10387         int i;
10388         uint32_t val;
10389
10390         /* Use the FW API if FW > v4.4*/
10391         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10392               (hw->aq.fw_maj_ver >= 5))) {
10393                 PMD_INIT_LOG(ERR,
10394                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10395                 return I40E_ERR_FIRMWARE_API_VERSION;
10396         }
10397
10398         /* Check if need reconfiguration */
10399         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10400                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10401                 return I40E_SUCCESS;
10402         }
10403
10404         /* Copy the new config to the current config */
10405         *old_cfg = *new_cfg;
10406         old_cfg->etsrec = old_cfg->etscfg;
10407         ret = i40e_set_dcb_config(hw);
10408         if (ret) {
10409                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10410                          i40e_stat_str(hw, ret),
10411                          i40e_aq_str(hw, hw->aq.asq_last_status));
10412                 return ret;
10413         }
10414         /* set receive Arbiter to RR mode and ETS scheme by default */
10415         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10416                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10417                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10418                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10419                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10420                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10421                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10422                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10423                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10424                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10425                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10426                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10427                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10428         }
10429         /* get local mib to check whether it is configured correctly */
10430         /* IEEE mode */
10431         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10432         /* Get Local DCB Config */
10433         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10434                                      &hw->local_dcbx_config);
10435
10436         /* if Veb is created, need to update TC of it at first */
10437         if (main_vsi->veb) {
10438                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10439                 if (ret)
10440                         PMD_INIT_LOG(WARNING,
10441                                  "Failed configuring TC for VEB seid=%d",
10442                                  main_vsi->veb->seid);
10443         }
10444         /* Update each VSI */
10445         i40e_vsi_config_tc(main_vsi, tc_map);
10446         if (main_vsi->veb) {
10447                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10448                         /* Beside main VSI and VMDQ VSIs, only enable default
10449                          * TC for other VSIs
10450                          */
10451                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10452                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10453                                                          tc_map);
10454                         else
10455                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10456                                                          I40E_DEFAULT_TCMAP);
10457                         if (ret)
10458                                 PMD_INIT_LOG(WARNING,
10459                                         "Failed configuring TC for VSI seid=%d",
10460                                         vsi_list->vsi->seid);
10461                         /* continue */
10462                 }
10463         }
10464         return I40E_SUCCESS;
10465 }
10466
10467 /*
10468  * i40e_dcb_init_configure - initial dcb config
10469  * @dev: device being configured
10470  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10471  *
10472  * Returns 0 on success, negative value on failure
10473  */
10474 static int
10475 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10476 {
10477         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10478         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10479         int i, ret = 0;
10480
10481         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10482                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10483                 return -ENOTSUP;
10484         }
10485
10486         /* DCB initialization:
10487          * Update DCB configuration from the Firmware and configure
10488          * LLDP MIB change event.
10489          */
10490         if (sw_dcb == TRUE) {
10491                 ret = i40e_init_dcb(hw);
10492                 /* If lldp agent is stopped, the return value from
10493                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10494                  * adminq status. Otherwise, it should return success.
10495                  */
10496                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10497                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10498                         memset(&hw->local_dcbx_config, 0,
10499                                 sizeof(struct i40e_dcbx_config));
10500                         /* set dcb default configuration */
10501                         hw->local_dcbx_config.etscfg.willing = 0;
10502                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10503                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10504                         hw->local_dcbx_config.etscfg.tsatable[0] =
10505                                                 I40E_IEEE_TSA_ETS;
10506                         /* all UPs mapping to TC0 */
10507                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10508                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10509                         hw->local_dcbx_config.etsrec =
10510                                 hw->local_dcbx_config.etscfg;
10511                         hw->local_dcbx_config.pfc.willing = 0;
10512                         hw->local_dcbx_config.pfc.pfccap =
10513                                                 I40E_MAX_TRAFFIC_CLASS;
10514                         /* FW needs one App to configure HW */
10515                         hw->local_dcbx_config.numapps = 1;
10516                         hw->local_dcbx_config.app[0].selector =
10517                                                 I40E_APP_SEL_ETHTYPE;
10518                         hw->local_dcbx_config.app[0].priority = 3;
10519                         hw->local_dcbx_config.app[0].protocolid =
10520                                                 I40E_APP_PROTOID_FCOE;
10521                         ret = i40e_set_dcb_config(hw);
10522                         if (ret) {
10523                                 PMD_INIT_LOG(ERR,
10524                                         "default dcb config fails. err = %d, aq_err = %d.",
10525                                         ret, hw->aq.asq_last_status);
10526                                 return -ENOSYS;
10527                         }
10528                 } else {
10529                         PMD_INIT_LOG(ERR,
10530                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10531                                 ret, hw->aq.asq_last_status);
10532                         return -ENOTSUP;
10533                 }
10534         } else {
10535                 ret = i40e_aq_start_lldp(hw, NULL);
10536                 if (ret != I40E_SUCCESS)
10537                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10538
10539                 ret = i40e_init_dcb(hw);
10540                 if (!ret) {
10541                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10542                                 PMD_INIT_LOG(ERR,
10543                                         "HW doesn't support DCBX offload.");
10544                                 return -ENOTSUP;
10545                         }
10546                 } else {
10547                         PMD_INIT_LOG(ERR,
10548                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10549                                 ret, hw->aq.asq_last_status);
10550                         return -ENOTSUP;
10551                 }
10552         }
10553         return 0;
10554 }
10555
10556 /*
10557  * i40e_dcb_setup - setup dcb related config
10558  * @dev: device being configured
10559  *
10560  * Returns 0 on success, negative value on failure
10561  */
10562 static int
10563 i40e_dcb_setup(struct rte_eth_dev *dev)
10564 {
10565         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10566         struct i40e_dcbx_config dcb_cfg;
10567         uint8_t tc_map = 0;
10568         int ret = 0;
10569
10570         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10571                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10572                 return -ENOTSUP;
10573         }
10574
10575         if (pf->vf_num != 0)
10576                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10577
10578         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10579         if (ret) {
10580                 PMD_INIT_LOG(ERR, "invalid dcb config");
10581                 return -EINVAL;
10582         }
10583         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10584         if (ret) {
10585                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10586                 return -ENOSYS;
10587         }
10588
10589         return 0;
10590 }
10591
10592 static int
10593 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10594                       struct rte_eth_dcb_info *dcb_info)
10595 {
10596         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10597         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10598         struct i40e_vsi *vsi = pf->main_vsi;
10599         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10600         uint16_t bsf, tc_mapping;
10601         int i, j = 0;
10602
10603         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10604                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10605         else
10606                 dcb_info->nb_tcs = 1;
10607         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10608                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10609         for (i = 0; i < dcb_info->nb_tcs; i++)
10610                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10611
10612         /* get queue mapping if vmdq is disabled */
10613         if (!pf->nb_cfg_vmdq_vsi) {
10614                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10615                         if (!(vsi->enabled_tc & (1 << i)))
10616                                 continue;
10617                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10618                         dcb_info->tc_queue.tc_rxq[j][i].base =
10619                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10620                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10621                         dcb_info->tc_queue.tc_txq[j][i].base =
10622                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10623                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10624                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10625                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10626                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10627                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10628                 }
10629                 return 0;
10630         }
10631
10632         /* get queue mapping if vmdq is enabled */
10633         do {
10634                 vsi = pf->vmdq[j].vsi;
10635                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10636                         if (!(vsi->enabled_tc & (1 << i)))
10637                                 continue;
10638                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10639                         dcb_info->tc_queue.tc_rxq[j][i].base =
10640                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10641                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10642                         dcb_info->tc_queue.tc_txq[j][i].base =
10643                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10644                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10645                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10646                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10647                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10648                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10649                 }
10650                 j++;
10651         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10652         return 0;
10653 }
10654
10655 static int
10656 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10657 {
10658         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10659         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10660         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10661         uint16_t interval =
10662                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10663         uint16_t msix_intr;
10664
10665         msix_intr = intr_handle->intr_vec[queue_id];
10666         if (msix_intr == I40E_MISC_VEC_ID)
10667                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10668                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10669                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10670                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10671                                (interval <<
10672                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10673         else
10674                 I40E_WRITE_REG(hw,
10675                                I40E_PFINT_DYN_CTLN(msix_intr -
10676                                                    I40E_RX_VEC_START),
10677                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10678                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10679                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10680                                (interval <<
10681                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10682
10683         I40E_WRITE_FLUSH(hw);
10684         rte_intr_enable(&pci_dev->intr_handle);
10685
10686         return 0;
10687 }
10688
10689 static int
10690 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10691 {
10692         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10693         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10694         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10695         uint16_t msix_intr;
10696
10697         msix_intr = intr_handle->intr_vec[queue_id];
10698         if (msix_intr == I40E_MISC_VEC_ID)
10699                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10700         else
10701                 I40E_WRITE_REG(hw,
10702                                I40E_PFINT_DYN_CTLN(msix_intr -
10703                                                    I40E_RX_VEC_START),
10704                                0);
10705         I40E_WRITE_FLUSH(hw);
10706
10707         return 0;
10708 }
10709
10710 static int i40e_get_regs(struct rte_eth_dev *dev,
10711                          struct rte_dev_reg_info *regs)
10712 {
10713         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10714         uint32_t *ptr_data = regs->data;
10715         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10716         const struct i40e_reg_info *reg_info;
10717
10718         if (ptr_data == NULL) {
10719                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10720                 regs->width = sizeof(uint32_t);
10721                 return 0;
10722         }
10723
10724         /* The first few registers have to be read using AQ operations */
10725         reg_idx = 0;
10726         while (i40e_regs_adminq[reg_idx].name) {
10727                 reg_info = &i40e_regs_adminq[reg_idx++];
10728                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10729                         for (arr_idx2 = 0;
10730                                         arr_idx2 <= reg_info->count2;
10731                                         arr_idx2++) {
10732                                 reg_offset = arr_idx * reg_info->stride1 +
10733                                         arr_idx2 * reg_info->stride2;
10734                                 reg_offset += reg_info->base_addr;
10735                                 ptr_data[reg_offset >> 2] =
10736                                         i40e_read_rx_ctl(hw, reg_offset);
10737                         }
10738         }
10739
10740         /* The remaining registers can be read using primitives */
10741         reg_idx = 0;
10742         while (i40e_regs_others[reg_idx].name) {
10743                 reg_info = &i40e_regs_others[reg_idx++];
10744                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10745                         for (arr_idx2 = 0;
10746                                         arr_idx2 <= reg_info->count2;
10747                                         arr_idx2++) {
10748                                 reg_offset = arr_idx * reg_info->stride1 +
10749                                         arr_idx2 * reg_info->stride2;
10750                                 reg_offset += reg_info->base_addr;
10751                                 ptr_data[reg_offset >> 2] =
10752                                         I40E_READ_REG(hw, reg_offset);
10753                         }
10754         }
10755
10756         return 0;
10757 }
10758
10759 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10760 {
10761         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10762
10763         /* Convert word count to byte count */
10764         return hw->nvm.sr_size << 1;
10765 }
10766
10767 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10768                            struct rte_dev_eeprom_info *eeprom)
10769 {
10770         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10771         uint16_t *data = eeprom->data;
10772         uint16_t offset, length, cnt_words;
10773         int ret_code;
10774
10775         offset = eeprom->offset >> 1;
10776         length = eeprom->length >> 1;
10777         cnt_words = length;
10778
10779         if (offset > hw->nvm.sr_size ||
10780                 offset + length > hw->nvm.sr_size) {
10781                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10782                 return -EINVAL;
10783         }
10784
10785         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10786
10787         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10788         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10789                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10790                 return -EIO;
10791         }
10792
10793         return 0;
10794 }
10795
10796 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10797                                       struct ether_addr *mac_addr)
10798 {
10799         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10800
10801         if (!is_valid_assigned_ether_addr(mac_addr)) {
10802                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10803                 return;
10804         }
10805
10806         /* Flags: 0x3 updates port address */
10807         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10808 }
10809
10810 static int
10811 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10812 {
10813         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10814         struct rte_eth_dev_data *dev_data = pf->dev_data;
10815         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10816         int ret = 0;
10817
10818         /* check if mtu is within the allowed range */
10819         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10820                 return -EINVAL;
10821
10822         /* mtu setting is forbidden if port is start */
10823         if (dev_data->dev_started) {
10824                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10825                             dev_data->port_id);
10826                 return -EBUSY;
10827         }
10828
10829         if (frame_size > ETHER_MAX_LEN)
10830                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10831         else
10832                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10833
10834         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10835
10836         return ret;
10837 }
10838
10839 /* Restore ethertype filter */
10840 static void
10841 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10842 {
10843         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10844         struct i40e_ethertype_filter_list
10845                 *ethertype_list = &pf->ethertype.ethertype_list;
10846         struct i40e_ethertype_filter *f;
10847         struct i40e_control_filter_stats stats;
10848         uint16_t flags;
10849
10850         TAILQ_FOREACH(f, ethertype_list, rules) {
10851                 flags = 0;
10852                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10853                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10854                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10855                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10856                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10857
10858                 memset(&stats, 0, sizeof(stats));
10859                 i40e_aq_add_rem_control_packet_filter(hw,
10860                                             f->input.mac_addr.addr_bytes,
10861                                             f->input.ether_type,
10862                                             flags, pf->main_vsi->seid,
10863                                             f->queue, 1, &stats, NULL);
10864         }
10865         PMD_DRV_LOG(INFO, "Ethertype filter:"
10866                     " mac_etype_used = %u, etype_used = %u,"
10867                     " mac_etype_free = %u, etype_free = %u",
10868                     stats.mac_etype_used, stats.etype_used,
10869                     stats.mac_etype_free, stats.etype_free);
10870 }
10871
10872 /* Restore tunnel filter */
10873 static void
10874 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10875 {
10876         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10877         struct i40e_vsi *vsi;
10878         struct i40e_pf_vf *vf;
10879         struct i40e_tunnel_filter_list
10880                 *tunnel_list = &pf->tunnel.tunnel_list;
10881         struct i40e_tunnel_filter *f;
10882         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10883         bool big_buffer = 0;
10884
10885         TAILQ_FOREACH(f, tunnel_list, rules) {
10886                 if (!f->is_to_vf)
10887                         vsi = pf->main_vsi;
10888                 else {
10889                         vf = &pf->vfs[f->vf_id];
10890                         vsi = vf->vsi;
10891                 }
10892                 memset(&cld_filter, 0, sizeof(cld_filter));
10893                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10894                         (struct ether_addr *)&cld_filter.element.outer_mac);
10895                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10896                         (struct ether_addr *)&cld_filter.element.inner_mac);
10897                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10898                 cld_filter.element.flags = f->input.flags;
10899                 cld_filter.element.tenant_id = f->input.tenant_id;
10900                 cld_filter.element.queue_number = f->queue;
10901                 rte_memcpy(cld_filter.general_fields,
10902                            f->input.general_fields,
10903                            sizeof(f->input.general_fields));
10904
10905                 if (((f->input.flags &
10906                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
10907                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
10908                     ((f->input.flags &
10909                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
10910                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
10911                     ((f->input.flags &
10912                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
10913                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
10914                         big_buffer = 1;
10915
10916                 if (big_buffer)
10917                         i40e_aq_add_cloud_filters_big_buffer(hw,
10918                                              vsi->seid, &cld_filter, 1);
10919                 else
10920                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10921                                                   &cld_filter.element, 1);
10922         }
10923 }
10924
10925 static void
10926 i40e_filter_restore(struct i40e_pf *pf)
10927 {
10928         i40e_ethertype_filter_restore(pf);
10929         i40e_tunnel_filter_restore(pf);
10930         i40e_fdir_filter_restore(pf);
10931 }
10932
10933 static bool
10934 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10935 {
10936         if (strcmp(dev->device->driver->name, drv->driver.name))
10937                 return false;
10938
10939         return true;
10940 }
10941
10942 bool
10943 is_i40e_supported(struct rte_eth_dev *dev)
10944 {
10945         return is_device_supported(dev, &rte_i40e_pmd);
10946 }
10947
10948 struct i40e_customized_pctype*
10949 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
10950 {
10951         int i;
10952
10953         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
10954                 if (pf->customized_pctype[i].index == index)
10955                         return &pf->customized_pctype[i];
10956         }
10957         return NULL;
10958 }
10959
10960 static int
10961 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
10962                               uint32_t pkg_size, uint32_t proto_num,
10963                               struct rte_pmd_i40e_proto_info *proto)
10964 {
10965         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10966         uint32_t pctype_num;
10967         struct rte_pmd_i40e_ptype_info *pctype;
10968         uint32_t buff_size;
10969         struct i40e_customized_pctype *new_pctype = NULL;
10970         uint8_t proto_id;
10971         uint8_t pctype_value;
10972         char name[64];
10973         uint32_t i, j, n;
10974         int ret;
10975
10976         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
10977                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
10978                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
10979         if (ret) {
10980                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
10981                 return -1;
10982         }
10983         if (!pctype_num) {
10984                 PMD_DRV_LOG(INFO, "No new pctype added");
10985                 return -1;
10986         }
10987
10988         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
10989         pctype = rte_zmalloc("new_pctype", buff_size, 0);
10990         if (!pctype) {
10991                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
10992                 return -1;
10993         }
10994         /* get information about new pctype list */
10995         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
10996                                         (uint8_t *)pctype, buff_size,
10997                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
10998         if (ret) {
10999                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11000                 rte_free(pctype);
11001                 return -1;
11002         }
11003
11004         /* Update customized pctype. */
11005         for (i = 0; i < pctype_num; i++) {
11006                 pctype_value = pctype[i].ptype_id;
11007                 memset(name, 0, sizeof(name));
11008                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11009                         proto_id = pctype[i].protocols[j];
11010                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11011                                 continue;
11012                         for (n = 0; n < proto_num; n++) {
11013                                 if (proto[n].proto_id != proto_id)
11014                                         continue;
11015                                 strcat(name, proto[n].name);
11016                                 strcat(name, "_");
11017                                 break;
11018                         }
11019                 }
11020                 name[strlen(name) - 1] = '\0';
11021                 if (!strcmp(name, "GTPC"))
11022                         new_pctype =
11023                                 i40e_find_customized_pctype(pf,
11024                                                       I40E_CUSTOMIZED_GTPC);
11025                 else if (!strcmp(name, "GTPU_IPV4"))
11026                         new_pctype =
11027                                 i40e_find_customized_pctype(pf,
11028                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11029                 else if (!strcmp(name, "GTPU_IPV6"))
11030                         new_pctype =
11031                                 i40e_find_customized_pctype(pf,
11032                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11033                 else if (!strcmp(name, "GTPU"))
11034                         new_pctype =
11035                                 i40e_find_customized_pctype(pf,
11036                                                       I40E_CUSTOMIZED_GTPU);
11037                 if (new_pctype) {
11038                         new_pctype->pctype = pctype_value;
11039                         new_pctype->valid = true;
11040                 }
11041         }
11042
11043         rte_free(pctype);
11044         return 0;
11045 }
11046
11047 static int
11048 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11049                                uint32_t pkg_size, uint32_t proto_num,
11050                                struct rte_pmd_i40e_proto_info *proto)
11051 {
11052         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11053         uint8_t port_id = dev->data->port_id;
11054         uint32_t ptype_num;
11055         struct rte_pmd_i40e_ptype_info *ptype;
11056         uint32_t buff_size;
11057         uint8_t proto_id;
11058         char name[16];
11059         uint32_t i, j, n;
11060         bool inner_ip;
11061         int ret;
11062
11063         /* get information about new ptype num */
11064         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11065                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11066                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11067         if (ret) {
11068                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11069                 return ret;
11070         }
11071         if (!ptype_num) {
11072                 PMD_DRV_LOG(INFO, "No new ptype added");
11073                 return -1;
11074         }
11075
11076         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11077         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11078         if (!ptype) {
11079                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11080                 return -1;
11081         }
11082
11083         /* get information about new ptype list */
11084         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11085                                         (uint8_t *)ptype, buff_size,
11086                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11087         if (ret) {
11088                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11089                 rte_free(ptype);
11090                 return ret;
11091         }
11092
11093         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11094         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11095         if (!ptype_mapping) {
11096                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11097                 rte_free(ptype);
11098                 return -1;
11099         }
11100
11101         /* Update ptype mapping table. */
11102         for (i = 0; i < ptype_num; i++) {
11103                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11104                 ptype_mapping[i].sw_ptype = 0;
11105                 inner_ip = false;
11106                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11107                         proto_id = ptype[i].protocols[j];
11108                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11109                                 continue;
11110                         for (n = 0; n < proto_num; n++) {
11111                                 if (proto[n].proto_id != proto_id)
11112                                         continue;
11113                                 memset(name, 0, sizeof(name));
11114                                 strcpy(name, proto[n].name);
11115                                 if (!strncmp(name, "IPV4", 4) && !inner_ip) {
11116                                         ptype_mapping[i].sw_ptype |=
11117                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11118                                         inner_ip = true;
11119                                 } else if (!strncmp(name, "IPV4", 4) &&
11120                                            inner_ip) {
11121                                         ptype_mapping[i].sw_ptype |=
11122                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11123                                 } else if (!strncmp(name, "IPV6", 4) &&
11124                                            !inner_ip) {
11125                                         ptype_mapping[i].sw_ptype |=
11126                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11127                                         inner_ip = true;
11128                                 } else if (!strncmp(name, "IPV6", 4) &&
11129                                            inner_ip) {
11130                                         ptype_mapping[i].sw_ptype |=
11131                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11132                                 } else if (!strncmp(name, "IPV4FRAG", 8)) {
11133                                         ptype_mapping[i].sw_ptype |=
11134                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11135                                         ptype_mapping[i].sw_ptype |=
11136                                                 RTE_PTYPE_INNER_L4_FRAG;
11137                                 } else if (!strncmp(name, "IPV6FRAG", 8)) {
11138                                         ptype_mapping[i].sw_ptype |=
11139                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11140                                         ptype_mapping[i].sw_ptype |=
11141                                                 RTE_PTYPE_INNER_L4_FRAG;
11142                                 } else if (!strncmp(name, "GTPC", 4))
11143                                         ptype_mapping[i].sw_ptype |=
11144                                                 RTE_PTYPE_TUNNEL_GTPC;
11145                                 else if (!strncmp(name, "GTPU", 4))
11146                                         ptype_mapping[i].sw_ptype |=
11147                                                 RTE_PTYPE_TUNNEL_GTPU;
11148                                 else if (!strncmp(name, "UDP", 3))
11149                                         ptype_mapping[i].sw_ptype |=
11150                                                 RTE_PTYPE_INNER_L4_UDP;
11151                                 else if (!strncmp(name, "TCP", 3))
11152                                         ptype_mapping[i].sw_ptype |=
11153                                                 RTE_PTYPE_INNER_L4_TCP;
11154                                 else if (!strncmp(name, "SCTP", 4))
11155                                         ptype_mapping[i].sw_ptype |=
11156                                                 RTE_PTYPE_INNER_L4_SCTP;
11157                                 else if (!strncmp(name, "ICMP", 4) ||
11158                                          !strncmp(name, "ICMPV6", 6))
11159                                         ptype_mapping[i].sw_ptype |=
11160                                                 RTE_PTYPE_INNER_L4_ICMP;
11161
11162                                 break;
11163                         }
11164                 }
11165         }
11166
11167         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11168                                                 ptype_num, 0);
11169         if (ret)
11170                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11171
11172         rte_free(ptype_mapping);
11173         rte_free(ptype);
11174         return ret;
11175 }
11176
11177 void
11178 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11179                               uint32_t pkg_size)
11180 {
11181         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11182         uint32_t proto_num;
11183         struct rte_pmd_i40e_proto_info *proto;
11184         uint32_t buff_size;
11185         uint32_t i;
11186         int ret;
11187
11188         /* get information about protocol number */
11189         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11190                                        (uint8_t *)&proto_num, sizeof(proto_num),
11191                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11192         if (ret) {
11193                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11194                 return;
11195         }
11196         if (!proto_num) {
11197                 PMD_DRV_LOG(INFO, "No new protocol added");
11198                 return;
11199         }
11200
11201         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11202         proto = rte_zmalloc("new_proto", buff_size, 0);
11203         if (!proto) {
11204                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11205                 return;
11206         }
11207
11208         /* get information about protocol list */
11209         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11210                                         (uint8_t *)proto, buff_size,
11211                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11212         if (ret) {
11213                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11214                 rte_free(proto);
11215                 return;
11216         }
11217
11218         /* Check if GTP is supported. */
11219         for (i = 0; i < proto_num; i++) {
11220                 if (!strncmp(proto[i].name, "GTP", 3)) {
11221                         pf->gtp_support = true;
11222                         break;
11223                 }
11224         }
11225
11226         /* Update customized pctype info */
11227         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11228                                             proto_num, proto);
11229         if (ret)
11230                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11231
11232         /* Update customized ptype info */
11233         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11234                                            proto_num, proto);
11235         if (ret)
11236                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11237
11238         rte_free(proto);
11239 }
11240
11241 /* Create a QinQ cloud filter
11242  *
11243  * The Fortville NIC has limited resources for tunnel filters,
11244  * so we can only reuse existing filters.
11245  *
11246  * In step 1 we define which Field Vector fields can be used for
11247  * filter types.
11248  * As we do not have the inner tag defined as a field,
11249  * we have to define it first, by reusing one of L1 entries.
11250  *
11251  * In step 2 we are replacing one of existing filter types with
11252  * a new one for QinQ.
11253  * As we reusing L1 and replacing L2, some of the default filter
11254  * types will disappear,which depends on L1 and L2 entries we reuse.
11255  *
11256  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11257  *
11258  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11259  *              later when we define the cloud filter.
11260  *      a.      Valid_flags.replace_cloud = 0
11261  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11262  *      c.      New_filter = 0x10
11263  *      d.      TR bit = 0xff (optional, not used here)
11264  *      e.      Buffer – 2 entries:
11265  *              i.      Byte 0 = 8 (outer vlan FV index).
11266  *                      Byte 1 = 0 (rsv)
11267  *                      Byte 2-3 = 0x0fff
11268  *              ii.     Byte 0 = 37 (inner vlan FV index).
11269  *                      Byte 1 =0 (rsv)
11270  *                      Byte 2-3 = 0x0fff
11271  *
11272  * Step 2:
11273  * 2.   Create cloud filter using two L1 filters entries: stag and
11274  *              new filter(outer vlan+ inner vlan)
11275  *      a.      Valid_flags.replace_cloud = 1
11276  *      b.      Old_filter = 1 (instead of outer IP)
11277  *      c.      New_filter = 0x10
11278  *      d.      Buffer – 2 entries:
11279  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11280  *                      Byte 1-3 = 0 (rsv)
11281  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11282  *                      Byte 9-11 = 0 (rsv)
11283  */
11284 static int
11285 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11286 {
11287         int ret = -ENOTSUP;
11288         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11289         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11290         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11291
11292         /* Init */
11293         memset(&filter_replace, 0,
11294                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11295         memset(&filter_replace_buf, 0,
11296                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11297
11298         /* create L1 filter */
11299         filter_replace.old_filter_type =
11300                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11301         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11302         filter_replace.tr_bit = 0;
11303
11304         /* Prepare the buffer, 2 entries */
11305         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11306         filter_replace_buf.data[0] |=
11307                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11308         /* Field Vector 12b mask */
11309         filter_replace_buf.data[2] = 0xff;
11310         filter_replace_buf.data[3] = 0x0f;
11311         filter_replace_buf.data[4] =
11312                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11313         filter_replace_buf.data[4] |=
11314                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11315         /* Field Vector 12b mask */
11316         filter_replace_buf.data[6] = 0xff;
11317         filter_replace_buf.data[7] = 0x0f;
11318         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11319                         &filter_replace_buf);
11320         if (ret != I40E_SUCCESS)
11321                 return ret;
11322
11323         /* Apply the second L2 cloud filter */
11324         memset(&filter_replace, 0,
11325                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11326         memset(&filter_replace_buf, 0,
11327                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11328
11329         /* create L2 filter, input for L2 filter will be L1 filter  */
11330         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11331         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11332         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11333
11334         /* Prepare the buffer, 2 entries */
11335         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11336         filter_replace_buf.data[0] |=
11337                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11338         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11339         filter_replace_buf.data[4] |=
11340                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11341         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11342                         &filter_replace_buf);
11343         return ret;
11344 }
11345
11346 RTE_INIT(i40e_init_log);
11347 static void
11348 i40e_init_log(void)
11349 {
11350         i40e_logtype_init = rte_log_register("pmd.i40e.init");
11351         if (i40e_logtype_init >= 0)
11352                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11353         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11354         if (i40e_logtype_driver >= 0)
11355                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
11356 }