drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68 #include "rte_pmd_i40e.h"
  69
  70 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  71 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  72
  73 #define I40E_CLEAR_PXE_WAIT_MS     200
  74
  75 /* Maximun number of capability elements */
  76 #define I40E_MAX_CAP_ELE_NUM       128
  77
  78 /* Wait count and interval */
  79 #define I40E_CHK_Q_ENA_COUNT       1000
  80 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  81
  82 /* Maximun number of VSI */
  83 #define I40E_MAX_NUM_VSIS          (384UL)
  84
  85 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  86
  87 /* Flow control default timer */
  88 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  89
  90 /* Flow control enable fwd bit */
  91 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  92
  93 /* Receive Packet Buffer size */
  94 #define I40E_RXPBSIZE (968 * 1024)
  95
  96 /* Kilobytes shift */
  97 #define I40E_KILOSHIFT 10
  98
  99 /* Flow control default high water */
 100 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
 101
 102 /* Flow control default low water */
 103 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
 104
 105 /* Receive Average Packet Size in Byte*/
 106 #define I40E_PACKET_AVERAGE_SIZE 128
 107
 108 /* Mask of PF interrupt causes */
 109 #define I40E_PFINT_ICR0_ENA_MASK ( \
 110                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 112                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 114                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 115                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 118                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 119
 120 #define I40E_FLOW_TYPES ( \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 130         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 131         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 132
 133 /* Additional timesync values. */
 134 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 135 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 136 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 137 #define I40E_PRTTSYN_TSYNENA     0x80000000
 138 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 139 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 /**
 142  * Below are values for writing un-exposed registers suggested
 143  * by silicon experts
 144  */
 145 /* Destination MAC address */
 146 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 147 /* Source MAC address */
 148 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 149 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 150 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 151 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 152 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 153 /* Single VLAN tag in the inner L2 header */
 154 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 155 /* Source IPv4 address */
 156 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 157 /* Destination IPv4 address */
 158 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 159 /* Source IPv4 address for X722 */
 160 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 161 /* Destination IPv4 address for X722 */
 162 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 163 /* IPv4 Protocol for X722 */
 164 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 165 /* IPv4 Time to Live for X722 */
 166 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 167 /* IPv4 Type of Service (TOS) */
 168 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 169 /* IPv4 Protocol */
 170 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 171 /* IPv4 Time to Live */
 172 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 173 /* Source IPv6 address */
 174 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 175 /* Destination IPv6 address */
 176 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 177 /* IPv6 Traffic Class (TC) */
 178 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 179 /* IPv6 Next Header */
 180 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 181 /* IPv6 Hop Limit */
 182 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 183 /* Source L4 port */
 184 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 185 /* Destination L4 port */
 186 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 187 /* SCTP verification tag */
 188 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 189 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 190 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 191 /* Source port of tunneling UDP */
 192 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 193 /* Destination port of tunneling UDP */
 194 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 195 /* UDP Tunneling ID, NVGRE/GRE key */
 196 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 197 /* Last ether type */
 198 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 199 /* Tunneling outer destination IPv4 address */
 200 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 201 /* Tunneling outer destination IPv6 address */
 202 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 203 /* 1st word of flex payload */
 204 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 205 /* 2nd word of flex payload */
 206 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 207 /* 3rd word of flex payload */
 208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 209 /* 4th word of flex payload */
 210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 211 /* 5th word of flex payload */
 212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 213 /* 6th word of flex payload */
 214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 215 /* 7th word of flex payload */
 216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 217 /* 8th word of flex payload */
 218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 219 /* all 8 words flex payload */
 220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 221 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 222
 223 #define I40E_TRANSLATE_INSET 0
 224 #define I40E_TRANSLATE_REG   1
 225
 226 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 227 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 228 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 229 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 230 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 231 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 232
 233 /* PCI offset for querying capability */
 234 #define PCI_DEV_CAP_REG            0xA4
 235 /* PCI offset for enabling/disabling Extended Tag */
 236 #define PCI_DEV_CTRL_REG           0xA8
 237 /* Bit mask of Extended Tag capability */
 238 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 239 /* Bit shift of Extended Tag enable/disable */
 240 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 241 /* Bit mask of Extended Tag enable/disable */
 242 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 243
 244 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 245 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 246 static int i40e_dev_configure(struct rte_eth_dev *dev);
 247 static int i40e_dev_start(struct rte_eth_dev *dev);
 248 static void i40e_dev_stop(struct rte_eth_dev *dev);
 249 static void i40e_dev_close(struct rte_eth_dev *dev);
 250 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 251 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 252 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 253 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 254 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 255 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 256 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 257 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 258                                struct rte_eth_stats *stats);
 259 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 260                                struct rte_eth_xstat *xstats, unsigned n);
 261 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 262                                      struct rte_eth_xstat_name *xstats_names,
 263                                      unsigned limit);
 264 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 265 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 266                                             uint16_t queue_id,
 267                                             uint8_t stat_idx,
 268                                             uint8_t is_rx);
 269 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 270                                 char *fw_version, size_t fw_size);
 271 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 272                               struct rte_eth_dev_info *dev_info);
 273 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 274                                 uint16_t vlan_id,
 275                                 int on);
 276 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 277                               enum rte_vlan_type vlan_type,
 278                               uint16_t tpid);
 279 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 280 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 281                                       uint16_t queue,
 282                                       int on);
 283 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 284 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 285 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 286 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 287                               struct rte_eth_fc_conf *fc_conf);
 288 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 289                               struct rte_eth_fc_conf *fc_conf);
 290 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 291                                        struct rte_eth_pfc_conf *pfc_conf);
 292 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 293                             struct ether_addr *mac_addr,
 294                             uint32_t index,
 295                             uint32_t pool);
 296 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 297 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 298                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 299                                     uint16_t reta_size);
 300 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 301                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 302                                    uint16_t reta_size);
 303
 304 static int i40e_get_cap(struct i40e_hw *hw);
 305 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 306 static int i40e_pf_setup(struct i40e_pf *pf);
 307 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 308 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 309 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 310 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 311                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 312 static void i40e_stat_update_48(struct i40e_hw *hw,
 313                                uint32_t hireg,
 314                                uint32_t loreg,
 315                                bool offset_loaded,
 316                                uint64_t *offset,
 317                                uint64_t *stat);
 318 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 319 static void i40e_dev_interrupt_handler(void *param);
 320 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 321                                 uint32_t base, uint32_t num);
 322 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 323 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 324                         uint32_t base);
 325 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 326                         uint16_t num);
 327 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 328 static int i40e_veb_release(struct i40e_veb *veb);
 329 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 330                                                 struct i40e_vsi *vsi);
 331 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 332 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 333 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 334                                              struct i40e_macvlan_filter *mv_f,
 335                                              int num,
 336                                              uint16_t vlan);
 337 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 338 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 339                                     struct rte_eth_rss_conf *rss_conf);
 340 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 341                                       struct rte_eth_rss_conf *rss_conf);
 342 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 343                                         struct rte_eth_udp_tunnel *udp_tunnel);
 344 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 345                                         struct rte_eth_udp_tunnel *udp_tunnel);
 346 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 347 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 348                                 enum rte_filter_op filter_op,
 349                                 void *arg);
 350 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 351                                 enum rte_filter_type filter_type,
 352                                 enum rte_filter_op filter_op,
 353                                 void *arg);
 354 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 355                                   struct rte_eth_dcb_info *dcb_info);
 356 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 357 static void i40e_configure_registers(struct i40e_hw *hw);
 358 static void i40e_hw_init(struct rte_eth_dev *dev);
 359 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 360 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 361                                                      uint16_t seid,
 362                                                      uint16_t rule_type,
 363                                                      uint16_t *entries,
 364                                                      uint16_t count,
 365                                                      uint16_t rule_id);
 366 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 367                         struct rte_eth_mirror_conf *mirror_conf,
 368                         uint8_t sw_id, uint8_t on);
 369 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 370
 371 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 372 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 373 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 374                                            struct timespec *timestamp,
 375                                            uint32_t flags);
 376 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 377                                            struct timespec *timestamp);
 378 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 379
 380 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 381
 382 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 383                                    struct timespec *timestamp);
 384 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 385                                     const struct timespec *timestamp);
 386
 387 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 388                                          uint16_t queue_id);
 389 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 390                                           uint16_t queue_id);
 391
 392 static int i40e_get_regs(struct rte_eth_dev *dev,
 393                          struct rte_dev_reg_info *regs);
 394
 395 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 396
 397 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 398                            struct rte_dev_eeprom_info *eeprom);
 399
 400 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 401                                       struct ether_addr *mac_addr);
 402
 403 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 404
 405 static int i40e_ethertype_filter_convert(
 406         const struct rte_eth_ethertype_filter *input,
 407         struct i40e_ethertype_filter *filter);
 408 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 409                                    struct i40e_ethertype_filter *filter);
 410
 411 static int i40e_tunnel_filter_convert(
 412         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 413         struct i40e_tunnel_filter *tunnel_filter);
 414 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 415                                 struct i40e_tunnel_filter *tunnel_filter);
 416 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 417
 418 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 419 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 420 static void i40e_filter_restore(struct i40e_pf *pf);
 421 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 422
 423 int i40e_logtype_init;
 424 int i40e_logtype_driver;
 425
 426 static const struct rte_pci_id pci_id_i40e_map[] = {
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 445         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 446         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 447         { .vendor_id = 0, /* sentinel */ },
 448 };
 449
 450 static const struct eth_dev_ops i40e_eth_dev_ops = {
 451         .dev_configure                = i40e_dev_configure,
 452         .dev_start                    = i40e_dev_start,
 453         .dev_stop                     = i40e_dev_stop,
 454         .dev_close                    = i40e_dev_close,
 455         .dev_reset                    = i40e_dev_reset,
 456         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 457         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 458         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 459         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 460         .dev_set_link_up              = i40e_dev_set_link_up,
 461         .dev_set_link_down            = i40e_dev_set_link_down,
 462         .link_update                  = i40e_dev_link_update,
 463         .stats_get                    = i40e_dev_stats_get,
 464         .xstats_get                   = i40e_dev_xstats_get,
 465         .xstats_get_names             = i40e_dev_xstats_get_names,
 466         .stats_reset                  = i40e_dev_stats_reset,
 467         .xstats_reset                 = i40e_dev_stats_reset,
 468         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 469         .fw_version_get               = i40e_fw_version_get,
 470         .dev_infos_get                = i40e_dev_info_get,
 471         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 472         .vlan_filter_set              = i40e_vlan_filter_set,
 473         .vlan_tpid_set                = i40e_vlan_tpid_set,
 474         .vlan_offload_set             = i40e_vlan_offload_set,
 475         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 476         .vlan_pvid_set                = i40e_vlan_pvid_set,
 477         .rx_queue_start               = i40e_dev_rx_queue_start,
 478         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 479         .tx_queue_start               = i40e_dev_tx_queue_start,
 480         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 481         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 482         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 483         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 484         .rx_queue_release             = i40e_dev_rx_queue_release,
 485         .rx_queue_count               = i40e_dev_rx_queue_count,
 486         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 487         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 488         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 489         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 490         .tx_queue_release             = i40e_dev_tx_queue_release,
 491         .dev_led_on                   = i40e_dev_led_on,
 492         .dev_led_off                  = i40e_dev_led_off,
 493         .flow_ctrl_get                = i40e_flow_ctrl_get,
 494         .flow_ctrl_set                = i40e_flow_ctrl_set,
 495         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 496         .mac_addr_add                 = i40e_macaddr_add,
 497         .mac_addr_remove              = i40e_macaddr_remove,
 498         .reta_update                  = i40e_dev_rss_reta_update,
 499         .reta_query                   = i40e_dev_rss_reta_query,
 500         .rss_hash_update              = i40e_dev_rss_hash_update,
 501         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 502         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 503         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 504         .filter_ctrl                  = i40e_dev_filter_ctrl,
 505         .rxq_info_get                 = i40e_rxq_info_get,
 506         .txq_info_get                 = i40e_txq_info_get,
 507         .mirror_rule_set              = i40e_mirror_rule_set,
 508         .mirror_rule_reset            = i40e_mirror_rule_reset,
 509         .timesync_enable              = i40e_timesync_enable,
 510         .timesync_disable             = i40e_timesync_disable,
 511         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 512         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 513         .get_dcb_info                 = i40e_dev_get_dcb_info,
 514         .timesync_adjust_time         = i40e_timesync_adjust_time,
 515         .timesync_read_time           = i40e_timesync_read_time,
 516         .timesync_write_time          = i40e_timesync_write_time,
 517         .get_reg                      = i40e_get_regs,
 518         .get_eeprom_length            = i40e_get_eeprom_length,
 519         .get_eeprom                   = i40e_get_eeprom,
 520         .mac_addr_set                 = i40e_set_default_mac_addr,
 521         .mtu_set                      = i40e_dev_mtu_set,
 522         .tm_ops_get                   = i40e_tm_ops_get,
 523 };
 524
 525 /* store statistics names and its offset in stats structure */
 526 struct rte_i40e_xstats_name_off {
 527         char name[RTE_ETH_XSTATS_NAME_SIZE];
 528         unsigned offset;
 529 };
 530
 531 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 532         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 533         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 534         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 535         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 536         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 537                 rx_unknown_protocol)},
 538         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 539         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 540         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 541         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 542 };
 543
 544 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 545                 sizeof(rte_i40e_stats_strings[0]))
 546
 547 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 548         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 549                 tx_dropped_link_down)},
 550         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 551         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 552                 illegal_bytes)},
 553         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 554         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 555                 mac_local_faults)},
 556         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 557                 mac_remote_faults)},
 558         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 559                 rx_length_errors)},
 560         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 561         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 562         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 563         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 564         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 565         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_127)},
 567         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_255)},
 569         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_511)},
 571         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_1023)},
 573         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 574                 rx_size_1522)},
 575         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 576                 rx_size_big)},
 577         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 578                 rx_undersize)},
 579         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 580                 rx_oversize)},
 581         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 582                 mac_short_packet_dropped)},
 583         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 584                 rx_fragments)},
 585         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 586         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 587         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_127)},
 589         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_255)},
 591         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_511)},
 593         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_1023)},
 595         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 596                 tx_size_1522)},
 597         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 598                 tx_size_big)},
 599         {"rx_flow_director_atr_match_packets",
 600                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 601         {"rx_flow_director_sb_match_packets",
 602                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 603         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 604                 tx_lpi_status)},
 605         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 606                 rx_lpi_status)},
 607         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 608                 tx_lpi_count)},
 609         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 610                 rx_lpi_count)},
 611 };
 612
 613 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 614                 sizeof(rte_i40e_hw_port_strings[0]))
 615
 616 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 617         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 618                 priority_xon_rx)},
 619         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 620                 priority_xoff_rx)},
 621 };
 622
 623 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 624                 sizeof(rte_i40e_rxq_prio_strings[0]))
 625
 626 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 627         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 628                 priority_xon_tx)},
 629         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 630                 priority_xoff_tx)},
 631         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 632                 priority_xon_2_xoff)},
 633 };
 634
 635 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 636                 sizeof(rte_i40e_txq_prio_strings[0]))
 637
 638 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 639         struct rte_pci_device *pci_dev)
 640 {
 641         return rte_eth_dev_pci_generic_probe(pci_dev,
 642                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 643 }
 644
 645 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 646 {
 647         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 648 }
 649
 650 static struct rte_pci_driver rte_i40e_pmd = {
 651         .id_table = pci_id_i40e_map,
 652         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 653                      RTE_PCI_DRV_IOVA_AS_VA,
 654         .probe = eth_i40e_pci_probe,
 655         .remove = eth_i40e_pci_remove,
 656 };
 657
 658 static inline int
 659 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 660                                      struct rte_eth_link *link)
 661 {
 662         struct rte_eth_link *dst = link;
 663         struct rte_eth_link *src = &(dev->data->dev_link);
 664
 665         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 666                                         *(uint64_t *)src) == 0)
 667                 return -1;
 668
 669         return 0;
 670 }
 671
 672 static inline int
 673 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 674                                       struct rte_eth_link *link)
 675 {
 676         struct rte_eth_link *dst = &(dev->data->dev_link);
 677         struct rte_eth_link *src = link;
 678
 679         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 680                                         *(uint64_t *)src) == 0)
 681                 return -1;
 682
 683         return 0;
 684 }
 685
 686 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 687 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 688 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 689
 690 #ifndef I40E_GLQF_ORT
 691 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 692 #endif
 693 #ifndef I40E_GLQF_PIT
 694 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 695 #endif
 696 #ifndef I40E_GLQF_L3_MAP
 697 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 698 #endif
 699
 700 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 701 {
 702         /*
 703          * Force global configuration for flexible payload
 704          * to the first 16 bytes of the corresponding L2/L3/L4 paylod.
 705          * This should be removed from code once proper
 706          * configuration API is added to avoid configuration conflicts
 707          * between ports of the same device.
 708          */
 709         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 710         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 711         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 712
 713         /*
 714          * Initialize registers for parsing packet type of QinQ
 715          * This should be removed from code once proper
 716          * configuration API is added to avoid configuration conflicts
 717          * between ports of the same device.
 718          */
 719         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 720         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 721 }
 722
 723 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 724
 725 /*
 726  * Add a ethertype filter to drop all flow control frames transmitted
 727  * from VSIs.
 728 */
 729 static void
 730 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 731 {
 732         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 733         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 734                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 735                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 736         int ret;
 737
 738         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 739                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 740                                 pf->main_vsi_seid, 0,
 741                                 TRUE, NULL, NULL);
 742         if (ret)
 743                 PMD_INIT_LOG(ERR,
 744                         "Failed to add filter to drop flow control frames from VSIs.");
 745 }
 746
 747 static int
 748 floating_veb_list_handler(__rte_unused const char *key,
 749                           const char *floating_veb_value,
 750                           void *opaque)
 751 {
 752         int idx = 0;
 753         unsigned int count = 0;
 754         char *end = NULL;
 755         int min, max;
 756         bool *vf_floating_veb = opaque;
 757
 758         while (isblank(*floating_veb_value))
 759                 floating_veb_value++;
 760
 761         /* Reset floating VEB configuration for VFs */
 762         for (idx = 0; idx < I40E_MAX_VF; idx++)
 763                 vf_floating_veb[idx] = false;
 764
 765         min = I40E_MAX_VF;
 766         do {
 767                 while (isblank(*floating_veb_value))
 768                         floating_veb_value++;
 769                 if (*floating_veb_value == '\0')
 770                         return -1;
 771                 errno = 0;
 772                 idx = strtoul(floating_veb_value, &end, 10);
 773                 if (errno || end == NULL)
 774                         return -1;
 775                 while (isblank(*end))
 776                         end++;
 777                 if (*end == '-') {
 778                         min = idx;
 779                 } else if ((*end == ';') || (*end == '\0')) {
 780                         max = idx;
 781                         if (min == I40E_MAX_VF)
 782                                 min = idx;
 783                         if (max >= I40E_MAX_VF)
 784                                 max = I40E_MAX_VF - 1;
 785                         for (idx = min; idx <= max; idx++) {
 786                                 vf_floating_veb[idx] = true;
 787                                 count++;
 788                         }
 789                         min = I40E_MAX_VF;
 790                 } else {
 791                         return -1;
 792                 }
 793                 floating_veb_value = end + 1;
 794         } while (*end != '\0');
 795
 796         if (count == 0)
 797                 return -1;
 798
 799         return 0;
 800 }
 801
 802 static void
 803 config_vf_floating_veb(struct rte_devargs *devargs,
 804                        uint16_t floating_veb,
 805                        bool *vf_floating_veb)
 806 {
 807         struct rte_kvargs *kvlist;
 808         int i;
 809         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 810
 811         if (!floating_veb)
 812                 return;
 813         /* All the VFs attach to the floating VEB by default
 814          * when the floating VEB is enabled.
 815          */
 816         for (i = 0; i < I40E_MAX_VF; i++)
 817                 vf_floating_veb[i] = true;
 818
 819         if (devargs == NULL)
 820                 return;
 821
 822         kvlist = rte_kvargs_parse(devargs->args, NULL);
 823         if (kvlist == NULL)
 824                 return;
 825
 826         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 827                 rte_kvargs_free(kvlist);
 828                 return;
 829         }
 830         /* When the floating_veb_list parameter exists, all the VFs
 831          * will attach to the legacy VEB firstly, then configure VFs
 832          * to the floating VEB according to the floating_veb_list.
 833          */
 834         if (rte_kvargs_process(kvlist, floating_veb_list,
 835                                floating_veb_list_handler,
 836                                vf_floating_veb) < 0) {
 837                 rte_kvargs_free(kvlist);
 838                 return;
 839         }
 840         rte_kvargs_free(kvlist);
 841 }
 842
 843 static int
 844 i40e_check_floating_handler(__rte_unused const char *key,
 845                             const char *value,
 846                             __rte_unused void *opaque)
 847 {
 848         if (strcmp(value, "1"))
 849                 return -1;
 850
 851         return 0;
 852 }
 853
 854 static int
 855 is_floating_veb_supported(struct rte_devargs *devargs)
 856 {
 857         struct rte_kvargs *kvlist;
 858         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 859
 860         if (devargs == NULL)
 861                 return 0;
 862
 863         kvlist = rte_kvargs_parse(devargs->args, NULL);
 864         if (kvlist == NULL)
 865                 return 0;
 866
 867         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 868                 rte_kvargs_free(kvlist);
 869                 return 0;
 870         }
 871         /* Floating VEB is enabled when there's key-value:
 872          * enable_floating_veb=1
 873          */
 874         if (rte_kvargs_process(kvlist, floating_veb_key,
 875                                i40e_check_floating_handler, NULL) < 0) {
 876                 rte_kvargs_free(kvlist);
 877                 return 0;
 878         }
 879         rte_kvargs_free(kvlist);
 880
 881         return 1;
 882 }
 883
 884 static void
 885 config_floating_veb(struct rte_eth_dev *dev)
 886 {
 887         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 888         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 889         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 890
 891         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 892
 893         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 894                 pf->floating_veb =
 895                         is_floating_veb_supported(pci_dev->device.devargs);
 896                 config_vf_floating_veb(pci_dev->device.devargs,
 897                                        pf->floating_veb,
 898                                        pf->floating_veb_list);
 899         } else {
 900                 pf->floating_veb = false;
 901         }
 902 }
 903
 904 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 905 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 906
 907 static int
 908 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 909 {
 910         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 911         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 912         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 913         int ret;
 914
 915         struct rte_hash_parameters ethertype_hash_params = {
 916                 .name = ethertype_hash_name,
 917                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 918                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 919                 .hash_func = rte_hash_crc,
 920                 .hash_func_init_val = 0,
 921                 .socket_id = rte_socket_id(),
 922         };
 923
 924         /* Initialize ethertype filter rule list and hash */
 925         TAILQ_INIT(&ethertype_rule->ethertype_list);
 926         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 927                  "ethertype_%s", dev->device->name);
 928         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 929         if (!ethertype_rule->hash_table) {
 930                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 931                 return -EINVAL;
 932         }
 933         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 934                                        sizeof(struct i40e_ethertype_filter *) *
 935                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 936                                        0);
 937         if (!ethertype_rule->hash_map) {
 938                 PMD_INIT_LOG(ERR,
 939                              "Failed to allocate memory for ethertype hash map!");
 940                 ret = -ENOMEM;
 941                 goto err_ethertype_hash_map_alloc;
 942         }
 943
 944         return 0;
 945
 946 err_ethertype_hash_map_alloc:
 947         rte_hash_free(ethertype_rule->hash_table);
 948
 949         return ret;
 950 }
 951
 952 static int
 953 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 954 {
 955         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 956         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 957         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 958         int ret;
 959
 960         struct rte_hash_parameters tunnel_hash_params = {
 961                 .name = tunnel_hash_name,
 962                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 963                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 964                 .hash_func = rte_hash_crc,
 965                 .hash_func_init_val = 0,
 966                 .socket_id = rte_socket_id(),
 967         };
 968
 969         /* Initialize tunnel filter rule list and hash */
 970         TAILQ_INIT(&tunnel_rule->tunnel_list);
 971         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 972                  "tunnel_%s", dev->device->name);
 973         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 974         if (!tunnel_rule->hash_table) {
 975                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 976                 return -EINVAL;
 977         }
 978         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 979                                     sizeof(struct i40e_tunnel_filter *) *
 980                                     I40E_MAX_TUNNEL_FILTER_NUM,
 981                                     0);
 982         if (!tunnel_rule->hash_map) {
 983                 PMD_INIT_LOG(ERR,
 984                              "Failed to allocate memory for tunnel hash map!");
 985                 ret = -ENOMEM;
 986                 goto err_tunnel_hash_map_alloc;
 987         }
 988
 989         return 0;
 990
 991 err_tunnel_hash_map_alloc:
 992         rte_hash_free(tunnel_rule->hash_table);
 993
 994         return ret;
 995 }
 996
 997 static int
 998 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 999 {
1000         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1001         struct i40e_fdir_info *fdir_info = &pf->fdir;
1002         char fdir_hash_name[RTE_HASH_NAMESIZE];
1003         int ret;
1004
1005         struct rte_hash_parameters fdir_hash_params = {
1006                 .name = fdir_hash_name,
1007                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1008                 .key_len = sizeof(struct rte_eth_fdir_input),
1009                 .hash_func = rte_hash_crc,
1010                 .hash_func_init_val = 0,
1011                 .socket_id = rte_socket_id(),
1012         };
1013
1014         /* Initialize flow director filter rule list and hash */
1015         TAILQ_INIT(&fdir_info->fdir_list);
1016         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1017                  "fdir_%s", dev->device->name);
1018         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1019         if (!fdir_info->hash_table) {
1020                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1021                 return -EINVAL;
1022         }
1023         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1024                                           sizeof(struct i40e_fdir_filter *) *
1025                                           I40E_MAX_FDIR_FILTER_NUM,
1026                                           0);
1027         if (!fdir_info->hash_map) {
1028                 PMD_INIT_LOG(ERR,
1029                              "Failed to allocate memory for fdir hash map!");
1030                 ret = -ENOMEM;
1031                 goto err_fdir_hash_map_alloc;
1032         }
1033         return 0;
1034
1035 err_fdir_hash_map_alloc:
1036         rte_hash_free(fdir_info->hash_table);
1037
1038         return ret;
1039 }
1040
1041 static void
1042 i40e_init_customized_info(struct i40e_pf *pf)
1043 {
1044         int i;
1045
1046         /* Initialize customized pctype */
1047         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1048                 pf->customized_pctype[i].index = i;
1049                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1050                 pf->customized_pctype[i].valid = false;
1051         }
1052
1053         pf->gtp_support = false;
1054 }
1055
1056 void
1057 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1058 {
1059         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1060         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1061         struct i40e_queue_regions *info = &pf->queue_region;
1062         uint16_t i;
1063
1064         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1065                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1066
1067         memset(info, 0, sizeof(struct i40e_queue_regions));
1068 }
1069
1070 static int
1071 eth_i40e_dev_init(struct rte_eth_dev *dev)
1072 {
1073         struct rte_pci_device *pci_dev;
1074         struct rte_intr_handle *intr_handle;
1075         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1076         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1077         struct i40e_vsi *vsi;
1078         int ret;
1079         uint32_t len;
1080         uint8_t aq_fail = 0;
1081
1082         PMD_INIT_FUNC_TRACE();
1083
1084         dev->dev_ops = &i40e_eth_dev_ops;
1085         dev->rx_pkt_burst = i40e_recv_pkts;
1086         dev->tx_pkt_burst = i40e_xmit_pkts;
1087         dev->tx_pkt_prepare = i40e_prep_pkts;
1088
1089         /* for secondary processes, we don't initialise any further as primary
1090          * has already done this work. Only check we don't need a different
1091          * RX function */
1092         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1093                 i40e_set_rx_function(dev);
1094                 i40e_set_tx_function(dev);
1095                 return 0;
1096         }
1097         i40e_set_default_ptype_table(dev);
1098         i40e_set_default_pctype_table(dev);
1099         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1100         intr_handle = &pci_dev->intr_handle;
1101
1102         rte_eth_copy_pci_info(dev, pci_dev);
1103
1104         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1105         pf->adapter->eth_dev = dev;
1106         pf->dev_data = dev->data;
1107
1108         hw->back = I40E_PF_TO_ADAPTER(pf);
1109         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1110         if (!hw->hw_addr) {
1111                 PMD_INIT_LOG(ERR,
1112                         "Hardware is not available, as address is NULL");
1113                 return -ENODEV;
1114         }
1115
1116         hw->vendor_id = pci_dev->id.vendor_id;
1117         hw->device_id = pci_dev->id.device_id;
1118         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1119         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1120         hw->bus.device = pci_dev->addr.devid;
1121         hw->bus.func = pci_dev->addr.function;
1122         hw->adapter_stopped = 0;
1123
1124         /* Make sure all is clean before doing PF reset */
1125         i40e_clear_hw(hw);
1126
1127         /* Initialize the hardware */
1128         i40e_hw_init(dev);
1129
1130         /* Reset here to make sure all is clean for each PF */
1131         ret = i40e_pf_reset(hw);
1132         if (ret) {
1133                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1134                 return ret;
1135         }
1136
1137         /* Initialize the shared code (base driver) */
1138         ret = i40e_init_shared_code(hw);
1139         if (ret) {
1140                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1141                 return ret;
1142         }
1143
1144         /*
1145          * To work around the NVM issue, initialize registers
1146          * for flexible payload and packet type of QinQ by
1147          * software. It should be removed once issues are fixed
1148          * in NVM.
1149          */
1150         i40e_GLQF_reg_init(hw);
1151
1152         /* Initialize the input set for filters (hash and fd) to default value */
1153         i40e_filter_input_set_init(pf);
1154
1155         /* Initialize the parameters for adminq */
1156         i40e_init_adminq_parameter(hw);
1157         ret = i40e_init_adminq(hw);
1158         if (ret != I40E_SUCCESS) {
1159                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1160                 return -EIO;
1161         }
1162         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1163                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1164                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1165                      ((hw->nvm.version >> 12) & 0xf),
1166                      ((hw->nvm.version >> 4) & 0xff),
1167                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1168
1169         /* initialise the L3_MAP register */
1170         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1171                                    0x00000028,  NULL);
1172         if (ret)
1173                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1174
1175         /* Need the special FW version to support floating VEB */
1176         config_floating_veb(dev);
1177         /* Clear PXE mode */
1178         i40e_clear_pxe_mode(hw);
1179         i40e_dev_sync_phy_type(hw);
1180
1181         /*
1182          * On X710, performance number is far from the expectation on recent
1183          * firmware versions. The fix for this issue may not be integrated in
1184          * the following firmware version. So the workaround in software driver
1185          * is needed. It needs to modify the initial values of 3 internal only
1186          * registers. Note that the workaround can be removed when it is fixed
1187          * in firmware in the future.
1188          */
1189         i40e_configure_registers(hw);
1190
1191         /* Get hw capabilities */
1192         ret = i40e_get_cap(hw);
1193         if (ret != I40E_SUCCESS) {
1194                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1195                 goto err_get_capabilities;
1196         }
1197
1198         /* Initialize parameters for PF */
1199         ret = i40e_pf_parameter_init(dev);
1200         if (ret != 0) {
1201                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1202                 goto err_parameter_init;
1203         }
1204
1205         /* Initialize the queue management */
1206         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1207         if (ret < 0) {
1208                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1209                 goto err_qp_pool_init;
1210         }
1211         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1212                                 hw->func_caps.num_msix_vectors - 1);
1213         if (ret < 0) {
1214                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1215                 goto err_msix_pool_init;
1216         }
1217
1218         /* Initialize lan hmc */
1219         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1220                                 hw->func_caps.num_rx_qp, 0, 0);
1221         if (ret != I40E_SUCCESS) {
1222                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1223                 goto err_init_lan_hmc;
1224         }
1225
1226         /* Configure lan hmc */
1227         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1228         if (ret != I40E_SUCCESS) {
1229                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1230                 goto err_configure_lan_hmc;
1231         }
1232
1233         /* Get and check the mac address */
1234         i40e_get_mac_addr(hw, hw->mac.addr);
1235         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1236                 PMD_INIT_LOG(ERR, "mac address is not valid");
1237                 ret = -EIO;
1238                 goto err_get_mac_addr;
1239         }
1240         /* Copy the permanent MAC address */
1241         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1242                         (struct ether_addr *) hw->mac.perm_addr);
1243
1244         /* Disable flow control */
1245         hw->fc.requested_mode = I40E_FC_NONE;
1246         i40e_set_fc(hw, &aq_fail, TRUE);
1247
1248         /* Set the global registers with default ether type value */
1249         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1250         if (ret != I40E_SUCCESS) {
1251                 PMD_INIT_LOG(ERR,
1252                         "Failed to set the default outer VLAN ether type");
1253                 goto err_setup_pf_switch;
1254         }
1255
1256         /* PF setup, which includes VSI setup */
1257         ret = i40e_pf_setup(pf);
1258         if (ret) {
1259                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1260                 goto err_setup_pf_switch;
1261         }
1262
1263         /* reset all stats of the device, including pf and main vsi */
1264         i40e_dev_stats_reset(dev);
1265
1266         vsi = pf->main_vsi;
1267
1268         /* Disable double vlan by default */
1269         i40e_vsi_config_double_vlan(vsi, FALSE);
1270
1271         /* Disable S-TAG identification when floating_veb is disabled */
1272         if (!pf->floating_veb) {
1273                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1274                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1275                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1276                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1277                 }
1278         }
1279
1280         if (!vsi->max_macaddrs)
1281                 len = ETHER_ADDR_LEN;
1282         else
1283                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1284
1285         /* Should be after VSI initialized */
1286         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1287         if (!dev->data->mac_addrs) {
1288                 PMD_INIT_LOG(ERR,
1289                         "Failed to allocated memory for storing mac address");
1290                 goto err_mac_alloc;
1291         }
1292         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1293                                         &dev->data->mac_addrs[0]);
1294
1295         /* Init dcb to sw mode by default */
1296         ret = i40e_dcb_init_configure(dev, TRUE);
1297         if (ret != I40E_SUCCESS) {
1298                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1299                 pf->flags &= ~I40E_FLAG_DCB;
1300         }
1301         /* Update HW struct after DCB configuration */
1302         i40e_get_cap(hw);
1303
1304         /* initialize pf host driver to setup SRIOV resource if applicable */
1305         i40e_pf_host_init(dev);
1306
1307         /* register callback func to eal lib */
1308         rte_intr_callback_register(intr_handle,
1309                                    i40e_dev_interrupt_handler, dev);
1310
1311         /* configure and enable device interrupt */
1312         i40e_pf_config_irq0(hw, TRUE);
1313         i40e_pf_enable_irq0(hw);
1314
1315         /* enable uio intr after callback register */
1316         rte_intr_enable(intr_handle);
1317         /*
1318          * Add an ethertype filter to drop all flow control frames transmitted
1319          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1320          * frames to wire.
1321          */
1322         i40e_add_tx_flow_control_drop_filter(pf);
1323
1324         /* Set the max frame size to 0x2600 by default,
1325          * in case other drivers changed the default value.
1326          */
1327         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1328
1329         /* initialize mirror rule list */
1330         TAILQ_INIT(&pf->mirror_list);
1331
1332         /* initialize Traffic Manager configuration */
1333         i40e_tm_conf_init(dev);
1334
1335         /* Initialize customized information */
1336         i40e_init_customized_info(pf);
1337
1338         ret = i40e_init_ethtype_filter_list(dev);
1339         if (ret < 0)
1340                 goto err_init_ethtype_filter_list;
1341         ret = i40e_init_tunnel_filter_list(dev);
1342         if (ret < 0)
1343                 goto err_init_tunnel_filter_list;
1344         ret = i40e_init_fdir_filter_list(dev);
1345         if (ret < 0)
1346                 goto err_init_fdir_filter_list;
1347
1348         /* initialize queue region configuration */
1349         i40e_init_queue_region_conf(dev);
1350
1351         return 0;
1352
1353 err_init_fdir_filter_list:
1354         rte_free(pf->tunnel.hash_table);
1355         rte_free(pf->tunnel.hash_map);
1356 err_init_tunnel_filter_list:
1357         rte_free(pf->ethertype.hash_table);
1358         rte_free(pf->ethertype.hash_map);
1359 err_init_ethtype_filter_list:
1360         rte_free(dev->data->mac_addrs);
1361 err_mac_alloc:
1362         i40e_vsi_release(pf->main_vsi);
1363 err_setup_pf_switch:
1364 err_get_mac_addr:
1365 err_configure_lan_hmc:
1366         (void)i40e_shutdown_lan_hmc(hw);
1367 err_init_lan_hmc:
1368         i40e_res_pool_destroy(&pf->msix_pool);
1369 err_msix_pool_init:
1370         i40e_res_pool_destroy(&pf->qp_pool);
1371 err_qp_pool_init:
1372 err_parameter_init:
1373 err_get_capabilities:
1374         (void)i40e_shutdown_adminq(hw);
1375
1376         return ret;
1377 }
1378
1379 static void
1380 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1381 {
1382         struct i40e_ethertype_filter *p_ethertype;
1383         struct i40e_ethertype_rule *ethertype_rule;
1384
1385         ethertype_rule = &pf->ethertype;
1386         /* Remove all ethertype filter rules and hash */
1387         if (ethertype_rule->hash_map)
1388                 rte_free(ethertype_rule->hash_map);
1389         if (ethertype_rule->hash_table)
1390                 rte_hash_free(ethertype_rule->hash_table);
1391
1392         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1393                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1394                              p_ethertype, rules);
1395                 rte_free(p_ethertype);
1396         }
1397 }
1398
1399 static void
1400 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1401 {
1402         struct i40e_tunnel_filter *p_tunnel;
1403         struct i40e_tunnel_rule *tunnel_rule;
1404
1405         tunnel_rule = &pf->tunnel;
1406         /* Remove all tunnel director rules and hash */
1407         if (tunnel_rule->hash_map)
1408                 rte_free(tunnel_rule->hash_map);
1409         if (tunnel_rule->hash_table)
1410                 rte_hash_free(tunnel_rule->hash_table);
1411
1412         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1413                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1414                 rte_free(p_tunnel);
1415         }
1416 }
1417
1418 static void
1419 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1420 {
1421         struct i40e_fdir_filter *p_fdir;
1422         struct i40e_fdir_info *fdir_info;
1423
1424         fdir_info = &pf->fdir;
1425         /* Remove all flow director rules and hash */
1426         if (fdir_info->hash_map)
1427                 rte_free(fdir_info->hash_map);
1428         if (fdir_info->hash_table)
1429                 rte_hash_free(fdir_info->hash_table);
1430
1431         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1432                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1433                 rte_free(p_fdir);
1434         }
1435 }
1436
1437 static int
1438 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1439 {
1440         struct i40e_pf *pf;
1441         struct rte_pci_device *pci_dev;
1442         struct rte_intr_handle *intr_handle;
1443         struct i40e_hw *hw;
1444         struct i40e_filter_control_settings settings;
1445         struct rte_flow *p_flow;
1446         int ret;
1447         uint8_t aq_fail = 0;
1448
1449         PMD_INIT_FUNC_TRACE();
1450
1451         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1452                 return 0;
1453
1454         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1455         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1456         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1457         intr_handle = &pci_dev->intr_handle;
1458
1459         if (hw->adapter_stopped == 0)
1460                 i40e_dev_close(dev);
1461
1462         dev->dev_ops = NULL;
1463         dev->rx_pkt_burst = NULL;
1464         dev->tx_pkt_burst = NULL;
1465
1466         /* Clear PXE mode */
1467         i40e_clear_pxe_mode(hw);
1468
1469         /* Unconfigure filter control */
1470         memset(&settings, 0, sizeof(settings));
1471         ret = i40e_set_filter_control(hw, &settings);
1472         if (ret)
1473                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1474                                         ret);
1475
1476         /* Disable flow control */
1477         hw->fc.requested_mode = I40E_FC_NONE;
1478         i40e_set_fc(hw, &aq_fail, TRUE);
1479
1480         /* uninitialize pf host driver */
1481         i40e_pf_host_uninit(dev);
1482
1483         rte_free(dev->data->mac_addrs);
1484         dev->data->mac_addrs = NULL;
1485
1486         /* disable uio intr before callback unregister */
1487         rte_intr_disable(intr_handle);
1488
1489         /* register callback func to eal lib */
1490         rte_intr_callback_unregister(intr_handle,
1491                                      i40e_dev_interrupt_handler, dev);
1492
1493         i40e_rm_ethtype_filter_list(pf);
1494         i40e_rm_tunnel_filter_list(pf);
1495         i40e_rm_fdir_filter_list(pf);
1496
1497         /* Remove all flows */
1498         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1499                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1500                 rte_free(p_flow);
1501         }
1502
1503         /* Remove all Traffic Manager configuration */
1504         i40e_tm_conf_uninit(dev);
1505
1506         return 0;
1507 }
1508
1509 static int
1510 i40e_dev_configure(struct rte_eth_dev *dev)
1511 {
1512         struct i40e_adapter *ad =
1513                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1514         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1515         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1516         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1517         int i, ret;
1518
1519         ret = i40e_dev_sync_phy_type(hw);
1520         if (ret)
1521                 return ret;
1522
1523         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1524          * bulk allocation or vector Rx preconditions we will reset it.
1525          */
1526         ad->rx_bulk_alloc_allowed = true;
1527         ad->rx_vec_allowed = true;
1528         ad->tx_simple_allowed = true;
1529         ad->tx_vec_allowed = true;
1530
1531         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1532                 ret = i40e_fdir_setup(pf);
1533                 if (ret != I40E_SUCCESS) {
1534                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1535                         return -ENOTSUP;
1536                 }
1537                 ret = i40e_fdir_configure(dev);
1538                 if (ret < 0) {
1539                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1540                         goto err;
1541                 }
1542         } else
1543                 i40e_fdir_teardown(pf);
1544
1545         ret = i40e_dev_init_vlan(dev);
1546         if (ret < 0)
1547                 goto err;
1548
1549         /* VMDQ setup.
1550          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1551          *  RSS setting have different requirements.
1552          *  General PMD driver call sequence are NIC init, configure,
1553          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1554          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1555          *  applicable. So, VMDQ setting has to be done before
1556          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1557          *  For RSS setting, it will try to calculate actual configured RX queue
1558          *  number, which will be available after rx_queue_setup(). dev_start()
1559          *  function is good to place RSS setup.
1560          */
1561         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1562                 ret = i40e_vmdq_setup(dev);
1563                 if (ret)
1564                         goto err;
1565         }
1566
1567         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1568                 ret = i40e_dcb_setup(dev);
1569                 if (ret) {
1570                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1571                         goto err_dcb;
1572                 }
1573         }
1574
1575         TAILQ_INIT(&pf->flow_list);
1576
1577         return 0;
1578
1579 err_dcb:
1580         /* need to release vmdq resource if exists */
1581         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1582                 i40e_vsi_release(pf->vmdq[i].vsi);
1583                 pf->vmdq[i].vsi = NULL;
1584         }
1585         rte_free(pf->vmdq);
1586         pf->vmdq = NULL;
1587 err:
1588         /* need to release fdir resource if exists */
1589         i40e_fdir_teardown(pf);
1590         return ret;
1591 }
1592
1593 void
1594 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1595 {
1596         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1597         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1598         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1599         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1600         uint16_t msix_vect = vsi->msix_intr;
1601         uint16_t i;
1602
1603         for (i = 0; i < vsi->nb_qps; i++) {
1604                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1605                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1606                 rte_wmb();
1607         }
1608
1609         if (vsi->type != I40E_VSI_SRIOV) {
1610                 if (!rte_intr_allow_others(intr_handle)) {
1611                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1612                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1613                         I40E_WRITE_REG(hw,
1614                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1615                                        0);
1616                 } else {
1617                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1618                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1619                         I40E_WRITE_REG(hw,
1620                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1621                                                        msix_vect - 1), 0);
1622                 }
1623         } else {
1624                 uint32_t reg;
1625                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1626                         vsi->user_param + (msix_vect - 1);
1627
1628                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1629                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1630         }
1631         I40E_WRITE_FLUSH(hw);
1632 }
1633
1634 static void
1635 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1636                        int base_queue, int nb_queue,
1637                        uint16_t itr_idx)
1638 {
1639         int i;
1640         uint32_t val;
1641         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1642
1643         /* Bind all RX queues to allocated MSIX interrupt */
1644         for (i = 0; i < nb_queue; i++) {
1645                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1646                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1647                         ((base_queue + i + 1) <<
1648                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1649                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1650                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1651
1652                 if (i == nb_queue - 1)
1653                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1654                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1655         }
1656
1657         /* Write first RX queue to Link list register as the head element */
1658         if (vsi->type != I40E_VSI_SRIOV) {
1659                 uint16_t interval =
1660                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1661
1662                 if (msix_vect == I40E_MISC_VEC_ID) {
1663                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1664                                        (base_queue <<
1665                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1666                                        (0x0 <<
1667                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1668                         I40E_WRITE_REG(hw,
1669                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1670                                        interval);
1671                 } else {
1672                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1673                                        (base_queue <<
1674                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1675                                        (0x0 <<
1676                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1677                         I40E_WRITE_REG(hw,
1678                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1679                                                        msix_vect - 1),
1680                                        interval);
1681                 }
1682         } else {
1683                 uint32_t reg;
1684
1685                 if (msix_vect == I40E_MISC_VEC_ID) {
1686                         I40E_WRITE_REG(hw,
1687                                        I40E_VPINT_LNKLST0(vsi->user_param),
1688                                        (base_queue <<
1689                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1690                                        (0x0 <<
1691                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1692                 } else {
1693                         /* num_msix_vectors_vf needs to minus irq0 */
1694                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1695                                 vsi->user_param + (msix_vect - 1);
1696
1697                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1698                                        (base_queue <<
1699                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1700                                        (0x0 <<
1701                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1702                 }
1703         }
1704
1705         I40E_WRITE_FLUSH(hw);
1706 }
1707
1708 void
1709 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1710 {
1711         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1712         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1713         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1714         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1715         uint16_t msix_vect = vsi->msix_intr;
1716         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1717         uint16_t queue_idx = 0;
1718         int record = 0;
1719         uint32_t val;
1720         int i;
1721
1722         for (i = 0; i < vsi->nb_qps; i++) {
1723                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1724                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1725         }
1726
1727         /* INTENA flag is not auto-cleared for interrupt */
1728         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1729         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1730                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1731                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1732         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1733
1734         /* VF bind interrupt */
1735         if (vsi->type == I40E_VSI_SRIOV) {
1736                 __vsi_queues_bind_intr(vsi, msix_vect,
1737                                        vsi->base_queue, vsi->nb_qps,
1738                                        itr_idx);
1739                 return;
1740         }
1741
1742         /* PF & VMDq bind interrupt */
1743         if (rte_intr_dp_is_en(intr_handle)) {
1744                 if (vsi->type == I40E_VSI_MAIN) {
1745                         queue_idx = 0;
1746                         record = 1;
1747                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1748                         struct i40e_vsi *main_vsi =
1749                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1750                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1751                         record = 1;
1752                 }
1753         }
1754
1755         for (i = 0; i < vsi->nb_used_qps; i++) {
1756                 if (nb_msix <= 1) {
1757                         if (!rte_intr_allow_others(intr_handle))
1758                                 /* allow to share MISC_VEC_ID */
1759                                 msix_vect = I40E_MISC_VEC_ID;
1760
1761                         /* no enough msix_vect, map all to one */
1762                         __vsi_queues_bind_intr(vsi, msix_vect,
1763                                                vsi->base_queue + i,
1764                                                vsi->nb_used_qps - i,
1765                                                itr_idx);
1766                         for (; !!record && i < vsi->nb_used_qps; i++)
1767                                 intr_handle->intr_vec[queue_idx + i] =
1768                                         msix_vect;
1769                         break;
1770                 }
1771                 /* 1:1 queue/msix_vect mapping */
1772                 __vsi_queues_bind_intr(vsi, msix_vect,
1773                                        vsi->base_queue + i, 1,
1774                                        itr_idx);
1775                 if (!!record)
1776                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1777
1778                 msix_vect++;
1779                 nb_msix--;
1780         }
1781 }
1782
1783 static void
1784 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1785 {
1786         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1787         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1788         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1789         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1790         uint16_t interval = i40e_calc_itr_interval(\
1791                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1792         uint16_t msix_intr, i;
1793
1794         if (rte_intr_allow_others(intr_handle))
1795                 for (i = 0; i < vsi->nb_msix; i++) {
1796                         msix_intr = vsi->msix_intr + i;
1797                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1798                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1799                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1800                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1801                                 (interval <<
1802                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1803                 }
1804         else
1805                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1806                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1807                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1808                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1809                                (interval <<
1810                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1811
1812         I40E_WRITE_FLUSH(hw);
1813 }
1814
1815 static void
1816 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1817 {
1818         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1819         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1820         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1821         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1822         uint16_t msix_intr, i;
1823
1824         if (rte_intr_allow_others(intr_handle))
1825                 for (i = 0; i < vsi->nb_msix; i++) {
1826                         msix_intr = vsi->msix_intr + i;
1827                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1828                                        0);
1829                 }
1830         else
1831                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1832
1833         I40E_WRITE_FLUSH(hw);
1834 }
1835
1836 static inline uint8_t
1837 i40e_parse_link_speeds(uint16_t link_speeds)
1838 {
1839         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1840
1841         if (link_speeds & ETH_LINK_SPEED_40G)
1842                 link_speed |= I40E_LINK_SPEED_40GB;
1843         if (link_speeds & ETH_LINK_SPEED_25G)
1844                 link_speed |= I40E_LINK_SPEED_25GB;
1845         if (link_speeds & ETH_LINK_SPEED_20G)
1846                 link_speed |= I40E_LINK_SPEED_20GB;
1847         if (link_speeds & ETH_LINK_SPEED_10G)
1848                 link_speed |= I40E_LINK_SPEED_10GB;
1849         if (link_speeds & ETH_LINK_SPEED_1G)
1850                 link_speed |= I40E_LINK_SPEED_1GB;
1851         if (link_speeds & ETH_LINK_SPEED_100M)
1852                 link_speed |= I40E_LINK_SPEED_100MB;
1853
1854         return link_speed;
1855 }
1856
1857 static int
1858 i40e_phy_conf_link(struct i40e_hw *hw,
1859                    uint8_t abilities,
1860                    uint8_t force_speed,
1861                    bool is_up)
1862 {
1863         enum i40e_status_code status;
1864         struct i40e_aq_get_phy_abilities_resp phy_ab;
1865         struct i40e_aq_set_phy_config phy_conf;
1866         enum i40e_aq_phy_type cnt;
1867         uint32_t phy_type_mask = 0;
1868
1869         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1870                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1871                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1872                         I40E_AQ_PHY_FLAG_LOW_POWER;
1873         const uint8_t advt = I40E_LINK_SPEED_40GB |
1874                         I40E_LINK_SPEED_25GB |
1875                         I40E_LINK_SPEED_10GB |
1876                         I40E_LINK_SPEED_1GB |
1877                         I40E_LINK_SPEED_100MB;
1878         int ret = -ENOTSUP;
1879
1880
1881         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1882                                               NULL);
1883         if (status)
1884                 return ret;
1885
1886         /* If link already up, no need to set up again */
1887         if (is_up && phy_ab.phy_type != 0)
1888                 return I40E_SUCCESS;
1889
1890         memset(&phy_conf, 0, sizeof(phy_conf));
1891
1892         /* bits 0-2 use the values from get_phy_abilities_resp */
1893         abilities &= ~mask;
1894         abilities |= phy_ab.abilities & mask;
1895
1896         /* update ablities and speed */
1897         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1898                 phy_conf.link_speed = advt;
1899         else
1900                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1901
1902         phy_conf.abilities = abilities;
1903
1904
1905
1906         /* To enable link, phy_type mask needs to include each type */
1907         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1908                 phy_type_mask |= 1 << cnt;
1909
1910         /* use get_phy_abilities_resp value for the rest */
1911         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1912         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1913                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1914                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1915         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1916         phy_conf.eee_capability = phy_ab.eee_capability;
1917         phy_conf.eeer = phy_ab.eeer_val;
1918         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1919
1920         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1921                     phy_ab.abilities, phy_ab.link_speed);
1922         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1923                     phy_conf.abilities, phy_conf.link_speed);
1924
1925         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1926         if (status)
1927                 return ret;
1928
1929         return I40E_SUCCESS;
1930 }
1931
1932 static int
1933 i40e_apply_link_speed(struct rte_eth_dev *dev)
1934 {
1935         uint8_t speed;
1936         uint8_t abilities = 0;
1937         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938         struct rte_eth_conf *conf = &dev->data->dev_conf;
1939
1940         speed = i40e_parse_link_speeds(conf->link_speeds);
1941         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1942         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1943                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1944         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1945
1946         return i40e_phy_conf_link(hw, abilities, speed, true);
1947 }
1948
1949 static int
1950 i40e_dev_start(struct rte_eth_dev *dev)
1951 {
1952         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1953         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1954         struct i40e_vsi *main_vsi = pf->main_vsi;
1955         int ret, i;
1956         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1957         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1958         uint32_t intr_vector = 0;
1959         struct i40e_vsi *vsi;
1960
1961         hw->adapter_stopped = 0;
1962
1963         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1964                 PMD_INIT_LOG(ERR,
1965                 "Invalid link_speeds for port %u, autonegotiation disabled",
1966                               dev->data->port_id);
1967                 return -EINVAL;
1968         }
1969
1970         rte_intr_disable(intr_handle);
1971
1972         if ((rte_intr_cap_multiple(intr_handle) ||
1973              !RTE_ETH_DEV_SRIOV(dev).active) &&
1974             dev->data->dev_conf.intr_conf.rxq != 0) {
1975                 intr_vector = dev->data->nb_rx_queues;
1976                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1977                 if (ret)
1978                         return ret;
1979         }
1980
1981         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1982                 intr_handle->intr_vec =
1983                         rte_zmalloc("intr_vec",
1984                                     dev->data->nb_rx_queues * sizeof(int),
1985                                     0);
1986                 if (!intr_handle->intr_vec) {
1987                         PMD_INIT_LOG(ERR,
1988                                 "Failed to allocate %d rx_queues intr_vec",
1989                                 dev->data->nb_rx_queues);
1990                         return -ENOMEM;
1991                 }
1992         }
1993
1994         /* Initialize VSI */
1995         ret = i40e_dev_rxtx_init(pf);
1996         if (ret != I40E_SUCCESS) {
1997                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1998                 goto err_up;
1999         }
2000
2001         /* Map queues with MSIX interrupt */
2002         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2003                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2004         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2005         i40e_vsi_enable_queues_intr(main_vsi);
2006
2007         /* Map VMDQ VSI queues with MSIX interrupt */
2008         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2009                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2010                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2011                                           I40E_ITR_INDEX_DEFAULT);
2012                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2013         }
2014
2015         /* enable FDIR MSIX interrupt */
2016         if (pf->fdir.fdir_vsi) {
2017                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2018                                           I40E_ITR_INDEX_NONE);
2019                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2020         }
2021
2022         /* Enable all queues which have been configured */
2023         ret = i40e_dev_switch_queues(pf, TRUE);
2024         if (ret != I40E_SUCCESS) {
2025                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2026                 goto err_up;
2027         }
2028
2029         /* Enable receiving broadcast packets */
2030         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2031         if (ret != I40E_SUCCESS)
2032                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2033
2034         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2035                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2036                                                 true, NULL);
2037                 if (ret != I40E_SUCCESS)
2038                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2039         }
2040
2041         /* Enable the VLAN promiscuous mode. */
2042         if (pf->vfs) {
2043                 for (i = 0; i < pf->vf_num; i++) {
2044                         vsi = pf->vfs[i].vsi;
2045                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2046                                                      true, NULL);
2047                 }
2048         }
2049
2050         /* Apply link configure */
2051         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2052                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2053                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2054                                 ETH_LINK_SPEED_40G)) {
2055                 PMD_DRV_LOG(ERR, "Invalid link setting");
2056                 goto err_up;
2057         }
2058         ret = i40e_apply_link_speed(dev);
2059         if (I40E_SUCCESS != ret) {
2060                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2061                 goto err_up;
2062         }
2063
2064         if (!rte_intr_allow_others(intr_handle)) {
2065                 rte_intr_callback_unregister(intr_handle,
2066                                              i40e_dev_interrupt_handler,
2067                                              (void *)dev);
2068                 /* configure and enable device interrupt */
2069                 i40e_pf_config_irq0(hw, FALSE);
2070                 i40e_pf_enable_irq0(hw);
2071
2072                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2073                         PMD_INIT_LOG(INFO,
2074                                 "lsc won't enable because of no intr multiplex");
2075         } else {
2076                 ret = i40e_aq_set_phy_int_mask(hw,
2077                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2078                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2079                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2080                 if (ret != I40E_SUCCESS)
2081                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2082
2083                 /* Call get_link_info aq commond to enable/disable LSE */
2084                 i40e_dev_link_update(dev, 0);
2085         }
2086
2087         /* enable uio intr after callback register */
2088         rte_intr_enable(intr_handle);
2089
2090         i40e_filter_restore(pf);
2091
2092         if (pf->tm_conf.root && !pf->tm_conf.committed)
2093                 PMD_DRV_LOG(WARNING,
2094                             "please call hierarchy_commit() "
2095                             "before starting the port");
2096
2097         return I40E_SUCCESS;
2098
2099 err_up:
2100         i40e_dev_switch_queues(pf, FALSE);
2101         i40e_dev_clear_queues(dev);
2102
2103         return ret;
2104 }
2105
2106 static void
2107 i40e_dev_stop(struct rte_eth_dev *dev)
2108 {
2109         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2110         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2111         struct i40e_vsi *main_vsi = pf->main_vsi;
2112         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2113         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2114         int i;
2115
2116         if (hw->adapter_stopped == 1)
2117                 return;
2118         /* Disable all queues */
2119         i40e_dev_switch_queues(pf, FALSE);
2120
2121         /* un-map queues with interrupt registers */
2122         i40e_vsi_disable_queues_intr(main_vsi);
2123         i40e_vsi_queues_unbind_intr(main_vsi);
2124
2125         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2126                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2127                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2128         }
2129
2130         if (pf->fdir.fdir_vsi) {
2131                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2132                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2133         }
2134         /* Clear all queues and release memory */
2135         i40e_dev_clear_queues(dev);
2136
2137         /* Set link down */
2138         i40e_dev_set_link_down(dev);
2139
2140         if (!rte_intr_allow_others(intr_handle))
2141                 /* resume to the default handler */
2142                 rte_intr_callback_register(intr_handle,
2143                                            i40e_dev_interrupt_handler,
2144                                            (void *)dev);
2145
2146         /* Clean datapath event and queue/vec mapping */
2147         rte_intr_efd_disable(intr_handle);
2148         if (intr_handle->intr_vec) {
2149                 rte_free(intr_handle->intr_vec);
2150                 intr_handle->intr_vec = NULL;
2151         }
2152
2153         /* reset hierarchy commit */
2154         pf->tm_conf.committed = false;
2155
2156         /* Remove all the queue region configuration */
2157         i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
2158
2159         hw->adapter_stopped = 1;
2160 }
2161
2162 static void
2163 i40e_dev_close(struct rte_eth_dev *dev)
2164 {
2165         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2166         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2167         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2168         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2169         struct i40e_mirror_rule *p_mirror;
2170         uint32_t reg;
2171         int i;
2172         int ret;
2173
2174         PMD_INIT_FUNC_TRACE();
2175
2176         i40e_dev_stop(dev);
2177
2178         /* Remove all mirror rules */
2179         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2180                 ret = i40e_aq_del_mirror_rule(hw,
2181                                               pf->main_vsi->veb->seid,
2182                                               p_mirror->rule_type,
2183                                               p_mirror->entries,
2184                                               p_mirror->num_entries,
2185                                               p_mirror->id);
2186                 if (ret < 0)
2187                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2188                                     "status = %d, aq_err = %d.", ret,
2189                                     hw->aq.asq_last_status);
2190
2191                 /* remove mirror software resource anyway */
2192                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2193                 rte_free(p_mirror);
2194                 pf->nb_mirror_rule--;
2195         }
2196
2197         i40e_dev_free_queues(dev);
2198
2199         /* Disable interrupt */
2200         i40e_pf_disable_irq0(hw);
2201         rte_intr_disable(intr_handle);
2202
2203         /* shutdown and destroy the HMC */
2204         i40e_shutdown_lan_hmc(hw);
2205
2206         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2207                 i40e_vsi_release(pf->vmdq[i].vsi);
2208                 pf->vmdq[i].vsi = NULL;
2209         }
2210         rte_free(pf->vmdq);
2211         pf->vmdq = NULL;
2212
2213         /* release all the existing VSIs and VEBs */
2214         i40e_fdir_teardown(pf);
2215         i40e_vsi_release(pf->main_vsi);
2216
2217         /* shutdown the adminq */
2218         i40e_aq_queue_shutdown(hw, true);
2219         i40e_shutdown_adminq(hw);
2220
2221         i40e_res_pool_destroy(&pf->qp_pool);
2222         i40e_res_pool_destroy(&pf->msix_pool);
2223
2224         /* force a PF reset to clean anything leftover */
2225         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2226         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2227                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2228         I40E_WRITE_FLUSH(hw);
2229 }
2230
2231 /*
2232  * Reset PF device only to re-initialize resources in PMD layer
2233  */
2234 static int
2235 i40e_dev_reset(struct rte_eth_dev *dev)
2236 {
2237         int ret;
2238
2239         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2240          * its VF to make them align with it. The detailed notification
2241          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2242          * To avoid unexpected behavior in VF, currently reset of PF with
2243          * SR-IOV activation is not supported. It might be supported later.
2244          */
2245         if (dev->data->sriov.active)
2246                 return -ENOTSUP;
2247
2248         ret = eth_i40e_dev_uninit(dev);
2249         if (ret)
2250                 return ret;
2251
2252         ret = eth_i40e_dev_init(dev);
2253
2254         return ret;
2255 }
2256
2257 static void
2258 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2259 {
2260         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2261         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2262         struct i40e_vsi *vsi = pf->main_vsi;
2263         int status;
2264
2265         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2266                                                      true, NULL, true);
2267         if (status != I40E_SUCCESS)
2268                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2269
2270         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2271                                                         TRUE, NULL);
2272         if (status != I40E_SUCCESS)
2273                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2274
2275 }
2276
2277 static void
2278 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2279 {
2280         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2281         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2282         struct i40e_vsi *vsi = pf->main_vsi;
2283         int status;
2284
2285         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2286                                                      false, NULL, true);
2287         if (status != I40E_SUCCESS)
2288                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2289
2290         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2291                                                         false, NULL);
2292         if (status != I40E_SUCCESS)
2293                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2294 }
2295
2296 static void
2297 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2298 {
2299         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2300         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2301         struct i40e_vsi *vsi = pf->main_vsi;
2302         int ret;
2303
2304         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2305         if (ret != I40E_SUCCESS)
2306                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2307 }
2308
2309 static void
2310 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2311 {
2312         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2313         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2314         struct i40e_vsi *vsi = pf->main_vsi;
2315         int ret;
2316
2317         if (dev->data->promiscuous == 1)
2318                 return; /* must remain in all_multicast mode */
2319
2320         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2321                                 vsi->seid, FALSE, NULL);
2322         if (ret != I40E_SUCCESS)
2323                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2324 }
2325
2326 /*
2327  * Set device link up.
2328  */
2329 static int
2330 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2331 {
2332         /* re-apply link speed setting */
2333         return i40e_apply_link_speed(dev);
2334 }
2335
2336 /*
2337  * Set device link down.
2338  */
2339 static int
2340 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2341 {
2342         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2343         uint8_t abilities = 0;
2344         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2345
2346         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2347         return i40e_phy_conf_link(hw, abilities, speed, false);
2348 }
2349
2350 int
2351 i40e_dev_link_update(struct rte_eth_dev *dev,
2352                      int wait_to_complete)
2353 {
2354 #define CHECK_INTERVAL 100  /* 100ms */
2355 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2356         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2357         struct i40e_link_status link_status;
2358         struct rte_eth_link link, old;
2359         int status;
2360         unsigned rep_cnt = MAX_REPEAT_TIME;
2361         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2362
2363         memset(&link, 0, sizeof(link));
2364         memset(&old, 0, sizeof(old));
2365         memset(&link_status, 0, sizeof(link_status));
2366         rte_i40e_dev_atomic_read_link_status(dev, &old);
2367
2368         do {
2369                 /* Get link status information from hardware */
2370                 status = i40e_aq_get_link_info(hw, enable_lse,
2371                                                 &link_status, NULL);
2372                 if (status != I40E_SUCCESS) {
2373                         link.link_speed = ETH_SPEED_NUM_100M;
2374                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2375                         PMD_DRV_LOG(ERR, "Failed to get link info");
2376                         goto out;
2377                 }
2378
2379                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2380                 if (!wait_to_complete || link.link_status)
2381                         break;
2382
2383                 rte_delay_ms(CHECK_INTERVAL);
2384         } while (--rep_cnt);
2385
2386         if (!link.link_status)
2387                 goto out;
2388
2389         /* i40e uses full duplex only */
2390         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2391
2392         /* Parse the link status */
2393         switch (link_status.link_speed) {
2394         case I40E_LINK_SPEED_100MB:
2395                 link.link_speed = ETH_SPEED_NUM_100M;
2396                 break;
2397         case I40E_LINK_SPEED_1GB:
2398                 link.link_speed = ETH_SPEED_NUM_1G;
2399                 break;
2400         case I40E_LINK_SPEED_10GB:
2401                 link.link_speed = ETH_SPEED_NUM_10G;
2402                 break;
2403         case I40E_LINK_SPEED_20GB:
2404                 link.link_speed = ETH_SPEED_NUM_20G;
2405                 break;
2406         case I40E_LINK_SPEED_25GB:
2407                 link.link_speed = ETH_SPEED_NUM_25G;
2408                 break;
2409         case I40E_LINK_SPEED_40GB:
2410                 link.link_speed = ETH_SPEED_NUM_40G;
2411                 break;
2412         default:
2413                 link.link_speed = ETH_SPEED_NUM_100M;
2414                 break;
2415         }
2416
2417         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2418                         ETH_LINK_SPEED_FIXED);
2419
2420 out:
2421         rte_i40e_dev_atomic_write_link_status(dev, &link);
2422         if (link.link_status == old.link_status)
2423                 return -1;
2424
2425         i40e_notify_all_vfs_link_status(dev);
2426
2427         return 0;
2428 }
2429
2430 /* Get all the statistics of a VSI */
2431 void
2432 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2433 {
2434         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2435         struct i40e_eth_stats *nes = &vsi->eth_stats;
2436         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2437         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2438
2439         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2440                             vsi->offset_loaded, &oes->rx_bytes,
2441                             &nes->rx_bytes);
2442         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2443                             vsi->offset_loaded, &oes->rx_unicast,
2444                             &nes->rx_unicast);
2445         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2446                             vsi->offset_loaded, &oes->rx_multicast,
2447                             &nes->rx_multicast);
2448         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2449                             vsi->offset_loaded, &oes->rx_broadcast,
2450                             &nes->rx_broadcast);
2451         /* exclude CRC bytes */
2452         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2453                 nes->rx_broadcast) * ETHER_CRC_LEN;
2454
2455         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2456                             &oes->rx_discards, &nes->rx_discards);
2457         /* GLV_REPC not supported */
2458         /* GLV_RMPC not supported */
2459         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2460                             &oes->rx_unknown_protocol,
2461                             &nes->rx_unknown_protocol);
2462         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2463                             vsi->offset_loaded, &oes->tx_bytes,
2464                             &nes->tx_bytes);
2465         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2466                             vsi->offset_loaded, &oes->tx_unicast,
2467                             &nes->tx_unicast);
2468         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2469                             vsi->offset_loaded, &oes->tx_multicast,
2470                             &nes->tx_multicast);
2471         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2472                             vsi->offset_loaded,  &oes->tx_broadcast,
2473                             &nes->tx_broadcast);
2474         /* GLV_TDPC not supported */
2475         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2476                             &oes->tx_errors, &nes->tx_errors);
2477         vsi->offset_loaded = true;
2478
2479         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2480                     vsi->vsi_id);
2481         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2482         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2483         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2484         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2485         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2486         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2487                     nes->rx_unknown_protocol);
2488         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2489         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2490         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2491         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2492         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2493         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2494         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2495                     vsi->vsi_id);
2496 }
2497
2498 static void
2499 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2500 {
2501         unsigned int i;
2502         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2503         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2504
2505         /* Get rx/tx bytes of internal transfer packets */
2506         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2507                         I40E_GLV_GORCL(hw->port),
2508                         pf->offset_loaded,
2509                         &pf->internal_stats_offset.rx_bytes,
2510                         &pf->internal_stats.rx_bytes);
2511
2512         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2513                         I40E_GLV_GOTCL(hw->port),
2514                         pf->offset_loaded,
2515                         &pf->internal_stats_offset.tx_bytes,
2516                         &pf->internal_stats.tx_bytes);
2517         /* Get total internal rx packet count */
2518         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2519                             I40E_GLV_UPRCL(hw->port),
2520                             pf->offset_loaded,
2521                             &pf->internal_stats_offset.rx_unicast,
2522                             &pf->internal_stats.rx_unicast);
2523         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2524                             I40E_GLV_MPRCL(hw->port),
2525                             pf->offset_loaded,
2526                             &pf->internal_stats_offset.rx_multicast,
2527                             &pf->internal_stats.rx_multicast);
2528         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2529                             I40E_GLV_BPRCL(hw->port),
2530                             pf->offset_loaded,
2531                             &pf->internal_stats_offset.rx_broadcast,
2532                             &pf->internal_stats.rx_broadcast);
2533
2534         /* exclude CRC size */
2535         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2536                 pf->internal_stats.rx_multicast +
2537                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2538
2539         /* Get statistics of struct i40e_eth_stats */
2540         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2541                             I40E_GLPRT_GORCL(hw->port),
2542                             pf->offset_loaded, &os->eth.rx_bytes,
2543                             &ns->eth.rx_bytes);
2544         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2545                             I40E_GLPRT_UPRCL(hw->port),
2546                             pf->offset_loaded, &os->eth.rx_unicast,
2547                             &ns->eth.rx_unicast);
2548         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2549                             I40E_GLPRT_MPRCL(hw->port),
2550                             pf->offset_loaded, &os->eth.rx_multicast,
2551                             &ns->eth.rx_multicast);
2552         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2553                             I40E_GLPRT_BPRCL(hw->port),
2554                             pf->offset_loaded, &os->eth.rx_broadcast,
2555                             &ns->eth.rx_broadcast);
2556         /* Workaround: CRC size should not be included in byte statistics,
2557          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2558          */
2559         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2560                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2561
2562         /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2563          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2564          * value.
2565          */
2566         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2567                 ns->eth.rx_bytes = 0;
2568         /* exlude internal rx bytes */
2569         else
2570                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2571
2572         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2573                             pf->offset_loaded, &os->eth.rx_discards,
2574                             &ns->eth.rx_discards);
2575         /* GLPRT_REPC not supported */
2576         /* GLPRT_RMPC not supported */
2577         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2578                             pf->offset_loaded,
2579                             &os->eth.rx_unknown_protocol,
2580                             &ns->eth.rx_unknown_protocol);
2581         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2582                             I40E_GLPRT_GOTCL(hw->port),
2583                             pf->offset_loaded, &os->eth.tx_bytes,
2584                             &ns->eth.tx_bytes);
2585         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2586                             I40E_GLPRT_UPTCL(hw->port),
2587                             pf->offset_loaded, &os->eth.tx_unicast,
2588                             &ns->eth.tx_unicast);
2589         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2590                             I40E_GLPRT_MPTCL(hw->port),
2591                             pf->offset_loaded, &os->eth.tx_multicast,
2592                             &ns->eth.tx_multicast);
2593         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2594                             I40E_GLPRT_BPTCL(hw->port),
2595                             pf->offset_loaded, &os->eth.tx_broadcast,
2596                             &ns->eth.tx_broadcast);
2597         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2598                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2599
2600         /* exclude internal tx bytes */
2601         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2602                 ns->eth.tx_bytes = 0;
2603         else
2604                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2605
2606         /* GLPRT_TEPC not supported */
2607
2608         /* additional port specific stats */
2609         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2610                             pf->offset_loaded, &os->tx_dropped_link_down,
2611                             &ns->tx_dropped_link_down);
2612         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2613                             pf->offset_loaded, &os->crc_errors,
2614                             &ns->crc_errors);
2615         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2616                             pf->offset_loaded, &os->illegal_bytes,
2617                             &ns->illegal_bytes);
2618         /* GLPRT_ERRBC not supported */
2619         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2620                             pf->offset_loaded, &os->mac_local_faults,
2621                             &ns->mac_local_faults);
2622         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2623                             pf->offset_loaded, &os->mac_remote_faults,
2624                             &ns->mac_remote_faults);
2625         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2626                             pf->offset_loaded, &os->rx_length_errors,
2627                             &ns->rx_length_errors);
2628         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2629                             pf->offset_loaded, &os->link_xon_rx,
2630                             &ns->link_xon_rx);
2631         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2632                             pf->offset_loaded, &os->link_xoff_rx,
2633                             &ns->link_xoff_rx);
2634         for (i = 0; i < 8; i++) {
2635                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2636                                     pf->offset_loaded,
2637                                     &os->priority_xon_rx[i],
2638                                     &ns->priority_xon_rx[i]);
2639                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2640                                     pf->offset_loaded,
2641                                     &os->priority_xoff_rx[i],
2642                                     &ns->priority_xoff_rx[i]);
2643         }
2644         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2645                             pf->offset_loaded, &os->link_xon_tx,
2646                             &ns->link_xon_tx);
2647         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2648                             pf->offset_loaded, &os->link_xoff_tx,
2649                             &ns->link_xoff_tx);
2650         for (i = 0; i < 8; i++) {
2651                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2652                                     pf->offset_loaded,
2653                                     &os->priority_xon_tx[i],
2654                                     &ns->priority_xon_tx[i]);
2655                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2656                                     pf->offset_loaded,
2657                                     &os->priority_xoff_tx[i],
2658                                     &ns->priority_xoff_tx[i]);
2659                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2660                                     pf->offset_loaded,
2661                                     &os->priority_xon_2_xoff[i],
2662                                     &ns->priority_xon_2_xoff[i]);
2663         }
2664         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2665                             I40E_GLPRT_PRC64L(hw->port),
2666                             pf->offset_loaded, &os->rx_size_64,
2667                             &ns->rx_size_64);
2668         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2669                             I40E_GLPRT_PRC127L(hw->port),
2670                             pf->offset_loaded, &os->rx_size_127,
2671                             &ns->rx_size_127);
2672         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2673                             I40E_GLPRT_PRC255L(hw->port),
2674                             pf->offset_loaded, &os->rx_size_255,
2675                             &ns->rx_size_255);
2676         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2677                             I40E_GLPRT_PRC511L(hw->port),
2678                             pf->offset_loaded, &os->rx_size_511,
2679                             &ns->rx_size_511);
2680         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2681                             I40E_GLPRT_PRC1023L(hw->port),
2682                             pf->offset_loaded, &os->rx_size_1023,
2683                             &ns->rx_size_1023);
2684         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2685                             I40E_GLPRT_PRC1522L(hw->port),
2686                             pf->offset_loaded, &os->rx_size_1522,
2687                             &ns->rx_size_1522);
2688         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2689                             I40E_GLPRT_PRC9522L(hw->port),
2690                             pf->offset_loaded, &os->rx_size_big,
2691                             &ns->rx_size_big);
2692         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2693                             pf->offset_loaded, &os->rx_undersize,
2694                             &ns->rx_undersize);
2695         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2696                             pf->offset_loaded, &os->rx_fragments,
2697                             &ns->rx_fragments);
2698         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2699                             pf->offset_loaded, &os->rx_oversize,
2700                             &ns->rx_oversize);
2701         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2702                             pf->offset_loaded, &os->rx_jabber,
2703                             &ns->rx_jabber);
2704         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2705                             I40E_GLPRT_PTC64L(hw->port),
2706                             pf->offset_loaded, &os->tx_size_64,
2707                             &ns->tx_size_64);
2708         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2709                             I40E_GLPRT_PTC127L(hw->port),
2710                             pf->offset_loaded, &os->tx_size_127,
2711                             &ns->tx_size_127);
2712         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2713                             I40E_GLPRT_PTC255L(hw->port),
2714                             pf->offset_loaded, &os->tx_size_255,
2715                             &ns->tx_size_255);
2716         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2717                             I40E_GLPRT_PTC511L(hw->port),
2718                             pf->offset_loaded, &os->tx_size_511,
2719                             &ns->tx_size_511);
2720         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2721                             I40E_GLPRT_PTC1023L(hw->port),
2722                             pf->offset_loaded, &os->tx_size_1023,
2723                             &ns->tx_size_1023);
2724         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2725                             I40E_GLPRT_PTC1522L(hw->port),
2726                             pf->offset_loaded, &os->tx_size_1522,
2727                             &ns->tx_size_1522);
2728         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2729                             I40E_GLPRT_PTC9522L(hw->port),
2730                             pf->offset_loaded, &os->tx_size_big,
2731                             &ns->tx_size_big);
2732         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2733                            pf->offset_loaded,
2734                            &os->fd_sb_match, &ns->fd_sb_match);
2735         /* GLPRT_MSPDC not supported */
2736         /* GLPRT_XEC not supported */
2737
2738         pf->offset_loaded = true;
2739
2740         if (pf->main_vsi)
2741                 i40e_update_vsi_stats(pf->main_vsi);
2742 }
2743
2744 /* Get all statistics of a port */
2745 static int
2746 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2747 {
2748         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2749         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2750         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2751         unsigned i;
2752
2753         /* call read registers - updates values, now write them to struct */
2754         i40e_read_stats_registers(pf, hw);
2755
2756         stats->ipackets = ns->eth.rx_unicast +
2757                         ns->eth.rx_multicast +
2758                         ns->eth.rx_broadcast -
2759                         ns->eth.rx_discards -
2760                         pf->main_vsi->eth_stats.rx_discards;
2761         stats->opackets = ns->eth.tx_unicast +
2762                         ns->eth.tx_multicast +
2763                         ns->eth.tx_broadcast;
2764         stats->ibytes   = ns->eth.rx_bytes;
2765         stats->obytes   = ns->eth.tx_bytes;
2766         stats->oerrors  = ns->eth.tx_errors +
2767                         pf->main_vsi->eth_stats.tx_errors;
2768
2769         /* Rx Errors */
2770         stats->imissed  = ns->eth.rx_discards +
2771                         pf->main_vsi->eth_stats.rx_discards;
2772         stats->ierrors  = ns->crc_errors +
2773                         ns->rx_length_errors + ns->rx_undersize +
2774                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2775
2776         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2777         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2778         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2779         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2780         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2781         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2782         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2783                     ns->eth.rx_unknown_protocol);
2784         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2785         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2786         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2787         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2788         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2789         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2790
2791         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2792                     ns->tx_dropped_link_down);
2793         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2794         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2795                     ns->illegal_bytes);
2796         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2797         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2798                     ns->mac_local_faults);
2799         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2800                     ns->mac_remote_faults);
2801         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2802                     ns->rx_length_errors);
2803         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2804         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2805         for (i = 0; i < 8; i++) {
2806                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2807                                 i, ns->priority_xon_rx[i]);
2808                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2809                                 i, ns->priority_xoff_rx[i]);
2810         }
2811         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2812         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2813         for (i = 0; i < 8; i++) {
2814                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2815                                 i, ns->priority_xon_tx[i]);
2816                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2817                                 i, ns->priority_xoff_tx[i]);
2818                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2819                                 i, ns->priority_xon_2_xoff[i]);
2820         }
2821         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2822         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2823         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2824         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2825         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2826         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2827         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2828         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2829         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2830         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2831         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2832         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2833         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2834         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2835         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2836         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2837         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2838         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2839         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2840                         ns->mac_short_packet_dropped);
2841         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2842                     ns->checksum_error);
2843         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2844         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2845         return 0;
2846 }
2847
2848 /* Reset the statistics */
2849 static void
2850 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2851 {
2852         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2853         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2854
2855         /* Mark PF and VSI stats to update the offset, aka "reset" */
2856         pf->offset_loaded = false;
2857         if (pf->main_vsi)
2858                 pf->main_vsi->offset_loaded = false;
2859
2860         /* read the stats, reading current register values into offset */
2861         i40e_read_stats_registers(pf, hw);
2862 }
2863
2864 static uint32_t
2865 i40e_xstats_calc_num(void)
2866 {
2867         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2868                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2869                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2870 }
2871
2872 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2873                                      struct rte_eth_xstat_name *xstats_names,
2874                                      __rte_unused unsigned limit)
2875 {
2876         unsigned count = 0;
2877         unsigned i, prio;
2878
2879         if (xstats_names == NULL)
2880                 return i40e_xstats_calc_num();
2881
2882         /* Note: limit checked in rte_eth_xstats_names() */
2883
2884         /* Get stats from i40e_eth_stats struct */
2885         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2886                 snprintf(xstats_names[count].name,
2887                          sizeof(xstats_names[count].name),
2888                          "%s", rte_i40e_stats_strings[i].name);
2889                 count++;
2890         }
2891
2892         /* Get individiual stats from i40e_hw_port struct */
2893         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2894                 snprintf(xstats_names[count].name,
2895                         sizeof(xstats_names[count].name),
2896                          "%s", rte_i40e_hw_port_strings[i].name);
2897                 count++;
2898         }
2899
2900         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2901                 for (prio = 0; prio < 8; prio++) {
2902                         snprintf(xstats_names[count].name,
2903                                  sizeof(xstats_names[count].name),
2904                                  "rx_priority%u_%s", prio,
2905                                  rte_i40e_rxq_prio_strings[i].name);
2906                         count++;
2907                 }
2908         }
2909
2910         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2911                 for (prio = 0; prio < 8; prio++) {
2912                         snprintf(xstats_names[count].name,
2913                                  sizeof(xstats_names[count].name),
2914                                  "tx_priority%u_%s", prio,
2915                                  rte_i40e_txq_prio_strings[i].name);
2916                         count++;
2917                 }
2918         }
2919         return count;
2920 }
2921
2922 static int
2923 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2924                     unsigned n)
2925 {
2926         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2927         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2928         unsigned i, count, prio;
2929         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2930
2931         count = i40e_xstats_calc_num();
2932         if (n < count)
2933                 return count;
2934
2935         i40e_read_stats_registers(pf, hw);
2936
2937         if (xstats == NULL)
2938                 return 0;
2939
2940         count = 0;
2941
2942         /* Get stats from i40e_eth_stats struct */
2943         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2944                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2945                         rte_i40e_stats_strings[i].offset);
2946                 xstats[count].id = count;
2947                 count++;
2948         }
2949
2950         /* Get individiual stats from i40e_hw_port struct */
2951         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2952                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2953                         rte_i40e_hw_port_strings[i].offset);
2954                 xstats[count].id = count;
2955                 count++;
2956         }
2957
2958         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2959                 for (prio = 0; prio < 8; prio++) {
2960                         xstats[count].value =
2961                                 *(uint64_t *)(((char *)hw_stats) +
2962                                 rte_i40e_rxq_prio_strings[i].offset +
2963                                 (sizeof(uint64_t) * prio));
2964                         xstats[count].id = count;
2965                         count++;
2966                 }
2967         }
2968
2969         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2970                 for (prio = 0; prio < 8; prio++) {
2971                         xstats[count].value =
2972                                 *(uint64_t *)(((char *)hw_stats) +
2973                                 rte_i40e_txq_prio_strings[i].offset +
2974                                 (sizeof(uint64_t) * prio));
2975                         xstats[count].id = count;
2976                         count++;
2977                 }
2978         }
2979
2980         return count;
2981 }
2982
2983 static int
2984 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2985                                  __rte_unused uint16_t queue_id,
2986                                  __rte_unused uint8_t stat_idx,
2987                                  __rte_unused uint8_t is_rx)
2988 {
2989         PMD_INIT_FUNC_TRACE();
2990
2991         return -ENOSYS;
2992 }
2993
2994 static int
2995 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2996 {
2997         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2998         u32 full_ver;
2999         u8 ver, patch;
3000         u16 build;
3001         int ret;
3002
3003         full_ver = hw->nvm.oem_ver;
3004         ver = (u8)(full_ver >> 24);
3005         build = (u16)((full_ver >> 8) & 0xffff);
3006         patch = (u8)(full_ver & 0xff);
3007
3008         ret = snprintf(fw_version, fw_size,
3009                  "%d.%d%d 0x%08x %d.%d.%d",
3010                  ((hw->nvm.version >> 12) & 0xf),
3011                  ((hw->nvm.version >> 4) & 0xff),
3012                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3013                  ver, build, patch);
3014
3015         ret += 1; /* add the size of '\0' */
3016         if (fw_size < (u32)ret)
3017                 return ret;
3018         else
3019                 return 0;
3020 }
3021
3022 static void
3023 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3024 {
3025         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3026         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3027         struct i40e_vsi *vsi = pf->main_vsi;
3028         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3029
3030         dev_info->pci_dev = pci_dev;
3031         dev_info->max_rx_queues = vsi->nb_qps;
3032         dev_info->max_tx_queues = vsi->nb_qps;
3033         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3034         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3035         dev_info->max_mac_addrs = vsi->max_macaddrs;
3036         dev_info->max_vfs = pci_dev->max_vfs;
3037         dev_info->rx_offload_capa =
3038                 DEV_RX_OFFLOAD_VLAN_STRIP |
3039                 DEV_RX_OFFLOAD_QINQ_STRIP |
3040                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3041                 DEV_RX_OFFLOAD_UDP_CKSUM |
3042                 DEV_RX_OFFLOAD_TCP_CKSUM;
3043         dev_info->tx_offload_capa =
3044                 DEV_TX_OFFLOAD_VLAN_INSERT |
3045                 DEV_TX_OFFLOAD_QINQ_INSERT |
3046                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3047                 DEV_TX_OFFLOAD_UDP_CKSUM |
3048                 DEV_TX_OFFLOAD_TCP_CKSUM |
3049                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3050                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3051                 DEV_TX_OFFLOAD_TCP_TSO |
3052                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3053                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3054                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3055                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3056         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3057                                                 sizeof(uint32_t);
3058         dev_info->reta_size = pf->hash_lut_size;
3059         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3060
3061         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3062                 .rx_thresh = {
3063                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3064                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3065                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3066                 },
3067                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3068                 .rx_drop_en = 0,
3069         };
3070
3071         dev_info->default_txconf = (struct rte_eth_txconf) {
3072                 .tx_thresh = {
3073                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3074                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3075                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3076                 },
3077                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3078                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3079                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3080                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3081         };
3082
3083         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3084                 .nb_max = I40E_MAX_RING_DESC,
3085                 .nb_min = I40E_MIN_RING_DESC,
3086                 .nb_align = I40E_ALIGN_RING_DESC,
3087         };
3088
3089         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3090                 .nb_max = I40E_MAX_RING_DESC,
3091                 .nb_min = I40E_MIN_RING_DESC,
3092                 .nb_align = I40E_ALIGN_RING_DESC,
3093                 .nb_seg_max = I40E_TX_MAX_SEG,
3094                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3095         };
3096
3097         if (pf->flags & I40E_FLAG_VMDQ) {
3098                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3099                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3100                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3101                                                 pf->max_nb_vmdq_vsi;
3102                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3103                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3104                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3105         }
3106
3107         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3108                 /* For XL710 */
3109                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3110         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3111                 /* For XXV710 */
3112                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3113         else
3114                 /* For X710 */
3115                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3116 }
3117
3118 static int
3119 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3120 {
3121         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3122         struct i40e_vsi *vsi = pf->main_vsi;
3123         PMD_INIT_FUNC_TRACE();
3124
3125         if (on)
3126                 return i40e_vsi_add_vlan(vsi, vlan_id);
3127         else
3128                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3129 }
3130
3131 static int
3132 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3133                                 enum rte_vlan_type vlan_type,
3134                                 uint16_t tpid, int qinq)
3135 {
3136         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3137         uint64_t reg_r = 0;
3138         uint64_t reg_w = 0;
3139         uint16_t reg_id = 3;
3140         int ret;
3141
3142         if (qinq) {
3143                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3144                         reg_id = 2;
3145         }
3146
3147         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3148                                           &reg_r, NULL);
3149         if (ret != I40E_SUCCESS) {
3150                 PMD_DRV_LOG(ERR,
3151                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3152                            reg_id);
3153                 return -EIO;
3154         }
3155         PMD_DRV_LOG(DEBUG,
3156                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3157                     reg_id, reg_r);
3158
3159         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3160         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3161         if (reg_r == reg_w) {
3162                 PMD_DRV_LOG(DEBUG, "No need to write");
3163                 return 0;
3164         }
3165
3166         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3167                                            reg_w, NULL);
3168         if (ret != I40E_SUCCESS) {
3169                 PMD_DRV_LOG(ERR,
3170                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3171                             reg_id);
3172                 return -EIO;
3173         }
3174         PMD_DRV_LOG(DEBUG,
3175                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3176                     reg_w, reg_id);
3177
3178         return 0;
3179 }
3180
3181 static int
3182 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3183                    enum rte_vlan_type vlan_type,
3184                    uint16_t tpid)
3185 {
3186         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3187         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3188         int ret = 0;
3189
3190         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3191              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3192             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3193                 PMD_DRV_LOG(ERR,
3194                             "Unsupported vlan type.");
3195                 return -EINVAL;
3196         }
3197         /* 802.1ad frames ability is added in NVM API 1.7*/
3198         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3199                 if (qinq) {
3200                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3201                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3202                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3203                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3204                 } else {
3205                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3206                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3207                 }
3208                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3209                 if (ret != I40E_SUCCESS) {
3210                         PMD_DRV_LOG(ERR,
3211                                     "Set switch config failed aq_err: %d",
3212                                     hw->aq.asq_last_status);
3213                         ret = -EIO;
3214                 }
3215         } else
3216                 /* If NVM API < 1.7, keep the register setting */
3217                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3218                                                       tpid, qinq);
3219
3220         return ret;
3221 }
3222
3223 static void
3224 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3225 {
3226         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3227         struct i40e_vsi *vsi = pf->main_vsi;
3228
3229         if (mask & ETH_VLAN_FILTER_MASK) {
3230                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3231                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3232                 else
3233                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3234         }
3235
3236         if (mask & ETH_VLAN_STRIP_MASK) {
3237                 /* Enable or disable VLAN stripping */
3238                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3239                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3240                 else
3241                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3242         }
3243
3244         if (mask & ETH_VLAN_EXTEND_MASK) {
3245                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3246                         i40e_vsi_config_double_vlan(vsi, TRUE);
3247                         /* Set global registers with default ethertype. */
3248                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3249                                            ETHER_TYPE_VLAN);
3250                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3251                                            ETHER_TYPE_VLAN);
3252                 }
3253                 else
3254                         i40e_vsi_config_double_vlan(vsi, FALSE);
3255         }
3256 }
3257
3258 static void
3259 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3260                           __rte_unused uint16_t queue,
3261                           __rte_unused int on)
3262 {
3263         PMD_INIT_FUNC_TRACE();
3264 }
3265
3266 static int
3267 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3268 {
3269         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3270         struct i40e_vsi *vsi = pf->main_vsi;
3271         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3272         struct i40e_vsi_vlan_pvid_info info;
3273
3274         memset(&info, 0, sizeof(info));
3275         info.on = on;
3276         if (info.on)
3277                 info.config.pvid = pvid;
3278         else {
3279                 info.config.reject.tagged =
3280                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3281                 info.config.reject.untagged =
3282                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3283         }
3284
3285         return i40e_vsi_vlan_pvid_set(vsi, &info);
3286 }
3287
3288 static int
3289 i40e_dev_led_on(struct rte_eth_dev *dev)
3290 {
3291         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3292         uint32_t mode = i40e_led_get(hw);
3293
3294         if (mode == 0)
3295                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3296
3297         return 0;
3298 }
3299
3300 static int
3301 i40e_dev_led_off(struct rte_eth_dev *dev)
3302 {
3303         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3304         uint32_t mode = i40e_led_get(hw);
3305
3306         if (mode != 0)
3307                 i40e_led_set(hw, 0, false);
3308
3309         return 0;
3310 }
3311
3312 static int
3313 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3314 {
3315         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3316         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3317
3318         fc_conf->pause_time = pf->fc_conf.pause_time;
3319
3320         /* read out from register, in case they are modified by other port */
3321         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3322                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3323         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3324                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3325
3326         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3327         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3328
3329          /* Return current mode according to actual setting*/
3330         switch (hw->fc.current_mode) {
3331         case I40E_FC_FULL:
3332                 fc_conf->mode = RTE_FC_FULL;
3333                 break;
3334         case I40E_FC_TX_PAUSE:
3335                 fc_conf->mode = RTE_FC_TX_PAUSE;
3336                 break;
3337         case I40E_FC_RX_PAUSE:
3338                 fc_conf->mode = RTE_FC_RX_PAUSE;
3339                 break;
3340         case I40E_FC_NONE:
3341         default:
3342                 fc_conf->mode = RTE_FC_NONE;
3343         };
3344
3345         return 0;
3346 }
3347
3348 static int
3349 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3350 {
3351         uint32_t mflcn_reg, fctrl_reg, reg;
3352         uint32_t max_high_water;
3353         uint8_t i, aq_failure;
3354         int err;
3355         struct i40e_hw *hw;
3356         struct i40e_pf *pf;
3357         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3358                 [RTE_FC_NONE] = I40E_FC_NONE,
3359                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3360                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3361                 [RTE_FC_FULL] = I40E_FC_FULL
3362         };
3363
3364         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3365
3366         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3367         if ((fc_conf->high_water > max_high_water) ||
3368                         (fc_conf->high_water < fc_conf->low_water)) {
3369                 PMD_INIT_LOG(ERR,
3370                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3371                         max_high_water);
3372                 return -EINVAL;
3373         }
3374
3375         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3376         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3377         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3378
3379         pf->fc_conf.pause_time = fc_conf->pause_time;
3380         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3381         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3382
3383         PMD_INIT_FUNC_TRACE();
3384
3385         /* All the link flow control related enable/disable register
3386          * configuration is handle by the F/W
3387          */
3388         err = i40e_set_fc(hw, &aq_failure, true);
3389         if (err < 0)
3390                 return -ENOSYS;
3391
3392         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3393                 /* Configure flow control refresh threshold,
3394                  * the value for stat_tx_pause_refresh_timer[8]
3395                  * is used for global pause operation.
3396                  */
3397
3398                 I40E_WRITE_REG(hw,
3399                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3400                                pf->fc_conf.pause_time);
3401
3402                 /* configure the timer value included in transmitted pause
3403                  * frame,
3404                  * the value for stat_tx_pause_quanta[8] is used for global
3405                  * pause operation
3406                  */
3407                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3408                                pf->fc_conf.pause_time);
3409
3410                 fctrl_reg = I40E_READ_REG(hw,
3411                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3412
3413                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3414                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3415                 else
3416                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3417
3418                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3419                                fctrl_reg);
3420         } else {
3421                 /* Configure pause time (2 TCs per register) */
3422                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3423                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3424                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3425
3426                 /* Configure flow control refresh threshold value */
3427                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3428                                pf->fc_conf.pause_time / 2);
3429
3430                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3431
3432                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3433                  *depending on configuration
3434                  */
3435                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3436                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3437                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3438                 } else {
3439                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3440                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3441                 }
3442
3443                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3444         }
3445
3446         /* config the water marker both based on the packets and bytes */
3447         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3448                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3449                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3450         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3451                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3452                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3453         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3454                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3455                        << I40E_KILOSHIFT);
3456         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3457                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3458                        << I40E_KILOSHIFT);
3459
3460         I40E_WRITE_FLUSH(hw);
3461
3462         return 0;
3463 }
3464
3465 static int
3466 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3467                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3468 {
3469         PMD_INIT_FUNC_TRACE();
3470
3471         return -ENOSYS;
3472 }
3473
3474 /* Add a MAC address, and update filters */
3475 static int
3476 i40e_macaddr_add(struct rte_eth_dev *dev,
3477                  struct ether_addr *mac_addr,
3478                  __rte_unused uint32_t index,
3479                  uint32_t pool)
3480 {
3481         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3482         struct i40e_mac_filter_info mac_filter;
3483         struct i40e_vsi *vsi;
3484         int ret;
3485
3486         /* If VMDQ not enabled or configured, return */
3487         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3488                           !pf->nb_cfg_vmdq_vsi)) {
3489                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3490                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3491                         pool);
3492                 return -ENOTSUP;
3493         }
3494
3495         if (pool > pf->nb_cfg_vmdq_vsi) {
3496                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3497                                 pool, pf->nb_cfg_vmdq_vsi);
3498                 return -EINVAL;
3499         }
3500
3501         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3502         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3503                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3504         else
3505                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3506
3507         if (pool == 0)
3508                 vsi = pf->main_vsi;
3509         else
3510                 vsi = pf->vmdq[pool - 1].vsi;
3511
3512         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3513         if (ret != I40E_SUCCESS) {
3514                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3515                 return -ENODEV;
3516         }
3517         return 0;
3518 }
3519
3520 /* Remove a MAC address, and update filters */
3521 static void
3522 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3523 {
3524         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3525         struct i40e_vsi *vsi;
3526         struct rte_eth_dev_data *data = dev->data;
3527         struct ether_addr *macaddr;
3528         int ret;
3529         uint32_t i;
3530         uint64_t pool_sel;
3531
3532         macaddr = &(data->mac_addrs[index]);
3533
3534         pool_sel = dev->data->mac_pool_sel[index];
3535
3536         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3537                 if (pool_sel & (1ULL << i)) {
3538                         if (i == 0)
3539                                 vsi = pf->main_vsi;
3540                         else {
3541                                 /* No VMDQ pool enabled or configured */
3542                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3543                                         (i > pf->nb_cfg_vmdq_vsi)) {
3544                                         PMD_DRV_LOG(ERR,
3545                                                 "No VMDQ pool enabled/configured");
3546                                         return;
3547                                 }
3548                                 vsi = pf->vmdq[i - 1].vsi;
3549                         }
3550                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3551
3552                         if (ret) {
3553                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3554                                 return;
3555                         }
3556                 }
3557         }
3558 }
3559
3560 /* Set perfect match or hash match of MAC and VLAN for a VF */
3561 static int
3562 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3563                  struct rte_eth_mac_filter *filter,
3564                  bool add)
3565 {
3566         struct i40e_hw *hw;
3567         struct i40e_mac_filter_info mac_filter;
3568         struct ether_addr old_mac;
3569         struct ether_addr *new_mac;
3570         struct i40e_pf_vf *vf = NULL;
3571         uint16_t vf_id;
3572         int ret;
3573
3574         if (pf == NULL) {
3575                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3576                 return -EINVAL;
3577         }
3578         hw = I40E_PF_TO_HW(pf);
3579
3580         if (filter == NULL) {
3581                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3582                 return -EINVAL;
3583         }
3584
3585         new_mac = &filter->mac_addr;
3586
3587         if (is_zero_ether_addr(new_mac)) {
3588                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3589                 return -EINVAL;
3590         }
3591
3592         vf_id = filter->dst_id;
3593
3594         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3595                 PMD_DRV_LOG(ERR, "Invalid argument.");
3596                 return -EINVAL;
3597         }
3598         vf = &pf->vfs[vf_id];
3599
3600         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3601                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3602                 return -EINVAL;
3603         }
3604
3605         if (add) {
3606                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3607                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3608                                 ETHER_ADDR_LEN);
3609                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3610                                  ETHER_ADDR_LEN);
3611
3612                 mac_filter.filter_type = filter->filter_type;
3613                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3614                 if (ret != I40E_SUCCESS) {
3615                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3616                         return -1;
3617                 }
3618                 ether_addr_copy(new_mac, &pf->dev_addr);
3619         } else {
3620                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3621                                 ETHER_ADDR_LEN);
3622                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3623                 if (ret != I40E_SUCCESS) {
3624                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3625                         return -1;
3626                 }
3627
3628                 /* Clear device address as it has been removed */
3629                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3630                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3631         }
3632
3633         return 0;
3634 }
3635
3636 /* MAC filter handle */
3637 static int
3638 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3639                 void *arg)
3640 {
3641         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3642         struct rte_eth_mac_filter *filter;
3643         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3644         int ret = I40E_NOT_SUPPORTED;
3645
3646         filter = (struct rte_eth_mac_filter *)(arg);
3647
3648         switch (filter_op) {
3649         case RTE_ETH_FILTER_NOP:
3650                 ret = I40E_SUCCESS;
3651                 break;
3652         case RTE_ETH_FILTER_ADD:
3653                 i40e_pf_disable_irq0(hw);
3654                 if (filter->is_vf)
3655                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3656                 i40e_pf_enable_irq0(hw);
3657                 break;
3658         case RTE_ETH_FILTER_DELETE:
3659                 i40e_pf_disable_irq0(hw);
3660                 if (filter->is_vf)
3661                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3662                 i40e_pf_enable_irq0(hw);
3663                 break;
3664         default:
3665                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3666                 ret = I40E_ERR_PARAM;
3667                 break;
3668         }
3669
3670         return ret;
3671 }
3672
3673 static int
3674 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3675 {
3676         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3677         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3678         int ret;
3679
3680         if (!lut)
3681                 return -EINVAL;
3682
3683         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3684                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3685                                           lut, lut_size);
3686                 if (ret) {
3687                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3688                         return ret;
3689                 }
3690         } else {
3691                 uint32_t *lut_dw = (uint32_t *)lut;
3692                 uint16_t i, lut_size_dw = lut_size / 4;
3693
3694                 for (i = 0; i < lut_size_dw; i++)
3695                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3696         }
3697
3698         return 0;
3699 }
3700
3701 static int
3702 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3703 {
3704         struct i40e_pf *pf;
3705         struct i40e_hw *hw;
3706         int ret;
3707
3708         if (!vsi || !lut)
3709                 return -EINVAL;
3710
3711         pf = I40E_VSI_TO_PF(vsi);
3712         hw = I40E_VSI_TO_HW(vsi);
3713
3714         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3715                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3716                                           lut, lut_size);
3717                 if (ret) {
3718                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3719                         return ret;
3720                 }
3721         } else {
3722                 uint32_t *lut_dw = (uint32_t *)lut;
3723                 uint16_t i, lut_size_dw = lut_size / 4;
3724
3725                 for (i = 0; i < lut_size_dw; i++)
3726                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3727                 I40E_WRITE_FLUSH(hw);
3728         }
3729
3730         return 0;
3731 }
3732
3733 static int
3734 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3735                          struct rte_eth_rss_reta_entry64 *reta_conf,
3736                          uint16_t reta_size)
3737 {
3738         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3739         uint16_t i, lut_size = pf->hash_lut_size;
3740         uint16_t idx, shift;
3741         uint8_t *lut;
3742         int ret;
3743
3744         if (reta_size != lut_size ||
3745                 reta_size > ETH_RSS_RETA_SIZE_512) {
3746                 PMD_DRV_LOG(ERR,
3747                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3748                         reta_size, lut_size);
3749                 return -EINVAL;
3750         }
3751
3752         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3753         if (!lut) {
3754                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3755                 return -ENOMEM;
3756         }
3757         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3758         if (ret)
3759                 goto out;
3760         for (i = 0; i < reta_size; i++) {
3761                 idx = i / RTE_RETA_GROUP_SIZE;
3762                 shift = i % RTE_RETA_GROUP_SIZE;
3763                 if (reta_conf[idx].mask & (1ULL << shift))
3764                         lut[i] = reta_conf[idx].reta[shift];
3765         }
3766         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3767
3768 out:
3769         rte_free(lut);
3770
3771         return ret;
3772 }
3773
3774 static int
3775 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3776                         struct rte_eth_rss_reta_entry64 *reta_conf,
3777                         uint16_t reta_size)
3778 {
3779         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3780         uint16_t i, lut_size = pf->hash_lut_size;
3781         uint16_t idx, shift;
3782         uint8_t *lut;
3783         int ret;
3784
3785         if (reta_size != lut_size ||
3786                 reta_size > ETH_RSS_RETA_SIZE_512) {
3787                 PMD_DRV_LOG(ERR,
3788                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3789                         reta_size, lut_size);
3790                 return -EINVAL;
3791         }
3792
3793         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3794         if (!lut) {
3795                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3796                 return -ENOMEM;
3797         }
3798
3799         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3800         if (ret)
3801                 goto out;
3802         for (i = 0; i < reta_size; i++) {
3803                 idx = i / RTE_RETA_GROUP_SIZE;
3804                 shift = i % RTE_RETA_GROUP_SIZE;
3805                 if (reta_conf[idx].mask & (1ULL << shift))
3806                         reta_conf[idx].reta[shift] = lut[i];
3807         }
3808
3809 out:
3810         rte_free(lut);
3811
3812         return ret;
3813 }
3814
3815 /**
3816  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3817  * @hw:   pointer to the HW structure
3818  * @mem:  pointer to mem struct to fill out
3819  * @size: size of memory requested
3820  * @alignment: what to align the allocation to
3821  **/
3822 enum i40e_status_code
3823 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3824                         struct i40e_dma_mem *mem,
3825                         u64 size,
3826                         u32 alignment)
3827 {
3828         const struct rte_memzone *mz = NULL;
3829         char z_name[RTE_MEMZONE_NAMESIZE];
3830
3831         if (!mem)
3832                 return I40E_ERR_PARAM;
3833
3834         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3835         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3836                                          alignment, RTE_PGSIZE_2M);
3837         if (!mz)
3838                 return I40E_ERR_NO_MEMORY;
3839
3840         mem->size = size;
3841         mem->va = mz->addr;
3842         mem->pa = mz->phys_addr;
3843         mem->zone = (const void *)mz;
3844         PMD_DRV_LOG(DEBUG,
3845                 "memzone %s allocated with physical address: %"PRIu64,
3846                 mz->name, mem->pa);
3847
3848         return I40E_SUCCESS;
3849 }
3850
3851 /**
3852  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3853  * @hw:   pointer to the HW structure
3854  * @mem:  ptr to mem struct to free
3855  **/
3856 enum i40e_status_code
3857 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3858                     struct i40e_dma_mem *mem)
3859 {
3860         if (!mem)
3861                 return I40E_ERR_PARAM;
3862
3863         PMD_DRV_LOG(DEBUG,
3864                 "memzone %s to be freed with physical address: %"PRIu64,
3865                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3866         rte_memzone_free((const struct rte_memzone *)mem->zone);
3867         mem->zone = NULL;
3868         mem->va = NULL;
3869         mem->pa = (u64)0;
3870
3871         return I40E_SUCCESS;
3872 }
3873
3874 /**
3875  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3876  * @hw:   pointer to the HW structure
3877  * @mem:  pointer to mem struct to fill out
3878  * @size: size of memory requested
3879  **/
3880 enum i40e_status_code
3881 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3882                          struct i40e_virt_mem *mem,
3883                          u32 size)
3884 {
3885         if (!mem)
3886                 return I40E_ERR_PARAM;
3887
3888         mem->size = size;
3889         mem->va = rte_zmalloc("i40e", size, 0);
3890
3891         if (mem->va)
3892                 return I40E_SUCCESS;
3893         else
3894                 return I40E_ERR_NO_MEMORY;
3895 }
3896
3897 /**
3898  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3899  * @hw:   pointer to the HW structure
3900  * @mem:  pointer to mem struct to free
3901  **/
3902 enum i40e_status_code
3903 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3904                      struct i40e_virt_mem *mem)
3905 {
3906         if (!mem)
3907                 return I40E_ERR_PARAM;
3908
3909         rte_free(mem->va);
3910         mem->va = NULL;
3911
3912         return I40E_SUCCESS;
3913 }
3914
3915 void
3916 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3917 {
3918         rte_spinlock_init(&sp->spinlock);
3919 }
3920
3921 void
3922 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3923 {
3924         rte_spinlock_lock(&sp->spinlock);
3925 }
3926
3927 void
3928 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3929 {
3930         rte_spinlock_unlock(&sp->spinlock);
3931 }
3932
3933 void
3934 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3935 {
3936         return;
3937 }
3938
3939 /**
3940  * Get the hardware capabilities, which will be parsed
3941  * and saved into struct i40e_hw.
3942  */
3943 static int
3944 i40e_get_cap(struct i40e_hw *hw)
3945 {
3946         struct i40e_aqc_list_capabilities_element_resp *buf;
3947         uint16_t len, size = 0;
3948         int ret;
3949
3950         /* Calculate a huge enough buff for saving response data temporarily */
3951         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3952                                                 I40E_MAX_CAP_ELE_NUM;
3953         buf = rte_zmalloc("i40e", len, 0);
3954         if (!buf) {
3955                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3956                 return I40E_ERR_NO_MEMORY;
3957         }
3958
3959         /* Get, parse the capabilities and save it to hw */
3960         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3961                         i40e_aqc_opc_list_func_capabilities, NULL);
3962         if (ret != I40E_SUCCESS)
3963                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3964
3965         /* Free the temporary buffer after being used */
3966         rte_free(buf);
3967
3968         return ret;
3969 }
3970
3971 static int
3972 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3973 {
3974         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3975         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3976         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3977         uint16_t qp_count = 0, vsi_count = 0;
3978
3979         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3980                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3981                 return -EINVAL;
3982         }
3983         /* Add the parameter init for LFC */
3984         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3985         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3986         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3987
3988         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3989         pf->max_num_vsi = hw->func_caps.num_vsis;
3990         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3991         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3992         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3993
3994         /* FDir queue/VSI allocation */
3995         pf->fdir_qp_offset = 0;
3996         if (hw->func_caps.fd) {
3997                 pf->flags |= I40E_FLAG_FDIR;
3998                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3999         } else {
4000                 pf->fdir_nb_qps = 0;
4001         }
4002         qp_count += pf->fdir_nb_qps;
4003         vsi_count += 1;
4004
4005         /* LAN queue/VSI allocation */
4006         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4007         if (!hw->func_caps.rss) {
4008                 pf->lan_nb_qps = 1;
4009         } else {
4010                 pf->flags |= I40E_FLAG_RSS;
4011                 if (hw->mac.type == I40E_MAC_X722)
4012                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4013                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4014         }
4015         qp_count += pf->lan_nb_qps;
4016         vsi_count += 1;
4017
4018         /* VF queue/VSI allocation */
4019         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4020         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4021                 pf->flags |= I40E_FLAG_SRIOV;
4022                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4023                 pf->vf_num = pci_dev->max_vfs;
4024                 PMD_DRV_LOG(DEBUG,
4025                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4026                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4027         } else {
4028                 pf->vf_nb_qps = 0;
4029                 pf->vf_num = 0;
4030         }
4031         qp_count += pf->vf_nb_qps * pf->vf_num;
4032         vsi_count += pf->vf_num;
4033
4034         /* VMDq queue/VSI allocation */
4035         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4036         pf->vmdq_nb_qps = 0;
4037         pf->max_nb_vmdq_vsi = 0;
4038         if (hw->func_caps.vmdq) {
4039                 if (qp_count < hw->func_caps.num_tx_qp &&
4040                         vsi_count < hw->func_caps.num_vsis) {
4041                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4042                                 qp_count) / pf->vmdq_nb_qp_max;
4043
4044                         /* Limit the maximum number of VMDq vsi to the maximum
4045                          * ethdev can support
4046                          */
4047                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4048                                 hw->func_caps.num_vsis - vsi_count);
4049                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4050                                 ETH_64_POOLS);
4051                         if (pf->max_nb_vmdq_vsi) {
4052                                 pf->flags |= I40E_FLAG_VMDQ;
4053                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4054                                 PMD_DRV_LOG(DEBUG,
4055                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4056                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4057                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4058                         } else {
4059                                 PMD_DRV_LOG(INFO,
4060                                         "No enough queues left for VMDq");
4061                         }
4062                 } else {
4063                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4064                 }
4065         }
4066         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4067         vsi_count += pf->max_nb_vmdq_vsi;
4068
4069         if (hw->func_caps.dcb)
4070                 pf->flags |= I40E_FLAG_DCB;
4071
4072         if (qp_count > hw->func_caps.num_tx_qp) {
4073                 PMD_DRV_LOG(ERR,
4074                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4075                         qp_count, hw->func_caps.num_tx_qp);
4076                 return -EINVAL;
4077         }
4078         if (vsi_count > hw->func_caps.num_vsis) {
4079                 PMD_DRV_LOG(ERR,
4080                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4081                         vsi_count, hw->func_caps.num_vsis);
4082                 return -EINVAL;
4083         }
4084
4085         return 0;
4086 }
4087
4088 static int
4089 i40e_pf_get_switch_config(struct i40e_pf *pf)
4090 {
4091         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4092         struct i40e_aqc_get_switch_config_resp *switch_config;
4093         struct i40e_aqc_switch_config_element_resp *element;
4094         uint16_t start_seid = 0, num_reported;
4095         int ret;
4096
4097         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4098                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4099         if (!switch_config) {
4100                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4101                 return -ENOMEM;
4102         }
4103
4104         /* Get the switch configurations */
4105         ret = i40e_aq_get_switch_config(hw, switch_config,
4106                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4107         if (ret != I40E_SUCCESS) {
4108                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4109                 goto fail;
4110         }
4111         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4112         if (num_reported != 1) { /* The number should be 1 */
4113                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4114                 goto fail;
4115         }
4116
4117         /* Parse the switch configuration elements */
4118         element = &(switch_config->element[0]);
4119         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4120                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4121                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4122         } else
4123                 PMD_DRV_LOG(INFO, "Unknown element type");
4124
4125 fail:
4126         rte_free(switch_config);
4127
4128         return ret;
4129 }
4130
4131 static int
4132 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4133                         uint32_t num)
4134 {
4135         struct pool_entry *entry;
4136
4137         if (pool == NULL || num == 0)
4138                 return -EINVAL;
4139
4140         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4141         if (entry == NULL) {
4142                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4143                 return -ENOMEM;
4144         }
4145
4146         /* queue heap initialize */
4147         pool->num_free = num;
4148         pool->num_alloc = 0;
4149         pool->base = base;
4150         LIST_INIT(&pool->alloc_list);
4151         LIST_INIT(&pool->free_list);
4152
4153         /* Initialize element  */
4154         entry->base = 0;
4155         entry->len = num;
4156
4157         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4158         return 0;
4159 }
4160
4161 static void
4162 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4163 {
4164         struct pool_entry *entry, *next_entry;
4165
4166         if (pool == NULL)
4167                 return;
4168
4169         for (entry = LIST_FIRST(&pool->alloc_list);
4170                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4171                         entry = next_entry) {
4172                 LIST_REMOVE(entry, next);
4173                 rte_free(entry);
4174         }
4175
4176         for (entry = LIST_FIRST(&pool->free_list);
4177                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4178                         entry = next_entry) {
4179                 LIST_REMOVE(entry, next);
4180                 rte_free(entry);
4181         }
4182
4183         pool->num_free = 0;
4184         pool->num_alloc = 0;
4185         pool->base = 0;
4186         LIST_INIT(&pool->alloc_list);
4187         LIST_INIT(&pool->free_list);
4188 }
4189
4190 static int
4191 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4192                        uint32_t base)
4193 {
4194         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4195         uint32_t pool_offset;
4196         int insert;
4197
4198         if (pool == NULL) {
4199                 PMD_DRV_LOG(ERR, "Invalid parameter");
4200                 return -EINVAL;
4201         }
4202
4203         pool_offset = base - pool->base;
4204         /* Lookup in alloc list */
4205         LIST_FOREACH(entry, &pool->alloc_list, next) {
4206                 if (entry->base == pool_offset) {
4207                         valid_entry = entry;
4208                         LIST_REMOVE(entry, next);
4209                         break;
4210                 }
4211         }
4212
4213         /* Not find, return */
4214         if (valid_entry == NULL) {
4215                 PMD_DRV_LOG(ERR, "Failed to find entry");
4216                 return -EINVAL;
4217         }
4218
4219         /**
4220          * Found it, move it to free list  and try to merge.
4221          * In order to make merge easier, always sort it by qbase.
4222          * Find adjacent prev and last entries.
4223          */
4224         prev = next = NULL;
4225         LIST_FOREACH(entry, &pool->free_list, next) {
4226                 if (entry->base > valid_entry->base) {
4227                         next = entry;
4228                         break;
4229                 }
4230                 prev = entry;
4231         }
4232
4233         insert = 0;
4234         /* Try to merge with next one*/
4235         if (next != NULL) {
4236                 /* Merge with next one */
4237                 if (valid_entry->base + valid_entry->len == next->base) {
4238                         next->base = valid_entry->base;
4239                         next->len += valid_entry->len;
4240                         rte_free(valid_entry);
4241                         valid_entry = next;
4242                         insert = 1;
4243                 }
4244         }
4245
4246         if (prev != NULL) {
4247                 /* Merge with previous one */
4248                 if (prev->base + prev->len == valid_entry->base) {
4249                         prev->len += valid_entry->len;
4250                         /* If it merge with next one, remove next node */
4251                         if (insert == 1) {
4252                                 LIST_REMOVE(valid_entry, next);
4253                                 rte_free(valid_entry);
4254                         } else {
4255                                 rte_free(valid_entry);
4256                                 insert = 1;
4257                         }
4258                 }
4259         }
4260
4261         /* Not find any entry to merge, insert */
4262         if (insert == 0) {
4263                 if (prev != NULL)
4264                         LIST_INSERT_AFTER(prev, valid_entry, next);
4265                 else if (next != NULL)
4266                         LIST_INSERT_BEFORE(next, valid_entry, next);
4267                 else /* It's empty list, insert to head */
4268                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4269         }
4270
4271         pool->num_free += valid_entry->len;
4272         pool->num_alloc -= valid_entry->len;
4273
4274         return 0;
4275 }
4276
4277 static int
4278 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4279                        uint16_t num)
4280 {
4281         struct pool_entry *entry, *valid_entry;
4282
4283         if (pool == NULL || num == 0) {
4284                 PMD_DRV_LOG(ERR, "Invalid parameter");
4285                 return -EINVAL;
4286         }
4287
4288         if (pool->num_free < num) {
4289                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4290                             num, pool->num_free);
4291                 return -ENOMEM;
4292         }
4293
4294         valid_entry = NULL;
4295         /* Lookup  in free list and find most fit one */
4296         LIST_FOREACH(entry, &pool->free_list, next) {
4297                 if (entry->len >= num) {
4298                         /* Find best one */
4299                         if (entry->len == num) {
4300                                 valid_entry = entry;
4301                                 break;
4302                         }
4303                         if (valid_entry == NULL || valid_entry->len > entry->len)
4304                                 valid_entry = entry;
4305                 }
4306         }
4307
4308         /* Not find one to satisfy the request, return */
4309         if (valid_entry == NULL) {
4310                 PMD_DRV_LOG(ERR, "No valid entry found");
4311                 return -ENOMEM;
4312         }
4313         /**
4314          * The entry have equal queue number as requested,
4315          * remove it from alloc_list.
4316          */
4317         if (valid_entry->len == num) {
4318                 LIST_REMOVE(valid_entry, next);
4319         } else {
4320                 /**
4321                  * The entry have more numbers than requested,
4322                  * create a new entry for alloc_list and minus its
4323                  * queue base and number in free_list.
4324                  */
4325                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4326                 if (entry == NULL) {
4327                         PMD_DRV_LOG(ERR,
4328                                 "Failed to allocate memory for resource pool");
4329                         return -ENOMEM;
4330                 }
4331                 entry->base = valid_entry->base;
4332                 entry->len = num;
4333                 valid_entry->base += num;
4334                 valid_entry->len -= num;
4335                 valid_entry = entry;
4336         }
4337
4338         /* Insert it into alloc list, not sorted */
4339         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4340
4341         pool->num_free -= valid_entry->len;
4342         pool->num_alloc += valid_entry->len;
4343
4344         return valid_entry->base + pool->base;
4345 }
4346
4347 /**
4348  * bitmap_is_subset - Check whether src2 is subset of src1
4349  **/
4350 static inline int
4351 bitmap_is_subset(uint8_t src1, uint8_t src2)
4352 {
4353         return !((src1 ^ src2) & src2);
4354 }
4355
4356 static enum i40e_status_code
4357 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4358 {
4359         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4360
4361         /* If DCB is not supported, only default TC is supported */
4362         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4363                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4364                 return I40E_NOT_SUPPORTED;
4365         }
4366
4367         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4368                 PMD_DRV_LOG(ERR,
4369                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4370                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4371                 return I40E_NOT_SUPPORTED;
4372         }
4373         return I40E_SUCCESS;
4374 }
4375
4376 int
4377 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4378                                 struct i40e_vsi_vlan_pvid_info *info)
4379 {
4380         struct i40e_hw *hw;
4381         struct i40e_vsi_context ctxt;
4382         uint8_t vlan_flags = 0;
4383         int ret;
4384
4385         if (vsi == NULL || info == NULL) {
4386                 PMD_DRV_LOG(ERR, "invalid parameters");
4387                 return I40E_ERR_PARAM;
4388         }
4389
4390         if (info->on) {
4391                 vsi->info.pvid = info->config.pvid;
4392                 /**
4393                  * If insert pvid is enabled, only tagged pkts are
4394                  * allowed to be sent out.
4395                  */
4396                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4397                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4398         } else {
4399                 vsi->info.pvid = 0;
4400                 if (info->config.reject.tagged == 0)
4401                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4402
4403                 if (info->config.reject.untagged == 0)
4404                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4405         }
4406         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4407                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4408         vsi->info.port_vlan_flags |= vlan_flags;
4409         vsi->info.valid_sections =
4410                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4411         memset(&ctxt, 0, sizeof(ctxt));
4412         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4413         ctxt.seid = vsi->seid;
4414
4415         hw = I40E_VSI_TO_HW(vsi);
4416         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4417         if (ret != I40E_SUCCESS)
4418                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4419
4420         return ret;
4421 }
4422
4423 static int
4424 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4425 {
4426         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4427         int i, ret;
4428         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4429
4430         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4431         if (ret != I40E_SUCCESS)
4432                 return ret;
4433
4434         if (!vsi->seid) {
4435                 PMD_DRV_LOG(ERR, "seid not valid");
4436                 return -EINVAL;
4437         }
4438
4439         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4440         tc_bw_data.tc_valid_bits = enabled_tcmap;
4441         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4442                 tc_bw_data.tc_bw_credits[i] =
4443                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4444
4445         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4446         if (ret != I40E_SUCCESS) {
4447                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4448                 return ret;
4449         }
4450
4451         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4452                                         sizeof(vsi->info.qs_handle));
4453         return I40E_SUCCESS;
4454 }
4455
4456 static enum i40e_status_code
4457 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4458                                  struct i40e_aqc_vsi_properties_data *info,
4459                                  uint8_t enabled_tcmap)
4460 {
4461         enum i40e_status_code ret;
4462         int i, total_tc = 0;
4463         uint16_t qpnum_per_tc, bsf, qp_idx;
4464
4465         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4466         if (ret != I40E_SUCCESS)
4467                 return ret;
4468
4469         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4470                 if (enabled_tcmap & (1 << i))
4471                         total_tc++;
4472         if (total_tc == 0)
4473                 total_tc = 1;
4474         vsi->enabled_tc = enabled_tcmap;
4475
4476         /* Number of queues per enabled TC */
4477         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4478         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4479         bsf = rte_bsf32(qpnum_per_tc);
4480
4481         /* Adjust the queue number to actual queues that can be applied */
4482         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4483                 vsi->nb_qps = qpnum_per_tc * total_tc;
4484
4485         /**
4486          * Configure TC and queue mapping parameters, for enabled TC,
4487          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4488          * default queue will serve it.
4489          */
4490         qp_idx = 0;
4491         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4492                 if (vsi->enabled_tc & (1 << i)) {
4493                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4494                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4495                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4496                         qp_idx += qpnum_per_tc;
4497                 } else
4498                         info->tc_mapping[i] = 0;
4499         }
4500
4501         /* Associate queue number with VSI */
4502         if (vsi->type == I40E_VSI_SRIOV) {
4503                 info->mapping_flags |=
4504                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4505                 for (i = 0; i < vsi->nb_qps; i++)
4506                         info->queue_mapping[i] =
4507                                 rte_cpu_to_le_16(vsi->base_queue + i);
4508         } else {
4509                 info->mapping_flags |=
4510                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4511                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4512         }
4513         info->valid_sections |=
4514                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4515
4516         return I40E_SUCCESS;
4517 }
4518
4519 static int
4520 i40e_veb_release(struct i40e_veb *veb)
4521 {
4522         struct i40e_vsi *vsi;
4523         struct i40e_hw *hw;
4524
4525         if (veb == NULL)
4526                 return -EINVAL;
4527
4528         if (!TAILQ_EMPTY(&veb->head)) {
4529                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4530                 return -EACCES;
4531         }
4532         /* associate_vsi field is NULL for floating VEB */
4533         if (veb->associate_vsi != NULL) {
4534                 vsi = veb->associate_vsi;
4535                 hw = I40E_VSI_TO_HW(vsi);
4536
4537                 vsi->uplink_seid = veb->uplink_seid;
4538                 vsi->veb = NULL;
4539         } else {
4540                 veb->associate_pf->main_vsi->floating_veb = NULL;
4541                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4542         }
4543
4544         i40e_aq_delete_element(hw, veb->seid, NULL);
4545         rte_free(veb);
4546         return I40E_SUCCESS;
4547 }
4548
4549 /* Setup a veb */
4550 static struct i40e_veb *
4551 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4552 {
4553         struct i40e_veb *veb;
4554         int ret;
4555         struct i40e_hw *hw;
4556
4557         if (pf == NULL) {
4558                 PMD_DRV_LOG(ERR,
4559                             "veb setup failed, associated PF shouldn't null");
4560                 return NULL;
4561         }
4562         hw = I40E_PF_TO_HW(pf);
4563
4564         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4565         if (!veb) {
4566                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4567                 goto fail;
4568         }
4569
4570         veb->associate_vsi = vsi;
4571         veb->associate_pf = pf;
4572         TAILQ_INIT(&veb->head);
4573         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4574
4575         /* create floating veb if vsi is NULL */
4576         if (vsi != NULL) {
4577                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4578                                       I40E_DEFAULT_TCMAP, false,
4579                                       &veb->seid, false, NULL);
4580         } else {
4581                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4582                                       true, &veb->seid, false, NULL);
4583         }
4584
4585         if (ret != I40E_SUCCESS) {
4586                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4587                             hw->aq.asq_last_status);
4588                 goto fail;
4589         }
4590         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4591
4592         /* get statistics index */
4593         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4594                                 &veb->stats_idx, NULL, NULL, NULL);
4595         if (ret != I40E_SUCCESS) {
4596                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4597                             hw->aq.asq_last_status);
4598                 goto fail;
4599         }
4600         /* Get VEB bandwidth, to be implemented */
4601         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4602         if (vsi)
4603                 vsi->uplink_seid = veb->seid;
4604
4605         return veb;
4606 fail:
4607         rte_free(veb);
4608         return NULL;
4609 }
4610
4611 int
4612 i40e_vsi_release(struct i40e_vsi *vsi)
4613 {
4614         struct i40e_pf *pf;
4615         struct i40e_hw *hw;
4616         struct i40e_vsi_list *vsi_list;
4617         void *temp;
4618         int ret;
4619         struct i40e_mac_filter *f;
4620         uint16_t user_param;
4621
4622         if (!vsi)
4623                 return I40E_SUCCESS;
4624
4625         if (!vsi->adapter)
4626                 return -EFAULT;
4627
4628         user_param = vsi->user_param;
4629
4630         pf = I40E_VSI_TO_PF(vsi);
4631         hw = I40E_VSI_TO_HW(vsi);
4632
4633         /* VSI has child to attach, release child first */
4634         if (vsi->veb) {
4635                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4636                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4637                                 return -1;
4638                 }
4639                 i40e_veb_release(vsi->veb);
4640         }
4641
4642         if (vsi->floating_veb) {
4643                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4644                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4645                                 return -1;
4646                 }
4647         }
4648
4649         /* Remove all macvlan filters of the VSI */
4650         i40e_vsi_remove_all_macvlan_filter(vsi);
4651         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4652                 rte_free(f);
4653
4654         if (vsi->type != I40E_VSI_MAIN &&
4655             ((vsi->type != I40E_VSI_SRIOV) ||
4656             !pf->floating_veb_list[user_param])) {
4657                 /* Remove vsi from parent's sibling list */
4658                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4659                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4660                         return I40E_ERR_PARAM;
4661                 }
4662                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4663                                 &vsi->sib_vsi_list, list);
4664
4665                 /* Remove all switch element of the VSI */
4666                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4667                 if (ret != I40E_SUCCESS)
4668                         PMD_DRV_LOG(ERR, "Failed to delete element");
4669         }
4670
4671         if ((vsi->type == I40E_VSI_SRIOV) &&
4672             pf->floating_veb_list[user_param]) {
4673                 /* Remove vsi from parent's sibling list */
4674                 if (vsi->parent_vsi == NULL ||
4675                     vsi->parent_vsi->floating_veb == NULL) {
4676                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4677                         return I40E_ERR_PARAM;
4678                 }
4679                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4680                              &vsi->sib_vsi_list, list);
4681
4682                 /* Remove all switch element of the VSI */
4683                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4684                 if (ret != I40E_SUCCESS)
4685                         PMD_DRV_LOG(ERR, "Failed to delete element");
4686         }
4687
4688         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4689
4690         if (vsi->type != I40E_VSI_SRIOV)
4691                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4692         rte_free(vsi);
4693
4694         return I40E_SUCCESS;
4695 }
4696
4697 static int
4698 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4699 {
4700         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4701         struct i40e_aqc_remove_macvlan_element_data def_filter;
4702         struct i40e_mac_filter_info filter;
4703         int ret;
4704
4705         if (vsi->type != I40E_VSI_MAIN)
4706                 return I40E_ERR_CONFIG;
4707         memset(&def_filter, 0, sizeof(def_filter));
4708         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4709                                         ETH_ADDR_LEN);
4710         def_filter.vlan_tag = 0;
4711         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4712                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4713         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4714         if (ret != I40E_SUCCESS) {
4715                 struct i40e_mac_filter *f;
4716                 struct ether_addr *mac;
4717
4718                 PMD_DRV_LOG(DEBUG,
4719                             "Cannot remove the default macvlan filter");
4720                 /* It needs to add the permanent mac into mac list */
4721                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4722                 if (f == NULL) {
4723                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4724                         return I40E_ERR_NO_MEMORY;
4725                 }
4726                 mac = &f->mac_info.mac_addr;
4727                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4728                                 ETH_ADDR_LEN);
4729                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4730                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4731                 vsi->mac_num++;
4732
4733                 return ret;
4734         }
4735         rte_memcpy(&filter.mac_addr,
4736                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4737         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4738         return i40e_vsi_add_mac(vsi, &filter);
4739 }
4740
4741 /*
4742  * i40e_vsi_get_bw_config - Query VSI BW Information
4743  * @vsi: the VSI to be queried
4744  *
4745  * Returns 0 on success, negative value on failure
4746  */
4747 static enum i40e_status_code
4748 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4749 {
4750         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4751         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4752         struct i40e_hw *hw = &vsi->adapter->hw;
4753         i40e_status ret;
4754         int i;
4755         uint32_t bw_max;
4756
4757         memset(&bw_config, 0, sizeof(bw_config));
4758         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4759         if (ret != I40E_SUCCESS) {
4760                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4761                             hw->aq.asq_last_status);
4762                 return ret;
4763         }
4764
4765         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4766         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4767                                         &ets_sla_config, NULL);
4768         if (ret != I40E_SUCCESS) {
4769                 PMD_DRV_LOG(ERR,
4770                         "VSI failed to get TC bandwdith configuration %u",
4771                         hw->aq.asq_last_status);
4772                 return ret;
4773         }
4774
4775         /* store and print out BW info */
4776         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4777         vsi->bw_info.bw_max = bw_config.max_bw;
4778         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4779         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4780         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4781                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4782                      I40E_16_BIT_WIDTH);
4783         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4784                 vsi->bw_info.bw_ets_share_credits[i] =
4785                                 ets_sla_config.share_credits[i];
4786                 vsi->bw_info.bw_ets_credits[i] =
4787                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4788                 /* 4 bits per TC, 4th bit is reserved */
4789                 vsi->bw_info.bw_ets_max[i] =
4790                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4791                                   RTE_LEN2MASK(3, uint8_t));
4792                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4793                             vsi->bw_info.bw_ets_share_credits[i]);
4794                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4795                             vsi->bw_info.bw_ets_credits[i]);
4796                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4797                             vsi->bw_info.bw_ets_max[i]);
4798         }
4799
4800         return I40E_SUCCESS;
4801 }
4802
4803 /* i40e_enable_pf_lb
4804  * @pf: pointer to the pf structure
4805  *
4806  * allow loopback on pf
4807  */
4808 static inline void
4809 i40e_enable_pf_lb(struct i40e_pf *pf)
4810 {
4811         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4812         struct i40e_vsi_context ctxt;
4813         int ret;
4814
4815         /* Use the FW API if FW >= v5.0 */
4816         if (hw->aq.fw_maj_ver < 5) {
4817                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4818                 return;
4819         }
4820
4821         memset(&ctxt, 0, sizeof(ctxt));
4822         ctxt.seid = pf->main_vsi_seid;
4823         ctxt.pf_num = hw->pf_id;
4824         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4825         if (ret) {
4826                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4827                             ret, hw->aq.asq_last_status);
4828                 return;
4829         }
4830         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4831         ctxt.info.valid_sections =
4832                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4833         ctxt.info.switch_id |=
4834                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4835
4836         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4837         if (ret)
4838                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4839                             hw->aq.asq_last_status);
4840 }
4841
4842 /* Setup a VSI */
4843 struct i40e_vsi *
4844 i40e_vsi_setup(struct i40e_pf *pf,
4845                enum i40e_vsi_type type,
4846                struct i40e_vsi *uplink_vsi,
4847                uint16_t user_param)
4848 {
4849         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4850         struct i40e_vsi *vsi;
4851         struct i40e_mac_filter_info filter;
4852         int ret;
4853         struct i40e_vsi_context ctxt;
4854         struct ether_addr broadcast =
4855                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4856
4857         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4858             uplink_vsi == NULL) {
4859                 PMD_DRV_LOG(ERR,
4860                         "VSI setup failed, VSI link shouldn't be NULL");
4861                 return NULL;
4862         }
4863
4864         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4865                 PMD_DRV_LOG(ERR,
4866                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4867                 return NULL;
4868         }
4869
4870         /* two situations
4871          * 1.type is not MAIN and uplink vsi is not NULL
4872          * If uplink vsi didn't setup VEB, create one first under veb field
4873          * 2.type is SRIOV and the uplink is NULL
4874          * If floating VEB is NULL, create one veb under floating veb field
4875          */
4876
4877         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4878             uplink_vsi->veb == NULL) {
4879                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4880
4881                 if (uplink_vsi->veb == NULL) {
4882                         PMD_DRV_LOG(ERR, "VEB setup failed");
4883                         return NULL;
4884                 }
4885                 /* set ALLOWLOOPBACk on pf, when veb is created */
4886                 i40e_enable_pf_lb(pf);
4887         }
4888
4889         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4890             pf->main_vsi->floating_veb == NULL) {
4891                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4892
4893                 if (pf->main_vsi->floating_veb == NULL) {
4894                         PMD_DRV_LOG(ERR, "VEB setup failed");
4895                         return NULL;
4896                 }
4897         }
4898
4899         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4900         if (!vsi) {
4901                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4902                 return NULL;
4903         }
4904         TAILQ_INIT(&vsi->mac_list);
4905         vsi->type = type;
4906         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4907         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4908         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4909         vsi->user_param = user_param;
4910         vsi->vlan_anti_spoof_on = 0;
4911         vsi->vlan_filter_on = 0;
4912         /* Allocate queues */
4913         switch (vsi->type) {
4914         case I40E_VSI_MAIN  :
4915                 vsi->nb_qps = pf->lan_nb_qps;
4916                 break;
4917         case I40E_VSI_SRIOV :
4918                 vsi->nb_qps = pf->vf_nb_qps;
4919                 break;
4920         case I40E_VSI_VMDQ2:
4921                 vsi->nb_qps = pf->vmdq_nb_qps;
4922                 break;
4923         case I40E_VSI_FDIR:
4924                 vsi->nb_qps = pf->fdir_nb_qps;
4925                 break;
4926         default:
4927                 goto fail_mem;
4928         }
4929         /*
4930          * The filter status descriptor is reported in rx queue 0,
4931          * while the tx queue for fdir filter programming has no
4932          * such constraints, can be non-zero queues.
4933          * To simplify it, choose FDIR vsi use queue 0 pair.
4934          * To make sure it will use queue 0 pair, queue allocation
4935          * need be done before this function is called
4936          */
4937         if (type != I40E_VSI_FDIR) {
4938                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4939                         if (ret < 0) {
4940                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4941                                                 vsi->seid, ret);
4942                                 goto fail_mem;
4943                         }
4944                         vsi->base_queue = ret;
4945         } else
4946                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4947
4948         /* VF has MSIX interrupt in VF range, don't allocate here */
4949         if (type == I40E_VSI_MAIN) {
4950                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4951                                           RTE_MIN(vsi->nb_qps,
4952                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4953                 if (ret < 0) {
4954                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4955                                     vsi->seid, ret);
4956                         goto fail_queue_alloc;
4957                 }
4958                 vsi->msix_intr = ret;
4959                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4960         } else if (type != I40E_VSI_SRIOV) {
4961                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4962                 if (ret < 0) {
4963                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4964                         goto fail_queue_alloc;
4965                 }
4966                 vsi->msix_intr = ret;
4967                 vsi->nb_msix = 1;
4968         } else {
4969                 vsi->msix_intr = 0;
4970                 vsi->nb_msix = 0;
4971         }
4972
4973         /* Add VSI */
4974         if (type == I40E_VSI_MAIN) {
4975                 /* For main VSI, no need to add since it's default one */
4976                 vsi->uplink_seid = pf->mac_seid;
4977                 vsi->seid = pf->main_vsi_seid;
4978                 /* Bind queues with specific MSIX interrupt */
4979                 /**
4980                  * Needs 2 interrupt at least, one for misc cause which will
4981                  * enabled from OS side, Another for queues binding the
4982                  * interrupt from device side only.
4983                  */
4984
4985                 /* Get default VSI parameters from hardware */
4986                 memset(&ctxt, 0, sizeof(ctxt));
4987                 ctxt.seid = vsi->seid;
4988                 ctxt.pf_num = hw->pf_id;
4989                 ctxt.uplink_seid = vsi->uplink_seid;
4990                 ctxt.vf_num = 0;
4991                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4992                 if (ret != I40E_SUCCESS) {
4993                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4994                         goto fail_msix_alloc;
4995                 }
4996                 rte_memcpy(&vsi->info, &ctxt.info,
4997                         sizeof(struct i40e_aqc_vsi_properties_data));
4998                 vsi->vsi_id = ctxt.vsi_number;
4999                 vsi->info.valid_sections = 0;
5000
5001                 /* Configure tc, enabled TC0 only */
5002                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5003                         I40E_SUCCESS) {
5004                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5005                         goto fail_msix_alloc;
5006                 }
5007
5008                 /* TC, queue mapping */
5009                 memset(&ctxt, 0, sizeof(ctxt));
5010                 vsi->info.valid_sections |=
5011                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5012                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5013                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5014                 rte_memcpy(&ctxt.info, &vsi->info,
5015                         sizeof(struct i40e_aqc_vsi_properties_data));
5016                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5017                                                 I40E_DEFAULT_TCMAP);
5018                 if (ret != I40E_SUCCESS) {
5019                         PMD_DRV_LOG(ERR,
5020                                 "Failed to configure TC queue mapping");
5021                         goto fail_msix_alloc;
5022                 }
5023                 ctxt.seid = vsi->seid;
5024                 ctxt.pf_num = hw->pf_id;
5025                 ctxt.uplink_seid = vsi->uplink_seid;
5026                 ctxt.vf_num = 0;
5027
5028                 /* Update VSI parameters */
5029                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5030                 if (ret != I40E_SUCCESS) {
5031                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5032                         goto fail_msix_alloc;
5033                 }
5034
5035                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5036                                                 sizeof(vsi->info.tc_mapping));
5037                 rte_memcpy(&vsi->info.queue_mapping,
5038                                 &ctxt.info.queue_mapping,
5039                         sizeof(vsi->info.queue_mapping));
5040                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5041                 vsi->info.valid_sections = 0;
5042
5043                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5044                                 ETH_ADDR_LEN);
5045
5046                 /**
5047                  * Updating default filter settings are necessary to prevent
5048                  * reception of tagged packets.
5049                  * Some old firmware configurations load a default macvlan
5050                  * filter which accepts both tagged and untagged packets.
5051                  * The updating is to use a normal filter instead if needed.
5052                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5053                  * The firmware with correct configurations load the default
5054                  * macvlan filter which is expected and cannot be removed.
5055                  */
5056                 i40e_update_default_filter_setting(vsi);
5057                 i40e_config_qinq(hw, vsi);
5058         } else if (type == I40E_VSI_SRIOV) {
5059                 memset(&ctxt, 0, sizeof(ctxt));
5060                 /**
5061                  * For other VSI, the uplink_seid equals to uplink VSI's
5062                  * uplink_seid since they share same VEB
5063                  */
5064                 if (uplink_vsi == NULL)
5065                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5066                 else
5067                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5068                 ctxt.pf_num = hw->pf_id;
5069                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5070                 ctxt.uplink_seid = vsi->uplink_seid;
5071                 ctxt.connection_type = 0x1;
5072                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5073
5074                 /* Use the VEB configuration if FW >= v5.0 */
5075                 if (hw->aq.fw_maj_ver >= 5) {
5076                         /* Configure switch ID */
5077                         ctxt.info.valid_sections |=
5078                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5079                         ctxt.info.switch_id =
5080                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5081                 }
5082
5083                 /* Configure port/vlan */
5084                 ctxt.info.valid_sections |=
5085                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5086                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5087                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5088                                                 hw->func_caps.enabled_tcmap);
5089                 if (ret != I40E_SUCCESS) {
5090                         PMD_DRV_LOG(ERR,
5091                                 "Failed to configure TC queue mapping");
5092                         goto fail_msix_alloc;
5093                 }
5094
5095                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5096                 ctxt.info.valid_sections |=
5097                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5098                 /**
5099                  * Since VSI is not created yet, only configure parameter,
5100                  * will add vsi below.
5101                  */
5102
5103                 i40e_config_qinq(hw, vsi);
5104         } else if (type == I40E_VSI_VMDQ2) {
5105                 memset(&ctxt, 0, sizeof(ctxt));
5106                 /*
5107                  * For other VSI, the uplink_seid equals to uplink VSI's
5108                  * uplink_seid since they share same VEB
5109                  */
5110                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5111                 ctxt.pf_num = hw->pf_id;
5112                 ctxt.vf_num = 0;
5113                 ctxt.uplink_seid = vsi->uplink_seid;
5114                 ctxt.connection_type = 0x1;
5115                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5116
5117                 ctxt.info.valid_sections |=
5118                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5119                 /* user_param carries flag to enable loop back */
5120                 if (user_param) {
5121                         ctxt.info.switch_id =
5122                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5123                         ctxt.info.switch_id |=
5124                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5125                 }
5126
5127                 /* Configure port/vlan */
5128                 ctxt.info.valid_sections |=
5129                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5130                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5131                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5132                                                 I40E_DEFAULT_TCMAP);
5133                 if (ret != I40E_SUCCESS) {
5134                         PMD_DRV_LOG(ERR,
5135                                 "Failed to configure TC queue mapping");
5136                         goto fail_msix_alloc;
5137                 }
5138                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5139                 ctxt.info.valid_sections |=
5140                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5141         } else if (type == I40E_VSI_FDIR) {
5142                 memset(&ctxt, 0, sizeof(ctxt));
5143                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5144                 ctxt.pf_num = hw->pf_id;
5145                 ctxt.vf_num = 0;
5146                 ctxt.uplink_seid = vsi->uplink_seid;
5147                 ctxt.connection_type = 0x1;     /* regular data port */
5148                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5149                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5150                                                 I40E_DEFAULT_TCMAP);
5151                 if (ret != I40E_SUCCESS) {
5152                         PMD_DRV_LOG(ERR,
5153                                 "Failed to configure TC queue mapping.");
5154                         goto fail_msix_alloc;
5155                 }
5156                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5157                 ctxt.info.valid_sections |=
5158                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5159         } else {
5160                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5161                 goto fail_msix_alloc;
5162         }
5163
5164         if (vsi->type != I40E_VSI_MAIN) {
5165                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5166                 if (ret != I40E_SUCCESS) {
5167                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5168                                     hw->aq.asq_last_status);
5169                         goto fail_msix_alloc;
5170                 }
5171                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5172                 vsi->info.valid_sections = 0;
5173                 vsi->seid = ctxt.seid;
5174                 vsi->vsi_id = ctxt.vsi_number;
5175                 vsi->sib_vsi_list.vsi = vsi;
5176                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5177                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5178                                           &vsi->sib_vsi_list, list);
5179                 } else {
5180                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5181                                           &vsi->sib_vsi_list, list);
5182                 }
5183         }
5184
5185         /* MAC/VLAN configuration */
5186         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5187         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5188
5189         ret = i40e_vsi_add_mac(vsi, &filter);
5190         if (ret != I40E_SUCCESS) {
5191                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5192                 goto fail_msix_alloc;
5193         }
5194
5195         /* Get VSI BW information */
5196         i40e_vsi_get_bw_config(vsi);
5197         return vsi;
5198 fail_msix_alloc:
5199         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5200 fail_queue_alloc:
5201         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5202 fail_mem:
5203         rte_free(vsi);
5204         return NULL;
5205 }
5206
5207 /* Configure vlan filter on or off */
5208 int
5209 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5210 {
5211         int i, num;
5212         struct i40e_mac_filter *f;
5213         void *temp;
5214         struct i40e_mac_filter_info *mac_filter;
5215         enum rte_mac_filter_type desired_filter;
5216         int ret = I40E_SUCCESS;
5217
5218         if (on) {
5219                 /* Filter to match MAC and VLAN */
5220                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5221         } else {
5222                 /* Filter to match only MAC */
5223                 desired_filter = RTE_MAC_PERFECT_MATCH;
5224         }
5225
5226         num = vsi->mac_num;
5227
5228         mac_filter = rte_zmalloc("mac_filter_info_data",
5229                                  num * sizeof(*mac_filter), 0);
5230         if (mac_filter == NULL) {
5231                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5232                 return I40E_ERR_NO_MEMORY;
5233         }
5234
5235         i = 0;
5236
5237         /* Remove all existing mac */
5238         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5239                 mac_filter[i] = f->mac_info;
5240                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5241                 if (ret) {
5242                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5243                                     on ? "enable" : "disable");
5244                         goto DONE;
5245                 }
5246                 i++;
5247         }
5248
5249         /* Override with new filter */
5250         for (i = 0; i < num; i++) {
5251                 mac_filter[i].filter_type = desired_filter;
5252                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5253                 if (ret) {
5254                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5255                                     on ? "enable" : "disable");
5256                         goto DONE;
5257                 }
5258         }
5259
5260 DONE:
5261         rte_free(mac_filter);
5262         return ret;
5263 }
5264
5265 /* Configure vlan stripping on or off */
5266 int
5267 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5268 {
5269         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5270         struct i40e_vsi_context ctxt;
5271         uint8_t vlan_flags;
5272         int ret = I40E_SUCCESS;
5273
5274         /* Check if it has been already on or off */
5275         if (vsi->info.valid_sections &
5276                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5277                 if (on) {
5278                         if ((vsi->info.port_vlan_flags &
5279                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5280                                 return 0; /* already on */
5281                 } else {
5282                         if ((vsi->info.port_vlan_flags &
5283                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5284                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5285                                 return 0; /* already off */
5286                 }
5287         }
5288
5289         if (on)
5290                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5291         else
5292                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5293         vsi->info.valid_sections =
5294                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5295         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5296         vsi->info.port_vlan_flags |= vlan_flags;
5297         ctxt.seid = vsi->seid;
5298         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5299         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5300         if (ret)
5301                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5302                             on ? "enable" : "disable");
5303
5304         return ret;
5305 }
5306
5307 static int
5308 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5309 {
5310         struct rte_eth_dev_data *data = dev->data;
5311         int ret;
5312         int mask = 0;
5313
5314         /* Apply vlan offload setting */
5315         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5316         i40e_vlan_offload_set(dev, mask);
5317
5318         /* Apply double-vlan setting, not implemented yet */
5319
5320         /* Apply pvid setting */
5321         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5322                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5323         if (ret)
5324                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5325
5326         return ret;
5327 }
5328
5329 static int
5330 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5331 {
5332         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5333
5334         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5335 }
5336
5337 static int
5338 i40e_update_flow_control(struct i40e_hw *hw)
5339 {
5340 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5341         struct i40e_link_status link_status;
5342         uint32_t rxfc = 0, txfc = 0, reg;
5343         uint8_t an_info;
5344         int ret;
5345
5346         memset(&link_status, 0, sizeof(link_status));
5347         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5348         if (ret != I40E_SUCCESS) {
5349                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5350                 goto write_reg; /* Disable flow control */
5351         }
5352
5353         an_info = hw->phy.link_info.an_info;
5354         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5355                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5356                 ret = I40E_ERR_NOT_READY;
5357                 goto write_reg; /* Disable flow control */
5358         }
5359         /**
5360          * If link auto negotiation is enabled, flow control needs to
5361          * be configured according to it
5362          */
5363         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5364         case I40E_LINK_PAUSE_RXTX:
5365                 rxfc = 1;
5366                 txfc = 1;
5367                 hw->fc.current_mode = I40E_FC_FULL;
5368                 break;
5369         case I40E_AQ_LINK_PAUSE_RX:
5370                 rxfc = 1;
5371                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5372                 break;
5373         case I40E_AQ_LINK_PAUSE_TX:
5374                 txfc = 1;
5375                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5376                 break;
5377         default:
5378                 hw->fc.current_mode = I40E_FC_NONE;
5379                 break;
5380         }
5381
5382 write_reg:
5383         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5384                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5385         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5386         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5387         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5388         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5389
5390         return ret;
5391 }
5392
5393 /* PF setup */
5394 static int
5395 i40e_pf_setup(struct i40e_pf *pf)
5396 {
5397         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5398         struct i40e_filter_control_settings settings;
5399         struct i40e_vsi *vsi;
5400         int ret;
5401
5402         /* Clear all stats counters */
5403         pf->offset_loaded = FALSE;
5404         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5405         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5406         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5407         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5408
5409         ret = i40e_pf_get_switch_config(pf);
5410         if (ret != I40E_SUCCESS) {
5411                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5412                 return ret;
5413         }
5414         if (pf->flags & I40E_FLAG_FDIR) {
5415                 /* make queue allocated first, let FDIR use queue pair 0*/
5416                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5417                 if (ret != I40E_FDIR_QUEUE_ID) {
5418                         PMD_DRV_LOG(ERR,
5419                                 "queue allocation fails for FDIR: ret =%d",
5420                                 ret);
5421                         pf->flags &= ~I40E_FLAG_FDIR;
5422                 }
5423         }
5424         /*  main VSI setup */
5425         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5426         if (!vsi) {
5427                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5428                 return I40E_ERR_NOT_READY;
5429         }
5430         pf->main_vsi = vsi;
5431
5432         /* Configure filter control */
5433         memset(&settings, 0, sizeof(settings));
5434         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5435                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5436         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5437                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5438         else {
5439                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5440                         hw->func_caps.rss_table_size);
5441                 return I40E_ERR_PARAM;
5442         }
5443         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5444                 hw->func_caps.rss_table_size);
5445         pf->hash_lut_size = hw->func_caps.rss_table_size;
5446
5447         /* Enable ethtype and macvlan filters */
5448         settings.enable_ethtype = TRUE;
5449         settings.enable_macvlan = TRUE;
5450         ret = i40e_set_filter_control(hw, &settings);
5451         if (ret)
5452                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5453                                                                 ret);
5454
5455         /* Update flow control according to the auto negotiation */
5456         i40e_update_flow_control(hw);
5457
5458         return I40E_SUCCESS;
5459 }
5460
5461 int
5462 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5463 {
5464         uint32_t reg;
5465         uint16_t j;
5466
5467         /**
5468          * Set or clear TX Queue Disable flags,
5469          * which is required by hardware.
5470          */
5471         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5472         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5473
5474         /* Wait until the request is finished */
5475         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5476                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5477                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5478                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5479                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5480                                                         & 0x1))) {
5481                         break;
5482                 }
5483         }
5484         if (on) {
5485                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5486                         return I40E_SUCCESS; /* already on, skip next steps */
5487
5488                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5489                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5490         } else {
5491                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5492                         return I40E_SUCCESS; /* already off, skip next steps */
5493                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5494         }
5495         /* Write the register */
5496         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5497         /* Check the result */
5498         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5499                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5500                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5501                 if (on) {
5502                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5503                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5504                                 break;
5505                 } else {
5506                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5507                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5508                                 break;
5509                 }
5510         }
5511         /* Check if it is timeout */
5512         if (j >= I40E_CHK_Q_ENA_COUNT) {
5513                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5514                             (on ? "enable" : "disable"), q_idx);
5515                 return I40E_ERR_TIMEOUT;
5516         }
5517
5518         return I40E_SUCCESS;
5519 }
5520
5521 /* Swith on or off the tx queues */
5522 static int
5523 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5524 {
5525         struct rte_eth_dev_data *dev_data = pf->dev_data;
5526         struct i40e_tx_queue *txq;
5527         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5528         uint16_t i;
5529         int ret;
5530
5531         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5532                 txq = dev_data->tx_queues[i];
5533                 /* Don't operate the queue if not configured or
5534                  * if starting only per queue */
5535                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5536                         continue;
5537                 if (on)
5538                         ret = i40e_dev_tx_queue_start(dev, i);
5539                 else
5540                         ret = i40e_dev_tx_queue_stop(dev, i);
5541                 if ( ret != I40E_SUCCESS)
5542                         return ret;
5543         }
5544
5545         return I40E_SUCCESS;
5546 }
5547
5548 int
5549 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5550 {
5551         uint32_t reg;
5552         uint16_t j;
5553
5554         /* Wait until the request is finished */
5555         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5556                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5557                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5558                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5559                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5560                         break;
5561         }
5562
5563         if (on) {
5564                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5565                         return I40E_SUCCESS; /* Already on, skip next steps */
5566                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5567         } else {
5568                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5569                         return I40E_SUCCESS; /* Already off, skip next steps */
5570                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5571         }
5572
5573         /* Write the register */
5574         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5575         /* Check the result */
5576         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5577                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5578                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5579                 if (on) {
5580                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5581                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5582                                 break;
5583                 } else {
5584                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5585                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5586                                 break;
5587                 }
5588         }
5589
5590         /* Check if it is timeout */
5591         if (j >= I40E_CHK_Q_ENA_COUNT) {
5592                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5593                             (on ? "enable" : "disable"), q_idx);
5594                 return I40E_ERR_TIMEOUT;
5595         }
5596
5597         return I40E_SUCCESS;
5598 }
5599 /* Switch on or off the rx queues */
5600 static int
5601 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5602 {
5603         struct rte_eth_dev_data *dev_data = pf->dev_data;
5604         struct i40e_rx_queue *rxq;
5605         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5606         uint16_t i;
5607         int ret;
5608
5609         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5610                 rxq = dev_data->rx_queues[i];
5611                 /* Don't operate the queue if not configured or
5612                  * if starting only per queue */
5613                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5614                         continue;
5615                 if (on)
5616                         ret = i40e_dev_rx_queue_start(dev, i);
5617                 else
5618                         ret = i40e_dev_rx_queue_stop(dev, i);
5619                 if (ret != I40E_SUCCESS)
5620                         return ret;
5621         }
5622
5623         return I40E_SUCCESS;
5624 }
5625
5626 /* Switch on or off all the rx/tx queues */
5627 int
5628 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5629 {
5630         int ret;
5631
5632         if (on) {
5633                 /* enable rx queues before enabling tx queues */
5634                 ret = i40e_dev_switch_rx_queues(pf, on);
5635                 if (ret) {
5636                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5637                         return ret;
5638                 }
5639                 ret = i40e_dev_switch_tx_queues(pf, on);
5640         } else {
5641                 /* Stop tx queues before stopping rx queues */
5642                 ret = i40e_dev_switch_tx_queues(pf, on);
5643                 if (ret) {
5644                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5645                         return ret;
5646                 }
5647                 ret = i40e_dev_switch_rx_queues(pf, on);
5648         }
5649
5650         return ret;
5651 }
5652
5653 /* Initialize VSI for TX */
5654 static int
5655 i40e_dev_tx_init(struct i40e_pf *pf)
5656 {
5657         struct rte_eth_dev_data *data = pf->dev_data;
5658         uint16_t i;
5659         uint32_t ret = I40E_SUCCESS;
5660         struct i40e_tx_queue *txq;
5661
5662         for (i = 0; i < data->nb_tx_queues; i++) {
5663                 txq = data->tx_queues[i];
5664                 if (!txq || !txq->q_set)
5665                         continue;
5666                 ret = i40e_tx_queue_init(txq);
5667                 if (ret != I40E_SUCCESS)
5668                         break;
5669         }
5670         if (ret == I40E_SUCCESS)
5671                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5672                                      ->eth_dev);
5673
5674         return ret;
5675 }
5676
5677 /* Initialize VSI for RX */
5678 static int
5679 i40e_dev_rx_init(struct i40e_pf *pf)
5680 {
5681         struct rte_eth_dev_data *data = pf->dev_data;
5682         int ret = I40E_SUCCESS;
5683         uint16_t i;
5684         struct i40e_rx_queue *rxq;
5685
5686         i40e_pf_config_mq_rx(pf);
5687         for (i = 0; i < data->nb_rx_queues; i++) {
5688                 rxq = data->rx_queues[i];
5689                 if (!rxq || !rxq->q_set)
5690                         continue;
5691
5692                 ret = i40e_rx_queue_init(rxq);
5693                 if (ret != I40E_SUCCESS) {
5694                         PMD_DRV_LOG(ERR,
5695                                 "Failed to do RX queue initialization");
5696                         break;
5697                 }
5698         }
5699         if (ret == I40E_SUCCESS)
5700                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5701                                      ->eth_dev);
5702
5703         return ret;
5704 }
5705
5706 static int
5707 i40e_dev_rxtx_init(struct i40e_pf *pf)
5708 {
5709         int err;
5710
5711         err = i40e_dev_tx_init(pf);
5712         if (err) {
5713                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5714                 return err;
5715         }
5716         err = i40e_dev_rx_init(pf);
5717         if (err) {
5718                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5719                 return err;
5720         }
5721
5722         return err;
5723 }
5724
5725 static int
5726 i40e_vmdq_setup(struct rte_eth_dev *dev)
5727 {
5728         struct rte_eth_conf *conf = &dev->data->dev_conf;
5729         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5730         int i, err, conf_vsis, j, loop;
5731         struct i40e_vsi *vsi;
5732         struct i40e_vmdq_info *vmdq_info;
5733         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5734         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5735
5736         /*
5737          * Disable interrupt to avoid message from VF. Furthermore, it will
5738          * avoid race condition in VSI creation/destroy.
5739          */
5740         i40e_pf_disable_irq0(hw);
5741
5742         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5743                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5744                 return -ENOTSUP;
5745         }
5746
5747         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5748         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5749                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5750                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5751                         pf->max_nb_vmdq_vsi);
5752                 return -ENOTSUP;
5753         }
5754
5755         if (pf->vmdq != NULL) {
5756                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5757                 return 0;
5758         }
5759
5760         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5761                                 sizeof(*vmdq_info) * conf_vsis, 0);
5762
5763         if (pf->vmdq == NULL) {
5764                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5765                 return -ENOMEM;
5766         }
5767
5768         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5769
5770         /* Create VMDQ VSI */
5771         for (i = 0; i < conf_vsis; i++) {
5772                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5773                                 vmdq_conf->enable_loop_back);
5774                 if (vsi == NULL) {
5775                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5776                         err = -1;
5777                         goto err_vsi_setup;
5778                 }
5779                 vmdq_info = &pf->vmdq[i];
5780                 vmdq_info->pf = pf;
5781                 vmdq_info->vsi = vsi;
5782         }
5783         pf->nb_cfg_vmdq_vsi = conf_vsis;
5784
5785         /* Configure Vlan */
5786         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5787         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5788                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5789                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5790                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5791                                         vmdq_conf->pool_map[i].vlan_id, j);
5792
5793                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5794                                                 vmdq_conf->pool_map[i].vlan_id);
5795                                 if (err) {
5796                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5797                                         err = -1;
5798                                         goto err_vsi_setup;
5799                                 }
5800                         }
5801                 }
5802         }
5803
5804         i40e_pf_enable_irq0(hw);
5805
5806         return 0;
5807
5808 err_vsi_setup:
5809         for (i = 0; i < conf_vsis; i++)
5810                 if (pf->vmdq[i].vsi == NULL)
5811                         break;
5812                 else
5813                         i40e_vsi_release(pf->vmdq[i].vsi);
5814
5815         rte_free(pf->vmdq);
5816         pf->vmdq = NULL;
5817         i40e_pf_enable_irq0(hw);
5818         return err;
5819 }
5820
5821 static void
5822 i40e_stat_update_32(struct i40e_hw *hw,
5823                    uint32_t reg,
5824                    bool offset_loaded,
5825                    uint64_t *offset,
5826                    uint64_t *stat)
5827 {
5828         uint64_t new_data;
5829
5830         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5831         if (!offset_loaded)
5832                 *offset = new_data;
5833
5834         if (new_data >= *offset)
5835                 *stat = (uint64_t)(new_data - *offset);
5836         else
5837                 *stat = (uint64_t)((new_data +
5838                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5839 }
5840
5841 static void
5842 i40e_stat_update_48(struct i40e_hw *hw,
5843                    uint32_t hireg,
5844                    uint32_t loreg,
5845                    bool offset_loaded,
5846                    uint64_t *offset,
5847                    uint64_t *stat)
5848 {
5849         uint64_t new_data;
5850
5851         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5852         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5853                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5854
5855         if (!offset_loaded)
5856                 *offset = new_data;
5857
5858         if (new_data >= *offset)
5859                 *stat = new_data - *offset;
5860         else
5861                 *stat = (uint64_t)((new_data +
5862                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5863
5864         *stat &= I40E_48_BIT_MASK;
5865 }
5866
5867 /* Disable IRQ0 */
5868 void
5869 i40e_pf_disable_irq0(struct i40e_hw *hw)
5870 {
5871         /* Disable all interrupt types */
5872         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5873         I40E_WRITE_FLUSH(hw);
5874 }
5875
5876 /* Enable IRQ0 */
5877 void
5878 i40e_pf_enable_irq0(struct i40e_hw *hw)
5879 {
5880         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5881                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5882                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5883                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5884         I40E_WRITE_FLUSH(hw);
5885 }
5886
5887 static void
5888 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5889 {
5890         /* read pending request and disable first */
5891         i40e_pf_disable_irq0(hw);
5892         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5893         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5894                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5895
5896         if (no_queue)
5897                 /* Link no queues with irq0 */
5898                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5899                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5900 }
5901
5902 static void
5903 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5904 {
5905         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5906         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5907         int i;
5908         uint16_t abs_vf_id;
5909         uint32_t index, offset, val;
5910
5911         if (!pf->vfs)
5912                 return;
5913         /**
5914          * Try to find which VF trigger a reset, use absolute VF id to access
5915          * since the reg is global register.
5916          */
5917         for (i = 0; i < pf->vf_num; i++) {
5918                 abs_vf_id = hw->func_caps.vf_base_id + i;
5919                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5920                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5921                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5922                 /* VFR event occurred */
5923                 if (val & (0x1 << offset)) {
5924                         int ret;
5925
5926                         /* Clear the event first */
5927                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5928                                                         (0x1 << offset));
5929                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5930                         /**
5931                          * Only notify a VF reset event occurred,
5932                          * don't trigger another SW reset
5933                          */
5934                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5935                         if (ret != I40E_SUCCESS)
5936                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5937                 }
5938         }
5939 }
5940
5941 static void
5942 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5943 {
5944         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5945         int i;
5946
5947         for (i = 0; i < pf->vf_num; i++)
5948                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5949 }
5950
5951 static void
5952 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5953 {
5954         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5955         struct i40e_arq_event_info info;
5956         uint16_t pending, opcode;
5957         int ret;
5958
5959         info.buf_len = I40E_AQ_BUF_SZ;
5960         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5961         if (!info.msg_buf) {
5962                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5963                 return;
5964         }
5965
5966         pending = 1;
5967         while (pending) {
5968                 ret = i40e_clean_arq_element(hw, &info, &pending);
5969
5970                 if (ret != I40E_SUCCESS) {
5971                         PMD_DRV_LOG(INFO,
5972                                 "Failed to read msg from AdminQ, aq_err: %u",
5973                                 hw->aq.asq_last_status);
5974                         break;
5975                 }
5976                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5977
5978                 switch (opcode) {
5979                 case i40e_aqc_opc_send_msg_to_pf:
5980                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5981                         i40e_pf_host_handle_vf_msg(dev,
5982                                         rte_le_to_cpu_16(info.desc.retval),
5983                                         rte_le_to_cpu_32(info.desc.cookie_high),
5984                                         rte_le_to_cpu_32(info.desc.cookie_low),
5985                                         info.msg_buf,
5986                                         info.msg_len);
5987                         break;
5988                 case i40e_aqc_opc_get_link_status:
5989                         ret = i40e_dev_link_update(dev, 0);
5990                         if (!ret)
5991                                 _rte_eth_dev_callback_process(dev,
5992                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5993                         break;
5994                 default:
5995                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5996                                     opcode);
5997                         break;
5998                 }
5999         }
6000         rte_free(info.msg_buf);
6001 }
6002
6003 /**
6004  * Interrupt handler triggered by NIC  for handling
6005  * specific interrupt.
6006  *
6007  * @param handle
6008  *  Pointer to interrupt handle.
6009  * @param param
6010  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6011  *
6012  * @return
6013  *  void
6014  */
6015 static void
6016 i40e_dev_interrupt_handler(void *param)
6017 {
6018         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6019         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6020         uint32_t icr0;
6021
6022         /* Disable interrupt */
6023         i40e_pf_disable_irq0(hw);
6024
6025         /* read out interrupt causes */
6026         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6027
6028         /* No interrupt event indicated */
6029         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6030                 PMD_DRV_LOG(INFO, "No interrupt event");
6031                 goto done;
6032         }
6033         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6034                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6035         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6036                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6037         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6038                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6039         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6040                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6041         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6042                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6043         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6044                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6045         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6046                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6047
6048         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6049                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6050                 i40e_dev_handle_vfr_event(dev);
6051         }
6052         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6053                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6054                 i40e_dev_handle_aq_msg(dev);
6055         }
6056
6057 done:
6058         /* Enable interrupt */
6059         i40e_pf_enable_irq0(hw);
6060         rte_intr_enable(dev->intr_handle);
6061 }
6062
6063 int
6064 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6065                          struct i40e_macvlan_filter *filter,
6066                          int total)
6067 {
6068         int ele_num, ele_buff_size;
6069         int num, actual_num, i;
6070         uint16_t flags;
6071         int ret = I40E_SUCCESS;
6072         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6073         struct i40e_aqc_add_macvlan_element_data *req_list;
6074
6075         if (filter == NULL  || total == 0)
6076                 return I40E_ERR_PARAM;
6077         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6078         ele_buff_size = hw->aq.asq_buf_size;
6079
6080         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6081         if (req_list == NULL) {
6082                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6083                 return I40E_ERR_NO_MEMORY;
6084         }
6085
6086         num = 0;
6087         do {
6088                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6089                 memset(req_list, 0, ele_buff_size);
6090
6091                 for (i = 0; i < actual_num; i++) {
6092                         rte_memcpy(req_list[i].mac_addr,
6093                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6094                         req_list[i].vlan_tag =
6095                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6096
6097                         switch (filter[num + i].filter_type) {
6098                         case RTE_MAC_PERFECT_MATCH:
6099                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6100                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6101                                 break;
6102                         case RTE_MACVLAN_PERFECT_MATCH:
6103                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6104                                 break;
6105                         case RTE_MAC_HASH_MATCH:
6106                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6107                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6108                                 break;
6109                         case RTE_MACVLAN_HASH_MATCH:
6110                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6111                                 break;
6112                         default:
6113                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6114                                 ret = I40E_ERR_PARAM;
6115                                 goto DONE;
6116                         }
6117
6118                         req_list[i].queue_number = 0;
6119
6120                         req_list[i].flags = rte_cpu_to_le_16(flags);
6121                 }
6122
6123                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6124                                                 actual_num, NULL);
6125                 if (ret != I40E_SUCCESS) {
6126                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6127                         goto DONE;
6128                 }
6129                 num += actual_num;
6130         } while (num < total);
6131
6132 DONE:
6133         rte_free(req_list);
6134         return ret;
6135 }
6136
6137 int
6138 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6139                             struct i40e_macvlan_filter *filter,
6140                             int total)
6141 {
6142         int ele_num, ele_buff_size;
6143         int num, actual_num, i;
6144         uint16_t flags;
6145         int ret = I40E_SUCCESS;
6146         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6147         struct i40e_aqc_remove_macvlan_element_data *req_list;
6148
6149         if (filter == NULL  || total == 0)
6150                 return I40E_ERR_PARAM;
6151
6152         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6153         ele_buff_size = hw->aq.asq_buf_size;
6154
6155         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6156         if (req_list == NULL) {
6157                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6158                 return I40E_ERR_NO_MEMORY;
6159         }
6160
6161         num = 0;
6162         do {
6163                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6164                 memset(req_list, 0, ele_buff_size);
6165
6166                 for (i = 0; i < actual_num; i++) {
6167                         rte_memcpy(req_list[i].mac_addr,
6168                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6169                         req_list[i].vlan_tag =
6170                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6171
6172                         switch (filter[num + i].filter_type) {
6173                         case RTE_MAC_PERFECT_MATCH:
6174                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6175                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6176                                 break;
6177                         case RTE_MACVLAN_PERFECT_MATCH:
6178                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6179                                 break;
6180                         case RTE_MAC_HASH_MATCH:
6181                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6182                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6183                                 break;
6184                         case RTE_MACVLAN_HASH_MATCH:
6185                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6186                                 break;
6187                         default:
6188                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6189                                 ret = I40E_ERR_PARAM;
6190                                 goto DONE;
6191                         }
6192                         req_list[i].flags = rte_cpu_to_le_16(flags);
6193                 }
6194
6195                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6196                                                 actual_num, NULL);
6197                 if (ret != I40E_SUCCESS) {
6198                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6199                         goto DONE;
6200                 }
6201                 num += actual_num;
6202         } while (num < total);
6203
6204 DONE:
6205         rte_free(req_list);
6206         return ret;
6207 }
6208
6209 /* Find out specific MAC filter */
6210 static struct i40e_mac_filter *
6211 i40e_find_mac_filter(struct i40e_vsi *vsi,
6212                          struct ether_addr *macaddr)
6213 {
6214         struct i40e_mac_filter *f;
6215
6216         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6217                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6218                         return f;
6219         }
6220
6221         return NULL;
6222 }
6223
6224 static bool
6225 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6226                          uint16_t vlan_id)
6227 {
6228         uint32_t vid_idx, vid_bit;
6229
6230         if (vlan_id > ETH_VLAN_ID_MAX)
6231                 return 0;
6232
6233         vid_idx = I40E_VFTA_IDX(vlan_id);
6234         vid_bit = I40E_VFTA_BIT(vlan_id);
6235
6236         if (vsi->vfta[vid_idx] & vid_bit)
6237                 return 1;
6238         else
6239                 return 0;
6240 }
6241
6242 static void
6243 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6244                        uint16_t vlan_id, bool on)
6245 {
6246         uint32_t vid_idx, vid_bit;
6247
6248         vid_idx = I40E_VFTA_IDX(vlan_id);
6249         vid_bit = I40E_VFTA_BIT(vlan_id);
6250
6251         if (on)
6252                 vsi->vfta[vid_idx] |= vid_bit;
6253         else
6254                 vsi->vfta[vid_idx] &= ~vid_bit;
6255 }
6256
6257 void
6258 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6259                      uint16_t vlan_id, bool on)
6260 {
6261         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6262         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6263         int ret;
6264
6265         if (vlan_id > ETH_VLAN_ID_MAX)
6266                 return;
6267
6268         i40e_store_vlan_filter(vsi, vlan_id, on);
6269
6270         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6271                 return;
6272
6273         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6274
6275         if (on) {
6276                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6277                                        &vlan_data, 1, NULL);
6278                 if (ret != I40E_SUCCESS)
6279                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6280         } else {
6281                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6282                                           &vlan_data, 1, NULL);
6283                 if (ret != I40E_SUCCESS)
6284                         PMD_DRV_LOG(ERR,
6285                                     "Failed to remove vlan filter");
6286         }
6287 }
6288
6289 /**
6290  * Find all vlan options for specific mac addr,
6291  * return with actual vlan found.
6292  */
6293 int
6294 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6295                            struct i40e_macvlan_filter *mv_f,
6296                            int num, struct ether_addr *addr)
6297 {
6298         int i;
6299         uint32_t j, k;
6300
6301         /**
6302          * Not to use i40e_find_vlan_filter to decrease the loop time,
6303          * although the code looks complex.
6304           */
6305         if (num < vsi->vlan_num)
6306                 return I40E_ERR_PARAM;
6307
6308         i = 0;
6309         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6310                 if (vsi->vfta[j]) {
6311                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6312                                 if (vsi->vfta[j] & (1 << k)) {
6313                                         if (i > num - 1) {
6314                                                 PMD_DRV_LOG(ERR,
6315                                                         "vlan number doesn't match");
6316                                                 return I40E_ERR_PARAM;
6317                                         }
6318                                         rte_memcpy(&mv_f[i].macaddr,
6319                                                         addr, ETH_ADDR_LEN);
6320                                         mv_f[i].vlan_id =
6321                                                 j * I40E_UINT32_BIT_SIZE + k;
6322                                         i++;
6323                                 }
6324                         }
6325                 }
6326         }
6327         return I40E_SUCCESS;
6328 }
6329
6330 static inline int
6331 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6332                            struct i40e_macvlan_filter *mv_f,
6333                            int num,
6334                            uint16_t vlan)
6335 {
6336         int i = 0;
6337         struct i40e_mac_filter *f;
6338
6339         if (num < vsi->mac_num)
6340                 return I40E_ERR_PARAM;
6341
6342         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6343                 if (i > num - 1) {
6344                         PMD_DRV_LOG(ERR, "buffer number not match");
6345                         return I40E_ERR_PARAM;
6346                 }
6347                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6348                                 ETH_ADDR_LEN);
6349                 mv_f[i].vlan_id = vlan;
6350                 mv_f[i].filter_type = f->mac_info.filter_type;
6351                 i++;
6352         }
6353
6354         return I40E_SUCCESS;
6355 }
6356
6357 static int
6358 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6359 {
6360         int i, j, num;
6361         struct i40e_mac_filter *f;
6362         struct i40e_macvlan_filter *mv_f;
6363         int ret = I40E_SUCCESS;
6364
6365         if (vsi == NULL || vsi->mac_num == 0)
6366                 return I40E_ERR_PARAM;
6367
6368         /* Case that no vlan is set */
6369         if (vsi->vlan_num == 0)
6370                 num = vsi->mac_num;
6371         else
6372                 num = vsi->mac_num * vsi->vlan_num;
6373
6374         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6375         if (mv_f == NULL) {
6376                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6377                 return I40E_ERR_NO_MEMORY;
6378         }
6379
6380         i = 0;
6381         if (vsi->vlan_num == 0) {
6382                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6383                         rte_memcpy(&mv_f[i].macaddr,
6384                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6385                         mv_f[i].filter_type = f->mac_info.filter_type;
6386                         mv_f[i].vlan_id = 0;
6387                         i++;
6388                 }
6389         } else {
6390                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6391                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6392                                         vsi->vlan_num, &f->mac_info.mac_addr);
6393                         if (ret != I40E_SUCCESS)
6394                                 goto DONE;
6395                         for (j = i; j < i + vsi->vlan_num; j++)
6396                                 mv_f[j].filter_type = f->mac_info.filter_type;
6397                         i += vsi->vlan_num;
6398                 }
6399         }
6400
6401         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6402 DONE:
6403         rte_free(mv_f);
6404
6405         return ret;
6406 }
6407
6408 int
6409 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6410 {
6411         struct i40e_macvlan_filter *mv_f;
6412         int mac_num;
6413         int ret = I40E_SUCCESS;
6414
6415         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6416                 return I40E_ERR_PARAM;
6417
6418         /* If it's already set, just return */
6419         if (i40e_find_vlan_filter(vsi,vlan))
6420                 return I40E_SUCCESS;
6421
6422         mac_num = vsi->mac_num;
6423
6424         if (mac_num == 0) {
6425                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6426                 return I40E_ERR_PARAM;
6427         }
6428
6429         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6430
6431         if (mv_f == NULL) {
6432                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6433                 return I40E_ERR_NO_MEMORY;
6434         }
6435
6436         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6437
6438         if (ret != I40E_SUCCESS)
6439                 goto DONE;
6440
6441         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6442
6443         if (ret != I40E_SUCCESS)
6444                 goto DONE;
6445
6446         i40e_set_vlan_filter(vsi, vlan, 1);
6447
6448         vsi->vlan_num++;
6449         ret = I40E_SUCCESS;
6450 DONE:
6451         rte_free(mv_f);
6452         return ret;
6453 }
6454
6455 int
6456 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6457 {
6458         struct i40e_macvlan_filter *mv_f;
6459         int mac_num;
6460         int ret = I40E_SUCCESS;
6461
6462         /**
6463          * Vlan 0 is the generic filter for untagged packets
6464          * and can't be removed.
6465          */
6466         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6467                 return I40E_ERR_PARAM;
6468
6469         /* If can't find it, just return */
6470         if (!i40e_find_vlan_filter(vsi, vlan))
6471                 return I40E_ERR_PARAM;
6472
6473         mac_num = vsi->mac_num;
6474
6475         if (mac_num == 0) {
6476                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6477                 return I40E_ERR_PARAM;
6478         }
6479
6480         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6481
6482         if (mv_f == NULL) {
6483                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6484                 return I40E_ERR_NO_MEMORY;
6485         }
6486
6487         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6488
6489         if (ret != I40E_SUCCESS)
6490                 goto DONE;
6491
6492         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6493
6494         if (ret != I40E_SUCCESS)
6495                 goto DONE;
6496
6497         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6498         if (vsi->vlan_num == 1) {
6499                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6500                 if (ret != I40E_SUCCESS)
6501                         goto DONE;
6502
6503                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6504                 if (ret != I40E_SUCCESS)
6505                         goto DONE;
6506         }
6507
6508         i40e_set_vlan_filter(vsi, vlan, 0);
6509
6510         vsi->vlan_num--;
6511         ret = I40E_SUCCESS;
6512 DONE:
6513         rte_free(mv_f);
6514         return ret;
6515 }
6516
6517 int
6518 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6519 {
6520         struct i40e_mac_filter *f;
6521         struct i40e_macvlan_filter *mv_f;
6522         int i, vlan_num = 0;
6523         int ret = I40E_SUCCESS;
6524
6525         /* If it's add and we've config it, return */
6526         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6527         if (f != NULL)
6528                 return I40E_SUCCESS;
6529         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6530                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6531
6532                 /**
6533                  * If vlan_num is 0, that's the first time to add mac,
6534                  * set mask for vlan_id 0.
6535                  */
6536                 if (vsi->vlan_num == 0) {
6537                         i40e_set_vlan_filter(vsi, 0, 1);
6538                         vsi->vlan_num = 1;
6539                 }
6540                 vlan_num = vsi->vlan_num;
6541         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6542                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6543                 vlan_num = 1;
6544
6545         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6546         if (mv_f == NULL) {
6547                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6548                 return I40E_ERR_NO_MEMORY;
6549         }
6550
6551         for (i = 0; i < vlan_num; i++) {
6552                 mv_f[i].filter_type = mac_filter->filter_type;
6553                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6554                                 ETH_ADDR_LEN);
6555         }
6556
6557         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6558                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6559                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6560                                         &mac_filter->mac_addr);
6561                 if (ret != I40E_SUCCESS)
6562                         goto DONE;
6563         }
6564
6565         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6566         if (ret != I40E_SUCCESS)
6567                 goto DONE;
6568
6569         /* Add the mac addr into mac list */
6570         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6571         if (f == NULL) {
6572                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6573                 ret = I40E_ERR_NO_MEMORY;
6574                 goto DONE;
6575         }
6576         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6577                         ETH_ADDR_LEN);
6578         f->mac_info.filter_type = mac_filter->filter_type;
6579         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6580         vsi->mac_num++;
6581
6582         ret = I40E_SUCCESS;
6583 DONE:
6584         rte_free(mv_f);
6585
6586         return ret;
6587 }
6588
6589 int
6590 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6591 {
6592         struct i40e_mac_filter *f;
6593         struct i40e_macvlan_filter *mv_f;
6594         int i, vlan_num;
6595         enum rte_mac_filter_type filter_type;
6596         int ret = I40E_SUCCESS;
6597
6598         /* Can't find it, return an error */
6599         f = i40e_find_mac_filter(vsi, addr);
6600         if (f == NULL)
6601                 return I40E_ERR_PARAM;
6602
6603         vlan_num = vsi->vlan_num;
6604         filter_type = f->mac_info.filter_type;
6605         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6606                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6607                 if (vlan_num == 0) {
6608                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6609                         return I40E_ERR_PARAM;
6610                 }
6611         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6612                         filter_type == RTE_MAC_HASH_MATCH)
6613                 vlan_num = 1;
6614
6615         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6616         if (mv_f == NULL) {
6617                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6618                 return I40E_ERR_NO_MEMORY;
6619         }
6620
6621         for (i = 0; i < vlan_num; i++) {
6622                 mv_f[i].filter_type = filter_type;
6623                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6624                                 ETH_ADDR_LEN);
6625         }
6626         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6627                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6628                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6629                 if (ret != I40E_SUCCESS)
6630                         goto DONE;
6631         }
6632
6633         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6634         if (ret != I40E_SUCCESS)
6635                 goto DONE;
6636
6637         /* Remove the mac addr into mac list */
6638         TAILQ_REMOVE(&vsi->mac_list, f, next);
6639         rte_free(f);
6640         vsi->mac_num--;
6641
6642         ret = I40E_SUCCESS;
6643 DONE:
6644         rte_free(mv_f);
6645         return ret;
6646 }
6647
6648 /* Configure hash enable flags for RSS */
6649 uint64_t
6650 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6651 {
6652         uint64_t hena = 0;
6653         int i;
6654
6655         if (!flags)
6656                 return hena;
6657
6658         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6659                 if (flags & (1ULL << i))
6660                         hena |= adapter->pctypes_tbl[i];
6661         }
6662
6663         return hena;
6664 }
6665
6666 /* Parse the hash enable flags */
6667 uint64_t
6668 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6669 {
6670         uint64_t rss_hf = 0;
6671
6672         if (!flags)
6673                 return rss_hf;
6674         int i;
6675
6676         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6677                 if (flags & adapter->pctypes_tbl[i])
6678                         rss_hf |= (1ULL << i);
6679         }
6680         return rss_hf;
6681 }
6682
6683 /* Disable RSS */
6684 static void
6685 i40e_pf_disable_rss(struct i40e_pf *pf)
6686 {
6687         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6688
6689         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6690         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6691         I40E_WRITE_FLUSH(hw);
6692 }
6693
6694 static int
6695 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6696 {
6697         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6698         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6699         int ret = 0;
6700
6701         if (!key || key_len == 0) {
6702                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6703                 return 0;
6704         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6705                 sizeof(uint32_t)) {
6706                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6707                 return -EINVAL;
6708         }
6709
6710         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6711                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6712                         (struct i40e_aqc_get_set_rss_key_data *)key;
6713
6714                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6715                 if (ret)
6716                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6717         } else {
6718                 uint32_t *hash_key = (uint32_t *)key;
6719                 uint16_t i;
6720
6721                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6722                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6723                 I40E_WRITE_FLUSH(hw);
6724         }
6725
6726         return ret;
6727 }
6728
6729 static int
6730 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6731 {
6732         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6733         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6734         int ret;
6735
6736         if (!key || !key_len)
6737                 return -EINVAL;
6738
6739         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6740                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6741                         (struct i40e_aqc_get_set_rss_key_data *)key);
6742                 if (ret) {
6743                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6744                         return ret;
6745                 }
6746         } else {
6747                 uint32_t *key_dw = (uint32_t *)key;
6748                 uint16_t i;
6749
6750                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6751                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6752         }
6753         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6754
6755         return 0;
6756 }
6757
6758 static int
6759 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6760 {
6761         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6762         uint64_t hena;
6763         int ret;
6764
6765         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6766                                rss_conf->rss_key_len);
6767         if (ret)
6768                 return ret;
6769
6770         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6771         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6772         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6773         I40E_WRITE_FLUSH(hw);
6774
6775         return 0;
6776 }
6777
6778 static int
6779 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6780                          struct rte_eth_rss_conf *rss_conf)
6781 {
6782         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6783         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6784         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6785         uint64_t hena;
6786
6787         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6788         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6789
6790         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6791                 if (rss_hf != 0) /* Enable RSS */
6792                         return -EINVAL;
6793                 return 0; /* Nothing to do */
6794         }
6795         /* RSS enabled */
6796         if (rss_hf == 0) /* Disable RSS */
6797                 return -EINVAL;
6798
6799         return i40e_hw_rss_hash_set(pf, rss_conf);
6800 }
6801
6802 static int
6803 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6804                            struct rte_eth_rss_conf *rss_conf)
6805 {
6806         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6807         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6808         uint64_t hena;
6809
6810         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6811                          &rss_conf->rss_key_len);
6812
6813         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6814         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6815         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6816
6817         return 0;
6818 }
6819
6820 static int
6821 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6822 {
6823         switch (filter_type) {
6824         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6825                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6826                 break;
6827         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6828                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6829                 break;
6830         case RTE_TUNNEL_FILTER_IMAC_TENID:
6831                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6832                 break;
6833         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6834                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6835                 break;
6836         case ETH_TUNNEL_FILTER_IMAC:
6837                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6838                 break;
6839         case ETH_TUNNEL_FILTER_OIP:
6840                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6841                 break;
6842         case ETH_TUNNEL_FILTER_IIP:
6843                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6844                 break;
6845         default:
6846                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6847                 return -EINVAL;
6848         }
6849
6850         return 0;
6851 }
6852
6853 /* Convert tunnel filter structure */
6854 static int
6855 i40e_tunnel_filter_convert(
6856         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6857         struct i40e_tunnel_filter *tunnel_filter)
6858 {
6859         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6860                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6861         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6862                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6863         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6864         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6865              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6866             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6867                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6868         else
6869                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6870         tunnel_filter->input.flags = cld_filter->element.flags;
6871         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6872         tunnel_filter->queue = cld_filter->element.queue_number;
6873         rte_memcpy(tunnel_filter->input.general_fields,
6874                    cld_filter->general_fields,
6875                    sizeof(cld_filter->general_fields));
6876
6877         return 0;
6878 }
6879
6880 /* Check if there exists the tunnel filter */
6881 struct i40e_tunnel_filter *
6882 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6883                              const struct i40e_tunnel_filter_input *input)
6884 {
6885         int ret;
6886
6887         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6888         if (ret < 0)
6889                 return NULL;
6890
6891         return tunnel_rule->hash_map[ret];
6892 }
6893
6894 /* Add a tunnel filter into the SW list */
6895 static int
6896 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6897                              struct i40e_tunnel_filter *tunnel_filter)
6898 {
6899         struct i40e_tunnel_rule *rule = &pf->tunnel;
6900         int ret;
6901
6902         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6903         if (ret < 0) {
6904                 PMD_DRV_LOG(ERR,
6905                             "Failed to insert tunnel filter to hash table %d!",
6906                             ret);
6907                 return ret;
6908         }
6909         rule->hash_map[ret] = tunnel_filter;
6910
6911         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6912
6913         return 0;
6914 }
6915
6916 /* Delete a tunnel filter from the SW list */
6917 int
6918 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6919                           struct i40e_tunnel_filter_input *input)
6920 {
6921         struct i40e_tunnel_rule *rule = &pf->tunnel;
6922         struct i40e_tunnel_filter *tunnel_filter;
6923         int ret;
6924
6925         ret = rte_hash_del_key(rule->hash_table, input);
6926         if (ret < 0) {
6927                 PMD_DRV_LOG(ERR,
6928                             "Failed to delete tunnel filter to hash table %d!",
6929                             ret);
6930                 return ret;
6931         }
6932         tunnel_filter = rule->hash_map[ret];
6933         rule->hash_map[ret] = NULL;
6934
6935         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6936         rte_free(tunnel_filter);
6937
6938         return 0;
6939 }
6940
6941 int
6942 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6943                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6944                         uint8_t add)
6945 {
6946         uint16_t ip_type;
6947         uint32_t ipv4_addr;
6948         uint8_t i, tun_type = 0;
6949         /* internal varialbe to convert ipv6 byte order */
6950         uint32_t convert_ipv6[4];
6951         int val, ret = 0;
6952         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6953         struct i40e_vsi *vsi = pf->main_vsi;
6954         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6955         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6956         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6957         struct i40e_tunnel_filter *tunnel, *node;
6958         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6959
6960         cld_filter = rte_zmalloc("tunnel_filter",
6961                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6962         0);
6963
6964         if (NULL == cld_filter) {
6965                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6966                 return -ENOMEM;
6967         }
6968         pfilter = cld_filter;
6969
6970         ether_addr_copy(&tunnel_filter->outer_mac,
6971                         (struct ether_addr *)&pfilter->element.outer_mac);
6972         ether_addr_copy(&tunnel_filter->inner_mac,
6973                         (struct ether_addr *)&pfilter->element.inner_mac);
6974
6975         pfilter->element.inner_vlan =
6976                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6977         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6978                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6979                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6980                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6981                                 &rte_cpu_to_le_32(ipv4_addr),
6982                                 sizeof(pfilter->element.ipaddr.v4.data));
6983         } else {
6984                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6985                 for (i = 0; i < 4; i++) {
6986                         convert_ipv6[i] =
6987                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6988                 }
6989                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6990                            &convert_ipv6,
6991                            sizeof(pfilter->element.ipaddr.v6.data));
6992         }
6993
6994         /* check tunneled type */
6995         switch (tunnel_filter->tunnel_type) {
6996         case RTE_TUNNEL_TYPE_VXLAN:
6997                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6998                 break;
6999         case RTE_TUNNEL_TYPE_NVGRE:
7000                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7001                 break;
7002         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7003                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7004                 break;
7005         default:
7006                 /* Other tunnel types is not supported. */
7007                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7008                 rte_free(cld_filter);
7009                 return -EINVAL;
7010         }
7011
7012         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7013                                        &pfilter->element.flags);
7014         if (val < 0) {
7015                 rte_free(cld_filter);
7016                 return -EINVAL;
7017         }
7018
7019         pfilter->element.flags |= rte_cpu_to_le_16(
7020                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7021                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7022         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7023         pfilter->element.queue_number =
7024                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7025
7026         /* Check if there is the filter in SW list */
7027         memset(&check_filter, 0, sizeof(check_filter));
7028         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7029         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7030         if (add && node) {
7031                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7032                 return -EINVAL;
7033         }
7034
7035         if (!add && !node) {
7036                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7037                 return -EINVAL;
7038         }
7039
7040         if (add) {
7041                 ret = i40e_aq_add_cloud_filters(hw,
7042                                         vsi->seid, &cld_filter->element, 1);
7043                 if (ret < 0) {
7044                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7045                         return -ENOTSUP;
7046                 }
7047                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7048                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7049                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7050         } else {
7051                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7052                                                    &cld_filter->element, 1);
7053                 if (ret < 0) {
7054                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7055                         return -ENOTSUP;
7056                 }
7057                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7058         }
7059
7060         rte_free(cld_filter);
7061         return ret;
7062 }
7063
7064 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7065 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7066 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7067 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7068 #define I40E_TR_GRE_KEY_MASK                    0x400
7069 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7070 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7071
7072 static enum
7073 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7074 {
7075         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7076         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7077         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7078         enum i40e_status_code status = I40E_SUCCESS;
7079
7080         memset(&filter_replace, 0,
7081                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7082         memset(&filter_replace_buf, 0,
7083                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7084
7085         /* create L1 filter */
7086         filter_replace.old_filter_type =
7087                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7088         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7089         filter_replace.tr_bit = 0;
7090
7091         /* Prepare the buffer, 3 entries */
7092         filter_replace_buf.data[0] =
7093                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7094         filter_replace_buf.data[0] |=
7095                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7096         filter_replace_buf.data[2] = 0xFF;
7097         filter_replace_buf.data[3] = 0xFF;
7098         filter_replace_buf.data[4] =
7099                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7100         filter_replace_buf.data[4] |=
7101                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7102         filter_replace_buf.data[7] = 0xF0;
7103         filter_replace_buf.data[8]
7104                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7105         filter_replace_buf.data[8] |=
7106                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7107         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7108                 I40E_TR_GENEVE_KEY_MASK |
7109                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7110         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7111                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7112                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7113
7114         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7115                                                &filter_replace_buf);
7116         return status;
7117 }
7118
7119 static enum
7120 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7121 {
7122         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7123         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7124         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7125         enum i40e_status_code status = I40E_SUCCESS;
7126
7127         /* For MPLSoUDP */
7128         memset(&filter_replace, 0,
7129                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7130         memset(&filter_replace_buf, 0,
7131                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7132         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7133                 I40E_AQC_MIRROR_CLOUD_FILTER;
7134         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7135         filter_replace.new_filter_type =
7136                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7137         /* Prepare the buffer, 2 entries */
7138         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7139         filter_replace_buf.data[0] |=
7140                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7141         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7142         filter_replace_buf.data[4] |=
7143                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7144         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7145                                                &filter_replace_buf);
7146         if (status < 0)
7147                 return status;
7148
7149         /* For MPLSoGRE */
7150         memset(&filter_replace, 0,
7151                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7152         memset(&filter_replace_buf, 0,
7153                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7154
7155         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7156                 I40E_AQC_MIRROR_CLOUD_FILTER;
7157         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7158         filter_replace.new_filter_type =
7159                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7160         /* Prepare the buffer, 2 entries */
7161         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7162         filter_replace_buf.data[0] |=
7163                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7164         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7165         filter_replace_buf.data[4] |=
7166                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7167
7168         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7169                                                &filter_replace_buf);
7170         return status;
7171 }
7172
7173 static enum i40e_status_code
7174 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7175 {
7176         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7177         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7178         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7179         enum i40e_status_code status = I40E_SUCCESS;
7180
7181         /* For GTP-C */
7182         memset(&filter_replace, 0,
7183                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7184         memset(&filter_replace_buf, 0,
7185                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7186         /* create L1 filter */
7187         filter_replace.old_filter_type =
7188                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7189         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7190         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7191                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7192         /* Prepare the buffer, 2 entries */
7193         filter_replace_buf.data[0] =
7194                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7195         filter_replace_buf.data[0] |=
7196                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7197         filter_replace_buf.data[2] = 0xFF;
7198         filter_replace_buf.data[3] = 0xFF;
7199         filter_replace_buf.data[4] =
7200                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7201         filter_replace_buf.data[4] |=
7202                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7203         filter_replace_buf.data[6] = 0xFF;
7204         filter_replace_buf.data[7] = 0xFF;
7205         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7206                                                &filter_replace_buf);
7207         if (status < 0)
7208                 return status;
7209
7210         /* for GTP-U */
7211         memset(&filter_replace, 0,
7212                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7213         memset(&filter_replace_buf, 0,
7214                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7215         /* create L1 filter */
7216         filter_replace.old_filter_type =
7217                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7218         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7219         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7220                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7221         /* Prepare the buffer, 2 entries */
7222         filter_replace_buf.data[0] =
7223                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7224         filter_replace_buf.data[0] |=
7225                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7226         filter_replace_buf.data[2] = 0xFF;
7227         filter_replace_buf.data[3] = 0xFF;
7228         filter_replace_buf.data[4] =
7229                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7230         filter_replace_buf.data[4] |=
7231                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7232         filter_replace_buf.data[6] = 0xFF;
7233         filter_replace_buf.data[7] = 0xFF;
7234
7235         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7236                                                &filter_replace_buf);
7237         return status;
7238 }
7239
7240 static enum
7241 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7242 {
7243         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7244         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7245         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7246         enum i40e_status_code status = I40E_SUCCESS;
7247
7248         /* for GTP-C */
7249         memset(&filter_replace, 0,
7250                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7251         memset(&filter_replace_buf, 0,
7252                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7253         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7254         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7255         filter_replace.new_filter_type =
7256                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7257         /* Prepare the buffer, 2 entries */
7258         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7259         filter_replace_buf.data[0] |=
7260                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7261         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7262         filter_replace_buf.data[4] |=
7263                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7264         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7265                                                &filter_replace_buf);
7266         if (status < 0)
7267                 return status;
7268
7269         /* for GTP-U */
7270         memset(&filter_replace, 0,
7271                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7272         memset(&filter_replace_buf, 0,
7273                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7274         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7275         filter_replace.old_filter_type =
7276                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7277         filter_replace.new_filter_type =
7278                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7279         /* Prepare the buffer, 2 entries */
7280         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7281         filter_replace_buf.data[0] |=
7282                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7283         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7284         filter_replace_buf.data[4] |=
7285                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7286
7287         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7288                                                &filter_replace_buf);
7289         return status;
7290 }
7291
7292 int
7293 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7294                       struct i40e_tunnel_filter_conf *tunnel_filter,
7295                       uint8_t add)
7296 {
7297         uint16_t ip_type;
7298         uint32_t ipv4_addr;
7299         uint8_t i, tun_type = 0;
7300         /* internal variable to convert ipv6 byte order */
7301         uint32_t convert_ipv6[4];
7302         int val, ret = 0;
7303         struct i40e_pf_vf *vf = NULL;
7304         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7305         struct i40e_vsi *vsi;
7306         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7307         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7308         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7309         struct i40e_tunnel_filter *tunnel, *node;
7310         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7311         uint32_t teid_le;
7312         bool big_buffer = 0;
7313
7314         cld_filter = rte_zmalloc("tunnel_filter",
7315                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7316                          0);
7317
7318         if (cld_filter == NULL) {
7319                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7320                 return -ENOMEM;
7321         }
7322         pfilter = cld_filter;
7323
7324         ether_addr_copy(&tunnel_filter->outer_mac,
7325                         (struct ether_addr *)&pfilter->element.outer_mac);
7326         ether_addr_copy(&tunnel_filter->inner_mac,
7327                         (struct ether_addr *)&pfilter->element.inner_mac);
7328
7329         pfilter->element.inner_vlan =
7330                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7331         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7332                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7333                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7334                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7335                                 &rte_cpu_to_le_32(ipv4_addr),
7336                                 sizeof(pfilter->element.ipaddr.v4.data));
7337         } else {
7338                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7339                 for (i = 0; i < 4; i++) {
7340                         convert_ipv6[i] =
7341                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7342                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7343                 }
7344                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7345                            &convert_ipv6,
7346                            sizeof(pfilter->element.ipaddr.v6.data));
7347         }
7348
7349         /* check tunneled type */
7350         switch (tunnel_filter->tunnel_type) {
7351         case I40E_TUNNEL_TYPE_VXLAN:
7352                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7353                 break;
7354         case I40E_TUNNEL_TYPE_NVGRE:
7355                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7356                 break;
7357         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7358                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7359                 break;
7360         case I40E_TUNNEL_TYPE_MPLSoUDP:
7361                 if (!pf->mpls_replace_flag) {
7362                         i40e_replace_mpls_l1_filter(pf);
7363                         i40e_replace_mpls_cloud_filter(pf);
7364                         pf->mpls_replace_flag = 1;
7365                 }
7366                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7367                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7368                         teid_le >> 4;
7369                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7370                         (teid_le & 0xF) << 12;
7371                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7372                         0x40;
7373                 big_buffer = 1;
7374                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7375                 break;
7376         case I40E_TUNNEL_TYPE_MPLSoGRE:
7377                 if (!pf->mpls_replace_flag) {
7378                         i40e_replace_mpls_l1_filter(pf);
7379                         i40e_replace_mpls_cloud_filter(pf);
7380                         pf->mpls_replace_flag = 1;
7381                 }
7382                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7383                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7384                         teid_le >> 4;
7385                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7386                         (teid_le & 0xF) << 12;
7387                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7388                         0x0;
7389                 big_buffer = 1;
7390                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7391                 break;
7392         case I40E_TUNNEL_TYPE_GTPC:
7393                 if (!pf->gtp_replace_flag) {
7394                         i40e_replace_gtp_l1_filter(pf);
7395                         i40e_replace_gtp_cloud_filter(pf);
7396                         pf->gtp_replace_flag = 1;
7397                 }
7398                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7399                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7400                         (teid_le >> 16) & 0xFFFF;
7401                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7402                         teid_le & 0xFFFF;
7403                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7404                         0x0;
7405                 big_buffer = 1;
7406                 break;
7407         case I40E_TUNNEL_TYPE_GTPU:
7408                 if (!pf->gtp_replace_flag) {
7409                         i40e_replace_gtp_l1_filter(pf);
7410                         i40e_replace_gtp_cloud_filter(pf);
7411                         pf->gtp_replace_flag = 1;
7412                 }
7413                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7414                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7415                         (teid_le >> 16) & 0xFFFF;
7416                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7417                         teid_le & 0xFFFF;
7418                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7419                         0x0;
7420                 big_buffer = 1;
7421                 break;
7422         case I40E_TUNNEL_TYPE_QINQ:
7423                 if (!pf->qinq_replace_flag) {
7424                         ret = i40e_cloud_filter_qinq_create(pf);
7425                         if (ret < 0)
7426                                 PMD_DRV_LOG(DEBUG,
7427                                             "QinQ tunnel filter already created.");
7428                         pf->qinq_replace_flag = 1;
7429                 }
7430                 /*      Add in the General fields the values of
7431                  *      the Outer and Inner VLAN
7432                  *      Big Buffer should be set, see changes in
7433                  *      i40e_aq_add_cloud_filters
7434                  */
7435                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7436                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7437                 big_buffer = 1;
7438                 break;
7439         default:
7440                 /* Other tunnel types is not supported. */
7441                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7442                 rte_free(cld_filter);
7443                 return -EINVAL;
7444         }
7445
7446         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7447                 pfilter->element.flags =
7448                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7449         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7450                 pfilter->element.flags =
7451                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7452         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7453                 pfilter->element.flags =
7454                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7455         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7456                 pfilter->element.flags =
7457                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7458         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7459                 pfilter->element.flags |=
7460                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7461         else {
7462                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7463                                                 &pfilter->element.flags);
7464                 if (val < 0) {
7465                         rte_free(cld_filter);
7466                         return -EINVAL;
7467                 }
7468         }
7469
7470         pfilter->element.flags |= rte_cpu_to_le_16(
7471                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7472                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7473         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7474         pfilter->element.queue_number =
7475                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7476
7477         if (!tunnel_filter->is_to_vf)
7478                 vsi = pf->main_vsi;
7479         else {
7480                 if (tunnel_filter->vf_id >= pf->vf_num) {
7481                         PMD_DRV_LOG(ERR, "Invalid argument.");
7482                         return -EINVAL;
7483                 }
7484                 vf = &pf->vfs[tunnel_filter->vf_id];
7485                 vsi = vf->vsi;
7486         }
7487
7488         /* Check if there is the filter in SW list */
7489         memset(&check_filter, 0, sizeof(check_filter));
7490         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7491         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7492         check_filter.vf_id = tunnel_filter->vf_id;
7493         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7494         if (add && node) {
7495                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7496                 return -EINVAL;
7497         }
7498
7499         if (!add && !node) {
7500                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7501                 return -EINVAL;
7502         }
7503
7504         if (add) {
7505                 if (big_buffer)
7506                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7507                                                    vsi->seid, cld_filter, 1);
7508                 else
7509                         ret = i40e_aq_add_cloud_filters(hw,
7510                                         vsi->seid, &cld_filter->element, 1);
7511                 if (ret < 0) {
7512                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7513                         return -ENOTSUP;
7514                 }
7515                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7516                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7517                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7518         } else {
7519                 if (big_buffer)
7520                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7521                                 hw, vsi->seid, cld_filter, 1);
7522                 else
7523                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7524                                                    &cld_filter->element, 1);
7525                 if (ret < 0) {
7526                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7527                         return -ENOTSUP;
7528                 }
7529                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7530         }
7531
7532         rte_free(cld_filter);
7533         return ret;
7534 }
7535
7536 static int
7537 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7538 {
7539         uint8_t i;
7540
7541         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7542                 if (pf->vxlan_ports[i] == port)
7543                         return i;
7544         }
7545
7546         return -1;
7547 }
7548
7549 static int
7550 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7551 {
7552         int  idx, ret;
7553         uint8_t filter_idx;
7554         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7555
7556         idx = i40e_get_vxlan_port_idx(pf, port);
7557
7558         /* Check if port already exists */
7559         if (idx >= 0) {
7560                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7561                 return -EINVAL;
7562         }
7563
7564         /* Now check if there is space to add the new port */
7565         idx = i40e_get_vxlan_port_idx(pf, 0);
7566         if (idx < 0) {
7567                 PMD_DRV_LOG(ERR,
7568                         "Maximum number of UDP ports reached, not adding port %d",
7569                         port);
7570                 return -ENOSPC;
7571         }
7572
7573         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7574                                         &filter_idx, NULL);
7575         if (ret < 0) {
7576                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7577                 return -1;
7578         }
7579
7580         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7581                          port,  filter_idx);
7582
7583         /* New port: add it and mark its index in the bitmap */
7584         pf->vxlan_ports[idx] = port;
7585         pf->vxlan_bitmap |= (1 << idx);
7586
7587         if (!(pf->flags & I40E_FLAG_VXLAN))
7588                 pf->flags |= I40E_FLAG_VXLAN;
7589
7590         return 0;
7591 }
7592
7593 static int
7594 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7595 {
7596         int idx;
7597         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7598
7599         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7600                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7601                 return -EINVAL;
7602         }
7603
7604         idx = i40e_get_vxlan_port_idx(pf, port);
7605
7606         if (idx < 0) {
7607                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7608                 return -EINVAL;
7609         }
7610
7611         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7612                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7613                 return -1;
7614         }
7615
7616         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7617                         port, idx);
7618
7619         pf->vxlan_ports[idx] = 0;
7620         pf->vxlan_bitmap &= ~(1 << idx);
7621
7622         if (!pf->vxlan_bitmap)
7623                 pf->flags &= ~I40E_FLAG_VXLAN;
7624
7625         return 0;
7626 }
7627
7628 /* Add UDP tunneling port */
7629 static int
7630 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7631                              struct rte_eth_udp_tunnel *udp_tunnel)
7632 {
7633         int ret = 0;
7634         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7635
7636         if (udp_tunnel == NULL)
7637                 return -EINVAL;
7638
7639         switch (udp_tunnel->prot_type) {
7640         case RTE_TUNNEL_TYPE_VXLAN:
7641                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7642                 break;
7643
7644         case RTE_TUNNEL_TYPE_GENEVE:
7645         case RTE_TUNNEL_TYPE_TEREDO:
7646                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7647                 ret = -1;
7648                 break;
7649
7650         default:
7651                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7652                 ret = -1;
7653                 break;
7654         }
7655
7656         return ret;
7657 }
7658
7659 /* Remove UDP tunneling port */
7660 static int
7661 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7662                              struct rte_eth_udp_tunnel *udp_tunnel)
7663 {
7664         int ret = 0;
7665         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7666
7667         if (udp_tunnel == NULL)
7668                 return -EINVAL;
7669
7670         switch (udp_tunnel->prot_type) {
7671         case RTE_TUNNEL_TYPE_VXLAN:
7672                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7673                 break;
7674         case RTE_TUNNEL_TYPE_GENEVE:
7675         case RTE_TUNNEL_TYPE_TEREDO:
7676                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7677                 ret = -1;
7678                 break;
7679         default:
7680                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7681                 ret = -1;
7682                 break;
7683         }
7684
7685         return ret;
7686 }
7687
7688 /* Calculate the maximum number of contiguous PF queues that are configured */
7689 static int
7690 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7691 {
7692         struct rte_eth_dev_data *data = pf->dev_data;
7693         int i, num;
7694         struct i40e_rx_queue *rxq;
7695
7696         num = 0;
7697         for (i = 0; i < pf->lan_nb_qps; i++) {
7698                 rxq = data->rx_queues[i];
7699                 if (rxq && rxq->q_set)
7700                         num++;
7701                 else
7702                         break;
7703         }
7704
7705         return num;
7706 }
7707
7708 /* Configure RSS */
7709 static int
7710 i40e_pf_config_rss(struct i40e_pf *pf)
7711 {
7712         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7713         struct rte_eth_rss_conf rss_conf;
7714         uint32_t i, lut = 0;
7715         uint16_t j, num;
7716
7717         /*
7718          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7719          * It's necessary to calculate the actual PF queues that are configured.
7720          */
7721         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7722                 num = i40e_pf_calc_configured_queues_num(pf);
7723         else
7724                 num = pf->dev_data->nb_rx_queues;
7725
7726         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7727         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7728                         num);
7729
7730         if (num == 0) {
7731                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7732                 return -ENOTSUP;
7733         }
7734
7735         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7736                 if (j == num)
7737                         j = 0;
7738                 lut = (lut << 8) | (j & ((0x1 <<
7739                         hw->func_caps.rss_table_entry_width) - 1));
7740                 if ((i & 3) == 3)
7741                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7742         }
7743
7744         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7745         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7746                 i40e_pf_disable_rss(pf);
7747                 return 0;
7748         }
7749         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7750                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7751                 /* Random default keys */
7752                 static uint32_t rss_key_default[] = {0x6b793944,
7753                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7754                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7755                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7756
7757                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7758                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7759                                                         sizeof(uint32_t);
7760         }
7761
7762         return i40e_hw_rss_hash_set(pf, &rss_conf);
7763 }
7764
7765 static int
7766 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7767                                struct rte_eth_tunnel_filter_conf *filter)
7768 {
7769         if (pf == NULL || filter == NULL) {
7770                 PMD_DRV_LOG(ERR, "Invalid parameter");
7771                 return -EINVAL;
7772         }
7773
7774         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7775                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7776                 return -EINVAL;
7777         }
7778
7779         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7780                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7781                 return -EINVAL;
7782         }
7783
7784         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7785                 (is_zero_ether_addr(&filter->outer_mac))) {
7786                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7787                 return -EINVAL;
7788         }
7789
7790         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7791                 (is_zero_ether_addr(&filter->inner_mac))) {
7792                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7793                 return -EINVAL;
7794         }
7795
7796         return 0;
7797 }
7798
7799 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7800 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7801 static int
7802 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7803 {
7804         uint32_t val, reg;
7805         int ret = -EINVAL;
7806
7807         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7808         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7809
7810         if (len == 3) {
7811                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7812         } else if (len == 4) {
7813                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7814         } else {
7815                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7816                 return ret;
7817         }
7818
7819         if (reg != val) {
7820                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7821                                                    reg, NULL);
7822                 if (ret != 0)
7823                         return ret;
7824         } else {
7825                 ret = 0;
7826         }
7827         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7828                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7829
7830         return ret;
7831 }
7832
7833 static int
7834 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7835 {
7836         int ret = -EINVAL;
7837
7838         if (!hw || !cfg)
7839                 return -EINVAL;
7840
7841         switch (cfg->cfg_type) {
7842         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7843                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7844                 break;
7845         default:
7846                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7847                 break;
7848         }
7849
7850         return ret;
7851 }
7852
7853 static int
7854 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7855                                enum rte_filter_op filter_op,
7856                                void *arg)
7857 {
7858         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7859         int ret = I40E_ERR_PARAM;
7860
7861         switch (filter_op) {
7862         case RTE_ETH_FILTER_SET:
7863                 ret = i40e_dev_global_config_set(hw,
7864                         (struct rte_eth_global_cfg *)arg);
7865                 break;
7866         default:
7867                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7868                 break;
7869         }
7870
7871         return ret;
7872 }
7873
7874 static int
7875 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7876                           enum rte_filter_op filter_op,
7877                           void *arg)
7878 {
7879         struct rte_eth_tunnel_filter_conf *filter;
7880         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7881         int ret = I40E_SUCCESS;
7882
7883         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7884
7885         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7886                 return I40E_ERR_PARAM;
7887
7888         switch (filter_op) {
7889         case RTE_ETH_FILTER_NOP:
7890                 if (!(pf->flags & I40E_FLAG_VXLAN))
7891                         ret = I40E_NOT_SUPPORTED;
7892                 break;
7893         case RTE_ETH_FILTER_ADD:
7894                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7895                 break;
7896         case RTE_ETH_FILTER_DELETE:
7897                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7898                 break;
7899         default:
7900                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7901                 ret = I40E_ERR_PARAM;
7902                 break;
7903         }
7904
7905         return ret;
7906 }
7907
7908 static int
7909 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7910 {
7911         int ret = 0;
7912         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7913
7914         /* RSS setup */
7915         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7916                 ret = i40e_pf_config_rss(pf);
7917         else
7918                 i40e_pf_disable_rss(pf);
7919
7920         return ret;
7921 }
7922
7923 /* Get the symmetric hash enable configurations per port */
7924 static void
7925 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7926 {
7927         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7928
7929         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7930 }
7931
7932 /* Set the symmetric hash enable configurations per port */
7933 static void
7934 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7935 {
7936         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7937
7938         if (enable > 0) {
7939                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7940                         PMD_DRV_LOG(INFO,
7941                                 "Symmetric hash has already been enabled");
7942                         return;
7943                 }
7944                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7945         } else {
7946                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7947                         PMD_DRV_LOG(INFO,
7948                                 "Symmetric hash has already been disabled");
7949                         return;
7950                 }
7951                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7952         }
7953         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7954         I40E_WRITE_FLUSH(hw);
7955 }
7956
7957 /*
7958  * Get global configurations of hash function type and symmetric hash enable
7959  * per flow type (pctype). Note that global configuration means it affects all
7960  * the ports on the same NIC.
7961  */
7962 static int
7963 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7964                                    struct rte_eth_hash_global_conf *g_cfg)
7965 {
7966         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
7967         uint32_t reg;
7968         uint16_t i, j;
7969
7970         memset(g_cfg, 0, sizeof(*g_cfg));
7971         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7972         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7973                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7974         else
7975                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7976         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7977                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7978
7979         /*
7980          * We work only with lowest 32 bits which is not correct, but to work
7981          * properly the valid_bit_mask size should be increased up to 64 bits
7982          * and this will brake ABI. This modification will be done in next
7983          * release
7984          */
7985         g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
7986
7987         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
7988                 if (!adapter->pctypes_tbl[i])
7989                         continue;
7990                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
7991                      j < I40E_FILTER_PCTYPE_MAX; j++) {
7992                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
7993                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
7994                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
7995                                         g_cfg->sym_hash_enable_mask[0] |=
7996                                                                 (1UL << i);
7997                                 }
7998                         }
7999                 }
8000         }
8001
8002         return 0;
8003 }
8004
8005 static int
8006 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8007                               const struct rte_eth_hash_global_conf *g_cfg)
8008 {
8009         uint32_t i;
8010         uint32_t mask0, i40e_mask = adapter->flow_types_mask;
8011
8012         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8013                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8014                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8015                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8016                                                 g_cfg->hash_func);
8017                 return -EINVAL;
8018         }
8019
8020         /*
8021          * As i40e supports less than 32 flow types, only first 32 bits need to
8022          * be checked.
8023          */
8024         mask0 = g_cfg->valid_bit_mask[0];
8025         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8026                 if (i == 0) {
8027                         /* Check if any unsupported flow type configured */
8028                         if ((mask0 | i40e_mask) ^ i40e_mask)
8029                                 goto mask_err;
8030                 } else {
8031                         if (g_cfg->valid_bit_mask[i])
8032                                 goto mask_err;
8033                 }
8034         }
8035
8036         return 0;
8037
8038 mask_err:
8039         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8040
8041         return -EINVAL;
8042 }
8043
8044 /*
8045  * Set global configurations of hash function type and symmetric hash enable
8046  * per flow type (pctype). Note any modifying global configuration will affect
8047  * all the ports on the same NIC.
8048  */
8049 static int
8050 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8051                                    struct rte_eth_hash_global_conf *g_cfg)
8052 {
8053         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8054         int ret;
8055         uint16_t i, j;
8056         uint32_t reg;
8057         /*
8058          * We work only with lowest 32 bits which is not correct, but to work
8059          * properly the valid_bit_mask size should be increased up to 64 bits
8060          * and this will brake ABI. This modification will be done in next
8061          * release
8062          */
8063         uint32_t mask0 = g_cfg->valid_bit_mask[0] &
8064                                         (uint32_t)adapter->flow_types_mask;
8065
8066         /* Check the input parameters */
8067         ret = i40e_hash_global_config_check(adapter, g_cfg);
8068         if (ret < 0)
8069                 return ret;
8070
8071         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
8072                 if (mask0 & (1UL << i)) {
8073                         reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
8074                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8075
8076                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8077                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8078                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8079                                         i40e_write_rx_ctl(hw,
8080                                                           I40E_GLQF_HSYM(j),
8081                                                           reg);
8082                         }
8083                 }
8084         }
8085
8086         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8087         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8088                 /* Toeplitz */
8089                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8090                         PMD_DRV_LOG(DEBUG,
8091                                 "Hash function already set to Toeplitz");
8092                         goto out;
8093                 }
8094                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8095         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8096                 /* Simple XOR */
8097                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8098                         PMD_DRV_LOG(DEBUG,
8099                                 "Hash function already set to Simple XOR");
8100                         goto out;
8101                 }
8102                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8103         } else
8104                 /* Use the default, and keep it as it is */
8105                 goto out;
8106
8107         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8108
8109 out:
8110         I40E_WRITE_FLUSH(hw);
8111
8112         return 0;
8113 }
8114
8115 /**
8116  * Valid input sets for hash and flow director filters per PCTYPE
8117  */
8118 static uint64_t
8119 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8120                 enum rte_filter_type filter)
8121 {
8122         uint64_t valid;
8123
8124         static const uint64_t valid_hash_inset_table[] = {
8125                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8126                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8127                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8128                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8129                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8130                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8131                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8132                         I40E_INSET_FLEX_PAYLOAD,
8133                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8134                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8135                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8136                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8137                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8138                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8139                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8140                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8141                         I40E_INSET_FLEX_PAYLOAD,
8142                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8143                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8144                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8145                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8146                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8147                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8148                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8149                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8150                         I40E_INSET_FLEX_PAYLOAD,
8151                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8152                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8153                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8154                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8155                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8156                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8157                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8158                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8159                         I40E_INSET_FLEX_PAYLOAD,
8160                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8161                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8162                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8163                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8164                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8165                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8166                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8167                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8168                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8169                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8170                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8171                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8172                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8173                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8174                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8175                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8176                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8177                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8178                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8179                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8180                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8181                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8182                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8183                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8184                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8185                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8186                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8187                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8188                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8189                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8190                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8191                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8192                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8193                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8194                         I40E_INSET_FLEX_PAYLOAD,
8195                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8196                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8197                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8198                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8199                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8200                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8201                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8202                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8203                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8204                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8205                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8206                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8207                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8208                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8209                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8210                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8211                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8212                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8213                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8214                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8215                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8216                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8217                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8218                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8219                         I40E_INSET_FLEX_PAYLOAD,
8220                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8221                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8222                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8223                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8224                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8225                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8226                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8227                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8228                         I40E_INSET_FLEX_PAYLOAD,
8229                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8230                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8231                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8232                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8233                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8234                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8235                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8236                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8237                         I40E_INSET_FLEX_PAYLOAD,
8238                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8239                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8240                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8241                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8242                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8243                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8244                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8245                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8246                         I40E_INSET_FLEX_PAYLOAD,
8247                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8248                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8249                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8250                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8251                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8252                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8253                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8254                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8255                         I40E_INSET_FLEX_PAYLOAD,
8256                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8257                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8258                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8259                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8260                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8261                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8262                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8263                         I40E_INSET_FLEX_PAYLOAD,
8264                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8265                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8266                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8267                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8268                         I40E_INSET_FLEX_PAYLOAD,
8269         };
8270
8271         /**
8272          * Flow director supports only fields defined in
8273          * union rte_eth_fdir_flow.
8274          */
8275         static const uint64_t valid_fdir_inset_table[] = {
8276                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8277                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8278                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8279                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8280                 I40E_INSET_IPV4_TTL,
8281                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8282                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8283                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8284                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8285                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8286                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8287                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8288                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8289                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8290                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8291                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8292                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8293                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8294                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8295                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8296                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8297                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8298                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8299                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8300                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8301                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8302                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8303                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8304                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8305                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8306                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8307                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8308                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8309                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8310                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8311                 I40E_INSET_SCTP_VT,
8312                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8313                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8314                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8315                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8316                 I40E_INSET_IPV4_TTL,
8317                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8318                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8319                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8320                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8321                 I40E_INSET_IPV6_HOP_LIMIT,
8322                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8323                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8324                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8325                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8326                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8327                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8328                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8329                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8330                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8331                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8332                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8333                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8334                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8335                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8336                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8337                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8338                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8339                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8340                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8341                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8342                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8343                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8344                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8345                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8346                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8347                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8348                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8349                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8350                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8351                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8352                 I40E_INSET_SCTP_VT,
8353                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8354                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8355                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8356                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8357                 I40E_INSET_IPV6_HOP_LIMIT,
8358                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8359                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8360                 I40E_INSET_LAST_ETHER_TYPE,
8361         };
8362
8363         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8364                 return 0;
8365         if (filter == RTE_ETH_FILTER_HASH)
8366                 valid = valid_hash_inset_table[pctype];
8367         else
8368                 valid = valid_fdir_inset_table[pctype];
8369
8370         return valid;
8371 }
8372
8373 /**
8374  * Validate if the input set is allowed for a specific PCTYPE
8375  */
8376 int
8377 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8378                 enum rte_filter_type filter, uint64_t inset)
8379 {
8380         uint64_t valid;
8381
8382         valid = i40e_get_valid_input_set(pctype, filter);
8383         if (inset & (~valid))
8384                 return -EINVAL;
8385
8386         return 0;
8387 }
8388
8389 /* default input set fields combination per pctype */
8390 uint64_t
8391 i40e_get_default_input_set(uint16_t pctype)
8392 {
8393         static const uint64_t default_inset_table[] = {
8394                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8395                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8396                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8397                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8398                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8399                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8400                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8401                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8402                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8403                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8404                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8405                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8406                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8407                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8408                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8409                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8410                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8411                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8412                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8413                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8414                         I40E_INSET_SCTP_VT,
8415                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8416                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8417                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8418                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8419                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8420                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8421                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8422                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8423                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8424                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8425                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8426                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8427                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8428                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8429                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8430                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8431                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8432                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8433                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8434                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8435                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8436                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8437                         I40E_INSET_SCTP_VT,
8438                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8439                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8440                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8441                         I40E_INSET_LAST_ETHER_TYPE,
8442         };
8443
8444         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8445                 return 0;
8446
8447         return default_inset_table[pctype];
8448 }
8449
8450 /**
8451  * Parse the input set from index to logical bit masks
8452  */
8453 static int
8454 i40e_parse_input_set(uint64_t *inset,
8455                      enum i40e_filter_pctype pctype,
8456                      enum rte_eth_input_set_field *field,
8457                      uint16_t size)
8458 {
8459         uint16_t i, j;
8460         int ret = -EINVAL;
8461
8462         static const struct {
8463                 enum rte_eth_input_set_field field;
8464                 uint64_t inset;
8465         } inset_convert_table[] = {
8466                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8467                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8468                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8469                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8470                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8471                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8472                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8473                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8474                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8475                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8476                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8477                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8478                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8479                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8480                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8481                         I40E_INSET_IPV6_NEXT_HDR},
8482                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8483                         I40E_INSET_IPV6_HOP_LIMIT},
8484                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8485                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8486                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8487                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8488                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8489                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8490                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8491                         I40E_INSET_SCTP_VT},
8492                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8493                         I40E_INSET_TUNNEL_DMAC},
8494                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8495                         I40E_INSET_VLAN_TUNNEL},
8496                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8497                         I40E_INSET_TUNNEL_ID},
8498                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8499                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8500                         I40E_INSET_FLEX_PAYLOAD_W1},
8501                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8502                         I40E_INSET_FLEX_PAYLOAD_W2},
8503                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8504                         I40E_INSET_FLEX_PAYLOAD_W3},
8505                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8506                         I40E_INSET_FLEX_PAYLOAD_W4},
8507                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8508                         I40E_INSET_FLEX_PAYLOAD_W5},
8509                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8510                         I40E_INSET_FLEX_PAYLOAD_W6},
8511                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8512                         I40E_INSET_FLEX_PAYLOAD_W7},
8513                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8514                         I40E_INSET_FLEX_PAYLOAD_W8},
8515         };
8516
8517         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8518                 return ret;
8519
8520         /* Only one item allowed for default or all */
8521         if (size == 1) {
8522                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8523                         *inset = i40e_get_default_input_set(pctype);
8524                         return 0;
8525                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8526                         *inset = I40E_INSET_NONE;
8527                         return 0;
8528                 }
8529         }
8530
8531         for (i = 0, *inset = 0; i < size; i++) {
8532                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8533                         if (field[i] == inset_convert_table[j].field) {
8534                                 *inset |= inset_convert_table[j].inset;
8535                                 break;
8536                         }
8537                 }
8538
8539                 /* It contains unsupported input set, return immediately */
8540                 if (j == RTE_DIM(inset_convert_table))
8541                         return ret;
8542         }
8543
8544         return 0;
8545 }
8546
8547 /**
8548  * Translate the input set from bit masks to register aware bit masks
8549  * and vice versa
8550  */
8551 uint64_t
8552 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8553 {
8554         uint64_t val = 0;
8555         uint16_t i;
8556
8557         struct inset_map {
8558                 uint64_t inset;
8559                 uint64_t inset_reg;
8560         };
8561
8562         static const struct inset_map inset_map_common[] = {
8563                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8564                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8565                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8566                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8567                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8568                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8569                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8570                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8571                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8572                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8573                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8574                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8575                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8576                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8577                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8578                 {I40E_INSET_TUNNEL_DMAC,
8579                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8580                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8581                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8582                 {I40E_INSET_TUNNEL_SRC_PORT,
8583                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8584                 {I40E_INSET_TUNNEL_DST_PORT,
8585                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8586                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8587                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8588                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8589                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8590                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8591                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8592                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8593                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8594                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8595         };
8596
8597     /* some different registers map in x722*/
8598         static const struct inset_map inset_map_diff_x722[] = {
8599                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8600                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8601                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8602                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8603         };
8604
8605         static const struct inset_map inset_map_diff_not_x722[] = {
8606                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8607                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8608                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8609                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8610         };
8611
8612         if (input == 0)
8613                 return val;
8614
8615         /* Translate input set to register aware inset */
8616         if (type == I40E_MAC_X722) {
8617                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8618                         if (input & inset_map_diff_x722[i].inset)
8619                                 val |= inset_map_diff_x722[i].inset_reg;
8620                 }
8621         } else {
8622                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8623                         if (input & inset_map_diff_not_x722[i].inset)
8624                                 val |= inset_map_diff_not_x722[i].inset_reg;
8625                 }
8626         }
8627
8628         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8629                 if (input & inset_map_common[i].inset)
8630                         val |= inset_map_common[i].inset_reg;
8631         }
8632
8633         return val;
8634 }
8635
8636 int
8637 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8638 {
8639         uint8_t i, idx = 0;
8640         uint64_t inset_need_mask = inset;
8641
8642         static const struct {
8643                 uint64_t inset;
8644                 uint32_t mask;
8645         } inset_mask_map[] = {
8646                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8647                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8648                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8649                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8650                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8651                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8652                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8653                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8654         };
8655
8656         if (!inset || !mask || !nb_elem)
8657                 return 0;
8658
8659         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8660                 /* Clear the inset bit, if no MASK is required,
8661                  * for example proto + ttl
8662                  */
8663                 if ((inset & inset_mask_map[i].inset) ==
8664                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8665                         inset_need_mask &= ~inset_mask_map[i].inset;
8666                 if (!inset_need_mask)
8667                         return 0;
8668         }
8669         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8670                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8671                     inset_mask_map[i].inset) {
8672                         if (idx >= nb_elem) {
8673                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8674                                 return -EINVAL;
8675                         }
8676                         mask[idx] = inset_mask_map[i].mask;
8677                         idx++;
8678                 }
8679         }
8680
8681         return idx;
8682 }
8683
8684 void
8685 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8686 {
8687         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8688
8689         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8690         if (reg != val)
8691                 i40e_write_rx_ctl(hw, addr, val);
8692         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8693                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8694 }
8695
8696 static void
8697 i40e_filter_input_set_init(struct i40e_pf *pf)
8698 {
8699         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8700         enum i40e_filter_pctype pctype;
8701         uint64_t input_set, inset_reg;
8702         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8703         int num, i;
8704         uint16_t flow_type;
8705
8706         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8707              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8708                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8709
8710                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8711                         continue;
8712
8713                 input_set = i40e_get_default_input_set(pctype);
8714
8715                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8716                                                    I40E_INSET_MASK_NUM_REG);
8717                 if (num < 0)
8718                         return;
8719                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8720                                         input_set);
8721
8722                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8723                                       (uint32_t)(inset_reg & UINT32_MAX));
8724                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8725                                      (uint32_t)((inset_reg >>
8726                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8727                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8728                                       (uint32_t)(inset_reg & UINT32_MAX));
8729                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8730                                      (uint32_t)((inset_reg >>
8731                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8732
8733                 for (i = 0; i < num; i++) {
8734                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8735                                              mask_reg[i]);
8736                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8737                                              mask_reg[i]);
8738                 }
8739                 /*clear unused mask registers of the pctype */
8740                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8741                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8742                                              0);
8743                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8744                                              0);
8745                 }
8746                 I40E_WRITE_FLUSH(hw);
8747
8748                 /* store the default input set */
8749                 pf->hash_input_set[pctype] = input_set;
8750                 pf->fdir.input_set[pctype] = input_set;
8751         }
8752 }
8753
8754 int
8755 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8756                          struct rte_eth_input_set_conf *conf)
8757 {
8758         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8759         enum i40e_filter_pctype pctype;
8760         uint64_t input_set, inset_reg = 0;
8761         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8762         int ret, i, num;
8763
8764         if (!conf) {
8765                 PMD_DRV_LOG(ERR, "Invalid pointer");
8766                 return -EFAULT;
8767         }
8768         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8769             conf->op != RTE_ETH_INPUT_SET_ADD) {
8770                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8771                 return -EINVAL;
8772         }
8773
8774         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8775         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8776                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8777                 return -EINVAL;
8778         }
8779
8780         if (hw->mac.type == I40E_MAC_X722) {
8781                 /* get translated pctype value in fd pctype register */
8782                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8783                         I40E_GLQF_FD_PCTYPES((int)pctype));
8784         }
8785
8786         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8787                                    conf->inset_size);
8788         if (ret) {
8789                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8790                 return -EINVAL;
8791         }
8792
8793         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8794                 /* get inset value in register */
8795                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8796                 inset_reg <<= I40E_32_BIT_WIDTH;
8797                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8798                 input_set |= pf->hash_input_set[pctype];
8799         }
8800         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8801                                            I40E_INSET_MASK_NUM_REG);
8802         if (num < 0)
8803                 return -EINVAL;
8804
8805         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8806
8807         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8808                               (uint32_t)(inset_reg & UINT32_MAX));
8809         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8810                              (uint32_t)((inset_reg >>
8811                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8812
8813         for (i = 0; i < num; i++)
8814                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8815                                      mask_reg[i]);
8816         /*clear unused mask registers of the pctype */
8817         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8818                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8819                                      0);
8820         I40E_WRITE_FLUSH(hw);
8821
8822         pf->hash_input_set[pctype] = input_set;
8823         return 0;
8824 }
8825
8826 int
8827 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8828                          struct rte_eth_input_set_conf *conf)
8829 {
8830         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8831         enum i40e_filter_pctype pctype;
8832         uint64_t input_set, inset_reg = 0;
8833         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8834         int ret, i, num;
8835
8836         if (!hw || !conf) {
8837                 PMD_DRV_LOG(ERR, "Invalid pointer");
8838                 return -EFAULT;
8839         }
8840         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8841             conf->op != RTE_ETH_INPUT_SET_ADD) {
8842                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8843                 return -EINVAL;
8844         }
8845
8846         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8847
8848         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8849                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8850                 return -EINVAL;
8851         }
8852
8853         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8854                                    conf->inset_size);
8855         if (ret) {
8856                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8857                 return -EINVAL;
8858         }
8859
8860         /* get inset value in register */
8861         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8862         inset_reg <<= I40E_32_BIT_WIDTH;
8863         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8864
8865         /* Can not change the inset reg for flex payload for fdir,
8866          * it is done by writing I40E_PRTQF_FD_FLXINSET
8867          * in i40e_set_flex_mask_on_pctype.
8868          */
8869         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8870                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8871         else
8872                 input_set |= pf->fdir.input_set[pctype];
8873         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8874                                            I40E_INSET_MASK_NUM_REG);
8875         if (num < 0)
8876                 return -EINVAL;
8877
8878         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8879
8880         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8881                               (uint32_t)(inset_reg & UINT32_MAX));
8882         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8883                              (uint32_t)((inset_reg >>
8884                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8885
8886         for (i = 0; i < num; i++)
8887                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8888                                      mask_reg[i]);
8889         /*clear unused mask registers of the pctype */
8890         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8891                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8892                                      0);
8893         I40E_WRITE_FLUSH(hw);
8894
8895         pf->fdir.input_set[pctype] = input_set;
8896         return 0;
8897 }
8898
8899 static int
8900 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8901 {
8902         int ret = 0;
8903
8904         if (!hw || !info) {
8905                 PMD_DRV_LOG(ERR, "Invalid pointer");
8906                 return -EFAULT;
8907         }
8908
8909         switch (info->info_type) {
8910         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8911                 i40e_get_symmetric_hash_enable_per_port(hw,
8912                                         &(info->info.enable));
8913                 break;
8914         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8915                 ret = i40e_get_hash_filter_global_config(hw,
8916                                 &(info->info.global_conf));
8917                 break;
8918         default:
8919                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8920                                                         info->info_type);
8921                 ret = -EINVAL;
8922                 break;
8923         }
8924
8925         return ret;
8926 }
8927
8928 static int
8929 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8930 {
8931         int ret = 0;
8932
8933         if (!hw || !info) {
8934                 PMD_DRV_LOG(ERR, "Invalid pointer");
8935                 return -EFAULT;
8936         }
8937
8938         switch (info->info_type) {
8939         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8940                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8941                 break;
8942         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8943                 ret = i40e_set_hash_filter_global_config(hw,
8944                                 &(info->info.global_conf));
8945                 break;
8946         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8947                 ret = i40e_hash_filter_inset_select(hw,
8948                                                &(info->info.input_set_conf));
8949                 break;
8950
8951         default:
8952                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8953                                                         info->info_type);
8954                 ret = -EINVAL;
8955                 break;
8956         }
8957
8958         return ret;
8959 }
8960
8961 /* Operations for hash function */
8962 static int
8963 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8964                       enum rte_filter_op filter_op,
8965                       void *arg)
8966 {
8967         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8968         int ret = 0;
8969
8970         switch (filter_op) {
8971         case RTE_ETH_FILTER_NOP:
8972                 break;
8973         case RTE_ETH_FILTER_GET:
8974                 ret = i40e_hash_filter_get(hw,
8975                         (struct rte_eth_hash_filter_info *)arg);
8976                 break;
8977         case RTE_ETH_FILTER_SET:
8978                 ret = i40e_hash_filter_set(hw,
8979                         (struct rte_eth_hash_filter_info *)arg);
8980                 break;
8981         default:
8982                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8983                                                                 filter_op);
8984                 ret = -ENOTSUP;
8985                 break;
8986         }
8987
8988         return ret;
8989 }
8990
8991 /* Convert ethertype filter structure */
8992 static int
8993 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8994                               struct i40e_ethertype_filter *filter)
8995 {
8996         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8997         filter->input.ether_type = input->ether_type;
8998         filter->flags = input->flags;
8999         filter->queue = input->queue;
9000
9001         return 0;
9002 }
9003
9004 /* Check if there exists the ehtertype filter */
9005 struct i40e_ethertype_filter *
9006 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9007                                 const struct i40e_ethertype_filter_input *input)
9008 {
9009         int ret;
9010
9011         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9012         if (ret < 0)
9013                 return NULL;
9014
9015         return ethertype_rule->hash_map[ret];
9016 }
9017
9018 /* Add ethertype filter in SW list */
9019 static int
9020 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9021                                 struct i40e_ethertype_filter *filter)
9022 {
9023         struct i40e_ethertype_rule *rule = &pf->ethertype;
9024         int ret;
9025
9026         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9027         if (ret < 0) {
9028                 PMD_DRV_LOG(ERR,
9029                             "Failed to insert ethertype filter"
9030                             " to hash table %d!",
9031                             ret);
9032                 return ret;
9033         }
9034         rule->hash_map[ret] = filter;
9035
9036         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9037
9038         return 0;
9039 }
9040
9041 /* Delete ethertype filter in SW list */
9042 int
9043 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9044                              struct i40e_ethertype_filter_input *input)
9045 {
9046         struct i40e_ethertype_rule *rule = &pf->ethertype;
9047         struct i40e_ethertype_filter *filter;
9048         int ret;
9049
9050         ret = rte_hash_del_key(rule->hash_table, input);
9051         if (ret < 0) {
9052                 PMD_DRV_LOG(ERR,
9053                             "Failed to delete ethertype filter"
9054                             " to hash table %d!",
9055                             ret);
9056                 return ret;
9057         }
9058         filter = rule->hash_map[ret];
9059         rule->hash_map[ret] = NULL;
9060
9061         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9062         rte_free(filter);
9063
9064         return 0;
9065 }
9066
9067 /*
9068  * Configure ethertype filter, which can director packet by filtering
9069  * with mac address and ether_type or only ether_type
9070  */
9071 int
9072 i40e_ethertype_filter_set(struct i40e_pf *pf,
9073                         struct rte_eth_ethertype_filter *filter,
9074                         bool add)
9075 {
9076         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9077         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9078         struct i40e_ethertype_filter *ethertype_filter, *node;
9079         struct i40e_ethertype_filter check_filter;
9080         struct i40e_control_filter_stats stats;
9081         uint16_t flags = 0;
9082         int ret;
9083
9084         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9085                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9086                 return -EINVAL;
9087         }
9088         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9089                 filter->ether_type == ETHER_TYPE_IPv6) {
9090                 PMD_DRV_LOG(ERR,
9091                         "unsupported ether_type(0x%04x) in control packet filter.",
9092                         filter->ether_type);
9093                 return -EINVAL;
9094         }
9095         if (filter->ether_type == ETHER_TYPE_VLAN)
9096                 PMD_DRV_LOG(WARNING,
9097                         "filter vlan ether_type in first tag is not supported.");
9098
9099         /* Check if there is the filter in SW list */
9100         memset(&check_filter, 0, sizeof(check_filter));
9101         i40e_ethertype_filter_convert(filter, &check_filter);
9102         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9103                                                &check_filter.input);
9104         if (add && node) {
9105                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9106                 return -EINVAL;
9107         }
9108
9109         if (!add && !node) {
9110                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9111                 return -EINVAL;
9112         }
9113
9114         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9115                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9116         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9117                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9118         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9119
9120         memset(&stats, 0, sizeof(stats));
9121         ret = i40e_aq_add_rem_control_packet_filter(hw,
9122                         filter->mac_addr.addr_bytes,
9123                         filter->ether_type, flags,
9124                         pf->main_vsi->seid,
9125                         filter->queue, add, &stats, NULL);
9126
9127         PMD_DRV_LOG(INFO,
9128                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9129                 ret, stats.mac_etype_used, stats.etype_used,
9130                 stats.mac_etype_free, stats.etype_free);
9131         if (ret < 0)
9132                 return -ENOSYS;
9133
9134         /* Add or delete a filter in SW list */
9135         if (add) {
9136                 ethertype_filter = rte_zmalloc("ethertype_filter",
9137                                        sizeof(*ethertype_filter), 0);
9138                 rte_memcpy(ethertype_filter, &check_filter,
9139                            sizeof(check_filter));
9140                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9141         } else {
9142                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9143         }
9144
9145         return ret;
9146 }
9147
9148 /*
9149  * Handle operations for ethertype filter.
9150  */
9151 static int
9152 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9153                                 enum rte_filter_op filter_op,
9154                                 void *arg)
9155 {
9156         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9157         int ret = 0;
9158
9159         if (filter_op == RTE_ETH_FILTER_NOP)
9160                 return ret;
9161
9162         if (arg == NULL) {
9163                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9164                             filter_op);
9165                 return -EINVAL;
9166         }
9167
9168         switch (filter_op) {
9169         case RTE_ETH_FILTER_ADD:
9170                 ret = i40e_ethertype_filter_set(pf,
9171                         (struct rte_eth_ethertype_filter *)arg,
9172                         TRUE);
9173                 break;
9174         case RTE_ETH_FILTER_DELETE:
9175                 ret = i40e_ethertype_filter_set(pf,
9176                         (struct rte_eth_ethertype_filter *)arg,
9177                         FALSE);
9178                 break;
9179         default:
9180                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9181                 ret = -ENOSYS;
9182                 break;
9183         }
9184         return ret;
9185 }
9186
9187 static int
9188 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9189                      enum rte_filter_type filter_type,
9190                      enum rte_filter_op filter_op,
9191                      void *arg)
9192 {
9193         int ret = 0;
9194
9195         if (dev == NULL)
9196                 return -EINVAL;
9197
9198         switch (filter_type) {
9199         case RTE_ETH_FILTER_NONE:
9200                 /* For global configuration */
9201                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9202                 break;
9203         case RTE_ETH_FILTER_HASH:
9204                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9205                 break;
9206         case RTE_ETH_FILTER_MACVLAN:
9207                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9208                 break;
9209         case RTE_ETH_FILTER_ETHERTYPE:
9210                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9211                 break;
9212         case RTE_ETH_FILTER_TUNNEL:
9213                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9214                 break;
9215         case RTE_ETH_FILTER_FDIR:
9216                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9217                 break;
9218         case RTE_ETH_FILTER_GENERIC:
9219                 if (filter_op != RTE_ETH_FILTER_GET)
9220                         return -EINVAL;
9221                 *(const void **)arg = &i40e_flow_ops;
9222                 break;
9223         default:
9224                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9225                                                         filter_type);
9226                 ret = -EINVAL;
9227                 break;
9228         }
9229
9230         return ret;
9231 }
9232
9233 /*
9234  * Check and enable Extended Tag.
9235  * Enabling Extended Tag is important for 40G performance.
9236  */
9237 static void
9238 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9239 {
9240         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9241         uint32_t buf = 0;
9242         int ret;
9243
9244         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9245                                       PCI_DEV_CAP_REG);
9246         if (ret < 0) {
9247                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9248                             PCI_DEV_CAP_REG);
9249                 return;
9250         }
9251         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9252                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9253                 return;
9254         }
9255
9256         buf = 0;
9257         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9258                                       PCI_DEV_CTRL_REG);
9259         if (ret < 0) {
9260                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9261                             PCI_DEV_CTRL_REG);
9262                 return;
9263         }
9264         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9265                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9266                 return;
9267         }
9268         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9269         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9270                                        PCI_DEV_CTRL_REG);
9271         if (ret < 0) {
9272                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9273                             PCI_DEV_CTRL_REG);
9274                 return;
9275         }
9276 }
9277
9278 /*
9279  * As some registers wouldn't be reset unless a global hardware reset,
9280  * hardware initialization is needed to put those registers into an
9281  * expected initial state.
9282  */
9283 static void
9284 i40e_hw_init(struct rte_eth_dev *dev)
9285 {
9286         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9287
9288         i40e_enable_extended_tag(dev);
9289
9290         /* clear the PF Queue Filter control register */
9291         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9292
9293         /* Disable symmetric hash per port */
9294         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9295 }
9296
9297 /*
9298  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9299  * however this function will return only one highest pctype index,
9300  * which is not quite correct. This is known problem of i40e driver
9301  * and needs to be fixed later.
9302  */
9303 enum i40e_filter_pctype
9304 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9305 {
9306         int i;
9307         uint64_t pctype_mask;
9308
9309         if (flow_type < I40E_FLOW_TYPE_MAX) {
9310                 pctype_mask = adapter->pctypes_tbl[flow_type];
9311                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9312                         if (pctype_mask & (1ULL << i))
9313                                 return (enum i40e_filter_pctype)i;
9314                 }
9315         }
9316         return I40E_FILTER_PCTYPE_INVALID;
9317 }
9318
9319 uint16_t
9320 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9321                         enum i40e_filter_pctype pctype)
9322 {
9323         uint16_t flowtype;
9324         uint64_t pctype_mask = 1ULL << pctype;
9325
9326         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9327              flowtype++) {
9328                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9329                         return flowtype;
9330         }
9331
9332         return RTE_ETH_FLOW_UNKNOWN;
9333 }
9334
9335 /*
9336  * On X710, performance number is far from the expectation on recent firmware
9337  * versions; on XL710, performance number is also far from the expectation on
9338  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9339  * mode is enabled and port MAC address is equal to the packet destination MAC
9340  * address. The fix for this issue may not be integrated in the following
9341  * firmware version. So the workaround in software driver is needed. It needs
9342  * to modify the initial values of 3 internal only registers for both X710 and
9343  * XL710. Note that the values for X710 or XL710 could be different, and the
9344  * workaround can be removed when it is fixed in firmware in the future.
9345  */
9346
9347 /* For both X710 and XL710 */
9348 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9349 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x20000200
9350 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9351
9352 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9353 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9354
9355 /* For X722 */
9356 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9357 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9358
9359 /* For X710 */
9360 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9361 /* For XL710 */
9362 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9363 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9364
9365 static int
9366 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9367 {
9368         enum i40e_status_code status;
9369         struct i40e_aq_get_phy_abilities_resp phy_ab;
9370         int ret = -ENOTSUP;
9371         int retries = 0;
9372
9373         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9374                                               NULL);
9375
9376         while (status) {
9377                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9378                         status);
9379                 retries++;
9380                 rte_delay_us(100000);
9381                 if  (retries < 5)
9382                         status = i40e_aq_get_phy_capabilities(hw, false,
9383                                         true, &phy_ab, NULL);
9384                 else
9385                         return ret;
9386         }
9387         return 0;
9388 }
9389
9390 static void
9391 i40e_configure_registers(struct i40e_hw *hw)
9392 {
9393         static struct {
9394                 uint32_t addr;
9395                 uint64_t val;
9396         } reg_table[] = {
9397                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9398                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9399                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9400         };
9401         uint64_t reg;
9402         uint32_t i;
9403         int ret;
9404
9405         for (i = 0; i < RTE_DIM(reg_table); i++) {
9406                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9407                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9408                                 reg_table[i].val =
9409                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9410                         else /* For X710/XL710/XXV710 */
9411                                 if (hw->aq.fw_maj_ver < 6)
9412                                         reg_table[i].val =
9413                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9414                                 else
9415                                         reg_table[i].val =
9416                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9417                 }
9418
9419                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9420                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9421                                 reg_table[i].val =
9422                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9423                         else /* For X710/XL710/XXV710 */
9424                                 reg_table[i].val =
9425                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9426                 }
9427
9428                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9429                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9430                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9431                                 reg_table[i].val =
9432                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9433                         else /* For X710 */
9434                                 reg_table[i].val =
9435                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9436                 }
9437
9438                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9439                                                         &reg, NULL);
9440                 if (ret < 0) {
9441                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9442                                                         reg_table[i].addr);
9443                         break;
9444                 }
9445                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9446                                                 reg_table[i].addr, reg);
9447                 if (reg == reg_table[i].val)
9448                         continue;
9449
9450                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9451                                                 reg_table[i].val, NULL);
9452                 if (ret < 0) {
9453                         PMD_DRV_LOG(ERR,
9454                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9455                                 reg_table[i].val, reg_table[i].addr);
9456                         break;
9457                 }
9458                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9459                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9460         }
9461 }
9462
9463 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9464 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9465 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9466 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9467 static int
9468 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9469 {
9470         uint32_t reg;
9471         int ret;
9472
9473         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9474                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9475                 return -EINVAL;
9476         }
9477
9478         /* Configure for double VLAN RX stripping */
9479         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9480         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9481                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9482                 ret = i40e_aq_debug_write_register(hw,
9483                                                    I40E_VSI_TSR(vsi->vsi_id),
9484                                                    reg, NULL);
9485                 if (ret < 0) {
9486                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9487                                     vsi->vsi_id);
9488                         return I40E_ERR_CONFIG;
9489                 }
9490         }
9491
9492         /* Configure for double VLAN TX insertion */
9493         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9494         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9495                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9496                 ret = i40e_aq_debug_write_register(hw,
9497                                                    I40E_VSI_L2TAGSTXVALID(
9498                                                    vsi->vsi_id), reg, NULL);
9499                 if (ret < 0) {
9500                         PMD_DRV_LOG(ERR,
9501                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9502                                 vsi->vsi_id);
9503                         return I40E_ERR_CONFIG;
9504                 }
9505         }
9506
9507         return 0;
9508 }
9509
9510 /**
9511  * i40e_aq_add_mirror_rule
9512  * @hw: pointer to the hardware structure
9513  * @seid: VEB seid to add mirror rule to
9514  * @dst_id: destination vsi seid
9515  * @entries: Buffer which contains the entities to be mirrored
9516  * @count: number of entities contained in the buffer
9517  * @rule_id:the rule_id of the rule to be added
9518  *
9519  * Add a mirror rule for a given veb.
9520  *
9521  **/
9522 static enum i40e_status_code
9523 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9524                         uint16_t seid, uint16_t dst_id,
9525                         uint16_t rule_type, uint16_t *entries,
9526                         uint16_t count, uint16_t *rule_id)
9527 {
9528         struct i40e_aq_desc desc;
9529         struct i40e_aqc_add_delete_mirror_rule cmd;
9530         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9531                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9532                 &desc.params.raw;
9533         uint16_t buff_len;
9534         enum i40e_status_code status;
9535
9536         i40e_fill_default_direct_cmd_desc(&desc,
9537                                           i40e_aqc_opc_add_mirror_rule);
9538         memset(&cmd, 0, sizeof(cmd));
9539
9540         buff_len = sizeof(uint16_t) * count;
9541         desc.datalen = rte_cpu_to_le_16(buff_len);
9542         if (buff_len > 0)
9543                 desc.flags |= rte_cpu_to_le_16(
9544                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9545         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9546                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9547         cmd.num_entries = rte_cpu_to_le_16(count);
9548         cmd.seid = rte_cpu_to_le_16(seid);
9549         cmd.destination = rte_cpu_to_le_16(dst_id);
9550
9551         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9552         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9553         PMD_DRV_LOG(INFO,
9554                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9555                 hw->aq.asq_last_status, resp->rule_id,
9556                 resp->mirror_rules_used, resp->mirror_rules_free);
9557         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9558
9559         return status;
9560 }
9561
9562 /**
9563  * i40e_aq_del_mirror_rule
9564  * @hw: pointer to the hardware structure
9565  * @seid: VEB seid to add mirror rule to
9566  * @entries: Buffer which contains the entities to be mirrored
9567  * @count: number of entities contained in the buffer
9568  * @rule_id:the rule_id of the rule to be delete
9569  *
9570  * Delete a mirror rule for a given veb.
9571  *
9572  **/
9573 static enum i40e_status_code
9574 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9575                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9576                 uint16_t count, uint16_t rule_id)
9577 {
9578         struct i40e_aq_desc desc;
9579         struct i40e_aqc_add_delete_mirror_rule cmd;
9580         uint16_t buff_len = 0;
9581         enum i40e_status_code status;
9582         void *buff = NULL;
9583
9584         i40e_fill_default_direct_cmd_desc(&desc,
9585                                           i40e_aqc_opc_delete_mirror_rule);
9586         memset(&cmd, 0, sizeof(cmd));
9587         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9588                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9589                                                           I40E_AQ_FLAG_RD));
9590                 cmd.num_entries = count;
9591                 buff_len = sizeof(uint16_t) * count;
9592                 desc.datalen = rte_cpu_to_le_16(buff_len);
9593                 buff = (void *)entries;
9594         } else
9595                 /* rule id is filled in destination field for deleting mirror rule */
9596                 cmd.destination = rte_cpu_to_le_16(rule_id);
9597
9598         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9599                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9600         cmd.seid = rte_cpu_to_le_16(seid);
9601
9602         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9603         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9604
9605         return status;
9606 }
9607
9608 /**
9609  * i40e_mirror_rule_set
9610  * @dev: pointer to the hardware structure
9611  * @mirror_conf: mirror rule info
9612  * @sw_id: mirror rule's sw_id
9613  * @on: enable/disable
9614  *
9615  * set a mirror rule.
9616  *
9617  **/
9618 static int
9619 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9620                         struct rte_eth_mirror_conf *mirror_conf,
9621                         uint8_t sw_id, uint8_t on)
9622 {
9623         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9624         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9625         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9626         struct i40e_mirror_rule *parent = NULL;
9627         uint16_t seid, dst_seid, rule_id;
9628         uint16_t i, j = 0;
9629         int ret;
9630
9631         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9632
9633         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9634                 PMD_DRV_LOG(ERR,
9635                         "mirror rule can not be configured without veb or vfs.");
9636                 return -ENOSYS;
9637         }
9638         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9639                 PMD_DRV_LOG(ERR, "mirror table is full.");
9640                 return -ENOSPC;
9641         }
9642         if (mirror_conf->dst_pool > pf->vf_num) {
9643                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9644                                  mirror_conf->dst_pool);
9645                 return -EINVAL;
9646         }
9647
9648         seid = pf->main_vsi->veb->seid;
9649
9650         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9651                 if (sw_id <= it->index) {
9652                         mirr_rule = it;
9653                         break;
9654                 }
9655                 parent = it;
9656         }
9657         if (mirr_rule && sw_id == mirr_rule->index) {
9658                 if (on) {
9659                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9660                         return -EEXIST;
9661                 } else {
9662                         ret = i40e_aq_del_mirror_rule(hw, seid,
9663                                         mirr_rule->rule_type,
9664                                         mirr_rule->entries,
9665                                         mirr_rule->num_entries, mirr_rule->id);
9666                         if (ret < 0) {
9667                                 PMD_DRV_LOG(ERR,
9668                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9669                                         ret, hw->aq.asq_last_status);
9670                                 return -ENOSYS;
9671                         }
9672                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9673                         rte_free(mirr_rule);
9674                         pf->nb_mirror_rule--;
9675                         return 0;
9676                 }
9677         } else if (!on) {
9678                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9679                 return -ENOENT;
9680         }
9681
9682         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9683                                 sizeof(struct i40e_mirror_rule) , 0);
9684         if (!mirr_rule) {
9685                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9686                 return I40E_ERR_NO_MEMORY;
9687         }
9688         switch (mirror_conf->rule_type) {
9689         case ETH_MIRROR_VLAN:
9690                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9691                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9692                                 mirr_rule->entries[j] =
9693                                         mirror_conf->vlan.vlan_id[i];
9694                                 j++;
9695                         }
9696                 }
9697                 if (j == 0) {
9698                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9699                         rte_free(mirr_rule);
9700                         return -EINVAL;
9701                 }
9702                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9703                 break;
9704         case ETH_MIRROR_VIRTUAL_POOL_UP:
9705         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9706                 /* check if the specified pool bit is out of range */
9707                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9708                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9709                         rte_free(mirr_rule);
9710                         return -EINVAL;
9711                 }
9712                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9713                         if (mirror_conf->pool_mask & (1ULL << i)) {
9714                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9715                                 j++;
9716                         }
9717                 }
9718                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9719                         /* add pf vsi to entries */
9720                         mirr_rule->entries[j] = pf->main_vsi_seid;
9721                         j++;
9722                 }
9723                 if (j == 0) {
9724                         PMD_DRV_LOG(ERR, "pool is not specified.");
9725                         rte_free(mirr_rule);
9726                         return -EINVAL;
9727                 }
9728                 /* egress and ingress in aq commands means from switch but not port */
9729                 mirr_rule->rule_type =
9730                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9731                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9732                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9733                 break;
9734         case ETH_MIRROR_UPLINK_PORT:
9735                 /* egress and ingress in aq commands means from switch but not port*/
9736                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9737                 break;
9738         case ETH_MIRROR_DOWNLINK_PORT:
9739                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9740                 break;
9741         default:
9742                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9743                         mirror_conf->rule_type);
9744                 rte_free(mirr_rule);
9745                 return -EINVAL;
9746         }
9747
9748         /* If the dst_pool is equal to vf_num, consider it as PF */
9749         if (mirror_conf->dst_pool == pf->vf_num)
9750                 dst_seid = pf->main_vsi_seid;
9751         else
9752                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9753
9754         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9755                                       mirr_rule->rule_type, mirr_rule->entries,
9756                                       j, &rule_id);
9757         if (ret < 0) {
9758                 PMD_DRV_LOG(ERR,
9759                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9760                         ret, hw->aq.asq_last_status);
9761                 rte_free(mirr_rule);
9762                 return -ENOSYS;
9763         }
9764
9765         mirr_rule->index = sw_id;
9766         mirr_rule->num_entries = j;
9767         mirr_rule->id = rule_id;
9768         mirr_rule->dst_vsi_seid = dst_seid;
9769
9770         if (parent)
9771                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9772         else
9773                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9774
9775         pf->nb_mirror_rule++;
9776         return 0;
9777 }
9778
9779 /**
9780  * i40e_mirror_rule_reset
9781  * @dev: pointer to the device
9782  * @sw_id: mirror rule's sw_id
9783  *
9784  * reset a mirror rule.
9785  *
9786  **/
9787 static int
9788 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9789 {
9790         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9791         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9792         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9793         uint16_t seid;
9794         int ret;
9795
9796         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9797
9798         seid = pf->main_vsi->veb->seid;
9799
9800         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9801                 if (sw_id == it->index) {
9802                         mirr_rule = it;
9803                         break;
9804                 }
9805         }
9806         if (mirr_rule) {
9807                 ret = i40e_aq_del_mirror_rule(hw, seid,
9808                                 mirr_rule->rule_type,
9809                                 mirr_rule->entries,
9810                                 mirr_rule->num_entries, mirr_rule->id);
9811                 if (ret < 0) {
9812                         PMD_DRV_LOG(ERR,
9813                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9814                                 ret, hw->aq.asq_last_status);
9815                         return -ENOSYS;
9816                 }
9817                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9818                 rte_free(mirr_rule);
9819                 pf->nb_mirror_rule--;
9820         } else {
9821                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9822                 return -ENOENT;
9823         }
9824         return 0;
9825 }
9826
9827 static uint64_t
9828 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9829 {
9830         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9831         uint64_t systim_cycles;
9832
9833         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9834         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9835                         << 32;
9836
9837         return systim_cycles;
9838 }
9839
9840 static uint64_t
9841 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9842 {
9843         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9844         uint64_t rx_tstamp;
9845
9846         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9847         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9848                         << 32;
9849
9850         return rx_tstamp;
9851 }
9852
9853 static uint64_t
9854 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9855 {
9856         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9857         uint64_t tx_tstamp;
9858
9859         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9860         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9861                         << 32;
9862
9863         return tx_tstamp;
9864 }
9865
9866 static void
9867 i40e_start_timecounters(struct rte_eth_dev *dev)
9868 {
9869         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9870         struct i40e_adapter *adapter =
9871                         (struct i40e_adapter *)dev->data->dev_private;
9872         struct rte_eth_link link;
9873         uint32_t tsync_inc_l;
9874         uint32_t tsync_inc_h;
9875
9876         /* Get current link speed. */
9877         memset(&link, 0, sizeof(link));
9878         i40e_dev_link_update(dev, 1);
9879         rte_i40e_dev_atomic_read_link_status(dev, &link);
9880
9881         switch (link.link_speed) {
9882         case ETH_SPEED_NUM_40G:
9883                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9884                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9885                 break;
9886         case ETH_SPEED_NUM_10G:
9887                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9888                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9889                 break;
9890         case ETH_SPEED_NUM_1G:
9891                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9892                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9893                 break;
9894         default:
9895                 tsync_inc_l = 0x0;
9896                 tsync_inc_h = 0x0;
9897         }
9898
9899         /* Set the timesync increment value. */
9900         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9901         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9902
9903         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9904         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9905         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9906
9907         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9908         adapter->systime_tc.cc_shift = 0;
9909         adapter->systime_tc.nsec_mask = 0;
9910
9911         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9912         adapter->rx_tstamp_tc.cc_shift = 0;
9913         adapter->rx_tstamp_tc.nsec_mask = 0;
9914
9915         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9916         adapter->tx_tstamp_tc.cc_shift = 0;
9917         adapter->tx_tstamp_tc.nsec_mask = 0;
9918 }
9919
9920 static int
9921 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9922 {
9923         struct i40e_adapter *adapter =
9924                         (struct i40e_adapter *)dev->data->dev_private;
9925
9926         adapter->systime_tc.nsec += delta;
9927         adapter->rx_tstamp_tc.nsec += delta;
9928         adapter->tx_tstamp_tc.nsec += delta;
9929
9930         return 0;
9931 }
9932
9933 static int
9934 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9935 {
9936         uint64_t ns;
9937         struct i40e_adapter *adapter =
9938                         (struct i40e_adapter *)dev->data->dev_private;
9939
9940         ns = rte_timespec_to_ns(ts);
9941
9942         /* Set the timecounters to a new value. */
9943         adapter->systime_tc.nsec = ns;
9944         adapter->rx_tstamp_tc.nsec = ns;
9945         adapter->tx_tstamp_tc.nsec = ns;
9946
9947         return 0;
9948 }
9949
9950 static int
9951 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9952 {
9953         uint64_t ns, systime_cycles;
9954         struct i40e_adapter *adapter =
9955                         (struct i40e_adapter *)dev->data->dev_private;
9956
9957         systime_cycles = i40e_read_systime_cyclecounter(dev);
9958         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9959         *ts = rte_ns_to_timespec(ns);
9960
9961         return 0;
9962 }
9963
9964 static int
9965 i40e_timesync_enable(struct rte_eth_dev *dev)
9966 {
9967         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9968         uint32_t tsync_ctl_l;
9969         uint32_t tsync_ctl_h;
9970
9971         /* Stop the timesync system time. */
9972         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9973         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9974         /* Reset the timesync system time value. */
9975         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9976         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9977
9978         i40e_start_timecounters(dev);
9979
9980         /* Clear timesync registers. */
9981         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9982         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9983         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9984         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9985         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9986         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9987
9988         /* Enable timestamping of PTP packets. */
9989         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9990         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9991
9992         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9993         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9994         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9995
9996         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9997         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9998
9999         return 0;
10000 }
10001
10002 static int
10003 i40e_timesync_disable(struct rte_eth_dev *dev)
10004 {
10005         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10006         uint32_t tsync_ctl_l;
10007         uint32_t tsync_ctl_h;
10008
10009         /* Disable timestamping of transmitted PTP packets. */
10010         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10011         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10012
10013         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10014         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10015
10016         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10017         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10018
10019         /* Reset the timesync increment value. */
10020         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10021         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10022
10023         return 0;
10024 }
10025
10026 static int
10027 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10028                                 struct timespec *timestamp, uint32_t flags)
10029 {
10030         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10031         struct i40e_adapter *adapter =
10032                 (struct i40e_adapter *)dev->data->dev_private;
10033
10034         uint32_t sync_status;
10035         uint32_t index = flags & 0x03;
10036         uint64_t rx_tstamp_cycles;
10037         uint64_t ns;
10038
10039         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10040         if ((sync_status & (1 << index)) == 0)
10041                 return -EINVAL;
10042
10043         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10044         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10045         *timestamp = rte_ns_to_timespec(ns);
10046
10047         return 0;
10048 }
10049
10050 static int
10051 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10052                                 struct timespec *timestamp)
10053 {
10054         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10055         struct i40e_adapter *adapter =
10056                 (struct i40e_adapter *)dev->data->dev_private;
10057
10058         uint32_t sync_status;
10059         uint64_t tx_tstamp_cycles;
10060         uint64_t ns;
10061
10062         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10063         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10064                 return -EINVAL;
10065
10066         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10067         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10068         *timestamp = rte_ns_to_timespec(ns);
10069
10070         return 0;
10071 }
10072
10073 /*
10074  * i40e_parse_dcb_configure - parse dcb configure from user
10075  * @dev: the device being configured
10076  * @dcb_cfg: pointer of the result of parse
10077  * @*tc_map: bit map of enabled traffic classes
10078  *
10079  * Returns 0 on success, negative value on failure
10080  */
10081 static int
10082 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10083                          struct i40e_dcbx_config *dcb_cfg,
10084                          uint8_t *tc_map)
10085 {
10086         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10087         uint8_t i, tc_bw, bw_lf;
10088
10089         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10090
10091         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10092         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10093                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10094                 return -EINVAL;
10095         }
10096
10097         /* assume each tc has the same bw */
10098         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10099         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10100                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10101         /* to ensure the sum of tcbw is equal to 100 */
10102         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10103         for (i = 0; i < bw_lf; i++)
10104                 dcb_cfg->etscfg.tcbwtable[i]++;
10105
10106         /* assume each tc has the same Transmission Selection Algorithm */
10107         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10108                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10109
10110         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10111                 dcb_cfg->etscfg.prioritytable[i] =
10112                                 dcb_rx_conf->dcb_tc[i];
10113
10114         /* FW needs one App to configure HW */
10115         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10116         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10117         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10118         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10119
10120         if (dcb_rx_conf->nb_tcs == 0)
10121                 *tc_map = 1; /* tc0 only */
10122         else
10123                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10124
10125         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10126                 dcb_cfg->pfc.willing = 0;
10127                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10128                 dcb_cfg->pfc.pfcenable = *tc_map;
10129         }
10130         return 0;
10131 }
10132
10133
10134 static enum i40e_status_code
10135 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10136                               struct i40e_aqc_vsi_properties_data *info,
10137                               uint8_t enabled_tcmap)
10138 {
10139         enum i40e_status_code ret;
10140         int i, total_tc = 0;
10141         uint16_t qpnum_per_tc, bsf, qp_idx;
10142         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10143         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10144         uint16_t used_queues;
10145
10146         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10147         if (ret != I40E_SUCCESS)
10148                 return ret;
10149
10150         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10151                 if (enabled_tcmap & (1 << i))
10152                         total_tc++;
10153         }
10154         if (total_tc == 0)
10155                 total_tc = 1;
10156         vsi->enabled_tc = enabled_tcmap;
10157
10158         /* different VSI has different queues assigned */
10159         if (vsi->type == I40E_VSI_MAIN)
10160                 used_queues = dev_data->nb_rx_queues -
10161                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10162         else if (vsi->type == I40E_VSI_VMDQ2)
10163                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10164         else {
10165                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10166                 return I40E_ERR_NO_AVAILABLE_VSI;
10167         }
10168
10169         qpnum_per_tc = used_queues / total_tc;
10170         /* Number of queues per enabled TC */
10171         if (qpnum_per_tc == 0) {
10172                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10173                 return I40E_ERR_INVALID_QP_ID;
10174         }
10175         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10176                                 I40E_MAX_Q_PER_TC);
10177         bsf = rte_bsf32(qpnum_per_tc);
10178
10179         /**
10180          * Configure TC and queue mapping parameters, for enabled TC,
10181          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10182          * default queue will serve it.
10183          */
10184         qp_idx = 0;
10185         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10186                 if (vsi->enabled_tc & (1 << i)) {
10187                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10188                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10189                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10190                         qp_idx += qpnum_per_tc;
10191                 } else
10192                         info->tc_mapping[i] = 0;
10193         }
10194
10195         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10196         if (vsi->type == I40E_VSI_SRIOV) {
10197                 info->mapping_flags |=
10198                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10199                 for (i = 0; i < vsi->nb_qps; i++)
10200                         info->queue_mapping[i] =
10201                                 rte_cpu_to_le_16(vsi->base_queue + i);
10202         } else {
10203                 info->mapping_flags |=
10204                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10205                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10206         }
10207         info->valid_sections |=
10208                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10209
10210         return I40E_SUCCESS;
10211 }
10212
10213 /*
10214  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10215  * @veb: VEB to be configured
10216  * @tc_map: enabled TC bitmap
10217  *
10218  * Returns 0 on success, negative value on failure
10219  */
10220 static enum i40e_status_code
10221 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10222 {
10223         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10224         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10225         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10226         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10227         enum i40e_status_code ret = I40E_SUCCESS;
10228         int i;
10229         uint32_t bw_max;
10230
10231         /* Check if enabled_tc is same as existing or new TCs */
10232         if (veb->enabled_tc == tc_map)
10233                 return ret;
10234
10235         /* configure tc bandwidth */
10236         memset(&veb_bw, 0, sizeof(veb_bw));
10237         veb_bw.tc_valid_bits = tc_map;
10238         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10239         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10240                 if (tc_map & BIT_ULL(i))
10241                         veb_bw.tc_bw_share_credits[i] = 1;
10242         }
10243         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10244                                                    &veb_bw, NULL);
10245         if (ret) {
10246                 PMD_INIT_LOG(ERR,
10247                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10248                         hw->aq.asq_last_status);
10249                 return ret;
10250         }
10251
10252         memset(&ets_query, 0, sizeof(ets_query));
10253         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10254                                                    &ets_query, NULL);
10255         if (ret != I40E_SUCCESS) {
10256                 PMD_DRV_LOG(ERR,
10257                         "Failed to get switch_comp ETS configuration %u",
10258                         hw->aq.asq_last_status);
10259                 return ret;
10260         }
10261         memset(&bw_query, 0, sizeof(bw_query));
10262         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10263                                                   &bw_query, NULL);
10264         if (ret != I40E_SUCCESS) {
10265                 PMD_DRV_LOG(ERR,
10266                         "Failed to get switch_comp bandwidth configuration %u",
10267                         hw->aq.asq_last_status);
10268                 return ret;
10269         }
10270
10271         /* store and print out BW info */
10272         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10273         veb->bw_info.bw_max = ets_query.tc_bw_max;
10274         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10275         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10276         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10277                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10278                      I40E_16_BIT_WIDTH);
10279         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10280                 veb->bw_info.bw_ets_share_credits[i] =
10281                                 bw_query.tc_bw_share_credits[i];
10282                 veb->bw_info.bw_ets_credits[i] =
10283                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10284                 /* 4 bits per TC, 4th bit is reserved */
10285                 veb->bw_info.bw_ets_max[i] =
10286                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10287                                   RTE_LEN2MASK(3, uint8_t));
10288                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10289                             veb->bw_info.bw_ets_share_credits[i]);
10290                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10291                             veb->bw_info.bw_ets_credits[i]);
10292                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10293                             veb->bw_info.bw_ets_max[i]);
10294         }
10295
10296         veb->enabled_tc = tc_map;
10297
10298         return ret;
10299 }
10300
10301
10302 /*
10303  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10304  * @vsi: VSI to be configured
10305  * @tc_map: enabled TC bitmap
10306  *
10307  * Returns 0 on success, negative value on failure
10308  */
10309 static enum i40e_status_code
10310 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10311 {
10312         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10313         struct i40e_vsi_context ctxt;
10314         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10315         enum i40e_status_code ret = I40E_SUCCESS;
10316         int i;
10317
10318         /* Check if enabled_tc is same as existing or new TCs */
10319         if (vsi->enabled_tc == tc_map)
10320                 return ret;
10321
10322         /* configure tc bandwidth */
10323         memset(&bw_data, 0, sizeof(bw_data));
10324         bw_data.tc_valid_bits = tc_map;
10325         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10326         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10327                 if (tc_map & BIT_ULL(i))
10328                         bw_data.tc_bw_credits[i] = 1;
10329         }
10330         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10331         if (ret) {
10332                 PMD_INIT_LOG(ERR,
10333                         "AQ command Config VSI BW allocation per TC failed = %d",
10334                         hw->aq.asq_last_status);
10335                 goto out;
10336         }
10337         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10338                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10339
10340         /* Update Queue Pairs Mapping for currently enabled UPs */
10341         ctxt.seid = vsi->seid;
10342         ctxt.pf_num = hw->pf_id;
10343         ctxt.vf_num = 0;
10344         ctxt.uplink_seid = vsi->uplink_seid;
10345         ctxt.info = vsi->info;
10346         i40e_get_cap(hw);
10347         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10348         if (ret)
10349                 goto out;
10350
10351         /* Update the VSI after updating the VSI queue-mapping information */
10352         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10353         if (ret) {
10354                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10355                         hw->aq.asq_last_status);
10356                 goto out;
10357         }
10358         /* update the local VSI info with updated queue map */
10359         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10360                                         sizeof(vsi->info.tc_mapping));
10361         rte_memcpy(&vsi->info.queue_mapping,
10362                         &ctxt.info.queue_mapping,
10363                 sizeof(vsi->info.queue_mapping));
10364         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10365         vsi->info.valid_sections = 0;
10366
10367         /* query and update current VSI BW information */
10368         ret = i40e_vsi_get_bw_config(vsi);
10369         if (ret) {
10370                 PMD_INIT_LOG(ERR,
10371                          "Failed updating vsi bw info, err %s aq_err %s",
10372                          i40e_stat_str(hw, ret),
10373                          i40e_aq_str(hw, hw->aq.asq_last_status));
10374                 goto out;
10375         }
10376
10377         vsi->enabled_tc = tc_map;
10378
10379 out:
10380         return ret;
10381 }
10382
10383 /*
10384  * i40e_dcb_hw_configure - program the dcb setting to hw
10385  * @pf: pf the configuration is taken on
10386  * @new_cfg: new configuration
10387  * @tc_map: enabled TC bitmap
10388  *
10389  * Returns 0 on success, negative value on failure
10390  */
10391 static enum i40e_status_code
10392 i40e_dcb_hw_configure(struct i40e_pf *pf,
10393                       struct i40e_dcbx_config *new_cfg,
10394                       uint8_t tc_map)
10395 {
10396         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10397         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10398         struct i40e_vsi *main_vsi = pf->main_vsi;
10399         struct i40e_vsi_list *vsi_list;
10400         enum i40e_status_code ret;
10401         int i;
10402         uint32_t val;
10403
10404         /* Use the FW API if FW > v4.4*/
10405         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10406               (hw->aq.fw_maj_ver >= 5))) {
10407                 PMD_INIT_LOG(ERR,
10408                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10409                 return I40E_ERR_FIRMWARE_API_VERSION;
10410         }
10411
10412         /* Check if need reconfiguration */
10413         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10414                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10415                 return I40E_SUCCESS;
10416         }
10417
10418         /* Copy the new config to the current config */
10419         *old_cfg = *new_cfg;
10420         old_cfg->etsrec = old_cfg->etscfg;
10421         ret = i40e_set_dcb_config(hw);
10422         if (ret) {
10423                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10424                          i40e_stat_str(hw, ret),
10425                          i40e_aq_str(hw, hw->aq.asq_last_status));
10426                 return ret;
10427         }
10428         /* set receive Arbiter to RR mode and ETS scheme by default */
10429         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10430                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10431                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10432                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10433                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10434                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10435                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10436                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10437                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10438                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10439                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10440                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10441                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10442         }
10443         /* get local mib to check whether it is configured correctly */
10444         /* IEEE mode */
10445         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10446         /* Get Local DCB Config */
10447         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10448                                      &hw->local_dcbx_config);
10449
10450         /* if Veb is created, need to update TC of it at first */
10451         if (main_vsi->veb) {
10452                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10453                 if (ret)
10454                         PMD_INIT_LOG(WARNING,
10455                                  "Failed configuring TC for VEB seid=%d",
10456                                  main_vsi->veb->seid);
10457         }
10458         /* Update each VSI */
10459         i40e_vsi_config_tc(main_vsi, tc_map);
10460         if (main_vsi->veb) {
10461                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10462                         /* Beside main VSI and VMDQ VSIs, only enable default
10463                          * TC for other VSIs
10464                          */
10465                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10466                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10467                                                          tc_map);
10468                         else
10469                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10470                                                          I40E_DEFAULT_TCMAP);
10471                         if (ret)
10472                                 PMD_INIT_LOG(WARNING,
10473                                         "Failed configuring TC for VSI seid=%d",
10474                                         vsi_list->vsi->seid);
10475                         /* continue */
10476                 }
10477         }
10478         return I40E_SUCCESS;
10479 }
10480
10481 /*
10482  * i40e_dcb_init_configure - initial dcb config
10483  * @dev: device being configured
10484  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10485  *
10486  * Returns 0 on success, negative value on failure
10487  */
10488 int
10489 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10490 {
10491         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10492         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10493         int i, ret = 0;
10494
10495         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10496                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10497                 return -ENOTSUP;
10498         }
10499
10500         /* DCB initialization:
10501          * Update DCB configuration from the Firmware and configure
10502          * LLDP MIB change event.
10503          */
10504         if (sw_dcb == TRUE) {
10505                 ret = i40e_init_dcb(hw);
10506                 /* If lldp agent is stopped, the return value from
10507                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10508                  * adminq status. Otherwise, it should return success.
10509                  */
10510                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10511                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10512                         memset(&hw->local_dcbx_config, 0,
10513                                 sizeof(struct i40e_dcbx_config));
10514                         /* set dcb default configuration */
10515                         hw->local_dcbx_config.etscfg.willing = 0;
10516                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10517                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10518                         hw->local_dcbx_config.etscfg.tsatable[0] =
10519                                                 I40E_IEEE_TSA_ETS;
10520                         /* all UPs mapping to TC0 */
10521                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10522                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10523                         hw->local_dcbx_config.etsrec =
10524                                 hw->local_dcbx_config.etscfg;
10525                         hw->local_dcbx_config.pfc.willing = 0;
10526                         hw->local_dcbx_config.pfc.pfccap =
10527                                                 I40E_MAX_TRAFFIC_CLASS;
10528                         /* FW needs one App to configure HW */
10529                         hw->local_dcbx_config.numapps = 1;
10530                         hw->local_dcbx_config.app[0].selector =
10531                                                 I40E_APP_SEL_ETHTYPE;
10532                         hw->local_dcbx_config.app[0].priority = 3;
10533                         hw->local_dcbx_config.app[0].protocolid =
10534                                                 I40E_APP_PROTOID_FCOE;
10535                         ret = i40e_set_dcb_config(hw);
10536                         if (ret) {
10537                                 PMD_INIT_LOG(ERR,
10538                                         "default dcb config fails. err = %d, aq_err = %d.",
10539                                         ret, hw->aq.asq_last_status);
10540                                 return -ENOSYS;
10541                         }
10542                 } else {
10543                         PMD_INIT_LOG(ERR,
10544                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10545                                 ret, hw->aq.asq_last_status);
10546                         return -ENOTSUP;
10547                 }
10548         } else {
10549                 ret = i40e_aq_start_lldp(hw, NULL);
10550                 if (ret != I40E_SUCCESS)
10551                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10552
10553                 ret = i40e_init_dcb(hw);
10554                 if (!ret) {
10555                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10556                                 PMD_INIT_LOG(ERR,
10557                                         "HW doesn't support DCBX offload.");
10558                                 return -ENOTSUP;
10559                         }
10560                 } else {
10561                         PMD_INIT_LOG(ERR,
10562                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10563                                 ret, hw->aq.asq_last_status);
10564                         return -ENOTSUP;
10565                 }
10566         }
10567         return 0;
10568 }
10569
10570 /*
10571  * i40e_dcb_setup - setup dcb related config
10572  * @dev: device being configured
10573  *
10574  * Returns 0 on success, negative value on failure
10575  */
10576 static int
10577 i40e_dcb_setup(struct rte_eth_dev *dev)
10578 {
10579         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10580         struct i40e_dcbx_config dcb_cfg;
10581         uint8_t tc_map = 0;
10582         int ret = 0;
10583
10584         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10585                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10586                 return -ENOTSUP;
10587         }
10588
10589         if (pf->vf_num != 0)
10590                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10591
10592         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10593         if (ret) {
10594                 PMD_INIT_LOG(ERR, "invalid dcb config");
10595                 return -EINVAL;
10596         }
10597         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10598         if (ret) {
10599                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10600                 return -ENOSYS;
10601         }
10602
10603         return 0;
10604 }
10605
10606 static int
10607 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10608                       struct rte_eth_dcb_info *dcb_info)
10609 {
10610         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10611         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10612         struct i40e_vsi *vsi = pf->main_vsi;
10613         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10614         uint16_t bsf, tc_mapping;
10615         int i, j = 0;
10616
10617         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10618                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10619         else
10620                 dcb_info->nb_tcs = 1;
10621         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10622                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10623         for (i = 0; i < dcb_info->nb_tcs; i++)
10624                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10625
10626         /* get queue mapping if vmdq is disabled */
10627         if (!pf->nb_cfg_vmdq_vsi) {
10628                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10629                         if (!(vsi->enabled_tc & (1 << i)))
10630                                 continue;
10631                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10632                         dcb_info->tc_queue.tc_rxq[j][i].base =
10633                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10634                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10635                         dcb_info->tc_queue.tc_txq[j][i].base =
10636                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10637                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10638                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10639                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10640                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10641                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10642                 }
10643                 return 0;
10644         }
10645
10646         /* get queue mapping if vmdq is enabled */
10647         do {
10648                 vsi = pf->vmdq[j].vsi;
10649                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10650                         if (!(vsi->enabled_tc & (1 << i)))
10651                                 continue;
10652                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10653                         dcb_info->tc_queue.tc_rxq[j][i].base =
10654                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10655                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10656                         dcb_info->tc_queue.tc_txq[j][i].base =
10657                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10658                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10659                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10660                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10661                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10662                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10663                 }
10664                 j++;
10665         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10666         return 0;
10667 }
10668
10669 static int
10670 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10671 {
10672         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10673         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10674         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10675         uint16_t interval =
10676                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10677         uint16_t msix_intr;
10678
10679         msix_intr = intr_handle->intr_vec[queue_id];
10680         if (msix_intr == I40E_MISC_VEC_ID)
10681                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10682                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10683                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10684                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10685                                (interval <<
10686                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10687         else
10688                 I40E_WRITE_REG(hw,
10689                                I40E_PFINT_DYN_CTLN(msix_intr -
10690                                                    I40E_RX_VEC_START),
10691                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10692                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10693                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10694                                (interval <<
10695                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10696
10697         I40E_WRITE_FLUSH(hw);
10698         rte_intr_enable(&pci_dev->intr_handle);
10699
10700         return 0;
10701 }
10702
10703 static int
10704 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10705 {
10706         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10707         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10708         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10709         uint16_t msix_intr;
10710
10711         msix_intr = intr_handle->intr_vec[queue_id];
10712         if (msix_intr == I40E_MISC_VEC_ID)
10713                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10714         else
10715                 I40E_WRITE_REG(hw,
10716                                I40E_PFINT_DYN_CTLN(msix_intr -
10717                                                    I40E_RX_VEC_START),
10718                                0);
10719         I40E_WRITE_FLUSH(hw);
10720
10721         return 0;
10722 }
10723
10724 static int i40e_get_regs(struct rte_eth_dev *dev,
10725                          struct rte_dev_reg_info *regs)
10726 {
10727         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10728         uint32_t *ptr_data = regs->data;
10729         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10730         const struct i40e_reg_info *reg_info;
10731
10732         if (ptr_data == NULL) {
10733                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10734                 regs->width = sizeof(uint32_t);
10735                 return 0;
10736         }
10737
10738         /* The first few registers have to be read using AQ operations */
10739         reg_idx = 0;
10740         while (i40e_regs_adminq[reg_idx].name) {
10741                 reg_info = &i40e_regs_adminq[reg_idx++];
10742                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10743                         for (arr_idx2 = 0;
10744                                         arr_idx2 <= reg_info->count2;
10745                                         arr_idx2++) {
10746                                 reg_offset = arr_idx * reg_info->stride1 +
10747                                         arr_idx2 * reg_info->stride2;
10748                                 reg_offset += reg_info->base_addr;
10749                                 ptr_data[reg_offset >> 2] =
10750                                         i40e_read_rx_ctl(hw, reg_offset);
10751                         }
10752         }
10753
10754         /* The remaining registers can be read using primitives */
10755         reg_idx = 0;
10756         while (i40e_regs_others[reg_idx].name) {
10757                 reg_info = &i40e_regs_others[reg_idx++];
10758                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10759                         for (arr_idx2 = 0;
10760                                         arr_idx2 <= reg_info->count2;
10761                                         arr_idx2++) {
10762                                 reg_offset = arr_idx * reg_info->stride1 +
10763                                         arr_idx2 * reg_info->stride2;
10764                                 reg_offset += reg_info->base_addr;
10765                                 ptr_data[reg_offset >> 2] =
10766                                         I40E_READ_REG(hw, reg_offset);
10767                         }
10768         }
10769
10770         return 0;
10771 }
10772
10773 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10774 {
10775         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10776
10777         /* Convert word count to byte count */
10778         return hw->nvm.sr_size << 1;
10779 }
10780
10781 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10782                            struct rte_dev_eeprom_info *eeprom)
10783 {
10784         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10785         uint16_t *data = eeprom->data;
10786         uint16_t offset, length, cnt_words;
10787         int ret_code;
10788
10789         offset = eeprom->offset >> 1;
10790         length = eeprom->length >> 1;
10791         cnt_words = length;
10792
10793         if (offset > hw->nvm.sr_size ||
10794                 offset + length > hw->nvm.sr_size) {
10795                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10796                 return -EINVAL;
10797         }
10798
10799         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10800
10801         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10802         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10803                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10804                 return -EIO;
10805         }
10806
10807         return 0;
10808 }
10809
10810 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10811                                       struct ether_addr *mac_addr)
10812 {
10813         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10814
10815         if (!is_valid_assigned_ether_addr(mac_addr)) {
10816                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10817                 return;
10818         }
10819
10820         /* Flags: 0x3 updates port address */
10821         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10822 }
10823
10824 static int
10825 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10826 {
10827         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10828         struct rte_eth_dev_data *dev_data = pf->dev_data;
10829         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10830         int ret = 0;
10831
10832         /* check if mtu is within the allowed range */
10833         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10834                 return -EINVAL;
10835
10836         /* mtu setting is forbidden if port is start */
10837         if (dev_data->dev_started) {
10838                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10839                             dev_data->port_id);
10840                 return -EBUSY;
10841         }
10842
10843         if (frame_size > ETHER_MAX_LEN)
10844                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10845         else
10846                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10847
10848         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10849
10850         return ret;
10851 }
10852
10853 /* Restore ethertype filter */
10854 static void
10855 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10856 {
10857         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10858         struct i40e_ethertype_filter_list
10859                 *ethertype_list = &pf->ethertype.ethertype_list;
10860         struct i40e_ethertype_filter *f;
10861         struct i40e_control_filter_stats stats;
10862         uint16_t flags;
10863
10864         TAILQ_FOREACH(f, ethertype_list, rules) {
10865                 flags = 0;
10866                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10867                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10868                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10869                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10870                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10871
10872                 memset(&stats, 0, sizeof(stats));
10873                 i40e_aq_add_rem_control_packet_filter(hw,
10874                                             f->input.mac_addr.addr_bytes,
10875                                             f->input.ether_type,
10876                                             flags, pf->main_vsi->seid,
10877                                             f->queue, 1, &stats, NULL);
10878         }
10879         PMD_DRV_LOG(INFO, "Ethertype filter:"
10880                     " mac_etype_used = %u, etype_used = %u,"
10881                     " mac_etype_free = %u, etype_free = %u",
10882                     stats.mac_etype_used, stats.etype_used,
10883                     stats.mac_etype_free, stats.etype_free);
10884 }
10885
10886 /* Restore tunnel filter */
10887 static void
10888 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10889 {
10890         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10891         struct i40e_vsi *vsi;
10892         struct i40e_pf_vf *vf;
10893         struct i40e_tunnel_filter_list
10894                 *tunnel_list = &pf->tunnel.tunnel_list;
10895         struct i40e_tunnel_filter *f;
10896         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10897         bool big_buffer = 0;
10898
10899         TAILQ_FOREACH(f, tunnel_list, rules) {
10900                 if (!f->is_to_vf)
10901                         vsi = pf->main_vsi;
10902                 else {
10903                         vf = &pf->vfs[f->vf_id];
10904                         vsi = vf->vsi;
10905                 }
10906                 memset(&cld_filter, 0, sizeof(cld_filter));
10907                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10908                         (struct ether_addr *)&cld_filter.element.outer_mac);
10909                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10910                         (struct ether_addr *)&cld_filter.element.inner_mac);
10911                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10912                 cld_filter.element.flags = f->input.flags;
10913                 cld_filter.element.tenant_id = f->input.tenant_id;
10914                 cld_filter.element.queue_number = f->queue;
10915                 rte_memcpy(cld_filter.general_fields,
10916                            f->input.general_fields,
10917                            sizeof(f->input.general_fields));
10918
10919                 if (((f->input.flags &
10920                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
10921                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
10922                     ((f->input.flags &
10923                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
10924                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
10925                     ((f->input.flags &
10926                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
10927                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
10928                         big_buffer = 1;
10929
10930                 if (big_buffer)
10931                         i40e_aq_add_cloud_filters_big_buffer(hw,
10932                                              vsi->seid, &cld_filter, 1);
10933                 else
10934                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10935                                                   &cld_filter.element, 1);
10936         }
10937 }
10938
10939 static void
10940 i40e_filter_restore(struct i40e_pf *pf)
10941 {
10942         i40e_ethertype_filter_restore(pf);
10943         i40e_tunnel_filter_restore(pf);
10944         i40e_fdir_filter_restore(pf);
10945 }
10946
10947 static bool
10948 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10949 {
10950         if (strcmp(dev->device->driver->name, drv->driver.name))
10951                 return false;
10952
10953         return true;
10954 }
10955
10956 bool
10957 is_i40e_supported(struct rte_eth_dev *dev)
10958 {
10959         return is_device_supported(dev, &rte_i40e_pmd);
10960 }
10961
10962 struct i40e_customized_pctype*
10963 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
10964 {
10965         int i;
10966
10967         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
10968                 if (pf->customized_pctype[i].index == index)
10969                         return &pf->customized_pctype[i];
10970         }
10971         return NULL;
10972 }
10973
10974 static int
10975 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
10976                               uint32_t pkg_size, uint32_t proto_num,
10977                               struct rte_pmd_i40e_proto_info *proto)
10978 {
10979         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10980         uint32_t pctype_num;
10981         struct rte_pmd_i40e_ptype_info *pctype;
10982         uint32_t buff_size;
10983         struct i40e_customized_pctype *new_pctype = NULL;
10984         uint8_t proto_id;
10985         uint8_t pctype_value;
10986         char name[64];
10987         uint32_t i, j, n;
10988         int ret;
10989
10990         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
10991                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
10992                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
10993         if (ret) {
10994                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
10995                 return -1;
10996         }
10997         if (!pctype_num) {
10998                 PMD_DRV_LOG(INFO, "No new pctype added");
10999                 return -1;
11000         }
11001
11002         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11003         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11004         if (!pctype) {
11005                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11006                 return -1;
11007         }
11008         /* get information about new pctype list */
11009         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11010                                         (uint8_t *)pctype, buff_size,
11011                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11012         if (ret) {
11013                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11014                 rte_free(pctype);
11015                 return -1;
11016         }
11017
11018         /* Update customized pctype. */
11019         for (i = 0; i < pctype_num; i++) {
11020                 pctype_value = pctype[i].ptype_id;
11021                 memset(name, 0, sizeof(name));
11022                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11023                         proto_id = pctype[i].protocols[j];
11024                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11025                                 continue;
11026                         for (n = 0; n < proto_num; n++) {
11027                                 if (proto[n].proto_id != proto_id)
11028                                         continue;
11029                                 strcat(name, proto[n].name);
11030                                 strcat(name, "_");
11031                                 break;
11032                         }
11033                 }
11034                 name[strlen(name) - 1] = '\0';
11035                 if (!strcmp(name, "GTPC"))
11036                         new_pctype =
11037                                 i40e_find_customized_pctype(pf,
11038                                                       I40E_CUSTOMIZED_GTPC);
11039                 else if (!strcmp(name, "GTPU_IPV4"))
11040                         new_pctype =
11041                                 i40e_find_customized_pctype(pf,
11042                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11043                 else if (!strcmp(name, "GTPU_IPV6"))
11044                         new_pctype =
11045                                 i40e_find_customized_pctype(pf,
11046                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11047                 else if (!strcmp(name, "GTPU"))
11048                         new_pctype =
11049                                 i40e_find_customized_pctype(pf,
11050                                                       I40E_CUSTOMIZED_GTPU);
11051                 if (new_pctype) {
11052                         new_pctype->pctype = pctype_value;
11053                         new_pctype->valid = true;
11054                 }
11055         }
11056
11057         rte_free(pctype);
11058         return 0;
11059 }
11060
11061 static int
11062 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11063                                uint32_t pkg_size, uint32_t proto_num,
11064                                struct rte_pmd_i40e_proto_info *proto)
11065 {
11066         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11067         uint16_t port_id = dev->data->port_id;
11068         uint32_t ptype_num;
11069         struct rte_pmd_i40e_ptype_info *ptype;
11070         uint32_t buff_size;
11071         uint8_t proto_id;
11072         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11073         uint32_t i, j, n;
11074         bool inner_ip;
11075         int ret;
11076
11077         /* get information about new ptype num */
11078         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11079                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11080                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11081         if (ret) {
11082                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11083                 return ret;
11084         }
11085         if (!ptype_num) {
11086                 PMD_DRV_LOG(INFO, "No new ptype added");
11087                 return -1;
11088         }
11089
11090         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11091         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11092         if (!ptype) {
11093                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11094                 return -1;
11095         }
11096
11097         /* get information about new ptype list */
11098         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11099                                         (uint8_t *)ptype, buff_size,
11100                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11101         if (ret) {
11102                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11103                 rte_free(ptype);
11104                 return ret;
11105         }
11106
11107         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11108         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11109         if (!ptype_mapping) {
11110                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11111                 rte_free(ptype);
11112                 return -1;
11113         }
11114
11115         /* Update ptype mapping table. */
11116         for (i = 0; i < ptype_num; i++) {
11117                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11118                 ptype_mapping[i].sw_ptype = 0;
11119                 inner_ip = false;
11120                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11121                         proto_id = ptype[i].protocols[j];
11122                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11123                                 continue;
11124                         for (n = 0; n < proto_num; n++) {
11125                                 if (proto[n].proto_id != proto_id)
11126                                         continue;
11127                                 memset(name, 0, sizeof(name));
11128                                 strcpy(name, proto[n].name);
11129                                 if (!strncmp(name, "IPV4", 4) && !inner_ip) {
11130                                         ptype_mapping[i].sw_ptype |=
11131                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11132                                         inner_ip = true;
11133                                 } else if (!strncmp(name, "IPV4FRAG", 8) &&
11134                                            inner_ip) {
11135                                         ptype_mapping[i].sw_ptype |=
11136                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11137                                         ptype_mapping[i].sw_ptype |=
11138                                                 RTE_PTYPE_INNER_L4_FRAG;
11139                                 } else if (!strncmp(name, "IPV4", 4) &&
11140                                            inner_ip)
11141                                         ptype_mapping[i].sw_ptype |=
11142                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11143                                 else if (!strncmp(name, "IPV6", 4) &&
11144                                          !inner_ip) {
11145                                         ptype_mapping[i].sw_ptype |=
11146                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11147                                         inner_ip = true;
11148                                 } else if (!strncmp(name, "IPV6FRAG", 8) &&
11149                                            inner_ip) {
11150                                         ptype_mapping[i].sw_ptype |=
11151                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11152                                         ptype_mapping[i].sw_ptype |=
11153                                                 RTE_PTYPE_INNER_L4_FRAG;
11154                                 } else if (!strncmp(name, "IPV6", 4) &&
11155                                            inner_ip)
11156                                         ptype_mapping[i].sw_ptype |=
11157                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11158                                 else if (!strncmp(name, "GTPC", 4))
11159                                         ptype_mapping[i].sw_ptype |=
11160                                                 RTE_PTYPE_TUNNEL_GTPC;
11161                                 else if (!strncmp(name, "GTPU", 4))
11162                                         ptype_mapping[i].sw_ptype |=
11163                                                 RTE_PTYPE_TUNNEL_GTPU;
11164                                 else if (!strncmp(name, "UDP", 3))
11165                                         ptype_mapping[i].sw_ptype |=
11166                                                 RTE_PTYPE_INNER_L4_UDP;
11167                                 else if (!strncmp(name, "TCP", 3))
11168                                         ptype_mapping[i].sw_ptype |=
11169                                                 RTE_PTYPE_INNER_L4_TCP;
11170                                 else if (!strncmp(name, "SCTP", 4))
11171                                         ptype_mapping[i].sw_ptype |=
11172                                                 RTE_PTYPE_INNER_L4_SCTP;
11173                                 else if (!strncmp(name, "ICMP", 4) ||
11174                                          !strncmp(name, "ICMPV6", 6))
11175                                         ptype_mapping[i].sw_ptype |=
11176                                                 RTE_PTYPE_INNER_L4_ICMP;
11177
11178                                 break;
11179                         }
11180                 }
11181         }
11182
11183         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11184                                                 ptype_num, 0);
11185         if (ret)
11186                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11187
11188         rte_free(ptype_mapping);
11189         rte_free(ptype);
11190         return ret;
11191 }
11192
11193 void
11194 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11195                               uint32_t pkg_size)
11196 {
11197         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11198         uint32_t proto_num;
11199         struct rte_pmd_i40e_proto_info *proto;
11200         uint32_t buff_size;
11201         uint32_t i;
11202         int ret;
11203
11204         /* get information about protocol number */
11205         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11206                                        (uint8_t *)&proto_num, sizeof(proto_num),
11207                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11208         if (ret) {
11209                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11210                 return;
11211         }
11212         if (!proto_num) {
11213                 PMD_DRV_LOG(INFO, "No new protocol added");
11214                 return;
11215         }
11216
11217         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11218         proto = rte_zmalloc("new_proto", buff_size, 0);
11219         if (!proto) {
11220                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11221                 return;
11222         }
11223
11224         /* get information about protocol list */
11225         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11226                                         (uint8_t *)proto, buff_size,
11227                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11228         if (ret) {
11229                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11230                 rte_free(proto);
11231                 return;
11232         }
11233
11234         /* Check if GTP is supported. */
11235         for (i = 0; i < proto_num; i++) {
11236                 if (!strncmp(proto[i].name, "GTP", 3)) {
11237                         pf->gtp_support = true;
11238                         break;
11239                 }
11240         }
11241
11242         /* Update customized pctype info */
11243         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11244                                             proto_num, proto);
11245         if (ret)
11246                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11247
11248         /* Update customized ptype info */
11249         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11250                                            proto_num, proto);
11251         if (ret)
11252                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11253
11254         rte_free(proto);
11255 }
11256
11257 /* Create a QinQ cloud filter
11258  *
11259  * The Fortville NIC has limited resources for tunnel filters,
11260  * so we can only reuse existing filters.
11261  *
11262  * In step 1 we define which Field Vector fields can be used for
11263  * filter types.
11264  * As we do not have the inner tag defined as a field,
11265  * we have to define it first, by reusing one of L1 entries.
11266  *
11267  * In step 2 we are replacing one of existing filter types with
11268  * a new one for QinQ.
11269  * As we reusing L1 and replacing L2, some of the default filter
11270  * types will disappear,which depends on L1 and L2 entries we reuse.
11271  *
11272  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11273  *
11274  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11275  *              later when we define the cloud filter.
11276  *      a.      Valid_flags.replace_cloud = 0
11277  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11278  *      c.      New_filter = 0x10
11279  *      d.      TR bit = 0xff (optional, not used here)
11280  *      e.      Buffer – 2 entries:
11281  *              i.      Byte 0 = 8 (outer vlan FV index).
11282  *                      Byte 1 = 0 (rsv)
11283  *                      Byte 2-3 = 0x0fff
11284  *              ii.     Byte 0 = 37 (inner vlan FV index).
11285  *                      Byte 1 =0 (rsv)
11286  *                      Byte 2-3 = 0x0fff
11287  *
11288  * Step 2:
11289  * 2.   Create cloud filter using two L1 filters entries: stag and
11290  *              new filter(outer vlan+ inner vlan)
11291  *      a.      Valid_flags.replace_cloud = 1
11292  *      b.      Old_filter = 1 (instead of outer IP)
11293  *      c.      New_filter = 0x10
11294  *      d.      Buffer – 2 entries:
11295  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11296  *                      Byte 1-3 = 0 (rsv)
11297  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11298  *                      Byte 9-11 = 0 (rsv)
11299  */
11300 static int
11301 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11302 {
11303         int ret = -ENOTSUP;
11304         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11305         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11306         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11307
11308         /* Init */
11309         memset(&filter_replace, 0,
11310                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11311         memset(&filter_replace_buf, 0,
11312                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11313
11314         /* create L1 filter */
11315         filter_replace.old_filter_type =
11316                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11317         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11318         filter_replace.tr_bit = 0;
11319
11320         /* Prepare the buffer, 2 entries */
11321         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11322         filter_replace_buf.data[0] |=
11323                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11324         /* Field Vector 12b mask */
11325         filter_replace_buf.data[2] = 0xff;
11326         filter_replace_buf.data[3] = 0x0f;
11327         filter_replace_buf.data[4] =
11328                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11329         filter_replace_buf.data[4] |=
11330                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11331         /* Field Vector 12b mask */
11332         filter_replace_buf.data[6] = 0xff;
11333         filter_replace_buf.data[7] = 0x0f;
11334         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11335                         &filter_replace_buf);
11336         if (ret != I40E_SUCCESS)
11337                 return ret;
11338
11339         /* Apply the second L2 cloud filter */
11340         memset(&filter_replace, 0,
11341                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11342         memset(&filter_replace_buf, 0,
11343                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11344
11345         /* create L2 filter, input for L2 filter will be L1 filter  */
11346         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11347         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11348         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11349
11350         /* Prepare the buffer, 2 entries */
11351         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11352         filter_replace_buf.data[0] |=
11353                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11354         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11355         filter_replace_buf.data[4] |=
11356                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11357         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11358                         &filter_replace_buf);
11359         return ret;
11360 }
11361
11362 RTE_INIT(i40e_init_log);
11363 static void
11364 i40e_init_log(void)
11365 {
11366         i40e_logtype_init = rte_log_register("pmd.i40e.init");
11367         if (i40e_logtype_init >= 0)
11368                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11369         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11370         if (i40e_logtype_driver >= 0)
11371                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
11372 }