drivers/net/i40e/i40e_ethdev_vf.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_atomic.h>
  51 #include <rte_branch_prediction.h>
  52 #include <rte_memory.h>
  53 #include <rte_memzone.h>
  54 #include <rte_eal.h>
  55 #include <rte_alarm.h>
  56 #include <rte_ether.h>
  57 #include <rte_ethdev.h>
  58 #include <rte_ethdev_pci.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_dev.h>
  62
  63 #include "i40e_logs.h"
  64 #include "base/i40e_prototype.h"
  65 #include "base/i40e_adminq_cmd.h"
  66 #include "base/i40e_type.h"
  67
  68 #include "i40e_rxtx.h"
  69 #include "i40e_ethdev.h"
  70 #include "i40e_pf.h"
  71 #define I40EVF_VSI_DEFAULT_MSIX_INTR     1
  72 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
  73
  74 /* busy wait delay in msec */
  75 #define I40EVF_BUSY_WAIT_DELAY 10
  76 #define I40EVF_BUSY_WAIT_COUNT 50
  77 #define MAX_RESET_WAIT_CNT     20
  78
  79 struct i40evf_arq_msg_info {
  80         enum i40e_virtchnl_ops ops;
  81         enum i40e_status_code result;
  82         uint16_t buf_len;
  83         uint16_t msg_len;
  84         uint8_t *msg;
  85 };
  86
  87 struct vf_cmd_info {
  88         enum i40e_virtchnl_ops ops;
  89         uint8_t *in_args;
  90         uint32_t in_args_size;
  91         uint8_t *out_buffer;
  92         /* Input & output type. pass in buffer size and pass out
  93          * actual return result
  94          */
  95         uint32_t out_size;
  96 };
  97
  98 enum i40evf_aq_result {
  99         I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
 100         I40EVF_MSG_NON,      /* Read nothing from admin queue */
 101         I40EVF_MSG_SYS,      /* Read system msg from admin queue */
 102         I40EVF_MSG_CMD,      /* Read async command result */
 103 };
 104
 105 static int i40evf_dev_configure(struct rte_eth_dev *dev);
 106 static int i40evf_dev_start(struct rte_eth_dev *dev);
 107 static void i40evf_dev_stop(struct rte_eth_dev *dev);
 108 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_dev_info *dev_info);
 110 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
 111                                   int wait_to_complete);
 112 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
 113                                 struct rte_eth_stats *stats);
 114 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 115                                  struct rte_eth_xstat *xstats, unsigned n);
 116 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
 117                                        struct rte_eth_xstat_name *xstats_names,
 118                                        unsigned limit);
 119 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
 120 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
 121                                   uint16_t vlan_id, int on);
 122 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 123 static int i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid,
 124                                 int on);
 125 static void i40evf_dev_close(struct rte_eth_dev *dev);
 126 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 127 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 128 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 129 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 130 static int i40evf_init_vlan(struct rte_eth_dev *dev);
 131 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
 132                                      uint16_t rx_queue_id);
 133 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
 134                                     uint16_t rx_queue_id);
 135 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
 136                                      uint16_t tx_queue_id);
 137 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
 138                                     uint16_t tx_queue_id);
 139 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
 140                                struct ether_addr *addr,
 141                                uint32_t index,
 142                                uint32_t pool);
 143 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 144 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
 145                         struct rte_eth_rss_reta_entry64 *reta_conf,
 146                         uint16_t reta_size);
 147 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
 148                         struct rte_eth_rss_reta_entry64 *reta_conf,
 149                         uint16_t reta_size);
 150 static int i40evf_config_rss(struct i40e_vf *vf);
 151 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
 152                                       struct rte_eth_rss_conf *rss_conf);
 153 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 154                                         struct rte_eth_rss_conf *rss_conf);
 155 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 156 static void i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
 157                                         struct ether_addr *mac_addr);
 158 static int
 159 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 160 static int
 161 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 162 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
 163                                    uint8_t *msg,
 164                                    uint16_t msglen);
 165
 166 /* Default hash key buffer for RSS */
 167 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
 168
 169 struct rte_i40evf_xstats_name_off {
 170         char name[RTE_ETH_XSTATS_NAME_SIZE];
 171         unsigned offset;
 172 };
 173
 174 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
 175         {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
 176         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 177         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 178         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 179         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 180         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 181                 rx_unknown_protocol)},
 182         {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
 183         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 184         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 185         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 186         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 187         {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
 188 };
 189
 190 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
 191                 sizeof(rte_i40evf_stats_strings[0]))
 192
 193 static const struct eth_dev_ops i40evf_eth_dev_ops = {
 194         .dev_configure        = i40evf_dev_configure,
 195         .dev_start            = i40evf_dev_start,
 196         .dev_stop             = i40evf_dev_stop,
 197         .promiscuous_enable   = i40evf_dev_promiscuous_enable,
 198         .promiscuous_disable  = i40evf_dev_promiscuous_disable,
 199         .allmulticast_enable  = i40evf_dev_allmulticast_enable,
 200         .allmulticast_disable = i40evf_dev_allmulticast_disable,
 201         .link_update          = i40evf_dev_link_update,
 202         .stats_get            = i40evf_dev_stats_get,
 203         .xstats_get           = i40evf_dev_xstats_get,
 204         .xstats_get_names     = i40evf_dev_xstats_get_names,
 205         .xstats_reset         = i40evf_dev_xstats_reset,
 206         .dev_close            = i40evf_dev_close,
 207         .dev_infos_get        = i40evf_dev_info_get,
 208         .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
 209         .vlan_filter_set      = i40evf_vlan_filter_set,
 210         .vlan_offload_set     = i40evf_vlan_offload_set,
 211         .vlan_pvid_set        = i40evf_vlan_pvid_set,
 212         .rx_queue_start       = i40evf_dev_rx_queue_start,
 213         .rx_queue_stop        = i40evf_dev_rx_queue_stop,
 214         .tx_queue_start       = i40evf_dev_tx_queue_start,
 215         .tx_queue_stop        = i40evf_dev_tx_queue_stop,
 216         .rx_queue_setup       = i40e_dev_rx_queue_setup,
 217         .rx_queue_release     = i40e_dev_rx_queue_release,
 218         .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
 219         .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
 220         .rx_descriptor_done   = i40e_dev_rx_descriptor_done,
 221         .rx_descriptor_status = i40e_dev_rx_descriptor_status,
 222         .tx_descriptor_status = i40e_dev_tx_descriptor_status,
 223         .tx_queue_setup       = i40e_dev_tx_queue_setup,
 224         .tx_queue_release     = i40e_dev_tx_queue_release,
 225         .rx_queue_count       = i40e_dev_rx_queue_count,
 226         .rxq_info_get         = i40e_rxq_info_get,
 227         .txq_info_get         = i40e_txq_info_get,
 228         .mac_addr_add         = i40evf_add_mac_addr,
 229         .mac_addr_remove      = i40evf_del_mac_addr,
 230         .reta_update          = i40evf_dev_rss_reta_update,
 231         .reta_query           = i40evf_dev_rss_reta_query,
 232         .rss_hash_update      = i40evf_dev_rss_hash_update,
 233         .rss_hash_conf_get    = i40evf_dev_rss_hash_conf_get,
 234         .mtu_set              = i40evf_dev_mtu_set,
 235         .mac_addr_set         = i40evf_set_default_mac_addr,
 236 };
 237
 238 /*
 239  * Read data in admin queue to get msg from pf driver
 240  */
 241 static enum i40evf_aq_result
 242 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
 243 {
 244         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 245         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 246         struct i40e_arq_event_info event;
 247         enum i40e_virtchnl_ops opcode;
 248         enum i40e_status_code retval;
 249         int ret;
 250         enum i40evf_aq_result result = I40EVF_MSG_NON;
 251
 252         event.buf_len = data->buf_len;
 253         event.msg_buf = data->msg;
 254         ret = i40e_clean_arq_element(hw, &event, NULL);
 255         /* Can't read any msg from adminQ */
 256         if (ret) {
 257                 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
 258                         result = I40EVF_MSG_ERR;
 259                 return result;
 260         }
 261
 262         opcode = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
 263         retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
 264         /* pf sys event */
 265         if (opcode == I40E_VIRTCHNL_OP_EVENT) {
 266                 struct i40e_virtchnl_pf_event *vpe =
 267                         (struct i40e_virtchnl_pf_event *)event.msg_buf;
 268
 269                 result = I40EVF_MSG_SYS;
 270                 switch (vpe->event) {
 271                 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
 272                         vf->link_up =
 273                                 vpe->event_data.link_event.link_status;
 274                         vf->link_speed =
 275                                 vpe->event_data.link_event.link_speed;
 276                         vf->pend_msg |= PFMSG_LINK_CHANGE;
 277                         PMD_DRV_LOG(INFO, "Link status update:%s",
 278                                     vf->link_up ? "up" : "down");
 279                         break;
 280                 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
 281                         vf->vf_reset = true;
 282                         vf->pend_msg |= PFMSG_RESET_IMPENDING;
 283                         PMD_DRV_LOG(INFO, "vf is reseting");
 284                         break;
 285                 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
 286                         vf->dev_closed = true;
 287                         vf->pend_msg |= PFMSG_DRIVER_CLOSE;
 288                         PMD_DRV_LOG(INFO, "PF driver closed");
 289                         break;
 290                 default:
 291                         PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
 292                                     __func__, vpe->event);
 293                 }
 294         } else {
 295                 /* async reply msg on command issued by vf previously */
 296                 result = I40EVF_MSG_CMD;
 297                 /* Actual data length read from PF */
 298                 data->msg_len = event.msg_len;
 299         }
 300
 301         data->result = retval;
 302         data->ops = opcode;
 303
 304         return result;
 305 }
 306
 307 /**
 308  * clear current command. Only call in case execute
 309  * _atomic_set_cmd successfully.
 310  */
 311 static inline void
 312 _clear_cmd(struct i40e_vf *vf)
 313 {
 314         rte_wmb();
 315         vf->pend_cmd = I40E_VIRTCHNL_OP_UNKNOWN;
 316 }
 317
 318 /*
 319  * Check there is pending cmd in execution. If none, set new command.
 320  */
 321 static inline int
 322 _atomic_set_cmd(struct i40e_vf *vf, enum i40e_virtchnl_ops ops)
 323 {
 324         int ret = rte_atomic32_cmpset(&vf->pend_cmd,
 325                         I40E_VIRTCHNL_OP_UNKNOWN, ops);
 326
 327         if (!ret)
 328                 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
 329
 330         return !ret;
 331 }
 332
 333 #define MAX_TRY_TIMES 200
 334 #define ASQ_DELAY_MS  10
 335
 336 static int
 337 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
 338 {
 339         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 340         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 341         struct i40evf_arq_msg_info info;
 342         enum i40evf_aq_result ret;
 343         int err, i = 0;
 344
 345         if (_atomic_set_cmd(vf, args->ops))
 346                 return -1;
 347
 348         info.msg = args->out_buffer;
 349         info.buf_len = args->out_size;
 350         info.ops = I40E_VIRTCHNL_OP_UNKNOWN;
 351         info.result = I40E_SUCCESS;
 352
 353         err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
 354                      args->in_args, args->in_args_size, NULL);
 355         if (err) {
 356                 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
 357                 _clear_cmd(vf);
 358                 return err;
 359         }
 360
 361         switch (args->ops) {
 362         case I40E_VIRTCHNL_OP_RESET_VF:
 363                 /*no need to process in this function */
 364                 err = 0;
 365                 break;
 366         case I40E_VIRTCHNL_OP_VERSION:
 367         case I40E_VIRTCHNL_OP_GET_VF_RESOURCES:
 368                 /* for init adminq commands, need to poll the response */
 369                 err = -1;
 370                 do {
 371                         ret = i40evf_read_pfmsg(dev, &info);
 372                         vf->cmd_retval = info.result;
 373                         if (ret == I40EVF_MSG_CMD) {
 374                                 err = 0;
 375                                 break;
 376                         } else if (ret == I40EVF_MSG_ERR)
 377                                 break;
 378                         rte_delay_ms(ASQ_DELAY_MS);
 379                         /* If don't read msg or read sys event, continue */
 380                 } while (i++ < MAX_TRY_TIMES);
 381                 _clear_cmd(vf);
 382                 break;
 383
 384         default:
 385                 /* for other adminq in running time, waiting the cmd done flag */
 386                 err = -1;
 387                 do {
 388                         if (vf->pend_cmd == I40E_VIRTCHNL_OP_UNKNOWN) {
 389                                 err = 0;
 390                                 break;
 391                         }
 392                         rte_delay_ms(ASQ_DELAY_MS);
 393                         /* If don't read msg or read sys event, continue */
 394                 } while (i++ < MAX_TRY_TIMES);
 395                 break;
 396         }
 397
 398         return err | vf->cmd_retval;
 399 }
 400
 401 /*
 402  * Check API version with sync wait until version read or fail from admin queue
 403  */
 404 static int
 405 i40evf_check_api_version(struct rte_eth_dev *dev)
 406 {
 407         struct i40e_virtchnl_version_info version, *pver;
 408         int err;
 409         struct vf_cmd_info args;
 410         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 411
 412         version.major = I40E_VIRTCHNL_VERSION_MAJOR;
 413         version.minor = I40E_VIRTCHNL_VERSION_MINOR;
 414
 415         args.ops = I40E_VIRTCHNL_OP_VERSION;
 416         args.in_args = (uint8_t *)&version;
 417         args.in_args_size = sizeof(version);
 418         args.out_buffer = vf->aq_resp;
 419         args.out_size = I40E_AQ_BUF_SZ;
 420
 421         err = i40evf_execute_vf_cmd(dev, &args);
 422         if (err) {
 423                 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
 424                 return err;
 425         }
 426
 427         pver = (struct i40e_virtchnl_version_info *)args.out_buffer;
 428         vf->version_major = pver->major;
 429         vf->version_minor = pver->minor;
 430         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 431                 PMD_DRV_LOG(INFO, "Peer is DPDK PF host");
 432         else if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
 433                 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR))
 434                 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
 435         else {
 436                 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
 437                                         vf->version_major, vf->version_minor,
 438                                                 I40E_VIRTCHNL_VERSION_MAJOR,
 439                                                 I40E_VIRTCHNL_VERSION_MINOR);
 440                 return -1;
 441         }
 442
 443         return 0;
 444 }
 445
 446 static int
 447 i40evf_get_vf_resource(struct rte_eth_dev *dev)
 448 {
 449         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 450         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 451         int err;
 452         struct vf_cmd_info args;
 453         uint32_t caps, len;
 454
 455         args.ops = I40E_VIRTCHNL_OP_GET_VF_RESOURCES;
 456         args.out_buffer = vf->aq_resp;
 457         args.out_size = I40E_AQ_BUF_SZ;
 458         if (PF_IS_V11(vf)) {
 459                 caps = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
 460                        I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ |
 461                        I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG |
 462                        I40E_VIRTCHNL_VF_OFFLOAD_VLAN |
 463                        I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING;
 464                 args.in_args = (uint8_t *)&caps;
 465                 args.in_args_size = sizeof(caps);
 466         } else {
 467                 args.in_args = NULL;
 468                 args.in_args_size = 0;
 469         }
 470         err = i40evf_execute_vf_cmd(dev, &args);
 471
 472         if (err) {
 473                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
 474                 return err;
 475         }
 476
 477         len =  sizeof(struct i40e_virtchnl_vf_resource) +
 478                 I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource);
 479
 480         (void)rte_memcpy(vf->vf_res, args.out_buffer,
 481                         RTE_MIN(args.out_size, len));
 482         i40e_vf_parse_hw_config(hw, vf->vf_res);
 483
 484         return 0;
 485 }
 486
 487 static int
 488 i40evf_config_promisc(struct rte_eth_dev *dev,
 489                       bool enable_unicast,
 490                       bool enable_multicast)
 491 {
 492         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 493         int err;
 494         struct vf_cmd_info args;
 495         struct i40e_virtchnl_promisc_info promisc;
 496
 497         promisc.flags = 0;
 498         promisc.vsi_id = vf->vsi_res->vsi_id;
 499
 500         if (enable_unicast)
 501                 promisc.flags |= I40E_FLAG_VF_UNICAST_PROMISC;
 502
 503         if (enable_multicast)
 504                 promisc.flags |= I40E_FLAG_VF_MULTICAST_PROMISC;
 505
 506         args.ops = I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
 507         args.in_args = (uint8_t *)&promisc;
 508         args.in_args_size = sizeof(promisc);
 509         args.out_buffer = vf->aq_resp;
 510         args.out_size = I40E_AQ_BUF_SZ;
 511
 512         err = i40evf_execute_vf_cmd(dev, &args);
 513
 514         if (err)
 515                 PMD_DRV_LOG(ERR, "fail to execute command "
 516                             "CONFIG_PROMISCUOUS_MODE");
 517         return err;
 518 }
 519
 520 /* Configure vlan and double vlan offload. Use flag to specify which part to configure */
 521 static int
 522 i40evf_config_vlan_offload(struct rte_eth_dev *dev,
 523                                 bool enable_vlan_strip)
 524 {
 525         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 526         int err;
 527         struct vf_cmd_info args;
 528         struct i40e_virtchnl_vlan_offload_info offload;
 529
 530         offload.vsi_id = vf->vsi_res->vsi_id;
 531         offload.enable_vlan_strip = enable_vlan_strip;
 532
 533         args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD;
 534         args.in_args = (uint8_t *)&offload;
 535         args.in_args_size = sizeof(offload);
 536         args.out_buffer = vf->aq_resp;
 537         args.out_size = I40E_AQ_BUF_SZ;
 538
 539         err = i40evf_execute_vf_cmd(dev, &args);
 540         if (err)
 541                 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_OFFLOAD");
 542
 543         return err;
 544 }
 545
 546 static int
 547 i40evf_config_vlan_pvid(struct rte_eth_dev *dev,
 548                                 struct i40e_vsi_vlan_pvid_info *info)
 549 {
 550         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 551         int err;
 552         struct vf_cmd_info args;
 553         struct i40e_virtchnl_pvid_info tpid_info;
 554
 555         if (info == NULL) {
 556                 PMD_DRV_LOG(ERR, "invalid parameters");
 557                 return I40E_ERR_PARAM;
 558         }
 559
 560         memset(&tpid_info, 0, sizeof(tpid_info));
 561         tpid_info.vsi_id = vf->vsi_res->vsi_id;
 562         (void)rte_memcpy(&tpid_info.info, info, sizeof(*info));
 563
 564         args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_PVID;
 565         args.in_args = (uint8_t *)&tpid_info;
 566         args.in_args_size = sizeof(tpid_info);
 567         args.out_buffer = vf->aq_resp;
 568         args.out_size = I40E_AQ_BUF_SZ;
 569
 570         err = i40evf_execute_vf_cmd(dev, &args);
 571         if (err)
 572                 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_PVID");
 573
 574         return err;
 575 }
 576
 577 static void
 578 i40evf_fill_virtchnl_vsi_txq_info(struct i40e_virtchnl_txq_info *txq_info,
 579                                   uint16_t vsi_id,
 580                                   uint16_t queue_id,
 581                                   uint16_t nb_txq,
 582                                   struct i40e_tx_queue *txq)
 583 {
 584         txq_info->vsi_id = vsi_id;
 585         txq_info->queue_id = queue_id;
 586         if (queue_id < nb_txq) {
 587                 txq_info->ring_len = txq->nb_tx_desc;
 588                 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
 589         }
 590 }
 591
 592 static void
 593 i40evf_fill_virtchnl_vsi_rxq_info(struct i40e_virtchnl_rxq_info *rxq_info,
 594                                   uint16_t vsi_id,
 595                                   uint16_t queue_id,
 596                                   uint16_t nb_rxq,
 597                                   uint32_t max_pkt_size,
 598                                   struct i40e_rx_queue *rxq)
 599 {
 600         rxq_info->vsi_id = vsi_id;
 601         rxq_info->queue_id = queue_id;
 602         rxq_info->max_pkt_size = max_pkt_size;
 603         if (queue_id < nb_rxq) {
 604                 rxq_info->ring_len = rxq->nb_rx_desc;
 605                 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
 606                 rxq_info->databuffer_size =
 607                         (rte_pktmbuf_data_room_size(rxq->mp) -
 608                                 RTE_PKTMBUF_HEADROOM);
 609         }
 610 }
 611
 612 /* It configures VSI queues to co-work with Linux PF host */
 613 static int
 614 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
 615 {
 616         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 617         struct i40e_rx_queue **rxq =
 618                 (struct i40e_rx_queue **)dev->data->rx_queues;
 619         struct i40e_tx_queue **txq =
 620                 (struct i40e_tx_queue **)dev->data->tx_queues;
 621         struct i40e_virtchnl_vsi_queue_config_info *vc_vqci;
 622         struct i40e_virtchnl_queue_pair_info *vc_qpi;
 623         struct vf_cmd_info args;
 624         uint16_t i, nb_qp = vf->num_queue_pairs;
 625         const uint32_t size =
 626                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
 627         uint8_t buff[size];
 628         int ret;
 629
 630         memset(buff, 0, sizeof(buff));
 631         vc_vqci = (struct i40e_virtchnl_vsi_queue_config_info *)buff;
 632         vc_vqci->vsi_id = vf->vsi_res->vsi_id;
 633         vc_vqci->num_queue_pairs = nb_qp;
 634
 635         for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
 636                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
 637                         vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 638                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
 639                         vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
 640                                         vf->max_pkt_len, rxq[i]);
 641         }
 642         memset(&args, 0, sizeof(args));
 643         args.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES;
 644         args.in_args = (uint8_t *)vc_vqci;
 645         args.in_args_size = size;
 646         args.out_buffer = vf->aq_resp;
 647         args.out_size = I40E_AQ_BUF_SZ;
 648         ret = i40evf_execute_vf_cmd(dev, &args);
 649         if (ret)
 650                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 651                         "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES");
 652
 653         return ret;
 654 }
 655
 656 /* It configures VSI queues to co-work with DPDK PF host */
 657 static int
 658 i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)
 659 {
 660         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 661         struct i40e_rx_queue **rxq =
 662                 (struct i40e_rx_queue **)dev->data->rx_queues;
 663         struct i40e_tx_queue **txq =
 664                 (struct i40e_tx_queue **)dev->data->tx_queues;
 665         struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei;
 666         struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
 667         struct vf_cmd_info args;
 668         uint16_t i, nb_qp = vf->num_queue_pairs;
 669         const uint32_t size =
 670                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);
 671         uint8_t buff[size];
 672         int ret;
 673
 674         memset(buff, 0, sizeof(buff));
 675         vc_vqcei = (struct i40e_virtchnl_vsi_queue_config_ext_info *)buff;
 676         vc_vqcei->vsi_id = vf->vsi_res->vsi_id;
 677         vc_vqcei->num_queue_pairs = nb_qp;
 678         vc_qpei = vc_vqcei->qpair;
 679         for (i = 0; i < nb_qp; i++, vc_qpei++) {
 680                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,
 681                         vc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 682                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,
 683                         vc_vqcei->vsi_id, i, dev->data->nb_rx_queues,
 684                                         vf->max_pkt_len, rxq[i]);
 685                 if (i < dev->data->nb_rx_queues)
 686                         /*
 687                          * It adds extra info for configuring VSI queues, which
 688                          * is needed to enable the configurable crc stripping
 689                          * in VF.
 690                          */
 691                         vc_qpei->rxq_ext.crcstrip =
 692                                 dev->data->dev_conf.rxmode.hw_strip_crc;
 693         }
 694         memset(&args, 0, sizeof(args));
 695         args.ops =
 696                 (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;
 697         args.in_args = (uint8_t *)vc_vqcei;
 698         args.in_args_size = size;
 699         args.out_buffer = vf->aq_resp;
 700         args.out_size = I40E_AQ_BUF_SZ;
 701         ret = i40evf_execute_vf_cmd(dev, &args);
 702         if (ret)
 703                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 704                         "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT");
 705
 706         return ret;
 707 }
 708
 709 static int
 710 i40evf_configure_queues(struct rte_eth_dev *dev)
 711 {
 712         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 713
 714         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 715                 /* To support DPDK PF host */
 716                 return i40evf_configure_vsi_queues_ext(dev);
 717         else
 718                 /* To support Linux PF host */
 719                 return i40evf_configure_vsi_queues(dev);
 720 }
 721
 722 static int
 723 i40evf_config_irq_map(struct rte_eth_dev *dev)
 724 {
 725         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 726         struct vf_cmd_info args;
 727         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \
 728                 sizeof(struct i40e_virtchnl_vector_map)];
 729         struct i40e_virtchnl_irq_map_info *map_info;
 730         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 731         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 732         uint32_t vector_id;
 733         int i, err;
 734
 735         if (rte_intr_allow_others(intr_handle)) {
 736                 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 737                         vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;
 738                 else
 739                         vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
 740         } else {
 741                 vector_id = I40E_MISC_VEC_ID;
 742         }
 743
 744         map_info = (struct i40e_virtchnl_irq_map_info *)cmd_buffer;
 745         map_info->num_vectors = 1;
 746         map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
 747         map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
 748         /* Alway use default dynamic MSIX interrupt */
 749         map_info->vecmap[0].vector_id = vector_id;
 750         /* Don't map any tx queue */
 751         map_info->vecmap[0].txq_map = 0;
 752         map_info->vecmap[0].rxq_map = 0;
 753         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 754                 map_info->vecmap[0].rxq_map |= 1 << i;
 755                 if (rte_intr_dp_is_en(intr_handle))
 756                         intr_handle->intr_vec[i] = vector_id;
 757         }
 758
 759         args.ops = I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP;
 760         args.in_args = (u8 *)cmd_buffer;
 761         args.in_args_size = sizeof(cmd_buffer);
 762         args.out_buffer = vf->aq_resp;
 763         args.out_size = I40E_AQ_BUF_SZ;
 764         err = i40evf_execute_vf_cmd(dev, &args);
 765         if (err)
 766                 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
 767
 768         return err;
 769 }
 770
 771 static int
 772 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
 773                                 bool on)
 774 {
 775         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 776         struct i40e_virtchnl_queue_select queue_select;
 777         int err;
 778         struct vf_cmd_info args;
 779         memset(&queue_select, 0, sizeof(queue_select));
 780         queue_select.vsi_id = vf->vsi_res->vsi_id;
 781
 782         if (isrx)
 783                 queue_select.rx_queues |= 1 << qid;
 784         else
 785                 queue_select.tx_queues |= 1 << qid;
 786
 787         if (on)
 788                 args.ops = I40E_VIRTCHNL_OP_ENABLE_QUEUES;
 789         else
 790                 args.ops = I40E_VIRTCHNL_OP_DISABLE_QUEUES;
 791         args.in_args = (u8 *)&queue_select;
 792         args.in_args_size = sizeof(queue_select);
 793         args.out_buffer = vf->aq_resp;
 794         args.out_size = I40E_AQ_BUF_SZ;
 795         err = i40evf_execute_vf_cmd(dev, &args);
 796         if (err)
 797                 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
 798                             isrx ? "RX" : "TX", qid, on ? "on" : "off");
 799
 800         return err;
 801 }
 802
 803 static int
 804 i40evf_start_queues(struct rte_eth_dev *dev)
 805 {
 806         struct rte_eth_dev_data *dev_data = dev->data;
 807         int i;
 808         struct i40e_rx_queue *rxq;
 809         struct i40e_tx_queue *txq;
 810
 811         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 812                 rxq = dev_data->rx_queues[i];
 813                 if (rxq->rx_deferred_start)
 814                         continue;
 815                 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
 816                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 817                         return -1;
 818                 }
 819         }
 820
 821         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 822                 txq = dev_data->tx_queues[i];
 823                 if (txq->tx_deferred_start)
 824                         continue;
 825                 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
 826                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 827                         return -1;
 828                 }
 829         }
 830
 831         return 0;
 832 }
 833
 834 static int
 835 i40evf_stop_queues(struct rte_eth_dev *dev)
 836 {
 837         int i;
 838
 839         /* Stop TX queues first */
 840         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 841                 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
 842                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 843                         return -1;
 844                 }
 845         }
 846
 847         /* Then stop RX queues */
 848         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 849                 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
 850                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 851                         return -1;
 852                 }
 853         }
 854
 855         return 0;
 856 }
 857
 858 static int
 859 i40evf_add_mac_addr(struct rte_eth_dev *dev,
 860                     struct ether_addr *addr,
 861                     __rte_unused uint32_t index,
 862                     __rte_unused uint32_t pool)
 863 {
 864         struct i40e_virtchnl_ether_addr_list *list;
 865         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 866         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
 867                         sizeof(struct i40e_virtchnl_ether_addr)];
 868         int err;
 869         struct vf_cmd_info args;
 870
 871         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 872                 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
 873                             addr->addr_bytes[0], addr->addr_bytes[1],
 874                             addr->addr_bytes[2], addr->addr_bytes[3],
 875                             addr->addr_bytes[4], addr->addr_bytes[5]);
 876                 return I40E_ERR_INVALID_MAC_ADDR;
 877         }
 878
 879         list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
 880         list->vsi_id = vf->vsi_res->vsi_id;
 881         list->num_elements = 1;
 882         (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
 883                                         sizeof(addr->addr_bytes));
 884
 885         args.ops = I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS;
 886         args.in_args = cmd_buffer;
 887         args.in_args_size = sizeof(cmd_buffer);
 888         args.out_buffer = vf->aq_resp;
 889         args.out_size = I40E_AQ_BUF_SZ;
 890         err = i40evf_execute_vf_cmd(dev, &args);
 891         if (err)
 892                 PMD_DRV_LOG(ERR, "fail to execute command "
 893                             "OP_ADD_ETHER_ADDRESS");
 894
 895         return err;
 896 }
 897
 898 static void
 899 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
 900                             struct ether_addr *addr)
 901 {
 902         struct i40e_virtchnl_ether_addr_list *list;
 903         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 904         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
 905                         sizeof(struct i40e_virtchnl_ether_addr)];
 906         int err;
 907         struct vf_cmd_info args;
 908
 909         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 910                 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
 911                             addr->addr_bytes[0], addr->addr_bytes[1],
 912                             addr->addr_bytes[2], addr->addr_bytes[3],
 913                             addr->addr_bytes[4], addr->addr_bytes[5]);
 914                 return;
 915         }
 916
 917         list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
 918         list->vsi_id = vf->vsi_res->vsi_id;
 919         list->num_elements = 1;
 920         (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
 921                         sizeof(addr->addr_bytes));
 922
 923         args.ops = I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
 924         args.in_args = cmd_buffer;
 925         args.in_args_size = sizeof(cmd_buffer);
 926         args.out_buffer = vf->aq_resp;
 927         args.out_size = I40E_AQ_BUF_SZ;
 928         err = i40evf_execute_vf_cmd(dev, &args);
 929         if (err)
 930                 PMD_DRV_LOG(ERR, "fail to execute command "
 931                             "OP_DEL_ETHER_ADDRESS");
 932         return;
 933 }
 934
 935 static void
 936 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
 937 {
 938         struct rte_eth_dev_data *data = dev->data;
 939         struct ether_addr *addr;
 940
 941         addr = &data->mac_addrs[index];
 942
 943         i40evf_del_mac_addr_by_addr(dev, addr);
 944 }
 945
 946 static int
 947 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
 948 {
 949         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 950         struct i40e_virtchnl_queue_select q_stats;
 951         int err;
 952         struct vf_cmd_info args;
 953
 954         memset(&q_stats, 0, sizeof(q_stats));
 955         q_stats.vsi_id = vf->vsi_res->vsi_id;
 956         args.ops = I40E_VIRTCHNL_OP_GET_STATS;
 957         args.in_args = (u8 *)&q_stats;
 958         args.in_args_size = sizeof(q_stats);
 959         args.out_buffer = vf->aq_resp;
 960         args.out_size = I40E_AQ_BUF_SZ;
 961
 962         err = i40evf_execute_vf_cmd(dev, &args);
 963         if (err) {
 964                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
 965                 *pstats = NULL;
 966                 return err;
 967         }
 968         *pstats = (struct i40e_eth_stats *)args.out_buffer;
 969         return 0;
 970 }
 971
 972 static int
 973 i40evf_get_statistics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 974 {
 975         int ret;
 976         struct i40e_eth_stats *pstats = NULL;
 977
 978         ret = i40evf_update_stats(dev, &pstats);
 979         if (ret != 0)
 980                 return 0;
 981
 982         stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
 983                                                 pstats->rx_broadcast;
 984         stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
 985                                                 pstats->tx_unicast;
 986         stats->imissed = pstats->rx_discards;
 987         stats->oerrors = pstats->tx_errors + pstats->tx_discards;
 988         stats->ibytes = pstats->rx_bytes;
 989         stats->obytes = pstats->tx_bytes;
 990
 991         return 0;
 992 }
 993
 994 static void
 995 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
 996 {
 997         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 998         struct i40e_eth_stats *pstats = NULL;
 999
1000         /* read stat values to clear hardware registers */
1001         i40evf_update_stats(dev, &pstats);
1002
1003         /* set stats offset base on current values */
1004         vf->vsi.eth_stats_offset = vf->vsi.eth_stats;
1005 }
1006
1007 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1008                                       struct rte_eth_xstat_name *xstats_names,
1009                                       __rte_unused unsigned limit)
1010 {
1011         unsigned i;
1012
1013         if (xstats_names != NULL)
1014                 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1015                         snprintf(xstats_names[i].name,
1016                                 sizeof(xstats_names[i].name),
1017                                 "%s", rte_i40evf_stats_strings[i].name);
1018                 }
1019         return I40EVF_NB_XSTATS;
1020 }
1021
1022 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1023                                  struct rte_eth_xstat *xstats, unsigned n)
1024 {
1025         int ret;
1026         unsigned i;
1027         struct i40e_eth_stats *pstats = NULL;
1028
1029         if (n < I40EVF_NB_XSTATS)
1030                 return I40EVF_NB_XSTATS;
1031
1032         ret = i40evf_update_stats(dev, &pstats);
1033         if (ret != 0)
1034                 return 0;
1035
1036         if (!xstats)
1037                 return 0;
1038
1039         /* loop over xstats array and values from pstats */
1040         for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1041                 xstats[i].id = i;
1042                 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1043                         rte_i40evf_stats_strings[i].offset);
1044         }
1045
1046         return I40EVF_NB_XSTATS;
1047 }
1048
1049 static int
1050 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1051 {
1052         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1053         struct i40e_virtchnl_vlan_filter_list *vlan_list;
1054         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1055                                                         sizeof(uint16_t)];
1056         int err;
1057         struct vf_cmd_info args;
1058
1059         vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1060         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1061         vlan_list->num_elements = 1;
1062         vlan_list->vlan_id[0] = vlanid;
1063
1064         args.ops = I40E_VIRTCHNL_OP_ADD_VLAN;
1065         args.in_args = (u8 *)&cmd_buffer;
1066         args.in_args_size = sizeof(cmd_buffer);
1067         args.out_buffer = vf->aq_resp;
1068         args.out_size = I40E_AQ_BUF_SZ;
1069         err = i40evf_execute_vf_cmd(dev, &args);
1070         if (err)
1071                 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1072
1073         return err;
1074 }
1075
1076 static int
1077 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1078 {
1079         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1080         struct i40e_virtchnl_vlan_filter_list *vlan_list;
1081         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1082                                                         sizeof(uint16_t)];
1083         int err;
1084         struct vf_cmd_info args;
1085
1086         vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1087         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1088         vlan_list->num_elements = 1;
1089         vlan_list->vlan_id[0] = vlanid;
1090
1091         args.ops = I40E_VIRTCHNL_OP_DEL_VLAN;
1092         args.in_args = (u8 *)&cmd_buffer;
1093         args.in_args_size = sizeof(cmd_buffer);
1094         args.out_buffer = vf->aq_resp;
1095         args.out_size = I40E_AQ_BUF_SZ;
1096         err = i40evf_execute_vf_cmd(dev, &args);
1097         if (err)
1098                 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1099
1100         return err;
1101 }
1102
1103 static const struct rte_pci_id pci_id_i40evf_map[] = {
1104         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1105         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1106         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1107         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1108         { .vendor_id = 0, /* sentinel */ },
1109 };
1110
1111 static inline int
1112 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1113                                     struct rte_eth_link *link)
1114 {
1115         struct rte_eth_link *dst = &(dev->data->dev_link);
1116         struct rte_eth_link *src = link;
1117
1118         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1119                                         *(uint64_t *)src) == 0)
1120                 return -1;
1121
1122         return 0;
1123 }
1124
1125 /* Disable IRQ0 */
1126 static inline void
1127 i40evf_disable_irq0(struct i40e_hw *hw)
1128 {
1129         /* Disable all interrupt types */
1130         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1131         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1132                        I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1133         I40EVF_WRITE_FLUSH(hw);
1134 }
1135
1136 /* Enable IRQ0 */
1137 static inline void
1138 i40evf_enable_irq0(struct i40e_hw *hw)
1139 {
1140         /* Enable admin queue interrupt trigger */
1141         uint32_t val;
1142
1143         i40evf_disable_irq0(hw);
1144         val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1145         val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1146                 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1147         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1148
1149         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1150                 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1151                 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1152                 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1153
1154         I40EVF_WRITE_FLUSH(hw);
1155 }
1156
1157 static int
1158 i40evf_reset_vf(struct i40e_hw *hw)
1159 {
1160         int i, reset;
1161
1162         if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1163                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1164                 return -1;
1165         }
1166         /**
1167           * After issuing vf reset command to pf, pf won't necessarily
1168           * reset vf, it depends on what state it exactly is. If it's not
1169           * initialized yet, it won't have vf reset since it's in a certain
1170           * state. If not, it will try to reset. Even vf is reset, pf will
1171           * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1172           * it to ACTIVE. In this duration, vf may not catch the moment that
1173           * COMPLETE is set. So, for vf, we'll try to wait a long time.
1174           */
1175         rte_delay_ms(200);
1176
1177         for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1178                 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1179                         I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1180                 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1181                 if (I40E_VFR_COMPLETED == reset || I40E_VFR_VFACTIVE == reset)
1182                         break;
1183                 else
1184                         rte_delay_ms(50);
1185         }
1186
1187         if (i >= MAX_RESET_WAIT_CNT) {
1188                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1189                 return -1;
1190         }
1191
1192         return 0;
1193 }
1194
1195 static int
1196 i40evf_init_vf(struct rte_eth_dev *dev)
1197 {
1198         int i, err, bufsz;
1199         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1200         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1201         uint16_t interval =
1202                 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1203
1204         vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1205         vf->dev_data = dev->data;
1206         err = i40e_set_mac_type(hw);
1207         if (err) {
1208                 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1209                 goto err;
1210         }
1211
1212         i40e_init_adminq_parameter(hw);
1213         err = i40e_init_adminq(hw);
1214         if (err) {
1215                 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1216                 goto err;
1217         }
1218
1219         /* Reset VF and wait until it's complete */
1220         if (i40evf_reset_vf(hw)) {
1221                 PMD_INIT_LOG(ERR, "reset NIC failed");
1222                 goto err_aq;
1223         }
1224
1225         /* VF reset, shutdown admin queue and initialize again */
1226         if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1227                 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1228                 return -1;
1229         }
1230
1231         i40e_init_adminq_parameter(hw);
1232         if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1233                 PMD_INIT_LOG(ERR, "init_adminq failed");
1234                 return -1;
1235         }
1236         vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1237         if (!vf->aq_resp) {
1238                 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1239                         goto err_aq;
1240         }
1241         if (i40evf_check_api_version(dev) != 0) {
1242                 PMD_INIT_LOG(ERR, "check_api version failed");
1243                 goto err_aq;
1244         }
1245         bufsz = sizeof(struct i40e_virtchnl_vf_resource) +
1246                 (I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource));
1247         vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1248         if (!vf->vf_res) {
1249                 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1250                         goto err_aq;
1251         }
1252
1253         if (i40evf_get_vf_resource(dev) != 0) {
1254                 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1255                 goto err_alloc;
1256         }
1257
1258         /* got VF config message back from PF, now we can parse it */
1259         for (i = 0; i < vf->vf_res->num_vsis; i++) {
1260                 if (vf->vf_res->vsi_res[i].vsi_type == I40E_VSI_SRIOV)
1261                         vf->vsi_res = &vf->vf_res->vsi_res[i];
1262         }
1263
1264         if (!vf->vsi_res) {
1265                 PMD_INIT_LOG(ERR, "no LAN VSI found");
1266                 goto err_alloc;
1267         }
1268
1269         if (hw->mac.type == I40E_MAC_X722_VF)
1270                 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1271         vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1272         vf->vsi.type = vf->vsi_res->vsi_type;
1273         vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1274         vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1275
1276         /* Store the MAC address configured by host, or generate random one */
1277         if (is_valid_assigned_ether_addr((struct ether_addr *)hw->mac.addr))
1278                 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1279         else
1280                 eth_random_addr(hw->mac.addr); /* Generate a random one */
1281
1282         /* If the PF host is not DPDK, set the interval of ITR0 to max*/
1283         if (vf->version_major != I40E_DPDK_VERSION_MAJOR) {
1284                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1285                                (I40E_ITR_INDEX_DEFAULT <<
1286                                 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1287                                (interval <<
1288                                 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1289                 I40EVF_WRITE_FLUSH(hw);
1290         }
1291
1292         return 0;
1293
1294 err_alloc:
1295         rte_free(vf->vf_res);
1296 err_aq:
1297         i40e_shutdown_adminq(hw); /* ignore error */
1298 err:
1299         return -1;
1300 }
1301
1302 static int
1303 i40evf_uninit_vf(struct rte_eth_dev *dev)
1304 {
1305         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1306         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1307
1308         PMD_INIT_FUNC_TRACE();
1309
1310         if (hw->adapter_stopped == 0)
1311                 i40evf_dev_close(dev);
1312         rte_free(vf->vf_res);
1313         vf->vf_res = NULL;
1314         rte_free(vf->aq_resp);
1315         vf->aq_resp = NULL;
1316
1317         return 0;
1318 }
1319
1320 static void
1321 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1322                 __rte_unused uint16_t msglen)
1323 {
1324         struct i40e_virtchnl_pf_event *pf_msg =
1325                         (struct i40e_virtchnl_pf_event *)msg;
1326         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1327
1328         switch (pf_msg->event) {
1329         case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
1330                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1331                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
1332                 break;
1333         case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
1334                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1335                 vf->link_up = pf_msg->event_data.link_event.link_status;
1336                 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1337                 break;
1338         case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1339                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1340                 break;
1341         default:
1342                 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1343                 break;
1344         }
1345 }
1346
1347 static void
1348 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1349 {
1350         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1351         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1352         struct i40e_arq_event_info info;
1353         uint16_t pending, aq_opc;
1354         enum i40e_virtchnl_ops msg_opc;
1355         enum i40e_status_code msg_ret;
1356         int ret;
1357
1358         info.buf_len = I40E_AQ_BUF_SZ;
1359         if (!vf->aq_resp) {
1360                 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1361                 return;
1362         }
1363         info.msg_buf = vf->aq_resp;
1364
1365         pending = 1;
1366         while (pending) {
1367                 ret = i40e_clean_arq_element(hw, &info, &pending);
1368
1369                 if (ret != I40E_SUCCESS) {
1370                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1371                                     "ret: %d", ret);
1372                         break;
1373                 }
1374                 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1375                 /* For the message sent from pf to vf, opcode is stored in
1376                  * cookie_high of struct i40e_aq_desc, while return error code
1377                  * are stored in cookie_low, Which is done by
1378                  * i40e_aq_send_msg_to_vf in PF driver.*/
1379                 msg_opc = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(
1380                                                   info.desc.cookie_high);
1381                 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1382                                                   info.desc.cookie_low);
1383                 switch (aq_opc) {
1384                 case i40e_aqc_opc_send_msg_to_vf:
1385                         if (msg_opc == I40E_VIRTCHNL_OP_EVENT)
1386                                 /* process event*/
1387                                 i40evf_handle_pf_event(dev, info.msg_buf,
1388                                                        info.msg_len);
1389                         else {
1390                                 /* read message and it's expected one */
1391                                 if (msg_opc == vf->pend_cmd) {
1392                                         vf->cmd_retval = msg_ret;
1393                                         /* prevent compiler reordering */
1394                                         rte_compiler_barrier();
1395                                         _clear_cmd(vf);
1396                                 } else
1397                                         PMD_DRV_LOG(ERR, "command mismatch,"
1398                                                 "expect %u, get %u",
1399                                                 vf->pend_cmd, msg_opc);
1400                                 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1401                                              " opcode = %d", msg_opc);
1402                         }
1403                         break;
1404                 default:
1405                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1406                                     aq_opc);
1407                         break;
1408                 }
1409         }
1410 }
1411
1412 /**
1413  * Interrupt handler triggered by NIC  for handling
1414  * specific interrupt. Only adminq interrupt is processed in VF.
1415  *
1416  * @param handle
1417  *  Pointer to interrupt handle.
1418  * @param param
1419  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1420  *
1421  * @return
1422  *  void
1423  */
1424 static void
1425 i40evf_dev_interrupt_handler(void *param)
1426 {
1427         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1428         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1429         uint32_t icr0;
1430
1431         i40evf_disable_irq0(hw);
1432
1433         /* read out interrupt causes */
1434         icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1435
1436         /* No interrupt event indicated */
1437         if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1438                 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do");
1439                 goto done;
1440         }
1441
1442         if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1443                 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1444                 i40evf_handle_aq_msg(dev);
1445         }
1446
1447         /* Link Status Change interrupt */
1448         if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1449                 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1450                                    " do nothing");
1451
1452 done:
1453         i40evf_enable_irq0(hw);
1454         rte_intr_enable(dev->intr_handle);
1455 }
1456
1457 static int
1458 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1459 {
1460         struct i40e_hw *hw
1461                 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1462         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1463
1464         PMD_INIT_FUNC_TRACE();
1465
1466         /* assign ops func pointer */
1467         eth_dev->dev_ops = &i40evf_eth_dev_ops;
1468         eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1469         eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1470
1471         /*
1472          * For secondary processes, we don't initialise any further as primary
1473          * has already done this work.
1474          */
1475         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1476                 i40e_set_rx_function(eth_dev);
1477                 i40e_set_tx_function(eth_dev);
1478                 return 0;
1479         }
1480         i40e_set_default_ptype_table(eth_dev);
1481         rte_eth_copy_pci_info(eth_dev, pci_dev);
1482         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1483
1484         hw->vendor_id = pci_dev->id.vendor_id;
1485         hw->device_id = pci_dev->id.device_id;
1486         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1487         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1488         hw->bus.device = pci_dev->addr.devid;
1489         hw->bus.func = pci_dev->addr.function;
1490         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1491         hw->adapter_stopped = 0;
1492
1493         if(i40evf_init_vf(eth_dev) != 0) {
1494                 PMD_INIT_LOG(ERR, "Init vf failed");
1495                 return -1;
1496         }
1497
1498         /* register callback func to eal lib */
1499         rte_intr_callback_register(&pci_dev->intr_handle,
1500                 i40evf_dev_interrupt_handler, (void *)eth_dev);
1501
1502         /* enable uio intr after callback register */
1503         rte_intr_enable(&pci_dev->intr_handle);
1504
1505         /* configure and enable device interrupt */
1506         i40evf_enable_irq0(hw);
1507
1508         /* copy mac addr */
1509         eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1510                                         ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1511                                         0);
1512         if (eth_dev->data->mac_addrs == NULL) {
1513                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1514                                 " store MAC addresses",
1515                                 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1516                 return -ENOMEM;
1517         }
1518         ether_addr_copy((struct ether_addr *)hw->mac.addr,
1519                         &eth_dev->data->mac_addrs[0]);
1520
1521         return 0;
1522 }
1523
1524 static int
1525 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1526 {
1527         PMD_INIT_FUNC_TRACE();
1528
1529         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1530                 return -EPERM;
1531
1532         eth_dev->dev_ops = NULL;
1533         eth_dev->rx_pkt_burst = NULL;
1534         eth_dev->tx_pkt_burst = NULL;
1535
1536         if (i40evf_uninit_vf(eth_dev) != 0) {
1537                 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1538                 return -1;
1539         }
1540
1541         rte_free(eth_dev->data->mac_addrs);
1542         eth_dev->data->mac_addrs = NULL;
1543
1544         return 0;
1545 }
1546
1547 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1548         struct rte_pci_device *pci_dev)
1549 {
1550         return rte_eth_dev_pci_generic_probe(pci_dev,
1551                 sizeof(struct i40e_adapter), i40evf_dev_init);
1552 }
1553
1554 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1555 {
1556         return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1557 }
1558
1559 /*
1560  * virtual function driver struct
1561  */
1562 static struct rte_pci_driver rte_i40evf_pmd = {
1563         .id_table = pci_id_i40evf_map,
1564         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1565         .probe = eth_i40evf_pci_probe,
1566         .remove = eth_i40evf_pci_remove,
1567 };
1568
1569 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1570 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1571 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1572
1573 static int
1574 i40evf_dev_configure(struct rte_eth_dev *dev)
1575 {
1576         struct i40e_adapter *ad =
1577                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1578         struct rte_eth_conf *conf = &dev->data->dev_conf;
1579         struct i40e_vf *vf;
1580
1581         /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1582          * allocation or vector Rx preconditions we will reset it.
1583          */
1584         ad->rx_bulk_alloc_allowed = true;
1585         ad->rx_vec_allowed = true;
1586         ad->tx_simple_allowed = true;
1587         ad->tx_vec_allowed = true;
1588
1589         /* For non-DPDK PF drivers, VF has no ability to disable HW
1590          * CRC strip, and is implicitly enabled by the PF.
1591          */
1592         if (!conf->rxmode.hw_strip_crc) {
1593                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1594                 if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
1595                     (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR)) {
1596                         /* Peer is running non-DPDK PF driver. */
1597                         PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1598                         return -EINVAL;
1599                 }
1600         }
1601
1602         return i40evf_init_vlan(dev);
1603 }
1604
1605 static int
1606 i40evf_init_vlan(struct rte_eth_dev *dev)
1607 {
1608         struct rte_eth_dev_data *data = dev->data;
1609         int ret;
1610
1611         /* Apply vlan offload setting */
1612         i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1613
1614         /* Apply pvid setting */
1615         ret = i40evf_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
1616                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
1617         return ret;
1618 }
1619
1620 static void
1621 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1622 {
1623         bool enable_vlan_strip = 0;
1624         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1625         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1626
1627         /* Linux pf host doesn't support vlan offload yet */
1628         if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1629                 /* Vlan stripping setting */
1630                 if (mask & ETH_VLAN_STRIP_MASK) {
1631                         /* Enable or disable VLAN stripping */
1632                         if (dev_conf->rxmode.hw_vlan_strip)
1633                                 enable_vlan_strip = 1;
1634                         else
1635                                 enable_vlan_strip = 0;
1636
1637                         i40evf_config_vlan_offload(dev, enable_vlan_strip);
1638                 }
1639         }
1640 }
1641
1642 static int
1643 i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1644 {
1645         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1646         struct i40e_vsi_vlan_pvid_info info;
1647         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1648
1649         memset(&info, 0, sizeof(info));
1650         info.on = on;
1651
1652         /* Linux pf host don't support vlan offload yet */
1653         if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1654                 if (info.on)
1655                         info.config.pvid = pvid;
1656                 else {
1657                         info.config.reject.tagged =
1658                                 dev_conf->txmode.hw_vlan_reject_tagged;
1659                         info.config.reject.untagged =
1660                                 dev_conf->txmode.hw_vlan_reject_untagged;
1661                 }
1662                 return i40evf_config_vlan_pvid(dev, &info);
1663         }
1664
1665         return 0;
1666 }
1667
1668 static int
1669 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1670 {
1671         struct i40e_rx_queue *rxq;
1672         int err = 0;
1673         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1674
1675         PMD_INIT_FUNC_TRACE();
1676
1677         if (rx_queue_id < dev->data->nb_rx_queues) {
1678                 rxq = dev->data->rx_queues[rx_queue_id];
1679
1680                 err = i40e_alloc_rx_queue_mbufs(rxq);
1681                 if (err) {
1682                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1683                         return err;
1684                 }
1685
1686                 rte_wmb();
1687
1688                 /* Init the RX tail register. */
1689                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1690                 I40EVF_WRITE_FLUSH(hw);
1691
1692                 /* Ready to switch the queue on */
1693                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1694
1695                 if (err)
1696                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1697                                     rx_queue_id);
1698                 else
1699                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1700         }
1701
1702         return err;
1703 }
1704
1705 static int
1706 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1707 {
1708         struct i40e_rx_queue *rxq;
1709         int err;
1710
1711         if (rx_queue_id < dev->data->nb_rx_queues) {
1712                 rxq = dev->data->rx_queues[rx_queue_id];
1713
1714                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1715
1716                 if (err) {
1717                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1718                                     rx_queue_id);
1719                         return err;
1720                 }
1721
1722                 i40e_rx_queue_release_mbufs(rxq);
1723                 i40e_reset_rx_queue(rxq);
1724                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1725         }
1726
1727         return 0;
1728 }
1729
1730 static int
1731 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1732 {
1733         int err = 0;
1734
1735         PMD_INIT_FUNC_TRACE();
1736
1737         if (tx_queue_id < dev->data->nb_tx_queues) {
1738
1739                 /* Ready to switch the queue on */
1740                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1741
1742                 if (err)
1743                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1744                                     tx_queue_id);
1745                 else
1746                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1747         }
1748
1749         return err;
1750 }
1751
1752 static int
1753 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1754 {
1755         struct i40e_tx_queue *txq;
1756         int err;
1757
1758         if (tx_queue_id < dev->data->nb_tx_queues) {
1759                 txq = dev->data->tx_queues[tx_queue_id];
1760
1761                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1762
1763                 if (err) {
1764                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1765                                     tx_queue_id);
1766                         return err;
1767                 }
1768
1769                 i40e_tx_queue_release_mbufs(txq);
1770                 i40e_reset_tx_queue(txq);
1771                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1772         }
1773
1774         return 0;
1775 }
1776
1777 static int
1778 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1779 {
1780         int ret;
1781
1782         if (on)
1783                 ret = i40evf_add_vlan(dev, vlan_id);
1784         else
1785                 ret = i40evf_del_vlan(dev,vlan_id);
1786
1787         return ret;
1788 }
1789
1790 static int
1791 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1792 {
1793         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1794         struct rte_eth_dev_data *dev_data = dev->data;
1795         struct rte_pktmbuf_pool_private *mbp_priv;
1796         uint16_t buf_size, len;
1797
1798         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1799         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1800         I40EVF_WRITE_FLUSH(hw);
1801
1802         /* Calculate the maximum packet length allowed */
1803         mbp_priv = rte_mempool_get_priv(rxq->mp);
1804         buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1805                                         RTE_PKTMBUF_HEADROOM);
1806         rxq->hs_mode = i40e_header_split_none;
1807         rxq->rx_hdr_len = 0;
1808         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1809         len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1810         rxq->max_pkt_len = RTE_MIN(len,
1811                 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1812
1813         /**
1814          * Check if the jumbo frame and maximum packet length are set correctly
1815          */
1816         if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1817                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1818                     rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1819                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1820                                 "larger than %u and smaller than %u, as jumbo "
1821                                 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1822                                         (uint32_t)I40E_FRAME_SIZE_MAX);
1823                         return I40E_ERR_CONFIG;
1824                 }
1825         } else {
1826                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1827                     rxq->max_pkt_len > ETHER_MAX_LEN) {
1828                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1829                                 "larger than %u and smaller than %u, as jumbo "
1830                                 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1831                                                 (uint32_t)ETHER_MAX_LEN);
1832                         return I40E_ERR_CONFIG;
1833                 }
1834         }
1835
1836         if (dev_data->dev_conf.rxmode.enable_scatter ||
1837             (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1838                 dev_data->scattered_rx = 1;
1839         }
1840
1841         return 0;
1842 }
1843
1844 static int
1845 i40evf_rx_init(struct rte_eth_dev *dev)
1846 {
1847         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1848         uint16_t i;
1849         int ret = I40E_SUCCESS;
1850         struct i40e_rx_queue **rxq =
1851                 (struct i40e_rx_queue **)dev->data->rx_queues;
1852
1853         i40evf_config_rss(vf);
1854         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1855                 if (!rxq[i] || !rxq[i]->q_set)
1856                         continue;
1857                 ret = i40evf_rxq_init(dev, rxq[i]);
1858                 if (ret != I40E_SUCCESS)
1859                         break;
1860         }
1861         if (ret == I40E_SUCCESS)
1862                 i40e_set_rx_function(dev);
1863
1864         return ret;
1865 }
1866
1867 static void
1868 i40evf_tx_init(struct rte_eth_dev *dev)
1869 {
1870         uint16_t i;
1871         struct i40e_tx_queue **txq =
1872                 (struct i40e_tx_queue **)dev->data->tx_queues;
1873         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1874
1875         for (i = 0; i < dev->data->nb_tx_queues; i++)
1876                 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1877
1878         i40e_set_tx_function(dev);
1879 }
1880
1881 static inline void
1882 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1883 {
1884         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1885         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1886         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1887         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1888
1889         if (!rte_intr_allow_others(intr_handle)) {
1890                 I40E_WRITE_REG(hw,
1891                                I40E_VFINT_DYN_CTL01,
1892                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1893                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1894                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1895                 I40EVF_WRITE_FLUSH(hw);
1896                 return;
1897         }
1898
1899         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1900                 /* To support DPDK PF host */
1901                 I40E_WRITE_REG(hw,
1902                         I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1903                         I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1904                         I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1905         /* If host driver is kernel driver, do nothing.
1906          * Interrupt 0 is used for rx packets, but don't set
1907          * I40E_VFINT_DYN_CTL01,
1908          * because it is already done in i40evf_enable_irq0.
1909          */
1910
1911         I40EVF_WRITE_FLUSH(hw);
1912 }
1913
1914 static inline void
1915 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1916 {
1917         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1918         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1919         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1920         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1921
1922         if (!rte_intr_allow_others(intr_handle)) {
1923                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1924                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1925                 I40EVF_WRITE_FLUSH(hw);
1926                 return;
1927         }
1928
1929         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1930                 I40E_WRITE_REG(hw,
1931                                I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR
1932                                                     - 1),
1933                                0);
1934         /* If host driver is kernel driver, do nothing.
1935          * Interrupt 0 is used for rx packets, but don't zero
1936          * I40E_VFINT_DYN_CTL01,
1937          * because interrupt 0 is also used for adminq processing.
1938          */
1939
1940         I40EVF_WRITE_FLUSH(hw);
1941 }
1942
1943 static int
1944 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1945 {
1946         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1947         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1948         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1949         uint16_t interval =
1950                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1951         uint16_t msix_intr;
1952
1953         msix_intr = intr_handle->intr_vec[queue_id];
1954         if (msix_intr == I40E_MISC_VEC_ID)
1955                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1956                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1957                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1958                                (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1959                                (interval <<
1960                                 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1961         else
1962                 I40E_WRITE_REG(hw,
1963                                I40E_VFINT_DYN_CTLN1(msix_intr -
1964                                                     I40E_RX_VEC_START),
1965                                I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1966                                I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1967                                (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1968                                (interval <<
1969                                 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1970
1971         I40EVF_WRITE_FLUSH(hw);
1972
1973         rte_intr_enable(&pci_dev->intr_handle);
1974
1975         return 0;
1976 }
1977
1978 static int
1979 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1980 {
1981         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1982         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1983         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1984         uint16_t msix_intr;
1985
1986         msix_intr = intr_handle->intr_vec[queue_id];
1987         if (msix_intr == I40E_MISC_VEC_ID)
1988                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1989         else
1990                 I40E_WRITE_REG(hw,
1991                                I40E_VFINT_DYN_CTLN1(msix_intr -
1992                                                     I40E_RX_VEC_START),
1993                                0);
1994
1995         I40EVF_WRITE_FLUSH(hw);
1996
1997         return 0;
1998 }
1999
2000 static void
2001 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
2002 {
2003         struct i40e_virtchnl_ether_addr_list *list;
2004         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2005         int err, i, j;
2006         int next_begin = 0;
2007         int begin = 0;
2008         uint32_t len;
2009         struct ether_addr *addr;
2010         struct vf_cmd_info args;
2011
2012         do {
2013                 j = 0;
2014                 len = sizeof(struct i40e_virtchnl_ether_addr_list);
2015                 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
2016                         if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
2017                                 continue;
2018                         len += sizeof(struct i40e_virtchnl_ether_addr);
2019                         if (len >= I40E_AQ_BUF_SZ) {
2020                                 next_begin = i + 1;
2021                                 break;
2022                         }
2023                 }
2024
2025                 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
2026                 if (!list) {
2027                         PMD_DRV_LOG(ERR, "fail to allocate memory");
2028                         return;
2029                 }
2030
2031                 for (i = begin; i < next_begin; i++) {
2032                         addr = &dev->data->mac_addrs[i];
2033                         if (is_zero_ether_addr(addr))
2034                                 continue;
2035                         (void)rte_memcpy(list->list[j].addr, addr->addr_bytes,
2036                                          sizeof(addr->addr_bytes));
2037                         PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
2038                                     addr->addr_bytes[0], addr->addr_bytes[1],
2039                                     addr->addr_bytes[2], addr->addr_bytes[3],
2040                                     addr->addr_bytes[4], addr->addr_bytes[5]);
2041                         j++;
2042                 }
2043                 list->vsi_id = vf->vsi_res->vsi_id;
2044                 list->num_elements = j;
2045                 args.ops = add ? I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS :
2046                            I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
2047                 args.in_args = (uint8_t *)list;
2048                 args.in_args_size = len;
2049                 args.out_buffer = vf->aq_resp;
2050                 args.out_size = I40E_AQ_BUF_SZ;
2051                 err = i40evf_execute_vf_cmd(dev, &args);
2052                 if (err)
2053                         PMD_DRV_LOG(ERR, "fail to execute command %s",
2054                                     add ? "OP_ADD_ETHER_ADDRESS" :
2055                                     "OP_DEL_ETHER_ADDRESS");
2056                 rte_free(list);
2057                 begin = next_begin;
2058         } while (begin < I40E_NUM_MACADDR_MAX);
2059 }
2060
2061 static int
2062 i40evf_dev_start(struct rte_eth_dev *dev)
2063 {
2064         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2065         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2066         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2067         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2068         uint32_t intr_vector = 0;
2069
2070         PMD_INIT_FUNC_TRACE();
2071
2072         hw->adapter_stopped = 0;
2073
2074         vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2075         vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2076                                         dev->data->nb_tx_queues);
2077
2078         /* check and configure queue intr-vector mapping */
2079         if (dev->data->dev_conf.intr_conf.rxq != 0) {
2080                 intr_vector = dev->data->nb_rx_queues;
2081                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2082                         return -1;
2083         }
2084
2085         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2086                 intr_handle->intr_vec =
2087                         rte_zmalloc("intr_vec",
2088                                     dev->data->nb_rx_queues * sizeof(int), 0);
2089                 if (!intr_handle->intr_vec) {
2090                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2091                                      " intr_vec", dev->data->nb_rx_queues);
2092                         return -ENOMEM;
2093                 }
2094         }
2095
2096         if (i40evf_rx_init(dev) != 0){
2097                 PMD_DRV_LOG(ERR, "failed to do RX init");
2098                 return -1;
2099         }
2100
2101         i40evf_tx_init(dev);
2102
2103         if (i40evf_configure_queues(dev) != 0) {
2104                 PMD_DRV_LOG(ERR, "configure queues failed");
2105                 goto err_queue;
2106         }
2107         if (i40evf_config_irq_map(dev)) {
2108                 PMD_DRV_LOG(ERR, "config_irq_map failed");
2109                 goto err_queue;
2110         }
2111
2112         /* Set all mac addrs */
2113         i40evf_add_del_all_mac_addr(dev, TRUE);
2114
2115         if (i40evf_start_queues(dev) != 0) {
2116                 PMD_DRV_LOG(ERR, "enable queues failed");
2117                 goto err_mac;
2118         }
2119
2120         i40evf_enable_queues_intr(dev);
2121         return 0;
2122
2123 err_mac:
2124         i40evf_add_del_all_mac_addr(dev, FALSE);
2125 err_queue:
2126         return -1;
2127 }
2128
2129 static void
2130 i40evf_dev_stop(struct rte_eth_dev *dev)
2131 {
2132         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2133         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2134
2135         PMD_INIT_FUNC_TRACE();
2136
2137         i40evf_stop_queues(dev);
2138         i40evf_disable_queues_intr(dev);
2139         i40e_dev_clear_queues(dev);
2140
2141         /* Clean datapath event and queue/vec mapping */
2142         rte_intr_efd_disable(intr_handle);
2143         if (intr_handle->intr_vec) {
2144                 rte_free(intr_handle->intr_vec);
2145                 intr_handle->intr_vec = NULL;
2146         }
2147         /* remove all mac addrs */
2148         i40evf_add_del_all_mac_addr(dev, FALSE);
2149
2150 }
2151
2152 static int
2153 i40evf_dev_link_update(struct rte_eth_dev *dev,
2154                        __rte_unused int wait_to_complete)
2155 {
2156         struct rte_eth_link new_link;
2157         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2158         /*
2159          * DPDK pf host provide interfacet to acquire link status
2160          * while Linux driver does not
2161          */
2162
2163         /* Linux driver PF host */
2164         switch (vf->link_speed) {
2165         case I40E_LINK_SPEED_100MB:
2166                 new_link.link_speed = ETH_SPEED_NUM_100M;
2167                 break;
2168         case I40E_LINK_SPEED_1GB:
2169                 new_link.link_speed = ETH_SPEED_NUM_1G;
2170                 break;
2171         case I40E_LINK_SPEED_10GB:
2172                 new_link.link_speed = ETH_SPEED_NUM_10G;
2173                 break;
2174         case I40E_LINK_SPEED_20GB:
2175                 new_link.link_speed = ETH_SPEED_NUM_20G;
2176                 break;
2177         case I40E_LINK_SPEED_25GB:
2178                 new_link.link_speed = ETH_SPEED_NUM_25G;
2179                 break;
2180         case I40E_LINK_SPEED_40GB:
2181                 new_link.link_speed = ETH_SPEED_NUM_40G;
2182                 break;
2183         default:
2184                 new_link.link_speed = ETH_SPEED_NUM_100M;
2185                 break;
2186         }
2187         /* full duplex only */
2188         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2189         new_link.link_status = vf->link_up ? ETH_LINK_UP :
2190                                              ETH_LINK_DOWN;
2191
2192         i40evf_dev_atomic_write_link_status(dev, &new_link);
2193
2194         return 0;
2195 }
2196
2197 static void
2198 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2199 {
2200         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2201         int ret;
2202
2203         /* If enabled, just return */
2204         if (vf->promisc_unicast_enabled)
2205                 return;
2206
2207         ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2208         if (ret == 0)
2209                 vf->promisc_unicast_enabled = TRUE;
2210 }
2211
2212 static void
2213 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2214 {
2215         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2216         int ret;
2217
2218         /* If disabled, just return */
2219         if (!vf->promisc_unicast_enabled)
2220                 return;
2221
2222         ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2223         if (ret == 0)
2224                 vf->promisc_unicast_enabled = FALSE;
2225 }
2226
2227 static void
2228 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2229 {
2230         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2231         int ret;
2232
2233         /* If enabled, just return */
2234         if (vf->promisc_multicast_enabled)
2235                 return;
2236
2237         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2238         if (ret == 0)
2239                 vf->promisc_multicast_enabled = TRUE;
2240 }
2241
2242 static void
2243 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2244 {
2245         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2246         int ret;
2247
2248         /* If enabled, just return */
2249         if (!vf->promisc_multicast_enabled)
2250                 return;
2251
2252         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2253         if (ret == 0)
2254                 vf->promisc_multicast_enabled = FALSE;
2255 }
2256
2257 static void
2258 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2259 {
2260         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2261
2262         memset(dev_info, 0, sizeof(*dev_info));
2263         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2264         dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2265         dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2266         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2267         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2268         dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2269         dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2270         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2271         dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2272         dev_info->rx_offload_capa =
2273                 DEV_RX_OFFLOAD_VLAN_STRIP |
2274                 DEV_RX_OFFLOAD_QINQ_STRIP |
2275                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2276                 DEV_RX_OFFLOAD_UDP_CKSUM |
2277                 DEV_RX_OFFLOAD_TCP_CKSUM;
2278         dev_info->tx_offload_capa =
2279                 DEV_TX_OFFLOAD_VLAN_INSERT |
2280                 DEV_TX_OFFLOAD_QINQ_INSERT |
2281                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2282                 DEV_TX_OFFLOAD_UDP_CKSUM |
2283                 DEV_TX_OFFLOAD_TCP_CKSUM |
2284                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2285
2286         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2287                 .rx_thresh = {
2288                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2289                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2290                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2291                 },
2292                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2293                 .rx_drop_en = 0,
2294         };
2295
2296         dev_info->default_txconf = (struct rte_eth_txconf) {
2297                 .tx_thresh = {
2298                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2299                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2300                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2301                 },
2302                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2303                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2304                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2305                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2306         };
2307
2308         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2309                 .nb_max = I40E_MAX_RING_DESC,
2310                 .nb_min = I40E_MIN_RING_DESC,
2311                 .nb_align = I40E_ALIGN_RING_DESC,
2312         };
2313
2314         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2315                 .nb_max = I40E_MAX_RING_DESC,
2316                 .nb_min = I40E_MIN_RING_DESC,
2317                 .nb_align = I40E_ALIGN_RING_DESC,
2318         };
2319 }
2320
2321 static void
2322 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2323 {
2324         if (i40evf_get_statistics(dev, stats))
2325                 PMD_DRV_LOG(ERR, "Get statistics failed");
2326 }
2327
2328 static void
2329 i40evf_dev_close(struct rte_eth_dev *dev)
2330 {
2331         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2332         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2333         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2334
2335         i40evf_dev_stop(dev);
2336         hw->adapter_stopped = 1;
2337         i40e_dev_free_queues(dev);
2338         i40evf_reset_vf(hw);
2339         i40e_shutdown_adminq(hw);
2340         /* disable uio intr before callback unregister */
2341         rte_intr_disable(intr_handle);
2342
2343         /* unregister callback func from eal lib */
2344         rte_intr_callback_unregister(intr_handle,
2345                                      i40evf_dev_interrupt_handler, dev);
2346         i40evf_disable_irq0(hw);
2347 }
2348
2349 static int
2350 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2351 {
2352         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2353         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2354         int ret;
2355
2356         if (!lut)
2357                 return -EINVAL;
2358
2359         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2360                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2361                                           lut, lut_size);
2362                 if (ret) {
2363                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2364                         return ret;
2365                 }
2366         } else {
2367                 uint32_t *lut_dw = (uint32_t *)lut;
2368                 uint16_t i, lut_size_dw = lut_size / 4;
2369
2370                 for (i = 0; i < lut_size_dw; i++)
2371                         lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2372         }
2373
2374         return 0;
2375 }
2376
2377 static int
2378 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2379 {
2380         struct i40e_vf *vf;
2381         struct i40e_hw *hw;
2382         int ret;
2383
2384         if (!vsi || !lut)
2385                 return -EINVAL;
2386
2387         vf = I40E_VSI_TO_VF(vsi);
2388         hw = I40E_VSI_TO_HW(vsi);
2389
2390         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2391                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2392                                           lut, lut_size);
2393                 if (ret) {
2394                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2395                         return ret;
2396                 }
2397         } else {
2398                 uint32_t *lut_dw = (uint32_t *)lut;
2399                 uint16_t i, lut_size_dw = lut_size / 4;
2400
2401                 for (i = 0; i < lut_size_dw; i++)
2402                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2403                 I40EVF_WRITE_FLUSH(hw);
2404         }
2405
2406         return 0;
2407 }
2408
2409 static int
2410 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2411                            struct rte_eth_rss_reta_entry64 *reta_conf,
2412                            uint16_t reta_size)
2413 {
2414         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2415         uint8_t *lut;
2416         uint16_t i, idx, shift;
2417         int ret;
2418
2419         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2420                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2421                         "(%d) doesn't match the number of hardware can "
2422                         "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2423                 return -EINVAL;
2424         }
2425
2426         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2427         if (!lut) {
2428                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2429                 return -ENOMEM;
2430         }
2431         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2432         if (ret)
2433                 goto out;
2434         for (i = 0; i < reta_size; i++) {
2435                 idx = i / RTE_RETA_GROUP_SIZE;
2436                 shift = i % RTE_RETA_GROUP_SIZE;
2437                 if (reta_conf[idx].mask & (1ULL << shift))
2438                         lut[i] = reta_conf[idx].reta[shift];
2439         }
2440         ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2441
2442 out:
2443         rte_free(lut);
2444
2445         return ret;
2446 }
2447
2448 static int
2449 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2450                           struct rte_eth_rss_reta_entry64 *reta_conf,
2451                           uint16_t reta_size)
2452 {
2453         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2454         uint16_t i, idx, shift;
2455         uint8_t *lut;
2456         int ret;
2457
2458         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2459                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2460                         "(%d) doesn't match the number of hardware can "
2461                         "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2462                 return -EINVAL;
2463         }
2464
2465         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2466         if (!lut) {
2467                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2468                 return -ENOMEM;
2469         }
2470
2471         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2472         if (ret)
2473                 goto out;
2474         for (i = 0; i < reta_size; i++) {
2475                 idx = i / RTE_RETA_GROUP_SIZE;
2476                 shift = i % RTE_RETA_GROUP_SIZE;
2477                 if (reta_conf[idx].mask & (1ULL << shift))
2478                         reta_conf[idx].reta[shift] = lut[i];
2479         }
2480
2481 out:
2482         rte_free(lut);
2483
2484         return ret;
2485 }
2486
2487 static int
2488 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2489 {
2490         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2491         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2492         int ret = 0;
2493
2494         if (!key || key_len == 0) {
2495                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2496                 return 0;
2497         } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2498                 sizeof(uint32_t)) {
2499                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2500                 return -EINVAL;
2501         }
2502
2503         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2504                 struct i40e_aqc_get_set_rss_key_data *key_dw =
2505                         (struct i40e_aqc_get_set_rss_key_data *)key;
2506
2507                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2508                 if (ret)
2509                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2510                                      "via AQ");
2511         } else {
2512                 uint32_t *hash_key = (uint32_t *)key;
2513                 uint16_t i;
2514
2515                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2516                         i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2517                 I40EVF_WRITE_FLUSH(hw);
2518         }
2519
2520         return ret;
2521 }
2522
2523 static int
2524 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2525 {
2526         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2527         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2528         int ret;
2529
2530         if (!key || !key_len)
2531                 return -EINVAL;
2532
2533         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2534                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2535                         (struct i40e_aqc_get_set_rss_key_data *)key);
2536                 if (ret) {
2537                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2538                         return ret;
2539                 }
2540         } else {
2541                 uint32_t *key_dw = (uint32_t *)key;
2542                 uint16_t i;
2543
2544                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2545                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2546         }
2547         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2548
2549         return 0;
2550 }
2551
2552 static int
2553 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2554 {
2555         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2556         uint64_t rss_hf, hena;
2557         int ret;
2558
2559         ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2560                                  rss_conf->rss_key_len);
2561         if (ret)
2562                 return ret;
2563
2564         rss_hf = rss_conf->rss_hf;
2565         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2566         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2567         if (hw->mac.type == I40E_MAC_X722)
2568                 hena &= ~I40E_RSS_HENA_ALL_X722;
2569         else
2570                 hena &= ~I40E_RSS_HENA_ALL;
2571         hena |= i40e_config_hena(rss_hf, hw->mac.type);
2572         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2573         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2574         I40EVF_WRITE_FLUSH(hw);
2575
2576         return 0;
2577 }
2578
2579 static void
2580 i40evf_disable_rss(struct i40e_vf *vf)
2581 {
2582         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2583         uint64_t hena;
2584
2585         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2586         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2587         if (hw->mac.type == I40E_MAC_X722)
2588                 hena &= ~I40E_RSS_HENA_ALL_X722;
2589         else
2590                 hena &= ~I40E_RSS_HENA_ALL;
2591         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2592         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2593         I40EVF_WRITE_FLUSH(hw);
2594 }
2595
2596 static int
2597 i40evf_config_rss(struct i40e_vf *vf)
2598 {
2599         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2600         struct rte_eth_rss_conf rss_conf;
2601         uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2602         uint16_t num;
2603
2604         if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2605                 i40evf_disable_rss(vf);
2606                 PMD_DRV_LOG(DEBUG, "RSS not configured");
2607                 return 0;
2608         }
2609
2610         num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2611         /* Fill out the look up table */
2612         for (i = 0, j = 0; i < nb_q; i++, j++) {
2613                 if (j >= num)
2614                         j = 0;
2615                 lut = (lut << 8) | j;
2616                 if ((i & 3) == 3)
2617                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2618         }
2619
2620         rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2621         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2622                 i40evf_disable_rss(vf);
2623                 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2624                 return 0;
2625         }
2626
2627         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2628                 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2629                 /* Calculate the default hash key */
2630                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2631                         rss_key_default[i] = (uint32_t)rte_rand();
2632                 rss_conf.rss_key = (uint8_t *)rss_key_default;
2633                 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2634                         sizeof(uint32_t);
2635         }
2636
2637         return i40evf_hw_rss_hash_set(vf, &rss_conf);
2638 }
2639
2640 static int
2641 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2642                            struct rte_eth_rss_conf *rss_conf)
2643 {
2644         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2645         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2646         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2647         uint64_t hena;
2648
2649         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2650         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2651         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
2652                  ? I40E_RSS_HENA_ALL_X722
2653                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
2654                 if (rss_hf != 0) /* Enable RSS */
2655                         return -EINVAL;
2656                 return 0;
2657         }
2658
2659         /* RSS enabled */
2660         if (rss_hf == 0) /* Disable RSS */
2661                 return -EINVAL;
2662
2663         return i40evf_hw_rss_hash_set(vf, rss_conf);
2664 }
2665
2666 static int
2667 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2668                              struct rte_eth_rss_conf *rss_conf)
2669 {
2670         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2671         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2672         uint64_t hena;
2673
2674         i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2675                            &rss_conf->rss_key_len);
2676
2677         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2678         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2679         rss_conf->rss_hf = i40e_parse_hena(hena);
2680
2681         return 0;
2682 }
2683
2684 static int
2685 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2686 {
2687         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2688         struct rte_eth_dev_data *dev_data = vf->dev_data;
2689         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2690         int ret = 0;
2691
2692         /* check if mtu is within the allowed range */
2693         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
2694                 return -EINVAL;
2695
2696         /* mtu setting is forbidden if port is start */
2697         if (dev_data->dev_started) {
2698                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2699                             dev_data->port_id);
2700                 return -EBUSY;
2701         }
2702
2703         if (frame_size > ETHER_MAX_LEN)
2704                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
2705         else
2706                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
2707
2708         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2709
2710         return ret;
2711 }
2712
2713 static void
2714 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2715                             struct ether_addr *mac_addr)
2716 {
2717         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2718
2719         if (!is_valid_assigned_ether_addr(mac_addr)) {
2720                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2721                 return;
2722         }
2723
2724         if (is_same_ether_addr(mac_addr, dev->data->mac_addrs))
2725                 return;
2726
2727         if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2728                 return;
2729
2730         i40evf_del_mac_addr_by_addr(dev, dev->data->mac_addrs);
2731
2732         i40evf_add_mac_addr(dev, mac_addr, 0, 0);
2733 }