drivers/net/i40e/i40e_flow.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright (c) 2016-2017 Intel Corporation. All rights reserved.
   5  *
   6  *   Redistribution and use in source and binary forms, with or without
   7  *   modification, are permitted provided that the following conditions
   8  *   are met:
   9  *
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in
  14  *       the documentation and/or other materials provided with the
  15  *       distribution.
  16  *     * Neither the name of Intel Corporation nor the names of its
  17  *       contributors may be used to endorse or promote products derived
  18  *       from this software without specific prior written permission.
  19  *
  20  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <sys/queue.h>
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40
  41 #include <rte_ether.h>
  42 #include <rte_ethdev.h>
  43 #include <rte_log.h>
  44 #include <rte_memzone.h>
  45 #include <rte_malloc.h>
  46 #include <rte_eth_ctrl.h>
  47 #include <rte_tailq.h>
  48 #include <rte_flow_driver.h>
  49
  50 #include "i40e_logs.h"
  51 #include "base/i40e_type.h"
  52 #include "base/i40e_prototype.h"
  53 #include "i40e_ethdev.h"
  54
  55 #define I40E_IPV6_TC_MASK       (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
  56 #define I40E_IPV6_FRAG_HEADER   44
  57 #define I40E_TENANT_ARRAY_NUM   3
  58 #define I40E_TCI_MASK           0xFFFF
  59
  60 static int i40e_flow_validate(struct rte_eth_dev *dev,
  61                               const struct rte_flow_attr *attr,
  62                               const struct rte_flow_item pattern[],
  63                               const struct rte_flow_action actions[],
  64                               struct rte_flow_error *error);
  65 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
  66                                          const struct rte_flow_attr *attr,
  67                                          const struct rte_flow_item pattern[],
  68                                          const struct rte_flow_action actions[],
  69                                          struct rte_flow_error *error);
  70 static int i40e_flow_destroy(struct rte_eth_dev *dev,
  71                              struct rte_flow *flow,
  72                              struct rte_flow_error *error);
  73 static int i40e_flow_flush(struct rte_eth_dev *dev,
  74                            struct rte_flow_error *error);
  75 static int
  76 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
  77                                   const struct rte_flow_item *pattern,
  78                                   struct rte_flow_error *error,
  79                                   struct rte_eth_ethertype_filter *filter);
  80 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
  81                                     const struct rte_flow_action *actions,
  82                                     struct rte_flow_error *error,
  83                                     struct rte_eth_ethertype_filter *filter);
  84 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
  85                                         const struct rte_flow_item *pattern,
  86                                         struct rte_flow_error *error,
  87                                         struct i40e_fdir_filter_conf *filter);
  88 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
  89                                        const struct rte_flow_action *actions,
  90                                        struct rte_flow_error *error,
  91                                        struct i40e_fdir_filter_conf *filter);
  92 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
  93                                  const struct rte_flow_action *actions,
  94                                  struct rte_flow_error *error,
  95                                  struct i40e_tunnel_filter_conf *filter);
  96 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
  97                                 struct rte_flow_error *error);
  98 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
  99                                     const struct rte_flow_attr *attr,
 100                                     const struct rte_flow_item pattern[],
 101                                     const struct rte_flow_action actions[],
 102                                     struct rte_flow_error *error,
 103                                     union i40e_filter_t *filter);
 104 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
 105                                        const struct rte_flow_attr *attr,
 106                                        const struct rte_flow_item pattern[],
 107                                        const struct rte_flow_action actions[],
 108                                        struct rte_flow_error *error,
 109                                        union i40e_filter_t *filter);
 110 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
 111                                         const struct rte_flow_attr *attr,
 112                                         const struct rte_flow_item pattern[],
 113                                         const struct rte_flow_action actions[],
 114                                         struct rte_flow_error *error,
 115                                         union i40e_filter_t *filter);
 116 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
 117                                         const struct rte_flow_attr *attr,
 118                                         const struct rte_flow_item pattern[],
 119                                         const struct rte_flow_action actions[],
 120                                         struct rte_flow_error *error,
 121                                         union i40e_filter_t *filter);
 122 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
 123                                        const struct rte_flow_attr *attr,
 124                                        const struct rte_flow_item pattern[],
 125                                        const struct rte_flow_action actions[],
 126                                        struct rte_flow_error *error,
 127                                        union i40e_filter_t *filter);
 128 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
 129                                       const struct rte_flow_attr *attr,
 130                                       const struct rte_flow_item pattern[],
 131                                       const struct rte_flow_action actions[],
 132                                       struct rte_flow_error *error,
 133                                       union i40e_filter_t *filter);
 134 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
 135                                       struct i40e_ethertype_filter *filter);
 136 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
 137                                            struct i40e_tunnel_filter *filter);
 138 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
 139 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
 140 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
 141 static int
 142 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
 143                               const struct rte_flow_attr *attr,
 144                               const struct rte_flow_item pattern[],
 145                               const struct rte_flow_action actions[],
 146                               struct rte_flow_error *error,
 147                               union i40e_filter_t *filter);
 148 static int
 149 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
 150                               const struct rte_flow_item *pattern,
 151                               struct rte_flow_error *error,
 152                               struct i40e_tunnel_filter_conf *filter);
 153
 154 const struct rte_flow_ops i40e_flow_ops = {
 155         .validate = i40e_flow_validate,
 156         .create = i40e_flow_create,
 157         .destroy = i40e_flow_destroy,
 158         .flush = i40e_flow_flush,
 159 };
 160
 161 union i40e_filter_t cons_filter;
 162 enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
 163
 164 /* Pattern matched ethertype filter */
 165 static enum rte_flow_item_type pattern_ethertype[] = {
 166         RTE_FLOW_ITEM_TYPE_ETH,
 167         RTE_FLOW_ITEM_TYPE_END,
 168 };
 169
 170 /* Pattern matched flow director filter */
 171 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
 172         RTE_FLOW_ITEM_TYPE_ETH,
 173         RTE_FLOW_ITEM_TYPE_IPV4,
 174         RTE_FLOW_ITEM_TYPE_END,
 175 };
 176
 177 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
 178         RTE_FLOW_ITEM_TYPE_ETH,
 179         RTE_FLOW_ITEM_TYPE_IPV4,
 180         RTE_FLOW_ITEM_TYPE_UDP,
 181         RTE_FLOW_ITEM_TYPE_END,
 182 };
 183
 184 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
 185         RTE_FLOW_ITEM_TYPE_ETH,
 186         RTE_FLOW_ITEM_TYPE_IPV4,
 187         RTE_FLOW_ITEM_TYPE_TCP,
 188         RTE_FLOW_ITEM_TYPE_END,
 189 };
 190
 191 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
 192         RTE_FLOW_ITEM_TYPE_ETH,
 193         RTE_FLOW_ITEM_TYPE_IPV4,
 194         RTE_FLOW_ITEM_TYPE_SCTP,
 195         RTE_FLOW_ITEM_TYPE_END,
 196 };
 197
 198 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = {
 199         RTE_FLOW_ITEM_TYPE_ETH,
 200         RTE_FLOW_ITEM_TYPE_IPV4,
 201         RTE_FLOW_ITEM_TYPE_UDP,
 202         RTE_FLOW_ITEM_TYPE_GTPC,
 203         RTE_FLOW_ITEM_TYPE_END,
 204 };
 205
 206 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = {
 207         RTE_FLOW_ITEM_TYPE_ETH,
 208         RTE_FLOW_ITEM_TYPE_IPV4,
 209         RTE_FLOW_ITEM_TYPE_UDP,
 210         RTE_FLOW_ITEM_TYPE_GTPU,
 211         RTE_FLOW_ITEM_TYPE_END,
 212 };
 213
 214 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = {
 215         RTE_FLOW_ITEM_TYPE_ETH,
 216         RTE_FLOW_ITEM_TYPE_IPV4,
 217         RTE_FLOW_ITEM_TYPE_UDP,
 218         RTE_FLOW_ITEM_TYPE_GTPU,
 219         RTE_FLOW_ITEM_TYPE_IPV4,
 220         RTE_FLOW_ITEM_TYPE_END,
 221 };
 222
 223 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = {
 224         RTE_FLOW_ITEM_TYPE_ETH,
 225         RTE_FLOW_ITEM_TYPE_IPV4,
 226         RTE_FLOW_ITEM_TYPE_UDP,
 227         RTE_FLOW_ITEM_TYPE_GTPU,
 228         RTE_FLOW_ITEM_TYPE_IPV6,
 229         RTE_FLOW_ITEM_TYPE_END,
 230 };
 231
 232 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
 233         RTE_FLOW_ITEM_TYPE_ETH,
 234         RTE_FLOW_ITEM_TYPE_IPV6,
 235         RTE_FLOW_ITEM_TYPE_END,
 236 };
 237
 238 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
 239         RTE_FLOW_ITEM_TYPE_ETH,
 240         RTE_FLOW_ITEM_TYPE_IPV6,
 241         RTE_FLOW_ITEM_TYPE_UDP,
 242         RTE_FLOW_ITEM_TYPE_END,
 243 };
 244
 245 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
 246         RTE_FLOW_ITEM_TYPE_ETH,
 247         RTE_FLOW_ITEM_TYPE_IPV6,
 248         RTE_FLOW_ITEM_TYPE_TCP,
 249         RTE_FLOW_ITEM_TYPE_END,
 250 };
 251
 252 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
 253         RTE_FLOW_ITEM_TYPE_ETH,
 254         RTE_FLOW_ITEM_TYPE_IPV6,
 255         RTE_FLOW_ITEM_TYPE_SCTP,
 256         RTE_FLOW_ITEM_TYPE_END,
 257 };
 258
 259 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = {
 260         RTE_FLOW_ITEM_TYPE_ETH,
 261         RTE_FLOW_ITEM_TYPE_IPV6,
 262         RTE_FLOW_ITEM_TYPE_UDP,
 263         RTE_FLOW_ITEM_TYPE_GTPC,
 264         RTE_FLOW_ITEM_TYPE_END,
 265 };
 266
 267 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = {
 268         RTE_FLOW_ITEM_TYPE_ETH,
 269         RTE_FLOW_ITEM_TYPE_IPV6,
 270         RTE_FLOW_ITEM_TYPE_UDP,
 271         RTE_FLOW_ITEM_TYPE_GTPU,
 272         RTE_FLOW_ITEM_TYPE_END,
 273 };
 274
 275 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = {
 276         RTE_FLOW_ITEM_TYPE_ETH,
 277         RTE_FLOW_ITEM_TYPE_IPV6,
 278         RTE_FLOW_ITEM_TYPE_UDP,
 279         RTE_FLOW_ITEM_TYPE_GTPU,
 280         RTE_FLOW_ITEM_TYPE_IPV4,
 281         RTE_FLOW_ITEM_TYPE_END,
 282 };
 283
 284 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = {
 285         RTE_FLOW_ITEM_TYPE_ETH,
 286         RTE_FLOW_ITEM_TYPE_IPV6,
 287         RTE_FLOW_ITEM_TYPE_UDP,
 288         RTE_FLOW_ITEM_TYPE_GTPU,
 289         RTE_FLOW_ITEM_TYPE_IPV6,
 290         RTE_FLOW_ITEM_TYPE_END,
 291 };
 292
 293 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
 294         RTE_FLOW_ITEM_TYPE_ETH,
 295         RTE_FLOW_ITEM_TYPE_RAW,
 296         RTE_FLOW_ITEM_TYPE_END,
 297 };
 298
 299 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
 300         RTE_FLOW_ITEM_TYPE_ETH,
 301         RTE_FLOW_ITEM_TYPE_RAW,
 302         RTE_FLOW_ITEM_TYPE_RAW,
 303         RTE_FLOW_ITEM_TYPE_END,
 304 };
 305
 306 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
 307         RTE_FLOW_ITEM_TYPE_ETH,
 308         RTE_FLOW_ITEM_TYPE_RAW,
 309         RTE_FLOW_ITEM_TYPE_RAW,
 310         RTE_FLOW_ITEM_TYPE_RAW,
 311         RTE_FLOW_ITEM_TYPE_END,
 312 };
 313
 314 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
 315         RTE_FLOW_ITEM_TYPE_ETH,
 316         RTE_FLOW_ITEM_TYPE_IPV4,
 317         RTE_FLOW_ITEM_TYPE_RAW,
 318         RTE_FLOW_ITEM_TYPE_END,
 319 };
 320
 321 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
 322         RTE_FLOW_ITEM_TYPE_ETH,
 323         RTE_FLOW_ITEM_TYPE_IPV4,
 324         RTE_FLOW_ITEM_TYPE_RAW,
 325         RTE_FLOW_ITEM_TYPE_RAW,
 326         RTE_FLOW_ITEM_TYPE_END,
 327 };
 328
 329 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
 330         RTE_FLOW_ITEM_TYPE_ETH,
 331         RTE_FLOW_ITEM_TYPE_IPV4,
 332         RTE_FLOW_ITEM_TYPE_RAW,
 333         RTE_FLOW_ITEM_TYPE_RAW,
 334         RTE_FLOW_ITEM_TYPE_RAW,
 335         RTE_FLOW_ITEM_TYPE_END,
 336 };
 337
 338 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
 339         RTE_FLOW_ITEM_TYPE_ETH,
 340         RTE_FLOW_ITEM_TYPE_IPV4,
 341         RTE_FLOW_ITEM_TYPE_UDP,
 342         RTE_FLOW_ITEM_TYPE_RAW,
 343         RTE_FLOW_ITEM_TYPE_END,
 344 };
 345
 346 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
 347         RTE_FLOW_ITEM_TYPE_ETH,
 348         RTE_FLOW_ITEM_TYPE_IPV4,
 349         RTE_FLOW_ITEM_TYPE_UDP,
 350         RTE_FLOW_ITEM_TYPE_RAW,
 351         RTE_FLOW_ITEM_TYPE_RAW,
 352         RTE_FLOW_ITEM_TYPE_END,
 353 };
 354
 355 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
 356         RTE_FLOW_ITEM_TYPE_ETH,
 357         RTE_FLOW_ITEM_TYPE_IPV4,
 358         RTE_FLOW_ITEM_TYPE_UDP,
 359         RTE_FLOW_ITEM_TYPE_RAW,
 360         RTE_FLOW_ITEM_TYPE_RAW,
 361         RTE_FLOW_ITEM_TYPE_RAW,
 362         RTE_FLOW_ITEM_TYPE_END,
 363 };
 364
 365 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
 366         RTE_FLOW_ITEM_TYPE_ETH,
 367         RTE_FLOW_ITEM_TYPE_IPV4,
 368         RTE_FLOW_ITEM_TYPE_TCP,
 369         RTE_FLOW_ITEM_TYPE_RAW,
 370         RTE_FLOW_ITEM_TYPE_END,
 371 };
 372
 373 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
 374         RTE_FLOW_ITEM_TYPE_ETH,
 375         RTE_FLOW_ITEM_TYPE_IPV4,
 376         RTE_FLOW_ITEM_TYPE_TCP,
 377         RTE_FLOW_ITEM_TYPE_RAW,
 378         RTE_FLOW_ITEM_TYPE_RAW,
 379         RTE_FLOW_ITEM_TYPE_END,
 380 };
 381
 382 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
 383         RTE_FLOW_ITEM_TYPE_ETH,
 384         RTE_FLOW_ITEM_TYPE_IPV4,
 385         RTE_FLOW_ITEM_TYPE_TCP,
 386         RTE_FLOW_ITEM_TYPE_RAW,
 387         RTE_FLOW_ITEM_TYPE_RAW,
 388         RTE_FLOW_ITEM_TYPE_RAW,
 389         RTE_FLOW_ITEM_TYPE_END,
 390 };
 391
 392 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
 393         RTE_FLOW_ITEM_TYPE_ETH,
 394         RTE_FLOW_ITEM_TYPE_IPV4,
 395         RTE_FLOW_ITEM_TYPE_SCTP,
 396         RTE_FLOW_ITEM_TYPE_RAW,
 397         RTE_FLOW_ITEM_TYPE_END,
 398 };
 399
 400 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
 401         RTE_FLOW_ITEM_TYPE_ETH,
 402         RTE_FLOW_ITEM_TYPE_IPV4,
 403         RTE_FLOW_ITEM_TYPE_SCTP,
 404         RTE_FLOW_ITEM_TYPE_RAW,
 405         RTE_FLOW_ITEM_TYPE_RAW,
 406         RTE_FLOW_ITEM_TYPE_END,
 407 };
 408
 409 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
 410         RTE_FLOW_ITEM_TYPE_ETH,
 411         RTE_FLOW_ITEM_TYPE_IPV4,
 412         RTE_FLOW_ITEM_TYPE_SCTP,
 413         RTE_FLOW_ITEM_TYPE_RAW,
 414         RTE_FLOW_ITEM_TYPE_RAW,
 415         RTE_FLOW_ITEM_TYPE_RAW,
 416         RTE_FLOW_ITEM_TYPE_END,
 417 };
 418
 419 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
 420         RTE_FLOW_ITEM_TYPE_ETH,
 421         RTE_FLOW_ITEM_TYPE_IPV6,
 422         RTE_FLOW_ITEM_TYPE_RAW,
 423         RTE_FLOW_ITEM_TYPE_END,
 424 };
 425
 426 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
 427         RTE_FLOW_ITEM_TYPE_ETH,
 428         RTE_FLOW_ITEM_TYPE_IPV6,
 429         RTE_FLOW_ITEM_TYPE_RAW,
 430         RTE_FLOW_ITEM_TYPE_RAW,
 431         RTE_FLOW_ITEM_TYPE_END,
 432 };
 433
 434 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
 435         RTE_FLOW_ITEM_TYPE_ETH,
 436         RTE_FLOW_ITEM_TYPE_IPV6,
 437         RTE_FLOW_ITEM_TYPE_RAW,
 438         RTE_FLOW_ITEM_TYPE_RAW,
 439         RTE_FLOW_ITEM_TYPE_RAW,
 440         RTE_FLOW_ITEM_TYPE_END,
 441 };
 442
 443 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
 444         RTE_FLOW_ITEM_TYPE_ETH,
 445         RTE_FLOW_ITEM_TYPE_IPV6,
 446         RTE_FLOW_ITEM_TYPE_UDP,
 447         RTE_FLOW_ITEM_TYPE_RAW,
 448         RTE_FLOW_ITEM_TYPE_END,
 449 };
 450
 451 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
 452         RTE_FLOW_ITEM_TYPE_ETH,
 453         RTE_FLOW_ITEM_TYPE_IPV6,
 454         RTE_FLOW_ITEM_TYPE_UDP,
 455         RTE_FLOW_ITEM_TYPE_RAW,
 456         RTE_FLOW_ITEM_TYPE_RAW,
 457         RTE_FLOW_ITEM_TYPE_END,
 458 };
 459
 460 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
 461         RTE_FLOW_ITEM_TYPE_ETH,
 462         RTE_FLOW_ITEM_TYPE_IPV6,
 463         RTE_FLOW_ITEM_TYPE_UDP,
 464         RTE_FLOW_ITEM_TYPE_RAW,
 465         RTE_FLOW_ITEM_TYPE_RAW,
 466         RTE_FLOW_ITEM_TYPE_RAW,
 467         RTE_FLOW_ITEM_TYPE_END,
 468 };
 469
 470 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
 471         RTE_FLOW_ITEM_TYPE_ETH,
 472         RTE_FLOW_ITEM_TYPE_IPV6,
 473         RTE_FLOW_ITEM_TYPE_TCP,
 474         RTE_FLOW_ITEM_TYPE_RAW,
 475         RTE_FLOW_ITEM_TYPE_END,
 476 };
 477
 478 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
 479         RTE_FLOW_ITEM_TYPE_ETH,
 480         RTE_FLOW_ITEM_TYPE_IPV6,
 481         RTE_FLOW_ITEM_TYPE_TCP,
 482         RTE_FLOW_ITEM_TYPE_RAW,
 483         RTE_FLOW_ITEM_TYPE_RAW,
 484         RTE_FLOW_ITEM_TYPE_END,
 485 };
 486
 487 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
 488         RTE_FLOW_ITEM_TYPE_ETH,
 489         RTE_FLOW_ITEM_TYPE_IPV6,
 490         RTE_FLOW_ITEM_TYPE_TCP,
 491         RTE_FLOW_ITEM_TYPE_RAW,
 492         RTE_FLOW_ITEM_TYPE_RAW,
 493         RTE_FLOW_ITEM_TYPE_RAW,
 494         RTE_FLOW_ITEM_TYPE_END,
 495 };
 496
 497 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
 498         RTE_FLOW_ITEM_TYPE_ETH,
 499         RTE_FLOW_ITEM_TYPE_IPV6,
 500         RTE_FLOW_ITEM_TYPE_SCTP,
 501         RTE_FLOW_ITEM_TYPE_RAW,
 502         RTE_FLOW_ITEM_TYPE_END,
 503 };
 504
 505 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
 506         RTE_FLOW_ITEM_TYPE_ETH,
 507         RTE_FLOW_ITEM_TYPE_IPV6,
 508         RTE_FLOW_ITEM_TYPE_SCTP,
 509         RTE_FLOW_ITEM_TYPE_RAW,
 510         RTE_FLOW_ITEM_TYPE_RAW,
 511         RTE_FLOW_ITEM_TYPE_END,
 512 };
 513
 514 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
 515         RTE_FLOW_ITEM_TYPE_ETH,
 516         RTE_FLOW_ITEM_TYPE_IPV6,
 517         RTE_FLOW_ITEM_TYPE_SCTP,
 518         RTE_FLOW_ITEM_TYPE_RAW,
 519         RTE_FLOW_ITEM_TYPE_RAW,
 520         RTE_FLOW_ITEM_TYPE_RAW,
 521         RTE_FLOW_ITEM_TYPE_END,
 522 };
 523
 524 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
 525         RTE_FLOW_ITEM_TYPE_ETH,
 526         RTE_FLOW_ITEM_TYPE_VLAN,
 527         RTE_FLOW_ITEM_TYPE_END,
 528 };
 529
 530 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
 531         RTE_FLOW_ITEM_TYPE_ETH,
 532         RTE_FLOW_ITEM_TYPE_VLAN,
 533         RTE_FLOW_ITEM_TYPE_IPV4,
 534         RTE_FLOW_ITEM_TYPE_END,
 535 };
 536
 537 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
 538         RTE_FLOW_ITEM_TYPE_ETH,
 539         RTE_FLOW_ITEM_TYPE_VLAN,
 540         RTE_FLOW_ITEM_TYPE_IPV4,
 541         RTE_FLOW_ITEM_TYPE_UDP,
 542         RTE_FLOW_ITEM_TYPE_END,
 543 };
 544
 545 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
 546         RTE_FLOW_ITEM_TYPE_ETH,
 547         RTE_FLOW_ITEM_TYPE_VLAN,
 548         RTE_FLOW_ITEM_TYPE_IPV4,
 549         RTE_FLOW_ITEM_TYPE_TCP,
 550         RTE_FLOW_ITEM_TYPE_END,
 551 };
 552
 553 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
 554         RTE_FLOW_ITEM_TYPE_ETH,
 555         RTE_FLOW_ITEM_TYPE_VLAN,
 556         RTE_FLOW_ITEM_TYPE_IPV4,
 557         RTE_FLOW_ITEM_TYPE_SCTP,
 558         RTE_FLOW_ITEM_TYPE_END,
 559 };
 560
 561 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
 562         RTE_FLOW_ITEM_TYPE_ETH,
 563         RTE_FLOW_ITEM_TYPE_VLAN,
 564         RTE_FLOW_ITEM_TYPE_IPV6,
 565         RTE_FLOW_ITEM_TYPE_END,
 566 };
 567
 568 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
 569         RTE_FLOW_ITEM_TYPE_ETH,
 570         RTE_FLOW_ITEM_TYPE_VLAN,
 571         RTE_FLOW_ITEM_TYPE_IPV6,
 572         RTE_FLOW_ITEM_TYPE_UDP,
 573         RTE_FLOW_ITEM_TYPE_END,
 574 };
 575
 576 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
 577         RTE_FLOW_ITEM_TYPE_ETH,
 578         RTE_FLOW_ITEM_TYPE_VLAN,
 579         RTE_FLOW_ITEM_TYPE_IPV6,
 580         RTE_FLOW_ITEM_TYPE_TCP,
 581         RTE_FLOW_ITEM_TYPE_END,
 582 };
 583
 584 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
 585         RTE_FLOW_ITEM_TYPE_ETH,
 586         RTE_FLOW_ITEM_TYPE_VLAN,
 587         RTE_FLOW_ITEM_TYPE_IPV6,
 588         RTE_FLOW_ITEM_TYPE_SCTP,
 589         RTE_FLOW_ITEM_TYPE_END,
 590 };
 591
 592 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
 593         RTE_FLOW_ITEM_TYPE_ETH,
 594         RTE_FLOW_ITEM_TYPE_VLAN,
 595         RTE_FLOW_ITEM_TYPE_RAW,
 596         RTE_FLOW_ITEM_TYPE_END,
 597 };
 598
 599 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
 600         RTE_FLOW_ITEM_TYPE_ETH,
 601         RTE_FLOW_ITEM_TYPE_VLAN,
 602         RTE_FLOW_ITEM_TYPE_RAW,
 603         RTE_FLOW_ITEM_TYPE_RAW,
 604         RTE_FLOW_ITEM_TYPE_END,
 605 };
 606
 607 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
 608         RTE_FLOW_ITEM_TYPE_ETH,
 609         RTE_FLOW_ITEM_TYPE_VLAN,
 610         RTE_FLOW_ITEM_TYPE_RAW,
 611         RTE_FLOW_ITEM_TYPE_RAW,
 612         RTE_FLOW_ITEM_TYPE_RAW,
 613         RTE_FLOW_ITEM_TYPE_END,
 614 };
 615
 616 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
 617         RTE_FLOW_ITEM_TYPE_ETH,
 618         RTE_FLOW_ITEM_TYPE_VLAN,
 619         RTE_FLOW_ITEM_TYPE_IPV4,
 620         RTE_FLOW_ITEM_TYPE_RAW,
 621         RTE_FLOW_ITEM_TYPE_END,
 622 };
 623
 624 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
 625         RTE_FLOW_ITEM_TYPE_ETH,
 626         RTE_FLOW_ITEM_TYPE_VLAN,
 627         RTE_FLOW_ITEM_TYPE_IPV4,
 628         RTE_FLOW_ITEM_TYPE_RAW,
 629         RTE_FLOW_ITEM_TYPE_RAW,
 630         RTE_FLOW_ITEM_TYPE_END,
 631 };
 632
 633 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
 634         RTE_FLOW_ITEM_TYPE_ETH,
 635         RTE_FLOW_ITEM_TYPE_VLAN,
 636         RTE_FLOW_ITEM_TYPE_IPV4,
 637         RTE_FLOW_ITEM_TYPE_RAW,
 638         RTE_FLOW_ITEM_TYPE_RAW,
 639         RTE_FLOW_ITEM_TYPE_RAW,
 640         RTE_FLOW_ITEM_TYPE_END,
 641 };
 642
 643 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
 644         RTE_FLOW_ITEM_TYPE_ETH,
 645         RTE_FLOW_ITEM_TYPE_VLAN,
 646         RTE_FLOW_ITEM_TYPE_IPV4,
 647         RTE_FLOW_ITEM_TYPE_UDP,
 648         RTE_FLOW_ITEM_TYPE_RAW,
 649         RTE_FLOW_ITEM_TYPE_END,
 650 };
 651
 652 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
 653         RTE_FLOW_ITEM_TYPE_ETH,
 654         RTE_FLOW_ITEM_TYPE_VLAN,
 655         RTE_FLOW_ITEM_TYPE_IPV4,
 656         RTE_FLOW_ITEM_TYPE_UDP,
 657         RTE_FLOW_ITEM_TYPE_RAW,
 658         RTE_FLOW_ITEM_TYPE_RAW,
 659         RTE_FLOW_ITEM_TYPE_END,
 660 };
 661
 662 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
 663         RTE_FLOW_ITEM_TYPE_ETH,
 664         RTE_FLOW_ITEM_TYPE_VLAN,
 665         RTE_FLOW_ITEM_TYPE_IPV4,
 666         RTE_FLOW_ITEM_TYPE_UDP,
 667         RTE_FLOW_ITEM_TYPE_RAW,
 668         RTE_FLOW_ITEM_TYPE_RAW,
 669         RTE_FLOW_ITEM_TYPE_RAW,
 670         RTE_FLOW_ITEM_TYPE_END,
 671 };
 672
 673 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
 674         RTE_FLOW_ITEM_TYPE_ETH,
 675         RTE_FLOW_ITEM_TYPE_VLAN,
 676         RTE_FLOW_ITEM_TYPE_IPV4,
 677         RTE_FLOW_ITEM_TYPE_TCP,
 678         RTE_FLOW_ITEM_TYPE_RAW,
 679         RTE_FLOW_ITEM_TYPE_END,
 680 };
 681
 682 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
 683         RTE_FLOW_ITEM_TYPE_ETH,
 684         RTE_FLOW_ITEM_TYPE_VLAN,
 685         RTE_FLOW_ITEM_TYPE_IPV4,
 686         RTE_FLOW_ITEM_TYPE_TCP,
 687         RTE_FLOW_ITEM_TYPE_RAW,
 688         RTE_FLOW_ITEM_TYPE_RAW,
 689         RTE_FLOW_ITEM_TYPE_END,
 690 };
 691
 692 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
 693         RTE_FLOW_ITEM_TYPE_ETH,
 694         RTE_FLOW_ITEM_TYPE_VLAN,
 695         RTE_FLOW_ITEM_TYPE_IPV4,
 696         RTE_FLOW_ITEM_TYPE_TCP,
 697         RTE_FLOW_ITEM_TYPE_RAW,
 698         RTE_FLOW_ITEM_TYPE_RAW,
 699         RTE_FLOW_ITEM_TYPE_RAW,
 700         RTE_FLOW_ITEM_TYPE_END,
 701 };
 702
 703 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
 704         RTE_FLOW_ITEM_TYPE_ETH,
 705         RTE_FLOW_ITEM_TYPE_VLAN,
 706         RTE_FLOW_ITEM_TYPE_IPV4,
 707         RTE_FLOW_ITEM_TYPE_SCTP,
 708         RTE_FLOW_ITEM_TYPE_RAW,
 709         RTE_FLOW_ITEM_TYPE_END,
 710 };
 711
 712 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
 713         RTE_FLOW_ITEM_TYPE_ETH,
 714         RTE_FLOW_ITEM_TYPE_VLAN,
 715         RTE_FLOW_ITEM_TYPE_IPV4,
 716         RTE_FLOW_ITEM_TYPE_SCTP,
 717         RTE_FLOW_ITEM_TYPE_RAW,
 718         RTE_FLOW_ITEM_TYPE_RAW,
 719         RTE_FLOW_ITEM_TYPE_END,
 720 };
 721
 722 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
 723         RTE_FLOW_ITEM_TYPE_ETH,
 724         RTE_FLOW_ITEM_TYPE_VLAN,
 725         RTE_FLOW_ITEM_TYPE_IPV4,
 726         RTE_FLOW_ITEM_TYPE_SCTP,
 727         RTE_FLOW_ITEM_TYPE_RAW,
 728         RTE_FLOW_ITEM_TYPE_RAW,
 729         RTE_FLOW_ITEM_TYPE_RAW,
 730         RTE_FLOW_ITEM_TYPE_END,
 731 };
 732
 733 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
 734         RTE_FLOW_ITEM_TYPE_ETH,
 735         RTE_FLOW_ITEM_TYPE_VLAN,
 736         RTE_FLOW_ITEM_TYPE_IPV6,
 737         RTE_FLOW_ITEM_TYPE_RAW,
 738         RTE_FLOW_ITEM_TYPE_END,
 739 };
 740
 741 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
 742         RTE_FLOW_ITEM_TYPE_ETH,
 743         RTE_FLOW_ITEM_TYPE_VLAN,
 744         RTE_FLOW_ITEM_TYPE_IPV6,
 745         RTE_FLOW_ITEM_TYPE_RAW,
 746         RTE_FLOW_ITEM_TYPE_RAW,
 747         RTE_FLOW_ITEM_TYPE_END,
 748 };
 749
 750 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
 751         RTE_FLOW_ITEM_TYPE_ETH,
 752         RTE_FLOW_ITEM_TYPE_VLAN,
 753         RTE_FLOW_ITEM_TYPE_IPV6,
 754         RTE_FLOW_ITEM_TYPE_RAW,
 755         RTE_FLOW_ITEM_TYPE_RAW,
 756         RTE_FLOW_ITEM_TYPE_RAW,
 757         RTE_FLOW_ITEM_TYPE_END,
 758 };
 759
 760 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
 761         RTE_FLOW_ITEM_TYPE_ETH,
 762         RTE_FLOW_ITEM_TYPE_VLAN,
 763         RTE_FLOW_ITEM_TYPE_IPV6,
 764         RTE_FLOW_ITEM_TYPE_UDP,
 765         RTE_FLOW_ITEM_TYPE_RAW,
 766         RTE_FLOW_ITEM_TYPE_END,
 767 };
 768
 769 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
 770         RTE_FLOW_ITEM_TYPE_ETH,
 771         RTE_FLOW_ITEM_TYPE_VLAN,
 772         RTE_FLOW_ITEM_TYPE_IPV6,
 773         RTE_FLOW_ITEM_TYPE_UDP,
 774         RTE_FLOW_ITEM_TYPE_RAW,
 775         RTE_FLOW_ITEM_TYPE_RAW,
 776         RTE_FLOW_ITEM_TYPE_END,
 777 };
 778
 779 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
 780         RTE_FLOW_ITEM_TYPE_ETH,
 781         RTE_FLOW_ITEM_TYPE_VLAN,
 782         RTE_FLOW_ITEM_TYPE_IPV6,
 783         RTE_FLOW_ITEM_TYPE_UDP,
 784         RTE_FLOW_ITEM_TYPE_RAW,
 785         RTE_FLOW_ITEM_TYPE_RAW,
 786         RTE_FLOW_ITEM_TYPE_RAW,
 787         RTE_FLOW_ITEM_TYPE_END,
 788 };
 789
 790 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
 791         RTE_FLOW_ITEM_TYPE_ETH,
 792         RTE_FLOW_ITEM_TYPE_VLAN,
 793         RTE_FLOW_ITEM_TYPE_IPV6,
 794         RTE_FLOW_ITEM_TYPE_TCP,
 795         RTE_FLOW_ITEM_TYPE_RAW,
 796         RTE_FLOW_ITEM_TYPE_END,
 797 };
 798
 799 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
 800         RTE_FLOW_ITEM_TYPE_ETH,
 801         RTE_FLOW_ITEM_TYPE_VLAN,
 802         RTE_FLOW_ITEM_TYPE_IPV6,
 803         RTE_FLOW_ITEM_TYPE_TCP,
 804         RTE_FLOW_ITEM_TYPE_RAW,
 805         RTE_FLOW_ITEM_TYPE_RAW,
 806         RTE_FLOW_ITEM_TYPE_END,
 807 };
 808
 809 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
 810         RTE_FLOW_ITEM_TYPE_ETH,
 811         RTE_FLOW_ITEM_TYPE_VLAN,
 812         RTE_FLOW_ITEM_TYPE_IPV6,
 813         RTE_FLOW_ITEM_TYPE_TCP,
 814         RTE_FLOW_ITEM_TYPE_RAW,
 815         RTE_FLOW_ITEM_TYPE_RAW,
 816         RTE_FLOW_ITEM_TYPE_RAW,
 817         RTE_FLOW_ITEM_TYPE_END,
 818 };
 819
 820 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
 821         RTE_FLOW_ITEM_TYPE_ETH,
 822         RTE_FLOW_ITEM_TYPE_VLAN,
 823         RTE_FLOW_ITEM_TYPE_IPV6,
 824         RTE_FLOW_ITEM_TYPE_SCTP,
 825         RTE_FLOW_ITEM_TYPE_RAW,
 826         RTE_FLOW_ITEM_TYPE_END,
 827 };
 828
 829 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
 830         RTE_FLOW_ITEM_TYPE_ETH,
 831         RTE_FLOW_ITEM_TYPE_VLAN,
 832         RTE_FLOW_ITEM_TYPE_IPV6,
 833         RTE_FLOW_ITEM_TYPE_SCTP,
 834         RTE_FLOW_ITEM_TYPE_RAW,
 835         RTE_FLOW_ITEM_TYPE_RAW,
 836         RTE_FLOW_ITEM_TYPE_END,
 837 };
 838
 839 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
 840         RTE_FLOW_ITEM_TYPE_ETH,
 841         RTE_FLOW_ITEM_TYPE_VLAN,
 842         RTE_FLOW_ITEM_TYPE_IPV6,
 843         RTE_FLOW_ITEM_TYPE_SCTP,
 844         RTE_FLOW_ITEM_TYPE_RAW,
 845         RTE_FLOW_ITEM_TYPE_RAW,
 846         RTE_FLOW_ITEM_TYPE_RAW,
 847         RTE_FLOW_ITEM_TYPE_END,
 848 };
 849
 850 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
 851         RTE_FLOW_ITEM_TYPE_ETH,
 852         RTE_FLOW_ITEM_TYPE_IPV4,
 853         RTE_FLOW_ITEM_TYPE_VF,
 854         RTE_FLOW_ITEM_TYPE_END,
 855 };
 856
 857 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
 858         RTE_FLOW_ITEM_TYPE_ETH,
 859         RTE_FLOW_ITEM_TYPE_IPV4,
 860         RTE_FLOW_ITEM_TYPE_UDP,
 861         RTE_FLOW_ITEM_TYPE_VF,
 862         RTE_FLOW_ITEM_TYPE_END,
 863 };
 864
 865 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
 866         RTE_FLOW_ITEM_TYPE_ETH,
 867         RTE_FLOW_ITEM_TYPE_IPV4,
 868         RTE_FLOW_ITEM_TYPE_TCP,
 869         RTE_FLOW_ITEM_TYPE_VF,
 870         RTE_FLOW_ITEM_TYPE_END,
 871 };
 872
 873 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
 874         RTE_FLOW_ITEM_TYPE_ETH,
 875         RTE_FLOW_ITEM_TYPE_IPV4,
 876         RTE_FLOW_ITEM_TYPE_SCTP,
 877         RTE_FLOW_ITEM_TYPE_VF,
 878         RTE_FLOW_ITEM_TYPE_END,
 879 };
 880
 881 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
 882         RTE_FLOW_ITEM_TYPE_ETH,
 883         RTE_FLOW_ITEM_TYPE_IPV6,
 884         RTE_FLOW_ITEM_TYPE_VF,
 885         RTE_FLOW_ITEM_TYPE_END,
 886 };
 887
 888 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
 889         RTE_FLOW_ITEM_TYPE_ETH,
 890         RTE_FLOW_ITEM_TYPE_IPV6,
 891         RTE_FLOW_ITEM_TYPE_UDP,
 892         RTE_FLOW_ITEM_TYPE_VF,
 893         RTE_FLOW_ITEM_TYPE_END,
 894 };
 895
 896 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
 897         RTE_FLOW_ITEM_TYPE_ETH,
 898         RTE_FLOW_ITEM_TYPE_IPV6,
 899         RTE_FLOW_ITEM_TYPE_TCP,
 900         RTE_FLOW_ITEM_TYPE_VF,
 901         RTE_FLOW_ITEM_TYPE_END,
 902 };
 903
 904 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
 905         RTE_FLOW_ITEM_TYPE_ETH,
 906         RTE_FLOW_ITEM_TYPE_IPV6,
 907         RTE_FLOW_ITEM_TYPE_SCTP,
 908         RTE_FLOW_ITEM_TYPE_VF,
 909         RTE_FLOW_ITEM_TYPE_END,
 910 };
 911
 912 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
 913         RTE_FLOW_ITEM_TYPE_ETH,
 914         RTE_FLOW_ITEM_TYPE_RAW,
 915         RTE_FLOW_ITEM_TYPE_VF,
 916         RTE_FLOW_ITEM_TYPE_END,
 917 };
 918
 919 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
 920         RTE_FLOW_ITEM_TYPE_ETH,
 921         RTE_FLOW_ITEM_TYPE_RAW,
 922         RTE_FLOW_ITEM_TYPE_RAW,
 923         RTE_FLOW_ITEM_TYPE_VF,
 924         RTE_FLOW_ITEM_TYPE_END,
 925 };
 926
 927 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
 928         RTE_FLOW_ITEM_TYPE_ETH,
 929         RTE_FLOW_ITEM_TYPE_RAW,
 930         RTE_FLOW_ITEM_TYPE_RAW,
 931         RTE_FLOW_ITEM_TYPE_RAW,
 932         RTE_FLOW_ITEM_TYPE_VF,
 933         RTE_FLOW_ITEM_TYPE_END,
 934 };
 935
 936 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
 937         RTE_FLOW_ITEM_TYPE_ETH,
 938         RTE_FLOW_ITEM_TYPE_IPV4,
 939         RTE_FLOW_ITEM_TYPE_RAW,
 940         RTE_FLOW_ITEM_TYPE_VF,
 941         RTE_FLOW_ITEM_TYPE_END,
 942 };
 943
 944 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
 945         RTE_FLOW_ITEM_TYPE_ETH,
 946         RTE_FLOW_ITEM_TYPE_IPV4,
 947         RTE_FLOW_ITEM_TYPE_RAW,
 948         RTE_FLOW_ITEM_TYPE_RAW,
 949         RTE_FLOW_ITEM_TYPE_VF,
 950         RTE_FLOW_ITEM_TYPE_END,
 951 };
 952
 953 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
 954         RTE_FLOW_ITEM_TYPE_ETH,
 955         RTE_FLOW_ITEM_TYPE_IPV4,
 956         RTE_FLOW_ITEM_TYPE_RAW,
 957         RTE_FLOW_ITEM_TYPE_RAW,
 958         RTE_FLOW_ITEM_TYPE_RAW,
 959         RTE_FLOW_ITEM_TYPE_VF,
 960         RTE_FLOW_ITEM_TYPE_END,
 961 };
 962
 963 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
 964         RTE_FLOW_ITEM_TYPE_ETH,
 965         RTE_FLOW_ITEM_TYPE_IPV4,
 966         RTE_FLOW_ITEM_TYPE_UDP,
 967         RTE_FLOW_ITEM_TYPE_RAW,
 968         RTE_FLOW_ITEM_TYPE_VF,
 969         RTE_FLOW_ITEM_TYPE_END,
 970 };
 971
 972 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
 973         RTE_FLOW_ITEM_TYPE_ETH,
 974         RTE_FLOW_ITEM_TYPE_IPV4,
 975         RTE_FLOW_ITEM_TYPE_UDP,
 976         RTE_FLOW_ITEM_TYPE_RAW,
 977         RTE_FLOW_ITEM_TYPE_RAW,
 978         RTE_FLOW_ITEM_TYPE_VF,
 979         RTE_FLOW_ITEM_TYPE_END,
 980 };
 981
 982 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
 983         RTE_FLOW_ITEM_TYPE_ETH,
 984         RTE_FLOW_ITEM_TYPE_IPV4,
 985         RTE_FLOW_ITEM_TYPE_UDP,
 986         RTE_FLOW_ITEM_TYPE_RAW,
 987         RTE_FLOW_ITEM_TYPE_RAW,
 988         RTE_FLOW_ITEM_TYPE_RAW,
 989         RTE_FLOW_ITEM_TYPE_VF,
 990         RTE_FLOW_ITEM_TYPE_END,
 991 };
 992
 993 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
 994         RTE_FLOW_ITEM_TYPE_ETH,
 995         RTE_FLOW_ITEM_TYPE_IPV4,
 996         RTE_FLOW_ITEM_TYPE_TCP,
 997         RTE_FLOW_ITEM_TYPE_RAW,
 998         RTE_FLOW_ITEM_TYPE_VF,
 999         RTE_FLOW_ITEM_TYPE_END,
1000 };
1001
1002 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
1003         RTE_FLOW_ITEM_TYPE_ETH,
1004         RTE_FLOW_ITEM_TYPE_IPV4,
1005         RTE_FLOW_ITEM_TYPE_TCP,
1006         RTE_FLOW_ITEM_TYPE_RAW,
1007         RTE_FLOW_ITEM_TYPE_RAW,
1008         RTE_FLOW_ITEM_TYPE_VF,
1009         RTE_FLOW_ITEM_TYPE_END,
1010 };
1011
1012 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
1013         RTE_FLOW_ITEM_TYPE_ETH,
1014         RTE_FLOW_ITEM_TYPE_IPV4,
1015         RTE_FLOW_ITEM_TYPE_TCP,
1016         RTE_FLOW_ITEM_TYPE_RAW,
1017         RTE_FLOW_ITEM_TYPE_RAW,
1018         RTE_FLOW_ITEM_TYPE_RAW,
1019         RTE_FLOW_ITEM_TYPE_VF,
1020         RTE_FLOW_ITEM_TYPE_END,
1021 };
1022
1023 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
1024         RTE_FLOW_ITEM_TYPE_ETH,
1025         RTE_FLOW_ITEM_TYPE_IPV4,
1026         RTE_FLOW_ITEM_TYPE_SCTP,
1027         RTE_FLOW_ITEM_TYPE_RAW,
1028         RTE_FLOW_ITEM_TYPE_VF,
1029         RTE_FLOW_ITEM_TYPE_END,
1030 };
1031
1032 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
1033         RTE_FLOW_ITEM_TYPE_ETH,
1034         RTE_FLOW_ITEM_TYPE_IPV4,
1035         RTE_FLOW_ITEM_TYPE_SCTP,
1036         RTE_FLOW_ITEM_TYPE_RAW,
1037         RTE_FLOW_ITEM_TYPE_RAW,
1038         RTE_FLOW_ITEM_TYPE_VF,
1039         RTE_FLOW_ITEM_TYPE_END,
1040 };
1041
1042 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
1043         RTE_FLOW_ITEM_TYPE_ETH,
1044         RTE_FLOW_ITEM_TYPE_IPV4,
1045         RTE_FLOW_ITEM_TYPE_SCTP,
1046         RTE_FLOW_ITEM_TYPE_RAW,
1047         RTE_FLOW_ITEM_TYPE_RAW,
1048         RTE_FLOW_ITEM_TYPE_RAW,
1049         RTE_FLOW_ITEM_TYPE_VF,
1050         RTE_FLOW_ITEM_TYPE_END,
1051 };
1052
1053 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
1054         RTE_FLOW_ITEM_TYPE_ETH,
1055         RTE_FLOW_ITEM_TYPE_IPV6,
1056         RTE_FLOW_ITEM_TYPE_RAW,
1057         RTE_FLOW_ITEM_TYPE_VF,
1058         RTE_FLOW_ITEM_TYPE_END,
1059 };
1060
1061 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
1062         RTE_FLOW_ITEM_TYPE_ETH,
1063         RTE_FLOW_ITEM_TYPE_IPV6,
1064         RTE_FLOW_ITEM_TYPE_RAW,
1065         RTE_FLOW_ITEM_TYPE_RAW,
1066         RTE_FLOW_ITEM_TYPE_VF,
1067         RTE_FLOW_ITEM_TYPE_END,
1068 };
1069
1070 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
1071         RTE_FLOW_ITEM_TYPE_ETH,
1072         RTE_FLOW_ITEM_TYPE_IPV6,
1073         RTE_FLOW_ITEM_TYPE_RAW,
1074         RTE_FLOW_ITEM_TYPE_RAW,
1075         RTE_FLOW_ITEM_TYPE_RAW,
1076         RTE_FLOW_ITEM_TYPE_VF,
1077         RTE_FLOW_ITEM_TYPE_END,
1078 };
1079
1080 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1081         RTE_FLOW_ITEM_TYPE_ETH,
1082         RTE_FLOW_ITEM_TYPE_IPV6,
1083         RTE_FLOW_ITEM_TYPE_UDP,
1084         RTE_FLOW_ITEM_TYPE_RAW,
1085         RTE_FLOW_ITEM_TYPE_VF,
1086         RTE_FLOW_ITEM_TYPE_END,
1087 };
1088
1089 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1090         RTE_FLOW_ITEM_TYPE_ETH,
1091         RTE_FLOW_ITEM_TYPE_IPV6,
1092         RTE_FLOW_ITEM_TYPE_UDP,
1093         RTE_FLOW_ITEM_TYPE_RAW,
1094         RTE_FLOW_ITEM_TYPE_RAW,
1095         RTE_FLOW_ITEM_TYPE_VF,
1096         RTE_FLOW_ITEM_TYPE_END,
1097 };
1098
1099 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1100         RTE_FLOW_ITEM_TYPE_ETH,
1101         RTE_FLOW_ITEM_TYPE_IPV6,
1102         RTE_FLOW_ITEM_TYPE_UDP,
1103         RTE_FLOW_ITEM_TYPE_RAW,
1104         RTE_FLOW_ITEM_TYPE_RAW,
1105         RTE_FLOW_ITEM_TYPE_RAW,
1106         RTE_FLOW_ITEM_TYPE_VF,
1107         RTE_FLOW_ITEM_TYPE_END,
1108 };
1109
1110 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1111         RTE_FLOW_ITEM_TYPE_ETH,
1112         RTE_FLOW_ITEM_TYPE_IPV6,
1113         RTE_FLOW_ITEM_TYPE_TCP,
1114         RTE_FLOW_ITEM_TYPE_RAW,
1115         RTE_FLOW_ITEM_TYPE_VF,
1116         RTE_FLOW_ITEM_TYPE_END,
1117 };
1118
1119 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1120         RTE_FLOW_ITEM_TYPE_ETH,
1121         RTE_FLOW_ITEM_TYPE_IPV6,
1122         RTE_FLOW_ITEM_TYPE_TCP,
1123         RTE_FLOW_ITEM_TYPE_RAW,
1124         RTE_FLOW_ITEM_TYPE_RAW,
1125         RTE_FLOW_ITEM_TYPE_VF,
1126         RTE_FLOW_ITEM_TYPE_END,
1127 };
1128
1129 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1130         RTE_FLOW_ITEM_TYPE_ETH,
1131         RTE_FLOW_ITEM_TYPE_IPV6,
1132         RTE_FLOW_ITEM_TYPE_TCP,
1133         RTE_FLOW_ITEM_TYPE_RAW,
1134         RTE_FLOW_ITEM_TYPE_RAW,
1135         RTE_FLOW_ITEM_TYPE_RAW,
1136         RTE_FLOW_ITEM_TYPE_VF,
1137         RTE_FLOW_ITEM_TYPE_END,
1138 };
1139
1140 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1141         RTE_FLOW_ITEM_TYPE_ETH,
1142         RTE_FLOW_ITEM_TYPE_IPV6,
1143         RTE_FLOW_ITEM_TYPE_SCTP,
1144         RTE_FLOW_ITEM_TYPE_RAW,
1145         RTE_FLOW_ITEM_TYPE_VF,
1146         RTE_FLOW_ITEM_TYPE_END,
1147 };
1148
1149 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1150         RTE_FLOW_ITEM_TYPE_ETH,
1151         RTE_FLOW_ITEM_TYPE_IPV6,
1152         RTE_FLOW_ITEM_TYPE_SCTP,
1153         RTE_FLOW_ITEM_TYPE_RAW,
1154         RTE_FLOW_ITEM_TYPE_RAW,
1155         RTE_FLOW_ITEM_TYPE_VF,
1156         RTE_FLOW_ITEM_TYPE_END,
1157 };
1158
1159 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1160         RTE_FLOW_ITEM_TYPE_ETH,
1161         RTE_FLOW_ITEM_TYPE_IPV6,
1162         RTE_FLOW_ITEM_TYPE_SCTP,
1163         RTE_FLOW_ITEM_TYPE_RAW,
1164         RTE_FLOW_ITEM_TYPE_RAW,
1165         RTE_FLOW_ITEM_TYPE_RAW,
1166         RTE_FLOW_ITEM_TYPE_VF,
1167         RTE_FLOW_ITEM_TYPE_END,
1168 };
1169
1170 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1171         RTE_FLOW_ITEM_TYPE_ETH,
1172         RTE_FLOW_ITEM_TYPE_VLAN,
1173         RTE_FLOW_ITEM_TYPE_VF,
1174         RTE_FLOW_ITEM_TYPE_END,
1175 };
1176
1177 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1178         RTE_FLOW_ITEM_TYPE_ETH,
1179         RTE_FLOW_ITEM_TYPE_VLAN,
1180         RTE_FLOW_ITEM_TYPE_IPV4,
1181         RTE_FLOW_ITEM_TYPE_VF,
1182         RTE_FLOW_ITEM_TYPE_END,
1183 };
1184
1185 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1186         RTE_FLOW_ITEM_TYPE_ETH,
1187         RTE_FLOW_ITEM_TYPE_VLAN,
1188         RTE_FLOW_ITEM_TYPE_IPV4,
1189         RTE_FLOW_ITEM_TYPE_UDP,
1190         RTE_FLOW_ITEM_TYPE_VF,
1191         RTE_FLOW_ITEM_TYPE_END,
1192 };
1193
1194 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1195         RTE_FLOW_ITEM_TYPE_ETH,
1196         RTE_FLOW_ITEM_TYPE_VLAN,
1197         RTE_FLOW_ITEM_TYPE_IPV4,
1198         RTE_FLOW_ITEM_TYPE_TCP,
1199         RTE_FLOW_ITEM_TYPE_VF,
1200         RTE_FLOW_ITEM_TYPE_END,
1201 };
1202
1203 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1204         RTE_FLOW_ITEM_TYPE_ETH,
1205         RTE_FLOW_ITEM_TYPE_VLAN,
1206         RTE_FLOW_ITEM_TYPE_IPV4,
1207         RTE_FLOW_ITEM_TYPE_SCTP,
1208         RTE_FLOW_ITEM_TYPE_VF,
1209         RTE_FLOW_ITEM_TYPE_END,
1210 };
1211
1212 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1213         RTE_FLOW_ITEM_TYPE_ETH,
1214         RTE_FLOW_ITEM_TYPE_VLAN,
1215         RTE_FLOW_ITEM_TYPE_IPV6,
1216         RTE_FLOW_ITEM_TYPE_VF,
1217         RTE_FLOW_ITEM_TYPE_END,
1218 };
1219
1220 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1221         RTE_FLOW_ITEM_TYPE_ETH,
1222         RTE_FLOW_ITEM_TYPE_VLAN,
1223         RTE_FLOW_ITEM_TYPE_IPV6,
1224         RTE_FLOW_ITEM_TYPE_UDP,
1225         RTE_FLOW_ITEM_TYPE_VF,
1226         RTE_FLOW_ITEM_TYPE_END,
1227 };
1228
1229 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1230         RTE_FLOW_ITEM_TYPE_ETH,
1231         RTE_FLOW_ITEM_TYPE_VLAN,
1232         RTE_FLOW_ITEM_TYPE_IPV6,
1233         RTE_FLOW_ITEM_TYPE_TCP,
1234         RTE_FLOW_ITEM_TYPE_VF,
1235         RTE_FLOW_ITEM_TYPE_END,
1236 };
1237
1238 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1239         RTE_FLOW_ITEM_TYPE_ETH,
1240         RTE_FLOW_ITEM_TYPE_VLAN,
1241         RTE_FLOW_ITEM_TYPE_IPV6,
1242         RTE_FLOW_ITEM_TYPE_SCTP,
1243         RTE_FLOW_ITEM_TYPE_VF,
1244         RTE_FLOW_ITEM_TYPE_END,
1245 };
1246
1247 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1248         RTE_FLOW_ITEM_TYPE_ETH,
1249         RTE_FLOW_ITEM_TYPE_VLAN,
1250         RTE_FLOW_ITEM_TYPE_RAW,
1251         RTE_FLOW_ITEM_TYPE_VF,
1252         RTE_FLOW_ITEM_TYPE_END,
1253 };
1254
1255 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1256         RTE_FLOW_ITEM_TYPE_ETH,
1257         RTE_FLOW_ITEM_TYPE_VLAN,
1258         RTE_FLOW_ITEM_TYPE_RAW,
1259         RTE_FLOW_ITEM_TYPE_RAW,
1260         RTE_FLOW_ITEM_TYPE_VF,
1261         RTE_FLOW_ITEM_TYPE_END,
1262 };
1263
1264 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1265         RTE_FLOW_ITEM_TYPE_ETH,
1266         RTE_FLOW_ITEM_TYPE_VLAN,
1267         RTE_FLOW_ITEM_TYPE_RAW,
1268         RTE_FLOW_ITEM_TYPE_RAW,
1269         RTE_FLOW_ITEM_TYPE_RAW,
1270         RTE_FLOW_ITEM_TYPE_VF,
1271         RTE_FLOW_ITEM_TYPE_END,
1272 };
1273
1274 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1275         RTE_FLOW_ITEM_TYPE_ETH,
1276         RTE_FLOW_ITEM_TYPE_VLAN,
1277         RTE_FLOW_ITEM_TYPE_IPV4,
1278         RTE_FLOW_ITEM_TYPE_RAW,
1279         RTE_FLOW_ITEM_TYPE_VF,
1280         RTE_FLOW_ITEM_TYPE_END,
1281 };
1282
1283 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1284         RTE_FLOW_ITEM_TYPE_ETH,
1285         RTE_FLOW_ITEM_TYPE_VLAN,
1286         RTE_FLOW_ITEM_TYPE_IPV4,
1287         RTE_FLOW_ITEM_TYPE_RAW,
1288         RTE_FLOW_ITEM_TYPE_RAW,
1289         RTE_FLOW_ITEM_TYPE_VF,
1290         RTE_FLOW_ITEM_TYPE_END,
1291 };
1292
1293 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1294         RTE_FLOW_ITEM_TYPE_ETH,
1295         RTE_FLOW_ITEM_TYPE_VLAN,
1296         RTE_FLOW_ITEM_TYPE_IPV4,
1297         RTE_FLOW_ITEM_TYPE_RAW,
1298         RTE_FLOW_ITEM_TYPE_RAW,
1299         RTE_FLOW_ITEM_TYPE_RAW,
1300         RTE_FLOW_ITEM_TYPE_VF,
1301         RTE_FLOW_ITEM_TYPE_END,
1302 };
1303
1304 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1305         RTE_FLOW_ITEM_TYPE_ETH,
1306         RTE_FLOW_ITEM_TYPE_VLAN,
1307         RTE_FLOW_ITEM_TYPE_IPV4,
1308         RTE_FLOW_ITEM_TYPE_UDP,
1309         RTE_FLOW_ITEM_TYPE_RAW,
1310         RTE_FLOW_ITEM_TYPE_VF,
1311         RTE_FLOW_ITEM_TYPE_END,
1312 };
1313
1314 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1315         RTE_FLOW_ITEM_TYPE_ETH,
1316         RTE_FLOW_ITEM_TYPE_VLAN,
1317         RTE_FLOW_ITEM_TYPE_IPV4,
1318         RTE_FLOW_ITEM_TYPE_UDP,
1319         RTE_FLOW_ITEM_TYPE_RAW,
1320         RTE_FLOW_ITEM_TYPE_RAW,
1321         RTE_FLOW_ITEM_TYPE_VF,
1322         RTE_FLOW_ITEM_TYPE_END,
1323 };
1324
1325 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1326         RTE_FLOW_ITEM_TYPE_ETH,
1327         RTE_FLOW_ITEM_TYPE_VLAN,
1328         RTE_FLOW_ITEM_TYPE_IPV4,
1329         RTE_FLOW_ITEM_TYPE_UDP,
1330         RTE_FLOW_ITEM_TYPE_RAW,
1331         RTE_FLOW_ITEM_TYPE_RAW,
1332         RTE_FLOW_ITEM_TYPE_RAW,
1333         RTE_FLOW_ITEM_TYPE_VF,
1334         RTE_FLOW_ITEM_TYPE_END,
1335 };
1336
1337 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1338         RTE_FLOW_ITEM_TYPE_ETH,
1339         RTE_FLOW_ITEM_TYPE_VLAN,
1340         RTE_FLOW_ITEM_TYPE_IPV4,
1341         RTE_FLOW_ITEM_TYPE_TCP,
1342         RTE_FLOW_ITEM_TYPE_RAW,
1343         RTE_FLOW_ITEM_TYPE_VF,
1344         RTE_FLOW_ITEM_TYPE_END,
1345 };
1346
1347 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1348         RTE_FLOW_ITEM_TYPE_ETH,
1349         RTE_FLOW_ITEM_TYPE_VLAN,
1350         RTE_FLOW_ITEM_TYPE_IPV4,
1351         RTE_FLOW_ITEM_TYPE_TCP,
1352         RTE_FLOW_ITEM_TYPE_RAW,
1353         RTE_FLOW_ITEM_TYPE_RAW,
1354         RTE_FLOW_ITEM_TYPE_VF,
1355         RTE_FLOW_ITEM_TYPE_END,
1356 };
1357
1358 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1359         RTE_FLOW_ITEM_TYPE_ETH,
1360         RTE_FLOW_ITEM_TYPE_VLAN,
1361         RTE_FLOW_ITEM_TYPE_IPV4,
1362         RTE_FLOW_ITEM_TYPE_TCP,
1363         RTE_FLOW_ITEM_TYPE_RAW,
1364         RTE_FLOW_ITEM_TYPE_RAW,
1365         RTE_FLOW_ITEM_TYPE_RAW,
1366         RTE_FLOW_ITEM_TYPE_VF,
1367         RTE_FLOW_ITEM_TYPE_END,
1368 };
1369
1370 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1371         RTE_FLOW_ITEM_TYPE_ETH,
1372         RTE_FLOW_ITEM_TYPE_VLAN,
1373         RTE_FLOW_ITEM_TYPE_IPV4,
1374         RTE_FLOW_ITEM_TYPE_SCTP,
1375         RTE_FLOW_ITEM_TYPE_RAW,
1376         RTE_FLOW_ITEM_TYPE_VF,
1377         RTE_FLOW_ITEM_TYPE_END,
1378 };
1379
1380 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1381         RTE_FLOW_ITEM_TYPE_ETH,
1382         RTE_FLOW_ITEM_TYPE_VLAN,
1383         RTE_FLOW_ITEM_TYPE_IPV4,
1384         RTE_FLOW_ITEM_TYPE_SCTP,
1385         RTE_FLOW_ITEM_TYPE_RAW,
1386         RTE_FLOW_ITEM_TYPE_RAW,
1387         RTE_FLOW_ITEM_TYPE_VF,
1388         RTE_FLOW_ITEM_TYPE_END,
1389 };
1390
1391 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1392         RTE_FLOW_ITEM_TYPE_ETH,
1393         RTE_FLOW_ITEM_TYPE_VLAN,
1394         RTE_FLOW_ITEM_TYPE_IPV4,
1395         RTE_FLOW_ITEM_TYPE_SCTP,
1396         RTE_FLOW_ITEM_TYPE_RAW,
1397         RTE_FLOW_ITEM_TYPE_RAW,
1398         RTE_FLOW_ITEM_TYPE_RAW,
1399         RTE_FLOW_ITEM_TYPE_VF,
1400         RTE_FLOW_ITEM_TYPE_END,
1401 };
1402
1403 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1404         RTE_FLOW_ITEM_TYPE_ETH,
1405         RTE_FLOW_ITEM_TYPE_VLAN,
1406         RTE_FLOW_ITEM_TYPE_IPV6,
1407         RTE_FLOW_ITEM_TYPE_RAW,
1408         RTE_FLOW_ITEM_TYPE_VF,
1409         RTE_FLOW_ITEM_TYPE_END,
1410 };
1411
1412 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1413         RTE_FLOW_ITEM_TYPE_ETH,
1414         RTE_FLOW_ITEM_TYPE_VLAN,
1415         RTE_FLOW_ITEM_TYPE_IPV6,
1416         RTE_FLOW_ITEM_TYPE_RAW,
1417         RTE_FLOW_ITEM_TYPE_RAW,
1418         RTE_FLOW_ITEM_TYPE_VF,
1419         RTE_FLOW_ITEM_TYPE_END,
1420 };
1421
1422 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1423         RTE_FLOW_ITEM_TYPE_ETH,
1424         RTE_FLOW_ITEM_TYPE_VLAN,
1425         RTE_FLOW_ITEM_TYPE_IPV6,
1426         RTE_FLOW_ITEM_TYPE_RAW,
1427         RTE_FLOW_ITEM_TYPE_RAW,
1428         RTE_FLOW_ITEM_TYPE_RAW,
1429         RTE_FLOW_ITEM_TYPE_VF,
1430         RTE_FLOW_ITEM_TYPE_END,
1431 };
1432
1433 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1434         RTE_FLOW_ITEM_TYPE_ETH,
1435         RTE_FLOW_ITEM_TYPE_VLAN,
1436         RTE_FLOW_ITEM_TYPE_IPV6,
1437         RTE_FLOW_ITEM_TYPE_UDP,
1438         RTE_FLOW_ITEM_TYPE_RAW,
1439         RTE_FLOW_ITEM_TYPE_VF,
1440         RTE_FLOW_ITEM_TYPE_END,
1441 };
1442
1443 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1444         RTE_FLOW_ITEM_TYPE_ETH,
1445         RTE_FLOW_ITEM_TYPE_VLAN,
1446         RTE_FLOW_ITEM_TYPE_IPV6,
1447         RTE_FLOW_ITEM_TYPE_UDP,
1448         RTE_FLOW_ITEM_TYPE_RAW,
1449         RTE_FLOW_ITEM_TYPE_RAW,
1450         RTE_FLOW_ITEM_TYPE_VF,
1451         RTE_FLOW_ITEM_TYPE_END,
1452 };
1453
1454 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1455         RTE_FLOW_ITEM_TYPE_ETH,
1456         RTE_FLOW_ITEM_TYPE_VLAN,
1457         RTE_FLOW_ITEM_TYPE_IPV6,
1458         RTE_FLOW_ITEM_TYPE_UDP,
1459         RTE_FLOW_ITEM_TYPE_RAW,
1460         RTE_FLOW_ITEM_TYPE_RAW,
1461         RTE_FLOW_ITEM_TYPE_RAW,
1462         RTE_FLOW_ITEM_TYPE_VF,
1463         RTE_FLOW_ITEM_TYPE_END,
1464 };
1465
1466 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1467         RTE_FLOW_ITEM_TYPE_ETH,
1468         RTE_FLOW_ITEM_TYPE_VLAN,
1469         RTE_FLOW_ITEM_TYPE_IPV6,
1470         RTE_FLOW_ITEM_TYPE_TCP,
1471         RTE_FLOW_ITEM_TYPE_RAW,
1472         RTE_FLOW_ITEM_TYPE_VF,
1473         RTE_FLOW_ITEM_TYPE_END,
1474 };
1475
1476 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1477         RTE_FLOW_ITEM_TYPE_ETH,
1478         RTE_FLOW_ITEM_TYPE_VLAN,
1479         RTE_FLOW_ITEM_TYPE_IPV6,
1480         RTE_FLOW_ITEM_TYPE_TCP,
1481         RTE_FLOW_ITEM_TYPE_RAW,
1482         RTE_FLOW_ITEM_TYPE_RAW,
1483         RTE_FLOW_ITEM_TYPE_VF,
1484         RTE_FLOW_ITEM_TYPE_END,
1485 };
1486
1487 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1488         RTE_FLOW_ITEM_TYPE_ETH,
1489         RTE_FLOW_ITEM_TYPE_VLAN,
1490         RTE_FLOW_ITEM_TYPE_IPV6,
1491         RTE_FLOW_ITEM_TYPE_TCP,
1492         RTE_FLOW_ITEM_TYPE_RAW,
1493         RTE_FLOW_ITEM_TYPE_RAW,
1494         RTE_FLOW_ITEM_TYPE_RAW,
1495         RTE_FLOW_ITEM_TYPE_VF,
1496         RTE_FLOW_ITEM_TYPE_END,
1497 };
1498
1499 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1500         RTE_FLOW_ITEM_TYPE_ETH,
1501         RTE_FLOW_ITEM_TYPE_VLAN,
1502         RTE_FLOW_ITEM_TYPE_IPV6,
1503         RTE_FLOW_ITEM_TYPE_SCTP,
1504         RTE_FLOW_ITEM_TYPE_RAW,
1505         RTE_FLOW_ITEM_TYPE_VF,
1506         RTE_FLOW_ITEM_TYPE_END,
1507 };
1508
1509 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1510         RTE_FLOW_ITEM_TYPE_ETH,
1511         RTE_FLOW_ITEM_TYPE_VLAN,
1512         RTE_FLOW_ITEM_TYPE_IPV6,
1513         RTE_FLOW_ITEM_TYPE_SCTP,
1514         RTE_FLOW_ITEM_TYPE_RAW,
1515         RTE_FLOW_ITEM_TYPE_RAW,
1516         RTE_FLOW_ITEM_TYPE_VF,
1517         RTE_FLOW_ITEM_TYPE_END,
1518 };
1519
1520 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1521         RTE_FLOW_ITEM_TYPE_ETH,
1522         RTE_FLOW_ITEM_TYPE_VLAN,
1523         RTE_FLOW_ITEM_TYPE_IPV6,
1524         RTE_FLOW_ITEM_TYPE_SCTP,
1525         RTE_FLOW_ITEM_TYPE_RAW,
1526         RTE_FLOW_ITEM_TYPE_RAW,
1527         RTE_FLOW_ITEM_TYPE_RAW,
1528         RTE_FLOW_ITEM_TYPE_VF,
1529         RTE_FLOW_ITEM_TYPE_END,
1530 };
1531
1532 /* Pattern matched tunnel filter */
1533 static enum rte_flow_item_type pattern_vxlan_1[] = {
1534         RTE_FLOW_ITEM_TYPE_ETH,
1535         RTE_FLOW_ITEM_TYPE_IPV4,
1536         RTE_FLOW_ITEM_TYPE_UDP,
1537         RTE_FLOW_ITEM_TYPE_VXLAN,
1538         RTE_FLOW_ITEM_TYPE_ETH,
1539         RTE_FLOW_ITEM_TYPE_END,
1540 };
1541
1542 static enum rte_flow_item_type pattern_vxlan_2[] = {
1543         RTE_FLOW_ITEM_TYPE_ETH,
1544         RTE_FLOW_ITEM_TYPE_IPV6,
1545         RTE_FLOW_ITEM_TYPE_UDP,
1546         RTE_FLOW_ITEM_TYPE_VXLAN,
1547         RTE_FLOW_ITEM_TYPE_ETH,
1548         RTE_FLOW_ITEM_TYPE_END,
1549 };
1550
1551 static enum rte_flow_item_type pattern_vxlan_3[] = {
1552         RTE_FLOW_ITEM_TYPE_ETH,
1553         RTE_FLOW_ITEM_TYPE_IPV4,
1554         RTE_FLOW_ITEM_TYPE_UDP,
1555         RTE_FLOW_ITEM_TYPE_VXLAN,
1556         RTE_FLOW_ITEM_TYPE_ETH,
1557         RTE_FLOW_ITEM_TYPE_VLAN,
1558         RTE_FLOW_ITEM_TYPE_END,
1559 };
1560
1561 static enum rte_flow_item_type pattern_vxlan_4[] = {
1562         RTE_FLOW_ITEM_TYPE_ETH,
1563         RTE_FLOW_ITEM_TYPE_IPV6,
1564         RTE_FLOW_ITEM_TYPE_UDP,
1565         RTE_FLOW_ITEM_TYPE_VXLAN,
1566         RTE_FLOW_ITEM_TYPE_ETH,
1567         RTE_FLOW_ITEM_TYPE_VLAN,
1568         RTE_FLOW_ITEM_TYPE_END,
1569 };
1570
1571 static enum rte_flow_item_type pattern_nvgre_1[] = {
1572         RTE_FLOW_ITEM_TYPE_ETH,
1573         RTE_FLOW_ITEM_TYPE_IPV4,
1574         RTE_FLOW_ITEM_TYPE_NVGRE,
1575         RTE_FLOW_ITEM_TYPE_ETH,
1576         RTE_FLOW_ITEM_TYPE_END,
1577 };
1578
1579 static enum rte_flow_item_type pattern_nvgre_2[] = {
1580         RTE_FLOW_ITEM_TYPE_ETH,
1581         RTE_FLOW_ITEM_TYPE_IPV6,
1582         RTE_FLOW_ITEM_TYPE_NVGRE,
1583         RTE_FLOW_ITEM_TYPE_ETH,
1584         RTE_FLOW_ITEM_TYPE_END,
1585 };
1586
1587 static enum rte_flow_item_type pattern_nvgre_3[] = {
1588         RTE_FLOW_ITEM_TYPE_ETH,
1589         RTE_FLOW_ITEM_TYPE_IPV4,
1590         RTE_FLOW_ITEM_TYPE_NVGRE,
1591         RTE_FLOW_ITEM_TYPE_ETH,
1592         RTE_FLOW_ITEM_TYPE_VLAN,
1593         RTE_FLOW_ITEM_TYPE_END,
1594 };
1595
1596 static enum rte_flow_item_type pattern_nvgre_4[] = {
1597         RTE_FLOW_ITEM_TYPE_ETH,
1598         RTE_FLOW_ITEM_TYPE_IPV6,
1599         RTE_FLOW_ITEM_TYPE_NVGRE,
1600         RTE_FLOW_ITEM_TYPE_ETH,
1601         RTE_FLOW_ITEM_TYPE_VLAN,
1602         RTE_FLOW_ITEM_TYPE_END,
1603 };
1604
1605 static enum rte_flow_item_type pattern_mpls_1[] = {
1606         RTE_FLOW_ITEM_TYPE_ETH,
1607         RTE_FLOW_ITEM_TYPE_IPV4,
1608         RTE_FLOW_ITEM_TYPE_UDP,
1609         RTE_FLOW_ITEM_TYPE_MPLS,
1610         RTE_FLOW_ITEM_TYPE_END,
1611 };
1612
1613 static enum rte_flow_item_type pattern_mpls_2[] = {
1614         RTE_FLOW_ITEM_TYPE_ETH,
1615         RTE_FLOW_ITEM_TYPE_IPV6,
1616         RTE_FLOW_ITEM_TYPE_UDP,
1617         RTE_FLOW_ITEM_TYPE_MPLS,
1618         RTE_FLOW_ITEM_TYPE_END,
1619 };
1620
1621 static enum rte_flow_item_type pattern_mpls_3[] = {
1622         RTE_FLOW_ITEM_TYPE_ETH,
1623         RTE_FLOW_ITEM_TYPE_IPV4,
1624         RTE_FLOW_ITEM_TYPE_GRE,
1625         RTE_FLOW_ITEM_TYPE_MPLS,
1626         RTE_FLOW_ITEM_TYPE_END,
1627 };
1628
1629 static enum rte_flow_item_type pattern_mpls_4[] = {
1630         RTE_FLOW_ITEM_TYPE_ETH,
1631         RTE_FLOW_ITEM_TYPE_IPV6,
1632         RTE_FLOW_ITEM_TYPE_GRE,
1633         RTE_FLOW_ITEM_TYPE_MPLS,
1634         RTE_FLOW_ITEM_TYPE_END,
1635 };
1636
1637 static enum rte_flow_item_type pattern_qinq_1[] = {
1638         RTE_FLOW_ITEM_TYPE_ETH,
1639         RTE_FLOW_ITEM_TYPE_VLAN,
1640         RTE_FLOW_ITEM_TYPE_VLAN,
1641         RTE_FLOW_ITEM_TYPE_END,
1642 };
1643
1644 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1645         /* Ethertype */
1646         { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1647         /* FDIR - support default flow type without flexible payload*/
1648         { pattern_ethertype, i40e_flow_parse_fdir_filter },
1649         { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1650         { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1651         { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1652         { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1653         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter },
1654         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter },
1655         { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1656         { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1657         { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1658         { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1659         { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1660         { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1661         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter },
1662         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter },
1663         { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1664         { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1665         /* FDIR - support default flow type with flexible payload */
1666         { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1667         { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1668         { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1669         { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1670         { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1671         { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1672         { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1673         { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1674         { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1675         { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1676         { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1677         { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1678         { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1679         { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1680         { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1681         { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1682         { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1683         { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1684         { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1685         { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1686         { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1687         { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1688         { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1689         { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1690         { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1691         { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1692         { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1693         /* FDIR - support single vlan input set */
1694         { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1695         { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1696         { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1697         { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1698         { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1699         { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1700         { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1701         { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1702         { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1703         { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1704         { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1705         { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1706         { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1707         { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1708         { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1709         { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1710         { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1711         { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1712         { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1713         { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1714         { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1715         { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1716         { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1717         { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1718         { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1719         { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1720         { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1721         { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1722         { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1723         { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1724         { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1725         { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1726         { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1727         { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1728         { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1729         { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1730         /* FDIR - support VF item */
1731         { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1732         { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1733         { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1734         { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1735         { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1736         { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1737         { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1738         { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1739         { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1740         { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1741         { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1742         { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1743         { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1744         { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1745         { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1746         { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1747         { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1748         { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1749         { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1750         { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1751         { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1752         { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1753         { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1754         { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1755         { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1756         { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1757         { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1758         { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1759         { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1760         { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1761         { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1762         { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1763         { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1764         { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1765         { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1766         { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1767         { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1768         { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1769         { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1770         { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1771         { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1772         { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1773         { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1774         { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1775         { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1776         { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1777         { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1778         { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1779         { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1780         { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1781         { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1782         { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1783         { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1784         { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1785         { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1786         { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1787         { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1788         { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1789         { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1790         { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1791         { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1792         { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1793         { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1794         { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1795         { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1796         { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1797         { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1798         { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1799         { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1800         { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1801         { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1802         /* VXLAN */
1803         { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1804         { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1805         { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1806         { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1807         /* NVGRE */
1808         { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1809         { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1810         { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1811         { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1812         /* MPLSoUDP & MPLSoGRE */
1813         { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1814         { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1815         { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1816         { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1817         /* GTP-C & GTP-U */
1818         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter },
1819         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter },
1820         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter },
1821         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter },
1822         /* QINQ */
1823         { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1824 };
1825
1826 #define NEXT_ITEM_OF_ACTION(act, actions, index)                        \
1827         do {                                                            \
1828                 act = actions + index;                                  \
1829                 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) {        \
1830                         index++;                                        \
1831                         act = actions + index;                          \
1832                 }                                                       \
1833         } while (0)
1834
1835 /* Find the first VOID or non-VOID item pointer */
1836 static const struct rte_flow_item *
1837 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1838 {
1839         bool is_find;
1840
1841         while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1842                 if (is_void)
1843                         is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1844                 else
1845                         is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1846                 if (is_find)
1847                         break;
1848                 item++;
1849         }
1850         return item;
1851 }
1852
1853 /* Skip all VOID items of the pattern */
1854 static void
1855 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1856                             const struct rte_flow_item *pattern)
1857 {
1858         uint32_t cpy_count = 0;
1859         const struct rte_flow_item *pb = pattern, *pe = pattern;
1860
1861         for (;;) {
1862                 /* Find a non-void item first */
1863                 pb = i40e_find_first_item(pb, false);
1864                 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1865                         pe = pb;
1866                         break;
1867                 }
1868
1869                 /* Find a void item */
1870                 pe = i40e_find_first_item(pb + 1, true);
1871
1872                 cpy_count = pe - pb;
1873                 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1874
1875                 items += cpy_count;
1876
1877                 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1878                         pb = pe;
1879                         break;
1880                 }
1881
1882                 pb = pe + 1;
1883         }
1884         /* Copy the END item. */
1885         rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1886 }
1887
1888 /* Check if the pattern matches a supported item type array */
1889 static bool
1890 i40e_match_pattern(enum rte_flow_item_type *item_array,
1891                    struct rte_flow_item *pattern)
1892 {
1893         struct rte_flow_item *item = pattern;
1894
1895         while ((*item_array == item->type) &&
1896                (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1897                 item_array++;
1898                 item++;
1899         }
1900
1901         return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1902                 item->type == RTE_FLOW_ITEM_TYPE_END);
1903 }
1904
1905 /* Find if there's parse filter function matched */
1906 static parse_filter_t
1907 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1908 {
1909         parse_filter_t parse_filter = NULL;
1910         uint8_t i = *idx;
1911
1912         for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1913                 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1914                                         pattern)) {
1915                         parse_filter = i40e_supported_patterns[i].parse_filter;
1916                         break;
1917                 }
1918         }
1919
1920         *idx = ++i;
1921
1922         return parse_filter;
1923 }
1924
1925 /* Parse attributes */
1926 static int
1927 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1928                      struct rte_flow_error *error)
1929 {
1930         /* Must be input direction */
1931         if (!attr->ingress) {
1932                 rte_flow_error_set(error, EINVAL,
1933                                    RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1934                                    attr, "Only support ingress.");
1935                 return -rte_errno;
1936         }
1937
1938         /* Not supported */
1939         if (attr->egress) {
1940                 rte_flow_error_set(error, EINVAL,
1941                                    RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1942                                    attr, "Not support egress.");
1943                 return -rte_errno;
1944         }
1945
1946         /* Not supported */
1947         if (attr->priority) {
1948                 rte_flow_error_set(error, EINVAL,
1949                                    RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1950                                    attr, "Not support priority.");
1951                 return -rte_errno;
1952         }
1953
1954         /* Not supported */
1955         if (attr->group) {
1956                 rte_flow_error_set(error, EINVAL,
1957                                    RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
1958                                    attr, "Not support group.");
1959                 return -rte_errno;
1960         }
1961
1962         return 0;
1963 }
1964
1965 static uint16_t
1966 i40e_get_outer_vlan(struct rte_eth_dev *dev)
1967 {
1968         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1969         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
1970         uint64_t reg_r = 0;
1971         uint16_t reg_id;
1972         uint16_t tpid;
1973
1974         if (qinq)
1975                 reg_id = 2;
1976         else
1977                 reg_id = 3;
1978
1979         i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
1980                                     &reg_r, NULL);
1981
1982         tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
1983
1984         return tpid;
1985 }
1986
1987 /* 1. Last in item should be NULL as range is not supported.
1988  * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
1989  * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
1990  * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
1991  *    FF:FF:FF:FF:FF:FF
1992  * 5. Ether_type mask should be 0xFFFF.
1993  */
1994 static int
1995 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
1996                                   const struct rte_flow_item *pattern,
1997                                   struct rte_flow_error *error,
1998                                   struct rte_eth_ethertype_filter *filter)
1999 {
2000         const struct rte_flow_item *item = pattern;
2001         const struct rte_flow_item_eth *eth_spec;
2002         const struct rte_flow_item_eth *eth_mask;
2003         enum rte_flow_item_type item_type;
2004         uint16_t outer_tpid;
2005
2006         outer_tpid = i40e_get_outer_vlan(dev);
2007
2008         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2009                 if (item->last) {
2010                         rte_flow_error_set(error, EINVAL,
2011                                            RTE_FLOW_ERROR_TYPE_ITEM,
2012                                            item,
2013                                            "Not support range");
2014                         return -rte_errno;
2015                 }
2016                 item_type = item->type;
2017                 switch (item_type) {
2018                 case RTE_FLOW_ITEM_TYPE_ETH:
2019                         eth_spec = (const struct rte_flow_item_eth *)item->spec;
2020                         eth_mask = (const struct rte_flow_item_eth *)item->mask;
2021                         /* Get the MAC info. */
2022                         if (!eth_spec || !eth_mask) {
2023                                 rte_flow_error_set(error, EINVAL,
2024                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2025                                                    item,
2026                                                    "NULL ETH spec/mask");
2027                                 return -rte_errno;
2028                         }
2029
2030                         /* Mask bits of source MAC address must be full of 0.
2031                          * Mask bits of destination MAC address must be full
2032                          * of 1 or full of 0.
2033                          */
2034                         if (!is_zero_ether_addr(&eth_mask->src) ||
2035                             (!is_zero_ether_addr(&eth_mask->dst) &&
2036                              !is_broadcast_ether_addr(&eth_mask->dst))) {
2037                                 rte_flow_error_set(error, EINVAL,
2038                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2039                                                    item,
2040                                                    "Invalid MAC_addr mask");
2041                                 return -rte_errno;
2042                         }
2043
2044                         if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
2045                                 rte_flow_error_set(error, EINVAL,
2046                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2047                                                    item,
2048                                                    "Invalid ethertype mask");
2049                                 return -rte_errno;
2050                         }
2051
2052                         /* If mask bits of destination MAC address
2053                          * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
2054                          */
2055                         if (is_broadcast_ether_addr(&eth_mask->dst)) {
2056                                 filter->mac_addr = eth_spec->dst;
2057                                 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
2058                         } else {
2059                                 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
2060                         }
2061                         filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
2062
2063                         if (filter->ether_type == ETHER_TYPE_IPv4 ||
2064                             filter->ether_type == ETHER_TYPE_IPv6 ||
2065                             filter->ether_type == ETHER_TYPE_LLDP ||
2066                             filter->ether_type == outer_tpid) {
2067                                 rte_flow_error_set(error, EINVAL,
2068                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2069                                                    item,
2070                                                    "Unsupported ether_type in"
2071                                                    " control packet filter.");
2072                                 return -rte_errno;
2073                         }
2074                         break;
2075                 default:
2076                         break;
2077                 }
2078         }
2079
2080         return 0;
2081 }
2082
2083 /* Ethertype action only supports QUEUE or DROP. */
2084 static int
2085 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
2086                                  const struct rte_flow_action *actions,
2087                                  struct rte_flow_error *error,
2088                                  struct rte_eth_ethertype_filter *filter)
2089 {
2090         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2091         const struct rte_flow_action *act;
2092         const struct rte_flow_action_queue *act_q;
2093         uint32_t index = 0;
2094
2095         /* Check if the first non-void action is QUEUE or DROP. */
2096         NEXT_ITEM_OF_ACTION(act, actions, index);
2097         if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2098             act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2099                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2100                                    act, "Not supported action.");
2101                 return -rte_errno;
2102         }
2103
2104         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2105                 act_q = (const struct rte_flow_action_queue *)act->conf;
2106                 filter->queue = act_q->index;
2107                 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2108                         rte_flow_error_set(error, EINVAL,
2109                                            RTE_FLOW_ERROR_TYPE_ACTION,
2110                                            act, "Invalid queue ID for"
2111                                            " ethertype_filter.");
2112                         return -rte_errno;
2113                 }
2114         } else {
2115                 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2116         }
2117
2118         /* Check if the next non-void item is END */
2119         index++;
2120         NEXT_ITEM_OF_ACTION(act, actions, index);
2121         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2122                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2123                                    act, "Not supported action.");
2124                 return -rte_errno;
2125         }
2126
2127         return 0;
2128 }
2129
2130 static int
2131 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2132                                  const struct rte_flow_attr *attr,
2133                                  const struct rte_flow_item pattern[],
2134                                  const struct rte_flow_action actions[],
2135                                  struct rte_flow_error *error,
2136                                  union i40e_filter_t *filter)
2137 {
2138         struct rte_eth_ethertype_filter *ethertype_filter =
2139                 &filter->ethertype_filter;
2140         int ret;
2141
2142         ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2143                                                 ethertype_filter);
2144         if (ret)
2145                 return ret;
2146
2147         ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2148                                                ethertype_filter);
2149         if (ret)
2150                 return ret;
2151
2152         ret = i40e_flow_parse_attr(attr, error);
2153         if (ret)
2154                 return ret;
2155
2156         cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2157
2158         return ret;
2159 }
2160
2161 static int
2162 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2163                          const struct rte_flow_item_raw *raw_spec,
2164                          struct rte_flow_error *error)
2165 {
2166         if (!raw_spec->relative) {
2167                 rte_flow_error_set(error, EINVAL,
2168                                    RTE_FLOW_ERROR_TYPE_ITEM,
2169                                    item,
2170                                    "Relative should be 1.");
2171                 return -rte_errno;
2172         }
2173
2174         if (raw_spec->offset % sizeof(uint16_t)) {
2175                 rte_flow_error_set(error, EINVAL,
2176                                    RTE_FLOW_ERROR_TYPE_ITEM,
2177                                    item,
2178                                    "Offset should be even.");
2179                 return -rte_errno;
2180         }
2181
2182         if (raw_spec->search || raw_spec->limit) {
2183                 rte_flow_error_set(error, EINVAL,
2184                                    RTE_FLOW_ERROR_TYPE_ITEM,
2185                                    item,
2186                                    "search or limit is not supported.");
2187                 return -rte_errno;
2188         }
2189
2190         if (raw_spec->offset < 0) {
2191                 rte_flow_error_set(error, EINVAL,
2192                                    RTE_FLOW_ERROR_TYPE_ITEM,
2193                                    item,
2194                                    "Offset should be non-negative.");
2195                 return -rte_errno;
2196         }
2197         return 0;
2198 }
2199
2200 static int
2201 i40e_flow_store_flex_pit(struct i40e_pf *pf,
2202                          struct i40e_fdir_flex_pit *flex_pit,
2203                          enum i40e_flxpld_layer_idx layer_idx,
2204                          uint8_t raw_id)
2205 {
2206         uint8_t field_idx;
2207
2208         field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
2209         /* Check if the configuration is conflicted */
2210         if (pf->fdir.flex_pit_flag[layer_idx] &&
2211             (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||
2212              pf->fdir.flex_set[field_idx].size != flex_pit->size ||
2213              pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))
2214                 return -1;
2215
2216         /* Check if the configuration exists. */
2217         if (pf->fdir.flex_pit_flag[layer_idx] &&
2218             (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&
2219              pf->fdir.flex_set[field_idx].size == flex_pit->size &&
2220              pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))
2221                 return 1;
2222
2223         pf->fdir.flex_set[field_idx].src_offset =
2224                 flex_pit->src_offset;
2225         pf->fdir.flex_set[field_idx].size =
2226                 flex_pit->size;
2227         pf->fdir.flex_set[field_idx].dst_offset =
2228                 flex_pit->dst_offset;
2229
2230         return 0;
2231 }
2232
2233 static int
2234 i40e_flow_store_flex_mask(struct i40e_pf *pf,
2235                           enum i40e_filter_pctype pctype,
2236                           uint8_t *mask)
2237 {
2238         struct i40e_fdir_flex_mask flex_mask;
2239         uint16_t mask_tmp;
2240         uint8_t i, nb_bitmask = 0;
2241
2242         memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
2243         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
2244                 mask_tmp = I40E_WORD(mask[i], mask[i + 1]);
2245                 if (mask_tmp) {
2246                         flex_mask.word_mask |=
2247                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
2248                         if (mask_tmp != UINT16_MAX) {
2249                                 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;
2250                                 flex_mask.bitmask[nb_bitmask].offset =
2251                                         i / sizeof(uint16_t);
2252                                 nb_bitmask++;
2253                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)
2254                                         return -1;
2255                         }
2256                 }
2257         }
2258         flex_mask.nb_bitmask = nb_bitmask;
2259
2260         if (pf->fdir.flex_mask_flag[pctype] &&
2261             (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2262                     sizeof(struct i40e_fdir_flex_mask))))
2263                 return -2;
2264         else if (pf->fdir.flex_mask_flag[pctype] &&
2265                  !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2266                           sizeof(struct i40e_fdir_flex_mask))))
2267                 return 1;
2268
2269         memcpy(&pf->fdir.flex_mask[pctype], &flex_mask,
2270                sizeof(struct i40e_fdir_flex_mask));
2271         return 0;
2272 }
2273
2274 static void
2275 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
2276                             enum i40e_flxpld_layer_idx layer_idx,
2277                             uint8_t raw_id)
2278 {
2279         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2280         uint32_t flx_pit;
2281         uint8_t field_idx;
2282         uint16_t min_next_off = 0;  /* in words */
2283         uint8_t i;
2284
2285         /* Set flex pit */
2286         for (i = 0; i < raw_id; i++) {
2287                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2288                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
2289                                      pf->fdir.flex_set[field_idx].size,
2290                                      pf->fdir.flex_set[field_idx].dst_offset);
2291
2292                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2293                 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
2294                         pf->fdir.flex_set[field_idx].size;
2295         }
2296
2297         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
2298                 /* set the non-used register obeying register's constrain */
2299                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2300                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
2301                                      NONUSE_FLX_PIT_DEST_OFF);
2302                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2303                 min_next_off++;
2304         }
2305
2306         pf->fdir.flex_pit_flag[layer_idx] = 1;
2307 }
2308
2309 static void
2310 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,
2311                             enum i40e_filter_pctype pctype)
2312 {
2313         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2314         struct i40e_fdir_flex_mask *flex_mask;
2315         uint32_t flxinset, fd_mask;
2316         uint8_t i;
2317
2318         /* Set flex mask */
2319         flex_mask = &pf->fdir.flex_mask[pctype];
2320         flxinset = (flex_mask->word_mask <<
2321                     I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
2322                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
2323         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
2324
2325         for (i = 0; i < flex_mask->nb_bitmask; i++) {
2326                 fd_mask = (flex_mask->bitmask[i].mask <<
2327                            I40E_PRTQF_FD_MSK_MASK_SHIFT) &
2328                         I40E_PRTQF_FD_MSK_MASK_MASK;
2329                 fd_mask |= ((flex_mask->bitmask[i].offset +
2330                              I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
2331                             I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
2332                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
2333                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
2334         }
2335
2336         pf->fdir.flex_mask_flag[pctype] = 1;
2337 }
2338
2339 static int
2340 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2341                          enum i40e_filter_pctype pctype,
2342                          uint64_t input_set)
2343 {
2344         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2345         uint64_t inset_reg = 0;
2346         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2347         int i, num;
2348
2349         /* Check if the input set is valid */
2350         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2351                                     input_set) != 0) {
2352                 PMD_DRV_LOG(ERR, "Invalid input set");
2353                 return -EINVAL;
2354         }
2355
2356         /* Check if the configuration is conflicted */
2357         if (pf->fdir.inset_flag[pctype] &&
2358             memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2359                 return -1;
2360
2361         if (pf->fdir.inset_flag[pctype] &&
2362             !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2363                 return 0;
2364
2365         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2366                                            I40E_INSET_MASK_NUM_REG);
2367         if (num < 0)
2368                 return -EINVAL;
2369
2370         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2371
2372         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2373                              (uint32_t)(inset_reg & UINT32_MAX));
2374         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2375                              (uint32_t)((inset_reg >>
2376                                          I40E_32_BIT_WIDTH) & UINT32_MAX));
2377
2378         for (i = 0; i < num; i++)
2379                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2380                                      mask_reg[i]);
2381
2382         /*clear unused mask registers of the pctype */
2383         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2384                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 0);
2385         I40E_WRITE_FLUSH(hw);
2386
2387         pf->fdir.input_set[pctype] = input_set;
2388         pf->fdir.inset_flag[pctype] = 1;
2389         return 0;
2390 }
2391
2392 static uint8_t
2393 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,
2394                                 enum rte_flow_item_type item_type,
2395                                 struct i40e_fdir_filter_conf *filter)
2396 {
2397         struct i40e_customized_pctype *cus_pctype = NULL;
2398
2399         switch (item_type) {
2400         case RTE_FLOW_ITEM_TYPE_GTPC:
2401                 cus_pctype = i40e_find_customized_pctype(pf,
2402                                                          I40E_CUSTOMIZED_GTPC);
2403                 break;
2404         case RTE_FLOW_ITEM_TYPE_GTPU:
2405                 if (!filter->input.flow_ext.inner_ip)
2406                         cus_pctype = i40e_find_customized_pctype(pf,
2407                                                          I40E_CUSTOMIZED_GTPU);
2408                 else if (filter->input.flow_ext.iip_type ==
2409                          I40E_FDIR_IPTYPE_IPV4)
2410                         cus_pctype = i40e_find_customized_pctype(pf,
2411                                                  I40E_CUSTOMIZED_GTPU_IPV4);
2412                 else if (filter->input.flow_ext.iip_type ==
2413                          I40E_FDIR_IPTYPE_IPV6)
2414                         cus_pctype = i40e_find_customized_pctype(pf,
2415                                                  I40E_CUSTOMIZED_GTPU_IPV6);
2416                 break;
2417         default:
2418                 PMD_DRV_LOG(ERR, "Unsupported item type");
2419                 break;
2420         }
2421
2422         if (cus_pctype)
2423                 return cus_pctype->pctype;
2424
2425         return I40E_FILTER_PCTYPE_INVALID;
2426 }
2427
2428 /* 1. Last in item should be NULL as range is not supported.
2429  * 2. Supported patterns: refer to array i40e_supported_patterns.
2430  * 3. Default supported flow type and input set: refer to array
2431  *    valid_fdir_inset_table in i40e_ethdev.c.
2432  * 4. Mask of fields which need to be matched should be
2433  *    filled with 1.
2434  * 5. Mask of fields which needn't to be matched should be
2435  *    filled with 0.
2436  * 6. GTP profile supports GTPv1 only.
2437  * 7. GTP-C response message ('source_port' = 2123) is not supported.
2438  */
2439 static int
2440 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2441                              const struct rte_flow_item *pattern,
2442                              struct rte_flow_error *error,
2443                              struct i40e_fdir_filter_conf *filter)
2444 {
2445         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2446         const struct rte_flow_item *item = pattern;
2447         const struct rte_flow_item_eth *eth_spec, *eth_mask;
2448         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2449         const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2450         const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2451         const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2452         const struct rte_flow_item_udp *udp_spec, *udp_mask;
2453         const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2454         const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
2455         const struct rte_flow_item_raw *raw_spec, *raw_mask;
2456         const struct rte_flow_item_vf *vf_spec;
2457
2458         uint8_t pctype = 0;
2459         uint64_t input_set = I40E_INSET_NONE;
2460         uint16_t frag_off;
2461         enum rte_flow_item_type item_type;
2462         enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2463         enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END;
2464         uint32_t i, j;
2465         uint8_t  ipv6_addr_mask[16] = {
2466                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2467                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2468         enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2469         uint8_t raw_id = 0;
2470         int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2471         uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2472         struct i40e_fdir_flex_pit flex_pit;
2473         uint8_t next_dst_off = 0;
2474         uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];
2475         uint16_t flex_size;
2476         bool cfg_flex_pit = true;
2477         bool cfg_flex_msk = true;
2478         uint16_t outer_tpid;
2479         uint16_t ether_type;
2480         uint32_t vtc_flow_cpu;
2481         bool outer_ip = true;
2482         int ret;
2483
2484         memset(off_arr, 0, sizeof(off_arr));
2485         memset(len_arr, 0, sizeof(len_arr));
2486         memset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN);
2487         outer_tpid = i40e_get_outer_vlan(dev);
2488         filter->input.flow_ext.customized_pctype = false;
2489         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2490                 if (item->last) {
2491                         rte_flow_error_set(error, EINVAL,
2492                                            RTE_FLOW_ERROR_TYPE_ITEM,
2493                                            item,
2494                                            "Not support range");
2495                         return -rte_errno;
2496                 }
2497                 item_type = item->type;
2498                 switch (item_type) {
2499                 case RTE_FLOW_ITEM_TYPE_ETH:
2500                         eth_spec = (const struct rte_flow_item_eth *)item->spec;
2501                         eth_mask = (const struct rte_flow_item_eth *)item->mask;
2502
2503                         if (eth_spec && eth_mask) {
2504                                 if (!is_zero_ether_addr(&eth_mask->src) ||
2505                                     !is_zero_ether_addr(&eth_mask->dst)) {
2506                                         rte_flow_error_set(error, EINVAL,
2507                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2508                                                       item,
2509                                                       "Invalid MAC_addr mask.");
2510                                         return -rte_errno;
2511                                 }
2512
2513                                 if ((eth_mask->type & UINT16_MAX) ==
2514                                     UINT16_MAX) {
2515                                         input_set |= I40E_INSET_LAST_ETHER_TYPE;
2516                                         filter->input.flow.l2_flow.ether_type =
2517                                                 eth_spec->type;
2518                                 }
2519
2520                                 ether_type = rte_be_to_cpu_16(eth_spec->type);
2521                                 if (ether_type == ETHER_TYPE_IPv4 ||
2522                                     ether_type == ETHER_TYPE_IPv6 ||
2523                                     ether_type == ETHER_TYPE_ARP ||
2524                                     ether_type == outer_tpid) {
2525                                         rte_flow_error_set(error, EINVAL,
2526                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2527                                                      item,
2528                                                      "Unsupported ether_type.");
2529                                         return -rte_errno;
2530                                 }
2531                         }
2532
2533                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2534                         layer_idx = I40E_FLXPLD_L2_IDX;
2535
2536                         break;
2537                 case RTE_FLOW_ITEM_TYPE_VLAN:
2538                         vlan_spec =
2539                                 (const struct rte_flow_item_vlan *)item->spec;
2540                         vlan_mask =
2541                                 (const struct rte_flow_item_vlan *)item->mask;
2542                         if (vlan_spec && vlan_mask) {
2543                                 if (vlan_mask->tci ==
2544                                     rte_cpu_to_be_16(I40E_TCI_MASK)) {
2545                                         input_set |= I40E_INSET_VLAN_INNER;
2546                                         filter->input.flow_ext.vlan_tci =
2547                                                 vlan_spec->tci;
2548                                 }
2549                         }
2550
2551                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2552                         layer_idx = I40E_FLXPLD_L2_IDX;
2553
2554                         break;
2555                 case RTE_FLOW_ITEM_TYPE_IPV4:
2556                         l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2557                         ipv4_spec =
2558                                 (const struct rte_flow_item_ipv4 *)item->spec;
2559                         ipv4_mask =
2560                                 (const struct rte_flow_item_ipv4 *)item->mask;
2561                         pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
2562                         layer_idx = I40E_FLXPLD_L3_IDX;
2563
2564                         if (ipv4_spec && ipv4_mask && outer_ip) {
2565                                 /* Check IPv4 mask and update input set */
2566                                 if (ipv4_mask->hdr.version_ihl ||
2567                                     ipv4_mask->hdr.total_length ||
2568                                     ipv4_mask->hdr.packet_id ||
2569                                     ipv4_mask->hdr.fragment_offset ||
2570                                     ipv4_mask->hdr.hdr_checksum) {
2571                                         rte_flow_error_set(error, EINVAL,
2572                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2573                                                    item,
2574                                                    "Invalid IPv4 mask.");
2575                                         return -rte_errno;
2576                                 }
2577
2578                                 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2579                                         input_set |= I40E_INSET_IPV4_SRC;
2580                                 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2581                                         input_set |= I40E_INSET_IPV4_DST;
2582                                 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2583                                         input_set |= I40E_INSET_IPV4_TOS;
2584                                 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2585                                         input_set |= I40E_INSET_IPV4_TTL;
2586                                 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2587                                         input_set |= I40E_INSET_IPV4_PROTO;
2588
2589                                 /* Check if it is fragment. */
2590                                 frag_off = ipv4_spec->hdr.fragment_offset;
2591                                 frag_off = rte_be_to_cpu_16(frag_off);
2592                                 if (frag_off & IPV4_HDR_OFFSET_MASK ||
2593                                     frag_off & IPV4_HDR_MF_FLAG)
2594                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV4;
2595
2596                                 /* Get the filter info */
2597                                 filter->input.flow.ip4_flow.proto =
2598                                         ipv4_spec->hdr.next_proto_id;
2599                                 filter->input.flow.ip4_flow.tos =
2600                                         ipv4_spec->hdr.type_of_service;
2601                                 filter->input.flow.ip4_flow.ttl =
2602                                         ipv4_spec->hdr.time_to_live;
2603                                 filter->input.flow.ip4_flow.src_ip =
2604                                         ipv4_spec->hdr.src_addr;
2605                                 filter->input.flow.ip4_flow.dst_ip =
2606                                         ipv4_spec->hdr.dst_addr;
2607                         } else if (!ipv4_spec && !ipv4_mask && !outer_ip) {
2608                                 filter->input.flow_ext.inner_ip = true;
2609                                 filter->input.flow_ext.iip_type =
2610                                         I40E_FDIR_IPTYPE_IPV4;
2611                         } else if ((ipv4_spec || ipv4_mask) && !outer_ip) {
2612                                 rte_flow_error_set(error, EINVAL,
2613                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2614                                                    item,
2615                                                    "Invalid inner IPv4 mask.");
2616                                 return -rte_errno;
2617                         }
2618
2619                         if (outer_ip)
2620                                 outer_ip = false;
2621
2622                         break;
2623                 case RTE_FLOW_ITEM_TYPE_IPV6:
2624                         l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2625                         ipv6_spec =
2626                                 (const struct rte_flow_item_ipv6 *)item->spec;
2627                         ipv6_mask =
2628                                 (const struct rte_flow_item_ipv6 *)item->mask;
2629                         pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
2630                         layer_idx = I40E_FLXPLD_L3_IDX;
2631
2632                         if (ipv6_spec && ipv6_mask && outer_ip) {
2633                                 /* Check IPv6 mask and update input set */
2634                                 if (ipv6_mask->hdr.payload_len) {
2635                                         rte_flow_error_set(error, EINVAL,
2636                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2637                                                    item,
2638                                                    "Invalid IPv6 mask");
2639                                         return -rte_errno;
2640                                 }
2641
2642                                 if (!memcmp(ipv6_mask->hdr.src_addr,
2643                                             ipv6_addr_mask,
2644                                             RTE_DIM(ipv6_mask->hdr.src_addr)))
2645                                         input_set |= I40E_INSET_IPV6_SRC;
2646                                 if (!memcmp(ipv6_mask->hdr.dst_addr,
2647                                             ipv6_addr_mask,
2648                                             RTE_DIM(ipv6_mask->hdr.dst_addr)))
2649                                         input_set |= I40E_INSET_IPV6_DST;
2650
2651                                 if ((ipv6_mask->hdr.vtc_flow &
2652                                      rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2653                                     == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2654                                         input_set |= I40E_INSET_IPV6_TC;
2655                                 if (ipv6_mask->hdr.proto == UINT8_MAX)
2656                                         input_set |= I40E_INSET_IPV6_NEXT_HDR;
2657                                 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2658                                         input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2659
2660                                 /* Get filter info */
2661                                 vtc_flow_cpu =
2662                                       rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2663                                 filter->input.flow.ipv6_flow.tc =
2664                                         (uint8_t)(vtc_flow_cpu >>
2665                                                   I40E_FDIR_IPv6_TC_OFFSET);
2666                                 filter->input.flow.ipv6_flow.proto =
2667                                         ipv6_spec->hdr.proto;
2668                                 filter->input.flow.ipv6_flow.hop_limits =
2669                                         ipv6_spec->hdr.hop_limits;
2670
2671                                 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2672                                            ipv6_spec->hdr.src_addr, 16);
2673                                 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2674                                            ipv6_spec->hdr.dst_addr, 16);
2675
2676                                 /* Check if it is fragment. */
2677                                 if (ipv6_spec->hdr.proto ==
2678                                     I40E_IPV6_FRAG_HEADER)
2679                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV6;
2680                         } else if (!ipv6_spec && !ipv6_mask && !outer_ip) {
2681                                 filter->input.flow_ext.inner_ip = true;
2682                                 filter->input.flow_ext.iip_type =
2683                                         I40E_FDIR_IPTYPE_IPV6;
2684                         } else if ((ipv6_spec || ipv6_mask) && !outer_ip) {
2685                                 rte_flow_error_set(error, EINVAL,
2686                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2687                                                    item,
2688                                                    "Invalid inner IPv6 mask");
2689                                 return -rte_errno;
2690                         }
2691
2692                         if (outer_ip)
2693                                 outer_ip = false;
2694                         break;
2695                 case RTE_FLOW_ITEM_TYPE_TCP:
2696                         tcp_spec = (const struct rte_flow_item_tcp *)item->spec;
2697                         tcp_mask = (const struct rte_flow_item_tcp *)item->mask;
2698
2699                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2700                                 pctype =
2701                                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2702                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2703                                 pctype =
2704                                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2705                         if (tcp_spec && tcp_mask) {
2706                                 /* Check TCP mask and update input set */
2707                                 if (tcp_mask->hdr.sent_seq ||
2708                                     tcp_mask->hdr.recv_ack ||
2709                                     tcp_mask->hdr.data_off ||
2710                                     tcp_mask->hdr.tcp_flags ||
2711                                     tcp_mask->hdr.rx_win ||
2712                                     tcp_mask->hdr.cksum ||
2713                                     tcp_mask->hdr.tcp_urp) {
2714                                         rte_flow_error_set(error, EINVAL,
2715                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2716                                                    item,
2717                                                    "Invalid TCP mask");
2718                                         return -rte_errno;
2719                                 }
2720
2721                                 if (tcp_mask->hdr.src_port == UINT16_MAX)
2722                                         input_set |= I40E_INSET_SRC_PORT;
2723                                 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2724                                         input_set |= I40E_INSET_DST_PORT;
2725
2726                                 /* Get filter info */
2727                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2728                                         filter->input.flow.tcp4_flow.src_port =
2729                                                 tcp_spec->hdr.src_port;
2730                                         filter->input.flow.tcp4_flow.dst_port =
2731                                                 tcp_spec->hdr.dst_port;
2732                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2733                                         filter->input.flow.tcp6_flow.src_port =
2734                                                 tcp_spec->hdr.src_port;
2735                                         filter->input.flow.tcp6_flow.dst_port =
2736                                                 tcp_spec->hdr.dst_port;
2737                                 }
2738                         }
2739
2740                         layer_idx = I40E_FLXPLD_L4_IDX;
2741
2742                         break;
2743                 case RTE_FLOW_ITEM_TYPE_UDP:
2744                         udp_spec = (const struct rte_flow_item_udp *)item->spec;
2745                         udp_mask = (const struct rte_flow_item_udp *)item->mask;
2746
2747                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2748                                 pctype =
2749                                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2750                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2751                                 pctype =
2752                                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2753
2754                         if (udp_spec && udp_mask) {
2755                                 /* Check UDP mask and update input set*/
2756                                 if (udp_mask->hdr.dgram_len ||
2757                                     udp_mask->hdr.dgram_cksum) {
2758                                         rte_flow_error_set(error, EINVAL,
2759                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2760                                                    item,
2761                                                    "Invalid UDP mask");
2762                                         return -rte_errno;
2763                                 }
2764
2765                                 if (udp_mask->hdr.src_port == UINT16_MAX)
2766                                         input_set |= I40E_INSET_SRC_PORT;
2767                                 if (udp_mask->hdr.dst_port == UINT16_MAX)
2768                                         input_set |= I40E_INSET_DST_PORT;
2769
2770                                 /* Get filter info */
2771                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2772                                         filter->input.flow.udp4_flow.src_port =
2773                                                 udp_spec->hdr.src_port;
2774                                         filter->input.flow.udp4_flow.dst_port =
2775                                                 udp_spec->hdr.dst_port;
2776                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2777                                         filter->input.flow.udp6_flow.src_port =
2778                                                 udp_spec->hdr.src_port;
2779                                         filter->input.flow.udp6_flow.dst_port =
2780                                                 udp_spec->hdr.dst_port;
2781                                 }
2782                         }
2783
2784                         layer_idx = I40E_FLXPLD_L4_IDX;
2785
2786                         break;
2787                 case RTE_FLOW_ITEM_TYPE_GTPC:
2788                 case RTE_FLOW_ITEM_TYPE_GTPU:
2789                         if (!pf->gtp_support) {
2790                                 rte_flow_error_set(error, EINVAL,
2791                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2792                                                    item,
2793                                                    "Unsupported protocol");
2794                                 return -rte_errno;
2795                         }
2796
2797                         gtp_spec = (const struct rte_flow_item_gtp *)item->spec;
2798                         gtp_mask = (const struct rte_flow_item_gtp *)item->mask;
2799
2800                         if (gtp_spec && gtp_mask) {
2801                                 if (gtp_mask->v_pt_rsv_flags ||
2802                                     gtp_mask->msg_type ||
2803                                     gtp_mask->msg_len ||
2804                                     gtp_mask->teid != UINT32_MAX) {
2805                                         rte_flow_error_set(error, EINVAL,
2806                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2807                                                    item,
2808                                                    "Invalid GTP mask");
2809                                         return -rte_errno;
2810                                 }
2811
2812                                 filter->input.flow.gtp_flow.teid =
2813                                         gtp_spec->teid;
2814                                 filter->input.flow_ext.customized_pctype = true;
2815                                 cus_proto = item_type;
2816                         }
2817                         break;
2818                 case RTE_FLOW_ITEM_TYPE_SCTP:
2819                         sctp_spec =
2820                                 (const struct rte_flow_item_sctp *)item->spec;
2821                         sctp_mask =
2822                                 (const struct rte_flow_item_sctp *)item->mask;
2823
2824                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2825                                 pctype =
2826                                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
2827                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2828                                 pctype =
2829                                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
2830
2831                         if (sctp_spec && sctp_mask) {
2832                                 /* Check SCTP mask and update input set */
2833                                 if (sctp_mask->hdr.cksum) {
2834                                         rte_flow_error_set(error, EINVAL,
2835                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2836                                                    item,
2837                                                    "Invalid UDP mask");
2838                                         return -rte_errno;
2839                                 }
2840
2841                                 if (sctp_mask->hdr.src_port == UINT16_MAX)
2842                                         input_set |= I40E_INSET_SRC_PORT;
2843                                 if (sctp_mask->hdr.dst_port == UINT16_MAX)
2844                                         input_set |= I40E_INSET_DST_PORT;
2845                                 if (sctp_mask->hdr.tag == UINT32_MAX)
2846                                         input_set |= I40E_INSET_SCTP_VT;
2847
2848                                 /* Get filter info */
2849                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2850                                         filter->input.flow.sctp4_flow.src_port =
2851                                                 sctp_spec->hdr.src_port;
2852                                         filter->input.flow.sctp4_flow.dst_port =
2853                                                 sctp_spec->hdr.dst_port;
2854                                         filter->input.flow.sctp4_flow.verify_tag
2855                                                 = sctp_spec->hdr.tag;
2856                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2857                                         filter->input.flow.sctp6_flow.src_port =
2858                                                 sctp_spec->hdr.src_port;
2859                                         filter->input.flow.sctp6_flow.dst_port =
2860                                                 sctp_spec->hdr.dst_port;
2861                                         filter->input.flow.sctp6_flow.verify_tag
2862                                                 = sctp_spec->hdr.tag;
2863                                 }
2864                         }
2865
2866                         layer_idx = I40E_FLXPLD_L4_IDX;
2867
2868                         break;
2869                 case RTE_FLOW_ITEM_TYPE_RAW:
2870                         raw_spec = (const struct rte_flow_item_raw *)item->spec;
2871                         raw_mask = (const struct rte_flow_item_raw *)item->mask;
2872
2873                         if (!raw_spec || !raw_mask) {
2874                                 rte_flow_error_set(error, EINVAL,
2875                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2876                                                    item,
2877                                                    "NULL RAW spec/mask");
2878                                 return -rte_errno;
2879                         }
2880
2881                         ret = i40e_flow_check_raw_item(item, raw_spec, error);
2882                         if (ret < 0)
2883                                 return ret;
2884
2885                         off_arr[raw_id] = raw_spec->offset;
2886                         len_arr[raw_id] = raw_spec->length;
2887
2888                         flex_size = 0;
2889                         memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
2890                         flex_pit.size =
2891                                 raw_spec->length / sizeof(uint16_t);
2892                         flex_pit.dst_offset =
2893                                 next_dst_off / sizeof(uint16_t);
2894
2895                         for (i = 0; i <= raw_id; i++) {
2896                                 if (i == raw_id)
2897                                         flex_pit.src_offset +=
2898                                                 raw_spec->offset /
2899                                                 sizeof(uint16_t);
2900                                 else
2901                                         flex_pit.src_offset +=
2902                                                 (off_arr[i] + len_arr[i]) /
2903                                                 sizeof(uint16_t);
2904                                 flex_size += len_arr[i];
2905                         }
2906                         if (((flex_pit.src_offset + flex_pit.size) >=
2907                              I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
2908                                 flex_size > I40E_FDIR_MAX_FLEXLEN) {
2909                                 rte_flow_error_set(error, EINVAL,
2910                                            RTE_FLOW_ERROR_TYPE_ITEM,
2911                                            item,
2912                                            "Exceeds maxmial payload limit.");
2913                                 return -rte_errno;
2914                         }
2915
2916                         /* Store flex pit to SW */
2917                         ret = i40e_flow_store_flex_pit(pf, &flex_pit,
2918                                                        layer_idx, raw_id);
2919                         if (ret < 0) {
2920                                 rte_flow_error_set(error, EINVAL,
2921                                    RTE_FLOW_ERROR_TYPE_ITEM,
2922                                    item,
2923                                    "Conflict with the first flexible rule.");
2924                                 return -rte_errno;
2925                         } else if (ret > 0)
2926                                 cfg_flex_pit = false;
2927
2928                         for (i = 0; i < raw_spec->length; i++) {
2929                                 j = i + next_dst_off;
2930                                 filter->input.flow_ext.flexbytes[j] =
2931                                         raw_spec->pattern[i];
2932                                 flex_mask[j] = raw_mask->pattern[i];
2933                         }
2934
2935                         next_dst_off += raw_spec->length;
2936                         raw_id++;
2937                         break;
2938                 case RTE_FLOW_ITEM_TYPE_VF:
2939                         vf_spec = (const struct rte_flow_item_vf *)item->spec;
2940                         filter->input.flow_ext.is_vf = 1;
2941                         filter->input.flow_ext.dst_id = vf_spec->id;
2942                         if (filter->input.flow_ext.is_vf &&
2943                             filter->input.flow_ext.dst_id >= pf->vf_num) {
2944                                 rte_flow_error_set(error, EINVAL,
2945                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2946                                                    item,
2947                                                    "Invalid VF ID for FDIR.");
2948                                 return -rte_errno;
2949                         }
2950                         break;
2951                 default:
2952                         break;
2953                 }
2954         }
2955
2956         /* Get customized pctype value */
2957         if (filter->input.flow_ext.customized_pctype) {
2958                 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter);
2959                 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
2960                         rte_flow_error_set(error, EINVAL,
2961                                            RTE_FLOW_ERROR_TYPE_ITEM,
2962                                            item,
2963                                            "Unsupported pctype");
2964                         return -rte_errno;
2965                 }
2966         }
2967
2968         /* If customized pctype is not used, set fdir configuration.*/
2969         if (!filter->input.flow_ext.customized_pctype) {
2970                 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
2971                 if (ret == -1) {
2972                         rte_flow_error_set(error, EINVAL,
2973                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
2974                                            "Conflict with the first rule's input set.");
2975                         return -rte_errno;
2976                 } else if (ret == -EINVAL) {
2977                         rte_flow_error_set(error, EINVAL,
2978                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
2979                                            "Invalid pattern mask.");
2980                         return -rte_errno;
2981                 }
2982
2983                 /* Store flex mask to SW */
2984                 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);
2985                 if (ret == -1) {
2986                         rte_flow_error_set(error, EINVAL,
2987                                            RTE_FLOW_ERROR_TYPE_ITEM,
2988                                            item,
2989                                            "Exceed maximal number of bitmasks");
2990                         return -rte_errno;
2991                 } else if (ret == -2) {
2992                         rte_flow_error_set(error, EINVAL,
2993                                            RTE_FLOW_ERROR_TYPE_ITEM,
2994                                            item,
2995                                            "Conflict with the first flexible rule");
2996                         return -rte_errno;
2997                 } else if (ret > 0)
2998                         cfg_flex_msk = false;
2999
3000                 if (cfg_flex_pit)
3001                         i40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id);
3002
3003                 if (cfg_flex_msk)
3004                         i40e_flow_set_fdir_flex_msk(pf, pctype);
3005         }
3006
3007         filter->input.pctype = pctype;
3008
3009         return 0;
3010 }
3011
3012 /* Parse to get the action info of a FDIR filter.
3013  * FDIR action supports QUEUE or (QUEUE + MARK).
3014  */
3015 static int
3016 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
3017                             const struct rte_flow_action *actions,
3018                             struct rte_flow_error *error,
3019                             struct i40e_fdir_filter_conf *filter)
3020 {
3021         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3022         const struct rte_flow_action *act;
3023         const struct rte_flow_action_queue *act_q;
3024         const struct rte_flow_action_mark *mark_spec;
3025         uint32_t index = 0;
3026
3027         /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
3028         NEXT_ITEM_OF_ACTION(act, actions, index);
3029         switch (act->type) {
3030         case RTE_FLOW_ACTION_TYPE_QUEUE:
3031                 act_q = (const struct rte_flow_action_queue *)act->conf;
3032                 filter->action.rx_queue = act_q->index;
3033                 if ((!filter->input.flow_ext.is_vf &&
3034                      filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
3035                     (filter->input.flow_ext.is_vf &&
3036                      filter->action.rx_queue >= pf->vf_nb_qps)) {
3037                         rte_flow_error_set(error, EINVAL,
3038                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3039                                            "Invalid queue ID for FDIR.");
3040                         return -rte_errno;
3041                 }
3042                 filter->action.behavior = I40E_FDIR_ACCEPT;
3043                 break;
3044         case RTE_FLOW_ACTION_TYPE_DROP:
3045                 filter->action.behavior = I40E_FDIR_REJECT;
3046                 break;
3047         case RTE_FLOW_ACTION_TYPE_PASSTHRU:
3048                 filter->action.behavior = I40E_FDIR_PASSTHRU;
3049                 break;
3050         default:
3051                 rte_flow_error_set(error, EINVAL,
3052                                    RTE_FLOW_ERROR_TYPE_ACTION, act,
3053                                    "Invalid action.");
3054                 return -rte_errno;
3055         }
3056
3057         /* Check if the next non-void item is MARK or FLAG or END. */
3058         index++;
3059         NEXT_ITEM_OF_ACTION(act, actions, index);
3060         switch (act->type) {
3061         case RTE_FLOW_ACTION_TYPE_MARK:
3062                 mark_spec = (const struct rte_flow_action_mark *)act->conf;
3063                 filter->action.report_status = I40E_FDIR_REPORT_ID;
3064                 filter->soft_id = mark_spec->id;
3065                 break;
3066         case RTE_FLOW_ACTION_TYPE_FLAG:
3067                 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS;
3068                 break;
3069         case RTE_FLOW_ACTION_TYPE_END:
3070                 return 0;
3071         default:
3072                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3073                                    act, "Invalid action.");
3074                 return -rte_errno;
3075         }
3076
3077         /* Check if the next non-void item is END */
3078         index++;
3079         NEXT_ITEM_OF_ACTION(act, actions, index);
3080         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3081                 rte_flow_error_set(error, EINVAL,
3082                                    RTE_FLOW_ERROR_TYPE_ACTION,
3083                                    act, "Invalid action.");
3084                 return -rte_errno;
3085         }
3086
3087         return 0;
3088 }
3089
3090 static int
3091 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
3092                             const struct rte_flow_attr *attr,
3093                             const struct rte_flow_item pattern[],
3094                             const struct rte_flow_action actions[],
3095                             struct rte_flow_error *error,
3096                             union i40e_filter_t *filter)
3097 {
3098         struct i40e_fdir_filter_conf *fdir_filter =
3099                 &filter->fdir_filter;
3100         int ret;
3101
3102         ret = i40e_flow_parse_fdir_pattern(dev, pattern, error, fdir_filter);
3103         if (ret)
3104                 return ret;
3105
3106         ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
3107         if (ret)
3108                 return ret;
3109
3110         ret = i40e_flow_parse_attr(attr, error);
3111         if (ret)
3112                 return ret;
3113
3114         cons_filter_type = RTE_ETH_FILTER_FDIR;
3115
3116         if (dev->data->dev_conf.fdir_conf.mode !=
3117             RTE_FDIR_MODE_PERFECT) {
3118                 rte_flow_error_set(error, ENOTSUP,
3119                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3120                                    NULL,
3121                                    "Check the mode in fdir_conf.");
3122                 return -rte_errno;
3123         }
3124
3125         return 0;
3126 }
3127
3128 /* Parse to get the action info of a tunnel filter
3129  * Tunnel action only supports PF, VF and QUEUE.
3130  */
3131 static int
3132 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
3133                               const struct rte_flow_action *actions,
3134                               struct rte_flow_error *error,
3135                               struct i40e_tunnel_filter_conf *filter)
3136 {
3137         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3138         const struct rte_flow_action *act;
3139         const struct rte_flow_action_queue *act_q;
3140         const struct rte_flow_action_vf *act_vf;
3141         uint32_t index = 0;
3142
3143         /* Check if the first non-void action is PF or VF. */
3144         NEXT_ITEM_OF_ACTION(act, actions, index);
3145         if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
3146             act->type != RTE_FLOW_ACTION_TYPE_VF) {
3147                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3148                                    act, "Not supported action.");
3149                 return -rte_errno;
3150         }
3151
3152         if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
3153                 act_vf = (const struct rte_flow_action_vf *)act->conf;
3154                 filter->vf_id = act_vf->id;
3155                 filter->is_to_vf = 1;
3156                 if (filter->vf_id >= pf->vf_num) {
3157                         rte_flow_error_set(error, EINVAL,
3158                                    RTE_FLOW_ERROR_TYPE_ACTION,
3159                                    act, "Invalid VF ID for tunnel filter");
3160                         return -rte_errno;
3161                 }
3162         }
3163
3164         /* Check if the next non-void item is QUEUE */
3165         index++;
3166         NEXT_ITEM_OF_ACTION(act, actions, index);
3167         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
3168                 act_q = (const struct rte_flow_action_queue *)act->conf;
3169                 filter->queue_id = act_q->index;
3170                 if ((!filter->is_to_vf) &&
3171                     (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
3172                         rte_flow_error_set(error, EINVAL,
3173                                    RTE_FLOW_ERROR_TYPE_ACTION,
3174                                    act, "Invalid queue ID for tunnel filter");
3175                         return -rte_errno;
3176                 } else if (filter->is_to_vf &&
3177                            (filter->queue_id >= pf->vf_nb_qps)) {
3178                         rte_flow_error_set(error, EINVAL,
3179                                    RTE_FLOW_ERROR_TYPE_ACTION,
3180                                    act, "Invalid queue ID for tunnel filter");
3181                         return -rte_errno;
3182                 }
3183         }
3184
3185         /* Check if the next non-void item is END */
3186         index++;
3187         NEXT_ITEM_OF_ACTION(act, actions, index);
3188         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3189                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3190                                    act, "Not supported action.");
3191                 return -rte_errno;
3192         }
3193
3194         return 0;
3195 }
3196
3197 static uint16_t i40e_supported_tunnel_filter_types[] = {
3198         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3199         ETH_TUNNEL_FILTER_IVLAN,
3200         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3201         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3202         ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3203         ETH_TUNNEL_FILTER_IMAC,
3204         ETH_TUNNEL_FILTER_IMAC,
3205 };
3206
3207 static int
3208 i40e_check_tunnel_filter_type(uint8_t filter_type)
3209 {
3210         uint8_t i;
3211
3212         for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3213                 if (filter_type == i40e_supported_tunnel_filter_types[i])
3214                         return 0;
3215         }
3216
3217         return -1;
3218 }
3219
3220 /* 1. Last in item should be NULL as range is not supported.
3221  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3222  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3223  * 3. Mask of fields which need to be matched should be
3224  *    filled with 1.
3225  * 4. Mask of fields which needn't to be matched should be
3226  *    filled with 0.
3227  */
3228 static int
3229 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3230                               const struct rte_flow_item *pattern,
3231                               struct rte_flow_error *error,
3232                               struct i40e_tunnel_filter_conf *filter)
3233 {
3234         const struct rte_flow_item *item = pattern;
3235         const struct rte_flow_item_eth *eth_spec;
3236         const struct rte_flow_item_eth *eth_mask;
3237         const struct rte_flow_item_vxlan *vxlan_spec;
3238         const struct rte_flow_item_vxlan *vxlan_mask;
3239         const struct rte_flow_item_vlan *vlan_spec;
3240         const struct rte_flow_item_vlan *vlan_mask;
3241         uint8_t filter_type = 0;
3242         bool is_vni_masked = 0;
3243         uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3244         enum rte_flow_item_type item_type;
3245         bool vxlan_flag = 0;
3246         uint32_t tenant_id_be = 0;
3247         int ret;
3248
3249         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3250                 if (item->last) {
3251                         rte_flow_error_set(error, EINVAL,
3252                                            RTE_FLOW_ERROR_TYPE_ITEM,
3253                                            item,
3254                                            "Not support range");
3255                         return -rte_errno;
3256                 }
3257                 item_type = item->type;
3258                 switch (item_type) {
3259                 case RTE_FLOW_ITEM_TYPE_ETH:
3260                         eth_spec = (const struct rte_flow_item_eth *)item->spec;
3261                         eth_mask = (const struct rte_flow_item_eth *)item->mask;
3262
3263                         /* Check if ETH item is used for place holder.
3264                          * If yes, both spec and mask should be NULL.
3265                          * If no, both spec and mask shouldn't be NULL.
3266                          */
3267                         if ((!eth_spec && eth_mask) ||
3268                             (eth_spec && !eth_mask)) {
3269                                 rte_flow_error_set(error, EINVAL,
3270                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3271                                                    item,
3272                                                    "Invalid ether spec/mask");
3273                                 return -rte_errno;
3274                         }
3275
3276                         if (eth_spec && eth_mask) {
3277                                 /* DST address of inner MAC shouldn't be masked.
3278                                  * SRC address of Inner MAC should be masked.
3279                                  */
3280                                 if (!is_broadcast_ether_addr(&eth_mask->dst) ||
3281                                     !is_zero_ether_addr(&eth_mask->src) ||
3282                                     eth_mask->type) {
3283                                         rte_flow_error_set(error, EINVAL,
3284                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3285                                                    item,
3286                                                    "Invalid ether spec/mask");
3287                                         return -rte_errno;
3288                                 }
3289
3290                                 if (!vxlan_flag) {
3291                                         rte_memcpy(&filter->outer_mac,
3292                                                    &eth_spec->dst,
3293                                                    ETHER_ADDR_LEN);
3294                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3295                                 } else {
3296                                         rte_memcpy(&filter->inner_mac,
3297                                                    &eth_spec->dst,
3298                                                    ETHER_ADDR_LEN);
3299                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3300                                 }
3301                         }
3302                         break;
3303                 case RTE_FLOW_ITEM_TYPE_VLAN:
3304                         vlan_spec =
3305                                 (const struct rte_flow_item_vlan *)item->spec;
3306                         vlan_mask =
3307                                 (const struct rte_flow_item_vlan *)item->mask;
3308                         if (!(vlan_spec && vlan_mask)) {
3309                                 rte_flow_error_set(error, EINVAL,
3310                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3311                                                    item,
3312                                                    "Invalid vlan item");
3313                                 return -rte_errno;
3314                         }
3315
3316                         if (vlan_spec && vlan_mask) {
3317                                 if (vlan_mask->tci ==
3318                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3319                                         filter->inner_vlan =
3320                                               rte_be_to_cpu_16(vlan_spec->tci) &
3321                                               I40E_TCI_MASK;
3322                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3323                         }
3324                         break;
3325                 case RTE_FLOW_ITEM_TYPE_IPV4:
3326                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3327                         /* IPv4 is used to describe protocol,
3328                          * spec and mask should be NULL.
3329                          */
3330                         if (item->spec || item->mask) {
3331                                 rte_flow_error_set(error, EINVAL,
3332                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3333                                                    item,
3334                                                    "Invalid IPv4 item");
3335                                 return -rte_errno;
3336                         }
3337                         break;
3338                 case RTE_FLOW_ITEM_TYPE_IPV6:
3339                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3340                         /* IPv6 is used to describe protocol,
3341                          * spec and mask should be NULL.
3342                          */
3343                         if (item->spec || item->mask) {
3344                                 rte_flow_error_set(error, EINVAL,
3345                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3346                                                    item,
3347                                                    "Invalid IPv6 item");
3348                                 return -rte_errno;
3349                         }
3350                         break;
3351                 case RTE_FLOW_ITEM_TYPE_UDP:
3352                         /* UDP is used to describe protocol,
3353                          * spec and mask should be NULL.
3354                          */
3355                         if (item->spec || item->mask) {
3356                                 rte_flow_error_set(error, EINVAL,
3357                                            RTE_FLOW_ERROR_TYPE_ITEM,
3358                                            item,
3359                                            "Invalid UDP item");
3360                                 return -rte_errno;
3361                         }
3362                         break;
3363                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3364                         vxlan_spec =
3365                                 (const struct rte_flow_item_vxlan *)item->spec;
3366                         vxlan_mask =
3367                                 (const struct rte_flow_item_vxlan *)item->mask;
3368                         /* Check if VXLAN item is used to describe protocol.
3369                          * If yes, both spec and mask should be NULL.
3370                          * If no, both spec and mask shouldn't be NULL.
3371                          */
3372                         if ((!vxlan_spec && vxlan_mask) ||
3373                             (vxlan_spec && !vxlan_mask)) {
3374                                 rte_flow_error_set(error, EINVAL,
3375                                            RTE_FLOW_ERROR_TYPE_ITEM,
3376                                            item,
3377                                            "Invalid VXLAN item");
3378                                 return -rte_errno;
3379                         }
3380
3381                         /* Check if VNI is masked. */
3382                         if (vxlan_spec && vxlan_mask) {
3383                                 is_vni_masked =
3384                                         !!memcmp(vxlan_mask->vni, vni_mask,
3385                                                  RTE_DIM(vni_mask));
3386                                 if (is_vni_masked) {
3387                                         rte_flow_error_set(error, EINVAL,
3388                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3389                                                    item,
3390                                                    "Invalid VNI mask");
3391                                         return -rte_errno;
3392                                 }
3393
3394                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3395                                            vxlan_spec->vni, 3);
3396                                 filter->tenant_id =
3397                                         rte_be_to_cpu_32(tenant_id_be);
3398                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3399                         }
3400
3401                         vxlan_flag = 1;
3402                         break;
3403                 default:
3404                         break;
3405                 }
3406         }
3407
3408         ret = i40e_check_tunnel_filter_type(filter_type);
3409         if (ret < 0) {
3410                 rte_flow_error_set(error, EINVAL,
3411                                    RTE_FLOW_ERROR_TYPE_ITEM,
3412                                    NULL,
3413                                    "Invalid filter type");
3414                 return -rte_errno;
3415         }
3416         filter->filter_type = filter_type;
3417
3418         filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3419
3420         return 0;
3421 }
3422
3423 static int
3424 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3425                              const struct rte_flow_attr *attr,
3426                              const struct rte_flow_item pattern[],
3427                              const struct rte_flow_action actions[],
3428                              struct rte_flow_error *error,
3429                              union i40e_filter_t *filter)
3430 {
3431         struct i40e_tunnel_filter_conf *tunnel_filter =
3432                 &filter->consistent_tunnel_filter;
3433         int ret;
3434
3435         ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3436                                             error, tunnel_filter);
3437         if (ret)
3438                 return ret;
3439
3440         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3441         if (ret)
3442                 return ret;
3443
3444         ret = i40e_flow_parse_attr(attr, error);
3445         if (ret)
3446                 return ret;
3447
3448         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3449
3450         return ret;
3451 }
3452
3453 /* 1. Last in item should be NULL as range is not supported.
3454  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3455  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3456  * 3. Mask of fields which need to be matched should be
3457  *    filled with 1.
3458  * 4. Mask of fields which needn't to be matched should be
3459  *    filled with 0.
3460  */
3461 static int
3462 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3463                               const struct rte_flow_item *pattern,
3464                               struct rte_flow_error *error,
3465                               struct i40e_tunnel_filter_conf *filter)
3466 {
3467         const struct rte_flow_item *item = pattern;
3468         const struct rte_flow_item_eth *eth_spec;
3469         const struct rte_flow_item_eth *eth_mask;
3470         const struct rte_flow_item_nvgre *nvgre_spec;
3471         const struct rte_flow_item_nvgre *nvgre_mask;
3472         const struct rte_flow_item_vlan *vlan_spec;
3473         const struct rte_flow_item_vlan *vlan_mask;
3474         enum rte_flow_item_type item_type;
3475         uint8_t filter_type = 0;
3476         bool is_tni_masked = 0;
3477         uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3478         bool nvgre_flag = 0;
3479         uint32_t tenant_id_be = 0;
3480         int ret;
3481
3482         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3483                 if (item->last) {
3484                         rte_flow_error_set(error, EINVAL,
3485                                            RTE_FLOW_ERROR_TYPE_ITEM,
3486                                            item,
3487                                            "Not support range");
3488                         return -rte_errno;
3489                 }
3490                 item_type = item->type;
3491                 switch (item_type) {
3492                 case RTE_FLOW_ITEM_TYPE_ETH:
3493                         eth_spec = (const struct rte_flow_item_eth *)item->spec;
3494                         eth_mask = (const struct rte_flow_item_eth *)item->mask;
3495
3496                         /* Check if ETH item is used for place holder.
3497                          * If yes, both spec and mask should be NULL.
3498                          * If no, both spec and mask shouldn't be NULL.
3499                          */
3500                         if ((!eth_spec && eth_mask) ||
3501                             (eth_spec && !eth_mask)) {
3502                                 rte_flow_error_set(error, EINVAL,
3503                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3504                                                    item,
3505                                                    "Invalid ether spec/mask");
3506                                 return -rte_errno;
3507                         }
3508
3509                         if (eth_spec && eth_mask) {
3510                                 /* DST address of inner MAC shouldn't be masked.
3511                                  * SRC address of Inner MAC should be masked.
3512                                  */
3513                                 if (!is_broadcast_ether_addr(&eth_mask->dst) ||
3514                                     !is_zero_ether_addr(&eth_mask->src) ||
3515                                     eth_mask->type) {
3516                                         rte_flow_error_set(error, EINVAL,
3517                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3518                                                    item,
3519                                                    "Invalid ether spec/mask");
3520                                         return -rte_errno;
3521                                 }
3522
3523                                 if (!nvgre_flag) {
3524                                         rte_memcpy(&filter->outer_mac,
3525                                                    &eth_spec->dst,
3526                                                    ETHER_ADDR_LEN);
3527                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3528                                 } else {
3529                                         rte_memcpy(&filter->inner_mac,
3530                                                    &eth_spec->dst,
3531                                                    ETHER_ADDR_LEN);
3532                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3533                                 }
3534                         }
3535
3536                         break;
3537                 case RTE_FLOW_ITEM_TYPE_VLAN:
3538                         vlan_spec =
3539                                 (const struct rte_flow_item_vlan *)item->spec;
3540                         vlan_mask =
3541                                 (const struct rte_flow_item_vlan *)item->mask;
3542                         if (!(vlan_spec && vlan_mask)) {
3543                                 rte_flow_error_set(error, EINVAL,
3544                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3545                                                    item,
3546                                                    "Invalid vlan item");
3547                                 return -rte_errno;
3548                         }
3549
3550                         if (vlan_spec && vlan_mask) {
3551                                 if (vlan_mask->tci ==
3552                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3553                                         filter->inner_vlan =
3554                                               rte_be_to_cpu_16(vlan_spec->tci) &
3555                                               I40E_TCI_MASK;
3556                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3557                         }
3558                         break;
3559                 case RTE_FLOW_ITEM_TYPE_IPV4:
3560                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3561                         /* IPv4 is used to describe protocol,
3562                          * spec and mask should be NULL.
3563                          */
3564                         if (item->spec || item->mask) {
3565                                 rte_flow_error_set(error, EINVAL,
3566                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3567                                                    item,
3568                                                    "Invalid IPv4 item");
3569                                 return -rte_errno;
3570                         }
3571                         break;
3572                 case RTE_FLOW_ITEM_TYPE_IPV6:
3573                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3574                         /* IPv6 is used to describe protocol,
3575                          * spec and mask should be NULL.
3576                          */
3577                         if (item->spec || item->mask) {
3578                                 rte_flow_error_set(error, EINVAL,
3579                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3580                                                    item,
3581                                                    "Invalid IPv6 item");
3582                                 return -rte_errno;
3583                         }
3584                         break;
3585                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3586                         nvgre_spec =
3587                                 (const struct rte_flow_item_nvgre *)item->spec;
3588                         nvgre_mask =
3589                                 (const struct rte_flow_item_nvgre *)item->mask;
3590                         /* Check if NVGRE item is used to describe protocol.
3591                          * If yes, both spec and mask should be NULL.
3592                          * If no, both spec and mask shouldn't be NULL.
3593                          */
3594                         if ((!nvgre_spec && nvgre_mask) ||
3595                             (nvgre_spec && !nvgre_mask)) {
3596                                 rte_flow_error_set(error, EINVAL,
3597                                            RTE_FLOW_ERROR_TYPE_ITEM,
3598                                            item,
3599                                            "Invalid NVGRE item");
3600                                 return -rte_errno;
3601                         }
3602
3603                         if (nvgre_spec && nvgre_mask) {
3604                                 is_tni_masked =
3605                                         !!memcmp(nvgre_mask->tni, tni_mask,
3606                                                  RTE_DIM(tni_mask));
3607                                 if (is_tni_masked) {
3608                                         rte_flow_error_set(error, EINVAL,
3609                                                        RTE_FLOW_ERROR_TYPE_ITEM,
3610                                                        item,
3611                                                        "Invalid TNI mask");
3612                                         return -rte_errno;
3613                                 }
3614                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3615                                            nvgre_spec->tni, 3);
3616                                 filter->tenant_id =
3617                                         rte_be_to_cpu_32(tenant_id_be);
3618                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3619                         }
3620
3621                         nvgre_flag = 1;
3622                         break;
3623                 default:
3624                         break;
3625                 }
3626         }
3627
3628         ret = i40e_check_tunnel_filter_type(filter_type);
3629         if (ret < 0) {
3630                 rte_flow_error_set(error, EINVAL,
3631                                    RTE_FLOW_ERROR_TYPE_ITEM,
3632                                    NULL,
3633                                    "Invalid filter type");
3634                 return -rte_errno;
3635         }
3636         filter->filter_type = filter_type;
3637
3638         filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
3639
3640         return 0;
3641 }
3642
3643 static int
3644 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
3645                              const struct rte_flow_attr *attr,
3646                              const struct rte_flow_item pattern[],
3647                              const struct rte_flow_action actions[],
3648                              struct rte_flow_error *error,
3649                              union i40e_filter_t *filter)
3650 {
3651         struct i40e_tunnel_filter_conf *tunnel_filter =
3652                 &filter->consistent_tunnel_filter;
3653         int ret;
3654
3655         ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
3656                                             error, tunnel_filter);
3657         if (ret)
3658                 return ret;
3659
3660         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3661         if (ret)
3662                 return ret;
3663
3664         ret = i40e_flow_parse_attr(attr, error);
3665         if (ret)
3666                 return ret;
3667
3668         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3669
3670         return ret;
3671 }
3672
3673 /* 1. Last in item should be NULL as range is not supported.
3674  * 2. Supported filter types: MPLS label.
3675  * 3. Mask of fields which need to be matched should be
3676  *    filled with 1.
3677  * 4. Mask of fields which needn't to be matched should be
3678  *    filled with 0.
3679  */
3680 static int
3681 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
3682                              const struct rte_flow_item *pattern,
3683                              struct rte_flow_error *error,
3684                              struct i40e_tunnel_filter_conf *filter)
3685 {
3686         const struct rte_flow_item *item = pattern;
3687         const struct rte_flow_item_mpls *mpls_spec;
3688         const struct rte_flow_item_mpls *mpls_mask;
3689         enum rte_flow_item_type item_type;
3690         bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
3691         const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
3692         uint32_t label_be = 0;
3693
3694         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3695                 if (item->last) {
3696                         rte_flow_error_set(error, EINVAL,
3697                                            RTE_FLOW_ERROR_TYPE_ITEM,
3698                                            item,
3699                                            "Not support range");
3700                         return -rte_errno;
3701                 }
3702                 item_type = item->type;
3703                 switch (item_type) {
3704                 case RTE_FLOW_ITEM_TYPE_ETH:
3705                         if (item->spec || item->mask) {
3706                                 rte_flow_error_set(error, EINVAL,
3707                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3708                                                    item,
3709                                                    "Invalid ETH item");
3710                                 return -rte_errno;
3711                         }
3712                         break;
3713                 case RTE_FLOW_ITEM_TYPE_IPV4:
3714                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3715                         /* IPv4 is used to describe protocol,
3716                          * spec and mask should be NULL.
3717                          */
3718                         if (item->spec || item->mask) {
3719                                 rte_flow_error_set(error, EINVAL,
3720                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3721                                                    item,
3722                                                    "Invalid IPv4 item");
3723                                 return -rte_errno;
3724                         }
3725                         break;
3726                 case RTE_FLOW_ITEM_TYPE_IPV6:
3727                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3728                         /* IPv6 is used to describe protocol,
3729                          * spec and mask should be NULL.
3730                          */
3731                         if (item->spec || item->mask) {
3732                                 rte_flow_error_set(error, EINVAL,
3733                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3734                                                    item,
3735                                                    "Invalid IPv6 item");
3736                                 return -rte_errno;
3737                         }
3738                         break;
3739                 case RTE_FLOW_ITEM_TYPE_UDP:
3740                         /* UDP is used to describe protocol,
3741                          * spec and mask should be NULL.
3742                          */
3743                         if (item->spec || item->mask) {
3744                                 rte_flow_error_set(error, EINVAL,
3745                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3746                                                    item,
3747                                                    "Invalid UDP item");
3748                                 return -rte_errno;
3749                         }
3750                         is_mplsoudp = 1;
3751                         break;
3752                 case RTE_FLOW_ITEM_TYPE_GRE:
3753                         /* GRE is used to describe protocol,
3754                          * spec and mask should be NULL.
3755                          */
3756                         if (item->spec || item->mask) {
3757                                 rte_flow_error_set(error, EINVAL,
3758                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3759                                                    item,
3760                                                    "Invalid GRE item");
3761                                 return -rte_errno;
3762                         }
3763                         break;
3764                 case RTE_FLOW_ITEM_TYPE_MPLS:
3765                         mpls_spec =
3766                                 (const struct rte_flow_item_mpls *)item->spec;
3767                         mpls_mask =
3768                                 (const struct rte_flow_item_mpls *)item->mask;
3769
3770                         if (!mpls_spec || !mpls_mask) {
3771                                 rte_flow_error_set(error, EINVAL,
3772                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3773                                                    item,
3774                                                    "Invalid MPLS item");
3775                                 return -rte_errno;
3776                         }
3777
3778                         if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
3779                                 rte_flow_error_set(error, EINVAL,
3780                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3781                                                    item,
3782                                                    "Invalid MPLS label mask");
3783                                 return -rte_errno;
3784                         }
3785                         rte_memcpy(((uint8_t *)&label_be + 1),
3786                                    mpls_spec->label_tc_s, 3);
3787                         filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
3788                         break;
3789                 default:
3790                         break;
3791                 }
3792         }
3793
3794         if (is_mplsoudp)
3795                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
3796         else
3797                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
3798
3799         return 0;
3800 }
3801
3802 static int
3803 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
3804                             const struct rte_flow_attr *attr,
3805                             const struct rte_flow_item pattern[],
3806                             const struct rte_flow_action actions[],
3807                             struct rte_flow_error *error,
3808                             union i40e_filter_t *filter)
3809 {
3810         struct i40e_tunnel_filter_conf *tunnel_filter =
3811                 &filter->consistent_tunnel_filter;
3812         int ret;
3813
3814         ret = i40e_flow_parse_mpls_pattern(dev, pattern,
3815                                            error, tunnel_filter);
3816         if (ret)
3817                 return ret;
3818
3819         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3820         if (ret)
3821                 return ret;
3822
3823         ret = i40e_flow_parse_attr(attr, error);
3824         if (ret)
3825                 return ret;
3826
3827         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3828
3829         return ret;
3830 }
3831
3832 /* 1. Last in item should be NULL as range is not supported.
3833  * 2. Supported filter types: GTP TEID.
3834  * 3. Mask of fields which need to be matched should be
3835  *    filled with 1.
3836  * 4. Mask of fields which needn't to be matched should be
3837  *    filled with 0.
3838  * 5. GTP profile supports GTPv1 only.
3839  * 6. GTP-C response message ('source_port' = 2123) is not supported.
3840  */
3841 static int
3842 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev,
3843                             const struct rte_flow_item *pattern,
3844                             struct rte_flow_error *error,
3845                             struct i40e_tunnel_filter_conf *filter)
3846 {
3847         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3848         const struct rte_flow_item *item = pattern;
3849         const struct rte_flow_item_gtp *gtp_spec;
3850         const struct rte_flow_item_gtp *gtp_mask;
3851         enum rte_flow_item_type item_type;
3852
3853         if (!pf->gtp_support) {
3854                 rte_flow_error_set(error, EINVAL,
3855                                    RTE_FLOW_ERROR_TYPE_ITEM,
3856                                    item,
3857                                    "GTP is not supported by default.");
3858                 return -rte_errno;
3859         }
3860
3861         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3862                 if (item->last) {
3863                         rte_flow_error_set(error, EINVAL,
3864                                            RTE_FLOW_ERROR_TYPE_ITEM,
3865                                            item,
3866                                            "Not support range");
3867                         return -rte_errno;
3868                 }
3869                 item_type = item->type;
3870                 switch (item_type) {
3871                 case RTE_FLOW_ITEM_TYPE_ETH:
3872                         if (item->spec || item->mask) {
3873                                 rte_flow_error_set(error, EINVAL,
3874                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3875                                                    item,
3876                                                    "Invalid ETH item");
3877                                 return -rte_errno;
3878                         }
3879                         break;
3880                 case RTE_FLOW_ITEM_TYPE_IPV4:
3881                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3882                         /* IPv4 is used to describe protocol,
3883                          * spec and mask should be NULL.
3884                          */
3885                         if (item->spec || item->mask) {
3886                                 rte_flow_error_set(error, EINVAL,
3887                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3888                                                    item,
3889                                                    "Invalid IPv4 item");
3890                                 return -rte_errno;
3891                         }
3892                         break;
3893                 case RTE_FLOW_ITEM_TYPE_UDP:
3894                         if (item->spec || item->mask) {
3895                                 rte_flow_error_set(error, EINVAL,
3896                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3897                                                    item,
3898                                                    "Invalid UDP item");
3899                                 return -rte_errno;
3900                         }
3901                         break;
3902                 case RTE_FLOW_ITEM_TYPE_GTPC:
3903                 case RTE_FLOW_ITEM_TYPE_GTPU:
3904                         gtp_spec =
3905                                 (const struct rte_flow_item_gtp *)item->spec;
3906                         gtp_mask =
3907                                 (const struct rte_flow_item_gtp *)item->mask;
3908
3909                         if (!gtp_spec || !gtp_mask) {
3910                                 rte_flow_error_set(error, EINVAL,
3911                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3912                                                    item,
3913                                                    "Invalid GTP item");
3914                                 return -rte_errno;
3915                         }
3916
3917                         if (gtp_mask->v_pt_rsv_flags ||
3918                             gtp_mask->msg_type ||
3919                             gtp_mask->msg_len ||
3920                             gtp_mask->teid != UINT32_MAX) {
3921                                 rte_flow_error_set(error, EINVAL,
3922                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3923                                                    item,
3924                                                    "Invalid GTP mask");
3925                                 return -rte_errno;
3926                         }
3927
3928                         if (item_type == RTE_FLOW_ITEM_TYPE_GTPC)
3929                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC;
3930                         else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU)
3931                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU;
3932
3933                         filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid);
3934
3935                         break;
3936                 default:
3937                         break;
3938                 }
3939         }
3940
3941         return 0;
3942 }
3943
3944 static int
3945 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
3946                            const struct rte_flow_attr *attr,
3947                            const struct rte_flow_item pattern[],
3948                            const struct rte_flow_action actions[],
3949                            struct rte_flow_error *error,
3950                            union i40e_filter_t *filter)
3951 {
3952         struct i40e_tunnel_filter_conf *tunnel_filter =
3953                 &filter->consistent_tunnel_filter;
3954         int ret;
3955
3956         ret = i40e_flow_parse_gtp_pattern(dev, pattern,
3957                                           error, tunnel_filter);
3958         if (ret)
3959                 return ret;
3960
3961         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3962         if (ret)
3963                 return ret;
3964
3965         ret = i40e_flow_parse_attr(attr, error);
3966         if (ret)
3967                 return ret;
3968
3969         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3970
3971         return ret;
3972 }
3973
3974 /* 1. Last in item should be NULL as range is not supported.
3975  * 2. Supported filter types: QINQ.
3976  * 3. Mask of fields which need to be matched should be
3977  *    filled with 1.
3978  * 4. Mask of fields which needn't to be matched should be
3979  *    filled with 0.
3980  */
3981 static int
3982 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
3983                               const struct rte_flow_item *pattern,
3984                               struct rte_flow_error *error,
3985                               struct i40e_tunnel_filter_conf *filter)
3986 {
3987         const struct rte_flow_item *item = pattern;
3988         const struct rte_flow_item_vlan *vlan_spec = NULL;
3989         const struct rte_flow_item_vlan *vlan_mask = NULL;
3990         const struct rte_flow_item_vlan *i_vlan_spec = NULL;
3991         const struct rte_flow_item_vlan *i_vlan_mask = NULL;
3992         const struct rte_flow_item_vlan *o_vlan_spec = NULL;
3993         const struct rte_flow_item_vlan *o_vlan_mask = NULL;
3994
3995         enum rte_flow_item_type item_type;
3996         bool vlan_flag = 0;
3997
3998         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3999                 if (item->last) {
4000                         rte_flow_error_set(error, EINVAL,
4001                                            RTE_FLOW_ERROR_TYPE_ITEM,
4002                                            item,
4003                                            "Not support range");
4004                         return -rte_errno;
4005                 }
4006                 item_type = item->type;
4007                 switch (item_type) {
4008                 case RTE_FLOW_ITEM_TYPE_ETH:
4009                         if (item->spec || item->mask) {
4010                                 rte_flow_error_set(error, EINVAL,
4011                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4012                                                    item,
4013                                                    "Invalid ETH item");
4014                                 return -rte_errno;
4015                         }
4016                         break;
4017                 case RTE_FLOW_ITEM_TYPE_VLAN:
4018                         vlan_spec =
4019                                 (const struct rte_flow_item_vlan *)item->spec;
4020                         vlan_mask =
4021                                 (const struct rte_flow_item_vlan *)item->mask;
4022
4023                         if (!(vlan_spec && vlan_mask)) {
4024                                 rte_flow_error_set(error, EINVAL,
4025                                            RTE_FLOW_ERROR_TYPE_ITEM,
4026                                            item,
4027                                            "Invalid vlan item");
4028                                 return -rte_errno;
4029                         }
4030
4031                         if (!vlan_flag) {
4032                                 o_vlan_spec = vlan_spec;
4033                                 o_vlan_mask = vlan_mask;
4034                                 vlan_flag = 1;
4035                         } else {
4036                                 i_vlan_spec = vlan_spec;
4037                                 i_vlan_mask = vlan_mask;
4038                                 vlan_flag = 0;
4039                         }
4040                         break;
4041
4042                 default:
4043                         break;
4044                 }
4045         }
4046
4047         /* Get filter specification */
4048         if ((o_vlan_mask != NULL) && (o_vlan_mask->tci ==
4049                         rte_cpu_to_be_16(I40E_TCI_MASK)) &&
4050                         (i_vlan_mask != NULL) &&
4051                         (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) {
4052                 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci)
4053                         & I40E_TCI_MASK;
4054                 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci)
4055                         & I40E_TCI_MASK;
4056         } else {
4057                         rte_flow_error_set(error, EINVAL,
4058                                            RTE_FLOW_ERROR_TYPE_ITEM,
4059                                            NULL,
4060                                            "Invalid filter type");
4061                         return -rte_errno;
4062         }
4063
4064         filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
4065         return 0;
4066 }
4067
4068 static int
4069 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
4070                               const struct rte_flow_attr *attr,
4071                               const struct rte_flow_item pattern[],
4072                               const struct rte_flow_action actions[],
4073                               struct rte_flow_error *error,
4074                               union i40e_filter_t *filter)
4075 {
4076         struct i40e_tunnel_filter_conf *tunnel_filter =
4077                 &filter->consistent_tunnel_filter;
4078         int ret;
4079
4080         ret = i40e_flow_parse_qinq_pattern(dev, pattern,
4081                                              error, tunnel_filter);
4082         if (ret)
4083                 return ret;
4084
4085         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4086         if (ret)
4087                 return ret;
4088
4089         ret = i40e_flow_parse_attr(attr, error);
4090         if (ret)
4091                 return ret;
4092
4093         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4094
4095         return ret;
4096 }
4097
4098 static int
4099 i40e_flow_validate(struct rte_eth_dev *dev,
4100                    const struct rte_flow_attr *attr,
4101                    const struct rte_flow_item pattern[],
4102                    const struct rte_flow_action actions[],
4103                    struct rte_flow_error *error)
4104 {
4105         struct rte_flow_item *items; /* internal pattern w/o VOID items */
4106         parse_filter_t parse_filter;
4107         uint32_t item_num = 0; /* non-void item number of pattern*/
4108         uint32_t i = 0;
4109         bool flag = false;
4110         int ret = I40E_NOT_SUPPORTED;
4111
4112         if (!pattern) {
4113                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4114                                    NULL, "NULL pattern.");
4115                 return -rte_errno;
4116         }
4117
4118         if (!actions) {
4119                 rte_flow_error_set(error, EINVAL,
4120                                    RTE_FLOW_ERROR_TYPE_ACTION_NUM,
4121                                    NULL, "NULL action.");
4122                 return -rte_errno;
4123         }
4124
4125         if (!attr) {
4126                 rte_flow_error_set(error, EINVAL,
4127                                    RTE_FLOW_ERROR_TYPE_ATTR,
4128                                    NULL, "NULL attribute.");
4129                 return -rte_errno;
4130         }
4131
4132         memset(&cons_filter, 0, sizeof(cons_filter));
4133
4134         /* Get the non-void item number of pattern */
4135         while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
4136                 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
4137                         item_num++;
4138                 i++;
4139         }
4140         item_num++;
4141
4142         items = rte_zmalloc("i40e_pattern",
4143                             item_num * sizeof(struct rte_flow_item), 0);
4144         if (!items) {
4145                 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4146                                    NULL, "No memory for PMD internal items.");
4147                 return -ENOMEM;
4148         }
4149
4150         i40e_pattern_skip_void_item(items, pattern);
4151
4152         i = 0;
4153         do {
4154                 parse_filter = i40e_find_parse_filter_func(items, &i);
4155                 if (!parse_filter && !flag) {
4156                         rte_flow_error_set(error, EINVAL,
4157                                            RTE_FLOW_ERROR_TYPE_ITEM,
4158                                            pattern, "Unsupported pattern");
4159                         rte_free(items);
4160                         return -rte_errno;
4161                 }
4162                 if (parse_filter)
4163                         ret = parse_filter(dev, attr, items, actions,
4164                                            error, &cons_filter);
4165                 flag = true;
4166         } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
4167
4168         rte_free(items);
4169
4170         return ret;
4171 }
4172
4173 static struct rte_flow *
4174 i40e_flow_create(struct rte_eth_dev *dev,
4175                  const struct rte_flow_attr *attr,
4176                  const struct rte_flow_item pattern[],
4177                  const struct rte_flow_action actions[],
4178                  struct rte_flow_error *error)
4179 {
4180         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4181         struct rte_flow *flow;
4182         int ret;
4183
4184         flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
4185         if (!flow) {
4186                 rte_flow_error_set(error, ENOMEM,
4187                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4188                                    "Failed to allocate memory");
4189                 return flow;
4190         }
4191
4192         ret = i40e_flow_validate(dev, attr, pattern, actions, error);
4193         if (ret < 0)
4194                 return NULL;
4195
4196         switch (cons_filter_type) {
4197         case RTE_ETH_FILTER_ETHERTYPE:
4198                 ret = i40e_ethertype_filter_set(pf,
4199                                         &cons_filter.ethertype_filter, 1);
4200                 if (ret)
4201                         goto free_flow;
4202                 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
4203                                         i40e_ethertype_filter_list);
4204                 break;
4205         case RTE_ETH_FILTER_FDIR:
4206                 ret = i40e_flow_add_del_fdir_filter(dev,
4207                                        &cons_filter.fdir_filter, 1);
4208                 if (ret)
4209                         goto free_flow;
4210                 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
4211                                         i40e_fdir_filter_list);
4212                 break;
4213         case RTE_ETH_FILTER_TUNNEL:
4214                 ret = i40e_dev_consistent_tunnel_filter_set(pf,
4215                             &cons_filter.consistent_tunnel_filter, 1);
4216                 if (ret)
4217                         goto free_flow;
4218                 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
4219                                         i40e_tunnel_filter_list);
4220                 break;
4221         default:
4222                 goto free_flow;
4223         }
4224
4225         flow->filter_type = cons_filter_type;
4226         TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
4227         return flow;
4228
4229 free_flow:
4230         rte_flow_error_set(error, -ret,
4231                            RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4232                            "Failed to create flow.");
4233         rte_free(flow);
4234         return NULL;
4235 }
4236
4237 static int
4238 i40e_flow_destroy(struct rte_eth_dev *dev,
4239                   struct rte_flow *flow,
4240                   struct rte_flow_error *error)
4241 {
4242         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4243         enum rte_filter_type filter_type = flow->filter_type;
4244         int ret = 0;
4245
4246         switch (filter_type) {
4247         case RTE_ETH_FILTER_ETHERTYPE:
4248                 ret = i40e_flow_destroy_ethertype_filter(pf,
4249                          (struct i40e_ethertype_filter *)flow->rule);
4250                 break;
4251         case RTE_ETH_FILTER_TUNNEL:
4252                 ret = i40e_flow_destroy_tunnel_filter(pf,
4253                               (struct i40e_tunnel_filter *)flow->rule);
4254                 break;
4255         case RTE_ETH_FILTER_FDIR:
4256                 ret = i40e_flow_add_del_fdir_filter(dev,
4257                        &((struct i40e_fdir_filter *)flow->rule)->fdir, 0);
4258                 break;
4259         default:
4260                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4261                             filter_type);
4262                 ret = -EINVAL;
4263                 break;
4264         }
4265
4266         if (!ret) {
4267                 TAILQ_REMOVE(&pf->flow_list, flow, node);
4268                 rte_free(flow);
4269         } else
4270                 rte_flow_error_set(error, -ret,
4271                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4272                                    "Failed to destroy flow.");
4273
4274         return ret;
4275 }
4276
4277 static int
4278 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
4279                                    struct i40e_ethertype_filter *filter)
4280 {
4281         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4282         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
4283         struct i40e_ethertype_filter *node;
4284         struct i40e_control_filter_stats stats;
4285         uint16_t flags = 0;
4286         int ret = 0;
4287
4288         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
4289                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
4290         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
4291                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
4292         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
4293
4294         memset(&stats, 0, sizeof(stats));
4295         ret = i40e_aq_add_rem_control_packet_filter(hw,
4296                                     filter->input.mac_addr.addr_bytes,
4297                                     filter->input.ether_type,
4298                                     flags, pf->main_vsi->seid,
4299                                     filter->queue, 0, &stats, NULL);
4300         if (ret < 0)
4301                 return ret;
4302
4303         node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
4304         if (!node)
4305                 return -EINVAL;
4306
4307         ret = i40e_sw_ethertype_filter_del(pf, &node->input);
4308
4309         return ret;
4310 }
4311
4312 static int
4313 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
4314                                 struct i40e_tunnel_filter *filter)
4315 {
4316         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4317         struct i40e_vsi *vsi;
4318         struct i40e_pf_vf *vf;
4319         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
4320         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
4321         struct i40e_tunnel_filter *node;
4322         bool big_buffer = 0;
4323         int ret = 0;
4324
4325         memset(&cld_filter, 0, sizeof(cld_filter));
4326         ether_addr_copy((struct ether_addr *)&filter->input.outer_mac,
4327                         (struct ether_addr *)&cld_filter.element.outer_mac);
4328         ether_addr_copy((struct ether_addr *)&filter->input.inner_mac,
4329                         (struct ether_addr *)&cld_filter.element.inner_mac);
4330         cld_filter.element.inner_vlan = filter->input.inner_vlan;
4331         cld_filter.element.flags = filter->input.flags;
4332         cld_filter.element.tenant_id = filter->input.tenant_id;
4333         cld_filter.element.queue_number = filter->queue;
4334         rte_memcpy(cld_filter.general_fields,
4335                    filter->input.general_fields,
4336                    sizeof(cld_filter.general_fields));
4337
4338         if (!filter->is_to_vf)
4339                 vsi = pf->main_vsi;
4340         else {
4341                 vf = &pf->vfs[filter->vf_id];
4342                 vsi = vf->vsi;
4343         }
4344
4345         if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
4346             I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
4347             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
4348             I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
4349             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
4350             I40E_AQC_ADD_CLOUD_FILTER_0X10))
4351                 big_buffer = 1;
4352
4353         if (big_buffer)
4354                 ret = i40e_aq_remove_cloud_filters_big_buffer(hw, vsi->seid,
4355                                                               &cld_filter, 1);
4356         else
4357                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4358                                                    &cld_filter.element, 1);
4359         if (ret < 0)
4360                 return -ENOTSUP;
4361
4362         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
4363         if (!node)
4364                 return -EINVAL;
4365
4366         ret = i40e_sw_tunnel_filter_del(pf, &node->input);
4367
4368         return ret;
4369 }
4370
4371 static int
4372 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
4373 {
4374         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4375         int ret;
4376
4377         ret = i40e_flow_flush_fdir_filter(pf);
4378         if (ret) {
4379                 rte_flow_error_set(error, -ret,
4380                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4381                                    "Failed to flush FDIR flows.");
4382                 return -rte_errno;
4383         }
4384
4385         ret = i40e_flow_flush_ethertype_filter(pf);
4386         if (ret) {
4387                 rte_flow_error_set(error, -ret,
4388                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4389                                    "Failed to ethertype flush flows.");
4390                 return -rte_errno;
4391         }
4392
4393         ret = i40e_flow_flush_tunnel_filter(pf);
4394         if (ret) {
4395                 rte_flow_error_set(error, -ret,
4396                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4397                                    "Failed to flush tunnel flows.");
4398                 return -rte_errno;
4399         }
4400
4401         return ret;
4402 }
4403
4404 static int
4405 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
4406 {
4407         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4408         struct i40e_fdir_info *fdir_info = &pf->fdir;
4409         struct i40e_fdir_filter *fdir_filter;
4410         struct rte_flow *flow;
4411         void *temp;
4412         int ret;
4413
4414         ret = i40e_fdir_flush(dev);
4415         if (!ret) {
4416                 /* Delete FDIR filters in FDIR list. */
4417                 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
4418                         ret = i40e_sw_fdir_filter_del(pf,
4419                                                       &fdir_filter->fdir.input);
4420                         if (ret < 0)
4421                                 return ret;
4422                 }
4423
4424                 /* Delete FDIR flows in flow list. */
4425                 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4426                         if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
4427                                 TAILQ_REMOVE(&pf->flow_list, flow, node);
4428                                 rte_free(flow);
4429                         }
4430                 }
4431         }
4432
4433         return ret;
4434 }
4435
4436 /* Flush all ethertype filters */
4437 static int
4438 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
4439 {
4440         struct i40e_ethertype_filter_list
4441                 *ethertype_list = &pf->ethertype.ethertype_list;
4442         struct i40e_ethertype_filter *filter;
4443         struct rte_flow *flow;
4444         void *temp;
4445         int ret = 0;
4446
4447         while ((filter = TAILQ_FIRST(ethertype_list))) {
4448                 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
4449                 if (ret)
4450                         return ret;
4451         }
4452
4453         /* Delete ethertype flows in flow list. */
4454         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4455                 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
4456                         TAILQ_REMOVE(&pf->flow_list, flow, node);
4457                         rte_free(flow);
4458                 }
4459         }
4460
4461         return ret;
4462 }
4463
4464 /* Flush all tunnel filters */
4465 static int
4466 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
4467 {
4468         struct i40e_tunnel_filter_list
4469                 *tunnel_list = &pf->tunnel.tunnel_list;
4470         struct i40e_tunnel_filter *filter;
4471         struct rte_flow *flow;
4472         void *temp;
4473         int ret = 0;
4474
4475         while ((filter = TAILQ_FIRST(tunnel_list))) {
4476                 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
4477                 if (ret)
4478                         return ret;
4479         }
4480
4481         /* Delete tunnel flows in flow list. */
4482         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4483                 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
4484                         TAILQ_REMOVE(&pf->flow_list, flow, node);
4485                         rte_free(flow);
4486                 }
4487         }
4488
4489         return ret;
4490 }