drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59
  60 #define DEFAULT_TX_RS_THRESH   32
  61 #define DEFAULT_TX_FREE_THRESH 32
  62 #define I40E_MAX_PKT_TYPE      256
  63
  64 #define I40E_TX_MAX_BURST  32
  65
  66 #define I40E_DMA_MEM_ALIGN 4096
  67
  68 /* Base address of the HW descriptor ring should be 128B aligned. */
  69 #define I40E_RING_BASE_ALIGN    128
  70
  71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  72                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  73
  74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  75
  76 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  77                 PKT_TX_IP_CKSUM |                \
  78                 PKT_TX_L4_MASK |                 \
  79                 PKT_TX_TCP_SEG |                 \
  80                 PKT_TX_OUTER_IP_CKSUM)
  81
  82 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  83                                       struct rte_mbuf **tx_pkts,
  84                                       uint16_t nb_pkts);
  85
  86 static inline void
  87 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  88 {
  89         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
  90                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
  91                 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
  92                 mb->vlan_tci =
  93                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
  94                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
  95                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
  96         } else {
  97                 mb->vlan_tci = 0;
  98         }
  99 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 100         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 101                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 102                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
 103                 mb->vlan_tci_outer = mb->vlan_tci;
 104                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 105                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 106                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 107                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 108         } else {
 109                 mb->vlan_tci_outer = 0;
 110         }
 111 #endif
 112         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 113                    mb->vlan_tci, mb->vlan_tci_outer);
 114 }
 115
 116 /* Translate the rx descriptor status to pkt flags */
 117 static inline uint64_t
 118 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 119 {
 120         uint64_t flags;
 121
 122         /* Check if RSS_HASH */
 123         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 124                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 125                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 126
 127         /* Check if FDIR Match */
 128         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 129                                                         PKT_RX_FDIR : 0);
 130
 131         return flags;
 132 }
 133
 134 static inline uint64_t
 135 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 136 {
 137         uint64_t flags = 0;
 138         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 139
 140 #define I40E_RX_ERR_BITS 0x3f
 141         if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
 142                 return flags;
 143         /* If RXE bit set, all other status bits are meaningless */
 144         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
 145                 flags |= PKT_RX_MAC_ERR;
 146                 return flags;
 147         }
 148
 149         /* If RECIPE bit set, all other status indications should be ignored */
 150         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
 151                 flags |= PKT_RX_RECIP_ERR;
 152                 return flags;
 153         }
 154         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
 155                 flags |= PKT_RX_HBUF_OVERFLOW;
 156         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 157                 flags |= PKT_RX_IP_CKSUM_BAD;
 158         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 159                 flags |= PKT_RX_L4_CKSUM_BAD;
 160         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 161                 flags |= PKT_RX_EIP_CKSUM_BAD;
 162         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
 163                 flags |= PKT_RX_OVERSIZE;
 164
 165         return flags;
 166 }
 167
 168 /* Function to check and set the ieee1588 timesync index and get the
 169  * appropriate flags.
 170  */
 171 #ifdef RTE_LIBRTE_IEEE1588
 172 static inline uint64_t
 173 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 174 {
 175         uint64_t pkt_flags = 0;
 176         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 177                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 178                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 179
 180         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 181                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 182                 pkt_flags = PKT_RX_IEEE1588_PTP;
 183         if (tsyn & 0x04) {
 184                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 185                 mb->timesync = tsyn & 0x03;
 186         }
 187
 188         return pkt_flags;
 189 }
 190 #endif
 191
 192 /* For each value it means, datasheet of hardware can tell more details
 193  *
 194  * @note: fix i40e_dev_supported_ptypes_get() if any change here.
 195  */
 196 static inline uint32_t
 197 i40e_rxd_pkt_type_mapping(uint8_t ptype)
 198 {
 199         static const uint32_t type_table[UINT8_MAX + 1] __rte_cache_aligned = {
 200                 /* L2 types */
 201                 /* [0] reserved */
 202                 [1] = RTE_PTYPE_L2_ETHER,
 203                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
 204                 /* [3] - [5] reserved */
 205                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
 206                 /* [7] - [10] reserved */
 207                 [11] = RTE_PTYPE_L2_ETHER_ARP,
 208                 /* [12] - [21] reserved */
 209
 210                 /* Non tunneled IPv4 */
 211                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 212                         RTE_PTYPE_L4_FRAG,
 213                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 214                         RTE_PTYPE_L4_NONFRAG,
 215                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 216                         RTE_PTYPE_L4_UDP,
 217                 /* [25] reserved */
 218                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 219                         RTE_PTYPE_L4_TCP,
 220                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 221                         RTE_PTYPE_L4_SCTP,
 222                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 223                         RTE_PTYPE_L4_ICMP,
 224
 225                 /* IPv4 --> IPv4 */
 226                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 227                         RTE_PTYPE_TUNNEL_IP |
 228                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 229                         RTE_PTYPE_INNER_L4_FRAG,
 230                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 231                         RTE_PTYPE_TUNNEL_IP |
 232                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 233                         RTE_PTYPE_INNER_L4_NONFRAG,
 234                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 235                         RTE_PTYPE_TUNNEL_IP |
 236                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 237                         RTE_PTYPE_INNER_L4_UDP,
 238                 /* [32] reserved */
 239                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 240                         RTE_PTYPE_TUNNEL_IP |
 241                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 242                         RTE_PTYPE_INNER_L4_TCP,
 243                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 244                         RTE_PTYPE_TUNNEL_IP |
 245                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 246                         RTE_PTYPE_INNER_L4_SCTP,
 247                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 248                         RTE_PTYPE_TUNNEL_IP |
 249                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 250                         RTE_PTYPE_INNER_L4_ICMP,
 251
 252                 /* IPv4 --> IPv6 */
 253                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 254                         RTE_PTYPE_TUNNEL_IP |
 255                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 256                         RTE_PTYPE_INNER_L4_FRAG,
 257                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 258                         RTE_PTYPE_TUNNEL_IP |
 259                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 260                         RTE_PTYPE_INNER_L4_NONFRAG,
 261                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 262                         RTE_PTYPE_TUNNEL_IP |
 263                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 264                         RTE_PTYPE_INNER_L4_UDP,
 265                 /* [39] reserved */
 266                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 267                         RTE_PTYPE_TUNNEL_IP |
 268                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 269                         RTE_PTYPE_INNER_L4_TCP,
 270                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 271                         RTE_PTYPE_TUNNEL_IP |
 272                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 273                         RTE_PTYPE_INNER_L4_SCTP,
 274                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 275                         RTE_PTYPE_TUNNEL_IP |
 276                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 277                         RTE_PTYPE_INNER_L4_ICMP,
 278
 279                 /* IPv4 --> GRE/Teredo/VXLAN */
 280                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 281                         RTE_PTYPE_TUNNEL_GRENAT,
 282
 283                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
 284                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 285                         RTE_PTYPE_TUNNEL_GRENAT |
 286                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 287                         RTE_PTYPE_INNER_L4_FRAG,
 288                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 289                         RTE_PTYPE_TUNNEL_GRENAT |
 290                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 291                         RTE_PTYPE_INNER_L4_NONFRAG,
 292                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 293                         RTE_PTYPE_TUNNEL_GRENAT |
 294                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 295                         RTE_PTYPE_INNER_L4_UDP,
 296                 /* [47] reserved */
 297                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 298                         RTE_PTYPE_TUNNEL_GRENAT |
 299                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 300                         RTE_PTYPE_INNER_L4_TCP,
 301                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 302                         RTE_PTYPE_TUNNEL_GRENAT |
 303                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 304                         RTE_PTYPE_INNER_L4_SCTP,
 305                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 306                         RTE_PTYPE_TUNNEL_GRENAT |
 307                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 308                         RTE_PTYPE_INNER_L4_ICMP,
 309
 310                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
 311                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 312                         RTE_PTYPE_TUNNEL_GRENAT |
 313                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 314                         RTE_PTYPE_INNER_L4_FRAG,
 315                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 316                         RTE_PTYPE_TUNNEL_GRENAT |
 317                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 318                         RTE_PTYPE_INNER_L4_NONFRAG,
 319                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 320                         RTE_PTYPE_TUNNEL_GRENAT |
 321                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 322                         RTE_PTYPE_INNER_L4_UDP,
 323                 /* [54] reserved */
 324                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 325                         RTE_PTYPE_TUNNEL_GRENAT |
 326                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 327                         RTE_PTYPE_INNER_L4_TCP,
 328                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 329                         RTE_PTYPE_TUNNEL_GRENAT |
 330                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 331                         RTE_PTYPE_INNER_L4_SCTP,
 332                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 333                         RTE_PTYPE_TUNNEL_GRENAT |
 334                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 335                         RTE_PTYPE_INNER_L4_ICMP,
 336
 337                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
 338                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 339                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
 340
 341                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
 342                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 343                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 344                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 345                         RTE_PTYPE_INNER_L4_FRAG,
 346                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 347                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 348                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 349                         RTE_PTYPE_INNER_L4_NONFRAG,
 350                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 351                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 352                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 353                         RTE_PTYPE_INNER_L4_UDP,
 354                 /* [62] reserved */
 355                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 356                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 357                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 358                         RTE_PTYPE_INNER_L4_TCP,
 359                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 360                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 361                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 362                         RTE_PTYPE_INNER_L4_SCTP,
 363                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 364                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 365                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 366                         RTE_PTYPE_INNER_L4_ICMP,
 367
 368                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
 369                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 370                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 371                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 372                         RTE_PTYPE_INNER_L4_FRAG,
 373                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 374                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 375                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 376                         RTE_PTYPE_INNER_L4_NONFRAG,
 377                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 378                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 379                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 380                         RTE_PTYPE_INNER_L4_UDP,
 381                 /* [69] reserved */
 382                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 383                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 384                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 385                         RTE_PTYPE_INNER_L4_TCP,
 386                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 387                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 388                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 389                         RTE_PTYPE_INNER_L4_SCTP,
 390                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 391                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 392                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 393                         RTE_PTYPE_INNER_L4_ICMP,
 394
 395                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
 396                 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 397                         RTE_PTYPE_TUNNEL_GRENAT |
 398                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
 399
 400                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
 401                 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 402                         RTE_PTYPE_TUNNEL_GRENAT |
 403                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 404                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 405                         RTE_PTYPE_INNER_L4_FRAG,
 406                 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 407                         RTE_PTYPE_TUNNEL_GRENAT |
 408                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 409                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 410                         RTE_PTYPE_INNER_L4_NONFRAG,
 411                 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 412                         RTE_PTYPE_TUNNEL_GRENAT |
 413                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 414                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 415                         RTE_PTYPE_INNER_L4_UDP,
 416                 /* [77] reserved */
 417                 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 418                         RTE_PTYPE_TUNNEL_GRENAT |
 419                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 420                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 421                         RTE_PTYPE_INNER_L4_TCP,
 422                 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 423                         RTE_PTYPE_TUNNEL_GRENAT |
 424                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 425                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 426                         RTE_PTYPE_INNER_L4_SCTP,
 427                 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 428                         RTE_PTYPE_TUNNEL_GRENAT |
 429                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 430                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 431                         RTE_PTYPE_INNER_L4_ICMP,
 432
 433                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
 434                 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 435                         RTE_PTYPE_TUNNEL_GRENAT |
 436                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 437                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 438                         RTE_PTYPE_INNER_L4_FRAG,
 439                 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 440                         RTE_PTYPE_TUNNEL_GRENAT |
 441                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 442                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 443                         RTE_PTYPE_INNER_L4_NONFRAG,
 444                 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 445                         RTE_PTYPE_TUNNEL_GRENAT |
 446                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 447                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 448                         RTE_PTYPE_INNER_L4_UDP,
 449                 /* [84] reserved */
 450                 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 451                         RTE_PTYPE_TUNNEL_GRENAT |
 452                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 453                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 454                         RTE_PTYPE_INNER_L4_TCP,
 455                 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 456                         RTE_PTYPE_TUNNEL_GRENAT |
 457                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 458                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 459                         RTE_PTYPE_INNER_L4_SCTP,
 460                 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 461                         RTE_PTYPE_TUNNEL_GRENAT |
 462                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 463                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 464                         RTE_PTYPE_INNER_L4_ICMP,
 465
 466                 /* Non tunneled IPv6 */
 467                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 468                         RTE_PTYPE_L4_FRAG,
 469                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 470                         RTE_PTYPE_L4_NONFRAG,
 471                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 472                         RTE_PTYPE_L4_UDP,
 473                 /* [91] reserved */
 474                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 475                         RTE_PTYPE_L4_TCP,
 476                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 477                         RTE_PTYPE_L4_SCTP,
 478                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 479                         RTE_PTYPE_L4_ICMP,
 480
 481                 /* IPv6 --> IPv4 */
 482                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 483                         RTE_PTYPE_TUNNEL_IP |
 484                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 485                         RTE_PTYPE_INNER_L4_FRAG,
 486                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 487                         RTE_PTYPE_TUNNEL_IP |
 488                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 489                         RTE_PTYPE_INNER_L4_NONFRAG,
 490                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 491                         RTE_PTYPE_TUNNEL_IP |
 492                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 493                         RTE_PTYPE_INNER_L4_UDP,
 494                 /* [98] reserved */
 495                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 496                         RTE_PTYPE_TUNNEL_IP |
 497                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 498                         RTE_PTYPE_INNER_L4_TCP,
 499                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 500                         RTE_PTYPE_TUNNEL_IP |
 501                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 502                         RTE_PTYPE_INNER_L4_SCTP,
 503                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 504                         RTE_PTYPE_TUNNEL_IP |
 505                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 506                         RTE_PTYPE_INNER_L4_ICMP,
 507
 508                 /* IPv6 --> IPv6 */
 509                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 510                         RTE_PTYPE_TUNNEL_IP |
 511                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 512                         RTE_PTYPE_INNER_L4_FRAG,
 513                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 514                         RTE_PTYPE_TUNNEL_IP |
 515                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 516                         RTE_PTYPE_INNER_L4_NONFRAG,
 517                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 518                         RTE_PTYPE_TUNNEL_IP |
 519                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 520                         RTE_PTYPE_INNER_L4_UDP,
 521                 /* [105] reserved */
 522                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 523                         RTE_PTYPE_TUNNEL_IP |
 524                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 525                         RTE_PTYPE_INNER_L4_TCP,
 526                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 527                         RTE_PTYPE_TUNNEL_IP |
 528                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 529                         RTE_PTYPE_INNER_L4_SCTP,
 530                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 531                         RTE_PTYPE_TUNNEL_IP |
 532                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 533                         RTE_PTYPE_INNER_L4_ICMP,
 534
 535                 /* IPv6 --> GRE/Teredo/VXLAN */
 536                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 537                         RTE_PTYPE_TUNNEL_GRENAT,
 538
 539                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
 540                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 541                         RTE_PTYPE_TUNNEL_GRENAT |
 542                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 543                         RTE_PTYPE_INNER_L4_FRAG,
 544                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 545                         RTE_PTYPE_TUNNEL_GRENAT |
 546                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 547                         RTE_PTYPE_INNER_L4_NONFRAG,
 548                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 549                         RTE_PTYPE_TUNNEL_GRENAT |
 550                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 551                         RTE_PTYPE_INNER_L4_UDP,
 552                 /* [113] reserved */
 553                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 554                         RTE_PTYPE_TUNNEL_GRENAT |
 555                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 556                         RTE_PTYPE_INNER_L4_TCP,
 557                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 558                         RTE_PTYPE_TUNNEL_GRENAT |
 559                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 560                         RTE_PTYPE_INNER_L4_SCTP,
 561                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 562                         RTE_PTYPE_TUNNEL_GRENAT |
 563                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 564                         RTE_PTYPE_INNER_L4_ICMP,
 565
 566                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
 567                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 568                         RTE_PTYPE_TUNNEL_GRENAT |
 569                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 570                         RTE_PTYPE_INNER_L4_FRAG,
 571                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 572                         RTE_PTYPE_TUNNEL_GRENAT |
 573                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 574                         RTE_PTYPE_INNER_L4_NONFRAG,
 575                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 576                         RTE_PTYPE_TUNNEL_GRENAT |
 577                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 578                         RTE_PTYPE_INNER_L4_UDP,
 579                 /* [120] reserved */
 580                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 581                         RTE_PTYPE_TUNNEL_GRENAT |
 582                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 583                         RTE_PTYPE_INNER_L4_TCP,
 584                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 585                         RTE_PTYPE_TUNNEL_GRENAT |
 586                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 587                         RTE_PTYPE_INNER_L4_SCTP,
 588                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 589                         RTE_PTYPE_TUNNEL_GRENAT |
 590                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 591                         RTE_PTYPE_INNER_L4_ICMP,
 592
 593                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
 594                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 595                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
 596
 597                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
 598                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 599                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 600                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 601                         RTE_PTYPE_INNER_L4_FRAG,
 602                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 603                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 604                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 605                         RTE_PTYPE_INNER_L4_NONFRAG,
 606                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 607                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 608                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 609                         RTE_PTYPE_INNER_L4_UDP,
 610                 /* [128] reserved */
 611                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 612                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 613                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 614                         RTE_PTYPE_INNER_L4_TCP,
 615                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 616                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 617                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 618                         RTE_PTYPE_INNER_L4_SCTP,
 619                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 620                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 621                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 622                         RTE_PTYPE_INNER_L4_ICMP,
 623
 624                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
 625                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 626                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 627                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 628                         RTE_PTYPE_INNER_L4_FRAG,
 629                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 630                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 631                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 632                         RTE_PTYPE_INNER_L4_NONFRAG,
 633                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 634                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 635                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 636                         RTE_PTYPE_INNER_L4_UDP,
 637                 /* [135] reserved */
 638                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 639                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 640                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 641                         RTE_PTYPE_INNER_L4_TCP,
 642                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 643                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 644                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 645                         RTE_PTYPE_INNER_L4_SCTP,
 646                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 647                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 648                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 649                         RTE_PTYPE_INNER_L4_ICMP,
 650
 651                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
 652                 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 653                         RTE_PTYPE_TUNNEL_GRENAT |
 654                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
 655
 656                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
 657                 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 658                         RTE_PTYPE_TUNNEL_GRENAT |
 659                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 660                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 661                         RTE_PTYPE_INNER_L4_FRAG,
 662                 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 663                         RTE_PTYPE_TUNNEL_GRENAT |
 664                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 665                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 666                         RTE_PTYPE_INNER_L4_NONFRAG,
 667                 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 668                         RTE_PTYPE_TUNNEL_GRENAT |
 669                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 670                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 671                         RTE_PTYPE_INNER_L4_UDP,
 672                 /* [143] reserved */
 673                 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 674                         RTE_PTYPE_TUNNEL_GRENAT |
 675                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 676                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 677                         RTE_PTYPE_INNER_L4_TCP,
 678                 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 679                         RTE_PTYPE_TUNNEL_GRENAT |
 680                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 681                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 682                         RTE_PTYPE_INNER_L4_SCTP,
 683                 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 684                         RTE_PTYPE_TUNNEL_GRENAT |
 685                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 686                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 687                         RTE_PTYPE_INNER_L4_ICMP,
 688
 689                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
 690                 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 691                         RTE_PTYPE_TUNNEL_GRENAT |
 692                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 693                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 694                         RTE_PTYPE_INNER_L4_FRAG,
 695                 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 696                         RTE_PTYPE_TUNNEL_GRENAT |
 697                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 698                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 699                         RTE_PTYPE_INNER_L4_NONFRAG,
 700                 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 701                         RTE_PTYPE_TUNNEL_GRENAT |
 702                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 703                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 704                         RTE_PTYPE_INNER_L4_UDP,
 705                 /* [150] reserved */
 706                 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 707                         RTE_PTYPE_TUNNEL_GRENAT |
 708                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 709                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 710                         RTE_PTYPE_INNER_L4_TCP,
 711                 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 712                         RTE_PTYPE_TUNNEL_GRENAT |
 713                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 714                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 715                         RTE_PTYPE_INNER_L4_SCTP,
 716                 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 717                         RTE_PTYPE_TUNNEL_GRENAT |
 718                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 719                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 720                         RTE_PTYPE_INNER_L4_ICMP,
 721
 722                 /* L2 NSH packet type */
 723                 [154] = RTE_PTYPE_L2_ETHER_NSH,
 724                 [155] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 725                         RTE_PTYPE_L4_FRAG,
 726                 [156] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 727                         RTE_PTYPE_L4_NONFRAG,
 728                 [157] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 729                         RTE_PTYPE_L4_UDP,
 730                 [158] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 731                         RTE_PTYPE_L4_TCP,
 732                 [159] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 733                         RTE_PTYPE_L4_SCTP,
 734                 [160] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 735                         RTE_PTYPE_L4_ICMP,
 736                 [161] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 737                         RTE_PTYPE_L4_FRAG,
 738                 [162] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 739                         RTE_PTYPE_L4_NONFRAG,
 740                 [163] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 741                         RTE_PTYPE_L4_UDP,
 742                 [164] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 743                         RTE_PTYPE_L4_TCP,
 744                 [165] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 745                         RTE_PTYPE_L4_SCTP,
 746                 [166] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 747                         RTE_PTYPE_L4_ICMP,
 748
 749                 /* All others reserved */
 750         };
 751
 752         return type_table[ptype];
 753 }
 754
 755 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 756 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 757 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 758 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 759 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 760
 761 static inline uint64_t
 762 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 763 {
 764         uint64_t flags = 0;
 765 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 766         uint16_t flexbh, flexbl;
 767
 768         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 769                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 770                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 771         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 772                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 773                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 774
 775
 776         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 777                 mb->hash.fdir.hi =
 778                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 779                 flags |= PKT_RX_FDIR_ID;
 780         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 781                 mb->hash.fdir.hi =
 782                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 783                 flags |= PKT_RX_FDIR_FLX;
 784         }
 785         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 786                 mb->hash.fdir.lo =
 787                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 788                 flags |= PKT_RX_FDIR_FLX;
 789         }
 790 #else
 791         mb->hash.fdir.hi =
 792                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 793         flags |= PKT_RX_FDIR_ID;
 794 #endif
 795         return flags;
 796 }
 797 static inline void
 798 i40e_txd_enable_checksum(uint64_t ol_flags,
 799                         uint32_t *td_cmd,
 800                         uint32_t *td_offset,
 801                         union i40e_tx_offload tx_offload,
 802                         uint32_t *cd_tunneling)
 803 {
 804         /* UDP tunneling packet TX checksum offload */
 805         if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
 806
 807                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 808                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 809
 810                 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 811                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 812                 else if (ol_flags & PKT_TX_OUTER_IPV4)
 813                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 814                 else if (ol_flags & PKT_TX_OUTER_IPV6)
 815                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 816
 817                 /* Now set the ctx descriptor fields */
 818                 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 819                                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
 820                                 (tx_offload.l2_len >> 1) <<
 821                                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 822
 823         } else
 824                 *td_offset |= (tx_offload.l2_len >> 1)
 825                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 826
 827         /* Enable L3 checksum offloads */
 828         if (ol_flags & PKT_TX_IP_CKSUM) {
 829                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 830                 *td_offset |= (tx_offload.l3_len >> 2)
 831                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 832         } else if (ol_flags & PKT_TX_IPV4) {
 833                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 834                 *td_offset |= (tx_offload.l3_len >> 2)
 835                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 836         } else if (ol_flags & PKT_TX_IPV6) {
 837                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 838                 *td_offset |= (tx_offload.l3_len >> 2)
 839                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 840         }
 841
 842         if (ol_flags & PKT_TX_TCP_SEG) {
 843                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 844                 *td_offset |= (tx_offload.l4_len >> 2)
 845                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 846                 return;
 847         }
 848
 849         /* Enable L4 checksum offloads */
 850         switch (ol_flags & PKT_TX_L4_MASK) {
 851         case PKT_TX_TCP_CKSUM:
 852                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 853                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 854                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 855                 break;
 856         case PKT_TX_SCTP_CKSUM:
 857                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 858                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 859                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 860                 break;
 861         case PKT_TX_UDP_CKSUM:
 862                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 863                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 864                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 865                 break;
 866         default:
 867                 break;
 868         }
 869 }
 870
 871 /* Construct the tx flags */
 872 static inline uint64_t
 873 i40e_build_ctob(uint32_t td_cmd,
 874                 uint32_t td_offset,
 875                 unsigned int size,
 876                 uint32_t td_tag)
 877 {
 878         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 879                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 880                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 881                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 882                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 883 }
 884
 885 static inline int
 886 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 887 {
 888         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 889         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 890         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 891         uint16_t nb_tx_desc = txq->nb_tx_desc;
 892         uint16_t desc_to_clean_to;
 893         uint16_t nb_tx_to_clean;
 894
 895         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 896         if (desc_to_clean_to >= nb_tx_desc)
 897                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 898
 899         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 900         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 901                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 902                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 903                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 904                         "(port=%d queue=%d)", desc_to_clean_to,
 905                                 txq->port_id, txq->queue_id);
 906                 return -1;
 907         }
 908
 909         if (last_desc_cleaned > desc_to_clean_to)
 910                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 911                                                         desc_to_clean_to);
 912         else
 913                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 914                                         last_desc_cleaned);
 915
 916         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 917
 918         txq->last_desc_cleaned = desc_to_clean_to;
 919         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 920
 921         return 0;
 922 }
 923
 924 static inline int
 925 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 926 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 927 #else
 928 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 929 #endif
 930 {
 931         int ret = 0;
 932
 933 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 934         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 935                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 936                              "rxq->rx_free_thresh=%d, "
 937                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 938                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 939                 ret = -EINVAL;
 940         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 941                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 942                              "rxq->rx_free_thresh=%d, "
 943                              "rxq->nb_rx_desc=%d",
 944                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 945                 ret = -EINVAL;
 946         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 947                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 948                              "rxq->nb_rx_desc=%d, "
 949                              "rxq->rx_free_thresh=%d",
 950                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 951                 ret = -EINVAL;
 952         } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
 953                                 RTE_PMD_I40E_RX_MAX_BURST))) {
 954                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 955                              "rxq->nb_rx_desc=%d, "
 956                              "I40E_MAX_RING_DESC=%d, "
 957                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 958                              rxq->nb_rx_desc, I40E_MAX_RING_DESC,
 959                              RTE_PMD_I40E_RX_MAX_BURST);
 960                 ret = -EINVAL;
 961         }
 962 #else
 963         ret = -EINVAL;
 964 #endif
 965
 966         return ret;
 967 }
 968
 969 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 970 #define I40E_LOOK_AHEAD 8
 971 #if (I40E_LOOK_AHEAD != 8)
 972 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 973 #endif
 974 static inline int
 975 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 976 {
 977         volatile union i40e_rx_desc *rxdp;
 978         struct i40e_rx_entry *rxep;
 979         struct rte_mbuf *mb;
 980         uint16_t pkt_len;
 981         uint64_t qword1;
 982         uint32_t rx_status;
 983         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 984         int32_t i, j, nb_rx = 0;
 985         uint64_t pkt_flags;
 986
 987         rxdp = &rxq->rx_ring[rxq->rx_tail];
 988         rxep = &rxq->sw_ring[rxq->rx_tail];
 989
 990         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 991         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 992                                 I40E_RXD_QW1_STATUS_SHIFT;
 993
 994         /* Make sure there is at least 1 packet to receive */
 995         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 996                 return 0;
 997
 998         /**
 999          * Scan LOOK_AHEAD descriptors at a time to determine which
1000          * descriptors reference packets that are ready to be received.
1001          */
1002         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
1003                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
1004                 /* Read desc statuses backwards to avoid race condition */
1005                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
1006                         qword1 = rte_le_to_cpu_64(\
1007                                 rxdp[j].wb.qword1.status_error_len);
1008                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1009                                         I40E_RXD_QW1_STATUS_SHIFT;
1010                 }
1011
1012                 /* Compute how many status bits were set */
1013                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
1014                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
1015
1016                 nb_rx += nb_dd;
1017
1018                 /* Translate descriptor info to mbuf parameters */
1019                 for (j = 0; j < nb_dd; j++) {
1020                         mb = rxep[j].mbuf;
1021                         qword1 = rte_le_to_cpu_64(\
1022                                 rxdp[j].wb.qword1.status_error_len);
1023                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1024                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1025                         mb->data_len = pkt_len;
1026                         mb->pkt_len = pkt_len;
1027                         mb->ol_flags = 0;
1028                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
1029                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1030                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1031                         mb->packet_type =
1032                                 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1033                                                 I40E_RXD_QW1_PTYPE_MASK) >>
1034                                                 I40E_RXD_QW1_PTYPE_SHIFT));
1035                         if (pkt_flags & PKT_RX_RSS_HASH)
1036                                 mb->hash.rss = rte_le_to_cpu_32(\
1037                                         rxdp[j].wb.qword0.hi_dword.rss);
1038                         if (pkt_flags & PKT_RX_FDIR)
1039                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
1040
1041 #ifdef RTE_LIBRTE_IEEE1588
1042                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
1043 #endif
1044                         mb->ol_flags |= pkt_flags;
1045
1046                 }
1047
1048                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
1049                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1050
1051                 if (nb_dd != I40E_LOOK_AHEAD)
1052                         break;
1053         }
1054
1055         /* Clear software ring entries */
1056         for (i = 0; i < nb_rx; i++)
1057                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1058
1059         return nb_rx;
1060 }
1061
1062 static inline uint16_t
1063 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
1064                         struct rte_mbuf **rx_pkts,
1065                         uint16_t nb_pkts)
1066 {
1067         uint16_t i;
1068         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1069
1070         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1071
1072         for (i = 0; i < nb_pkts; i++)
1073                 rx_pkts[i] = stage[i];
1074
1075         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1076         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1077
1078         return nb_pkts;
1079 }
1080
1081 static inline int
1082 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
1083 {
1084         volatile union i40e_rx_desc *rxdp;
1085         struct i40e_rx_entry *rxep;
1086         struct rte_mbuf *mb;
1087         uint16_t alloc_idx, i;
1088         uint64_t dma_addr;
1089         int diag;
1090
1091         /* Allocate buffers in bulk */
1092         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1093                                 (rxq->rx_free_thresh - 1));
1094         rxep = &(rxq->sw_ring[alloc_idx]);
1095         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1096                                         rxq->rx_free_thresh);
1097         if (unlikely(diag != 0)) {
1098                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
1099                 return -ENOMEM;
1100         }
1101
1102         rxdp = &rxq->rx_ring[alloc_idx];
1103         for (i = 0; i < rxq->rx_free_thresh; i++) {
1104                 if (likely(i < (rxq->rx_free_thresh - 1)))
1105                         /* Prefetch next mbuf */
1106                         rte_prefetch0(rxep[i + 1].mbuf);
1107
1108                 mb = rxep[i].mbuf;
1109                 rte_mbuf_refcnt_set(mb, 1);
1110                 mb->next = NULL;
1111                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1112                 mb->nb_segs = 1;
1113                 mb->port = rxq->port_id;
1114                 dma_addr = rte_cpu_to_le_64(\
1115                         rte_mbuf_data_dma_addr_default(mb));
1116                 rxdp[i].read.hdr_addr = 0;
1117                 rxdp[i].read.pkt_addr = dma_addr;
1118         }
1119
1120         /* Update rx tail regsiter */
1121         rte_wmb();
1122         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1123
1124         rxq->rx_free_trigger =
1125                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1126         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1127                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1128
1129         return 0;
1130 }
1131
1132 static inline uint16_t
1133 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1134 {
1135         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
1136         uint16_t nb_rx = 0;
1137
1138         if (!nb_pkts)
1139                 return 0;
1140
1141         if (rxq->rx_nb_avail)
1142                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1143
1144         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
1145         rxq->rx_next_avail = 0;
1146         rxq->rx_nb_avail = nb_rx;
1147         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1148
1149         if (rxq->rx_tail > rxq->rx_free_trigger) {
1150                 if (i40e_rx_alloc_bufs(rxq) != 0) {
1151                         uint16_t i, j;
1152
1153                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1154                                    "port_id=%u, queue_id=%u",
1155                                    rxq->port_id, rxq->queue_id);
1156                         rxq->rx_nb_avail = 0;
1157                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1158                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1159                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1160
1161                         return 0;
1162                 }
1163         }
1164
1165         if (rxq->rx_tail >= rxq->nb_rx_desc)
1166                 rxq->rx_tail = 0;
1167
1168         if (rxq->rx_nb_avail)
1169                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1170
1171         return 0;
1172 }
1173
1174 static uint16_t
1175 i40e_recv_pkts_bulk_alloc(void *rx_queue,
1176                           struct rte_mbuf **rx_pkts,
1177                           uint16_t nb_pkts)
1178 {
1179         uint16_t nb_rx = 0, n, count;
1180
1181         if (unlikely(nb_pkts == 0))
1182                 return 0;
1183
1184         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
1185                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1186
1187         while (nb_pkts) {
1188                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
1189                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1190                 nb_rx = (uint16_t)(nb_rx + count);
1191                 nb_pkts = (uint16_t)(nb_pkts - count);
1192                 if (count < n)
1193                         break;
1194         }
1195
1196         return nb_rx;
1197 }
1198 #else
1199 static uint16_t
1200 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
1201                           struct rte_mbuf __rte_unused **rx_pkts,
1202                           uint16_t __rte_unused nb_pkts)
1203 {
1204         return 0;
1205 }
1206 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1207
1208 uint16_t
1209 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1210 {
1211         struct i40e_rx_queue *rxq;
1212         volatile union i40e_rx_desc *rx_ring;
1213         volatile union i40e_rx_desc *rxdp;
1214         union i40e_rx_desc rxd;
1215         struct i40e_rx_entry *sw_ring;
1216         struct i40e_rx_entry *rxe;
1217         struct rte_mbuf *rxm;
1218         struct rte_mbuf *nmb;
1219         uint16_t nb_rx;
1220         uint32_t rx_status;
1221         uint64_t qword1;
1222         uint16_t rx_packet_len;
1223         uint16_t rx_id, nb_hold;
1224         uint64_t dma_addr;
1225         uint64_t pkt_flags;
1226
1227         nb_rx = 0;
1228         nb_hold = 0;
1229         rxq = rx_queue;
1230         rx_id = rxq->rx_tail;
1231         rx_ring = rxq->rx_ring;
1232         sw_ring = rxq->sw_ring;
1233
1234         while (nb_rx < nb_pkts) {
1235                 rxdp = &rx_ring[rx_id];
1236                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1237                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1238                                 >> I40E_RXD_QW1_STATUS_SHIFT;
1239
1240                 /* Check the DD bit first */
1241                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1242                         break;
1243
1244                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1245                 if (unlikely(!nmb))
1246                         break;
1247                 rxd = *rxdp;
1248
1249                 nb_hold++;
1250                 rxe = &sw_ring[rx_id];
1251                 rx_id++;
1252                 if (unlikely(rx_id == rxq->nb_rx_desc))
1253                         rx_id = 0;
1254
1255                 /* Prefetch next mbuf */
1256                 rte_prefetch0(sw_ring[rx_id].mbuf);
1257
1258                 /**
1259                  * When next RX descriptor is on a cache line boundary,
1260                  * prefetch the next 4 RX descriptors and next 8 pointers
1261                  * to mbufs.
1262                  */
1263                 if ((rx_id & 0x3) == 0) {
1264                         rte_prefetch0(&rx_ring[rx_id]);
1265                         rte_prefetch0(&sw_ring[rx_id]);
1266                 }
1267                 rxm = rxe->mbuf;
1268                 rxe->mbuf = nmb;
1269                 dma_addr =
1270                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
1271                 rxdp->read.hdr_addr = 0;
1272                 rxdp->read.pkt_addr = dma_addr;
1273
1274                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1275                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1276
1277                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1278                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1279                 rxm->nb_segs = 1;
1280                 rxm->next = NULL;
1281                 rxm->pkt_len = rx_packet_len;
1282                 rxm->data_len = rx_packet_len;
1283                 rxm->port = rxq->port_id;
1284                 rxm->ol_flags = 0;
1285                 i40e_rxd_to_vlan_tci(rxm, &rxd);
1286                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1287                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1288                 rxm->packet_type =
1289                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1290                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1291                 if (pkt_flags & PKT_RX_RSS_HASH)
1292                         rxm->hash.rss =
1293                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1294                 if (pkt_flags & PKT_RX_FDIR)
1295                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1296
1297 #ifdef RTE_LIBRTE_IEEE1588
1298                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
1299 #endif
1300                 rxm->ol_flags |= pkt_flags;
1301
1302                 rx_pkts[nb_rx++] = rxm;
1303         }
1304         rxq->rx_tail = rx_id;
1305
1306         /**
1307          * If the number of free RX descriptors is greater than the RX free
1308          * threshold of the queue, advance the receive tail register of queue.
1309          * Update that register with the value of the last processed RX
1310          * descriptor minus 1.
1311          */
1312         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1313         if (nb_hold > rxq->rx_free_thresh) {
1314                 rx_id = (uint16_t) ((rx_id == 0) ?
1315                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1316                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1317                 nb_hold = 0;
1318         }
1319         rxq->nb_rx_hold = nb_hold;
1320
1321         return nb_rx;
1322 }
1323
1324 uint16_t
1325 i40e_recv_scattered_pkts(void *rx_queue,
1326                          struct rte_mbuf **rx_pkts,
1327                          uint16_t nb_pkts)
1328 {
1329         struct i40e_rx_queue *rxq = rx_queue;
1330         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
1331         volatile union i40e_rx_desc *rxdp;
1332         union i40e_rx_desc rxd;
1333         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
1334         struct i40e_rx_entry *rxe;
1335         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1336         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1337         struct rte_mbuf *nmb, *rxm;
1338         uint16_t rx_id = rxq->rx_tail;
1339         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1340         uint32_t rx_status;
1341         uint64_t qword1;
1342         uint64_t dma_addr;
1343         uint64_t pkt_flags;
1344
1345         while (nb_rx < nb_pkts) {
1346                 rxdp = &rx_ring[rx_id];
1347                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1348                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1349                                         I40E_RXD_QW1_STATUS_SHIFT;
1350
1351                 /* Check the DD bit */
1352                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1353                         break;
1354
1355                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1356                 if (unlikely(!nmb))
1357                         break;
1358                 rxd = *rxdp;
1359                 nb_hold++;
1360                 rxe = &sw_ring[rx_id];
1361                 rx_id++;
1362                 if (rx_id == rxq->nb_rx_desc)
1363                         rx_id = 0;
1364
1365                 /* Prefetch next mbuf */
1366                 rte_prefetch0(sw_ring[rx_id].mbuf);
1367
1368                 /**
1369                  * When next RX descriptor is on a cache line boundary,
1370                  * prefetch the next 4 RX descriptors and next 8 pointers
1371                  * to mbufs.
1372                  */
1373                 if ((rx_id & 0x3) == 0) {
1374                         rte_prefetch0(&rx_ring[rx_id]);
1375                         rte_prefetch0(&sw_ring[rx_id]);
1376                 }
1377
1378                 rxm = rxe->mbuf;
1379                 rxe->mbuf = nmb;
1380                 dma_addr =
1381                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
1382
1383                 /* Set data buffer address and data length of the mbuf */
1384                 rxdp->read.hdr_addr = 0;
1385                 rxdp->read.pkt_addr = dma_addr;
1386                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1387                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1388                 rxm->data_len = rx_packet_len;
1389                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1390
1391                 /**
1392                  * If this is the first buffer of the received packet, set the
1393                  * pointer to the first mbuf of the packet and initialize its
1394                  * context. Otherwise, update the total length and the number
1395                  * of segments of the current scattered packet, and update the
1396                  * pointer to the last mbuf of the current packet.
1397                  */
1398                 if (!first_seg) {
1399                         first_seg = rxm;
1400                         first_seg->nb_segs = 1;
1401                         first_seg->pkt_len = rx_packet_len;
1402                 } else {
1403                         first_seg->pkt_len =
1404                                 (uint16_t)(first_seg->pkt_len +
1405                                                 rx_packet_len);
1406                         first_seg->nb_segs++;
1407                         last_seg->next = rxm;
1408                 }
1409
1410                 /**
1411                  * If this is not the last buffer of the received packet,
1412                  * update the pointer to the last mbuf of the current scattered
1413                  * packet and continue to parse the RX ring.
1414                  */
1415                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1416                         last_seg = rxm;
1417                         continue;
1418                 }
1419
1420                 /**
1421                  * This is the last buffer of the received packet. If the CRC
1422                  * is not stripped by the hardware:
1423                  *  - Subtract the CRC length from the total packet length.
1424                  *  - If the last buffer only contains the whole CRC or a part
1425                  *  of it, free the mbuf associated to the last buffer. If part
1426                  *  of the CRC is also contained in the previous mbuf, subtract
1427                  *  the length of that CRC part from the data length of the
1428                  *  previous mbuf.
1429                  */
1430                 rxm->next = NULL;
1431                 if (unlikely(rxq->crc_len > 0)) {
1432                         first_seg->pkt_len -= ETHER_CRC_LEN;
1433                         if (rx_packet_len <= ETHER_CRC_LEN) {
1434                                 rte_pktmbuf_free_seg(rxm);
1435                                 first_seg->nb_segs--;
1436                                 last_seg->data_len =
1437                                         (uint16_t)(last_seg->data_len -
1438                                         (ETHER_CRC_LEN - rx_packet_len));
1439                                 last_seg->next = NULL;
1440                         } else
1441                                 rxm->data_len = (uint16_t)(rx_packet_len -
1442                                                                 ETHER_CRC_LEN);
1443                 }
1444
1445                 first_seg->port = rxq->port_id;
1446                 first_seg->ol_flags = 0;
1447                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
1448                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1449                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1450                 first_seg->packet_type =
1451                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1452                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1453                 if (pkt_flags & PKT_RX_RSS_HASH)
1454                         rxm->hash.rss =
1455                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1456                 if (pkt_flags & PKT_RX_FDIR)
1457                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1458
1459 #ifdef RTE_LIBRTE_IEEE1588
1460                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
1461 #endif
1462                 first_seg->ol_flags |= pkt_flags;
1463
1464                 /* Prefetch data of first segment, if configured to do so. */
1465                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1466                         first_seg->data_off));
1467                 rx_pkts[nb_rx++] = first_seg;
1468                 first_seg = NULL;
1469         }
1470
1471         /* Record index of the next RX descriptor to probe. */
1472         rxq->rx_tail = rx_id;
1473         rxq->pkt_first_seg = first_seg;
1474         rxq->pkt_last_seg = last_seg;
1475
1476         /**
1477          * If the number of free RX descriptors is greater than the RX free
1478          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1479          * register. Update the RDT with the value of the last processed RX
1480          * descriptor minus 1, to guarantee that the RDT register is never
1481          * equal to the RDH register, which creates a "full" ring situtation
1482          * from the hardware point of view.
1483          */
1484         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1485         if (nb_hold > rxq->rx_free_thresh) {
1486                 rx_id = (uint16_t)(rx_id == 0 ?
1487                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1488                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1489                 nb_hold = 0;
1490         }
1491         rxq->nb_rx_hold = nb_hold;
1492
1493         return nb_rx;
1494 }
1495
1496 /* Check if the context descriptor is needed for TX offloading */
1497 static inline uint16_t
1498 i40e_calc_context_desc(uint64_t flags)
1499 {
1500         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
1501                 PKT_TX_TCP_SEG |
1502                 PKT_TX_QINQ_PKT;
1503
1504 #ifdef RTE_LIBRTE_IEEE1588
1505         mask |= PKT_TX_IEEE1588_TMST;
1506 #endif
1507
1508         return (flags & mask) ? 1 : 0;
1509 }
1510
1511 /* set i40e TSO context descriptor */
1512 static inline uint64_t
1513 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1514 {
1515         uint64_t ctx_desc = 0;
1516         uint32_t cd_cmd, hdr_len, cd_tso_len;
1517
1518         if (!tx_offload.l4_len) {
1519                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1520                 return ctx_desc;
1521         }
1522
1523         /**
1524          * in case of tunneling packet, the outer_l2_len and
1525          * outer_l3_len must be 0.
1526          */
1527         hdr_len = tx_offload.outer_l2_len +
1528                 tx_offload.outer_l3_len +
1529                 tx_offload.l2_len +
1530                 tx_offload.l3_len +
1531                 tx_offload.l4_len;
1532
1533         cd_cmd = I40E_TX_CTX_DESC_TSO;
1534         cd_tso_len = mbuf->pkt_len - hdr_len;
1535         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1536                 ((uint64_t)cd_tso_len <<
1537                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1538                 ((uint64_t)mbuf->tso_segsz <<
1539                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1540
1541         return ctx_desc;
1542 }
1543
1544 uint16_t
1545 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1546 {
1547         struct i40e_tx_queue *txq;
1548         struct i40e_tx_entry *sw_ring;
1549         struct i40e_tx_entry *txe, *txn;
1550         volatile struct i40e_tx_desc *txd;
1551         volatile struct i40e_tx_desc *txr;
1552         struct rte_mbuf *tx_pkt;
1553         struct rte_mbuf *m_seg;
1554         uint32_t cd_tunneling_params;
1555         uint16_t tx_id;
1556         uint16_t nb_tx;
1557         uint32_t td_cmd;
1558         uint32_t td_offset;
1559         uint32_t tx_flags;
1560         uint32_t td_tag;
1561         uint64_t ol_flags;
1562         uint16_t nb_used;
1563         uint16_t nb_ctx;
1564         uint16_t tx_last;
1565         uint16_t slen;
1566         uint64_t buf_dma_addr;
1567         union i40e_tx_offload tx_offload = {0};
1568
1569         txq = tx_queue;
1570         sw_ring = txq->sw_ring;
1571         txr = txq->tx_ring;
1572         tx_id = txq->tx_tail;
1573         txe = &sw_ring[tx_id];
1574
1575         /* Check if the descriptor ring needs to be cleaned. */
1576         if (txq->nb_tx_free < txq->tx_free_thresh)
1577                 i40e_xmit_cleanup(txq);
1578
1579         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1580                 td_cmd = 0;
1581                 td_tag = 0;
1582                 td_offset = 0;
1583                 tx_flags = 0;
1584
1585                 tx_pkt = *tx_pkts++;
1586                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1587
1588                 ol_flags = tx_pkt->ol_flags;
1589                 tx_offload.l2_len = tx_pkt->l2_len;
1590                 tx_offload.l3_len = tx_pkt->l3_len;
1591                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1592                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1593                 tx_offload.l4_len = tx_pkt->l4_len;
1594                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1595
1596                 /* Calculate the number of context descriptors needed. */
1597                 nb_ctx = i40e_calc_context_desc(ol_flags);
1598
1599                 /**
1600                  * The number of descriptors that must be allocated for
1601                  * a packet equals to the number of the segments of that
1602                  * packet plus 1 context descriptor if needed.
1603                  */
1604                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1605                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1606
1607                 /* Circular ring */
1608                 if (tx_last >= txq->nb_tx_desc)
1609                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1610
1611                 if (nb_used > txq->nb_tx_free) {
1612                         if (i40e_xmit_cleanup(txq) != 0) {
1613                                 if (nb_tx == 0)
1614                                         return 0;
1615                                 goto end_of_tx;
1616                         }
1617                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1618                                 while (nb_used > txq->nb_tx_free) {
1619                                         if (i40e_xmit_cleanup(txq) != 0) {
1620                                                 if (nb_tx == 0)
1621                                                         return 0;
1622                                                 goto end_of_tx;
1623                                         }
1624                                 }
1625                         }
1626                 }
1627
1628                 /* Descriptor based VLAN insertion */
1629                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1630                         tx_flags |= tx_pkt->vlan_tci <<
1631                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1632                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1633                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1634                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1635                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1636                 }
1637
1638                 /* Always enable CRC offload insertion */
1639                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1640
1641                 /* Enable checksum offloading */
1642                 cd_tunneling_params = 0;
1643                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK) {
1644                         i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1645                                 tx_offload, &cd_tunneling_params);
1646                 }
1647
1648                 if (nb_ctx) {
1649                         /* Setup TX context descriptor if required */
1650                         volatile struct i40e_tx_context_desc *ctx_txd =
1651                                 (volatile struct i40e_tx_context_desc *)\
1652                                                         &txr[tx_id];
1653                         uint16_t cd_l2tag2 = 0;
1654                         uint64_t cd_type_cmd_tso_mss =
1655                                 I40E_TX_DESC_DTYPE_CONTEXT;
1656
1657                         txn = &sw_ring[txe->next_id];
1658                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1659                         if (txe->mbuf != NULL) {
1660                                 rte_pktmbuf_free_seg(txe->mbuf);
1661                                 txe->mbuf = NULL;
1662                         }
1663
1664                         /* TSO enabled means no timestamp */
1665                         if (ol_flags & PKT_TX_TCP_SEG)
1666                                 cd_type_cmd_tso_mss |=
1667                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1668                         else {
1669 #ifdef RTE_LIBRTE_IEEE1588
1670                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1671                                         cd_type_cmd_tso_mss |=
1672                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1673                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1674 #endif
1675                         }
1676
1677                         ctx_txd->tunneling_params =
1678                                 rte_cpu_to_le_32(cd_tunneling_params);
1679                         if (ol_flags & PKT_TX_QINQ_PKT) {
1680                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1681                                 cd_type_cmd_tso_mss |=
1682                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1683                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1684                         }
1685                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1686                         ctx_txd->type_cmd_tso_mss =
1687                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1688
1689                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1690                                 "tunneling_params: %#x;\n"
1691                                 "l2tag2: %#hx;\n"
1692                                 "rsvd: %#hx;\n"
1693                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1694                                 tx_pkt, tx_id,
1695                                 ctx_txd->tunneling_params,
1696                                 ctx_txd->l2tag2,
1697                                 ctx_txd->rsvd,
1698                                 ctx_txd->type_cmd_tso_mss);
1699
1700                         txe->last_id = tx_last;
1701                         tx_id = txe->next_id;
1702                         txe = txn;
1703                 }
1704
1705                 m_seg = tx_pkt;
1706                 do {
1707                         txd = &txr[tx_id];
1708                         txn = &sw_ring[txe->next_id];
1709
1710                         if (txe->mbuf)
1711                                 rte_pktmbuf_free_seg(txe->mbuf);
1712                         txe->mbuf = m_seg;
1713
1714                         /* Setup TX Descriptor */
1715                         slen = m_seg->data_len;
1716                         buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1717
1718                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1719                                 "buf_dma_addr: %#"PRIx64";\n"
1720                                 "td_cmd: %#x;\n"
1721                                 "td_offset: %#x;\n"
1722                                 "td_len: %u;\n"
1723                                 "td_tag: %#x;\n",
1724                                 tx_pkt, tx_id, buf_dma_addr,
1725                                 td_cmd, td_offset, slen, td_tag);
1726
1727                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1728                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1729                                                 td_offset, slen, td_tag);
1730                         txe->last_id = tx_last;
1731                         tx_id = txe->next_id;
1732                         txe = txn;
1733                         m_seg = m_seg->next;
1734                 } while (m_seg != NULL);
1735
1736                 /* The last packet data descriptor needs End Of Packet (EOP) */
1737                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1738                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1739                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1740
1741                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1742                         PMD_TX_FREE_LOG(DEBUG,
1743                                         "Setting RS bit on TXD id="
1744                                         "%4u (port=%d queue=%d)",
1745                                         tx_last, txq->port_id, txq->queue_id);
1746
1747                         td_cmd |= I40E_TX_DESC_CMD_RS;
1748
1749                         /* Update txq RS bit counters */
1750                         txq->nb_tx_used = 0;
1751                 }
1752
1753                 txd->cmd_type_offset_bsz |=
1754                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1755                                         I40E_TXD_QW1_CMD_SHIFT);
1756         }
1757
1758 end_of_tx:
1759         rte_wmb();
1760
1761         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1762                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1763                    (unsigned) tx_id, (unsigned) nb_tx);
1764
1765         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1766         txq->tx_tail = tx_id;
1767
1768         return nb_tx;
1769 }
1770
1771 static inline int __attribute__((always_inline))
1772 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1773 {
1774         struct i40e_tx_entry *txep;
1775         uint16_t i;
1776
1777         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1778                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1779                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1780                 return 0;
1781
1782         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1783
1784         for (i = 0; i < txq->tx_rs_thresh; i++)
1785                 rte_prefetch0((txep + i)->mbuf);
1786
1787         if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1788                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1789                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1790                         txep->mbuf = NULL;
1791                 }
1792         } else {
1793                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1794                         rte_pktmbuf_free_seg(txep->mbuf);
1795                         txep->mbuf = NULL;
1796                 }
1797         }
1798
1799         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1800         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1801         if (txq->tx_next_dd >= txq->nb_tx_desc)
1802                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1803
1804         return txq->tx_rs_thresh;
1805 }
1806
1807 /* Populate 4 descriptors with data from 4 mbufs */
1808 static inline void
1809 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1810 {
1811         uint64_t dma_addr;
1812         uint32_t i;
1813
1814         for (i = 0; i < 4; i++, txdp++, pkts++) {
1815                 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1816                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1817                 txdp->cmd_type_offset_bsz =
1818                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1819                                         (*pkts)->data_len, 0);
1820         }
1821 }
1822
1823 /* Populate 1 descriptor with data from 1 mbuf */
1824 static inline void
1825 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1826 {
1827         uint64_t dma_addr;
1828
1829         dma_addr = rte_mbuf_data_dma_addr(*pkts);
1830         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1831         txdp->cmd_type_offset_bsz =
1832                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1833                                 (*pkts)->data_len, 0);
1834 }
1835
1836 /* Fill hardware descriptor ring with mbuf data */
1837 static inline void
1838 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1839                      struct rte_mbuf **pkts,
1840                      uint16_t nb_pkts)
1841 {
1842         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1843         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1844         const int N_PER_LOOP = 4;
1845         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1846         int mainpart, leftover;
1847         int i, j;
1848
1849         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1850         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1851         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1852                 for (j = 0; j < N_PER_LOOP; ++j) {
1853                         (txep + i + j)->mbuf = *(pkts + i + j);
1854                 }
1855                 tx4(txdp + i, pkts + i);
1856         }
1857         if (unlikely(leftover > 0)) {
1858                 for (i = 0; i < leftover; ++i) {
1859                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1860                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1861                 }
1862         }
1863 }
1864
1865 static inline uint16_t
1866 tx_xmit_pkts(struct i40e_tx_queue *txq,
1867              struct rte_mbuf **tx_pkts,
1868              uint16_t nb_pkts)
1869 {
1870         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1871         uint16_t n = 0;
1872
1873         /**
1874          * Begin scanning the H/W ring for done descriptors when the number
1875          * of available descriptors drops below tx_free_thresh. For each done
1876          * descriptor, free the associated buffer.
1877          */
1878         if (txq->nb_tx_free < txq->tx_free_thresh)
1879                 i40e_tx_free_bufs(txq);
1880
1881         /* Use available descriptor only */
1882         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1883         if (unlikely(!nb_pkts))
1884                 return 0;
1885
1886         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1887         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1888                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1889                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1890                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1891                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1892                                                 I40E_TXD_QW1_CMD_SHIFT);
1893                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1894                 txq->tx_tail = 0;
1895         }
1896
1897         /* Fill hardware descriptor ring with mbuf data */
1898         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1899         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1900
1901         /* Determin if RS bit needs to be set */
1902         if (txq->tx_tail > txq->tx_next_rs) {
1903                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1904                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1905                                                 I40E_TXD_QW1_CMD_SHIFT);
1906                 txq->tx_next_rs =
1907                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1908                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1909                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1910         }
1911
1912         if (txq->tx_tail >= txq->nb_tx_desc)
1913                 txq->tx_tail = 0;
1914
1915         /* Update the tx tail register */
1916         rte_wmb();
1917         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1918
1919         return nb_pkts;
1920 }
1921
1922 static uint16_t
1923 i40e_xmit_pkts_simple(void *tx_queue,
1924                       struct rte_mbuf **tx_pkts,
1925                       uint16_t nb_pkts)
1926 {
1927         uint16_t nb_tx = 0;
1928
1929         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1930                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1931                                                 tx_pkts, nb_pkts);
1932
1933         while (nb_pkts) {
1934                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1935                                                 I40E_TX_MAX_BURST);
1936
1937                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1938                                                 &tx_pkts[nb_tx], num);
1939                 nb_tx = (uint16_t)(nb_tx + ret);
1940                 nb_pkts = (uint16_t)(nb_pkts - ret);
1941                 if (ret < num)
1942                         break;
1943         }
1944
1945         return nb_tx;
1946 }
1947
1948 /*
1949  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1950  * application used, which assume having sequential ones. But from driver's
1951  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1952  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1953  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1954  * use queue_idx from 0 to 95 to access queues, while real queue would be
1955  * different. This function will do a queue mapping to find VSI the queue
1956  * belongs to.
1957  */
1958 static struct i40e_vsi*
1959 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1960 {
1961         /* the queue in MAIN VSI range */
1962         if (queue_idx < pf->main_vsi->nb_qps)
1963                 return pf->main_vsi;
1964
1965         queue_idx -= pf->main_vsi->nb_qps;
1966
1967         /* queue_idx is greater than VMDQ VSIs range */
1968         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1969                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1970                 return NULL;
1971         }
1972
1973         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1974 }
1975
1976 static uint16_t
1977 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1978 {
1979         /* the queue in MAIN VSI range */
1980         if (queue_idx < pf->main_vsi->nb_qps)
1981                 return queue_idx;
1982
1983         /* It's VMDQ queues */
1984         queue_idx -= pf->main_vsi->nb_qps;
1985
1986         if (pf->nb_cfg_vmdq_vsi)
1987                 return queue_idx % pf->vmdq_nb_qps;
1988         else {
1989                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1990                 return (uint16_t)(-1);
1991         }
1992 }
1993
1994 int
1995 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1996 {
1997         struct i40e_rx_queue *rxq;
1998         int err = -1;
1999         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2000
2001         PMD_INIT_FUNC_TRACE();
2002
2003         if (rx_queue_id < dev->data->nb_rx_queues) {
2004                 rxq = dev->data->rx_queues[rx_queue_id];
2005
2006                 err = i40e_alloc_rx_queue_mbufs(rxq);
2007                 if (err) {
2008                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
2009                         return err;
2010                 }
2011
2012                 rte_wmb();
2013
2014                 /* Init the RX tail regieter. */
2015                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2016
2017                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
2018
2019                 if (err) {
2020                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
2021                                     rx_queue_id);
2022
2023                         i40e_rx_queue_release_mbufs(rxq);
2024                         i40e_reset_rx_queue(rxq);
2025                 } else
2026                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2027         }
2028
2029         return err;
2030 }
2031
2032 int
2033 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2034 {
2035         struct i40e_rx_queue *rxq;
2036         int err;
2037         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2038
2039         if (rx_queue_id < dev->data->nb_rx_queues) {
2040                 rxq = dev->data->rx_queues[rx_queue_id];
2041
2042                 /*
2043                 * rx_queue_id is queue id aplication refers to, while
2044                 * rxq->reg_idx is the real queue index.
2045                 */
2046                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
2047
2048                 if (err) {
2049                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
2050                                     rx_queue_id);
2051                         return err;
2052                 }
2053                 i40e_rx_queue_release_mbufs(rxq);
2054                 i40e_reset_rx_queue(rxq);
2055                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2056         }
2057
2058         return 0;
2059 }
2060
2061 int
2062 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2063 {
2064         int err = -1;
2065         struct i40e_tx_queue *txq;
2066         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2067
2068         PMD_INIT_FUNC_TRACE();
2069
2070         if (tx_queue_id < dev->data->nb_tx_queues) {
2071                 txq = dev->data->tx_queues[tx_queue_id];
2072
2073                 /*
2074                 * tx_queue_id is queue id aplication refers to, while
2075                 * rxq->reg_idx is the real queue index.
2076                 */
2077                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
2078                 if (err)
2079                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
2080                                     tx_queue_id);
2081                 else
2082                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2083         }
2084
2085         return err;
2086 }
2087
2088 int
2089 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2090 {
2091         struct i40e_tx_queue *txq;
2092         int err;
2093         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2094
2095         if (tx_queue_id < dev->data->nb_tx_queues) {
2096                 txq = dev->data->tx_queues[tx_queue_id];
2097
2098                 /*
2099                 * tx_queue_id is queue id aplication refers to, while
2100                 * txq->reg_idx is the real queue index.
2101                 */
2102                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
2103
2104                 if (err) {
2105                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
2106                                     tx_queue_id);
2107                         return err;
2108                 }
2109
2110                 i40e_tx_queue_release_mbufs(txq);
2111                 i40e_reset_tx_queue(txq);
2112                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2113         }
2114
2115         return 0;
2116 }
2117
2118 const uint32_t *
2119 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2120 {
2121         static const uint32_t ptypes[] = {
2122                 /* refers to i40e_rxd_pkt_type_mapping() */
2123                 RTE_PTYPE_L2_ETHER,
2124                 RTE_PTYPE_L2_ETHER_TIMESYNC,
2125                 RTE_PTYPE_L2_ETHER_LLDP,
2126                 RTE_PTYPE_L2_ETHER_ARP,
2127                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2128                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2129                 RTE_PTYPE_L4_FRAG,
2130                 RTE_PTYPE_L4_ICMP,
2131                 RTE_PTYPE_L4_NONFRAG,
2132                 RTE_PTYPE_L4_SCTP,
2133                 RTE_PTYPE_L4_TCP,
2134                 RTE_PTYPE_L4_UDP,
2135                 RTE_PTYPE_TUNNEL_GRENAT,
2136                 RTE_PTYPE_TUNNEL_IP,
2137                 RTE_PTYPE_INNER_L2_ETHER,
2138                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2139                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2140                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2141                 RTE_PTYPE_INNER_L4_FRAG,
2142                 RTE_PTYPE_INNER_L4_ICMP,
2143                 RTE_PTYPE_INNER_L4_NONFRAG,
2144                 RTE_PTYPE_INNER_L4_SCTP,
2145                 RTE_PTYPE_INNER_L4_TCP,
2146                 RTE_PTYPE_INNER_L4_UDP,
2147                 RTE_PTYPE_UNKNOWN
2148         };
2149
2150         if (dev->rx_pkt_burst == i40e_recv_pkts ||
2151 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2152             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
2153 #endif
2154             dev->rx_pkt_burst == i40e_recv_scattered_pkts)
2155                 return ptypes;
2156         return NULL;
2157 }
2158
2159 int
2160 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
2161                         uint16_t queue_idx,
2162                         uint16_t nb_desc,
2163                         unsigned int socket_id,
2164                         const struct rte_eth_rxconf *rx_conf,
2165                         struct rte_mempool *mp)
2166 {
2167         struct i40e_vsi *vsi;
2168         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2169         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2170         struct i40e_adapter *ad =
2171                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2172         struct i40e_rx_queue *rxq;
2173         const struct rte_memzone *rz;
2174         uint32_t ring_size;
2175         uint16_t len, i;
2176         uint16_t base, bsf, tc_mapping;
2177         int use_def_burst_func = 1;
2178
2179         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2180                 struct i40e_vf *vf =
2181                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2182                 vsi = &vf->vsi;
2183         } else
2184                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2185
2186         if (vsi == NULL) {
2187                 PMD_DRV_LOG(ERR, "VSI not available or queue "
2188                             "index exceeds the maximum");
2189                 return I40E_ERR_PARAM;
2190         }
2191         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2192                         (nb_desc > I40E_MAX_RING_DESC) ||
2193                         (nb_desc < I40E_MIN_RING_DESC)) {
2194                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
2195                             "invalid", nb_desc);
2196                 return I40E_ERR_PARAM;
2197         }
2198
2199         /* Free memory if needed */
2200         if (dev->data->rx_queues[queue_idx]) {
2201                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
2202                 dev->data->rx_queues[queue_idx] = NULL;
2203         }
2204
2205         /* Allocate the rx queue data structure */
2206         rxq = rte_zmalloc_socket("i40e rx queue",
2207                                  sizeof(struct i40e_rx_queue),
2208                                  RTE_CACHE_LINE_SIZE,
2209                                  socket_id);
2210         if (!rxq) {
2211                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2212                             "rx queue data structure");
2213                 return -ENOMEM;
2214         }
2215         rxq->mp = mp;
2216         rxq->nb_rx_desc = nb_desc;
2217         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2218         rxq->queue_id = queue_idx;
2219         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2220                 rxq->reg_idx = queue_idx;
2221         else /* PF device */
2222                 rxq->reg_idx = vsi->base_queue +
2223                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2224
2225         rxq->port_id = dev->data->port_id;
2226         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2227                                                         0 : ETHER_CRC_LEN);
2228         rxq->drop_en = rx_conf->rx_drop_en;
2229         rxq->vsi = vsi;
2230         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2231
2232         /* Allocate the maximun number of RX ring hardware descriptor. */
2233         ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
2234         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2235         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2236                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2237         if (!rz) {
2238                 i40e_dev_rx_queue_release(rxq);
2239                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2240                 return -ENOMEM;
2241         }
2242
2243         /* Zero all the descriptors in the ring. */
2244         memset(rz->addr, 0, ring_size);
2245
2246         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2247         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2248
2249 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2250         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2251 #else
2252         len = nb_desc;
2253 #endif
2254
2255         /* Allocate the software ring. */
2256         rxq->sw_ring =
2257                 rte_zmalloc_socket("i40e rx sw ring",
2258                                    sizeof(struct i40e_rx_entry) * len,
2259                                    RTE_CACHE_LINE_SIZE,
2260                                    socket_id);
2261         if (!rxq->sw_ring) {
2262                 i40e_dev_rx_queue_release(rxq);
2263                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2264                 return -ENOMEM;
2265         }
2266
2267         i40e_reset_rx_queue(rxq);
2268         rxq->q_set = TRUE;
2269         dev->data->rx_queues[queue_idx] = rxq;
2270
2271         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2272
2273         if (!use_def_burst_func) {
2274 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2275                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2276                              "satisfied. Rx Burst Bulk Alloc function will be "
2277                              "used on port=%d, queue=%d.",
2278                              rxq->port_id, rxq->queue_id);
2279 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2280         } else {
2281                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2282                              "not satisfied, Scattered Rx is requested, "
2283                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2284                              "not enabled on port=%d, queue=%d.",
2285                              rxq->port_id, rxq->queue_id);
2286                 ad->rx_bulk_alloc_allowed = false;
2287         }
2288
2289         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2290                 if (!(vsi->enabled_tc & (1 << i)))
2291                         continue;
2292                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2293                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2294                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2295                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2296                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2297
2298                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2299                         rxq->dcb_tc = i;
2300         }
2301
2302         return 0;
2303 }
2304
2305 void
2306 i40e_dev_rx_queue_release(void *rxq)
2307 {
2308         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2309
2310         if (!q) {
2311                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2312                 return;
2313         }
2314
2315         i40e_rx_queue_release_mbufs(q);
2316         rte_free(q->sw_ring);
2317         rte_free(q);
2318 }
2319
2320 uint32_t
2321 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2322 {
2323 #define I40E_RXQ_SCAN_INTERVAL 4
2324         volatile union i40e_rx_desc *rxdp;
2325         struct i40e_rx_queue *rxq;
2326         uint16_t desc = 0;
2327
2328         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
2329                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
2330                 return 0;
2331         }
2332
2333         rxq = dev->data->rx_queues[rx_queue_id];
2334         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2335         while ((desc < rxq->nb_rx_desc) &&
2336                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2337                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2338                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2339                 /**
2340                  * Check the DD bit of a rx descriptor of each 4 in a group,
2341                  * to avoid checking too frequently and downgrading performance
2342                  * too much.
2343                  */
2344                 desc += I40E_RXQ_SCAN_INTERVAL;
2345                 rxdp += I40E_RXQ_SCAN_INTERVAL;
2346                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2347                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2348                                         desc - rxq->nb_rx_desc]);
2349         }
2350
2351         return desc;
2352 }
2353
2354 int
2355 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2356 {
2357         volatile union i40e_rx_desc *rxdp;
2358         struct i40e_rx_queue *rxq = rx_queue;
2359         uint16_t desc;
2360         int ret;
2361
2362         if (unlikely(offset >= rxq->nb_rx_desc)) {
2363                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
2364                 return 0;
2365         }
2366
2367         desc = rxq->rx_tail + offset;
2368         if (desc >= rxq->nb_rx_desc)
2369                 desc -= rxq->nb_rx_desc;
2370
2371         rxdp = &(rxq->rx_ring[desc]);
2372
2373         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2374                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2375                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2376
2377         return ret;
2378 }
2379
2380 int
2381 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2382                         uint16_t queue_idx,
2383                         uint16_t nb_desc,
2384                         unsigned int socket_id,
2385                         const struct rte_eth_txconf *tx_conf)
2386 {
2387         struct i40e_vsi *vsi;
2388         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2390         struct i40e_tx_queue *txq;
2391         const struct rte_memzone *tz;
2392         uint32_t ring_size;
2393         uint16_t tx_rs_thresh, tx_free_thresh;
2394         uint16_t i, base, bsf, tc_mapping;
2395
2396         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2397                 struct i40e_vf *vf =
2398                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2399                 vsi = &vf->vsi;
2400         } else
2401                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2402
2403         if (vsi == NULL) {
2404                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2405                             "exceeds the maximum", queue_idx);
2406                 return I40E_ERR_PARAM;
2407         }
2408
2409         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2410                         (nb_desc > I40E_MAX_RING_DESC) ||
2411                         (nb_desc < I40E_MIN_RING_DESC)) {
2412                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2413                             "invalid", nb_desc);
2414                 return I40E_ERR_PARAM;
2415         }
2416
2417         /**
2418          * The following two parameters control the setting of the RS bit on
2419          * transmit descriptors. TX descriptors will have their RS bit set
2420          * after txq->tx_rs_thresh descriptors have been used. The TX
2421          * descriptor ring will be cleaned after txq->tx_free_thresh
2422          * descriptors are used or if the number of descriptors required to
2423          * transmit a packet is greater than the number of free TX descriptors.
2424          *
2425          * The following constraints must be satisfied:
2426          *  - tx_rs_thresh must be greater than 0.
2427          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2428          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2429          *  - tx_rs_thresh must be a divisor of the ring size.
2430          *  - tx_free_thresh must be greater than 0.
2431          *  - tx_free_thresh must be less than the size of the ring minus 3.
2432          *
2433          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2434          * race condition, hence the maximum threshold constraints. When set
2435          * to zero use default values.
2436          */
2437         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2438                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2439         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2440                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2441         if (tx_rs_thresh >= (nb_desc - 2)) {
2442                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2443                              "number of TX descriptors minus 2. "
2444                              "(tx_rs_thresh=%u port=%d queue=%d)",
2445                              (unsigned int)tx_rs_thresh,
2446                              (int)dev->data->port_id,
2447                              (int)queue_idx);
2448                 return I40E_ERR_PARAM;
2449         }
2450         if (tx_free_thresh >= (nb_desc - 3)) {
2451                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2452                              "tx_free_thresh must be less than the "
2453                              "number of TX descriptors minus 3. "
2454                              "(tx_free_thresh=%u port=%d queue=%d)",
2455                              (unsigned int)tx_free_thresh,
2456                              (int)dev->data->port_id,
2457                              (int)queue_idx);
2458                 return I40E_ERR_PARAM;
2459         }
2460         if (tx_rs_thresh > tx_free_thresh) {
2461                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2462                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2463                              " tx_rs_thresh=%u port=%d queue=%d)",
2464                              (unsigned int)tx_free_thresh,
2465                              (unsigned int)tx_rs_thresh,
2466                              (int)dev->data->port_id,
2467                              (int)queue_idx);
2468                 return I40E_ERR_PARAM;
2469         }
2470         if ((nb_desc % tx_rs_thresh) != 0) {
2471                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2472                              "number of TX descriptors. (tx_rs_thresh=%u"
2473                              " port=%d queue=%d)",
2474                              (unsigned int)tx_rs_thresh,
2475                              (int)dev->data->port_id,
2476                              (int)queue_idx);
2477                 return I40E_ERR_PARAM;
2478         }
2479         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2480                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2481                              "tx_rs_thresh is greater than 1. "
2482                              "(tx_rs_thresh=%u port=%d queue=%d)",
2483                              (unsigned int)tx_rs_thresh,
2484                              (int)dev->data->port_id,
2485                              (int)queue_idx);
2486                 return I40E_ERR_PARAM;
2487         }
2488
2489         /* Free memory if needed. */
2490         if (dev->data->tx_queues[queue_idx]) {
2491                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2492                 dev->data->tx_queues[queue_idx] = NULL;
2493         }
2494
2495         /* Allocate the TX queue data structure. */
2496         txq = rte_zmalloc_socket("i40e tx queue",
2497                                   sizeof(struct i40e_tx_queue),
2498                                   RTE_CACHE_LINE_SIZE,
2499                                   socket_id);
2500         if (!txq) {
2501                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2502                             "tx queue structure");
2503                 return -ENOMEM;
2504         }
2505
2506         /* Allocate TX hardware ring descriptors. */
2507         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2508         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2509         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2510                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2511         if (!tz) {
2512                 i40e_dev_tx_queue_release(txq);
2513                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2514                 return -ENOMEM;
2515         }
2516
2517         txq->nb_tx_desc = nb_desc;
2518         txq->tx_rs_thresh = tx_rs_thresh;
2519         txq->tx_free_thresh = tx_free_thresh;
2520         txq->pthresh = tx_conf->tx_thresh.pthresh;
2521         txq->hthresh = tx_conf->tx_thresh.hthresh;
2522         txq->wthresh = tx_conf->tx_thresh.wthresh;
2523         txq->queue_id = queue_idx;
2524         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2525                 txq->reg_idx = queue_idx;
2526         else /* PF device */
2527                 txq->reg_idx = vsi->base_queue +
2528                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2529
2530         txq->port_id = dev->data->port_id;
2531         txq->txq_flags = tx_conf->txq_flags;
2532         txq->vsi = vsi;
2533         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2534
2535         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2536         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2537
2538         /* Allocate software ring */
2539         txq->sw_ring =
2540                 rte_zmalloc_socket("i40e tx sw ring",
2541                                    sizeof(struct i40e_tx_entry) * nb_desc,
2542                                    RTE_CACHE_LINE_SIZE,
2543                                    socket_id);
2544         if (!txq->sw_ring) {
2545                 i40e_dev_tx_queue_release(txq);
2546                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2547                 return -ENOMEM;
2548         }
2549
2550         i40e_reset_tx_queue(txq);
2551         txq->q_set = TRUE;
2552         dev->data->tx_queues[queue_idx] = txq;
2553
2554         /* Use a simple TX queue without offloads or multi segs if possible */
2555         i40e_set_tx_function_flag(dev, txq);
2556
2557         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2558                 if (!(vsi->enabled_tc & (1 << i)))
2559                         continue;
2560                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2561                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2562                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2563                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2564                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2565
2566                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2567                         txq->dcb_tc = i;
2568         }
2569
2570         return 0;
2571 }
2572
2573 void
2574 i40e_dev_tx_queue_release(void *txq)
2575 {
2576         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2577
2578         if (!q) {
2579                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2580                 return;
2581         }
2582
2583         i40e_tx_queue_release_mbufs(q);
2584         rte_free(q->sw_ring);
2585         rte_free(q);
2586 }
2587
2588 const struct rte_memzone *
2589 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2590 {
2591         const struct rte_memzone *mz;
2592
2593         mz = rte_memzone_lookup(name);
2594         if (mz)
2595                 return mz;
2596
2597         if (rte_xen_dom0_supported())
2598                 mz = rte_memzone_reserve_bounded(name, len,
2599                                 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2600         else
2601                 mz = rte_memzone_reserve_aligned(name, len,
2602                                 socket_id, 0, I40E_RING_BASE_ALIGN);
2603         return mz;
2604 }
2605
2606 void
2607 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2608 {
2609         uint16_t i;
2610
2611         /* SSE Vector driver has a different way of releasing mbufs. */
2612         if (rxq->rx_using_sse) {
2613                 i40e_rx_queue_release_mbufs_vec(rxq);
2614                 return;
2615         }
2616
2617         if (!rxq || !rxq->sw_ring) {
2618                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2619                 return;
2620         }
2621
2622         for (i = 0; i < rxq->nb_rx_desc; i++) {
2623                 if (rxq->sw_ring[i].mbuf) {
2624                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2625                         rxq->sw_ring[i].mbuf = NULL;
2626                 }
2627         }
2628 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2629         if (rxq->rx_nb_avail == 0)
2630                 return;
2631         for (i = 0; i < rxq->rx_nb_avail; i++) {
2632                 struct rte_mbuf *mbuf;
2633
2634                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2635                 rte_pktmbuf_free_seg(mbuf);
2636         }
2637         rxq->rx_nb_avail = 0;
2638 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2639 }
2640
2641 void
2642 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2643 {
2644         unsigned i;
2645         uint16_t len;
2646
2647         if (!rxq) {
2648                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2649                 return;
2650         }
2651
2652 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2653         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2654                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2655         else
2656 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2657                 len = rxq->nb_rx_desc;
2658
2659         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2660                 ((volatile char *)rxq->rx_ring)[i] = 0;
2661
2662 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2663         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2664         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2665                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2666
2667         rxq->rx_nb_avail = 0;
2668         rxq->rx_next_avail = 0;
2669         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2670 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2671         rxq->rx_tail = 0;
2672         rxq->nb_rx_hold = 0;
2673         rxq->pkt_first_seg = NULL;
2674         rxq->pkt_last_seg = NULL;
2675
2676         rxq->rxrearm_start = 0;
2677         rxq->rxrearm_nb = 0;
2678 }
2679
2680 void
2681 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2682 {
2683         uint16_t i;
2684
2685         if (!txq || !txq->sw_ring) {
2686                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2687                 return;
2688         }
2689
2690         for (i = 0; i < txq->nb_tx_desc; i++) {
2691                 if (txq->sw_ring[i].mbuf) {
2692                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2693                         txq->sw_ring[i].mbuf = NULL;
2694                 }
2695         }
2696 }
2697
2698 void
2699 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2700 {
2701         struct i40e_tx_entry *txe;
2702         uint16_t i, prev, size;
2703
2704         if (!txq) {
2705                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2706                 return;
2707         }
2708
2709         txe = txq->sw_ring;
2710         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2711         for (i = 0; i < size; i++)
2712                 ((volatile char *)txq->tx_ring)[i] = 0;
2713
2714         prev = (uint16_t)(txq->nb_tx_desc - 1);
2715         for (i = 0; i < txq->nb_tx_desc; i++) {
2716                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2717
2718                 txd->cmd_type_offset_bsz =
2719                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2720                 txe[i].mbuf =  NULL;
2721                 txe[i].last_id = i;
2722                 txe[prev].next_id = i;
2723                 prev = i;
2724         }
2725
2726         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2727         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2728
2729         txq->tx_tail = 0;
2730         txq->nb_tx_used = 0;
2731
2732         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2733         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2734 }
2735
2736 /* Init the TX queue in hardware */
2737 int
2738 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2739 {
2740         enum i40e_status_code err = I40E_SUCCESS;
2741         struct i40e_vsi *vsi = txq->vsi;
2742         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2743         uint16_t pf_q = txq->reg_idx;
2744         struct i40e_hmc_obj_txq tx_ctx;
2745         uint32_t qtx_ctl;
2746
2747         /* clear the context structure first */
2748         memset(&tx_ctx, 0, sizeof(tx_ctx));
2749         tx_ctx.new_context = 1;
2750         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2751         tx_ctx.qlen = txq->nb_tx_desc;
2752
2753 #ifdef RTE_LIBRTE_IEEE1588
2754         tx_ctx.timesync_ena = 1;
2755 #endif
2756         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2757         if (vsi->type == I40E_VSI_FDIR)
2758                 tx_ctx.fd_ena = TRUE;
2759
2760         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2761         if (err != I40E_SUCCESS) {
2762                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2763                 return err;
2764         }
2765
2766         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2767         if (err != I40E_SUCCESS) {
2768                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2769                 return err;
2770         }
2771
2772         /* Now associate this queue with this PCI function */
2773         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2774         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2775                                         I40E_QTX_CTL_PF_INDX_MASK);
2776         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2777         I40E_WRITE_FLUSH(hw);
2778
2779         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2780
2781         return err;
2782 }
2783
2784 int
2785 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2786 {
2787         struct i40e_rx_entry *rxe = rxq->sw_ring;
2788         uint64_t dma_addr;
2789         uint16_t i;
2790
2791         for (i = 0; i < rxq->nb_rx_desc; i++) {
2792                 volatile union i40e_rx_desc *rxd;
2793                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2794
2795                 if (unlikely(!mbuf)) {
2796                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2797                         return -ENOMEM;
2798                 }
2799
2800                 rte_mbuf_refcnt_set(mbuf, 1);
2801                 mbuf->next = NULL;
2802                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2803                 mbuf->nb_segs = 1;
2804                 mbuf->port = rxq->port_id;
2805
2806                 dma_addr =
2807                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2808
2809                 rxd = &rxq->rx_ring[i];
2810                 rxd->read.pkt_addr = dma_addr;
2811                 rxd->read.hdr_addr = 0;
2812 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2813                 rxd->read.rsvd1 = 0;
2814                 rxd->read.rsvd2 = 0;
2815 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2816
2817                 rxe[i].mbuf = mbuf;
2818         }
2819
2820         return 0;
2821 }
2822
2823 /*
2824  * Calculate the buffer length, and check the jumbo frame
2825  * and maximum packet length.
2826  */
2827 static int
2828 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2829 {
2830         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2831         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2832         struct rte_eth_dev_data *data = pf->dev_data;
2833         uint16_t buf_size, len;
2834
2835         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2836                 RTE_PKTMBUF_HEADROOM);
2837
2838         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2839                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2840         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2841                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2842                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2843                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2844                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2845                 rxq->hs_mode = i40e_header_split_enabled;
2846                 break;
2847         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2848         default:
2849                 rxq->rx_hdr_len = 0;
2850                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2851                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2852                 rxq->hs_mode = i40e_header_split_none;
2853                 break;
2854         }
2855
2856         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2857         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2858         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2859                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2860                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2861                         PMD_DRV_LOG(ERR, "maximum packet length must "
2862                                     "be larger than %u and smaller than %u,"
2863                                     "as jumbo frame is enabled",
2864                                     (uint32_t)ETHER_MAX_LEN,
2865                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2866                         return I40E_ERR_CONFIG;
2867                 }
2868         } else {
2869                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2870                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2871                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2872                                     "larger than %u and smaller than %u, "
2873                                     "as jumbo frame is disabled",
2874                                     (uint32_t)ETHER_MIN_LEN,
2875                                     (uint32_t)ETHER_MAX_LEN);
2876                         return I40E_ERR_CONFIG;
2877                 }
2878         }
2879
2880         return 0;
2881 }
2882
2883 /* Init the RX queue in hardware */
2884 int
2885 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2886 {
2887         int err = I40E_SUCCESS;
2888         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2889         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2890         uint16_t pf_q = rxq->reg_idx;
2891         uint16_t buf_size;
2892         struct i40e_hmc_obj_rxq rx_ctx;
2893
2894         err = i40e_rx_queue_config(rxq);
2895         if (err < 0) {
2896                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2897                 return err;
2898         }
2899
2900         /* Clear the context structure first */
2901         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2902         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2903         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2904
2905         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2906         rx_ctx.qlen = rxq->nb_rx_desc;
2907 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2908         rx_ctx.dsize = 1;
2909 #endif
2910         rx_ctx.dtype = rxq->hs_mode;
2911         if (rxq->hs_mode)
2912                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2913         else
2914                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2915         rx_ctx.rxmax = rxq->max_pkt_len;
2916         rx_ctx.tphrdesc_ena = 1;
2917         rx_ctx.tphwdesc_ena = 1;
2918         rx_ctx.tphdata_ena = 1;
2919         rx_ctx.tphhead_ena = 1;
2920         rx_ctx.lrxqthresh = 2;
2921         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2922         rx_ctx.l2tsel = 1;
2923         /* showiv indicates if inner VLAN is stripped inside of tunnel
2924          * packet. When set it to 1, vlan information is stripped from
2925          * the inner header, but the hardware does not put it in the
2926          * descriptor. So set it zero by default.
2927          */
2928         rx_ctx.showiv = 0;
2929         rx_ctx.prefena = 1;
2930
2931         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2932         if (err != I40E_SUCCESS) {
2933                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2934                 return err;
2935         }
2936         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2937         if (err != I40E_SUCCESS) {
2938                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2939                 return err;
2940         }
2941
2942         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2943
2944         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2945                 RTE_PKTMBUF_HEADROOM);
2946
2947         /* Check if scattered RX needs to be used. */
2948         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2949                 dev_data->scattered_rx = 1;
2950         }
2951
2952         /* Init the RX tail regieter. */
2953         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2954
2955         return 0;
2956 }
2957
2958 void
2959 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2960 {
2961         uint16_t i;
2962
2963         PMD_INIT_FUNC_TRACE();
2964
2965         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2966                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2967                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2968         }
2969
2970         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2971                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2972                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2973         }
2974 }
2975
2976 void
2977 i40e_dev_free_queues(struct rte_eth_dev *dev)
2978 {
2979         uint16_t i;
2980
2981         PMD_INIT_FUNC_TRACE();
2982
2983         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2984                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2985                 dev->data->rx_queues[i] = NULL;
2986         }
2987         dev->data->nb_rx_queues = 0;
2988
2989         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2990                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2991                 dev->data->tx_queues[i] = NULL;
2992         }
2993         dev->data->nb_tx_queues = 0;
2994 }
2995
2996 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2997 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2998
2999 enum i40e_status_code
3000 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
3001 {
3002         struct i40e_tx_queue *txq;
3003         const struct rte_memzone *tz = NULL;
3004         uint32_t ring_size;
3005         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3006
3007         if (!pf) {
3008                 PMD_DRV_LOG(ERR, "PF is not available");
3009                 return I40E_ERR_BAD_PTR;
3010         }
3011
3012         /* Allocate the TX queue data structure. */
3013         txq = rte_zmalloc_socket("i40e fdir tx queue",
3014                                   sizeof(struct i40e_tx_queue),
3015                                   RTE_CACHE_LINE_SIZE,
3016                                   SOCKET_ID_ANY);
3017         if (!txq) {
3018                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3019                                         "tx queue structure.");
3020                 return I40E_ERR_NO_MEMORY;
3021         }
3022
3023         /* Allocate TX hardware ring descriptors. */
3024         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
3025         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3026
3027         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
3028                                       I40E_FDIR_QUEUE_ID, ring_size,
3029                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3030         if (!tz) {
3031                 i40e_dev_tx_queue_release(txq);
3032                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
3033                 return I40E_ERR_NO_MEMORY;
3034         }
3035
3036         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
3037         txq->queue_id = I40E_FDIR_QUEUE_ID;
3038         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3039         txq->vsi = pf->fdir.fdir_vsi;
3040
3041         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
3042         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
3043         /*
3044          * don't need to allocate software ring and reset for the fdir
3045          * program queue just set the queue has been configured.
3046          */
3047         txq->q_set = TRUE;
3048         pf->fdir.txq = txq;
3049
3050         return I40E_SUCCESS;
3051 }
3052
3053 enum i40e_status_code
3054 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3055 {
3056         struct i40e_rx_queue *rxq;
3057         const struct rte_memzone *rz = NULL;
3058         uint32_t ring_size;
3059         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3060
3061         if (!pf) {
3062                 PMD_DRV_LOG(ERR, "PF is not available");
3063                 return I40E_ERR_BAD_PTR;
3064         }
3065
3066         /* Allocate the RX queue data structure. */
3067         rxq = rte_zmalloc_socket("i40e fdir rx queue",
3068                                   sizeof(struct i40e_rx_queue),
3069                                   RTE_CACHE_LINE_SIZE,
3070                                   SOCKET_ID_ANY);
3071         if (!rxq) {
3072                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3073                                         "rx queue structure.");
3074                 return I40E_ERR_NO_MEMORY;
3075         }
3076
3077         /* Allocate RX hardware ring descriptors. */
3078         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3079         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3080
3081         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3082                                       I40E_FDIR_QUEUE_ID, ring_size,
3083                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3084         if (!rz) {
3085                 i40e_dev_rx_queue_release(rxq);
3086                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3087                 return I40E_ERR_NO_MEMORY;
3088         }
3089
3090         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3091         rxq->queue_id = I40E_FDIR_QUEUE_ID;
3092         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3093         rxq->vsi = pf->fdir.fdir_vsi;
3094
3095         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
3096         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3097
3098         /*
3099          * Don't need to allocate software ring and reset for the fdir
3100          * rx queue, just set the queue has been configured.
3101          */
3102         rxq->q_set = TRUE;
3103         pf->fdir.rxq = rxq;
3104
3105         return I40E_SUCCESS;
3106 }
3107
3108 void
3109 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3110         struct rte_eth_rxq_info *qinfo)
3111 {
3112         struct i40e_rx_queue *rxq;
3113
3114         rxq = dev->data->rx_queues[queue_id];
3115
3116         qinfo->mp = rxq->mp;
3117         qinfo->scattered_rx = dev->data->scattered_rx;
3118         qinfo->nb_desc = rxq->nb_rx_desc;
3119
3120         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3121         qinfo->conf.rx_drop_en = rxq->drop_en;
3122         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3123 }
3124
3125 void
3126 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3127         struct rte_eth_txq_info *qinfo)
3128 {
3129         struct i40e_tx_queue *txq;
3130
3131         txq = dev->data->tx_queues[queue_id];
3132
3133         qinfo->nb_desc = txq->nb_tx_desc;
3134
3135         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3136         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3137         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3138
3139         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3140         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3141         qinfo->conf.txq_flags = txq->txq_flags;
3142         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3143 }
3144
3145 void __attribute__((cold))
3146 i40e_set_rx_function(struct rte_eth_dev *dev)
3147 {
3148         struct i40e_adapter *ad =
3149                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3150         uint16_t rx_using_sse, i;
3151         /* In order to allow Vector Rx there are a few configuration
3152          * conditions to be met and Rx Bulk Allocation should be allowed.
3153          */
3154         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3155                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3156                     !ad->rx_bulk_alloc_allowed) {
3157                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3158                                      " Vector Rx preconditions",
3159                                      dev->data->port_id);
3160
3161                         ad->rx_vec_allowed = false;
3162                 }
3163                 if (ad->rx_vec_allowed) {
3164                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3165                                 struct i40e_rx_queue *rxq =
3166                                         dev->data->rx_queues[i];
3167
3168                                 if (i40e_rxq_vec_setup(rxq)) {
3169                                         ad->rx_vec_allowed = false;
3170                                         break;
3171                                 }
3172                         }
3173                 }
3174         }
3175
3176         if (dev->data->scattered_rx) {
3177                 /* Set the non-LRO scattered callback: there are Vector and
3178                  * single allocation versions.
3179                  */
3180                 if (ad->rx_vec_allowed) {
3181                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
3182                                             "callback (port=%d).",
3183                                      dev->data->port_id);
3184
3185                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3186                 } else {
3187                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
3188                                            "allocation callback (port=%d).",
3189                                      dev->data->port_id);
3190                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
3191                 }
3192         /* If parameters allow we are going to choose between the following
3193          * callbacks:
3194          *    - Vector
3195          *    - Bulk Allocation
3196          *    - Single buffer allocation (the simplest one)
3197          */
3198         } else if (ad->rx_vec_allowed) {
3199                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
3200                                     "burst size no less than %d (port=%d).",
3201                              RTE_I40E_DESCS_PER_LOOP,
3202                              dev->data->port_id);
3203
3204                 dev->rx_pkt_burst = i40e_recv_pkts_vec;
3205         } else if (ad->rx_bulk_alloc_allowed) {
3206                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3207                                     "satisfied. Rx Burst Bulk Alloc function "
3208                                     "will be used on port=%d.",
3209                              dev->data->port_id);
3210
3211                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3212         } else {
3213                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
3214                                     "satisfied, or Scattered Rx is requested "
3215                                     "(port=%d).",
3216                              dev->data->port_id);
3217
3218                 dev->rx_pkt_burst = i40e_recv_pkts;
3219         }
3220
3221         /* Propagate information about RX function choice through all queues. */
3222         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3223                 rx_using_sse =
3224                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3225                          dev->rx_pkt_burst == i40e_recv_pkts_vec);
3226
3227                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3228                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3229
3230                         rxq->rx_using_sse = rx_using_sse;
3231                 }
3232         }
3233 }
3234
3235 void __attribute__((cold))
3236 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3237 {
3238         struct i40e_adapter *ad =
3239                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3240
3241         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
3242         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
3243                         && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
3244                 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
3245                         PMD_INIT_LOG(DEBUG, "Vector tx"
3246                                      " can be enabled on this txq.");
3247
3248                 } else {
3249                         ad->tx_vec_allowed = false;
3250                 }
3251         } else {
3252                 ad->tx_simple_allowed = false;
3253         }
3254 }
3255
3256 void __attribute__((cold))
3257 i40e_set_tx_function(struct rte_eth_dev *dev)
3258 {
3259         struct i40e_adapter *ad =
3260                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3261         int i;
3262
3263         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3264                 if (ad->tx_vec_allowed) {
3265                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3266                                 struct i40e_tx_queue *txq =
3267                                         dev->data->tx_queues[i];
3268
3269                                 if (i40e_txq_vec_setup(txq)) {
3270                                         ad->tx_vec_allowed = false;
3271                                         break;
3272                                 }
3273                         }
3274                 }
3275         }
3276
3277         if (ad->tx_simple_allowed) {
3278                 if (ad->tx_vec_allowed) {
3279                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3280                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3281                 } else {
3282                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3283                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3284                 }
3285         } else {
3286                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3287                 dev->tx_pkt_burst = i40e_xmit_pkts;
3288         }
3289 }
3290
3291 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
3292 int __attribute__((weak))
3293 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3294 {
3295         return -1;
3296 }
3297
3298 uint16_t __attribute__((weak))
3299 i40e_recv_pkts_vec(
3300         void __rte_unused *rx_queue,
3301         struct rte_mbuf __rte_unused **rx_pkts,
3302         uint16_t __rte_unused nb_pkts)
3303 {
3304         return 0;
3305 }
3306
3307 uint16_t __attribute__((weak))
3308 i40e_recv_scattered_pkts_vec(
3309         void __rte_unused *rx_queue,
3310         struct rte_mbuf __rte_unused **rx_pkts,
3311         uint16_t __rte_unused nb_pkts)
3312 {
3313         return 0;
3314 }
3315
3316 int __attribute__((weak))
3317 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3318 {
3319         return -1;
3320 }
3321
3322 int __attribute__((weak))
3323 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3324 {
3325         return -1;
3326 }
3327
3328 void __attribute__((weak))
3329 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3330 {
3331         return;
3332 }
3333
3334 uint16_t __attribute__((weak))
3335 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
3336                    struct rte_mbuf __rte_unused **tx_pkts,
3337                    uint16_t __rte_unused nb_pkts)
3338 {
3339         return 0;
3340 }