drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53 #include <rte_ip.h>
  54 #include <rte_net.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_type.h"
  59 #include "i40e_ethdev.h"
  60 #include "i40e_rxtx.h"
  61
  62 #define DEFAULT_TX_RS_THRESH   32
  63 #define DEFAULT_TX_FREE_THRESH 32
  64 #define I40E_MAX_PKT_TYPE      256
  65
  66 #define I40E_TX_MAX_BURST  32
  67
  68 #define I40E_DMA_MEM_ALIGN 4096
  69
  70 /* Base address of the HW descriptor ring should be 128B aligned. */
  71 #define I40E_RING_BASE_ALIGN    128
  72
  73 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  74                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  75
  76 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  77
  78 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  79                 PKT_TX_IP_CKSUM |                \
  80                 PKT_TX_L4_MASK |                 \
  81                 PKT_TX_TCP_SEG |                 \
  82                 PKT_TX_OUTER_IP_CKSUM)
  83
  84 #define I40E_TX_OFFLOAD_MASK (  \
  85                 PKT_TX_IP_CKSUM |       \
  86                 PKT_TX_L4_MASK |        \
  87                 PKT_TX_OUTER_IP_CKSUM | \
  88                 PKT_TX_TCP_SEG |        \
  89                 PKT_TX_QINQ_PKT |       \
  90                 PKT_TX_VLAN_PKT)
  91
  92 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
  93                 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
  94
  95 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  96                                       struct rte_mbuf **tx_pkts,
  97                                       uint16_t nb_pkts);
  98
  99 static inline void
 100 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
 101 {
 102         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 103                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 104                 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
 105                 mb->vlan_tci =
 106                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 107                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
 108                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
 109         } else {
 110                 mb->vlan_tci = 0;
 111         }
 112 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 113         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 114                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 115                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
 116                 mb->vlan_tci_outer = mb->vlan_tci;
 117                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 118                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 119                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 120                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 121         } else {
 122                 mb->vlan_tci_outer = 0;
 123         }
 124 #endif
 125         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 126                    mb->vlan_tci, mb->vlan_tci_outer);
 127 }
 128
 129 /* Translate the rx descriptor status to pkt flags */
 130 static inline uint64_t
 131 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 132 {
 133         uint64_t flags;
 134
 135         /* Check if RSS_HASH */
 136         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 137                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 138                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 139
 140         /* Check if FDIR Match */
 141         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 142                                                         PKT_RX_FDIR : 0);
 143
 144         return flags;
 145 }
 146
 147 static inline uint64_t
 148 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 149 {
 150         uint64_t flags = 0;
 151         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 152
 153 #define I40E_RX_ERR_BITS 0x3f
 154         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 155                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 156                 return flags;
 157         }
 158
 159         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 160                 flags |= PKT_RX_IP_CKSUM_BAD;
 161         else
 162                 flags |= PKT_RX_IP_CKSUM_GOOD;
 163
 164         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 165                 flags |= PKT_RX_L4_CKSUM_BAD;
 166         else
 167                 flags |= PKT_RX_L4_CKSUM_GOOD;
 168
 169         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 170                 flags |= PKT_RX_EIP_CKSUM_BAD;
 171
 172         return flags;
 173 }
 174
 175 /* Function to check and set the ieee1588 timesync index and get the
 176  * appropriate flags.
 177  */
 178 #ifdef RTE_LIBRTE_IEEE1588
 179 static inline uint64_t
 180 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 181 {
 182         uint64_t pkt_flags = 0;
 183         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 184                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 185                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 186
 187         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 188                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 189                 pkt_flags = PKT_RX_IEEE1588_PTP;
 190         if (tsyn & 0x04) {
 191                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 192                 mb->timesync = tsyn & 0x03;
 193         }
 194
 195         return pkt_flags;
 196 }
 197 #endif
 198
 199 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 200 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 201 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 202 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 203 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 204
 205 static inline uint64_t
 206 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 207 {
 208         uint64_t flags = 0;
 209 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 210         uint16_t flexbh, flexbl;
 211
 212         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 213                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 214                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 215         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 216                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 217                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 218
 219
 220         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 221                 mb->hash.fdir.hi =
 222                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 223                 flags |= PKT_RX_FDIR_ID;
 224         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 225                 mb->hash.fdir.hi =
 226                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 227                 flags |= PKT_RX_FDIR_FLX;
 228         }
 229         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 230                 mb->hash.fdir.lo =
 231                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 232                 flags |= PKT_RX_FDIR_FLX;
 233         }
 234 #else
 235         mb->hash.fdir.hi =
 236                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 237         flags |= PKT_RX_FDIR_ID;
 238 #endif
 239         return flags;
 240 }
 241
 242 static inline void
 243 i40e_parse_tunneling_params(uint64_t ol_flags,
 244                             union i40e_tx_offload tx_offload,
 245                             uint32_t *cd_tunneling)
 246 {
 247         /* EIPT: External (outer) IP header type */
 248         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 249                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 250         else if (ol_flags & PKT_TX_OUTER_IPV4)
 251                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 252         else if (ol_flags & PKT_TX_OUTER_IPV6)
 253                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 254
 255         /* EIPLEN: External (outer) IP header length, in DWords */
 256         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 257                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 258
 259         /* L4TUNT: L4 Tunneling Type */
 260         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 261         case PKT_TX_TUNNEL_IPIP:
 262                 /* for non UDP / GRE tunneling, set to 00b */
 263                 break;
 264         case PKT_TX_TUNNEL_VXLAN:
 265         case PKT_TX_TUNNEL_GENEVE:
 266                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 267                 break;
 268         case PKT_TX_TUNNEL_GRE:
 269                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 270                 break;
 271         default:
 272                 PMD_TX_LOG(ERR, "Tunnel type not supported");
 273                 return;
 274         }
 275
 276         /* L4TUNLEN: L4 Tunneling Length, in Words
 277          *
 278          * We depend on app to set rte_mbuf.l2_len correctly.
 279          * For IP in GRE it should be set to the length of the GRE
 280          * header;
 281          * for MAC in GRE or MAC in UDP it should be set to the length
 282          * of the GRE or UDP headers plus the inner MAC up to including
 283          * its last Ethertype.
 284          */
 285         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 286                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 287 }
 288
 289 static inline void
 290 i40e_txd_enable_checksum(uint64_t ol_flags,
 291                         uint32_t *td_cmd,
 292                         uint32_t *td_offset,
 293                         union i40e_tx_offload tx_offload)
 294 {
 295         /* Set MACLEN */
 296         if (ol_flags & PKT_TX_TUNNEL_MASK)
 297                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 298                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 299         else
 300                 *td_offset |= (tx_offload.l2_len >> 1)
 301                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 302
 303         /* Enable L3 checksum offloads */
 304         if (ol_flags & PKT_TX_IP_CKSUM) {
 305                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 306                 *td_offset |= (tx_offload.l3_len >> 2)
 307                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 308         } else if (ol_flags & PKT_TX_IPV4) {
 309                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 310                 *td_offset |= (tx_offload.l3_len >> 2)
 311                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 312         } else if (ol_flags & PKT_TX_IPV6) {
 313                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 314                 *td_offset |= (tx_offload.l3_len >> 2)
 315                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 316         }
 317
 318         if (ol_flags & PKT_TX_TCP_SEG) {
 319                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 320                 *td_offset |= (tx_offload.l4_len >> 2)
 321                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 322                 return;
 323         }
 324
 325         /* Enable L4 checksum offloads */
 326         switch (ol_flags & PKT_TX_L4_MASK) {
 327         case PKT_TX_TCP_CKSUM:
 328                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 329                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 330                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 331                 break;
 332         case PKT_TX_SCTP_CKSUM:
 333                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 334                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 335                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 336                 break;
 337         case PKT_TX_UDP_CKSUM:
 338                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 339                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 340                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 341                 break;
 342         default:
 343                 break;
 344         }
 345 }
 346
 347 /* Construct the tx flags */
 348 static inline uint64_t
 349 i40e_build_ctob(uint32_t td_cmd,
 350                 uint32_t td_offset,
 351                 unsigned int size,
 352                 uint32_t td_tag)
 353 {
 354         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 355                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 356                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 357                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 358                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 359 }
 360
 361 static inline int
 362 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 363 {
 364         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 365         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 366         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 367         uint16_t nb_tx_desc = txq->nb_tx_desc;
 368         uint16_t desc_to_clean_to;
 369         uint16_t nb_tx_to_clean;
 370
 371         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 372         if (desc_to_clean_to >= nb_tx_desc)
 373                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 374
 375         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 376         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 377                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 378                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 379                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 380                         "(port=%d queue=%d)", desc_to_clean_to,
 381                                 txq->port_id, txq->queue_id);
 382                 return -1;
 383         }
 384
 385         if (last_desc_cleaned > desc_to_clean_to)
 386                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 387                                                         desc_to_clean_to);
 388         else
 389                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 390                                         last_desc_cleaned);
 391
 392         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 393
 394         txq->last_desc_cleaned = desc_to_clean_to;
 395         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 396
 397         return 0;
 398 }
 399
 400 static inline int
 401 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 402 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 403 #else
 404 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 405 #endif
 406 {
 407         int ret = 0;
 408
 409 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 410         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 411                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 412                              "rxq->rx_free_thresh=%d, "
 413                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 414                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 415                 ret = -EINVAL;
 416         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 417                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 418                              "rxq->rx_free_thresh=%d, "
 419                              "rxq->nb_rx_desc=%d",
 420                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 421                 ret = -EINVAL;
 422         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 423                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 424                              "rxq->nb_rx_desc=%d, "
 425                              "rxq->rx_free_thresh=%d",
 426                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 427                 ret = -EINVAL;
 428         }
 429 #else
 430         ret = -EINVAL;
 431 #endif
 432
 433         return ret;
 434 }
 435
 436 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 437 #define I40E_LOOK_AHEAD 8
 438 #if (I40E_LOOK_AHEAD != 8)
 439 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 440 #endif
 441 static inline int
 442 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 443 {
 444         volatile union i40e_rx_desc *rxdp;
 445         struct i40e_rx_entry *rxep;
 446         struct rte_mbuf *mb;
 447         uint16_t pkt_len;
 448         uint64_t qword1;
 449         uint32_t rx_status;
 450         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 451         int32_t i, j, nb_rx = 0;
 452         uint64_t pkt_flags;
 453
 454         rxdp = &rxq->rx_ring[rxq->rx_tail];
 455         rxep = &rxq->sw_ring[rxq->rx_tail];
 456
 457         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 458         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 459                                 I40E_RXD_QW1_STATUS_SHIFT;
 460
 461         /* Make sure there is at least 1 packet to receive */
 462         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 463                 return 0;
 464
 465         /**
 466          * Scan LOOK_AHEAD descriptors at a time to determine which
 467          * descriptors reference packets that are ready to be received.
 468          */
 469         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 470                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 471                 /* Read desc statuses backwards to avoid race condition */
 472                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 473                         qword1 = rte_le_to_cpu_64(\
 474                                 rxdp[j].wb.qword1.status_error_len);
 475                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 476                                         I40E_RXD_QW1_STATUS_SHIFT;
 477                 }
 478
 479                 rte_smp_rmb();
 480
 481                 /* Compute how many status bits were set */
 482                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 483                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 484
 485                 nb_rx += nb_dd;
 486
 487                 /* Translate descriptor info to mbuf parameters */
 488                 for (j = 0; j < nb_dd; j++) {
 489                         mb = rxep[j].mbuf;
 490                         qword1 = rte_le_to_cpu_64(\
 491                                 rxdp[j].wb.qword1.status_error_len);
 492                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 493                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 494                         mb->data_len = pkt_len;
 495                         mb->pkt_len = pkt_len;
 496                         mb->ol_flags = 0;
 497                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 498                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 499                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 500                         mb->packet_type =
 501                                 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
 502                                                 I40E_RXD_QW1_PTYPE_MASK) >>
 503                                                 I40E_RXD_QW1_PTYPE_SHIFT));
 504                         if (pkt_flags & PKT_RX_RSS_HASH)
 505                                 mb->hash.rss = rte_le_to_cpu_32(\
 506                                         rxdp[j].wb.qword0.hi_dword.rss);
 507                         if (pkt_flags & PKT_RX_FDIR)
 508                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 509
 510 #ifdef RTE_LIBRTE_IEEE1588
 511                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 512 #endif
 513                         mb->ol_flags |= pkt_flags;
 514
 515                 }
 516
 517                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 518                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 519
 520                 if (nb_dd != I40E_LOOK_AHEAD)
 521                         break;
 522         }
 523
 524         /* Clear software ring entries */
 525         for (i = 0; i < nb_rx; i++)
 526                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 527
 528         return nb_rx;
 529 }
 530
 531 static inline uint16_t
 532 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 533                         struct rte_mbuf **rx_pkts,
 534                         uint16_t nb_pkts)
 535 {
 536         uint16_t i;
 537         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 538
 539         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 540
 541         for (i = 0; i < nb_pkts; i++)
 542                 rx_pkts[i] = stage[i];
 543
 544         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 545         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 546
 547         return nb_pkts;
 548 }
 549
 550 static inline int
 551 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 552 {
 553         volatile union i40e_rx_desc *rxdp;
 554         struct i40e_rx_entry *rxep;
 555         struct rte_mbuf *mb;
 556         uint16_t alloc_idx, i;
 557         uint64_t dma_addr;
 558         int diag;
 559
 560         /* Allocate buffers in bulk */
 561         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 562                                 (rxq->rx_free_thresh - 1));
 563         rxep = &(rxq->sw_ring[alloc_idx]);
 564         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 565                                         rxq->rx_free_thresh);
 566         if (unlikely(diag != 0)) {
 567                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 568                 return -ENOMEM;
 569         }
 570
 571         rxdp = &rxq->rx_ring[alloc_idx];
 572         for (i = 0; i < rxq->rx_free_thresh; i++) {
 573                 if (likely(i < (rxq->rx_free_thresh - 1)))
 574                         /* Prefetch next mbuf */
 575                         rte_prefetch0(rxep[i + 1].mbuf);
 576
 577                 mb = rxep[i].mbuf;
 578                 rte_mbuf_refcnt_set(mb, 1);
 579                 mb->next = NULL;
 580                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 581                 mb->nb_segs = 1;
 582                 mb->port = rxq->port_id;
 583                 dma_addr = rte_cpu_to_le_64(\
 584                         rte_mbuf_data_dma_addr_default(mb));
 585                 rxdp[i].read.hdr_addr = 0;
 586                 rxdp[i].read.pkt_addr = dma_addr;
 587         }
 588
 589         /* Update rx tail regsiter */
 590         rte_wmb();
 591         I40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
 592
 593         rxq->rx_free_trigger =
 594                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 595         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 596                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 597
 598         return 0;
 599 }
 600
 601 static inline uint16_t
 602 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 603 {
 604         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 605         uint16_t nb_rx = 0;
 606
 607         if (!nb_pkts)
 608                 return 0;
 609
 610         if (rxq->rx_nb_avail)
 611                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 612
 613         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 614         rxq->rx_next_avail = 0;
 615         rxq->rx_nb_avail = nb_rx;
 616         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 617
 618         if (rxq->rx_tail > rxq->rx_free_trigger) {
 619                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 620                         uint16_t i, j;
 621
 622                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
 623                                    "port_id=%u, queue_id=%u",
 624                                    rxq->port_id, rxq->queue_id);
 625                         rxq->rx_nb_avail = 0;
 626                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 627                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 628                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 629
 630                         return 0;
 631                 }
 632         }
 633
 634         if (rxq->rx_tail >= rxq->nb_rx_desc)
 635                 rxq->rx_tail = 0;
 636
 637         if (rxq->rx_nb_avail)
 638                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 639
 640         return 0;
 641 }
 642
 643 static uint16_t
 644 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 645                           struct rte_mbuf **rx_pkts,
 646                           uint16_t nb_pkts)
 647 {
 648         uint16_t nb_rx = 0, n, count;
 649
 650         if (unlikely(nb_pkts == 0))
 651                 return 0;
 652
 653         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 654                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 655
 656         while (nb_pkts) {
 657                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 658                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 659                 nb_rx = (uint16_t)(nb_rx + count);
 660                 nb_pkts = (uint16_t)(nb_pkts - count);
 661                 if (count < n)
 662                         break;
 663         }
 664
 665         return nb_rx;
 666 }
 667 #else
 668 static uint16_t
 669 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 670                           struct rte_mbuf __rte_unused **rx_pkts,
 671                           uint16_t __rte_unused nb_pkts)
 672 {
 673         return 0;
 674 }
 675 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 676
 677 uint16_t
 678 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 679 {
 680         struct i40e_rx_queue *rxq;
 681         volatile union i40e_rx_desc *rx_ring;
 682         volatile union i40e_rx_desc *rxdp;
 683         union i40e_rx_desc rxd;
 684         struct i40e_rx_entry *sw_ring;
 685         struct i40e_rx_entry *rxe;
 686         struct rte_mbuf *rxm;
 687         struct rte_mbuf *nmb;
 688         uint16_t nb_rx;
 689         uint32_t rx_status;
 690         uint64_t qword1;
 691         uint16_t rx_packet_len;
 692         uint16_t rx_id, nb_hold;
 693         uint64_t dma_addr;
 694         uint64_t pkt_flags;
 695
 696         nb_rx = 0;
 697         nb_hold = 0;
 698         rxq = rx_queue;
 699         rx_id = rxq->rx_tail;
 700         rx_ring = rxq->rx_ring;
 701         sw_ring = rxq->sw_ring;
 702
 703         while (nb_rx < nb_pkts) {
 704                 rxdp = &rx_ring[rx_id];
 705                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 706                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 707                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 708
 709                 /* Check the DD bit first */
 710                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 711                         break;
 712
 713                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 714                 if (unlikely(!nmb))
 715                         break;
 716                 rxd = *rxdp;
 717
 718                 nb_hold++;
 719                 rxe = &sw_ring[rx_id];
 720                 rx_id++;
 721                 if (unlikely(rx_id == rxq->nb_rx_desc))
 722                         rx_id = 0;
 723
 724                 /* Prefetch next mbuf */
 725                 rte_prefetch0(sw_ring[rx_id].mbuf);
 726
 727                 /**
 728                  * When next RX descriptor is on a cache line boundary,
 729                  * prefetch the next 4 RX descriptors and next 8 pointers
 730                  * to mbufs.
 731                  */
 732                 if ((rx_id & 0x3) == 0) {
 733                         rte_prefetch0(&rx_ring[rx_id]);
 734                         rte_prefetch0(&sw_ring[rx_id]);
 735                 }
 736                 rxm = rxe->mbuf;
 737                 rxe->mbuf = nmb;
 738                 dma_addr =
 739                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
 740                 rxdp->read.hdr_addr = 0;
 741                 rxdp->read.pkt_addr = dma_addr;
 742
 743                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 744                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 745
 746                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 747                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 748                 rxm->nb_segs = 1;
 749                 rxm->next = NULL;
 750                 rxm->pkt_len = rx_packet_len;
 751                 rxm->data_len = rx_packet_len;
 752                 rxm->port = rxq->port_id;
 753                 rxm->ol_flags = 0;
 754                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 755                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 756                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 757                 rxm->packet_type =
 758                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
 759                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
 760                 if (pkt_flags & PKT_RX_RSS_HASH)
 761                         rxm->hash.rss =
 762                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 763                 if (pkt_flags & PKT_RX_FDIR)
 764                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 765
 766 #ifdef RTE_LIBRTE_IEEE1588
 767                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 768 #endif
 769                 rxm->ol_flags |= pkt_flags;
 770
 771                 rx_pkts[nb_rx++] = rxm;
 772         }
 773         rxq->rx_tail = rx_id;
 774
 775         /**
 776          * If the number of free RX descriptors is greater than the RX free
 777          * threshold of the queue, advance the receive tail register of queue.
 778          * Update that register with the value of the last processed RX
 779          * descriptor minus 1.
 780          */
 781         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 782         if (nb_hold > rxq->rx_free_thresh) {
 783                 rx_id = (uint16_t) ((rx_id == 0) ?
 784                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 785                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 786                 nb_hold = 0;
 787         }
 788         rxq->nb_rx_hold = nb_hold;
 789
 790         return nb_rx;
 791 }
 792
 793 uint16_t
 794 i40e_recv_scattered_pkts(void *rx_queue,
 795                          struct rte_mbuf **rx_pkts,
 796                          uint16_t nb_pkts)
 797 {
 798         struct i40e_rx_queue *rxq = rx_queue;
 799         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 800         volatile union i40e_rx_desc *rxdp;
 801         union i40e_rx_desc rxd;
 802         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 803         struct i40e_rx_entry *rxe;
 804         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 805         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 806         struct rte_mbuf *nmb, *rxm;
 807         uint16_t rx_id = rxq->rx_tail;
 808         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 809         uint32_t rx_status;
 810         uint64_t qword1;
 811         uint64_t dma_addr;
 812         uint64_t pkt_flags;
 813
 814         while (nb_rx < nb_pkts) {
 815                 rxdp = &rx_ring[rx_id];
 816                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 817                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 818                                         I40E_RXD_QW1_STATUS_SHIFT;
 819
 820                 /* Check the DD bit */
 821                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 822                         break;
 823
 824                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 825                 if (unlikely(!nmb))
 826                         break;
 827                 rxd = *rxdp;
 828                 nb_hold++;
 829                 rxe = &sw_ring[rx_id];
 830                 rx_id++;
 831                 if (rx_id == rxq->nb_rx_desc)
 832                         rx_id = 0;
 833
 834                 /* Prefetch next mbuf */
 835                 rte_prefetch0(sw_ring[rx_id].mbuf);
 836
 837                 /**
 838                  * When next RX descriptor is on a cache line boundary,
 839                  * prefetch the next 4 RX descriptors and next 8 pointers
 840                  * to mbufs.
 841                  */
 842                 if ((rx_id & 0x3) == 0) {
 843                         rte_prefetch0(&rx_ring[rx_id]);
 844                         rte_prefetch0(&sw_ring[rx_id]);
 845                 }
 846
 847                 rxm = rxe->mbuf;
 848                 rxe->mbuf = nmb;
 849                 dma_addr =
 850                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
 851
 852                 /* Set data buffer address and data length of the mbuf */
 853                 rxdp->read.hdr_addr = 0;
 854                 rxdp->read.pkt_addr = dma_addr;
 855                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 856                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 857                 rxm->data_len = rx_packet_len;
 858                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 859
 860                 /**
 861                  * If this is the first buffer of the received packet, set the
 862                  * pointer to the first mbuf of the packet and initialize its
 863                  * context. Otherwise, update the total length and the number
 864                  * of segments of the current scattered packet, and update the
 865                  * pointer to the last mbuf of the current packet.
 866                  */
 867                 if (!first_seg) {
 868                         first_seg = rxm;
 869                         first_seg->nb_segs = 1;
 870                         first_seg->pkt_len = rx_packet_len;
 871                 } else {
 872                         first_seg->pkt_len =
 873                                 (uint16_t)(first_seg->pkt_len +
 874                                                 rx_packet_len);
 875                         first_seg->nb_segs++;
 876                         last_seg->next = rxm;
 877                 }
 878
 879                 /**
 880                  * If this is not the last buffer of the received packet,
 881                  * update the pointer to the last mbuf of the current scattered
 882                  * packet and continue to parse the RX ring.
 883                  */
 884                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 885                         last_seg = rxm;
 886                         continue;
 887                 }
 888
 889                 /**
 890                  * This is the last buffer of the received packet. If the CRC
 891                  * is not stripped by the hardware:
 892                  *  - Subtract the CRC length from the total packet length.
 893                  *  - If the last buffer only contains the whole CRC or a part
 894                  *  of it, free the mbuf associated to the last buffer. If part
 895                  *  of the CRC is also contained in the previous mbuf, subtract
 896                  *  the length of that CRC part from the data length of the
 897                  *  previous mbuf.
 898                  */
 899                 rxm->next = NULL;
 900                 if (unlikely(rxq->crc_len > 0)) {
 901                         first_seg->pkt_len -= ETHER_CRC_LEN;
 902                         if (rx_packet_len <= ETHER_CRC_LEN) {
 903                                 rte_pktmbuf_free_seg(rxm);
 904                                 first_seg->nb_segs--;
 905                                 last_seg->data_len =
 906                                         (uint16_t)(last_seg->data_len -
 907                                         (ETHER_CRC_LEN - rx_packet_len));
 908                                 last_seg->next = NULL;
 909                         } else
 910                                 rxm->data_len = (uint16_t)(rx_packet_len -
 911                                                                 ETHER_CRC_LEN);
 912                 }
 913
 914                 first_seg->port = rxq->port_id;
 915                 first_seg->ol_flags = 0;
 916                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 917                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 918                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 919                 first_seg->packet_type =
 920                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
 921                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
 922                 if (pkt_flags & PKT_RX_RSS_HASH)
 923                         first_seg->hash.rss =
 924                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 925                 if (pkt_flags & PKT_RX_FDIR)
 926                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 927
 928 #ifdef RTE_LIBRTE_IEEE1588
 929                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 930 #endif
 931                 first_seg->ol_flags |= pkt_flags;
 932
 933                 /* Prefetch data of first segment, if configured to do so. */
 934                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 935                         first_seg->data_off));
 936                 rx_pkts[nb_rx++] = first_seg;
 937                 first_seg = NULL;
 938         }
 939
 940         /* Record index of the next RX descriptor to probe. */
 941         rxq->rx_tail = rx_id;
 942         rxq->pkt_first_seg = first_seg;
 943         rxq->pkt_last_seg = last_seg;
 944
 945         /**
 946          * If the number of free RX descriptors is greater than the RX free
 947          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 948          * register. Update the RDT with the value of the last processed RX
 949          * descriptor minus 1, to guarantee that the RDT register is never
 950          * equal to the RDH register, which creates a "full" ring situtation
 951          * from the hardware point of view.
 952          */
 953         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 954         if (nb_hold > rxq->rx_free_thresh) {
 955                 rx_id = (uint16_t)(rx_id == 0 ?
 956                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 957                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 958                 nb_hold = 0;
 959         }
 960         rxq->nb_rx_hold = nb_hold;
 961
 962         return nb_rx;
 963 }
 964
 965 /* Check if the context descriptor is needed for TX offloading */
 966 static inline uint16_t
 967 i40e_calc_context_desc(uint64_t flags)
 968 {
 969         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
 970                 PKT_TX_TCP_SEG |
 971                 PKT_TX_QINQ_PKT |
 972                 PKT_TX_TUNNEL_MASK;
 973
 974 #ifdef RTE_LIBRTE_IEEE1588
 975         mask |= PKT_TX_IEEE1588_TMST;
 976 #endif
 977
 978         return (flags & mask) ? 1 : 0;
 979 }
 980
 981 /* set i40e TSO context descriptor */
 982 static inline uint64_t
 983 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
 984 {
 985         uint64_t ctx_desc = 0;
 986         uint32_t cd_cmd, hdr_len, cd_tso_len;
 987
 988         if (!tx_offload.l4_len) {
 989                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
 990                 return ctx_desc;
 991         }
 992
 993         /**
 994          * in case of non tunneling packet, the outer_l2_len and
 995          * outer_l3_len must be 0.
 996          */
 997         hdr_len = tx_offload.outer_l2_len +
 998                 tx_offload.outer_l3_len +
 999                 tx_offload.l2_len +
1000                 tx_offload.l3_len +
1001                 tx_offload.l4_len;
1002
1003         cd_cmd = I40E_TX_CTX_DESC_TSO;
1004         cd_tso_len = mbuf->pkt_len - hdr_len;
1005         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1006                 ((uint64_t)cd_tso_len <<
1007                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1008                 ((uint64_t)mbuf->tso_segsz <<
1009                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1010
1011         return ctx_desc;
1012 }
1013
1014 uint16_t
1015 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1016 {
1017         struct i40e_tx_queue *txq;
1018         struct i40e_tx_entry *sw_ring;
1019         struct i40e_tx_entry *txe, *txn;
1020         volatile struct i40e_tx_desc *txd;
1021         volatile struct i40e_tx_desc *txr;
1022         struct rte_mbuf *tx_pkt;
1023         struct rte_mbuf *m_seg;
1024         uint32_t cd_tunneling_params;
1025         uint16_t tx_id;
1026         uint16_t nb_tx;
1027         uint32_t td_cmd;
1028         uint32_t td_offset;
1029         uint32_t tx_flags;
1030         uint32_t td_tag;
1031         uint64_t ol_flags;
1032         uint16_t nb_used;
1033         uint16_t nb_ctx;
1034         uint16_t tx_last;
1035         uint16_t slen;
1036         uint64_t buf_dma_addr;
1037         union i40e_tx_offload tx_offload = {0};
1038
1039         txq = tx_queue;
1040         sw_ring = txq->sw_ring;
1041         txr = txq->tx_ring;
1042         tx_id = txq->tx_tail;
1043         txe = &sw_ring[tx_id];
1044
1045         /* Check if the descriptor ring needs to be cleaned. */
1046         if (txq->nb_tx_free < txq->tx_free_thresh)
1047                 i40e_xmit_cleanup(txq);
1048
1049         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1050                 td_cmd = 0;
1051                 td_tag = 0;
1052                 td_offset = 0;
1053                 tx_flags = 0;
1054
1055                 tx_pkt = *tx_pkts++;
1056                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1057
1058                 ol_flags = tx_pkt->ol_flags;
1059                 tx_offload.l2_len = tx_pkt->l2_len;
1060                 tx_offload.l3_len = tx_pkt->l3_len;
1061                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1062                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1063                 tx_offload.l4_len = tx_pkt->l4_len;
1064                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1065
1066                 /* Calculate the number of context descriptors needed. */
1067                 nb_ctx = i40e_calc_context_desc(ol_flags);
1068
1069                 /**
1070                  * The number of descriptors that must be allocated for
1071                  * a packet equals to the number of the segments of that
1072                  * packet plus 1 context descriptor if needed.
1073                  */
1074                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1075                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1076
1077                 /* Circular ring */
1078                 if (tx_last >= txq->nb_tx_desc)
1079                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1080
1081                 if (nb_used > txq->nb_tx_free) {
1082                         if (i40e_xmit_cleanup(txq) != 0) {
1083                                 if (nb_tx == 0)
1084                                         return 0;
1085                                 goto end_of_tx;
1086                         }
1087                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1088                                 while (nb_used > txq->nb_tx_free) {
1089                                         if (i40e_xmit_cleanup(txq) != 0) {
1090                                                 if (nb_tx == 0)
1091                                                         return 0;
1092                                                 goto end_of_tx;
1093                                         }
1094                                 }
1095                         }
1096                 }
1097
1098                 /* Descriptor based VLAN insertion */
1099                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1100                         tx_flags |= tx_pkt->vlan_tci <<
1101                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1102                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1103                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1104                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1105                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1106                 }
1107
1108                 /* Always enable CRC offload insertion */
1109                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1110
1111                 /* Fill in tunneling parameters if necessary */
1112                 cd_tunneling_params = 0;
1113                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1114                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1115                                                     &cd_tunneling_params);
1116                 /* Enable checksum offloading */
1117                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1118                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1119                                                  &td_offset, tx_offload);
1120
1121                 if (nb_ctx) {
1122                         /* Setup TX context descriptor if required */
1123                         volatile struct i40e_tx_context_desc *ctx_txd =
1124                                 (volatile struct i40e_tx_context_desc *)\
1125                                                         &txr[tx_id];
1126                         uint16_t cd_l2tag2 = 0;
1127                         uint64_t cd_type_cmd_tso_mss =
1128                                 I40E_TX_DESC_DTYPE_CONTEXT;
1129
1130                         txn = &sw_ring[txe->next_id];
1131                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1132                         if (txe->mbuf != NULL) {
1133                                 rte_pktmbuf_free_seg(txe->mbuf);
1134                                 txe->mbuf = NULL;
1135                         }
1136
1137                         /* TSO enabled means no timestamp */
1138                         if (ol_flags & PKT_TX_TCP_SEG)
1139                                 cd_type_cmd_tso_mss |=
1140                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1141                         else {
1142 #ifdef RTE_LIBRTE_IEEE1588
1143                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1144                                         cd_type_cmd_tso_mss |=
1145                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1146                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1147 #endif
1148                         }
1149
1150                         ctx_txd->tunneling_params =
1151                                 rte_cpu_to_le_32(cd_tunneling_params);
1152                         if (ol_flags & PKT_TX_QINQ_PKT) {
1153                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1154                                 cd_type_cmd_tso_mss |=
1155                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1156                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1157                         }
1158                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1159                         ctx_txd->type_cmd_tso_mss =
1160                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1161
1162                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1163                                 "tunneling_params: %#x;\n"
1164                                 "l2tag2: %#hx;\n"
1165                                 "rsvd: %#hx;\n"
1166                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1167                                 tx_pkt, tx_id,
1168                                 ctx_txd->tunneling_params,
1169                                 ctx_txd->l2tag2,
1170                                 ctx_txd->rsvd,
1171                                 ctx_txd->type_cmd_tso_mss);
1172
1173                         txe->last_id = tx_last;
1174                         tx_id = txe->next_id;
1175                         txe = txn;
1176                 }
1177
1178                 m_seg = tx_pkt;
1179                 do {
1180                         txd = &txr[tx_id];
1181                         txn = &sw_ring[txe->next_id];
1182
1183                         if (txe->mbuf)
1184                                 rte_pktmbuf_free_seg(txe->mbuf);
1185                         txe->mbuf = m_seg;
1186
1187                         /* Setup TX Descriptor */
1188                         slen = m_seg->data_len;
1189                         buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1190
1191                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1192                                 "buf_dma_addr: %#"PRIx64";\n"
1193                                 "td_cmd: %#x;\n"
1194                                 "td_offset: %#x;\n"
1195                                 "td_len: %u;\n"
1196                                 "td_tag: %#x;\n",
1197                                 tx_pkt, tx_id, buf_dma_addr,
1198                                 td_cmd, td_offset, slen, td_tag);
1199
1200                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1201                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1202                                                 td_offset, slen, td_tag);
1203                         txe->last_id = tx_last;
1204                         tx_id = txe->next_id;
1205                         txe = txn;
1206                         m_seg = m_seg->next;
1207                 } while (m_seg != NULL);
1208
1209                 /* The last packet data descriptor needs End Of Packet (EOP) */
1210                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1211                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1212                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1213
1214                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1215                         PMD_TX_FREE_LOG(DEBUG,
1216                                         "Setting RS bit on TXD id="
1217                                         "%4u (port=%d queue=%d)",
1218                                         tx_last, txq->port_id, txq->queue_id);
1219
1220                         td_cmd |= I40E_TX_DESC_CMD_RS;
1221
1222                         /* Update txq RS bit counters */
1223                         txq->nb_tx_used = 0;
1224                 }
1225
1226                 txd->cmd_type_offset_bsz |=
1227                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1228                                         I40E_TXD_QW1_CMD_SHIFT);
1229         }
1230
1231 end_of_tx:
1232         rte_wmb();
1233
1234         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1235                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1236                    (unsigned) tx_id, (unsigned) nb_tx);
1237
1238         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1239         txq->tx_tail = tx_id;
1240
1241         return nb_tx;
1242 }
1243
1244 static inline int __attribute__((always_inline))
1245 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1246 {
1247         struct i40e_tx_entry *txep;
1248         uint16_t i;
1249
1250         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1251                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1252                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1253                 return 0;
1254
1255         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1256
1257         for (i = 0; i < txq->tx_rs_thresh; i++)
1258                 rte_prefetch0((txep + i)->mbuf);
1259
1260         if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1261                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1262                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1263                         txep->mbuf = NULL;
1264                 }
1265         } else {
1266                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1267                         rte_pktmbuf_free_seg(txep->mbuf);
1268                         txep->mbuf = NULL;
1269                 }
1270         }
1271
1272         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1273         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1274         if (txq->tx_next_dd >= txq->nb_tx_desc)
1275                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1276
1277         return txq->tx_rs_thresh;
1278 }
1279
1280 /* Populate 4 descriptors with data from 4 mbufs */
1281 static inline void
1282 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1283 {
1284         uint64_t dma_addr;
1285         uint32_t i;
1286
1287         for (i = 0; i < 4; i++, txdp++, pkts++) {
1288                 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1289                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1290                 txdp->cmd_type_offset_bsz =
1291                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1292                                         (*pkts)->data_len, 0);
1293         }
1294 }
1295
1296 /* Populate 1 descriptor with data from 1 mbuf */
1297 static inline void
1298 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1299 {
1300         uint64_t dma_addr;
1301
1302         dma_addr = rte_mbuf_data_dma_addr(*pkts);
1303         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1304         txdp->cmd_type_offset_bsz =
1305                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1306                                 (*pkts)->data_len, 0);
1307 }
1308
1309 /* Fill hardware descriptor ring with mbuf data */
1310 static inline void
1311 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1312                      struct rte_mbuf **pkts,
1313                      uint16_t nb_pkts)
1314 {
1315         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1316         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1317         const int N_PER_LOOP = 4;
1318         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1319         int mainpart, leftover;
1320         int i, j;
1321
1322         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1323         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1324         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1325                 for (j = 0; j < N_PER_LOOP; ++j) {
1326                         (txep + i + j)->mbuf = *(pkts + i + j);
1327                 }
1328                 tx4(txdp + i, pkts + i);
1329         }
1330         if (unlikely(leftover > 0)) {
1331                 for (i = 0; i < leftover; ++i) {
1332                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1333                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1334                 }
1335         }
1336 }
1337
1338 static inline uint16_t
1339 tx_xmit_pkts(struct i40e_tx_queue *txq,
1340              struct rte_mbuf **tx_pkts,
1341              uint16_t nb_pkts)
1342 {
1343         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1344         uint16_t n = 0;
1345
1346         /**
1347          * Begin scanning the H/W ring for done descriptors when the number
1348          * of available descriptors drops below tx_free_thresh. For each done
1349          * descriptor, free the associated buffer.
1350          */
1351         if (txq->nb_tx_free < txq->tx_free_thresh)
1352                 i40e_tx_free_bufs(txq);
1353
1354         /* Use available descriptor only */
1355         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1356         if (unlikely(!nb_pkts))
1357                 return 0;
1358
1359         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1360         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1361                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1362                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1363                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1364                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1365                                                 I40E_TXD_QW1_CMD_SHIFT);
1366                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1367                 txq->tx_tail = 0;
1368         }
1369
1370         /* Fill hardware descriptor ring with mbuf data */
1371         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1372         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1373
1374         /* Determin if RS bit needs to be set */
1375         if (txq->tx_tail > txq->tx_next_rs) {
1376                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1377                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1378                                                 I40E_TXD_QW1_CMD_SHIFT);
1379                 txq->tx_next_rs =
1380                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1381                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1382                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1383         }
1384
1385         if (txq->tx_tail >= txq->nb_tx_desc)
1386                 txq->tx_tail = 0;
1387
1388         /* Update the tx tail register */
1389         rte_wmb();
1390         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, txq->tx_tail);
1391
1392         return nb_pkts;
1393 }
1394
1395 static uint16_t
1396 i40e_xmit_pkts_simple(void *tx_queue,
1397                       struct rte_mbuf **tx_pkts,
1398                       uint16_t nb_pkts)
1399 {
1400         uint16_t nb_tx = 0;
1401
1402         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1403                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1404                                                 tx_pkts, nb_pkts);
1405
1406         while (nb_pkts) {
1407                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1408                                                 I40E_TX_MAX_BURST);
1409
1410                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1411                                                 &tx_pkts[nb_tx], num);
1412                 nb_tx = (uint16_t)(nb_tx + ret);
1413                 nb_pkts = (uint16_t)(nb_pkts - ret);
1414                 if (ret < num)
1415                         break;
1416         }
1417
1418         return nb_tx;
1419 }
1420
1421 /*********************************************************************
1422  *
1423  *  TX prep functions
1424  *
1425  **********************************************************************/
1426 uint16_t
1427 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1428                 uint16_t nb_pkts)
1429 {
1430         int i, ret;
1431         uint64_t ol_flags;
1432         struct rte_mbuf *m;
1433
1434         for (i = 0; i < nb_pkts; i++) {
1435                 m = tx_pkts[i];
1436                 ol_flags = m->ol_flags;
1437
1438                 /**
1439                  * m->nb_segs is uint8_t, so nb_segs is always less than
1440                  * I40E_TX_MAX_SEG.
1441                  * We check only a condition for nb_segs > I40E_TX_MAX_MTU_SEG.
1442                  */
1443                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1444                         if (m->nb_segs > I40E_TX_MAX_MTU_SEG) {
1445                                 rte_errno = -EINVAL;
1446                                 return i;
1447                         }
1448                 } else if ((m->tso_segsz < I40E_MIN_TSO_MSS) ||
1449                                 (m->tso_segsz > I40E_MAX_TSO_MSS)) {
1450                         /* MSS outside the range (256B - 9674B) are considered
1451                          * malicious
1452                          */
1453                         rte_errno = -EINVAL;
1454                         return i;
1455                 }
1456
1457                 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1458                         rte_errno = -ENOTSUP;
1459                         return i;
1460                 }
1461
1462 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1463                 ret = rte_validate_tx_offload(m);
1464                 if (ret != 0) {
1465                         rte_errno = ret;
1466                         return i;
1467                 }
1468 #endif
1469                 ret = rte_net_intel_cksum_prepare(m);
1470                 if (ret != 0) {
1471                         rte_errno = ret;
1472                         return i;
1473                 }
1474         }
1475         return i;
1476 }
1477
1478 /*
1479  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1480  * application used, which assume having sequential ones. But from driver's
1481  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1482  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1483  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1484  * use queue_idx from 0 to 95 to access queues, while real queue would be
1485  * different. This function will do a queue mapping to find VSI the queue
1486  * belongs to.
1487  */
1488 static struct i40e_vsi*
1489 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1490 {
1491         /* the queue in MAIN VSI range */
1492         if (queue_idx < pf->main_vsi->nb_qps)
1493                 return pf->main_vsi;
1494
1495         queue_idx -= pf->main_vsi->nb_qps;
1496
1497         /* queue_idx is greater than VMDQ VSIs range */
1498         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1499                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1500                 return NULL;
1501         }
1502
1503         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1504 }
1505
1506 static uint16_t
1507 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1508 {
1509         /* the queue in MAIN VSI range */
1510         if (queue_idx < pf->main_vsi->nb_qps)
1511                 return queue_idx;
1512
1513         /* It's VMDQ queues */
1514         queue_idx -= pf->main_vsi->nb_qps;
1515
1516         if (pf->nb_cfg_vmdq_vsi)
1517                 return queue_idx % pf->vmdq_nb_qps;
1518         else {
1519                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1520                 return (uint16_t)(-1);
1521         }
1522 }
1523
1524 int
1525 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1526 {
1527         struct i40e_rx_queue *rxq;
1528         int err = -1;
1529         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1530
1531         PMD_INIT_FUNC_TRACE();
1532
1533         if (rx_queue_id < dev->data->nb_rx_queues) {
1534                 rxq = dev->data->rx_queues[rx_queue_id];
1535
1536                 err = i40e_alloc_rx_queue_mbufs(rxq);
1537                 if (err) {
1538                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1539                         return err;
1540                 }
1541
1542                 rte_wmb();
1543
1544                 /* Init the RX tail regieter. */
1545                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1546
1547                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1548
1549                 if (err) {
1550                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1551                                     rx_queue_id);
1552
1553                         i40e_rx_queue_release_mbufs(rxq);
1554                         i40e_reset_rx_queue(rxq);
1555                 } else
1556                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1557         }
1558
1559         return err;
1560 }
1561
1562 int
1563 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1564 {
1565         struct i40e_rx_queue *rxq;
1566         int err;
1567         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1568
1569         if (rx_queue_id < dev->data->nb_rx_queues) {
1570                 rxq = dev->data->rx_queues[rx_queue_id];
1571
1572                 /*
1573                 * rx_queue_id is queue id aplication refers to, while
1574                 * rxq->reg_idx is the real queue index.
1575                 */
1576                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1577
1578                 if (err) {
1579                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1580                                     rx_queue_id);
1581                         return err;
1582                 }
1583                 i40e_rx_queue_release_mbufs(rxq);
1584                 i40e_reset_rx_queue(rxq);
1585                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1586         }
1587
1588         return 0;
1589 }
1590
1591 int
1592 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1593 {
1594         int err = -1;
1595         struct i40e_tx_queue *txq;
1596         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1597
1598         PMD_INIT_FUNC_TRACE();
1599
1600         if (tx_queue_id < dev->data->nb_tx_queues) {
1601                 txq = dev->data->tx_queues[tx_queue_id];
1602
1603                 /*
1604                 * tx_queue_id is queue id aplication refers to, while
1605                 * rxq->reg_idx is the real queue index.
1606                 */
1607                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1608                 if (err)
1609                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1610                                     tx_queue_id);
1611                 else
1612                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1613         }
1614
1615         return err;
1616 }
1617
1618 int
1619 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1620 {
1621         struct i40e_tx_queue *txq;
1622         int err;
1623         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1624
1625         if (tx_queue_id < dev->data->nb_tx_queues) {
1626                 txq = dev->data->tx_queues[tx_queue_id];
1627
1628                 /*
1629                 * tx_queue_id is queue id aplication refers to, while
1630                 * txq->reg_idx is the real queue index.
1631                 */
1632                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1633
1634                 if (err) {
1635                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1636                                     tx_queue_id);
1637                         return err;
1638                 }
1639
1640                 i40e_tx_queue_release_mbufs(txq);
1641                 i40e_reset_tx_queue(txq);
1642                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1643         }
1644
1645         return 0;
1646 }
1647
1648 const uint32_t *
1649 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1650 {
1651         static const uint32_t ptypes[] = {
1652                 /* refers to i40e_rxd_pkt_type_mapping() */
1653                 RTE_PTYPE_L2_ETHER,
1654                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1655                 RTE_PTYPE_L2_ETHER_LLDP,
1656                 RTE_PTYPE_L2_ETHER_ARP,
1657                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1658                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1659                 RTE_PTYPE_L4_FRAG,
1660                 RTE_PTYPE_L4_ICMP,
1661                 RTE_PTYPE_L4_NONFRAG,
1662                 RTE_PTYPE_L4_SCTP,
1663                 RTE_PTYPE_L4_TCP,
1664                 RTE_PTYPE_L4_UDP,
1665                 RTE_PTYPE_TUNNEL_GRENAT,
1666                 RTE_PTYPE_TUNNEL_IP,
1667                 RTE_PTYPE_INNER_L2_ETHER,
1668                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1669                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1670                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1671                 RTE_PTYPE_INNER_L4_FRAG,
1672                 RTE_PTYPE_INNER_L4_ICMP,
1673                 RTE_PTYPE_INNER_L4_NONFRAG,
1674                 RTE_PTYPE_INNER_L4_SCTP,
1675                 RTE_PTYPE_INNER_L4_TCP,
1676                 RTE_PTYPE_INNER_L4_UDP,
1677                 RTE_PTYPE_UNKNOWN
1678         };
1679
1680         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1681 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1682             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1683 #endif
1684             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1685             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1686             dev->rx_pkt_burst == i40e_recv_pkts_vec)
1687                 return ptypes;
1688         return NULL;
1689 }
1690
1691 int
1692 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1693                         uint16_t queue_idx,
1694                         uint16_t nb_desc,
1695                         unsigned int socket_id,
1696                         const struct rte_eth_rxconf *rx_conf,
1697                         struct rte_mempool *mp)
1698 {
1699         struct i40e_vsi *vsi;
1700         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1701         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1702         struct i40e_adapter *ad =
1703                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1704         struct i40e_rx_queue *rxq;
1705         const struct rte_memzone *rz;
1706         uint32_t ring_size;
1707         uint16_t len, i;
1708         uint16_t base, bsf, tc_mapping;
1709         int use_def_burst_func = 1;
1710
1711         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1712                 struct i40e_vf *vf =
1713                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1714                 vsi = &vf->vsi;
1715         } else
1716                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1717
1718         if (vsi == NULL) {
1719                 PMD_DRV_LOG(ERR, "VSI not available or queue "
1720                             "index exceeds the maximum");
1721                 return I40E_ERR_PARAM;
1722         }
1723         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1724                         (nb_desc > I40E_MAX_RING_DESC) ||
1725                         (nb_desc < I40E_MIN_RING_DESC)) {
1726                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1727                             "invalid", nb_desc);
1728                 return I40E_ERR_PARAM;
1729         }
1730
1731         /* Free memory if needed */
1732         if (dev->data->rx_queues[queue_idx]) {
1733                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1734                 dev->data->rx_queues[queue_idx] = NULL;
1735         }
1736
1737         /* Allocate the rx queue data structure */
1738         rxq = rte_zmalloc_socket("i40e rx queue",
1739                                  sizeof(struct i40e_rx_queue),
1740                                  RTE_CACHE_LINE_SIZE,
1741                                  socket_id);
1742         if (!rxq) {
1743                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1744                             "rx queue data structure");
1745                 return -ENOMEM;
1746         }
1747         rxq->mp = mp;
1748         rxq->nb_rx_desc = nb_desc;
1749         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1750         rxq->queue_id = queue_idx;
1751         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
1752                 rxq->reg_idx = queue_idx;
1753         else /* PF device */
1754                 rxq->reg_idx = vsi->base_queue +
1755                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
1756
1757         rxq->port_id = dev->data->port_id;
1758         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1759                                                         0 : ETHER_CRC_LEN);
1760         rxq->drop_en = rx_conf->rx_drop_en;
1761         rxq->vsi = vsi;
1762         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1763
1764         /* Allocate the maximun number of RX ring hardware descriptor. */
1765         len = I40E_MAX_RING_DESC;
1766
1767 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1768         /**
1769          * Allocating a little more memory because vectorized/bulk_alloc Rx
1770          * functions doesn't check boundaries each time.
1771          */
1772         len += RTE_PMD_I40E_RX_MAX_BURST;
1773 #endif
1774
1775         ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1776                               I40E_DMA_MEM_ALIGN);
1777
1778         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1779                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1780         if (!rz) {
1781                 i40e_dev_rx_queue_release(rxq);
1782                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1783                 return -ENOMEM;
1784         }
1785
1786         /* Zero all the descriptors in the ring. */
1787         memset(rz->addr, 0, ring_size);
1788
1789         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1790         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1791
1792 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1793         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1794 #else
1795         len = nb_desc;
1796 #endif
1797
1798         /* Allocate the software ring. */
1799         rxq->sw_ring =
1800                 rte_zmalloc_socket("i40e rx sw ring",
1801                                    sizeof(struct i40e_rx_entry) * len,
1802                                    RTE_CACHE_LINE_SIZE,
1803                                    socket_id);
1804         if (!rxq->sw_ring) {
1805                 i40e_dev_rx_queue_release(rxq);
1806                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1807                 return -ENOMEM;
1808         }
1809
1810         i40e_reset_rx_queue(rxq);
1811         rxq->q_set = TRUE;
1812         dev->data->rx_queues[queue_idx] = rxq;
1813
1814         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1815
1816         if (!use_def_burst_func) {
1817 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1818                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1819                              "satisfied. Rx Burst Bulk Alloc function will be "
1820                              "used on port=%d, queue=%d.",
1821                              rxq->port_id, rxq->queue_id);
1822 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1823         } else {
1824                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1825                              "not satisfied, Scattered Rx is requested, "
1826                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1827                              "not enabled on port=%d, queue=%d.",
1828                              rxq->port_id, rxq->queue_id);
1829                 ad->rx_bulk_alloc_allowed = false;
1830         }
1831
1832         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1833                 if (!(vsi->enabled_tc & (1 << i)))
1834                         continue;
1835                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1836                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1837                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1838                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1839                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1840
1841                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1842                         rxq->dcb_tc = i;
1843         }
1844
1845         return 0;
1846 }
1847
1848 void
1849 i40e_dev_rx_queue_release(void *rxq)
1850 {
1851         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1852
1853         if (!q) {
1854                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1855                 return;
1856         }
1857
1858         i40e_rx_queue_release_mbufs(q);
1859         rte_free(q->sw_ring);
1860         rte_free(q);
1861 }
1862
1863 uint32_t
1864 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1865 {
1866 #define I40E_RXQ_SCAN_INTERVAL 4
1867         volatile union i40e_rx_desc *rxdp;
1868         struct i40e_rx_queue *rxq;
1869         uint16_t desc = 0;
1870
1871         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1872                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1873                 return 0;
1874         }
1875
1876         rxq = dev->data->rx_queues[rx_queue_id];
1877         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1878         while ((desc < rxq->nb_rx_desc) &&
1879                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1880                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1881                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1882                 /**
1883                  * Check the DD bit of a rx descriptor of each 4 in a group,
1884                  * to avoid checking too frequently and downgrading performance
1885                  * too much.
1886                  */
1887                 desc += I40E_RXQ_SCAN_INTERVAL;
1888                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1889                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1890                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1891                                         desc - rxq->nb_rx_desc]);
1892         }
1893
1894         return desc;
1895 }
1896
1897 int
1898 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1899 {
1900         volatile union i40e_rx_desc *rxdp;
1901         struct i40e_rx_queue *rxq = rx_queue;
1902         uint16_t desc;
1903         int ret;
1904
1905         if (unlikely(offset >= rxq->nb_rx_desc)) {
1906                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1907                 return 0;
1908         }
1909
1910         desc = rxq->rx_tail + offset;
1911         if (desc >= rxq->nb_rx_desc)
1912                 desc -= rxq->nb_rx_desc;
1913
1914         rxdp = &(rxq->rx_ring[desc]);
1915
1916         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1917                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1918                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1919
1920         return ret;
1921 }
1922
1923 int
1924 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1925                         uint16_t queue_idx,
1926                         uint16_t nb_desc,
1927                         unsigned int socket_id,
1928                         const struct rte_eth_txconf *tx_conf)
1929 {
1930         struct i40e_vsi *vsi;
1931         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1932         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1933         struct i40e_tx_queue *txq;
1934         const struct rte_memzone *tz;
1935         uint32_t ring_size;
1936         uint16_t tx_rs_thresh, tx_free_thresh;
1937         uint16_t i, base, bsf, tc_mapping;
1938
1939         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1940                 struct i40e_vf *vf =
1941                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1942                 vsi = &vf->vsi;
1943         } else
1944                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1945
1946         if (vsi == NULL) {
1947                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
1948                             "exceeds the maximum", queue_idx);
1949                 return I40E_ERR_PARAM;
1950         }
1951
1952         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1953                         (nb_desc > I40E_MAX_RING_DESC) ||
1954                         (nb_desc < I40E_MIN_RING_DESC)) {
1955                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1956                             "invalid", nb_desc);
1957                 return I40E_ERR_PARAM;
1958         }
1959
1960         /**
1961          * The following two parameters control the setting of the RS bit on
1962          * transmit descriptors. TX descriptors will have their RS bit set
1963          * after txq->tx_rs_thresh descriptors have been used. The TX
1964          * descriptor ring will be cleaned after txq->tx_free_thresh
1965          * descriptors are used or if the number of descriptors required to
1966          * transmit a packet is greater than the number of free TX descriptors.
1967          *
1968          * The following constraints must be satisfied:
1969          *  - tx_rs_thresh must be greater than 0.
1970          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1971          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1972          *  - tx_rs_thresh must be a divisor of the ring size.
1973          *  - tx_free_thresh must be greater than 0.
1974          *  - tx_free_thresh must be less than the size of the ring minus 3.
1975          *
1976          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1977          * race condition, hence the maximum threshold constraints. When set
1978          * to zero use default values.
1979          */
1980         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1981                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1982         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1983                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1984         if (tx_rs_thresh >= (nb_desc - 2)) {
1985                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1986                              "number of TX descriptors minus 2. "
1987                              "(tx_rs_thresh=%u port=%d queue=%d)",
1988                              (unsigned int)tx_rs_thresh,
1989                              (int)dev->data->port_id,
1990                              (int)queue_idx);
1991                 return I40E_ERR_PARAM;
1992         }
1993         if (tx_free_thresh >= (nb_desc - 3)) {
1994                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
1995                              "number of TX descriptors minus 3. "
1996                              "(tx_free_thresh=%u port=%d queue=%d)",
1997                              (unsigned int)tx_free_thresh,
1998                              (int)dev->data->port_id,
1999                              (int)queue_idx);
2000                 return I40E_ERR_PARAM;
2001         }
2002         if (tx_rs_thresh > tx_free_thresh) {
2003                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2004                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2005                              " tx_rs_thresh=%u port=%d queue=%d)",
2006                              (unsigned int)tx_free_thresh,
2007                              (unsigned int)tx_rs_thresh,
2008                              (int)dev->data->port_id,
2009                              (int)queue_idx);
2010                 return I40E_ERR_PARAM;
2011         }
2012         if ((nb_desc % tx_rs_thresh) != 0) {
2013                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2014                              "number of TX descriptors. (tx_rs_thresh=%u"
2015                              " port=%d queue=%d)",
2016                              (unsigned int)tx_rs_thresh,
2017                              (int)dev->data->port_id,
2018                              (int)queue_idx);
2019                 return I40E_ERR_PARAM;
2020         }
2021         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2022                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2023                              "tx_rs_thresh is greater than 1. "
2024                              "(tx_rs_thresh=%u port=%d queue=%d)",
2025                              (unsigned int)tx_rs_thresh,
2026                              (int)dev->data->port_id,
2027                              (int)queue_idx);
2028                 return I40E_ERR_PARAM;
2029         }
2030
2031         /* Free memory if needed. */
2032         if (dev->data->tx_queues[queue_idx]) {
2033                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2034                 dev->data->tx_queues[queue_idx] = NULL;
2035         }
2036
2037         /* Allocate the TX queue data structure. */
2038         txq = rte_zmalloc_socket("i40e tx queue",
2039                                   sizeof(struct i40e_tx_queue),
2040                                   RTE_CACHE_LINE_SIZE,
2041                                   socket_id);
2042         if (!txq) {
2043                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2044                             "tx queue structure");
2045                 return -ENOMEM;
2046         }
2047
2048         /* Allocate TX hardware ring descriptors. */
2049         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2050         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2051         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2052                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2053         if (!tz) {
2054                 i40e_dev_tx_queue_release(txq);
2055                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2056                 return -ENOMEM;
2057         }
2058
2059         txq->nb_tx_desc = nb_desc;
2060         txq->tx_rs_thresh = tx_rs_thresh;
2061         txq->tx_free_thresh = tx_free_thresh;
2062         txq->pthresh = tx_conf->tx_thresh.pthresh;
2063         txq->hthresh = tx_conf->tx_thresh.hthresh;
2064         txq->wthresh = tx_conf->tx_thresh.wthresh;
2065         txq->queue_id = queue_idx;
2066         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2067                 txq->reg_idx = queue_idx;
2068         else /* PF device */
2069                 txq->reg_idx = vsi->base_queue +
2070                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2071
2072         txq->port_id = dev->data->port_id;
2073         txq->txq_flags = tx_conf->txq_flags;
2074         txq->vsi = vsi;
2075         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2076
2077         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2078         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2079
2080         /* Allocate software ring */
2081         txq->sw_ring =
2082                 rte_zmalloc_socket("i40e tx sw ring",
2083                                    sizeof(struct i40e_tx_entry) * nb_desc,
2084                                    RTE_CACHE_LINE_SIZE,
2085                                    socket_id);
2086         if (!txq->sw_ring) {
2087                 i40e_dev_tx_queue_release(txq);
2088                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2089                 return -ENOMEM;
2090         }
2091
2092         i40e_reset_tx_queue(txq);
2093         txq->q_set = TRUE;
2094         dev->data->tx_queues[queue_idx] = txq;
2095
2096         /* Use a simple TX queue without offloads or multi segs if possible */
2097         i40e_set_tx_function_flag(dev, txq);
2098
2099         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2100                 if (!(vsi->enabled_tc & (1 << i)))
2101                         continue;
2102                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2103                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2104                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2105                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2106                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2107
2108                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2109                         txq->dcb_tc = i;
2110         }
2111
2112         return 0;
2113 }
2114
2115 void
2116 i40e_dev_tx_queue_release(void *txq)
2117 {
2118         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2119
2120         if (!q) {
2121                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2122                 return;
2123         }
2124
2125         i40e_tx_queue_release_mbufs(q);
2126         rte_free(q->sw_ring);
2127         rte_free(q);
2128 }
2129
2130 const struct rte_memzone *
2131 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2132 {
2133         const struct rte_memzone *mz;
2134
2135         mz = rte_memzone_lookup(name);
2136         if (mz)
2137                 return mz;
2138
2139         if (rte_xen_dom0_supported())
2140                 mz = rte_memzone_reserve_bounded(name, len,
2141                                 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2142         else
2143                 mz = rte_memzone_reserve_aligned(name, len,
2144                                 socket_id, 0, I40E_RING_BASE_ALIGN);
2145         return mz;
2146 }
2147
2148 void
2149 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2150 {
2151         uint16_t i;
2152
2153         /* SSE Vector driver has a different way of releasing mbufs. */
2154         if (rxq->rx_using_sse) {
2155                 i40e_rx_queue_release_mbufs_vec(rxq);
2156                 return;
2157         }
2158
2159         if (!rxq->sw_ring) {
2160                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2161                 return;
2162         }
2163
2164         for (i = 0; i < rxq->nb_rx_desc; i++) {
2165                 if (rxq->sw_ring[i].mbuf) {
2166                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2167                         rxq->sw_ring[i].mbuf = NULL;
2168                 }
2169         }
2170 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2171         if (rxq->rx_nb_avail == 0)
2172                 return;
2173         for (i = 0; i < rxq->rx_nb_avail; i++) {
2174                 struct rte_mbuf *mbuf;
2175
2176                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2177                 rte_pktmbuf_free_seg(mbuf);
2178         }
2179         rxq->rx_nb_avail = 0;
2180 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2181 }
2182
2183 void
2184 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2185 {
2186         unsigned i;
2187         uint16_t len;
2188
2189         if (!rxq) {
2190                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2191                 return;
2192         }
2193
2194 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2195         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2196                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2197         else
2198 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2199                 len = rxq->nb_rx_desc;
2200
2201         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2202                 ((volatile char *)rxq->rx_ring)[i] = 0;
2203
2204 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2205         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2206         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2207                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2208
2209         rxq->rx_nb_avail = 0;
2210         rxq->rx_next_avail = 0;
2211         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2212 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2213         rxq->rx_tail = 0;
2214         rxq->nb_rx_hold = 0;
2215         rxq->pkt_first_seg = NULL;
2216         rxq->pkt_last_seg = NULL;
2217
2218         rxq->rxrearm_start = 0;
2219         rxq->rxrearm_nb = 0;
2220 }
2221
2222 void
2223 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2224 {
2225         uint16_t i;
2226
2227         if (!txq || !txq->sw_ring) {
2228                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2229                 return;
2230         }
2231
2232         for (i = 0; i < txq->nb_tx_desc; i++) {
2233                 if (txq->sw_ring[i].mbuf) {
2234                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2235                         txq->sw_ring[i].mbuf = NULL;
2236                 }
2237         }
2238 }
2239
2240 void
2241 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2242 {
2243         struct i40e_tx_entry *txe;
2244         uint16_t i, prev, size;
2245
2246         if (!txq) {
2247                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2248                 return;
2249         }
2250
2251         txe = txq->sw_ring;
2252         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2253         for (i = 0; i < size; i++)
2254                 ((volatile char *)txq->tx_ring)[i] = 0;
2255
2256         prev = (uint16_t)(txq->nb_tx_desc - 1);
2257         for (i = 0; i < txq->nb_tx_desc; i++) {
2258                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2259
2260                 txd->cmd_type_offset_bsz =
2261                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2262                 txe[i].mbuf =  NULL;
2263                 txe[i].last_id = i;
2264                 txe[prev].next_id = i;
2265                 prev = i;
2266         }
2267
2268         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2269         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2270
2271         txq->tx_tail = 0;
2272         txq->nb_tx_used = 0;
2273
2274         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2275         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2276 }
2277
2278 /* Init the TX queue in hardware */
2279 int
2280 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2281 {
2282         enum i40e_status_code err = I40E_SUCCESS;
2283         struct i40e_vsi *vsi = txq->vsi;
2284         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2285         uint16_t pf_q = txq->reg_idx;
2286         struct i40e_hmc_obj_txq tx_ctx;
2287         uint32_t qtx_ctl;
2288
2289         /* clear the context structure first */
2290         memset(&tx_ctx, 0, sizeof(tx_ctx));
2291         tx_ctx.new_context = 1;
2292         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2293         tx_ctx.qlen = txq->nb_tx_desc;
2294
2295 #ifdef RTE_LIBRTE_IEEE1588
2296         tx_ctx.timesync_ena = 1;
2297 #endif
2298         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2299         if (vsi->type == I40E_VSI_FDIR)
2300                 tx_ctx.fd_ena = TRUE;
2301
2302         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2303         if (err != I40E_SUCCESS) {
2304                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2305                 return err;
2306         }
2307
2308         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2309         if (err != I40E_SUCCESS) {
2310                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2311                 return err;
2312         }
2313
2314         /* Now associate this queue with this PCI function */
2315         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2316         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2317                                         I40E_QTX_CTL_PF_INDX_MASK);
2318         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2319         I40E_WRITE_FLUSH(hw);
2320
2321         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2322
2323         return err;
2324 }
2325
2326 int
2327 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2328 {
2329         struct i40e_rx_entry *rxe = rxq->sw_ring;
2330         uint64_t dma_addr;
2331         uint16_t i;
2332
2333         for (i = 0; i < rxq->nb_rx_desc; i++) {
2334                 volatile union i40e_rx_desc *rxd;
2335                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2336
2337                 if (unlikely(!mbuf)) {
2338                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2339                         return -ENOMEM;
2340                 }
2341
2342                 rte_mbuf_refcnt_set(mbuf, 1);
2343                 mbuf->next = NULL;
2344                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2345                 mbuf->nb_segs = 1;
2346                 mbuf->port = rxq->port_id;
2347
2348                 dma_addr =
2349                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2350
2351                 rxd = &rxq->rx_ring[i];
2352                 rxd->read.pkt_addr = dma_addr;
2353                 rxd->read.hdr_addr = 0;
2354 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2355                 rxd->read.rsvd1 = 0;
2356                 rxd->read.rsvd2 = 0;
2357 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2358
2359                 rxe[i].mbuf = mbuf;
2360         }
2361
2362         return 0;
2363 }
2364
2365 /*
2366  * Calculate the buffer length, and check the jumbo frame
2367  * and maximum packet length.
2368  */
2369 static int
2370 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2371 {
2372         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2373         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2374         struct rte_eth_dev_data *data = pf->dev_data;
2375         uint16_t buf_size, len;
2376
2377         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2378                 RTE_PKTMBUF_HEADROOM);
2379
2380         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2381                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2382         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2383                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2384                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2385                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2386                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2387                 rxq->hs_mode = i40e_header_split_enabled;
2388                 break;
2389         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2390         default:
2391                 rxq->rx_hdr_len = 0;
2392                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2393                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2394                 rxq->hs_mode = i40e_header_split_none;
2395                 break;
2396         }
2397
2398         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2399         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2400         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2401                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2402                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2403                         PMD_DRV_LOG(ERR, "maximum packet length must "
2404                                     "be larger than %u and smaller than %u,"
2405                                     "as jumbo frame is enabled",
2406                                     (uint32_t)ETHER_MAX_LEN,
2407                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2408                         return I40E_ERR_CONFIG;
2409                 }
2410         } else {
2411                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2412                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2413                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2414                                     "larger than %u and smaller than %u, "
2415                                     "as jumbo frame is disabled",
2416                                     (uint32_t)ETHER_MIN_LEN,
2417                                     (uint32_t)ETHER_MAX_LEN);
2418                         return I40E_ERR_CONFIG;
2419                 }
2420         }
2421
2422         return 0;
2423 }
2424
2425 /* Init the RX queue in hardware */
2426 int
2427 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2428 {
2429         int err = I40E_SUCCESS;
2430         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2431         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2432         uint16_t pf_q = rxq->reg_idx;
2433         uint16_t buf_size;
2434         struct i40e_hmc_obj_rxq rx_ctx;
2435
2436         err = i40e_rx_queue_config(rxq);
2437         if (err < 0) {
2438                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2439                 return err;
2440         }
2441
2442         /* Clear the context structure first */
2443         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2444         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2445         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2446
2447         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2448         rx_ctx.qlen = rxq->nb_rx_desc;
2449 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2450         rx_ctx.dsize = 1;
2451 #endif
2452         rx_ctx.dtype = rxq->hs_mode;
2453         if (rxq->hs_mode)
2454                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2455         else
2456                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2457         rx_ctx.rxmax = rxq->max_pkt_len;
2458         rx_ctx.tphrdesc_ena = 1;
2459         rx_ctx.tphwdesc_ena = 1;
2460         rx_ctx.tphdata_ena = 1;
2461         rx_ctx.tphhead_ena = 1;
2462         rx_ctx.lrxqthresh = 2;
2463         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2464         rx_ctx.l2tsel = 1;
2465         /* showiv indicates if inner VLAN is stripped inside of tunnel
2466          * packet. When set it to 1, vlan information is stripped from
2467          * the inner header, but the hardware does not put it in the
2468          * descriptor. So set it zero by default.
2469          */
2470         rx_ctx.showiv = 0;
2471         rx_ctx.prefena = 1;
2472
2473         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2474         if (err != I40E_SUCCESS) {
2475                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2476                 return err;
2477         }
2478         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2479         if (err != I40E_SUCCESS) {
2480                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2481                 return err;
2482         }
2483
2484         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2485
2486         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2487                 RTE_PKTMBUF_HEADROOM);
2488
2489         /* Check if scattered RX needs to be used. */
2490         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2491                 dev_data->scattered_rx = 1;
2492         }
2493
2494         /* Init the RX tail regieter. */
2495         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2496
2497         return 0;
2498 }
2499
2500 void
2501 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2502 {
2503         uint16_t i;
2504
2505         PMD_INIT_FUNC_TRACE();
2506
2507         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2508                 if (!dev->data->tx_queues[i])
2509                         continue;
2510                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2511                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2512         }
2513
2514         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2515                 if (!dev->data->rx_queues[i])
2516                         continue;
2517                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2518                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2519         }
2520 }
2521
2522 void
2523 i40e_dev_free_queues(struct rte_eth_dev *dev)
2524 {
2525         uint16_t i;
2526
2527         PMD_INIT_FUNC_TRACE();
2528
2529         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2530                 if (!dev->data->rx_queues[i])
2531                         continue;
2532                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2533                 dev->data->rx_queues[i] = NULL;
2534         }
2535         dev->data->nb_rx_queues = 0;
2536
2537         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2538                 if (!dev->data->tx_queues[i])
2539                         continue;
2540                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2541                 dev->data->tx_queues[i] = NULL;
2542         }
2543         dev->data->nb_tx_queues = 0;
2544 }
2545
2546 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2547 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2548
2549 enum i40e_status_code
2550 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2551 {
2552         struct i40e_tx_queue *txq;
2553         const struct rte_memzone *tz = NULL;
2554         uint32_t ring_size;
2555         struct rte_eth_dev *dev;
2556
2557         if (!pf) {
2558                 PMD_DRV_LOG(ERR, "PF is not available");
2559                 return I40E_ERR_BAD_PTR;
2560         }
2561
2562         dev = pf->adapter->eth_dev;
2563
2564         /* Allocate the TX queue data structure. */
2565         txq = rte_zmalloc_socket("i40e fdir tx queue",
2566                                   sizeof(struct i40e_tx_queue),
2567                                   RTE_CACHE_LINE_SIZE,
2568                                   SOCKET_ID_ANY);
2569         if (!txq) {
2570                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2571                                         "tx queue structure.");
2572                 return I40E_ERR_NO_MEMORY;
2573         }
2574
2575         /* Allocate TX hardware ring descriptors. */
2576         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2577         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2578
2579         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2580                                       I40E_FDIR_QUEUE_ID, ring_size,
2581                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2582         if (!tz) {
2583                 i40e_dev_tx_queue_release(txq);
2584                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2585                 return I40E_ERR_NO_MEMORY;
2586         }
2587
2588         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2589         txq->queue_id = I40E_FDIR_QUEUE_ID;
2590         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2591         txq->vsi = pf->fdir.fdir_vsi;
2592
2593         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2594         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2595         /*
2596          * don't need to allocate software ring and reset for the fdir
2597          * program queue just set the queue has been configured.
2598          */
2599         txq->q_set = TRUE;
2600         pf->fdir.txq = txq;
2601
2602         return I40E_SUCCESS;
2603 }
2604
2605 enum i40e_status_code
2606 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2607 {
2608         struct i40e_rx_queue *rxq;
2609         const struct rte_memzone *rz = NULL;
2610         uint32_t ring_size;
2611         struct rte_eth_dev *dev;
2612
2613         if (!pf) {
2614                 PMD_DRV_LOG(ERR, "PF is not available");
2615                 return I40E_ERR_BAD_PTR;
2616         }
2617
2618         dev = pf->adapter->eth_dev;
2619
2620         /* Allocate the RX queue data structure. */
2621         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2622                                   sizeof(struct i40e_rx_queue),
2623                                   RTE_CACHE_LINE_SIZE,
2624                                   SOCKET_ID_ANY);
2625         if (!rxq) {
2626                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2627                                         "rx queue structure.");
2628                 return I40E_ERR_NO_MEMORY;
2629         }
2630
2631         /* Allocate RX hardware ring descriptors. */
2632         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2633         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2634
2635         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2636                                       I40E_FDIR_QUEUE_ID, ring_size,
2637                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2638         if (!rz) {
2639                 i40e_dev_rx_queue_release(rxq);
2640                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2641                 return I40E_ERR_NO_MEMORY;
2642         }
2643
2644         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2645         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2646         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2647         rxq->vsi = pf->fdir.fdir_vsi;
2648
2649         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2650         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2651
2652         /*
2653          * Don't need to allocate software ring and reset for the fdir
2654          * rx queue, just set the queue has been configured.
2655          */
2656         rxq->q_set = TRUE;
2657         pf->fdir.rxq = rxq;
2658
2659         return I40E_SUCCESS;
2660 }
2661
2662 void
2663 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2664         struct rte_eth_rxq_info *qinfo)
2665 {
2666         struct i40e_rx_queue *rxq;
2667
2668         rxq = dev->data->rx_queues[queue_id];
2669
2670         qinfo->mp = rxq->mp;
2671         qinfo->scattered_rx = dev->data->scattered_rx;
2672         qinfo->nb_desc = rxq->nb_rx_desc;
2673
2674         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2675         qinfo->conf.rx_drop_en = rxq->drop_en;
2676         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2677 }
2678
2679 void
2680 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2681         struct rte_eth_txq_info *qinfo)
2682 {
2683         struct i40e_tx_queue *txq;
2684
2685         txq = dev->data->tx_queues[queue_id];
2686
2687         qinfo->nb_desc = txq->nb_tx_desc;
2688
2689         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2690         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2691         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2692
2693         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2694         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2695         qinfo->conf.txq_flags = txq->txq_flags;
2696         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2697 }
2698
2699 void __attribute__((cold))
2700 i40e_set_rx_function(struct rte_eth_dev *dev)
2701 {
2702         struct i40e_adapter *ad =
2703                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2704         uint16_t rx_using_sse, i;
2705         /* In order to allow Vector Rx there are a few configuration
2706          * conditions to be met and Rx Bulk Allocation should be allowed.
2707          */
2708         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2709                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2710                     !ad->rx_bulk_alloc_allowed) {
2711                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2712                                      " Vector Rx preconditions",
2713                                      dev->data->port_id);
2714
2715                         ad->rx_vec_allowed = false;
2716                 }
2717                 if (ad->rx_vec_allowed) {
2718                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2719                                 struct i40e_rx_queue *rxq =
2720                                         dev->data->rx_queues[i];
2721
2722                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
2723                                         ad->rx_vec_allowed = false;
2724                                         break;
2725                                 }
2726                         }
2727                 }
2728         }
2729
2730         if (dev->data->scattered_rx) {
2731                 /* Set the non-LRO scattered callback: there are Vector and
2732                  * single allocation versions.
2733                  */
2734                 if (ad->rx_vec_allowed) {
2735                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
2736                                             "callback (port=%d).",
2737                                      dev->data->port_id);
2738
2739                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
2740                 } else {
2741                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
2742                                            "allocation callback (port=%d).",
2743                                      dev->data->port_id);
2744                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2745                 }
2746         /* If parameters allow we are going to choose between the following
2747          * callbacks:
2748          *    - Vector
2749          *    - Bulk Allocation
2750          *    - Single buffer allocation (the simplest one)
2751          */
2752         } else if (ad->rx_vec_allowed) {
2753                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
2754                                     "burst size no less than %d (port=%d).",
2755                              RTE_I40E_DESCS_PER_LOOP,
2756                              dev->data->port_id);
2757
2758                 dev->rx_pkt_burst = i40e_recv_pkts_vec;
2759         } else if (ad->rx_bulk_alloc_allowed) {
2760                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2761                                     "satisfied. Rx Burst Bulk Alloc function "
2762                                     "will be used on port=%d.",
2763                              dev->data->port_id);
2764
2765                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2766         } else {
2767                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
2768                                     "satisfied, or Scattered Rx is requested "
2769                                     "(port=%d).",
2770                              dev->data->port_id);
2771
2772                 dev->rx_pkt_burst = i40e_recv_pkts;
2773         }
2774
2775         /* Propagate information about RX function choice through all queues. */
2776         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2777                 rx_using_sse =
2778                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
2779                          dev->rx_pkt_burst == i40e_recv_pkts_vec);
2780
2781                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2782                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
2783
2784                         if (rxq)
2785                                 rxq->rx_using_sse = rx_using_sse;
2786                 }
2787         }
2788 }
2789
2790 void __attribute__((cold))
2791 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
2792 {
2793         struct i40e_adapter *ad =
2794                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2795
2796         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2797         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
2798                         && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
2799                 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
2800                         PMD_INIT_LOG(DEBUG, "Vector tx"
2801                                      " can be enabled on this txq.");
2802
2803                 } else {
2804                         ad->tx_vec_allowed = false;
2805                 }
2806         } else {
2807                 ad->tx_simple_allowed = false;
2808         }
2809 }
2810
2811 void __attribute__((cold))
2812 i40e_set_tx_function(struct rte_eth_dev *dev)
2813 {
2814         struct i40e_adapter *ad =
2815                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2816         int i;
2817
2818         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2819                 if (ad->tx_vec_allowed) {
2820                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2821                                 struct i40e_tx_queue *txq =
2822                                         dev->data->tx_queues[i];
2823
2824                                 if (txq && i40e_txq_vec_setup(txq)) {
2825                                         ad->tx_vec_allowed = false;
2826                                         break;
2827                                 }
2828                         }
2829                 }
2830         }
2831
2832         if (ad->tx_simple_allowed) {
2833                 if (ad->tx_vec_allowed) {
2834                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
2835                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
2836                 } else {
2837                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2838                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2839                 }
2840                 dev->tx_pkt_prepare = NULL;
2841         } else {
2842                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
2843                 dev->tx_pkt_burst = i40e_xmit_pkts;
2844                 dev->tx_pkt_prepare = i40e_prep_pkts;
2845         }
2846 }
2847
2848 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
2849 int __attribute__((weak))
2850 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
2851 {
2852         return -1;
2853 }
2854
2855 uint16_t __attribute__((weak))
2856 i40e_recv_pkts_vec(
2857         void __rte_unused *rx_queue,
2858         struct rte_mbuf __rte_unused **rx_pkts,
2859         uint16_t __rte_unused nb_pkts)
2860 {
2861         return 0;
2862 }
2863
2864 uint16_t __attribute__((weak))
2865 i40e_recv_scattered_pkts_vec(
2866         void __rte_unused *rx_queue,
2867         struct rte_mbuf __rte_unused **rx_pkts,
2868         uint16_t __rte_unused nb_pkts)
2869 {
2870         return 0;
2871 }
2872
2873 int __attribute__((weak))
2874 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
2875 {
2876         return -1;
2877 }
2878
2879 int __attribute__((weak))
2880 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
2881 {
2882         return -1;
2883 }
2884
2885 void __attribute__((weak))
2886 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
2887 {
2888         return;
2889 }
2890
2891 uint16_t __attribute__((weak))
2892 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
2893                    struct rte_mbuf __rte_unused **tx_pkts,
2894                    uint16_t __rte_unused nb_pkts)
2895 {
2896         return 0;
2897 }