drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59
  60 #define DEFAULT_TX_RS_THRESH   32
  61 #define DEFAULT_TX_FREE_THRESH 32
  62 #define I40E_MAX_PKT_TYPE      256
  63
  64 #define I40E_TX_MAX_BURST  32
  65
  66 #define I40E_DMA_MEM_ALIGN 4096
  67
  68 /* Base address of the HW descriptor ring should be 128B aligned. */
  69 #define I40E_RING_BASE_ALIGN    128
  70
  71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  72                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  73
  74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  75
  76 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  77                 PKT_TX_IP_CKSUM |                \
  78                 PKT_TX_L4_MASK |                 \
  79                 PKT_TX_OUTER_IP_CKSUM)
  80
  81 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  82                                       struct rte_mbuf **tx_pkts,
  83                                       uint16_t nb_pkts);
  84
  85 static inline void
  86 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  87 {
  88         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
  89                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
  90                 mb->ol_flags |= PKT_RX_VLAN_PKT;
  91                 mb->vlan_tci =
  92                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
  93                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
  94                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
  95         } else {
  96                 mb->vlan_tci = 0;
  97         }
  98 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
  99         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 100                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 101                 mb->ol_flags |= PKT_RX_QINQ_PKT;
 102                 mb->vlan_tci_outer = mb->vlan_tci;
 103                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 104                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 105                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 106                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 107         } else {
 108                 mb->vlan_tci_outer = 0;
 109         }
 110 #endif
 111         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 112                    mb->vlan_tci, mb->vlan_tci_outer);
 113 }
 114
 115 /* Translate the rx descriptor status to pkt flags */
 116 static inline uint64_t
 117 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 118 {
 119         uint64_t flags;
 120
 121         /* Check if RSS_HASH */
 122         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 123                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 124                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 125
 126         /* Check if FDIR Match */
 127         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 128                                                         PKT_RX_FDIR : 0);
 129
 130         return flags;
 131 }
 132
 133 static inline uint64_t
 134 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 135 {
 136         uint64_t flags = 0;
 137         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 138
 139 #define I40E_RX_ERR_BITS 0x3f
 140         if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
 141                 return flags;
 142         /* If RXE bit set, all other status bits are meaningless */
 143         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
 144                 flags |= PKT_RX_MAC_ERR;
 145                 return flags;
 146         }
 147
 148         /* If RECIPE bit set, all other status indications should be ignored */
 149         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
 150                 flags |= PKT_RX_RECIP_ERR;
 151                 return flags;
 152         }
 153         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
 154                 flags |= PKT_RX_HBUF_OVERFLOW;
 155         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 156                 flags |= PKT_RX_IP_CKSUM_BAD;
 157         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 158                 flags |= PKT_RX_L4_CKSUM_BAD;
 159         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 160                 flags |= PKT_RX_EIP_CKSUM_BAD;
 161         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
 162                 flags |= PKT_RX_OVERSIZE;
 163
 164         return flags;
 165 }
 166
 167 /* Function to check and set the ieee1588 timesync index and get the
 168  * appropriate flags.
 169  */
 170 #ifdef RTE_LIBRTE_IEEE1588
 171 static inline uint64_t
 172 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 173 {
 174         uint64_t pkt_flags = 0;
 175         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 176                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 177                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 178
 179         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 180                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 181                 pkt_flags = PKT_RX_IEEE1588_PTP;
 182         if (tsyn & 0x04) {
 183                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 184                 mb->timesync = tsyn & 0x03;
 185         }
 186
 187         return pkt_flags;
 188 }
 189 #endif
 190
 191 /* For each value it means, datasheet of hardware can tell more details */
 192 static inline uint32_t
 193 i40e_rxd_pkt_type_mapping(uint8_t ptype)
 194 {
 195         static const uint32_t ptype_table[UINT8_MAX] __rte_cache_aligned = {
 196                 /* L2 types */
 197                 /* [0] reserved */
 198                 [1] = RTE_PTYPE_L2_ETHER,
 199                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
 200                 /* [3] - [5] reserved */
 201                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
 202                 /* [7] - [10] reserved */
 203                 [11] = RTE_PTYPE_L2_ETHER_ARP,
 204                 /* [12] - [21] reserved */
 205
 206                 /* Non tunneled IPv4 */
 207                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 208                         RTE_PTYPE_L4_FRAG,
 209                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 210                         RTE_PTYPE_L4_NONFRAG,
 211                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 212                         RTE_PTYPE_L4_UDP,
 213                 /* [25] reserved */
 214                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 215                         RTE_PTYPE_L4_TCP,
 216                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 217                         RTE_PTYPE_L4_SCTP,
 218                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 219                         RTE_PTYPE_L4_ICMP,
 220
 221                 /* IPv4 --> IPv4 */
 222                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 223                         RTE_PTYPE_TUNNEL_IP |
 224                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 225                         RTE_PTYPE_INNER_L4_FRAG,
 226                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 227                         RTE_PTYPE_TUNNEL_IP |
 228                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 229                         RTE_PTYPE_INNER_L4_NONFRAG,
 230                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 231                         RTE_PTYPE_TUNNEL_IP |
 232                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 233                         RTE_PTYPE_INNER_L4_UDP,
 234                 /* [32] reserved */
 235                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 236                         RTE_PTYPE_TUNNEL_IP |
 237                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 238                         RTE_PTYPE_INNER_L4_TCP,
 239                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 240                         RTE_PTYPE_TUNNEL_IP |
 241                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 242                         RTE_PTYPE_INNER_L4_SCTP,
 243                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 244                         RTE_PTYPE_TUNNEL_IP |
 245                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 246                         RTE_PTYPE_INNER_L4_ICMP,
 247
 248                 /* IPv4 --> IPv6 */
 249                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 250                         RTE_PTYPE_TUNNEL_IP |
 251                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 252                         RTE_PTYPE_INNER_L4_FRAG,
 253                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 254                         RTE_PTYPE_TUNNEL_IP |
 255                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 256                         RTE_PTYPE_INNER_L4_NONFRAG,
 257                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 258                         RTE_PTYPE_TUNNEL_IP |
 259                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 260                         RTE_PTYPE_INNER_L4_UDP,
 261                 /* [39] reserved */
 262                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 263                         RTE_PTYPE_TUNNEL_IP |
 264                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 265                         RTE_PTYPE_INNER_L4_TCP,
 266                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 267                         RTE_PTYPE_TUNNEL_IP |
 268                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 269                         RTE_PTYPE_INNER_L4_SCTP,
 270                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 271                         RTE_PTYPE_TUNNEL_IP |
 272                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 273                         RTE_PTYPE_INNER_L4_ICMP,
 274
 275                 /* IPv4 --> GRE/Teredo/VXLAN */
 276                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 277                         RTE_PTYPE_TUNNEL_GRENAT,
 278
 279                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
 280                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 281                         RTE_PTYPE_TUNNEL_GRENAT |
 282                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 283                         RTE_PTYPE_INNER_L4_FRAG,
 284                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 285                         RTE_PTYPE_TUNNEL_GRENAT |
 286                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 287                         RTE_PTYPE_INNER_L4_NONFRAG,
 288                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 289                         RTE_PTYPE_TUNNEL_GRENAT |
 290                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 291                         RTE_PTYPE_INNER_L4_UDP,
 292                 /* [47] reserved */
 293                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 294                         RTE_PTYPE_TUNNEL_GRENAT |
 295                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 296                         RTE_PTYPE_INNER_L4_TCP,
 297                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 298                         RTE_PTYPE_TUNNEL_GRENAT |
 299                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 300                         RTE_PTYPE_INNER_L4_SCTP,
 301                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 302                         RTE_PTYPE_TUNNEL_GRENAT |
 303                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 304                         RTE_PTYPE_INNER_L4_ICMP,
 305
 306                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
 307                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 308                         RTE_PTYPE_TUNNEL_GRENAT |
 309                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 310                         RTE_PTYPE_INNER_L4_FRAG,
 311                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 312                         RTE_PTYPE_TUNNEL_GRENAT |
 313                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 314                         RTE_PTYPE_INNER_L4_NONFRAG,
 315                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 316                         RTE_PTYPE_TUNNEL_GRENAT |
 317                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 318                         RTE_PTYPE_INNER_L4_UDP,
 319                 /* [54] reserved */
 320                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 321                         RTE_PTYPE_TUNNEL_GRENAT |
 322                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 323                         RTE_PTYPE_INNER_L4_TCP,
 324                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 325                         RTE_PTYPE_TUNNEL_GRENAT |
 326                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 327                         RTE_PTYPE_INNER_L4_SCTP,
 328                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 329                         RTE_PTYPE_TUNNEL_GRENAT |
 330                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 331                         RTE_PTYPE_INNER_L4_ICMP,
 332
 333                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
 334                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 335                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
 336
 337                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
 338                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 339                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 340                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 341                         RTE_PTYPE_INNER_L4_FRAG,
 342                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 343                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 344                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 345                         RTE_PTYPE_INNER_L4_NONFRAG,
 346                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 347                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 348                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 349                         RTE_PTYPE_INNER_L4_UDP,
 350                 /* [62] reserved */
 351                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 352                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 353                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 354                         RTE_PTYPE_INNER_L4_TCP,
 355                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 356                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 357                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 358                         RTE_PTYPE_INNER_L4_SCTP,
 359                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 360                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 361                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 362                         RTE_PTYPE_INNER_L4_ICMP,
 363
 364                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
 365                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 366                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 367                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 368                         RTE_PTYPE_INNER_L4_FRAG,
 369                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 370                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 371                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 372                         RTE_PTYPE_INNER_L4_NONFRAG,
 373                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 374                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 375                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 376                         RTE_PTYPE_INNER_L4_UDP,
 377                 /* [69] reserved */
 378                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 379                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 380                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 381                         RTE_PTYPE_INNER_L4_TCP,
 382                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 383                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 384                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 385                         RTE_PTYPE_INNER_L4_SCTP,
 386                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 387                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 388                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 389                         RTE_PTYPE_INNER_L4_ICMP,
 390
 391                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
 392                 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 393                         RTE_PTYPE_TUNNEL_GRENAT |
 394                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
 395
 396                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
 397                 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 398                         RTE_PTYPE_TUNNEL_GRENAT |
 399                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 400                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 401                         RTE_PTYPE_INNER_L4_FRAG,
 402                 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 403                         RTE_PTYPE_TUNNEL_GRENAT |
 404                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 405                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 406                         RTE_PTYPE_INNER_L4_NONFRAG,
 407                 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 408                         RTE_PTYPE_TUNNEL_GRENAT |
 409                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 410                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 411                         RTE_PTYPE_INNER_L4_UDP,
 412                 /* [77] reserved */
 413                 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 414                         RTE_PTYPE_TUNNEL_GRENAT |
 415                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 416                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 417                         RTE_PTYPE_INNER_L4_TCP,
 418                 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 419                         RTE_PTYPE_TUNNEL_GRENAT |
 420                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 421                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 422                         RTE_PTYPE_INNER_L4_SCTP,
 423                 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 424                         RTE_PTYPE_TUNNEL_GRENAT |
 425                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 426                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 427                         RTE_PTYPE_INNER_L4_ICMP,
 428
 429                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
 430                 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 431                         RTE_PTYPE_TUNNEL_GRENAT |
 432                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 433                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 434                         RTE_PTYPE_INNER_L4_FRAG,
 435                 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 436                         RTE_PTYPE_TUNNEL_GRENAT |
 437                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 438                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 439                         RTE_PTYPE_INNER_L4_NONFRAG,
 440                 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 441                         RTE_PTYPE_TUNNEL_GRENAT |
 442                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 443                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 444                         RTE_PTYPE_INNER_L4_UDP,
 445                 /* [84] reserved */
 446                 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 447                         RTE_PTYPE_TUNNEL_GRENAT |
 448                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 449                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 450                         RTE_PTYPE_INNER_L4_TCP,
 451                 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 452                         RTE_PTYPE_TUNNEL_GRENAT |
 453                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 454                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 455                         RTE_PTYPE_INNER_L4_SCTP,
 456                 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 457                         RTE_PTYPE_TUNNEL_GRENAT |
 458                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 459                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 460                         RTE_PTYPE_INNER_L4_ICMP,
 461
 462                 /* Non tunneled IPv6 */
 463                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 464                         RTE_PTYPE_L4_FRAG,
 465                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 466                         RTE_PTYPE_L4_NONFRAG,
 467                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 468                         RTE_PTYPE_L4_UDP,
 469                 /* [91] reserved */
 470                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 471                         RTE_PTYPE_L4_TCP,
 472                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 473                         RTE_PTYPE_L4_SCTP,
 474                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 475                         RTE_PTYPE_L4_ICMP,
 476
 477                 /* IPv6 --> IPv4 */
 478                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 479                         RTE_PTYPE_TUNNEL_IP |
 480                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 481                         RTE_PTYPE_INNER_L4_FRAG,
 482                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 483                         RTE_PTYPE_TUNNEL_IP |
 484                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 485                         RTE_PTYPE_INNER_L4_NONFRAG,
 486                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 487                         RTE_PTYPE_TUNNEL_IP |
 488                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 489                         RTE_PTYPE_INNER_L4_UDP,
 490                 /* [98] reserved */
 491                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 492                         RTE_PTYPE_TUNNEL_IP |
 493                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 494                         RTE_PTYPE_INNER_L4_TCP,
 495                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 496                         RTE_PTYPE_TUNNEL_IP |
 497                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 498                         RTE_PTYPE_INNER_L4_SCTP,
 499                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 500                         RTE_PTYPE_TUNNEL_IP |
 501                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 502                         RTE_PTYPE_INNER_L4_ICMP,
 503
 504                 /* IPv6 --> IPv6 */
 505                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 506                         RTE_PTYPE_TUNNEL_IP |
 507                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 508                         RTE_PTYPE_INNER_L4_FRAG,
 509                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 510                         RTE_PTYPE_TUNNEL_IP |
 511                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 512                         RTE_PTYPE_INNER_L4_NONFRAG,
 513                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 514                         RTE_PTYPE_TUNNEL_IP |
 515                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 516                         RTE_PTYPE_INNER_L4_UDP,
 517                 /* [105] reserved */
 518                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 519                         RTE_PTYPE_TUNNEL_IP |
 520                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 521                         RTE_PTYPE_INNER_L4_TCP,
 522                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 523                         RTE_PTYPE_TUNNEL_IP |
 524                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 525                         RTE_PTYPE_INNER_L4_SCTP,
 526                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 527                         RTE_PTYPE_TUNNEL_IP |
 528                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 529                         RTE_PTYPE_INNER_L4_ICMP,
 530
 531                 /* IPv6 --> GRE/Teredo/VXLAN */
 532                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 533                         RTE_PTYPE_TUNNEL_GRENAT,
 534
 535                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
 536                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 537                         RTE_PTYPE_TUNNEL_GRENAT |
 538                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 539                         RTE_PTYPE_INNER_L4_FRAG,
 540                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 541                         RTE_PTYPE_TUNNEL_GRENAT |
 542                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 543                         RTE_PTYPE_INNER_L4_NONFRAG,
 544                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 545                         RTE_PTYPE_TUNNEL_GRENAT |
 546                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 547                         RTE_PTYPE_INNER_L4_UDP,
 548                 /* [113] reserved */
 549                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 550                         RTE_PTYPE_TUNNEL_GRENAT |
 551                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 552                         RTE_PTYPE_INNER_L4_TCP,
 553                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 554                         RTE_PTYPE_TUNNEL_GRENAT |
 555                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 556                         RTE_PTYPE_INNER_L4_SCTP,
 557                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 558                         RTE_PTYPE_TUNNEL_GRENAT |
 559                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 560                         RTE_PTYPE_INNER_L4_ICMP,
 561
 562                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
 563                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 564                         RTE_PTYPE_TUNNEL_GRENAT |
 565                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 566                         RTE_PTYPE_INNER_L4_FRAG,
 567                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 568                         RTE_PTYPE_TUNNEL_GRENAT |
 569                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 570                         RTE_PTYPE_INNER_L4_NONFRAG,
 571                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 572                         RTE_PTYPE_TUNNEL_GRENAT |
 573                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 574                         RTE_PTYPE_INNER_L4_UDP,
 575                 /* [120] reserved */
 576                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 577                         RTE_PTYPE_TUNNEL_GRENAT |
 578                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 579                         RTE_PTYPE_INNER_L4_TCP,
 580                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 581                         RTE_PTYPE_TUNNEL_GRENAT |
 582                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 583                         RTE_PTYPE_INNER_L4_SCTP,
 584                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 585                         RTE_PTYPE_TUNNEL_GRENAT |
 586                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 587                         RTE_PTYPE_INNER_L4_ICMP,
 588
 589                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
 590                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 591                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
 592
 593                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
 594                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 595                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 596                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 597                         RTE_PTYPE_INNER_L4_FRAG,
 598                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 599                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 600                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 601                         RTE_PTYPE_INNER_L4_NONFRAG,
 602                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 603                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 604                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 605                         RTE_PTYPE_INNER_L4_UDP,
 606                 /* [128] reserved */
 607                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 608                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 609                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 610                         RTE_PTYPE_INNER_L4_TCP,
 611                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 612                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 613                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 614                         RTE_PTYPE_INNER_L4_SCTP,
 615                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 616                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 617                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 618                         RTE_PTYPE_INNER_L4_ICMP,
 619
 620                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
 621                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 622                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 623                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 624                         RTE_PTYPE_INNER_L4_FRAG,
 625                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 626                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 627                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 628                         RTE_PTYPE_INNER_L4_NONFRAG,
 629                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 630                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 631                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 632                         RTE_PTYPE_INNER_L4_UDP,
 633                 /* [135] reserved */
 634                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 635                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 636                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 637                         RTE_PTYPE_INNER_L4_TCP,
 638                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 639                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 640                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 641                         RTE_PTYPE_INNER_L4_SCTP,
 642                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 643                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 644                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 645                         RTE_PTYPE_INNER_L4_ICMP,
 646
 647                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
 648                 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 649                         RTE_PTYPE_TUNNEL_GRENAT |
 650                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
 651
 652                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
 653                 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 654                         RTE_PTYPE_TUNNEL_GRENAT |
 655                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 656                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 657                         RTE_PTYPE_INNER_L4_FRAG,
 658                 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 659                         RTE_PTYPE_TUNNEL_GRENAT |
 660                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 661                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 662                         RTE_PTYPE_INNER_L4_NONFRAG,
 663                 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 664                         RTE_PTYPE_TUNNEL_GRENAT |
 665                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 666                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 667                         RTE_PTYPE_INNER_L4_UDP,
 668                 /* [143] reserved */
 669                 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 670                         RTE_PTYPE_TUNNEL_GRENAT |
 671                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 672                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 673                         RTE_PTYPE_INNER_L4_TCP,
 674                 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 675                         RTE_PTYPE_TUNNEL_GRENAT |
 676                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 677                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 678                         RTE_PTYPE_INNER_L4_SCTP,
 679                 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 680                         RTE_PTYPE_TUNNEL_GRENAT |
 681                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 682                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 683                         RTE_PTYPE_INNER_L4_ICMP,
 684
 685                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
 686                 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 687                         RTE_PTYPE_TUNNEL_GRENAT |
 688                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 689                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 690                         RTE_PTYPE_INNER_L4_FRAG,
 691                 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 692                         RTE_PTYPE_TUNNEL_GRENAT |
 693                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 694                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 695                         RTE_PTYPE_INNER_L4_NONFRAG,
 696                 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 697                         RTE_PTYPE_TUNNEL_GRENAT |
 698                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 699                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 700                         RTE_PTYPE_INNER_L4_UDP,
 701                 /* [150] reserved */
 702                 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 703                         RTE_PTYPE_TUNNEL_GRENAT |
 704                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 705                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 706                         RTE_PTYPE_INNER_L4_TCP,
 707                 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 708                         RTE_PTYPE_TUNNEL_GRENAT |
 709                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 710                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 711                         RTE_PTYPE_INNER_L4_SCTP,
 712                 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 713                         RTE_PTYPE_TUNNEL_GRENAT |
 714                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 715                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 716                         RTE_PTYPE_INNER_L4_ICMP,
 717
 718                 /* All others reserved */
 719         };
 720
 721         return ptype_table[ptype];
 722 }
 723
 724 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 725 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 726 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 727 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 728 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 729
 730 static inline uint64_t
 731 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 732 {
 733         uint64_t flags = 0;
 734 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 735         uint16_t flexbh, flexbl;
 736
 737         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 738                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 739                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 740         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 741                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 742                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 743
 744
 745         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 746                 mb->hash.fdir.hi =
 747                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 748                 flags |= PKT_RX_FDIR_ID;
 749         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 750                 mb->hash.fdir.hi =
 751                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 752                 flags |= PKT_RX_FDIR_FLX;
 753         }
 754         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 755                 mb->hash.fdir.lo =
 756                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 757                 flags |= PKT_RX_FDIR_FLX;
 758         }
 759 #else
 760         mb->hash.fdir.hi =
 761                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 762         flags |= PKT_RX_FDIR_ID;
 763 #endif
 764         return flags;
 765 }
 766 static inline void
 767 i40e_txd_enable_checksum(uint64_t ol_flags,
 768                         uint32_t *td_cmd,
 769                         uint32_t *td_offset,
 770                         union i40e_tx_offload tx_offload,
 771                         uint32_t *cd_tunneling)
 772 {
 773         /* UDP tunneling packet TX checksum offload */
 774         if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
 775
 776                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 777                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 778
 779                 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 780                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 781                 else if (ol_flags & PKT_TX_OUTER_IPV4)
 782                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 783                 else if (ol_flags & PKT_TX_OUTER_IPV6)
 784                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 785
 786                 /* Now set the ctx descriptor fields */
 787                 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 788                                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
 789                                 (tx_offload.l2_len >> 1) <<
 790                                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 791
 792         } else
 793                 *td_offset |= (tx_offload.l2_len >> 1)
 794                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 795
 796         /* Enable L3 checksum offloads */
 797         if (ol_flags & PKT_TX_IP_CKSUM) {
 798                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 799                 *td_offset |= (tx_offload.l3_len >> 2)
 800                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 801         } else if (ol_flags & PKT_TX_IPV4) {
 802                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 803                 *td_offset |= (tx_offload.l3_len >> 2)
 804                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 805         } else if (ol_flags & PKT_TX_IPV6) {
 806                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 807                 *td_offset |= (tx_offload.l3_len >> 2)
 808                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 809         }
 810
 811         if (ol_flags & PKT_TX_TCP_SEG) {
 812                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 813                 *td_offset |= (tx_offload.l4_len >> 2)
 814                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 815                 return;
 816         }
 817
 818         /* Enable L4 checksum offloads */
 819         switch (ol_flags & PKT_TX_L4_MASK) {
 820         case PKT_TX_TCP_CKSUM:
 821                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 822                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 823                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 824                 break;
 825         case PKT_TX_SCTP_CKSUM:
 826                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 827                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 828                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 829                 break;
 830         case PKT_TX_UDP_CKSUM:
 831                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 832                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 833                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 834                 break;
 835         default:
 836                 break;
 837         }
 838 }
 839
 840 static inline struct rte_mbuf *
 841 rte_rxmbuf_alloc(struct rte_mempool *mp)
 842 {
 843         struct rte_mbuf *m;
 844
 845         m = __rte_mbuf_raw_alloc(mp);
 846         __rte_mbuf_sanity_check_raw(m, 0);
 847
 848         return m;
 849 }
 850
 851 /* Construct the tx flags */
 852 static inline uint64_t
 853 i40e_build_ctob(uint32_t td_cmd,
 854                 uint32_t td_offset,
 855                 unsigned int size,
 856                 uint32_t td_tag)
 857 {
 858         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 859                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 860                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 861                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 862                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 863 }
 864
 865 static inline int
 866 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 867 {
 868         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 869         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 870         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 871         uint16_t nb_tx_desc = txq->nb_tx_desc;
 872         uint16_t desc_to_clean_to;
 873         uint16_t nb_tx_to_clean;
 874
 875         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 876         if (desc_to_clean_to >= nb_tx_desc)
 877                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 878
 879         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 880         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 881                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 882                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 883                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 884                         "(port=%d queue=%d)", desc_to_clean_to,
 885                                 txq->port_id, txq->queue_id);
 886                 return -1;
 887         }
 888
 889         if (last_desc_cleaned > desc_to_clean_to)
 890                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 891                                                         desc_to_clean_to);
 892         else
 893                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 894                                         last_desc_cleaned);
 895
 896         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 897
 898         txq->last_desc_cleaned = desc_to_clean_to;
 899         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 900
 901         return 0;
 902 }
 903
 904 static inline int
 905 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 906 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 907 #else
 908 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 909 #endif
 910 {
 911         int ret = 0;
 912
 913 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 914         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 915                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 916                              "rxq->rx_free_thresh=%d, "
 917                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 918                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 919                 ret = -EINVAL;
 920         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 921                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 922                              "rxq->rx_free_thresh=%d, "
 923                              "rxq->nb_rx_desc=%d",
 924                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 925                 ret = -EINVAL;
 926         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 927                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 928                              "rxq->nb_rx_desc=%d, "
 929                              "rxq->rx_free_thresh=%d",
 930                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 931                 ret = -EINVAL;
 932         } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
 933                                 RTE_PMD_I40E_RX_MAX_BURST))) {
 934                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 935                              "rxq->nb_rx_desc=%d, "
 936                              "I40E_MAX_RING_DESC=%d, "
 937                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 938                              rxq->nb_rx_desc, I40E_MAX_RING_DESC,
 939                              RTE_PMD_I40E_RX_MAX_BURST);
 940                 ret = -EINVAL;
 941         }
 942 #else
 943         ret = -EINVAL;
 944 #endif
 945
 946         return ret;
 947 }
 948
 949 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 950 #define I40E_LOOK_AHEAD 8
 951 #if (I40E_LOOK_AHEAD != 8)
 952 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 953 #endif
 954 static inline int
 955 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 956 {
 957         volatile union i40e_rx_desc *rxdp;
 958         struct i40e_rx_entry *rxep;
 959         struct rte_mbuf *mb;
 960         uint16_t pkt_len;
 961         uint64_t qword1;
 962         uint32_t rx_status;
 963         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 964         int32_t i, j, nb_rx = 0;
 965         uint64_t pkt_flags;
 966
 967         rxdp = &rxq->rx_ring[rxq->rx_tail];
 968         rxep = &rxq->sw_ring[rxq->rx_tail];
 969
 970         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 971         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 972                                 I40E_RXD_QW1_STATUS_SHIFT;
 973
 974         /* Make sure there is at least 1 packet to receive */
 975         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 976                 return 0;
 977
 978         /**
 979          * Scan LOOK_AHEAD descriptors at a time to determine which
 980          * descriptors reference packets that are ready to be received.
 981          */
 982         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 983                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 984                 /* Read desc statuses backwards to avoid race condition */
 985                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 986                         qword1 = rte_le_to_cpu_64(\
 987                                 rxdp[j].wb.qword1.status_error_len);
 988                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 989                                         I40E_RXD_QW1_STATUS_SHIFT;
 990                 }
 991
 992                 /* Compute how many status bits were set */
 993                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 994                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 995
 996                 nb_rx += nb_dd;
 997
 998                 /* Translate descriptor info to mbuf parameters */
 999                 for (j = 0; j < nb_dd; j++) {
1000                         mb = rxep[j].mbuf;
1001                         qword1 = rte_le_to_cpu_64(\
1002                                 rxdp[j].wb.qword1.status_error_len);
1003                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1004                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1005                         mb->data_len = pkt_len;
1006                         mb->pkt_len = pkt_len;
1007                         mb->ol_flags = 0;
1008                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
1009                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1010                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1011                         mb->packet_type =
1012                                 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1013                                                 I40E_RXD_QW1_PTYPE_MASK) >>
1014                                                 I40E_RXD_QW1_PTYPE_SHIFT));
1015                         if (pkt_flags & PKT_RX_RSS_HASH)
1016                                 mb->hash.rss = rte_le_to_cpu_32(\
1017                                         rxdp[j].wb.qword0.hi_dword.rss);
1018                         if (pkt_flags & PKT_RX_FDIR)
1019                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
1020
1021 #ifdef RTE_LIBRTE_IEEE1588
1022                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
1023 #endif
1024                         mb->ol_flags |= pkt_flags;
1025
1026                 }
1027
1028                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
1029                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1030
1031                 if (nb_dd != I40E_LOOK_AHEAD)
1032                         break;
1033         }
1034
1035         /* Clear software ring entries */
1036         for (i = 0; i < nb_rx; i++)
1037                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1038
1039         return nb_rx;
1040 }
1041
1042 static inline uint16_t
1043 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
1044                         struct rte_mbuf **rx_pkts,
1045                         uint16_t nb_pkts)
1046 {
1047         uint16_t i;
1048         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1049
1050         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1051
1052         for (i = 0; i < nb_pkts; i++)
1053                 rx_pkts[i] = stage[i];
1054
1055         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1056         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1057
1058         return nb_pkts;
1059 }
1060
1061 static inline int
1062 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
1063 {
1064         volatile union i40e_rx_desc *rxdp;
1065         struct i40e_rx_entry *rxep;
1066         struct rte_mbuf *mb;
1067         uint16_t alloc_idx, i;
1068         uint64_t dma_addr;
1069         int diag;
1070
1071         /* Allocate buffers in bulk */
1072         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1073                                 (rxq->rx_free_thresh - 1));
1074         rxep = &(rxq->sw_ring[alloc_idx]);
1075         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1076                                         rxq->rx_free_thresh);
1077         if (unlikely(diag != 0)) {
1078                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
1079                 return -ENOMEM;
1080         }
1081
1082         rxdp = &rxq->rx_ring[alloc_idx];
1083         for (i = 0; i < rxq->rx_free_thresh; i++) {
1084                 if (likely(i < (rxq->rx_free_thresh - 1)))
1085                         /* Prefetch next mbuf */
1086                         rte_prefetch0(rxep[i + 1].mbuf);
1087
1088                 mb = rxep[i].mbuf;
1089                 rte_mbuf_refcnt_set(mb, 1);
1090                 mb->next = NULL;
1091                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1092                 mb->nb_segs = 1;
1093                 mb->port = rxq->port_id;
1094                 dma_addr = rte_cpu_to_le_64(\
1095                         rte_mbuf_data_dma_addr_default(mb));
1096                 rxdp[i].read.hdr_addr = 0;
1097                 rxdp[i].read.pkt_addr = dma_addr;
1098         }
1099
1100         /* Update rx tail regsiter */
1101         rte_wmb();
1102         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1103
1104         rxq->rx_free_trigger =
1105                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1106         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1107                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1108
1109         return 0;
1110 }
1111
1112 static inline uint16_t
1113 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1114 {
1115         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
1116         uint16_t nb_rx = 0;
1117
1118         if (!nb_pkts)
1119                 return 0;
1120
1121         if (rxq->rx_nb_avail)
1122                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1123
1124         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
1125         rxq->rx_next_avail = 0;
1126         rxq->rx_nb_avail = nb_rx;
1127         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1128
1129         if (rxq->rx_tail > rxq->rx_free_trigger) {
1130                 if (i40e_rx_alloc_bufs(rxq) != 0) {
1131                         uint16_t i, j;
1132
1133                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1134                                    "port_id=%u, queue_id=%u",
1135                                    rxq->port_id, rxq->queue_id);
1136                         rxq->rx_nb_avail = 0;
1137                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1138                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1139                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1140
1141                         return 0;
1142                 }
1143         }
1144
1145         if (rxq->rx_tail >= rxq->nb_rx_desc)
1146                 rxq->rx_tail = 0;
1147
1148         if (rxq->rx_nb_avail)
1149                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1150
1151         return 0;
1152 }
1153
1154 static uint16_t
1155 i40e_recv_pkts_bulk_alloc(void *rx_queue,
1156                           struct rte_mbuf **rx_pkts,
1157                           uint16_t nb_pkts)
1158 {
1159         uint16_t nb_rx = 0, n, count;
1160
1161         if (unlikely(nb_pkts == 0))
1162                 return 0;
1163
1164         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
1165                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1166
1167         while (nb_pkts) {
1168                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
1169                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1170                 nb_rx = (uint16_t)(nb_rx + count);
1171                 nb_pkts = (uint16_t)(nb_pkts - count);
1172                 if (count < n)
1173                         break;
1174         }
1175
1176         return nb_rx;
1177 }
1178 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1179
1180 uint16_t
1181 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1182 {
1183         struct i40e_rx_queue *rxq;
1184         volatile union i40e_rx_desc *rx_ring;
1185         volatile union i40e_rx_desc *rxdp;
1186         union i40e_rx_desc rxd;
1187         struct i40e_rx_entry *sw_ring;
1188         struct i40e_rx_entry *rxe;
1189         struct rte_mbuf *rxm;
1190         struct rte_mbuf *nmb;
1191         uint16_t nb_rx;
1192         uint32_t rx_status;
1193         uint64_t qword1;
1194         uint16_t rx_packet_len;
1195         uint16_t rx_id, nb_hold;
1196         uint64_t dma_addr;
1197         uint64_t pkt_flags;
1198
1199         nb_rx = 0;
1200         nb_hold = 0;
1201         rxq = rx_queue;
1202         rx_id = rxq->rx_tail;
1203         rx_ring = rxq->rx_ring;
1204         sw_ring = rxq->sw_ring;
1205
1206         while (nb_rx < nb_pkts) {
1207                 rxdp = &rx_ring[rx_id];
1208                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1209                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1210                                 >> I40E_RXD_QW1_STATUS_SHIFT;
1211
1212                 /* Check the DD bit first */
1213                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1214                         break;
1215
1216                 nmb = rte_rxmbuf_alloc(rxq->mp);
1217                 if (unlikely(!nmb))
1218                         break;
1219                 rxd = *rxdp;
1220
1221                 nb_hold++;
1222                 rxe = &sw_ring[rx_id];
1223                 rx_id++;
1224                 if (unlikely(rx_id == rxq->nb_rx_desc))
1225                         rx_id = 0;
1226
1227                 /* Prefetch next mbuf */
1228                 rte_prefetch0(sw_ring[rx_id].mbuf);
1229
1230                 /**
1231                  * When next RX descriptor is on a cache line boundary,
1232                  * prefetch the next 4 RX descriptors and next 8 pointers
1233                  * to mbufs.
1234                  */
1235                 if ((rx_id & 0x3) == 0) {
1236                         rte_prefetch0(&rx_ring[rx_id]);
1237                         rte_prefetch0(&sw_ring[rx_id]);
1238                 }
1239                 rxm = rxe->mbuf;
1240                 rxe->mbuf = nmb;
1241                 dma_addr =
1242                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
1243                 rxdp->read.hdr_addr = 0;
1244                 rxdp->read.pkt_addr = dma_addr;
1245
1246                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1247                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1248
1249                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1250                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1251                 rxm->nb_segs = 1;
1252                 rxm->next = NULL;
1253                 rxm->pkt_len = rx_packet_len;
1254                 rxm->data_len = rx_packet_len;
1255                 rxm->port = rxq->port_id;
1256                 rxm->ol_flags = 0;
1257                 i40e_rxd_to_vlan_tci(rxm, &rxd);
1258                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1259                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1260                 rxm->packet_type =
1261                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1262                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1263                 if (pkt_flags & PKT_RX_RSS_HASH)
1264                         rxm->hash.rss =
1265                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1266                 if (pkt_flags & PKT_RX_FDIR)
1267                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1268
1269 #ifdef RTE_LIBRTE_IEEE1588
1270                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
1271 #endif
1272                 rxm->ol_flags |= pkt_flags;
1273
1274                 rx_pkts[nb_rx++] = rxm;
1275         }
1276         rxq->rx_tail = rx_id;
1277
1278         /**
1279          * If the number of free RX descriptors is greater than the RX free
1280          * threshold of the queue, advance the receive tail register of queue.
1281          * Update that register with the value of the last processed RX
1282          * descriptor minus 1.
1283          */
1284         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1285         if (nb_hold > rxq->rx_free_thresh) {
1286                 rx_id = (uint16_t) ((rx_id == 0) ?
1287                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1288                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1289                 nb_hold = 0;
1290         }
1291         rxq->nb_rx_hold = nb_hold;
1292
1293         return nb_rx;
1294 }
1295
1296 uint16_t
1297 i40e_recv_scattered_pkts(void *rx_queue,
1298                          struct rte_mbuf **rx_pkts,
1299                          uint16_t nb_pkts)
1300 {
1301         struct i40e_rx_queue *rxq = rx_queue;
1302         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
1303         volatile union i40e_rx_desc *rxdp;
1304         union i40e_rx_desc rxd;
1305         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
1306         struct i40e_rx_entry *rxe;
1307         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1308         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1309         struct rte_mbuf *nmb, *rxm;
1310         uint16_t rx_id = rxq->rx_tail;
1311         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1312         uint32_t rx_status;
1313         uint64_t qword1;
1314         uint64_t dma_addr;
1315         uint64_t pkt_flags;
1316
1317         while (nb_rx < nb_pkts) {
1318                 rxdp = &rx_ring[rx_id];
1319                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1320                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1321                                         I40E_RXD_QW1_STATUS_SHIFT;
1322
1323                 /* Check the DD bit */
1324                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1325                         break;
1326
1327                 nmb = rte_rxmbuf_alloc(rxq->mp);
1328                 if (unlikely(!nmb))
1329                         break;
1330                 rxd = *rxdp;
1331                 nb_hold++;
1332                 rxe = &sw_ring[rx_id];
1333                 rx_id++;
1334                 if (rx_id == rxq->nb_rx_desc)
1335                         rx_id = 0;
1336
1337                 /* Prefetch next mbuf */
1338                 rte_prefetch0(sw_ring[rx_id].mbuf);
1339
1340                 /**
1341                  * When next RX descriptor is on a cache line boundary,
1342                  * prefetch the next 4 RX descriptors and next 8 pointers
1343                  * to mbufs.
1344                  */
1345                 if ((rx_id & 0x3) == 0) {
1346                         rte_prefetch0(&rx_ring[rx_id]);
1347                         rte_prefetch0(&sw_ring[rx_id]);
1348                 }
1349
1350                 rxm = rxe->mbuf;
1351                 rxe->mbuf = nmb;
1352                 dma_addr =
1353                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
1354
1355                 /* Set data buffer address and data length of the mbuf */
1356                 rxdp->read.hdr_addr = 0;
1357                 rxdp->read.pkt_addr = dma_addr;
1358                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1359                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1360                 rxm->data_len = rx_packet_len;
1361                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1362
1363                 /**
1364                  * If this is the first buffer of the received packet, set the
1365                  * pointer to the first mbuf of the packet and initialize its
1366                  * context. Otherwise, update the total length and the number
1367                  * of segments of the current scattered packet, and update the
1368                  * pointer to the last mbuf of the current packet.
1369                  */
1370                 if (!first_seg) {
1371                         first_seg = rxm;
1372                         first_seg->nb_segs = 1;
1373                         first_seg->pkt_len = rx_packet_len;
1374                 } else {
1375                         first_seg->pkt_len =
1376                                 (uint16_t)(first_seg->pkt_len +
1377                                                 rx_packet_len);
1378                         first_seg->nb_segs++;
1379                         last_seg->next = rxm;
1380                 }
1381
1382                 /**
1383                  * If this is not the last buffer of the received packet,
1384                  * update the pointer to the last mbuf of the current scattered
1385                  * packet and continue to parse the RX ring.
1386                  */
1387                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1388                         last_seg = rxm;
1389                         continue;
1390                 }
1391
1392                 /**
1393                  * This is the last buffer of the received packet. If the CRC
1394                  * is not stripped by the hardware:
1395                  *  - Subtract the CRC length from the total packet length.
1396                  *  - If the last buffer only contains the whole CRC or a part
1397                  *  of it, free the mbuf associated to the last buffer. If part
1398                  *  of the CRC is also contained in the previous mbuf, subtract
1399                  *  the length of that CRC part from the data length of the
1400                  *  previous mbuf.
1401                  */
1402                 rxm->next = NULL;
1403                 if (unlikely(rxq->crc_len > 0)) {
1404                         first_seg->pkt_len -= ETHER_CRC_LEN;
1405                         if (rx_packet_len <= ETHER_CRC_LEN) {
1406                                 rte_pktmbuf_free_seg(rxm);
1407                                 first_seg->nb_segs--;
1408                                 last_seg->data_len =
1409                                         (uint16_t)(last_seg->data_len -
1410                                         (ETHER_CRC_LEN - rx_packet_len));
1411                                 last_seg->next = NULL;
1412                         } else
1413                                 rxm->data_len = (uint16_t)(rx_packet_len -
1414                                                                 ETHER_CRC_LEN);
1415                 }
1416
1417                 first_seg->port = rxq->port_id;
1418                 first_seg->ol_flags = 0;
1419                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
1420                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1421                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1422                 first_seg->packet_type =
1423                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1424                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1425                 if (pkt_flags & PKT_RX_RSS_HASH)
1426                         rxm->hash.rss =
1427                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1428                 if (pkt_flags & PKT_RX_FDIR)
1429                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1430
1431 #ifdef RTE_LIBRTE_IEEE1588
1432                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
1433 #endif
1434                 first_seg->ol_flags |= pkt_flags;
1435
1436                 /* Prefetch data of first segment, if configured to do so. */
1437                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1438                         first_seg->data_off));
1439                 rx_pkts[nb_rx++] = first_seg;
1440                 first_seg = NULL;
1441         }
1442
1443         /* Record index of the next RX descriptor to probe. */
1444         rxq->rx_tail = rx_id;
1445         rxq->pkt_first_seg = first_seg;
1446         rxq->pkt_last_seg = last_seg;
1447
1448         /**
1449          * If the number of free RX descriptors is greater than the RX free
1450          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1451          * register. Update the RDT with the value of the last processed RX
1452          * descriptor minus 1, to guarantee that the RDT register is never
1453          * equal to the RDH register, which creates a "full" ring situtation
1454          * from the hardware point of view.
1455          */
1456         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1457         if (nb_hold > rxq->rx_free_thresh) {
1458                 rx_id = (uint16_t)(rx_id == 0 ?
1459                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1460                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1461                 nb_hold = 0;
1462         }
1463         rxq->nb_rx_hold = nb_hold;
1464
1465         return nb_rx;
1466 }
1467
1468 /* Check if the context descriptor is needed for TX offloading */
1469 static inline uint16_t
1470 i40e_calc_context_desc(uint64_t flags)
1471 {
1472         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
1473                 PKT_TX_TCP_SEG |
1474                 PKT_TX_QINQ_PKT;
1475
1476 #ifdef RTE_LIBRTE_IEEE1588
1477         mask |= PKT_TX_IEEE1588_TMST;
1478 #endif
1479
1480         return (flags & mask) ? 1 : 0;
1481 }
1482
1483 /* set i40e TSO context descriptor */
1484 static inline uint64_t
1485 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1486 {
1487         uint64_t ctx_desc = 0;
1488         uint32_t cd_cmd, hdr_len, cd_tso_len;
1489
1490         if (!tx_offload.l4_len) {
1491                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1492                 return ctx_desc;
1493         }
1494
1495         /**
1496          * in case of tunneling packet, the outer_l2_len and
1497          * outer_l3_len must be 0.
1498          */
1499         hdr_len = tx_offload.outer_l2_len +
1500                 tx_offload.outer_l3_len +
1501                 tx_offload.l2_len +
1502                 tx_offload.l3_len +
1503                 tx_offload.l4_len;
1504
1505         cd_cmd = I40E_TX_CTX_DESC_TSO;
1506         cd_tso_len = mbuf->pkt_len - hdr_len;
1507         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1508                 ((uint64_t)cd_tso_len <<
1509                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1510                 ((uint64_t)mbuf->tso_segsz <<
1511                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1512
1513         return ctx_desc;
1514 }
1515
1516 uint16_t
1517 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1518 {
1519         struct i40e_tx_queue *txq;
1520         struct i40e_tx_entry *sw_ring;
1521         struct i40e_tx_entry *txe, *txn;
1522         volatile struct i40e_tx_desc *txd;
1523         volatile struct i40e_tx_desc *txr;
1524         struct rte_mbuf *tx_pkt;
1525         struct rte_mbuf *m_seg;
1526         uint32_t cd_tunneling_params;
1527         uint16_t tx_id;
1528         uint16_t nb_tx;
1529         uint32_t td_cmd;
1530         uint32_t td_offset;
1531         uint32_t tx_flags;
1532         uint32_t td_tag;
1533         uint64_t ol_flags;
1534         uint16_t nb_used;
1535         uint16_t nb_ctx;
1536         uint16_t tx_last;
1537         uint16_t slen;
1538         uint64_t buf_dma_addr;
1539         union i40e_tx_offload tx_offload = {0};
1540
1541         txq = tx_queue;
1542         sw_ring = txq->sw_ring;
1543         txr = txq->tx_ring;
1544         tx_id = txq->tx_tail;
1545         txe = &sw_ring[tx_id];
1546
1547         /* Check if the descriptor ring needs to be cleaned. */
1548         if (txq->nb_tx_free < txq->tx_free_thresh)
1549                 i40e_xmit_cleanup(txq);
1550
1551         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1552                 td_cmd = 0;
1553                 td_tag = 0;
1554                 td_offset = 0;
1555                 tx_flags = 0;
1556
1557                 tx_pkt = *tx_pkts++;
1558                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1559
1560                 ol_flags = tx_pkt->ol_flags;
1561                 tx_offload.l2_len = tx_pkt->l2_len;
1562                 tx_offload.l3_len = tx_pkt->l3_len;
1563                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1564                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1565                 tx_offload.l4_len = tx_pkt->l4_len;
1566                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1567
1568                 /* Calculate the number of context descriptors needed. */
1569                 nb_ctx = i40e_calc_context_desc(ol_flags);
1570
1571                 /**
1572                  * The number of descriptors that must be allocated for
1573                  * a packet equals to the number of the segments of that
1574                  * packet plus 1 context descriptor if needed.
1575                  */
1576                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1577                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1578
1579                 /* Circular ring */
1580                 if (tx_last >= txq->nb_tx_desc)
1581                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1582
1583                 if (nb_used > txq->nb_tx_free) {
1584                         if (i40e_xmit_cleanup(txq) != 0) {
1585                                 if (nb_tx == 0)
1586                                         return 0;
1587                                 goto end_of_tx;
1588                         }
1589                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1590                                 while (nb_used > txq->nb_tx_free) {
1591                                         if (i40e_xmit_cleanup(txq) != 0) {
1592                                                 if (nb_tx == 0)
1593                                                         return 0;
1594                                                 goto end_of_tx;
1595                                         }
1596                                 }
1597                         }
1598                 }
1599
1600                 /* Descriptor based VLAN insertion */
1601                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1602                         tx_flags |= tx_pkt->vlan_tci <<
1603                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1604                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1605                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1606                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1607                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1608                 }
1609
1610                 /* Always enable CRC offload insertion */
1611                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1612
1613                 /* Enable checksum offloading */
1614                 cd_tunneling_params = 0;
1615                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK) {
1616                         i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1617                                 tx_offload, &cd_tunneling_params);
1618                 }
1619
1620                 if (nb_ctx) {
1621                         /* Setup TX context descriptor if required */
1622                         volatile struct i40e_tx_context_desc *ctx_txd =
1623                                 (volatile struct i40e_tx_context_desc *)\
1624                                                         &txr[tx_id];
1625                         uint16_t cd_l2tag2 = 0;
1626                         uint64_t cd_type_cmd_tso_mss =
1627                                 I40E_TX_DESC_DTYPE_CONTEXT;
1628
1629                         txn = &sw_ring[txe->next_id];
1630                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1631                         if (txe->mbuf != NULL) {
1632                                 rte_pktmbuf_free_seg(txe->mbuf);
1633                                 txe->mbuf = NULL;
1634                         }
1635
1636                         /* TSO enabled means no timestamp */
1637                         if (ol_flags & PKT_TX_TCP_SEG)
1638                                 cd_type_cmd_tso_mss |=
1639                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1640                         else {
1641 #ifdef RTE_LIBRTE_IEEE1588
1642                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1643                                         cd_type_cmd_tso_mss |=
1644                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1645                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1646 #endif
1647                         }
1648
1649                         ctx_txd->tunneling_params =
1650                                 rte_cpu_to_le_32(cd_tunneling_params);
1651                         if (ol_flags & PKT_TX_QINQ_PKT) {
1652                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1653                                 cd_type_cmd_tso_mss |=
1654                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1655                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1656                         }
1657                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1658                         ctx_txd->type_cmd_tso_mss =
1659                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1660
1661                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1662                                 "tunneling_params: %#x;\n"
1663                                 "l2tag2: %#hx;\n"
1664                                 "rsvd: %#hx;\n"
1665                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1666                                 tx_pkt, tx_id,
1667                                 ctx_txd->tunneling_params,
1668                                 ctx_txd->l2tag2,
1669                                 ctx_txd->rsvd,
1670                                 ctx_txd->type_cmd_tso_mss);
1671
1672                         txe->last_id = tx_last;
1673                         tx_id = txe->next_id;
1674                         txe = txn;
1675                 }
1676
1677                 m_seg = tx_pkt;
1678                 do {
1679                         txd = &txr[tx_id];
1680                         txn = &sw_ring[txe->next_id];
1681
1682                         if (txe->mbuf)
1683                                 rte_pktmbuf_free_seg(txe->mbuf);
1684                         txe->mbuf = m_seg;
1685
1686                         /* Setup TX Descriptor */
1687                         slen = m_seg->data_len;
1688                         buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1689
1690                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1691                                 "buf_dma_addr: %#"PRIx64";\n"
1692                                 "td_cmd: %#x;\n"
1693                                 "td_offset: %#x;\n"
1694                                 "td_len: %u;\n"
1695                                 "td_tag: %#x;\n",
1696                                 tx_pkt, tx_id, buf_dma_addr,
1697                                 td_cmd, td_offset, slen, td_tag);
1698
1699                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1700                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1701                                                 td_offset, slen, td_tag);
1702                         txe->last_id = tx_last;
1703                         tx_id = txe->next_id;
1704                         txe = txn;
1705                         m_seg = m_seg->next;
1706                 } while (m_seg != NULL);
1707
1708                 /* The last packet data descriptor needs End Of Packet (EOP) */
1709                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1710                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1711                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1712
1713                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1714                         PMD_TX_FREE_LOG(DEBUG,
1715                                         "Setting RS bit on TXD id="
1716                                         "%4u (port=%d queue=%d)",
1717                                         tx_last, txq->port_id, txq->queue_id);
1718
1719                         td_cmd |= I40E_TX_DESC_CMD_RS;
1720
1721                         /* Update txq RS bit counters */
1722                         txq->nb_tx_used = 0;
1723                 }
1724
1725                 txd->cmd_type_offset_bsz |=
1726                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1727                                         I40E_TXD_QW1_CMD_SHIFT);
1728         }
1729
1730 end_of_tx:
1731         rte_wmb();
1732
1733         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1734                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1735                    (unsigned) tx_id, (unsigned) nb_tx);
1736
1737         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1738         txq->tx_tail = tx_id;
1739
1740         return nb_tx;
1741 }
1742
1743 static inline int __attribute__((always_inline))
1744 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1745 {
1746         struct i40e_tx_entry *txep;
1747         uint16_t i;
1748
1749         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1750                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1751                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1752                 return 0;
1753
1754         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1755
1756         for (i = 0; i < txq->tx_rs_thresh; i++)
1757                 rte_prefetch0((txep + i)->mbuf);
1758
1759         if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1760                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1761                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1762                         txep->mbuf = NULL;
1763                 }
1764         } else {
1765                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1766                         rte_pktmbuf_free_seg(txep->mbuf);
1767                         txep->mbuf = NULL;
1768                 }
1769         }
1770
1771         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1772         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1773         if (txq->tx_next_dd >= txq->nb_tx_desc)
1774                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1775
1776         return txq->tx_rs_thresh;
1777 }
1778
1779 /* Populate 4 descriptors with data from 4 mbufs */
1780 static inline void
1781 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1782 {
1783         uint64_t dma_addr;
1784         uint32_t i;
1785
1786         for (i = 0; i < 4; i++, txdp++, pkts++) {
1787                 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1788                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1789                 txdp->cmd_type_offset_bsz =
1790                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1791                                         (*pkts)->data_len, 0);
1792         }
1793 }
1794
1795 /* Populate 1 descriptor with data from 1 mbuf */
1796 static inline void
1797 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1798 {
1799         uint64_t dma_addr;
1800
1801         dma_addr = rte_mbuf_data_dma_addr(*pkts);
1802         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1803         txdp->cmd_type_offset_bsz =
1804                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1805                                 (*pkts)->data_len, 0);
1806 }
1807
1808 /* Fill hardware descriptor ring with mbuf data */
1809 static inline void
1810 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1811                      struct rte_mbuf **pkts,
1812                      uint16_t nb_pkts)
1813 {
1814         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1815         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1816         const int N_PER_LOOP = 4;
1817         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1818         int mainpart, leftover;
1819         int i, j;
1820
1821         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1822         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1823         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1824                 for (j = 0; j < N_PER_LOOP; ++j) {
1825                         (txep + i + j)->mbuf = *(pkts + i + j);
1826                 }
1827                 tx4(txdp + i, pkts + i);
1828         }
1829         if (unlikely(leftover > 0)) {
1830                 for (i = 0; i < leftover; ++i) {
1831                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1832                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1833                 }
1834         }
1835 }
1836
1837 static inline uint16_t
1838 tx_xmit_pkts(struct i40e_tx_queue *txq,
1839              struct rte_mbuf **tx_pkts,
1840              uint16_t nb_pkts)
1841 {
1842         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1843         uint16_t n = 0;
1844
1845         /**
1846          * Begin scanning the H/W ring for done descriptors when the number
1847          * of available descriptors drops below tx_free_thresh. For each done
1848          * descriptor, free the associated buffer.
1849          */
1850         if (txq->nb_tx_free < txq->tx_free_thresh)
1851                 i40e_tx_free_bufs(txq);
1852
1853         /* Use available descriptor only */
1854         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1855         if (unlikely(!nb_pkts))
1856                 return 0;
1857
1858         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1859         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1860                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1861                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1862                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1863                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1864                                                 I40E_TXD_QW1_CMD_SHIFT);
1865                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1866                 txq->tx_tail = 0;
1867         }
1868
1869         /* Fill hardware descriptor ring with mbuf data */
1870         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1871         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1872
1873         /* Determin if RS bit needs to be set */
1874         if (txq->tx_tail > txq->tx_next_rs) {
1875                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1876                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1877                                                 I40E_TXD_QW1_CMD_SHIFT);
1878                 txq->tx_next_rs =
1879                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1880                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1881                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1882         }
1883
1884         if (txq->tx_tail >= txq->nb_tx_desc)
1885                 txq->tx_tail = 0;
1886
1887         /* Update the tx tail register */
1888         rte_wmb();
1889         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1890
1891         return nb_pkts;
1892 }
1893
1894 static uint16_t
1895 i40e_xmit_pkts_simple(void *tx_queue,
1896                       struct rte_mbuf **tx_pkts,
1897                       uint16_t nb_pkts)
1898 {
1899         uint16_t nb_tx = 0;
1900
1901         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1902                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1903                                                 tx_pkts, nb_pkts);
1904
1905         while (nb_pkts) {
1906                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1907                                                 I40E_TX_MAX_BURST);
1908
1909                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1910                                                 &tx_pkts[nb_tx], num);
1911                 nb_tx = (uint16_t)(nb_tx + ret);
1912                 nb_pkts = (uint16_t)(nb_pkts - ret);
1913                 if (ret < num)
1914                         break;
1915         }
1916
1917         return nb_tx;
1918 }
1919
1920 /*
1921  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1922  * application used, which assume having sequential ones. But from driver's
1923  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1924  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1925  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1926  * use queue_idx from 0 to 95 to access queues, while real queue would be
1927  * different. This function will do a queue mapping to find VSI the queue
1928  * belongs to.
1929  */
1930 static struct i40e_vsi*
1931 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1932 {
1933         /* the queue in MAIN VSI range */
1934         if (queue_idx < pf->main_vsi->nb_qps)
1935                 return pf->main_vsi;
1936
1937         queue_idx -= pf->main_vsi->nb_qps;
1938
1939         /* queue_idx is greater than VMDQ VSIs range */
1940         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1941                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1942                 return NULL;
1943         }
1944
1945         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1946 }
1947
1948 static uint16_t
1949 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1950 {
1951         /* the queue in MAIN VSI range */
1952         if (queue_idx < pf->main_vsi->nb_qps)
1953                 return queue_idx;
1954
1955         /* It's VMDQ queues */
1956         queue_idx -= pf->main_vsi->nb_qps;
1957
1958         if (pf->nb_cfg_vmdq_vsi)
1959                 return queue_idx % pf->vmdq_nb_qps;
1960         else {
1961                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1962                 return (uint16_t)(-1);
1963         }
1964 }
1965
1966 int
1967 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1968 {
1969         struct i40e_rx_queue *rxq;
1970         int err = -1;
1971         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1972
1973         PMD_INIT_FUNC_TRACE();
1974
1975         if (rx_queue_id < dev->data->nb_rx_queues) {
1976                 rxq = dev->data->rx_queues[rx_queue_id];
1977
1978                 err = i40e_alloc_rx_queue_mbufs(rxq);
1979                 if (err) {
1980                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1981                         return err;
1982                 }
1983
1984                 rte_wmb();
1985
1986                 /* Init the RX tail regieter. */
1987                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1988
1989                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1990
1991                 if (err) {
1992                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1993                                     rx_queue_id);
1994
1995                         i40e_rx_queue_release_mbufs(rxq);
1996                         i40e_reset_rx_queue(rxq);
1997                 } else
1998                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1999         }
2000
2001         return err;
2002 }
2003
2004 int
2005 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2006 {
2007         struct i40e_rx_queue *rxq;
2008         int err;
2009         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2010
2011         if (rx_queue_id < dev->data->nb_rx_queues) {
2012                 rxq = dev->data->rx_queues[rx_queue_id];
2013
2014                 /*
2015                 * rx_queue_id is queue id aplication refers to, while
2016                 * rxq->reg_idx is the real queue index.
2017                 */
2018                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
2019
2020                 if (err) {
2021                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
2022                                     rx_queue_id);
2023                         return err;
2024                 }
2025                 i40e_rx_queue_release_mbufs(rxq);
2026                 i40e_reset_rx_queue(rxq);
2027                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2028         }
2029
2030         return 0;
2031 }
2032
2033 int
2034 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2035 {
2036         int err = -1;
2037         struct i40e_tx_queue *txq;
2038         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2039
2040         PMD_INIT_FUNC_TRACE();
2041
2042         if (tx_queue_id < dev->data->nb_tx_queues) {
2043                 txq = dev->data->tx_queues[tx_queue_id];
2044
2045                 /*
2046                 * tx_queue_id is queue id aplication refers to, while
2047                 * rxq->reg_idx is the real queue index.
2048                 */
2049                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
2050                 if (err)
2051                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
2052                                     tx_queue_id);
2053                 else
2054                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2055         }
2056
2057         return err;
2058 }
2059
2060 int
2061 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2062 {
2063         struct i40e_tx_queue *txq;
2064         int err;
2065         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2066
2067         if (tx_queue_id < dev->data->nb_tx_queues) {
2068                 txq = dev->data->tx_queues[tx_queue_id];
2069
2070                 /*
2071                 * tx_queue_id is queue id aplication refers to, while
2072                 * txq->reg_idx is the real queue index.
2073                 */
2074                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
2075
2076                 if (err) {
2077                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
2078                                     tx_queue_id);
2079                         return err;
2080                 }
2081
2082                 i40e_tx_queue_release_mbufs(txq);
2083                 i40e_reset_tx_queue(txq);
2084                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2085         }
2086
2087         return 0;
2088 }
2089
2090 int
2091 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
2092                         uint16_t queue_idx,
2093                         uint16_t nb_desc,
2094                         unsigned int socket_id,
2095                         const struct rte_eth_rxconf *rx_conf,
2096                         struct rte_mempool *mp)
2097 {
2098         struct i40e_vsi *vsi;
2099         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2101         struct i40e_adapter *ad =
2102                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2103         struct i40e_rx_queue *rxq;
2104         const struct rte_memzone *rz;
2105         uint32_t ring_size;
2106         uint16_t len, i;
2107         uint16_t base, bsf, tc_mapping;
2108         int use_def_burst_func = 1;
2109
2110         if (hw->mac.type == I40E_MAC_VF) {
2111                 struct i40e_vf *vf =
2112                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2113                 vsi = &vf->vsi;
2114         } else
2115                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2116
2117         if (vsi == NULL) {
2118                 PMD_DRV_LOG(ERR, "VSI not available or queue "
2119                             "index exceeds the maximum");
2120                 return I40E_ERR_PARAM;
2121         }
2122         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2123                         (nb_desc > I40E_MAX_RING_DESC) ||
2124                         (nb_desc < I40E_MIN_RING_DESC)) {
2125                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
2126                             "invalid", nb_desc);
2127                 return I40E_ERR_PARAM;
2128         }
2129
2130         /* Free memory if needed */
2131         if (dev->data->rx_queues[queue_idx]) {
2132                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
2133                 dev->data->rx_queues[queue_idx] = NULL;
2134         }
2135
2136         /* Allocate the rx queue data structure */
2137         rxq = rte_zmalloc_socket("i40e rx queue",
2138                                  sizeof(struct i40e_rx_queue),
2139                                  RTE_CACHE_LINE_SIZE,
2140                                  socket_id);
2141         if (!rxq) {
2142                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2143                             "rx queue data structure");
2144                 return -ENOMEM;
2145         }
2146         rxq->mp = mp;
2147         rxq->nb_rx_desc = nb_desc;
2148         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2149         rxq->queue_id = queue_idx;
2150         if (hw->mac.type == I40E_MAC_VF)
2151                 rxq->reg_idx = queue_idx;
2152         else /* PF device */
2153                 rxq->reg_idx = vsi->base_queue +
2154                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2155
2156         rxq->port_id = dev->data->port_id;
2157         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2158                                                         0 : ETHER_CRC_LEN);
2159         rxq->drop_en = rx_conf->rx_drop_en;
2160         rxq->vsi = vsi;
2161         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2162
2163         /* Allocate the maximun number of RX ring hardware descriptor. */
2164         ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
2165         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2166         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2167                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2168         if (!rz) {
2169                 i40e_dev_rx_queue_release(rxq);
2170                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2171                 return -ENOMEM;
2172         }
2173
2174         /* Zero all the descriptors in the ring. */
2175         memset(rz->addr, 0, ring_size);
2176
2177         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2178         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2179
2180 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2181         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2182 #else
2183         len = nb_desc;
2184 #endif
2185
2186         /* Allocate the software ring. */
2187         rxq->sw_ring =
2188                 rte_zmalloc_socket("i40e rx sw ring",
2189                                    sizeof(struct i40e_rx_entry) * len,
2190                                    RTE_CACHE_LINE_SIZE,
2191                                    socket_id);
2192         if (!rxq->sw_ring) {
2193                 i40e_dev_rx_queue_release(rxq);
2194                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2195                 return -ENOMEM;
2196         }
2197
2198         i40e_reset_rx_queue(rxq);
2199         rxq->q_set = TRUE;
2200         dev->data->rx_queues[queue_idx] = rxq;
2201
2202         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2203
2204         if (!use_def_burst_func) {
2205 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2206                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2207                              "satisfied. Rx Burst Bulk Alloc function will be "
2208                              "used on port=%d, queue=%d.",
2209                              rxq->port_id, rxq->queue_id);
2210 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2211         } else {
2212                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2213                              "not satisfied, Scattered Rx is requested, "
2214                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2215                              "not enabled on port=%d, queue=%d.",
2216                              rxq->port_id, rxq->queue_id);
2217                 ad->rx_bulk_alloc_allowed = false;
2218         }
2219
2220         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2221                 if (!(vsi->enabled_tc & (1 << i)))
2222                         continue;
2223                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2224                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2225                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2226                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2227                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2228
2229                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2230                         rxq->dcb_tc = i;
2231         }
2232
2233         return 0;
2234 }
2235
2236 void
2237 i40e_dev_rx_queue_release(void *rxq)
2238 {
2239         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2240
2241         if (!q) {
2242                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2243                 return;
2244         }
2245
2246         i40e_rx_queue_release_mbufs(q);
2247         rte_free(q->sw_ring);
2248         rte_free(q);
2249 }
2250
2251 uint32_t
2252 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2253 {
2254 #define I40E_RXQ_SCAN_INTERVAL 4
2255         volatile union i40e_rx_desc *rxdp;
2256         struct i40e_rx_queue *rxq;
2257         uint16_t desc = 0;
2258
2259         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
2260                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
2261                 return 0;
2262         }
2263
2264         rxq = dev->data->rx_queues[rx_queue_id];
2265         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2266         while ((desc < rxq->nb_rx_desc) &&
2267                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2268                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2269                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2270                 /**
2271                  * Check the DD bit of a rx descriptor of each 4 in a group,
2272                  * to avoid checking too frequently and downgrading performance
2273                  * too much.
2274                  */
2275                 desc += I40E_RXQ_SCAN_INTERVAL;
2276                 rxdp += I40E_RXQ_SCAN_INTERVAL;
2277                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2278                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2279                                         desc - rxq->nb_rx_desc]);
2280         }
2281
2282         return desc;
2283 }
2284
2285 int
2286 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2287 {
2288         volatile union i40e_rx_desc *rxdp;
2289         struct i40e_rx_queue *rxq = rx_queue;
2290         uint16_t desc;
2291         int ret;
2292
2293         if (unlikely(offset >= rxq->nb_rx_desc)) {
2294                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
2295                 return 0;
2296         }
2297
2298         desc = rxq->rx_tail + offset;
2299         if (desc >= rxq->nb_rx_desc)
2300                 desc -= rxq->nb_rx_desc;
2301
2302         rxdp = &(rxq->rx_ring[desc]);
2303
2304         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2305                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2306                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2307
2308         return ret;
2309 }
2310
2311 int
2312 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2313                         uint16_t queue_idx,
2314                         uint16_t nb_desc,
2315                         unsigned int socket_id,
2316                         const struct rte_eth_txconf *tx_conf)
2317 {
2318         struct i40e_vsi *vsi;
2319         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2320         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2321         struct i40e_tx_queue *txq;
2322         const struct rte_memzone *tz;
2323         uint32_t ring_size;
2324         uint16_t tx_rs_thresh, tx_free_thresh;
2325         uint16_t i, base, bsf, tc_mapping;
2326
2327         if (hw->mac.type == I40E_MAC_VF) {
2328                 struct i40e_vf *vf =
2329                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2330                 vsi = &vf->vsi;
2331         } else
2332                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2333
2334         if (vsi == NULL) {
2335                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2336                             "exceeds the maximum", queue_idx);
2337                 return I40E_ERR_PARAM;
2338         }
2339
2340         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2341                         (nb_desc > I40E_MAX_RING_DESC) ||
2342                         (nb_desc < I40E_MIN_RING_DESC)) {
2343                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2344                             "invalid", nb_desc);
2345                 return I40E_ERR_PARAM;
2346         }
2347
2348         /**
2349          * The following two parameters control the setting of the RS bit on
2350          * transmit descriptors. TX descriptors will have their RS bit set
2351          * after txq->tx_rs_thresh descriptors have been used. The TX
2352          * descriptor ring will be cleaned after txq->tx_free_thresh
2353          * descriptors are used or if the number of descriptors required to
2354          * transmit a packet is greater than the number of free TX descriptors.
2355          *
2356          * The following constraints must be satisfied:
2357          *  - tx_rs_thresh must be greater than 0.
2358          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2359          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2360          *  - tx_rs_thresh must be a divisor of the ring size.
2361          *  - tx_free_thresh must be greater than 0.
2362          *  - tx_free_thresh must be less than the size of the ring minus 3.
2363          *
2364          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2365          * race condition, hence the maximum threshold constraints. When set
2366          * to zero use default values.
2367          */
2368         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2369                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2370         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2371                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2372         if (tx_rs_thresh >= (nb_desc - 2)) {
2373                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2374                              "number of TX descriptors minus 2. "
2375                              "(tx_rs_thresh=%u port=%d queue=%d)",
2376                              (unsigned int)tx_rs_thresh,
2377                              (int)dev->data->port_id,
2378                              (int)queue_idx);
2379                 return I40E_ERR_PARAM;
2380         }
2381         if (tx_free_thresh >= (nb_desc - 3)) {
2382                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2383                              "tx_free_thresh must be less than the "
2384                              "number of TX descriptors minus 3. "
2385                              "(tx_free_thresh=%u port=%d queue=%d)",
2386                              (unsigned int)tx_free_thresh,
2387                              (int)dev->data->port_id,
2388                              (int)queue_idx);
2389                 return I40E_ERR_PARAM;
2390         }
2391         if (tx_rs_thresh > tx_free_thresh) {
2392                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2393                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2394                              " tx_rs_thresh=%u port=%d queue=%d)",
2395                              (unsigned int)tx_free_thresh,
2396                              (unsigned int)tx_rs_thresh,
2397                              (int)dev->data->port_id,
2398                              (int)queue_idx);
2399                 return I40E_ERR_PARAM;
2400         }
2401         if ((nb_desc % tx_rs_thresh) != 0) {
2402                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2403                              "number of TX descriptors. (tx_rs_thresh=%u"
2404                              " port=%d queue=%d)",
2405                              (unsigned int)tx_rs_thresh,
2406                              (int)dev->data->port_id,
2407                              (int)queue_idx);
2408                 return I40E_ERR_PARAM;
2409         }
2410         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2411                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2412                              "tx_rs_thresh is greater than 1. "
2413                              "(tx_rs_thresh=%u port=%d queue=%d)",
2414                              (unsigned int)tx_rs_thresh,
2415                              (int)dev->data->port_id,
2416                              (int)queue_idx);
2417                 return I40E_ERR_PARAM;
2418         }
2419
2420         /* Free memory if needed. */
2421         if (dev->data->tx_queues[queue_idx]) {
2422                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2423                 dev->data->tx_queues[queue_idx] = NULL;
2424         }
2425
2426         /* Allocate the TX queue data structure. */
2427         txq = rte_zmalloc_socket("i40e tx queue",
2428                                   sizeof(struct i40e_tx_queue),
2429                                   RTE_CACHE_LINE_SIZE,
2430                                   socket_id);
2431         if (!txq) {
2432                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2433                             "tx queue structure");
2434                 return -ENOMEM;
2435         }
2436
2437         /* Allocate TX hardware ring descriptors. */
2438         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2439         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2440         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2441                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2442         if (!tz) {
2443                 i40e_dev_tx_queue_release(txq);
2444                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2445                 return -ENOMEM;
2446         }
2447
2448         txq->nb_tx_desc = nb_desc;
2449         txq->tx_rs_thresh = tx_rs_thresh;
2450         txq->tx_free_thresh = tx_free_thresh;
2451         txq->pthresh = tx_conf->tx_thresh.pthresh;
2452         txq->hthresh = tx_conf->tx_thresh.hthresh;
2453         txq->wthresh = tx_conf->tx_thresh.wthresh;
2454         txq->queue_id = queue_idx;
2455         if (hw->mac.type == I40E_MAC_VF)
2456                 txq->reg_idx = queue_idx;
2457         else /* PF device */
2458                 txq->reg_idx = vsi->base_queue +
2459                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2460
2461         txq->port_id = dev->data->port_id;
2462         txq->txq_flags = tx_conf->txq_flags;
2463         txq->vsi = vsi;
2464         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2465
2466         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2467         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2468
2469         /* Allocate software ring */
2470         txq->sw_ring =
2471                 rte_zmalloc_socket("i40e tx sw ring",
2472                                    sizeof(struct i40e_tx_entry) * nb_desc,
2473                                    RTE_CACHE_LINE_SIZE,
2474                                    socket_id);
2475         if (!txq->sw_ring) {
2476                 i40e_dev_tx_queue_release(txq);
2477                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2478                 return -ENOMEM;
2479         }
2480
2481         i40e_reset_tx_queue(txq);
2482         txq->q_set = TRUE;
2483         dev->data->tx_queues[queue_idx] = txq;
2484
2485         /* Use a simple TX queue without offloads or multi segs if possible */
2486         i40e_set_tx_function_flag(dev, txq);
2487
2488         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2489                 if (!(vsi->enabled_tc & (1 << i)))
2490                         continue;
2491                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2492                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2493                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2494                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2495                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2496
2497                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2498                         txq->dcb_tc = i;
2499         }
2500
2501         return 0;
2502 }
2503
2504 void
2505 i40e_dev_tx_queue_release(void *txq)
2506 {
2507         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2508
2509         if (!q) {
2510                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2511                 return;
2512         }
2513
2514         i40e_tx_queue_release_mbufs(q);
2515         rte_free(q->sw_ring);
2516         rte_free(q);
2517 }
2518
2519 const struct rte_memzone *
2520 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2521 {
2522         const struct rte_memzone *mz;
2523
2524         mz = rte_memzone_lookup(name);
2525         if (mz)
2526                 return mz;
2527
2528         if (rte_xen_dom0_supported())
2529                 mz = rte_memzone_reserve_bounded(name, len,
2530                                 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2531         else
2532                 mz = rte_memzone_reserve_aligned(name, len,
2533                                 socket_id, 0, I40E_RING_BASE_ALIGN);
2534         return mz;
2535 }
2536
2537 void
2538 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2539 {
2540         uint16_t i;
2541
2542         /* SSE Vector driver has a different way of releasing mbufs. */
2543         if (rxq->rx_using_sse) {
2544                 i40e_rx_queue_release_mbufs_vec(rxq);
2545                 return;
2546         }
2547
2548         if (!rxq || !rxq->sw_ring) {
2549                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2550                 return;
2551         }
2552
2553         for (i = 0; i < rxq->nb_rx_desc; i++) {
2554                 if (rxq->sw_ring[i].mbuf) {
2555                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2556                         rxq->sw_ring[i].mbuf = NULL;
2557                 }
2558         }
2559 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2560         if (rxq->rx_nb_avail == 0)
2561                 return;
2562         for (i = 0; i < rxq->rx_nb_avail; i++) {
2563                 struct rte_mbuf *mbuf;
2564
2565                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2566                 rte_pktmbuf_free_seg(mbuf);
2567         }
2568         rxq->rx_nb_avail = 0;
2569 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2570 }
2571
2572 void
2573 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2574 {
2575         unsigned i;
2576         uint16_t len;
2577
2578         if (!rxq) {
2579                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2580                 return;
2581         }
2582
2583 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2584         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2585                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2586         else
2587 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2588                 len = rxq->nb_rx_desc;
2589
2590         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2591                 ((volatile char *)rxq->rx_ring)[i] = 0;
2592
2593 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2594         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2595         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2596                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2597
2598         rxq->rx_nb_avail = 0;
2599         rxq->rx_next_avail = 0;
2600         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2601 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2602         rxq->rx_tail = 0;
2603         rxq->nb_rx_hold = 0;
2604         rxq->pkt_first_seg = NULL;
2605         rxq->pkt_last_seg = NULL;
2606
2607         rxq->rxrearm_start = 0;
2608         rxq->rxrearm_nb = 0;
2609 }
2610
2611 void
2612 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2613 {
2614         uint16_t i;
2615
2616         if (!txq || !txq->sw_ring) {
2617                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2618                 return;
2619         }
2620
2621         for (i = 0; i < txq->nb_tx_desc; i++) {
2622                 if (txq->sw_ring[i].mbuf) {
2623                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2624                         txq->sw_ring[i].mbuf = NULL;
2625                 }
2626         }
2627 }
2628
2629 void
2630 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2631 {
2632         struct i40e_tx_entry *txe;
2633         uint16_t i, prev, size;
2634
2635         if (!txq) {
2636                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2637                 return;
2638         }
2639
2640         txe = txq->sw_ring;
2641         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2642         for (i = 0; i < size; i++)
2643                 ((volatile char *)txq->tx_ring)[i] = 0;
2644
2645         prev = (uint16_t)(txq->nb_tx_desc - 1);
2646         for (i = 0; i < txq->nb_tx_desc; i++) {
2647                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2648
2649                 txd->cmd_type_offset_bsz =
2650                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2651                 txe[i].mbuf =  NULL;
2652                 txe[i].last_id = i;
2653                 txe[prev].next_id = i;
2654                 prev = i;
2655         }
2656
2657         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2658         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2659
2660         txq->tx_tail = 0;
2661         txq->nb_tx_used = 0;
2662
2663         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2664         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2665 }
2666
2667 /* Init the TX queue in hardware */
2668 int
2669 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2670 {
2671         enum i40e_status_code err = I40E_SUCCESS;
2672         struct i40e_vsi *vsi = txq->vsi;
2673         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2674         uint16_t pf_q = txq->reg_idx;
2675         struct i40e_hmc_obj_txq tx_ctx;
2676         uint32_t qtx_ctl;
2677
2678         /* clear the context structure first */
2679         memset(&tx_ctx, 0, sizeof(tx_ctx));
2680         tx_ctx.new_context = 1;
2681         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2682         tx_ctx.qlen = txq->nb_tx_desc;
2683
2684 #ifdef RTE_LIBRTE_IEEE1588
2685         tx_ctx.timesync_ena = 1;
2686 #endif
2687         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2688         if (vsi->type == I40E_VSI_FDIR)
2689                 tx_ctx.fd_ena = TRUE;
2690
2691         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2692         if (err != I40E_SUCCESS) {
2693                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2694                 return err;
2695         }
2696
2697         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2698         if (err != I40E_SUCCESS) {
2699                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2700                 return err;
2701         }
2702
2703         /* Now associate this queue with this PCI function */
2704         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2705         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2706                                         I40E_QTX_CTL_PF_INDX_MASK);
2707         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2708         I40E_WRITE_FLUSH(hw);
2709
2710         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2711
2712         return err;
2713 }
2714
2715 int
2716 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2717 {
2718         struct i40e_rx_entry *rxe = rxq->sw_ring;
2719         uint64_t dma_addr;
2720         uint16_t i;
2721
2722         for (i = 0; i < rxq->nb_rx_desc; i++) {
2723                 volatile union i40e_rx_desc *rxd;
2724                 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2725
2726                 if (unlikely(!mbuf)) {
2727                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2728                         return -ENOMEM;
2729                 }
2730
2731                 rte_mbuf_refcnt_set(mbuf, 1);
2732                 mbuf->next = NULL;
2733                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2734                 mbuf->nb_segs = 1;
2735                 mbuf->port = rxq->port_id;
2736
2737                 dma_addr =
2738                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2739
2740                 rxd = &rxq->rx_ring[i];
2741                 rxd->read.pkt_addr = dma_addr;
2742                 rxd->read.hdr_addr = 0;
2743 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2744                 rxd->read.rsvd1 = 0;
2745                 rxd->read.rsvd2 = 0;
2746 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2747
2748                 rxe[i].mbuf = mbuf;
2749         }
2750
2751         return 0;
2752 }
2753
2754 /*
2755  * Calculate the buffer length, and check the jumbo frame
2756  * and maximum packet length.
2757  */
2758 static int
2759 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2760 {
2761         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2762         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2763         struct rte_eth_dev_data *data = pf->dev_data;
2764         uint16_t buf_size, len;
2765
2766         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2767                 RTE_PKTMBUF_HEADROOM);
2768
2769         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2770                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2771         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2772                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2773                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2774                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2775                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2776                 rxq->hs_mode = i40e_header_split_enabled;
2777                 break;
2778         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2779         default:
2780                 rxq->rx_hdr_len = 0;
2781                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2782                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2783                 rxq->hs_mode = i40e_header_split_none;
2784                 break;
2785         }
2786
2787         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2788         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2789         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2790                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2791                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2792                         PMD_DRV_LOG(ERR, "maximum packet length must "
2793                                     "be larger than %u and smaller than %u,"
2794                                     "as jumbo frame is enabled",
2795                                     (uint32_t)ETHER_MAX_LEN,
2796                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2797                         return I40E_ERR_CONFIG;
2798                 }
2799         } else {
2800                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2801                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2802                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2803                                     "larger than %u and smaller than %u, "
2804                                     "as jumbo frame is disabled",
2805                                     (uint32_t)ETHER_MIN_LEN,
2806                                     (uint32_t)ETHER_MAX_LEN);
2807                         return I40E_ERR_CONFIG;
2808                 }
2809         }
2810
2811         return 0;
2812 }
2813
2814 /* Init the RX queue in hardware */
2815 int
2816 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2817 {
2818         int err = I40E_SUCCESS;
2819         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2820         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2821         uint16_t pf_q = rxq->reg_idx;
2822         uint16_t buf_size;
2823         struct i40e_hmc_obj_rxq rx_ctx;
2824
2825         err = i40e_rx_queue_config(rxq);
2826         if (err < 0) {
2827                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2828                 return err;
2829         }
2830
2831         /* Clear the context structure first */
2832         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2833         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2834         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2835
2836         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2837         rx_ctx.qlen = rxq->nb_rx_desc;
2838 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2839         rx_ctx.dsize = 1;
2840 #endif
2841         rx_ctx.dtype = rxq->hs_mode;
2842         if (rxq->hs_mode)
2843                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2844         else
2845                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2846         rx_ctx.rxmax = rxq->max_pkt_len;
2847         rx_ctx.tphrdesc_ena = 1;
2848         rx_ctx.tphwdesc_ena = 1;
2849         rx_ctx.tphdata_ena = 1;
2850         rx_ctx.tphhead_ena = 1;
2851         rx_ctx.lrxqthresh = 2;
2852         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2853         rx_ctx.l2tsel = 1;
2854         rx_ctx.showiv = 1;
2855         rx_ctx.prefena = 1;
2856
2857         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2858         if (err != I40E_SUCCESS) {
2859                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2860                 return err;
2861         }
2862         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2863         if (err != I40E_SUCCESS) {
2864                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2865                 return err;
2866         }
2867
2868         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2869
2870         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2871                 RTE_PKTMBUF_HEADROOM);
2872
2873         /* Check if scattered RX needs to be used. */
2874         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2875                 dev_data->scattered_rx = 1;
2876         }
2877
2878         /* Init the RX tail regieter. */
2879         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2880
2881         return 0;
2882 }
2883
2884 void
2885 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2886 {
2887         uint16_t i;
2888
2889         PMD_INIT_FUNC_TRACE();
2890
2891         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2892                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2893                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2894         }
2895
2896         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2897                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2898                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2899         }
2900 }
2901
2902 void
2903 i40e_dev_free_queues(struct rte_eth_dev *dev)
2904 {
2905         uint16_t i;
2906
2907         PMD_INIT_FUNC_TRACE();
2908
2909         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2910                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2911                 dev->data->rx_queues[i] = NULL;
2912         }
2913         dev->data->nb_rx_queues = 0;
2914
2915         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2916                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2917                 dev->data->tx_queues[i] = NULL;
2918         }
2919         dev->data->nb_tx_queues = 0;
2920 }
2921
2922 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2923 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2924
2925 enum i40e_status_code
2926 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2927 {
2928         struct i40e_tx_queue *txq;
2929         const struct rte_memzone *tz = NULL;
2930         uint32_t ring_size;
2931         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2932
2933         if (!pf) {
2934                 PMD_DRV_LOG(ERR, "PF is not available");
2935                 return I40E_ERR_BAD_PTR;
2936         }
2937
2938         /* Allocate the TX queue data structure. */
2939         txq = rte_zmalloc_socket("i40e fdir tx queue",
2940                                   sizeof(struct i40e_tx_queue),
2941                                   RTE_CACHE_LINE_SIZE,
2942                                   SOCKET_ID_ANY);
2943         if (!txq) {
2944                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2945                                         "tx queue structure.");
2946                 return I40E_ERR_NO_MEMORY;
2947         }
2948
2949         /* Allocate TX hardware ring descriptors. */
2950         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2951         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2952
2953         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2954                                       I40E_FDIR_QUEUE_ID, ring_size,
2955                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2956         if (!tz) {
2957                 i40e_dev_tx_queue_release(txq);
2958                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2959                 return I40E_ERR_NO_MEMORY;
2960         }
2961
2962         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2963         txq->queue_id = I40E_FDIR_QUEUE_ID;
2964         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2965         txq->vsi = pf->fdir.fdir_vsi;
2966
2967         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2968         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2969         /*
2970          * don't need to allocate software ring and reset for the fdir
2971          * program queue just set the queue has been configured.
2972          */
2973         txq->q_set = TRUE;
2974         pf->fdir.txq = txq;
2975
2976         return I40E_SUCCESS;
2977 }
2978
2979 enum i40e_status_code
2980 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2981 {
2982         struct i40e_rx_queue *rxq;
2983         const struct rte_memzone *rz = NULL;
2984         uint32_t ring_size;
2985         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2986
2987         if (!pf) {
2988                 PMD_DRV_LOG(ERR, "PF is not available");
2989                 return I40E_ERR_BAD_PTR;
2990         }
2991
2992         /* Allocate the RX queue data structure. */
2993         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2994                                   sizeof(struct i40e_rx_queue),
2995                                   RTE_CACHE_LINE_SIZE,
2996                                   SOCKET_ID_ANY);
2997         if (!rxq) {
2998                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2999                                         "rx queue structure.");
3000                 return I40E_ERR_NO_MEMORY;
3001         }
3002
3003         /* Allocate RX hardware ring descriptors. */
3004         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3005         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3006
3007         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3008                                       I40E_FDIR_QUEUE_ID, ring_size,
3009                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3010         if (!rz) {
3011                 i40e_dev_rx_queue_release(rxq);
3012                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3013                 return I40E_ERR_NO_MEMORY;
3014         }
3015
3016         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3017         rxq->queue_id = I40E_FDIR_QUEUE_ID;
3018         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3019         rxq->vsi = pf->fdir.fdir_vsi;
3020
3021         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
3022         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3023
3024         /*
3025          * Don't need to allocate software ring and reset for the fdir
3026          * rx queue, just set the queue has been configured.
3027          */
3028         rxq->q_set = TRUE;
3029         pf->fdir.rxq = rxq;
3030
3031         return I40E_SUCCESS;
3032 }
3033
3034 void
3035 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3036         struct rte_eth_rxq_info *qinfo)
3037 {
3038         struct i40e_rx_queue *rxq;
3039
3040         rxq = dev->data->rx_queues[queue_id];
3041
3042         qinfo->mp = rxq->mp;
3043         qinfo->scattered_rx = dev->data->scattered_rx;
3044         qinfo->nb_desc = rxq->nb_rx_desc;
3045
3046         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3047         qinfo->conf.rx_drop_en = rxq->drop_en;
3048         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3049 }
3050
3051 void
3052 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3053         struct rte_eth_txq_info *qinfo)
3054 {
3055         struct i40e_tx_queue *txq;
3056
3057         txq = dev->data->tx_queues[queue_id];
3058
3059         qinfo->nb_desc = txq->nb_tx_desc;
3060
3061         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3062         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3063         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3064
3065         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3066         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3067         qinfo->conf.txq_flags = txq->txq_flags;
3068         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3069 }
3070
3071 void __attribute__((cold))
3072 i40e_set_rx_function(struct rte_eth_dev *dev)
3073 {
3074         struct i40e_adapter *ad =
3075                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3076         uint16_t rx_using_sse, i;
3077         /* In order to allow Vector Rx there are a few configuration
3078          * conditions to be met and Rx Bulk Allocation should be allowed.
3079          */
3080         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3081                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3082                     !ad->rx_bulk_alloc_allowed) {
3083                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3084                                      " Vector Rx preconditions",
3085                                      dev->data->port_id);
3086
3087                         ad->rx_vec_allowed = false;
3088                 }
3089                 if (ad->rx_vec_allowed) {
3090                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3091                                 struct i40e_rx_queue *rxq =
3092                                         dev->data->rx_queues[i];
3093
3094                                 if (i40e_rxq_vec_setup(rxq)) {
3095                                         ad->rx_vec_allowed = false;
3096                                         break;
3097                                 }
3098                         }
3099                 }
3100         }
3101
3102         if (dev->data->scattered_rx) {
3103                 /* Set the non-LRO scattered callback: there are Vector and
3104                  * single allocation versions.
3105                  */
3106                 if (ad->rx_vec_allowed) {
3107                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
3108                                             "callback (port=%d).",
3109                                      dev->data->port_id);
3110
3111                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3112                 } else {
3113                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
3114                                            "allocation callback (port=%d).",
3115                                      dev->data->port_id);
3116                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
3117                 }
3118         /* If parameters allow we are going to choose between the following
3119          * callbacks:
3120          *    - Vector
3121          *    - Bulk Allocation
3122          *    - Single buffer allocation (the simplest one)
3123          */
3124         } else if (ad->rx_vec_allowed) {
3125                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
3126                                     "burst size no less than %d (port=%d).",
3127                              RTE_I40E_DESCS_PER_LOOP,
3128                              dev->data->port_id);
3129
3130                 dev->rx_pkt_burst = i40e_recv_pkts_vec;
3131         } else if (ad->rx_bulk_alloc_allowed) {
3132                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3133                                     "satisfied. Rx Burst Bulk Alloc function "
3134                                     "will be used on port=%d.",
3135                              dev->data->port_id);
3136
3137                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3138         } else {
3139                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
3140                                     "satisfied, or Scattered Rx is requested "
3141                                     "(port=%d).",
3142                              dev->data->port_id);
3143
3144                 dev->rx_pkt_burst = i40e_recv_pkts;
3145         }
3146
3147         /* Propagate information about RX function choice through all queues. */
3148         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3149                 rx_using_sse =
3150                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3151                          dev->rx_pkt_burst == i40e_recv_pkts_vec);
3152
3153                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3154                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3155
3156                         rxq->rx_using_sse = rx_using_sse;
3157                 }
3158         }
3159 }
3160
3161 void __attribute__((cold))
3162 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3163 {
3164         struct i40e_adapter *ad =
3165                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3166
3167         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
3168         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
3169                         && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
3170                 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
3171                         PMD_INIT_LOG(DEBUG, "Vector tx"
3172                                      " can be enabled on this txq.");
3173
3174                 } else {
3175                         ad->tx_vec_allowed = false;
3176                 }
3177         } else {
3178                 ad->tx_simple_allowed = false;
3179         }
3180 }
3181
3182 void __attribute__((cold))
3183 i40e_set_tx_function(struct rte_eth_dev *dev)
3184 {
3185         struct i40e_adapter *ad =
3186                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3187         int i;
3188
3189         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3190                 if (ad->tx_vec_allowed) {
3191                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3192                                 struct i40e_tx_queue *txq =
3193                                         dev->data->tx_queues[i];
3194
3195                                 if (i40e_txq_vec_setup(txq)) {
3196                                         ad->tx_vec_allowed = false;
3197                                         break;
3198                                 }
3199                         }
3200                 }
3201         }
3202
3203         if (ad->tx_simple_allowed) {
3204                 if (ad->tx_vec_allowed) {
3205                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3206                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3207                 } else {
3208                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3209                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3210                 }
3211         } else {
3212                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3213                 dev->tx_pkt_burst = i40e_xmit_pkts;
3214         }
3215 }
3216
3217 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
3218 int __attribute__((weak))
3219 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3220 {
3221         return -1;
3222 }
3223
3224 uint16_t __attribute__((weak))
3225 i40e_recv_pkts_vec(
3226         void __rte_unused *rx_queue,
3227         struct rte_mbuf __rte_unused **rx_pkts,
3228         uint16_t __rte_unused nb_pkts)
3229 {
3230         return 0;
3231 }
3232
3233 uint16_t __attribute__((weak))
3234 i40e_recv_scattered_pkts_vec(
3235         void __rte_unused *rx_queue,
3236         struct rte_mbuf __rte_unused **rx_pkts,
3237         uint16_t __rte_unused nb_pkts)
3238 {
3239         return 0;
3240 }
3241
3242 int __attribute__((weak))
3243 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3244 {
3245         return -1;
3246 }
3247
3248 int __attribute__((weak))
3249 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3250 {
3251         return -1;
3252 }
3253
3254 void __attribute__((weak))
3255 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3256 {
3257         return;
3258 }
3259
3260 uint16_t __attribute__((weak))
3261 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
3262                    struct rte_mbuf __rte_unused **tx_pkts,
3263                    uint16_t __rte_unused nb_pkts)
3264 {
3265         return 0;
3266 }