drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59
  60 #define DEFAULT_TX_RS_THRESH   32
  61 #define DEFAULT_TX_FREE_THRESH 32
  62 #define I40E_MAX_PKT_TYPE      256
  63
  64 #define I40E_TX_MAX_BURST  32
  65
  66 #define I40E_DMA_MEM_ALIGN 4096
  67
  68 /* Base address of the HW descriptor ring should be 128B aligned. */
  69 #define I40E_RING_BASE_ALIGN    128
  70
  71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  72                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  73
  74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  75
  76 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  77                 PKT_TX_IP_CKSUM |                \
  78                 PKT_TX_L4_MASK |                 \
  79                 PKT_TX_TCP_SEG |                 \
  80                 PKT_TX_OUTER_IP_CKSUM)
  81
  82 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  83                                       struct rte_mbuf **tx_pkts,
  84                                       uint16_t nb_pkts);
  85
  86 static inline void
  87 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  88 {
  89         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
  90                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
  91                 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
  92                 mb->vlan_tci =
  93                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
  94                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
  95                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
  96         } else {
  97                 mb->vlan_tci = 0;
  98         }
  99 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 100         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 101                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 102                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
 103                 mb->vlan_tci_outer = mb->vlan_tci;
 104                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 105                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 106                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 107                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 108         } else {
 109                 mb->vlan_tci_outer = 0;
 110         }
 111 #endif
 112         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 113                    mb->vlan_tci, mb->vlan_tci_outer);
 114 }
 115
 116 /* Translate the rx descriptor status to pkt flags */
 117 static inline uint64_t
 118 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 119 {
 120         uint64_t flags;
 121
 122         /* Check if RSS_HASH */
 123         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 124                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 125                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 126
 127         /* Check if FDIR Match */
 128         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 129                                                         PKT_RX_FDIR : 0);
 130
 131         return flags;
 132 }
 133
 134 static inline uint64_t
 135 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 136 {
 137         uint64_t flags = 0;
 138         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 139
 140 #define I40E_RX_ERR_BITS 0x3f
 141         if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
 142                 return flags;
 143         /* If RXE bit set, all other status bits are meaningless */
 144         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
 145                 flags |= PKT_RX_MAC_ERR;
 146                 return flags;
 147         }
 148
 149         /* If RECIPE bit set, all other status indications should be ignored */
 150         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
 151                 flags |= PKT_RX_RECIP_ERR;
 152                 return flags;
 153         }
 154         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
 155                 flags |= PKT_RX_HBUF_OVERFLOW;
 156         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 157                 flags |= PKT_RX_IP_CKSUM_BAD;
 158         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 159                 flags |= PKT_RX_L4_CKSUM_BAD;
 160         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 161                 flags |= PKT_RX_EIP_CKSUM_BAD;
 162         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
 163                 flags |= PKT_RX_OVERSIZE;
 164
 165         return flags;
 166 }
 167
 168 /* Function to check and set the ieee1588 timesync index and get the
 169  * appropriate flags.
 170  */
 171 #ifdef RTE_LIBRTE_IEEE1588
 172 static inline uint64_t
 173 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 174 {
 175         uint64_t pkt_flags = 0;
 176         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 177                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 178                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 179
 180         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 181                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 182                 pkt_flags = PKT_RX_IEEE1588_PTP;
 183         if (tsyn & 0x04) {
 184                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 185                 mb->timesync = tsyn & 0x03;
 186         }
 187
 188         return pkt_flags;
 189 }
 190 #endif
 191
 192 /* For each value it means, datasheet of hardware can tell more details
 193  *
 194  * @note: fix i40e_dev_supported_ptypes_get() if any change here.
 195  */
 196 static inline uint32_t
 197 i40e_rxd_pkt_type_mapping(uint8_t ptype)
 198 {
 199         static const uint32_t type_table[UINT8_MAX + 1] __rte_cache_aligned = {
 200                 /* L2 types */
 201                 /* [0] reserved */
 202                 [1] = RTE_PTYPE_L2_ETHER,
 203                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
 204                 /* [3] - [5] reserved */
 205                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
 206                 /* [7] - [10] reserved */
 207                 [11] = RTE_PTYPE_L2_ETHER_ARP,
 208                 /* [12] - [21] reserved */
 209
 210                 /* Non tunneled IPv4 */
 211                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 212                         RTE_PTYPE_L4_FRAG,
 213                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 214                         RTE_PTYPE_L4_NONFRAG,
 215                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 216                         RTE_PTYPE_L4_UDP,
 217                 /* [25] reserved */
 218                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 219                         RTE_PTYPE_L4_TCP,
 220                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 221                         RTE_PTYPE_L4_SCTP,
 222                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 223                         RTE_PTYPE_L4_ICMP,
 224
 225                 /* IPv4 --> IPv4 */
 226                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 227                         RTE_PTYPE_TUNNEL_IP |
 228                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 229                         RTE_PTYPE_INNER_L4_FRAG,
 230                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 231                         RTE_PTYPE_TUNNEL_IP |
 232                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 233                         RTE_PTYPE_INNER_L4_NONFRAG,
 234                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 235                         RTE_PTYPE_TUNNEL_IP |
 236                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 237                         RTE_PTYPE_INNER_L4_UDP,
 238                 /* [32] reserved */
 239                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 240                         RTE_PTYPE_TUNNEL_IP |
 241                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 242                         RTE_PTYPE_INNER_L4_TCP,
 243                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 244                         RTE_PTYPE_TUNNEL_IP |
 245                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 246                         RTE_PTYPE_INNER_L4_SCTP,
 247                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 248                         RTE_PTYPE_TUNNEL_IP |
 249                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 250                         RTE_PTYPE_INNER_L4_ICMP,
 251
 252                 /* IPv4 --> IPv6 */
 253                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 254                         RTE_PTYPE_TUNNEL_IP |
 255                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 256                         RTE_PTYPE_INNER_L4_FRAG,
 257                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 258                         RTE_PTYPE_TUNNEL_IP |
 259                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 260                         RTE_PTYPE_INNER_L4_NONFRAG,
 261                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 262                         RTE_PTYPE_TUNNEL_IP |
 263                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 264                         RTE_PTYPE_INNER_L4_UDP,
 265                 /* [39] reserved */
 266                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 267                         RTE_PTYPE_TUNNEL_IP |
 268                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 269                         RTE_PTYPE_INNER_L4_TCP,
 270                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 271                         RTE_PTYPE_TUNNEL_IP |
 272                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 273                         RTE_PTYPE_INNER_L4_SCTP,
 274                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 275                         RTE_PTYPE_TUNNEL_IP |
 276                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 277                         RTE_PTYPE_INNER_L4_ICMP,
 278
 279                 /* IPv4 --> GRE/Teredo/VXLAN */
 280                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 281                         RTE_PTYPE_TUNNEL_GRENAT,
 282
 283                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
 284                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 285                         RTE_PTYPE_TUNNEL_GRENAT |
 286                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 287                         RTE_PTYPE_INNER_L4_FRAG,
 288                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 289                         RTE_PTYPE_TUNNEL_GRENAT |
 290                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 291                         RTE_PTYPE_INNER_L4_NONFRAG,
 292                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 293                         RTE_PTYPE_TUNNEL_GRENAT |
 294                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 295                         RTE_PTYPE_INNER_L4_UDP,
 296                 /* [47] reserved */
 297                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 298                         RTE_PTYPE_TUNNEL_GRENAT |
 299                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 300                         RTE_PTYPE_INNER_L4_TCP,
 301                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 302                         RTE_PTYPE_TUNNEL_GRENAT |
 303                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 304                         RTE_PTYPE_INNER_L4_SCTP,
 305                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 306                         RTE_PTYPE_TUNNEL_GRENAT |
 307                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 308                         RTE_PTYPE_INNER_L4_ICMP,
 309
 310                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
 311                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 312                         RTE_PTYPE_TUNNEL_GRENAT |
 313                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 314                         RTE_PTYPE_INNER_L4_FRAG,
 315                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 316                         RTE_PTYPE_TUNNEL_GRENAT |
 317                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 318                         RTE_PTYPE_INNER_L4_NONFRAG,
 319                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 320                         RTE_PTYPE_TUNNEL_GRENAT |
 321                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 322                         RTE_PTYPE_INNER_L4_UDP,
 323                 /* [54] reserved */
 324                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 325                         RTE_PTYPE_TUNNEL_GRENAT |
 326                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 327                         RTE_PTYPE_INNER_L4_TCP,
 328                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 329                         RTE_PTYPE_TUNNEL_GRENAT |
 330                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 331                         RTE_PTYPE_INNER_L4_SCTP,
 332                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 333                         RTE_PTYPE_TUNNEL_GRENAT |
 334                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 335                         RTE_PTYPE_INNER_L4_ICMP,
 336
 337                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
 338                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 339                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
 340
 341                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
 342                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 343                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 344                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 345                         RTE_PTYPE_INNER_L4_FRAG,
 346                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 347                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 348                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 349                         RTE_PTYPE_INNER_L4_NONFRAG,
 350                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 351                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 352                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 353                         RTE_PTYPE_INNER_L4_UDP,
 354                 /* [62] reserved */
 355                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 356                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 357                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 358                         RTE_PTYPE_INNER_L4_TCP,
 359                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 360                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 361                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 362                         RTE_PTYPE_INNER_L4_SCTP,
 363                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 364                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 365                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 366                         RTE_PTYPE_INNER_L4_ICMP,
 367
 368                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
 369                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 370                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 371                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 372                         RTE_PTYPE_INNER_L4_FRAG,
 373                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 374                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 375                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 376                         RTE_PTYPE_INNER_L4_NONFRAG,
 377                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 378                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 379                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 380                         RTE_PTYPE_INNER_L4_UDP,
 381                 /* [69] reserved */
 382                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 383                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 384                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 385                         RTE_PTYPE_INNER_L4_TCP,
 386                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 387                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 388                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 389                         RTE_PTYPE_INNER_L4_SCTP,
 390                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 391                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 392                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 393                         RTE_PTYPE_INNER_L4_ICMP,
 394
 395                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
 396                 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 397                         RTE_PTYPE_TUNNEL_GRENAT |
 398                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
 399
 400                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
 401                 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 402                         RTE_PTYPE_TUNNEL_GRENAT |
 403                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 404                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 405                         RTE_PTYPE_INNER_L4_FRAG,
 406                 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 407                         RTE_PTYPE_TUNNEL_GRENAT |
 408                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 409                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 410                         RTE_PTYPE_INNER_L4_NONFRAG,
 411                 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 412                         RTE_PTYPE_TUNNEL_GRENAT |
 413                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 414                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 415                         RTE_PTYPE_INNER_L4_UDP,
 416                 /* [77] reserved */
 417                 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 418                         RTE_PTYPE_TUNNEL_GRENAT |
 419                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 420                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 421                         RTE_PTYPE_INNER_L4_TCP,
 422                 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 423                         RTE_PTYPE_TUNNEL_GRENAT |
 424                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 425                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 426                         RTE_PTYPE_INNER_L4_SCTP,
 427                 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 428                         RTE_PTYPE_TUNNEL_GRENAT |
 429                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 430                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 431                         RTE_PTYPE_INNER_L4_ICMP,
 432
 433                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
 434                 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 435                         RTE_PTYPE_TUNNEL_GRENAT |
 436                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 437                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 438                         RTE_PTYPE_INNER_L4_FRAG,
 439                 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 440                         RTE_PTYPE_TUNNEL_GRENAT |
 441                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 442                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 443                         RTE_PTYPE_INNER_L4_NONFRAG,
 444                 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 445                         RTE_PTYPE_TUNNEL_GRENAT |
 446                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 447                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 448                         RTE_PTYPE_INNER_L4_UDP,
 449                 /* [84] reserved */
 450                 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 451                         RTE_PTYPE_TUNNEL_GRENAT |
 452                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 453                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 454                         RTE_PTYPE_INNER_L4_TCP,
 455                 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 456                         RTE_PTYPE_TUNNEL_GRENAT |
 457                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 458                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 459                         RTE_PTYPE_INNER_L4_SCTP,
 460                 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 461                         RTE_PTYPE_TUNNEL_GRENAT |
 462                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 463                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 464                         RTE_PTYPE_INNER_L4_ICMP,
 465
 466                 /* Non tunneled IPv6 */
 467                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 468                         RTE_PTYPE_L4_FRAG,
 469                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 470                         RTE_PTYPE_L4_NONFRAG,
 471                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 472                         RTE_PTYPE_L4_UDP,
 473                 /* [91] reserved */
 474                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 475                         RTE_PTYPE_L4_TCP,
 476                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 477                         RTE_PTYPE_L4_SCTP,
 478                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 479                         RTE_PTYPE_L4_ICMP,
 480
 481                 /* IPv6 --> IPv4 */
 482                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 483                         RTE_PTYPE_TUNNEL_IP |
 484                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 485                         RTE_PTYPE_INNER_L4_FRAG,
 486                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 487                         RTE_PTYPE_TUNNEL_IP |
 488                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 489                         RTE_PTYPE_INNER_L4_NONFRAG,
 490                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 491                         RTE_PTYPE_TUNNEL_IP |
 492                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 493                         RTE_PTYPE_INNER_L4_UDP,
 494                 /* [98] reserved */
 495                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 496                         RTE_PTYPE_TUNNEL_IP |
 497                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 498                         RTE_PTYPE_INNER_L4_TCP,
 499                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 500                         RTE_PTYPE_TUNNEL_IP |
 501                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 502                         RTE_PTYPE_INNER_L4_SCTP,
 503                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 504                         RTE_PTYPE_TUNNEL_IP |
 505                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 506                         RTE_PTYPE_INNER_L4_ICMP,
 507
 508                 /* IPv6 --> IPv6 */
 509                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 510                         RTE_PTYPE_TUNNEL_IP |
 511                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 512                         RTE_PTYPE_INNER_L4_FRAG,
 513                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 514                         RTE_PTYPE_TUNNEL_IP |
 515                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 516                         RTE_PTYPE_INNER_L4_NONFRAG,
 517                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 518                         RTE_PTYPE_TUNNEL_IP |
 519                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 520                         RTE_PTYPE_INNER_L4_UDP,
 521                 /* [105] reserved */
 522                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 523                         RTE_PTYPE_TUNNEL_IP |
 524                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 525                         RTE_PTYPE_INNER_L4_TCP,
 526                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 527                         RTE_PTYPE_TUNNEL_IP |
 528                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 529                         RTE_PTYPE_INNER_L4_SCTP,
 530                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 531                         RTE_PTYPE_TUNNEL_IP |
 532                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 533                         RTE_PTYPE_INNER_L4_ICMP,
 534
 535                 /* IPv6 --> GRE/Teredo/VXLAN */
 536                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 537                         RTE_PTYPE_TUNNEL_GRENAT,
 538
 539                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
 540                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 541                         RTE_PTYPE_TUNNEL_GRENAT |
 542                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 543                         RTE_PTYPE_INNER_L4_FRAG,
 544                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 545                         RTE_PTYPE_TUNNEL_GRENAT |
 546                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 547                         RTE_PTYPE_INNER_L4_NONFRAG,
 548                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 549                         RTE_PTYPE_TUNNEL_GRENAT |
 550                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 551                         RTE_PTYPE_INNER_L4_UDP,
 552                 /* [113] reserved */
 553                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 554                         RTE_PTYPE_TUNNEL_GRENAT |
 555                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 556                         RTE_PTYPE_INNER_L4_TCP,
 557                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 558                         RTE_PTYPE_TUNNEL_GRENAT |
 559                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 560                         RTE_PTYPE_INNER_L4_SCTP,
 561                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 562                         RTE_PTYPE_TUNNEL_GRENAT |
 563                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 564                         RTE_PTYPE_INNER_L4_ICMP,
 565
 566                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
 567                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 568                         RTE_PTYPE_TUNNEL_GRENAT |
 569                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 570                         RTE_PTYPE_INNER_L4_FRAG,
 571                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 572                         RTE_PTYPE_TUNNEL_GRENAT |
 573                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 574                         RTE_PTYPE_INNER_L4_NONFRAG,
 575                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 576                         RTE_PTYPE_TUNNEL_GRENAT |
 577                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 578                         RTE_PTYPE_INNER_L4_UDP,
 579                 /* [120] reserved */
 580                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 581                         RTE_PTYPE_TUNNEL_GRENAT |
 582                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 583                         RTE_PTYPE_INNER_L4_TCP,
 584                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 585                         RTE_PTYPE_TUNNEL_GRENAT |
 586                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 587                         RTE_PTYPE_INNER_L4_SCTP,
 588                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 589                         RTE_PTYPE_TUNNEL_GRENAT |
 590                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 591                         RTE_PTYPE_INNER_L4_ICMP,
 592
 593                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
 594                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 595                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
 596
 597                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
 598                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 599                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 600                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 601                         RTE_PTYPE_INNER_L4_FRAG,
 602                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 603                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 604                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 605                         RTE_PTYPE_INNER_L4_NONFRAG,
 606                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 607                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 608                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 609                         RTE_PTYPE_INNER_L4_UDP,
 610                 /* [128] reserved */
 611                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 612                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 613                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 614                         RTE_PTYPE_INNER_L4_TCP,
 615                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 616                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 617                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 618                         RTE_PTYPE_INNER_L4_SCTP,
 619                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 620                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 621                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 622                         RTE_PTYPE_INNER_L4_ICMP,
 623
 624                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
 625                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 626                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 627                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 628                         RTE_PTYPE_INNER_L4_FRAG,
 629                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 630                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 631                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 632                         RTE_PTYPE_INNER_L4_NONFRAG,
 633                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 634                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 635                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 636                         RTE_PTYPE_INNER_L4_UDP,
 637                 /* [135] reserved */
 638                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 639                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 640                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 641                         RTE_PTYPE_INNER_L4_TCP,
 642                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 643                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 644                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 645                         RTE_PTYPE_INNER_L4_SCTP,
 646                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 647                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 648                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 649                         RTE_PTYPE_INNER_L4_ICMP,
 650
 651                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
 652                 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 653                         RTE_PTYPE_TUNNEL_GRENAT |
 654                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
 655
 656                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
 657                 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 658                         RTE_PTYPE_TUNNEL_GRENAT |
 659                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 660                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 661                         RTE_PTYPE_INNER_L4_FRAG,
 662                 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 663                         RTE_PTYPE_TUNNEL_GRENAT |
 664                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 665                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 666                         RTE_PTYPE_INNER_L4_NONFRAG,
 667                 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 668                         RTE_PTYPE_TUNNEL_GRENAT |
 669                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 670                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 671                         RTE_PTYPE_INNER_L4_UDP,
 672                 /* [143] reserved */
 673                 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 674                         RTE_PTYPE_TUNNEL_GRENAT |
 675                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 676                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 677                         RTE_PTYPE_INNER_L4_TCP,
 678                 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 679                         RTE_PTYPE_TUNNEL_GRENAT |
 680                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 681                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 682                         RTE_PTYPE_INNER_L4_SCTP,
 683                 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 684                         RTE_PTYPE_TUNNEL_GRENAT |
 685                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 686                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 687                         RTE_PTYPE_INNER_L4_ICMP,
 688
 689                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
 690                 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 691                         RTE_PTYPE_TUNNEL_GRENAT |
 692                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 693                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 694                         RTE_PTYPE_INNER_L4_FRAG,
 695                 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 696                         RTE_PTYPE_TUNNEL_GRENAT |
 697                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 698                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 699                         RTE_PTYPE_INNER_L4_NONFRAG,
 700                 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 701                         RTE_PTYPE_TUNNEL_GRENAT |
 702                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 703                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 704                         RTE_PTYPE_INNER_L4_UDP,
 705                 /* [150] reserved */
 706                 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 707                         RTE_PTYPE_TUNNEL_GRENAT |
 708                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 709                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 710                         RTE_PTYPE_INNER_L4_TCP,
 711                 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 712                         RTE_PTYPE_TUNNEL_GRENAT |
 713                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 714                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 715                         RTE_PTYPE_INNER_L4_SCTP,
 716                 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 717                         RTE_PTYPE_TUNNEL_GRENAT |
 718                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 719                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 720                         RTE_PTYPE_INNER_L4_ICMP,
 721
 722                 /* All others reserved */
 723         };
 724
 725         return type_table[ptype];
 726 }
 727
 728 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 729 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 730 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 731 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 732 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 733
 734 static inline uint64_t
 735 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 736 {
 737         uint64_t flags = 0;
 738 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 739         uint16_t flexbh, flexbl;
 740
 741         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 742                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 743                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 744         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 745                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 746                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 747
 748
 749         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 750                 mb->hash.fdir.hi =
 751                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 752                 flags |= PKT_RX_FDIR_ID;
 753         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 754                 mb->hash.fdir.hi =
 755                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 756                 flags |= PKT_RX_FDIR_FLX;
 757         }
 758         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 759                 mb->hash.fdir.lo =
 760                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 761                 flags |= PKT_RX_FDIR_FLX;
 762         }
 763 #else
 764         mb->hash.fdir.hi =
 765                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 766         flags |= PKT_RX_FDIR_ID;
 767 #endif
 768         return flags;
 769 }
 770 static inline void
 771 i40e_txd_enable_checksum(uint64_t ol_flags,
 772                         uint32_t *td_cmd,
 773                         uint32_t *td_offset,
 774                         union i40e_tx_offload tx_offload,
 775                         uint32_t *cd_tunneling)
 776 {
 777         /* UDP tunneling packet TX checksum offload */
 778         if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
 779
 780                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 781                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 782
 783                 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 784                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 785                 else if (ol_flags & PKT_TX_OUTER_IPV4)
 786                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 787                 else if (ol_flags & PKT_TX_OUTER_IPV6)
 788                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 789
 790                 /* Now set the ctx descriptor fields */
 791                 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 792                                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
 793                                 (tx_offload.l2_len >> 1) <<
 794                                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 795
 796         } else
 797                 *td_offset |= (tx_offload.l2_len >> 1)
 798                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 799
 800         /* Enable L3 checksum offloads */
 801         if (ol_flags & PKT_TX_IP_CKSUM) {
 802                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 803                 *td_offset |= (tx_offload.l3_len >> 2)
 804                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 805         } else if (ol_flags & PKT_TX_IPV4) {
 806                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 807                 *td_offset |= (tx_offload.l3_len >> 2)
 808                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 809         } else if (ol_flags & PKT_TX_IPV6) {
 810                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 811                 *td_offset |= (tx_offload.l3_len >> 2)
 812                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 813         }
 814
 815         if (ol_flags & PKT_TX_TCP_SEG) {
 816                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 817                 *td_offset |= (tx_offload.l4_len >> 2)
 818                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 819                 return;
 820         }
 821
 822         /* Enable L4 checksum offloads */
 823         switch (ol_flags & PKT_TX_L4_MASK) {
 824         case PKT_TX_TCP_CKSUM:
 825                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 826                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 827                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 828                 break;
 829         case PKT_TX_SCTP_CKSUM:
 830                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 831                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 832                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 833                 break;
 834         case PKT_TX_UDP_CKSUM:
 835                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 836                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 837                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 838                 break;
 839         default:
 840                 break;
 841         }
 842 }
 843
 844 /* Construct the tx flags */
 845 static inline uint64_t
 846 i40e_build_ctob(uint32_t td_cmd,
 847                 uint32_t td_offset,
 848                 unsigned int size,
 849                 uint32_t td_tag)
 850 {
 851         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 852                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 853                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 854                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 855                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 856 }
 857
 858 static inline int
 859 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 860 {
 861         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 862         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 863         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 864         uint16_t nb_tx_desc = txq->nb_tx_desc;
 865         uint16_t desc_to_clean_to;
 866         uint16_t nb_tx_to_clean;
 867
 868         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 869         if (desc_to_clean_to >= nb_tx_desc)
 870                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 871
 872         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 873         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 874                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 875                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 876                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 877                         "(port=%d queue=%d)", desc_to_clean_to,
 878                                 txq->port_id, txq->queue_id);
 879                 return -1;
 880         }
 881
 882         if (last_desc_cleaned > desc_to_clean_to)
 883                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 884                                                         desc_to_clean_to);
 885         else
 886                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 887                                         last_desc_cleaned);
 888
 889         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 890
 891         txq->last_desc_cleaned = desc_to_clean_to;
 892         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 893
 894         return 0;
 895 }
 896
 897 static inline int
 898 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 899 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 900 #else
 901 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 902 #endif
 903 {
 904         int ret = 0;
 905
 906 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 907         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 908                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 909                              "rxq->rx_free_thresh=%d, "
 910                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 911                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 912                 ret = -EINVAL;
 913         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 914                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 915                              "rxq->rx_free_thresh=%d, "
 916                              "rxq->nb_rx_desc=%d",
 917                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 918                 ret = -EINVAL;
 919         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 920                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 921                              "rxq->nb_rx_desc=%d, "
 922                              "rxq->rx_free_thresh=%d",
 923                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 924                 ret = -EINVAL;
 925         } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
 926                                 RTE_PMD_I40E_RX_MAX_BURST))) {
 927                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 928                              "rxq->nb_rx_desc=%d, "
 929                              "I40E_MAX_RING_DESC=%d, "
 930                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 931                              rxq->nb_rx_desc, I40E_MAX_RING_DESC,
 932                              RTE_PMD_I40E_RX_MAX_BURST);
 933                 ret = -EINVAL;
 934         }
 935 #else
 936         ret = -EINVAL;
 937 #endif
 938
 939         return ret;
 940 }
 941
 942 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 943 #define I40E_LOOK_AHEAD 8
 944 #if (I40E_LOOK_AHEAD != 8)
 945 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 946 #endif
 947 static inline int
 948 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 949 {
 950         volatile union i40e_rx_desc *rxdp;
 951         struct i40e_rx_entry *rxep;
 952         struct rte_mbuf *mb;
 953         uint16_t pkt_len;
 954         uint64_t qword1;
 955         uint32_t rx_status;
 956         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 957         int32_t i, j, nb_rx = 0;
 958         uint64_t pkt_flags;
 959
 960         rxdp = &rxq->rx_ring[rxq->rx_tail];
 961         rxep = &rxq->sw_ring[rxq->rx_tail];
 962
 963         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 964         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 965                                 I40E_RXD_QW1_STATUS_SHIFT;
 966
 967         /* Make sure there is at least 1 packet to receive */
 968         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 969                 return 0;
 970
 971         /**
 972          * Scan LOOK_AHEAD descriptors at a time to determine which
 973          * descriptors reference packets that are ready to be received.
 974          */
 975         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 976                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 977                 /* Read desc statuses backwards to avoid race condition */
 978                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 979                         qword1 = rte_le_to_cpu_64(\
 980                                 rxdp[j].wb.qword1.status_error_len);
 981                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 982                                         I40E_RXD_QW1_STATUS_SHIFT;
 983                 }
 984
 985                 /* Compute how many status bits were set */
 986                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 987                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 988
 989                 nb_rx += nb_dd;
 990
 991                 /* Translate descriptor info to mbuf parameters */
 992                 for (j = 0; j < nb_dd; j++) {
 993                         mb = rxep[j].mbuf;
 994                         qword1 = rte_le_to_cpu_64(\
 995                                 rxdp[j].wb.qword1.status_error_len);
 996                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 997                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 998                         mb->data_len = pkt_len;
 999                         mb->pkt_len = pkt_len;
1000                         mb->ol_flags = 0;
1001                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
1002                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1003                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1004                         mb->packet_type =
1005                                 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1006                                                 I40E_RXD_QW1_PTYPE_MASK) >>
1007                                                 I40E_RXD_QW1_PTYPE_SHIFT));
1008                         if (pkt_flags & PKT_RX_RSS_HASH)
1009                                 mb->hash.rss = rte_le_to_cpu_32(\
1010                                         rxdp[j].wb.qword0.hi_dword.rss);
1011                         if (pkt_flags & PKT_RX_FDIR)
1012                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
1013
1014 #ifdef RTE_LIBRTE_IEEE1588
1015                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
1016 #endif
1017                         mb->ol_flags |= pkt_flags;
1018
1019                 }
1020
1021                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
1022                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1023
1024                 if (nb_dd != I40E_LOOK_AHEAD)
1025                         break;
1026         }
1027
1028         /* Clear software ring entries */
1029         for (i = 0; i < nb_rx; i++)
1030                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1031
1032         return nb_rx;
1033 }
1034
1035 static inline uint16_t
1036 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
1037                         struct rte_mbuf **rx_pkts,
1038                         uint16_t nb_pkts)
1039 {
1040         uint16_t i;
1041         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1042
1043         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1044
1045         for (i = 0; i < nb_pkts; i++)
1046                 rx_pkts[i] = stage[i];
1047
1048         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1049         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1050
1051         return nb_pkts;
1052 }
1053
1054 static inline int
1055 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
1056 {
1057         volatile union i40e_rx_desc *rxdp;
1058         struct i40e_rx_entry *rxep;
1059         struct rte_mbuf *mb;
1060         uint16_t alloc_idx, i;
1061         uint64_t dma_addr;
1062         int diag;
1063
1064         /* Allocate buffers in bulk */
1065         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1066                                 (rxq->rx_free_thresh - 1));
1067         rxep = &(rxq->sw_ring[alloc_idx]);
1068         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1069                                         rxq->rx_free_thresh);
1070         if (unlikely(diag != 0)) {
1071                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
1072                 return -ENOMEM;
1073         }
1074
1075         rxdp = &rxq->rx_ring[alloc_idx];
1076         for (i = 0; i < rxq->rx_free_thresh; i++) {
1077                 if (likely(i < (rxq->rx_free_thresh - 1)))
1078                         /* Prefetch next mbuf */
1079                         rte_prefetch0(rxep[i + 1].mbuf);
1080
1081                 mb = rxep[i].mbuf;
1082                 rte_mbuf_refcnt_set(mb, 1);
1083                 mb->next = NULL;
1084                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1085                 mb->nb_segs = 1;
1086                 mb->port = rxq->port_id;
1087                 dma_addr = rte_cpu_to_le_64(\
1088                         rte_mbuf_data_dma_addr_default(mb));
1089                 rxdp[i].read.hdr_addr = 0;
1090                 rxdp[i].read.pkt_addr = dma_addr;
1091         }
1092
1093         /* Update rx tail regsiter */
1094         rte_wmb();
1095         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1096
1097         rxq->rx_free_trigger =
1098                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1099         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1100                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1101
1102         return 0;
1103 }
1104
1105 static inline uint16_t
1106 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1107 {
1108         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
1109         uint16_t nb_rx = 0;
1110
1111         if (!nb_pkts)
1112                 return 0;
1113
1114         if (rxq->rx_nb_avail)
1115                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1116
1117         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
1118         rxq->rx_next_avail = 0;
1119         rxq->rx_nb_avail = nb_rx;
1120         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1121
1122         if (rxq->rx_tail > rxq->rx_free_trigger) {
1123                 if (i40e_rx_alloc_bufs(rxq) != 0) {
1124                         uint16_t i, j;
1125
1126                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1127                                    "port_id=%u, queue_id=%u",
1128                                    rxq->port_id, rxq->queue_id);
1129                         rxq->rx_nb_avail = 0;
1130                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1131                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1132                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1133
1134                         return 0;
1135                 }
1136         }
1137
1138         if (rxq->rx_tail >= rxq->nb_rx_desc)
1139                 rxq->rx_tail = 0;
1140
1141         if (rxq->rx_nb_avail)
1142                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1143
1144         return 0;
1145 }
1146
1147 static uint16_t
1148 i40e_recv_pkts_bulk_alloc(void *rx_queue,
1149                           struct rte_mbuf **rx_pkts,
1150                           uint16_t nb_pkts)
1151 {
1152         uint16_t nb_rx = 0, n, count;
1153
1154         if (unlikely(nb_pkts == 0))
1155                 return 0;
1156
1157         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
1158                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1159
1160         while (nb_pkts) {
1161                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
1162                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1163                 nb_rx = (uint16_t)(nb_rx + count);
1164                 nb_pkts = (uint16_t)(nb_pkts - count);
1165                 if (count < n)
1166                         break;
1167         }
1168
1169         return nb_rx;
1170 }
1171 #else
1172 static uint16_t
1173 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
1174                           struct rte_mbuf __rte_unused **rx_pkts,
1175                           uint16_t __rte_unused nb_pkts)
1176 {
1177         return 0;
1178 }
1179 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1180
1181 uint16_t
1182 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1183 {
1184         struct i40e_rx_queue *rxq;
1185         volatile union i40e_rx_desc *rx_ring;
1186         volatile union i40e_rx_desc *rxdp;
1187         union i40e_rx_desc rxd;
1188         struct i40e_rx_entry *sw_ring;
1189         struct i40e_rx_entry *rxe;
1190         struct rte_mbuf *rxm;
1191         struct rte_mbuf *nmb;
1192         uint16_t nb_rx;
1193         uint32_t rx_status;
1194         uint64_t qword1;
1195         uint16_t rx_packet_len;
1196         uint16_t rx_id, nb_hold;
1197         uint64_t dma_addr;
1198         uint64_t pkt_flags;
1199
1200         nb_rx = 0;
1201         nb_hold = 0;
1202         rxq = rx_queue;
1203         rx_id = rxq->rx_tail;
1204         rx_ring = rxq->rx_ring;
1205         sw_ring = rxq->sw_ring;
1206
1207         while (nb_rx < nb_pkts) {
1208                 rxdp = &rx_ring[rx_id];
1209                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1210                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1211                                 >> I40E_RXD_QW1_STATUS_SHIFT;
1212
1213                 /* Check the DD bit first */
1214                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1215                         break;
1216
1217                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1218                 if (unlikely(!nmb))
1219                         break;
1220                 rxd = *rxdp;
1221
1222                 nb_hold++;
1223                 rxe = &sw_ring[rx_id];
1224                 rx_id++;
1225                 if (unlikely(rx_id == rxq->nb_rx_desc))
1226                         rx_id = 0;
1227
1228                 /* Prefetch next mbuf */
1229                 rte_prefetch0(sw_ring[rx_id].mbuf);
1230
1231                 /**
1232                  * When next RX descriptor is on a cache line boundary,
1233                  * prefetch the next 4 RX descriptors and next 8 pointers
1234                  * to mbufs.
1235                  */
1236                 if ((rx_id & 0x3) == 0) {
1237                         rte_prefetch0(&rx_ring[rx_id]);
1238                         rte_prefetch0(&sw_ring[rx_id]);
1239                 }
1240                 rxm = rxe->mbuf;
1241                 rxe->mbuf = nmb;
1242                 dma_addr =
1243                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
1244                 rxdp->read.hdr_addr = 0;
1245                 rxdp->read.pkt_addr = dma_addr;
1246
1247                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1248                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1249
1250                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1251                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1252                 rxm->nb_segs = 1;
1253                 rxm->next = NULL;
1254                 rxm->pkt_len = rx_packet_len;
1255                 rxm->data_len = rx_packet_len;
1256                 rxm->port = rxq->port_id;
1257                 rxm->ol_flags = 0;
1258                 i40e_rxd_to_vlan_tci(rxm, &rxd);
1259                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1260                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1261                 rxm->packet_type =
1262                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1263                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1264                 if (pkt_flags & PKT_RX_RSS_HASH)
1265                         rxm->hash.rss =
1266                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1267                 if (pkt_flags & PKT_RX_FDIR)
1268                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1269
1270 #ifdef RTE_LIBRTE_IEEE1588
1271                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
1272 #endif
1273                 rxm->ol_flags |= pkt_flags;
1274
1275                 rx_pkts[nb_rx++] = rxm;
1276         }
1277         rxq->rx_tail = rx_id;
1278
1279         /**
1280          * If the number of free RX descriptors is greater than the RX free
1281          * threshold of the queue, advance the receive tail register of queue.
1282          * Update that register with the value of the last processed RX
1283          * descriptor minus 1.
1284          */
1285         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1286         if (nb_hold > rxq->rx_free_thresh) {
1287                 rx_id = (uint16_t) ((rx_id == 0) ?
1288                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1289                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1290                 nb_hold = 0;
1291         }
1292         rxq->nb_rx_hold = nb_hold;
1293
1294         return nb_rx;
1295 }
1296
1297 uint16_t
1298 i40e_recv_scattered_pkts(void *rx_queue,
1299                          struct rte_mbuf **rx_pkts,
1300                          uint16_t nb_pkts)
1301 {
1302         struct i40e_rx_queue *rxq = rx_queue;
1303         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
1304         volatile union i40e_rx_desc *rxdp;
1305         union i40e_rx_desc rxd;
1306         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
1307         struct i40e_rx_entry *rxe;
1308         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1309         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1310         struct rte_mbuf *nmb, *rxm;
1311         uint16_t rx_id = rxq->rx_tail;
1312         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1313         uint32_t rx_status;
1314         uint64_t qword1;
1315         uint64_t dma_addr;
1316         uint64_t pkt_flags;
1317
1318         while (nb_rx < nb_pkts) {
1319                 rxdp = &rx_ring[rx_id];
1320                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1321                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1322                                         I40E_RXD_QW1_STATUS_SHIFT;
1323
1324                 /* Check the DD bit */
1325                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1326                         break;
1327
1328                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1329                 if (unlikely(!nmb))
1330                         break;
1331                 rxd = *rxdp;
1332                 nb_hold++;
1333                 rxe = &sw_ring[rx_id];
1334                 rx_id++;
1335                 if (rx_id == rxq->nb_rx_desc)
1336                         rx_id = 0;
1337
1338                 /* Prefetch next mbuf */
1339                 rte_prefetch0(sw_ring[rx_id].mbuf);
1340
1341                 /**
1342                  * When next RX descriptor is on a cache line boundary,
1343                  * prefetch the next 4 RX descriptors and next 8 pointers
1344                  * to mbufs.
1345                  */
1346                 if ((rx_id & 0x3) == 0) {
1347                         rte_prefetch0(&rx_ring[rx_id]);
1348                         rte_prefetch0(&sw_ring[rx_id]);
1349                 }
1350
1351                 rxm = rxe->mbuf;
1352                 rxe->mbuf = nmb;
1353                 dma_addr =
1354                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
1355
1356                 /* Set data buffer address and data length of the mbuf */
1357                 rxdp->read.hdr_addr = 0;
1358                 rxdp->read.pkt_addr = dma_addr;
1359                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1360                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1361                 rxm->data_len = rx_packet_len;
1362                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1363
1364                 /**
1365                  * If this is the first buffer of the received packet, set the
1366                  * pointer to the first mbuf of the packet and initialize its
1367                  * context. Otherwise, update the total length and the number
1368                  * of segments of the current scattered packet, and update the
1369                  * pointer to the last mbuf of the current packet.
1370                  */
1371                 if (!first_seg) {
1372                         first_seg = rxm;
1373                         first_seg->nb_segs = 1;
1374                         first_seg->pkt_len = rx_packet_len;
1375                 } else {
1376                         first_seg->pkt_len =
1377                                 (uint16_t)(first_seg->pkt_len +
1378                                                 rx_packet_len);
1379                         first_seg->nb_segs++;
1380                         last_seg->next = rxm;
1381                 }
1382
1383                 /**
1384                  * If this is not the last buffer of the received packet,
1385                  * update the pointer to the last mbuf of the current scattered
1386                  * packet and continue to parse the RX ring.
1387                  */
1388                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1389                         last_seg = rxm;
1390                         continue;
1391                 }
1392
1393                 /**
1394                  * This is the last buffer of the received packet. If the CRC
1395                  * is not stripped by the hardware:
1396                  *  - Subtract the CRC length from the total packet length.
1397                  *  - If the last buffer only contains the whole CRC or a part
1398                  *  of it, free the mbuf associated to the last buffer. If part
1399                  *  of the CRC is also contained in the previous mbuf, subtract
1400                  *  the length of that CRC part from the data length of the
1401                  *  previous mbuf.
1402                  */
1403                 rxm->next = NULL;
1404                 if (unlikely(rxq->crc_len > 0)) {
1405                         first_seg->pkt_len -= ETHER_CRC_LEN;
1406                         if (rx_packet_len <= ETHER_CRC_LEN) {
1407                                 rte_pktmbuf_free_seg(rxm);
1408                                 first_seg->nb_segs--;
1409                                 last_seg->data_len =
1410                                         (uint16_t)(last_seg->data_len -
1411                                         (ETHER_CRC_LEN - rx_packet_len));
1412                                 last_seg->next = NULL;
1413                         } else
1414                                 rxm->data_len = (uint16_t)(rx_packet_len -
1415                                                                 ETHER_CRC_LEN);
1416                 }
1417
1418                 first_seg->port = rxq->port_id;
1419                 first_seg->ol_flags = 0;
1420                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
1421                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1422                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1423                 first_seg->packet_type =
1424                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1425                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1426                 if (pkt_flags & PKT_RX_RSS_HASH)
1427                         rxm->hash.rss =
1428                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1429                 if (pkt_flags & PKT_RX_FDIR)
1430                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1431
1432 #ifdef RTE_LIBRTE_IEEE1588
1433                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
1434 #endif
1435                 first_seg->ol_flags |= pkt_flags;
1436
1437                 /* Prefetch data of first segment, if configured to do so. */
1438                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1439                         first_seg->data_off));
1440                 rx_pkts[nb_rx++] = first_seg;
1441                 first_seg = NULL;
1442         }
1443
1444         /* Record index of the next RX descriptor to probe. */
1445         rxq->rx_tail = rx_id;
1446         rxq->pkt_first_seg = first_seg;
1447         rxq->pkt_last_seg = last_seg;
1448
1449         /**
1450          * If the number of free RX descriptors is greater than the RX free
1451          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1452          * register. Update the RDT with the value of the last processed RX
1453          * descriptor minus 1, to guarantee that the RDT register is never
1454          * equal to the RDH register, which creates a "full" ring situtation
1455          * from the hardware point of view.
1456          */
1457         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1458         if (nb_hold > rxq->rx_free_thresh) {
1459                 rx_id = (uint16_t)(rx_id == 0 ?
1460                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1461                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1462                 nb_hold = 0;
1463         }
1464         rxq->nb_rx_hold = nb_hold;
1465
1466         return nb_rx;
1467 }
1468
1469 /* Check if the context descriptor is needed for TX offloading */
1470 static inline uint16_t
1471 i40e_calc_context_desc(uint64_t flags)
1472 {
1473         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
1474                 PKT_TX_TCP_SEG |
1475                 PKT_TX_QINQ_PKT;
1476
1477 #ifdef RTE_LIBRTE_IEEE1588
1478         mask |= PKT_TX_IEEE1588_TMST;
1479 #endif
1480
1481         return (flags & mask) ? 1 : 0;
1482 }
1483
1484 /* set i40e TSO context descriptor */
1485 static inline uint64_t
1486 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1487 {
1488         uint64_t ctx_desc = 0;
1489         uint32_t cd_cmd, hdr_len, cd_tso_len;
1490
1491         if (!tx_offload.l4_len) {
1492                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1493                 return ctx_desc;
1494         }
1495
1496         /**
1497          * in case of tunneling packet, the outer_l2_len and
1498          * outer_l3_len must be 0.
1499          */
1500         hdr_len = tx_offload.outer_l2_len +
1501                 tx_offload.outer_l3_len +
1502                 tx_offload.l2_len +
1503                 tx_offload.l3_len +
1504                 tx_offload.l4_len;
1505
1506         cd_cmd = I40E_TX_CTX_DESC_TSO;
1507         cd_tso_len = mbuf->pkt_len - hdr_len;
1508         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1509                 ((uint64_t)cd_tso_len <<
1510                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1511                 ((uint64_t)mbuf->tso_segsz <<
1512                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1513
1514         return ctx_desc;
1515 }
1516
1517 uint16_t
1518 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1519 {
1520         struct i40e_tx_queue *txq;
1521         struct i40e_tx_entry *sw_ring;
1522         struct i40e_tx_entry *txe, *txn;
1523         volatile struct i40e_tx_desc *txd;
1524         volatile struct i40e_tx_desc *txr;
1525         struct rte_mbuf *tx_pkt;
1526         struct rte_mbuf *m_seg;
1527         uint32_t cd_tunneling_params;
1528         uint16_t tx_id;
1529         uint16_t nb_tx;
1530         uint32_t td_cmd;
1531         uint32_t td_offset;
1532         uint32_t tx_flags;
1533         uint32_t td_tag;
1534         uint64_t ol_flags;
1535         uint16_t nb_used;
1536         uint16_t nb_ctx;
1537         uint16_t tx_last;
1538         uint16_t slen;
1539         uint64_t buf_dma_addr;
1540         union i40e_tx_offload tx_offload = {0};
1541
1542         txq = tx_queue;
1543         sw_ring = txq->sw_ring;
1544         txr = txq->tx_ring;
1545         tx_id = txq->tx_tail;
1546         txe = &sw_ring[tx_id];
1547
1548         /* Check if the descriptor ring needs to be cleaned. */
1549         if (txq->nb_tx_free < txq->tx_free_thresh)
1550                 i40e_xmit_cleanup(txq);
1551
1552         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1553                 td_cmd = 0;
1554                 td_tag = 0;
1555                 td_offset = 0;
1556                 tx_flags = 0;
1557
1558                 tx_pkt = *tx_pkts++;
1559                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1560
1561                 ol_flags = tx_pkt->ol_flags;
1562                 tx_offload.l2_len = tx_pkt->l2_len;
1563                 tx_offload.l3_len = tx_pkt->l3_len;
1564                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1565                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1566                 tx_offload.l4_len = tx_pkt->l4_len;
1567                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1568
1569                 /* Calculate the number of context descriptors needed. */
1570                 nb_ctx = i40e_calc_context_desc(ol_flags);
1571
1572                 /**
1573                  * The number of descriptors that must be allocated for
1574                  * a packet equals to the number of the segments of that
1575                  * packet plus 1 context descriptor if needed.
1576                  */
1577                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1578                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1579
1580                 /* Circular ring */
1581                 if (tx_last >= txq->nb_tx_desc)
1582                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1583
1584                 if (nb_used > txq->nb_tx_free) {
1585                         if (i40e_xmit_cleanup(txq) != 0) {
1586                                 if (nb_tx == 0)
1587                                         return 0;
1588                                 goto end_of_tx;
1589                         }
1590                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1591                                 while (nb_used > txq->nb_tx_free) {
1592                                         if (i40e_xmit_cleanup(txq) != 0) {
1593                                                 if (nb_tx == 0)
1594                                                         return 0;
1595                                                 goto end_of_tx;
1596                                         }
1597                                 }
1598                         }
1599                 }
1600
1601                 /* Descriptor based VLAN insertion */
1602                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1603                         tx_flags |= tx_pkt->vlan_tci <<
1604                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1605                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1606                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1607                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1608                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1609                 }
1610
1611                 /* Always enable CRC offload insertion */
1612                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1613
1614                 /* Enable checksum offloading */
1615                 cd_tunneling_params = 0;
1616                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK) {
1617                         i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1618                                 tx_offload, &cd_tunneling_params);
1619                 }
1620
1621                 if (nb_ctx) {
1622                         /* Setup TX context descriptor if required */
1623                         volatile struct i40e_tx_context_desc *ctx_txd =
1624                                 (volatile struct i40e_tx_context_desc *)\
1625                                                         &txr[tx_id];
1626                         uint16_t cd_l2tag2 = 0;
1627                         uint64_t cd_type_cmd_tso_mss =
1628                                 I40E_TX_DESC_DTYPE_CONTEXT;
1629
1630                         txn = &sw_ring[txe->next_id];
1631                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1632                         if (txe->mbuf != NULL) {
1633                                 rte_pktmbuf_free_seg(txe->mbuf);
1634                                 txe->mbuf = NULL;
1635                         }
1636
1637                         /* TSO enabled means no timestamp */
1638                         if (ol_flags & PKT_TX_TCP_SEG)
1639                                 cd_type_cmd_tso_mss |=
1640                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1641                         else {
1642 #ifdef RTE_LIBRTE_IEEE1588
1643                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1644                                         cd_type_cmd_tso_mss |=
1645                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1646                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1647 #endif
1648                         }
1649
1650                         ctx_txd->tunneling_params =
1651                                 rte_cpu_to_le_32(cd_tunneling_params);
1652                         if (ol_flags & PKT_TX_QINQ_PKT) {
1653                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1654                                 cd_type_cmd_tso_mss |=
1655                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1656                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1657                         }
1658                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1659                         ctx_txd->type_cmd_tso_mss =
1660                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1661
1662                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1663                                 "tunneling_params: %#x;\n"
1664                                 "l2tag2: %#hx;\n"
1665                                 "rsvd: %#hx;\n"
1666                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1667                                 tx_pkt, tx_id,
1668                                 ctx_txd->tunneling_params,
1669                                 ctx_txd->l2tag2,
1670                                 ctx_txd->rsvd,
1671                                 ctx_txd->type_cmd_tso_mss);
1672
1673                         txe->last_id = tx_last;
1674                         tx_id = txe->next_id;
1675                         txe = txn;
1676                 }
1677
1678                 m_seg = tx_pkt;
1679                 do {
1680                         txd = &txr[tx_id];
1681                         txn = &sw_ring[txe->next_id];
1682
1683                         if (txe->mbuf)
1684                                 rte_pktmbuf_free_seg(txe->mbuf);
1685                         txe->mbuf = m_seg;
1686
1687                         /* Setup TX Descriptor */
1688                         slen = m_seg->data_len;
1689                         buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1690
1691                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1692                                 "buf_dma_addr: %#"PRIx64";\n"
1693                                 "td_cmd: %#x;\n"
1694                                 "td_offset: %#x;\n"
1695                                 "td_len: %u;\n"
1696                                 "td_tag: %#x;\n",
1697                                 tx_pkt, tx_id, buf_dma_addr,
1698                                 td_cmd, td_offset, slen, td_tag);
1699
1700                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1701                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1702                                                 td_offset, slen, td_tag);
1703                         txe->last_id = tx_last;
1704                         tx_id = txe->next_id;
1705                         txe = txn;
1706                         m_seg = m_seg->next;
1707                 } while (m_seg != NULL);
1708
1709                 /* The last packet data descriptor needs End Of Packet (EOP) */
1710                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1711                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1712                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1713
1714                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1715                         PMD_TX_FREE_LOG(DEBUG,
1716                                         "Setting RS bit on TXD id="
1717                                         "%4u (port=%d queue=%d)",
1718                                         tx_last, txq->port_id, txq->queue_id);
1719
1720                         td_cmd |= I40E_TX_DESC_CMD_RS;
1721
1722                         /* Update txq RS bit counters */
1723                         txq->nb_tx_used = 0;
1724                 }
1725
1726                 txd->cmd_type_offset_bsz |=
1727                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1728                                         I40E_TXD_QW1_CMD_SHIFT);
1729         }
1730
1731 end_of_tx:
1732         rte_wmb();
1733
1734         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1735                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1736                    (unsigned) tx_id, (unsigned) nb_tx);
1737
1738         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1739         txq->tx_tail = tx_id;
1740
1741         return nb_tx;
1742 }
1743
1744 static inline int __attribute__((always_inline))
1745 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1746 {
1747         struct i40e_tx_entry *txep;
1748         uint16_t i;
1749
1750         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1751                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1752                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1753                 return 0;
1754
1755         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1756
1757         for (i = 0; i < txq->tx_rs_thresh; i++)
1758                 rte_prefetch0((txep + i)->mbuf);
1759
1760         if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1761                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1762                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1763                         txep->mbuf = NULL;
1764                 }
1765         } else {
1766                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1767                         rte_pktmbuf_free_seg(txep->mbuf);
1768                         txep->mbuf = NULL;
1769                 }
1770         }
1771
1772         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1773         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1774         if (txq->tx_next_dd >= txq->nb_tx_desc)
1775                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1776
1777         return txq->tx_rs_thresh;
1778 }
1779
1780 /* Populate 4 descriptors with data from 4 mbufs */
1781 static inline void
1782 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1783 {
1784         uint64_t dma_addr;
1785         uint32_t i;
1786
1787         for (i = 0; i < 4; i++, txdp++, pkts++) {
1788                 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1789                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1790                 txdp->cmd_type_offset_bsz =
1791                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1792                                         (*pkts)->data_len, 0);
1793         }
1794 }
1795
1796 /* Populate 1 descriptor with data from 1 mbuf */
1797 static inline void
1798 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1799 {
1800         uint64_t dma_addr;
1801
1802         dma_addr = rte_mbuf_data_dma_addr(*pkts);
1803         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1804         txdp->cmd_type_offset_bsz =
1805                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1806                                 (*pkts)->data_len, 0);
1807 }
1808
1809 /* Fill hardware descriptor ring with mbuf data */
1810 static inline void
1811 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1812                      struct rte_mbuf **pkts,
1813                      uint16_t nb_pkts)
1814 {
1815         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1816         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1817         const int N_PER_LOOP = 4;
1818         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1819         int mainpart, leftover;
1820         int i, j;
1821
1822         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1823         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1824         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1825                 for (j = 0; j < N_PER_LOOP; ++j) {
1826                         (txep + i + j)->mbuf = *(pkts + i + j);
1827                 }
1828                 tx4(txdp + i, pkts + i);
1829         }
1830         if (unlikely(leftover > 0)) {
1831                 for (i = 0; i < leftover; ++i) {
1832                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1833                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1834                 }
1835         }
1836 }
1837
1838 static inline uint16_t
1839 tx_xmit_pkts(struct i40e_tx_queue *txq,
1840              struct rte_mbuf **tx_pkts,
1841              uint16_t nb_pkts)
1842 {
1843         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1844         uint16_t n = 0;
1845
1846         /**
1847          * Begin scanning the H/W ring for done descriptors when the number
1848          * of available descriptors drops below tx_free_thresh. For each done
1849          * descriptor, free the associated buffer.
1850          */
1851         if (txq->nb_tx_free < txq->tx_free_thresh)
1852                 i40e_tx_free_bufs(txq);
1853
1854         /* Use available descriptor only */
1855         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1856         if (unlikely(!nb_pkts))
1857                 return 0;
1858
1859         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1860         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1861                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1862                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1863                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1864                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1865                                                 I40E_TXD_QW1_CMD_SHIFT);
1866                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1867                 txq->tx_tail = 0;
1868         }
1869
1870         /* Fill hardware descriptor ring with mbuf data */
1871         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1872         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1873
1874         /* Determin if RS bit needs to be set */
1875         if (txq->tx_tail > txq->tx_next_rs) {
1876                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1877                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1878                                                 I40E_TXD_QW1_CMD_SHIFT);
1879                 txq->tx_next_rs =
1880                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1881                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1882                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1883         }
1884
1885         if (txq->tx_tail >= txq->nb_tx_desc)
1886                 txq->tx_tail = 0;
1887
1888         /* Update the tx tail register */
1889         rte_wmb();
1890         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1891
1892         return nb_pkts;
1893 }
1894
1895 static uint16_t
1896 i40e_xmit_pkts_simple(void *tx_queue,
1897                       struct rte_mbuf **tx_pkts,
1898                       uint16_t nb_pkts)
1899 {
1900         uint16_t nb_tx = 0;
1901
1902         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1903                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1904                                                 tx_pkts, nb_pkts);
1905
1906         while (nb_pkts) {
1907                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1908                                                 I40E_TX_MAX_BURST);
1909
1910                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1911                                                 &tx_pkts[nb_tx], num);
1912                 nb_tx = (uint16_t)(nb_tx + ret);
1913                 nb_pkts = (uint16_t)(nb_pkts - ret);
1914                 if (ret < num)
1915                         break;
1916         }
1917
1918         return nb_tx;
1919 }
1920
1921 /*
1922  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1923  * application used, which assume having sequential ones. But from driver's
1924  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1925  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1926  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1927  * use queue_idx from 0 to 95 to access queues, while real queue would be
1928  * different. This function will do a queue mapping to find VSI the queue
1929  * belongs to.
1930  */
1931 static struct i40e_vsi*
1932 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1933 {
1934         /* the queue in MAIN VSI range */
1935         if (queue_idx < pf->main_vsi->nb_qps)
1936                 return pf->main_vsi;
1937
1938         queue_idx -= pf->main_vsi->nb_qps;
1939
1940         /* queue_idx is greater than VMDQ VSIs range */
1941         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1942                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1943                 return NULL;
1944         }
1945
1946         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1947 }
1948
1949 static uint16_t
1950 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1951 {
1952         /* the queue in MAIN VSI range */
1953         if (queue_idx < pf->main_vsi->nb_qps)
1954                 return queue_idx;
1955
1956         /* It's VMDQ queues */
1957         queue_idx -= pf->main_vsi->nb_qps;
1958
1959         if (pf->nb_cfg_vmdq_vsi)
1960                 return queue_idx % pf->vmdq_nb_qps;
1961         else {
1962                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1963                 return (uint16_t)(-1);
1964         }
1965 }
1966
1967 int
1968 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1969 {
1970         struct i40e_rx_queue *rxq;
1971         int err = -1;
1972         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1973
1974         PMD_INIT_FUNC_TRACE();
1975
1976         if (rx_queue_id < dev->data->nb_rx_queues) {
1977                 rxq = dev->data->rx_queues[rx_queue_id];
1978
1979                 err = i40e_alloc_rx_queue_mbufs(rxq);
1980                 if (err) {
1981                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1982                         return err;
1983                 }
1984
1985                 rte_wmb();
1986
1987                 /* Init the RX tail regieter. */
1988                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1989
1990                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1991
1992                 if (err) {
1993                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1994                                     rx_queue_id);
1995
1996                         i40e_rx_queue_release_mbufs(rxq);
1997                         i40e_reset_rx_queue(rxq);
1998                 } else
1999                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2000         }
2001
2002         return err;
2003 }
2004
2005 int
2006 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2007 {
2008         struct i40e_rx_queue *rxq;
2009         int err;
2010         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2011
2012         if (rx_queue_id < dev->data->nb_rx_queues) {
2013                 rxq = dev->data->rx_queues[rx_queue_id];
2014
2015                 /*
2016                 * rx_queue_id is queue id aplication refers to, while
2017                 * rxq->reg_idx is the real queue index.
2018                 */
2019                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
2020
2021                 if (err) {
2022                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
2023                                     rx_queue_id);
2024                         return err;
2025                 }
2026                 i40e_rx_queue_release_mbufs(rxq);
2027                 i40e_reset_rx_queue(rxq);
2028                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2029         }
2030
2031         return 0;
2032 }
2033
2034 int
2035 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2036 {
2037         int err = -1;
2038         struct i40e_tx_queue *txq;
2039         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2040
2041         PMD_INIT_FUNC_TRACE();
2042
2043         if (tx_queue_id < dev->data->nb_tx_queues) {
2044                 txq = dev->data->tx_queues[tx_queue_id];
2045
2046                 /*
2047                 * tx_queue_id is queue id aplication refers to, while
2048                 * rxq->reg_idx is the real queue index.
2049                 */
2050                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
2051                 if (err)
2052                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
2053                                     tx_queue_id);
2054                 else
2055                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2056         }
2057
2058         return err;
2059 }
2060
2061 int
2062 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2063 {
2064         struct i40e_tx_queue *txq;
2065         int err;
2066         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2067
2068         if (tx_queue_id < dev->data->nb_tx_queues) {
2069                 txq = dev->data->tx_queues[tx_queue_id];
2070
2071                 /*
2072                 * tx_queue_id is queue id aplication refers to, while
2073                 * txq->reg_idx is the real queue index.
2074                 */
2075                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
2076
2077                 if (err) {
2078                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
2079                                     tx_queue_id);
2080                         return err;
2081                 }
2082
2083                 i40e_tx_queue_release_mbufs(txq);
2084                 i40e_reset_tx_queue(txq);
2085                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2086         }
2087
2088         return 0;
2089 }
2090
2091 const uint32_t *
2092 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2093 {
2094         static const uint32_t ptypes[] = {
2095                 /* refers to i40e_rxd_pkt_type_mapping() */
2096                 RTE_PTYPE_L2_ETHER,
2097                 RTE_PTYPE_L2_ETHER_TIMESYNC,
2098                 RTE_PTYPE_L2_ETHER_LLDP,
2099                 RTE_PTYPE_L2_ETHER_ARP,
2100                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2101                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2102                 RTE_PTYPE_L4_FRAG,
2103                 RTE_PTYPE_L4_ICMP,
2104                 RTE_PTYPE_L4_NONFRAG,
2105                 RTE_PTYPE_L4_SCTP,
2106                 RTE_PTYPE_L4_TCP,
2107                 RTE_PTYPE_L4_UDP,
2108                 RTE_PTYPE_TUNNEL_GRENAT,
2109                 RTE_PTYPE_TUNNEL_IP,
2110                 RTE_PTYPE_INNER_L2_ETHER,
2111                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2112                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2113                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2114                 RTE_PTYPE_INNER_L4_FRAG,
2115                 RTE_PTYPE_INNER_L4_ICMP,
2116                 RTE_PTYPE_INNER_L4_NONFRAG,
2117                 RTE_PTYPE_INNER_L4_SCTP,
2118                 RTE_PTYPE_INNER_L4_TCP,
2119                 RTE_PTYPE_INNER_L4_UDP,
2120                 RTE_PTYPE_UNKNOWN
2121         };
2122
2123         if (dev->rx_pkt_burst == i40e_recv_pkts ||
2124 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2125             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
2126 #endif
2127             dev->rx_pkt_burst == i40e_recv_scattered_pkts)
2128                 return ptypes;
2129         return NULL;
2130 }
2131
2132 int
2133 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
2134                         uint16_t queue_idx,
2135                         uint16_t nb_desc,
2136                         unsigned int socket_id,
2137                         const struct rte_eth_rxconf *rx_conf,
2138                         struct rte_mempool *mp)
2139 {
2140         struct i40e_vsi *vsi;
2141         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2142         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2143         struct i40e_adapter *ad =
2144                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2145         struct i40e_rx_queue *rxq;
2146         const struct rte_memzone *rz;
2147         uint32_t ring_size;
2148         uint16_t len, i;
2149         uint16_t base, bsf, tc_mapping;
2150         int use_def_burst_func = 1;
2151
2152         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2153                 struct i40e_vf *vf =
2154                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2155                 vsi = &vf->vsi;
2156         } else
2157                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2158
2159         if (vsi == NULL) {
2160                 PMD_DRV_LOG(ERR, "VSI not available or queue "
2161                             "index exceeds the maximum");
2162                 return I40E_ERR_PARAM;
2163         }
2164         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2165                         (nb_desc > I40E_MAX_RING_DESC) ||
2166                         (nb_desc < I40E_MIN_RING_DESC)) {
2167                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
2168                             "invalid", nb_desc);
2169                 return I40E_ERR_PARAM;
2170         }
2171
2172         /* Free memory if needed */
2173         if (dev->data->rx_queues[queue_idx]) {
2174                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
2175                 dev->data->rx_queues[queue_idx] = NULL;
2176         }
2177
2178         /* Allocate the rx queue data structure */
2179         rxq = rte_zmalloc_socket("i40e rx queue",
2180                                  sizeof(struct i40e_rx_queue),
2181                                  RTE_CACHE_LINE_SIZE,
2182                                  socket_id);
2183         if (!rxq) {
2184                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2185                             "rx queue data structure");
2186                 return -ENOMEM;
2187         }
2188         rxq->mp = mp;
2189         rxq->nb_rx_desc = nb_desc;
2190         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2191         rxq->queue_id = queue_idx;
2192         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2193                 rxq->reg_idx = queue_idx;
2194         else /* PF device */
2195                 rxq->reg_idx = vsi->base_queue +
2196                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2197
2198         rxq->port_id = dev->data->port_id;
2199         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2200                                                         0 : ETHER_CRC_LEN);
2201         rxq->drop_en = rx_conf->rx_drop_en;
2202         rxq->vsi = vsi;
2203         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2204
2205         /* Allocate the maximun number of RX ring hardware descriptor. */
2206         ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
2207         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2208         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2209                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2210         if (!rz) {
2211                 i40e_dev_rx_queue_release(rxq);
2212                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2213                 return -ENOMEM;
2214         }
2215
2216         /* Zero all the descriptors in the ring. */
2217         memset(rz->addr, 0, ring_size);
2218
2219         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2220         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2221
2222 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2223         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2224 #else
2225         len = nb_desc;
2226 #endif
2227
2228         /* Allocate the software ring. */
2229         rxq->sw_ring =
2230                 rte_zmalloc_socket("i40e rx sw ring",
2231                                    sizeof(struct i40e_rx_entry) * len,
2232                                    RTE_CACHE_LINE_SIZE,
2233                                    socket_id);
2234         if (!rxq->sw_ring) {
2235                 i40e_dev_rx_queue_release(rxq);
2236                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2237                 return -ENOMEM;
2238         }
2239
2240         i40e_reset_rx_queue(rxq);
2241         rxq->q_set = TRUE;
2242         dev->data->rx_queues[queue_idx] = rxq;
2243
2244         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2245
2246         if (!use_def_burst_func) {
2247 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2248                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2249                              "satisfied. Rx Burst Bulk Alloc function will be "
2250                              "used on port=%d, queue=%d.",
2251                              rxq->port_id, rxq->queue_id);
2252 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2253         } else {
2254                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2255                              "not satisfied, Scattered Rx is requested, "
2256                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2257                              "not enabled on port=%d, queue=%d.",
2258                              rxq->port_id, rxq->queue_id);
2259                 ad->rx_bulk_alloc_allowed = false;
2260         }
2261
2262         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2263                 if (!(vsi->enabled_tc & (1 << i)))
2264                         continue;
2265                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2266                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2267                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2268                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2269                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2270
2271                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2272                         rxq->dcb_tc = i;
2273         }
2274
2275         return 0;
2276 }
2277
2278 void
2279 i40e_dev_rx_queue_release(void *rxq)
2280 {
2281         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2282
2283         if (!q) {
2284                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2285                 return;
2286         }
2287
2288         i40e_rx_queue_release_mbufs(q);
2289         rte_free(q->sw_ring);
2290         rte_free(q);
2291 }
2292
2293 uint32_t
2294 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2295 {
2296 #define I40E_RXQ_SCAN_INTERVAL 4
2297         volatile union i40e_rx_desc *rxdp;
2298         struct i40e_rx_queue *rxq;
2299         uint16_t desc = 0;
2300
2301         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
2302                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
2303                 return 0;
2304         }
2305
2306         rxq = dev->data->rx_queues[rx_queue_id];
2307         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2308         while ((desc < rxq->nb_rx_desc) &&
2309                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2310                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2311                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2312                 /**
2313                  * Check the DD bit of a rx descriptor of each 4 in a group,
2314                  * to avoid checking too frequently and downgrading performance
2315                  * too much.
2316                  */
2317                 desc += I40E_RXQ_SCAN_INTERVAL;
2318                 rxdp += I40E_RXQ_SCAN_INTERVAL;
2319                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2320                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2321                                         desc - rxq->nb_rx_desc]);
2322         }
2323
2324         return desc;
2325 }
2326
2327 int
2328 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2329 {
2330         volatile union i40e_rx_desc *rxdp;
2331         struct i40e_rx_queue *rxq = rx_queue;
2332         uint16_t desc;
2333         int ret;
2334
2335         if (unlikely(offset >= rxq->nb_rx_desc)) {
2336                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
2337                 return 0;
2338         }
2339
2340         desc = rxq->rx_tail + offset;
2341         if (desc >= rxq->nb_rx_desc)
2342                 desc -= rxq->nb_rx_desc;
2343
2344         rxdp = &(rxq->rx_ring[desc]);
2345
2346         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2347                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2348                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2349
2350         return ret;
2351 }
2352
2353 int
2354 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2355                         uint16_t queue_idx,
2356                         uint16_t nb_desc,
2357                         unsigned int socket_id,
2358                         const struct rte_eth_txconf *tx_conf)
2359 {
2360         struct i40e_vsi *vsi;
2361         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2362         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2363         struct i40e_tx_queue *txq;
2364         const struct rte_memzone *tz;
2365         uint32_t ring_size;
2366         uint16_t tx_rs_thresh, tx_free_thresh;
2367         uint16_t i, base, bsf, tc_mapping;
2368
2369         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2370                 struct i40e_vf *vf =
2371                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2372                 vsi = &vf->vsi;
2373         } else
2374                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2375
2376         if (vsi == NULL) {
2377                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2378                             "exceeds the maximum", queue_idx);
2379                 return I40E_ERR_PARAM;
2380         }
2381
2382         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2383                         (nb_desc > I40E_MAX_RING_DESC) ||
2384                         (nb_desc < I40E_MIN_RING_DESC)) {
2385                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2386                             "invalid", nb_desc);
2387                 return I40E_ERR_PARAM;
2388         }
2389
2390         /**
2391          * The following two parameters control the setting of the RS bit on
2392          * transmit descriptors. TX descriptors will have their RS bit set
2393          * after txq->tx_rs_thresh descriptors have been used. The TX
2394          * descriptor ring will be cleaned after txq->tx_free_thresh
2395          * descriptors are used or if the number of descriptors required to
2396          * transmit a packet is greater than the number of free TX descriptors.
2397          *
2398          * The following constraints must be satisfied:
2399          *  - tx_rs_thresh must be greater than 0.
2400          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2401          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2402          *  - tx_rs_thresh must be a divisor of the ring size.
2403          *  - tx_free_thresh must be greater than 0.
2404          *  - tx_free_thresh must be less than the size of the ring minus 3.
2405          *
2406          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2407          * race condition, hence the maximum threshold constraints. When set
2408          * to zero use default values.
2409          */
2410         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2411                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2412         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2413                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2414         if (tx_rs_thresh >= (nb_desc - 2)) {
2415                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2416                              "number of TX descriptors minus 2. "
2417                              "(tx_rs_thresh=%u port=%d queue=%d)",
2418                              (unsigned int)tx_rs_thresh,
2419                              (int)dev->data->port_id,
2420                              (int)queue_idx);
2421                 return I40E_ERR_PARAM;
2422         }
2423         if (tx_free_thresh >= (nb_desc - 3)) {
2424                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2425                              "tx_free_thresh must be less than the "
2426                              "number of TX descriptors minus 3. "
2427                              "(tx_free_thresh=%u port=%d queue=%d)",
2428                              (unsigned int)tx_free_thresh,
2429                              (int)dev->data->port_id,
2430                              (int)queue_idx);
2431                 return I40E_ERR_PARAM;
2432         }
2433         if (tx_rs_thresh > tx_free_thresh) {
2434                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2435                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2436                              " tx_rs_thresh=%u port=%d queue=%d)",
2437                              (unsigned int)tx_free_thresh,
2438                              (unsigned int)tx_rs_thresh,
2439                              (int)dev->data->port_id,
2440                              (int)queue_idx);
2441                 return I40E_ERR_PARAM;
2442         }
2443         if ((nb_desc % tx_rs_thresh) != 0) {
2444                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2445                              "number of TX descriptors. (tx_rs_thresh=%u"
2446                              " port=%d queue=%d)",
2447                              (unsigned int)tx_rs_thresh,
2448                              (int)dev->data->port_id,
2449                              (int)queue_idx);
2450                 return I40E_ERR_PARAM;
2451         }
2452         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2453                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2454                              "tx_rs_thresh is greater than 1. "
2455                              "(tx_rs_thresh=%u port=%d queue=%d)",
2456                              (unsigned int)tx_rs_thresh,
2457                              (int)dev->data->port_id,
2458                              (int)queue_idx);
2459                 return I40E_ERR_PARAM;
2460         }
2461
2462         /* Free memory if needed. */
2463         if (dev->data->tx_queues[queue_idx]) {
2464                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2465                 dev->data->tx_queues[queue_idx] = NULL;
2466         }
2467
2468         /* Allocate the TX queue data structure. */
2469         txq = rte_zmalloc_socket("i40e tx queue",
2470                                   sizeof(struct i40e_tx_queue),
2471                                   RTE_CACHE_LINE_SIZE,
2472                                   socket_id);
2473         if (!txq) {
2474                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2475                             "tx queue structure");
2476                 return -ENOMEM;
2477         }
2478
2479         /* Allocate TX hardware ring descriptors. */
2480         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2481         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2482         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2483                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2484         if (!tz) {
2485                 i40e_dev_tx_queue_release(txq);
2486                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2487                 return -ENOMEM;
2488         }
2489
2490         txq->nb_tx_desc = nb_desc;
2491         txq->tx_rs_thresh = tx_rs_thresh;
2492         txq->tx_free_thresh = tx_free_thresh;
2493         txq->pthresh = tx_conf->tx_thresh.pthresh;
2494         txq->hthresh = tx_conf->tx_thresh.hthresh;
2495         txq->wthresh = tx_conf->tx_thresh.wthresh;
2496         txq->queue_id = queue_idx;
2497         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2498                 txq->reg_idx = queue_idx;
2499         else /* PF device */
2500                 txq->reg_idx = vsi->base_queue +
2501                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2502
2503         txq->port_id = dev->data->port_id;
2504         txq->txq_flags = tx_conf->txq_flags;
2505         txq->vsi = vsi;
2506         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2507
2508         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2509         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2510
2511         /* Allocate software ring */
2512         txq->sw_ring =
2513                 rte_zmalloc_socket("i40e tx sw ring",
2514                                    sizeof(struct i40e_tx_entry) * nb_desc,
2515                                    RTE_CACHE_LINE_SIZE,
2516                                    socket_id);
2517         if (!txq->sw_ring) {
2518                 i40e_dev_tx_queue_release(txq);
2519                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2520                 return -ENOMEM;
2521         }
2522
2523         i40e_reset_tx_queue(txq);
2524         txq->q_set = TRUE;
2525         dev->data->tx_queues[queue_idx] = txq;
2526
2527         /* Use a simple TX queue without offloads or multi segs if possible */
2528         i40e_set_tx_function_flag(dev, txq);
2529
2530         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2531                 if (!(vsi->enabled_tc & (1 << i)))
2532                         continue;
2533                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2534                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2535                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2536                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2537                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2538
2539                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2540                         txq->dcb_tc = i;
2541         }
2542
2543         return 0;
2544 }
2545
2546 void
2547 i40e_dev_tx_queue_release(void *txq)
2548 {
2549         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2550
2551         if (!q) {
2552                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2553                 return;
2554         }
2555
2556         i40e_tx_queue_release_mbufs(q);
2557         rte_free(q->sw_ring);
2558         rte_free(q);
2559 }
2560
2561 const struct rte_memzone *
2562 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2563 {
2564         const struct rte_memzone *mz;
2565
2566         mz = rte_memzone_lookup(name);
2567         if (mz)
2568                 return mz;
2569
2570         if (rte_xen_dom0_supported())
2571                 mz = rte_memzone_reserve_bounded(name, len,
2572                                 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2573         else
2574                 mz = rte_memzone_reserve_aligned(name, len,
2575                                 socket_id, 0, I40E_RING_BASE_ALIGN);
2576         return mz;
2577 }
2578
2579 void
2580 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2581 {
2582         uint16_t i;
2583
2584         /* SSE Vector driver has a different way of releasing mbufs. */
2585         if (rxq->rx_using_sse) {
2586                 i40e_rx_queue_release_mbufs_vec(rxq);
2587                 return;
2588         }
2589
2590         if (!rxq || !rxq->sw_ring) {
2591                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2592                 return;
2593         }
2594
2595         for (i = 0; i < rxq->nb_rx_desc; i++) {
2596                 if (rxq->sw_ring[i].mbuf) {
2597                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2598                         rxq->sw_ring[i].mbuf = NULL;
2599                 }
2600         }
2601 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2602         if (rxq->rx_nb_avail == 0)
2603                 return;
2604         for (i = 0; i < rxq->rx_nb_avail; i++) {
2605                 struct rte_mbuf *mbuf;
2606
2607                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2608                 rte_pktmbuf_free_seg(mbuf);
2609         }
2610         rxq->rx_nb_avail = 0;
2611 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2612 }
2613
2614 void
2615 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2616 {
2617         unsigned i;
2618         uint16_t len;
2619
2620         if (!rxq) {
2621                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2622                 return;
2623         }
2624
2625 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2626         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2627                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2628         else
2629 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2630                 len = rxq->nb_rx_desc;
2631
2632         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2633                 ((volatile char *)rxq->rx_ring)[i] = 0;
2634
2635 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2636         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2637         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2638                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2639
2640         rxq->rx_nb_avail = 0;
2641         rxq->rx_next_avail = 0;
2642         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2643 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2644         rxq->rx_tail = 0;
2645         rxq->nb_rx_hold = 0;
2646         rxq->pkt_first_seg = NULL;
2647         rxq->pkt_last_seg = NULL;
2648
2649         rxq->rxrearm_start = 0;
2650         rxq->rxrearm_nb = 0;
2651 }
2652
2653 void
2654 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2655 {
2656         uint16_t i;
2657
2658         if (!txq || !txq->sw_ring) {
2659                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2660                 return;
2661         }
2662
2663         for (i = 0; i < txq->nb_tx_desc; i++) {
2664                 if (txq->sw_ring[i].mbuf) {
2665                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2666                         txq->sw_ring[i].mbuf = NULL;
2667                 }
2668         }
2669 }
2670
2671 void
2672 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2673 {
2674         struct i40e_tx_entry *txe;
2675         uint16_t i, prev, size;
2676
2677         if (!txq) {
2678                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2679                 return;
2680         }
2681
2682         txe = txq->sw_ring;
2683         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2684         for (i = 0; i < size; i++)
2685                 ((volatile char *)txq->tx_ring)[i] = 0;
2686
2687         prev = (uint16_t)(txq->nb_tx_desc - 1);
2688         for (i = 0; i < txq->nb_tx_desc; i++) {
2689                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2690
2691                 txd->cmd_type_offset_bsz =
2692                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2693                 txe[i].mbuf =  NULL;
2694                 txe[i].last_id = i;
2695                 txe[prev].next_id = i;
2696                 prev = i;
2697         }
2698
2699         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2700         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2701
2702         txq->tx_tail = 0;
2703         txq->nb_tx_used = 0;
2704
2705         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2706         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2707 }
2708
2709 /* Init the TX queue in hardware */
2710 int
2711 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2712 {
2713         enum i40e_status_code err = I40E_SUCCESS;
2714         struct i40e_vsi *vsi = txq->vsi;
2715         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2716         uint16_t pf_q = txq->reg_idx;
2717         struct i40e_hmc_obj_txq tx_ctx;
2718         uint32_t qtx_ctl;
2719
2720         /* clear the context structure first */
2721         memset(&tx_ctx, 0, sizeof(tx_ctx));
2722         tx_ctx.new_context = 1;
2723         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2724         tx_ctx.qlen = txq->nb_tx_desc;
2725
2726 #ifdef RTE_LIBRTE_IEEE1588
2727         tx_ctx.timesync_ena = 1;
2728 #endif
2729         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2730         if (vsi->type == I40E_VSI_FDIR)
2731                 tx_ctx.fd_ena = TRUE;
2732
2733         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2734         if (err != I40E_SUCCESS) {
2735                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2736                 return err;
2737         }
2738
2739         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2740         if (err != I40E_SUCCESS) {
2741                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2742                 return err;
2743         }
2744
2745         /* Now associate this queue with this PCI function */
2746         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2747         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2748                                         I40E_QTX_CTL_PF_INDX_MASK);
2749         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2750         I40E_WRITE_FLUSH(hw);
2751
2752         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2753
2754         return err;
2755 }
2756
2757 int
2758 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2759 {
2760         struct i40e_rx_entry *rxe = rxq->sw_ring;
2761         uint64_t dma_addr;
2762         uint16_t i;
2763
2764         for (i = 0; i < rxq->nb_rx_desc; i++) {
2765                 volatile union i40e_rx_desc *rxd;
2766                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2767
2768                 if (unlikely(!mbuf)) {
2769                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2770                         return -ENOMEM;
2771                 }
2772
2773                 rte_mbuf_refcnt_set(mbuf, 1);
2774                 mbuf->next = NULL;
2775                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2776                 mbuf->nb_segs = 1;
2777                 mbuf->port = rxq->port_id;
2778
2779                 dma_addr =
2780                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2781
2782                 rxd = &rxq->rx_ring[i];
2783                 rxd->read.pkt_addr = dma_addr;
2784                 rxd->read.hdr_addr = 0;
2785 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2786                 rxd->read.rsvd1 = 0;
2787                 rxd->read.rsvd2 = 0;
2788 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2789
2790                 rxe[i].mbuf = mbuf;
2791         }
2792
2793         return 0;
2794 }
2795
2796 /*
2797  * Calculate the buffer length, and check the jumbo frame
2798  * and maximum packet length.
2799  */
2800 static int
2801 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2802 {
2803         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2804         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2805         struct rte_eth_dev_data *data = pf->dev_data;
2806         uint16_t buf_size, len;
2807
2808         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2809                 RTE_PKTMBUF_HEADROOM);
2810
2811         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2812                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2813         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2814                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2815                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2816                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2817                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2818                 rxq->hs_mode = i40e_header_split_enabled;
2819                 break;
2820         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2821         default:
2822                 rxq->rx_hdr_len = 0;
2823                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2824                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2825                 rxq->hs_mode = i40e_header_split_none;
2826                 break;
2827         }
2828
2829         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2830         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2831         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2832                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2833                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2834                         PMD_DRV_LOG(ERR, "maximum packet length must "
2835                                     "be larger than %u and smaller than %u,"
2836                                     "as jumbo frame is enabled",
2837                                     (uint32_t)ETHER_MAX_LEN,
2838                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2839                         return I40E_ERR_CONFIG;
2840                 }
2841         } else {
2842                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2843                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2844                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2845                                     "larger than %u and smaller than %u, "
2846                                     "as jumbo frame is disabled",
2847                                     (uint32_t)ETHER_MIN_LEN,
2848                                     (uint32_t)ETHER_MAX_LEN);
2849                         return I40E_ERR_CONFIG;
2850                 }
2851         }
2852
2853         return 0;
2854 }
2855
2856 /* Init the RX queue in hardware */
2857 int
2858 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2859 {
2860         int err = I40E_SUCCESS;
2861         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2862         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2863         uint16_t pf_q = rxq->reg_idx;
2864         uint16_t buf_size;
2865         struct i40e_hmc_obj_rxq rx_ctx;
2866
2867         err = i40e_rx_queue_config(rxq);
2868         if (err < 0) {
2869                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2870                 return err;
2871         }
2872
2873         /* Clear the context structure first */
2874         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2875         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2876         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2877
2878         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2879         rx_ctx.qlen = rxq->nb_rx_desc;
2880 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2881         rx_ctx.dsize = 1;
2882 #endif
2883         rx_ctx.dtype = rxq->hs_mode;
2884         if (rxq->hs_mode)
2885                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2886         else
2887                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2888         rx_ctx.rxmax = rxq->max_pkt_len;
2889         rx_ctx.tphrdesc_ena = 1;
2890         rx_ctx.tphwdesc_ena = 1;
2891         rx_ctx.tphdata_ena = 1;
2892         rx_ctx.tphhead_ena = 1;
2893         rx_ctx.lrxqthresh = 2;
2894         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2895         rx_ctx.l2tsel = 1;
2896         /* showiv indicates if inner VLAN is stripped inside of tunnel
2897          * packet. When set it to 1, vlan information is stripped from
2898          * the inner header, but the hardware does not put it in the
2899          * descriptor. So set it zero by default.
2900          */
2901         rx_ctx.showiv = 0;
2902         rx_ctx.prefena = 1;
2903
2904         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2905         if (err != I40E_SUCCESS) {
2906                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2907                 return err;
2908         }
2909         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2910         if (err != I40E_SUCCESS) {
2911                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2912                 return err;
2913         }
2914
2915         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2916
2917         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2918                 RTE_PKTMBUF_HEADROOM);
2919
2920         /* Check if scattered RX needs to be used. */
2921         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2922                 dev_data->scattered_rx = 1;
2923         }
2924
2925         /* Init the RX tail regieter. */
2926         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2927
2928         return 0;
2929 }
2930
2931 void
2932 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2933 {
2934         uint16_t i;
2935
2936         PMD_INIT_FUNC_TRACE();
2937
2938         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2939                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2940                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2941         }
2942
2943         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2944                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2945                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2946         }
2947 }
2948
2949 void
2950 i40e_dev_free_queues(struct rte_eth_dev *dev)
2951 {
2952         uint16_t i;
2953
2954         PMD_INIT_FUNC_TRACE();
2955
2956         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2957                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2958                 dev->data->rx_queues[i] = NULL;
2959         }
2960         dev->data->nb_rx_queues = 0;
2961
2962         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2963                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2964                 dev->data->tx_queues[i] = NULL;
2965         }
2966         dev->data->nb_tx_queues = 0;
2967 }
2968
2969 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2970 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2971
2972 enum i40e_status_code
2973 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2974 {
2975         struct i40e_tx_queue *txq;
2976         const struct rte_memzone *tz = NULL;
2977         uint32_t ring_size;
2978         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2979
2980         if (!pf) {
2981                 PMD_DRV_LOG(ERR, "PF is not available");
2982                 return I40E_ERR_BAD_PTR;
2983         }
2984
2985         /* Allocate the TX queue data structure. */
2986         txq = rte_zmalloc_socket("i40e fdir tx queue",
2987                                   sizeof(struct i40e_tx_queue),
2988                                   RTE_CACHE_LINE_SIZE,
2989                                   SOCKET_ID_ANY);
2990         if (!txq) {
2991                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2992                                         "tx queue structure.");
2993                 return I40E_ERR_NO_MEMORY;
2994         }
2995
2996         /* Allocate TX hardware ring descriptors. */
2997         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2998         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2999
3000         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
3001                                       I40E_FDIR_QUEUE_ID, ring_size,
3002                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3003         if (!tz) {
3004                 i40e_dev_tx_queue_release(txq);
3005                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
3006                 return I40E_ERR_NO_MEMORY;
3007         }
3008
3009         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
3010         txq->queue_id = I40E_FDIR_QUEUE_ID;
3011         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3012         txq->vsi = pf->fdir.fdir_vsi;
3013
3014         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
3015         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
3016         /*
3017          * don't need to allocate software ring and reset for the fdir
3018          * program queue just set the queue has been configured.
3019          */
3020         txq->q_set = TRUE;
3021         pf->fdir.txq = txq;
3022
3023         return I40E_SUCCESS;
3024 }
3025
3026 enum i40e_status_code
3027 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3028 {
3029         struct i40e_rx_queue *rxq;
3030         const struct rte_memzone *rz = NULL;
3031         uint32_t ring_size;
3032         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3033
3034         if (!pf) {
3035                 PMD_DRV_LOG(ERR, "PF is not available");
3036                 return I40E_ERR_BAD_PTR;
3037         }
3038
3039         /* Allocate the RX queue data structure. */
3040         rxq = rte_zmalloc_socket("i40e fdir rx queue",
3041                                   sizeof(struct i40e_rx_queue),
3042                                   RTE_CACHE_LINE_SIZE,
3043                                   SOCKET_ID_ANY);
3044         if (!rxq) {
3045                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3046                                         "rx queue structure.");
3047                 return I40E_ERR_NO_MEMORY;
3048         }
3049
3050         /* Allocate RX hardware ring descriptors. */
3051         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3052         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3053
3054         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3055                                       I40E_FDIR_QUEUE_ID, ring_size,
3056                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3057         if (!rz) {
3058                 i40e_dev_rx_queue_release(rxq);
3059                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3060                 return I40E_ERR_NO_MEMORY;
3061         }
3062
3063         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3064         rxq->queue_id = I40E_FDIR_QUEUE_ID;
3065         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3066         rxq->vsi = pf->fdir.fdir_vsi;
3067
3068         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
3069         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3070
3071         /*
3072          * Don't need to allocate software ring and reset for the fdir
3073          * rx queue, just set the queue has been configured.
3074          */
3075         rxq->q_set = TRUE;
3076         pf->fdir.rxq = rxq;
3077
3078         return I40E_SUCCESS;
3079 }
3080
3081 void
3082 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3083         struct rte_eth_rxq_info *qinfo)
3084 {
3085         struct i40e_rx_queue *rxq;
3086
3087         rxq = dev->data->rx_queues[queue_id];
3088
3089         qinfo->mp = rxq->mp;
3090         qinfo->scattered_rx = dev->data->scattered_rx;
3091         qinfo->nb_desc = rxq->nb_rx_desc;
3092
3093         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3094         qinfo->conf.rx_drop_en = rxq->drop_en;
3095         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3096 }
3097
3098 void
3099 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3100         struct rte_eth_txq_info *qinfo)
3101 {
3102         struct i40e_tx_queue *txq;
3103
3104         txq = dev->data->tx_queues[queue_id];
3105
3106         qinfo->nb_desc = txq->nb_tx_desc;
3107
3108         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3109         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3110         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3111
3112         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3113         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3114         qinfo->conf.txq_flags = txq->txq_flags;
3115         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3116 }
3117
3118 void __attribute__((cold))
3119 i40e_set_rx_function(struct rte_eth_dev *dev)
3120 {
3121         struct i40e_adapter *ad =
3122                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3123         uint16_t rx_using_sse, i;
3124         /* In order to allow Vector Rx there are a few configuration
3125          * conditions to be met and Rx Bulk Allocation should be allowed.
3126          */
3127         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3128                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3129                     !ad->rx_bulk_alloc_allowed) {
3130                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3131                                      " Vector Rx preconditions",
3132                                      dev->data->port_id);
3133
3134                         ad->rx_vec_allowed = false;
3135                 }
3136                 if (ad->rx_vec_allowed) {
3137                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3138                                 struct i40e_rx_queue *rxq =
3139                                         dev->data->rx_queues[i];
3140
3141                                 if (i40e_rxq_vec_setup(rxq)) {
3142                                         ad->rx_vec_allowed = false;
3143                                         break;
3144                                 }
3145                         }
3146                 }
3147         }
3148
3149         if (dev->data->scattered_rx) {
3150                 /* Set the non-LRO scattered callback: there are Vector and
3151                  * single allocation versions.
3152                  */
3153                 if (ad->rx_vec_allowed) {
3154                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
3155                                             "callback (port=%d).",
3156                                      dev->data->port_id);
3157
3158                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3159                 } else {
3160                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
3161                                            "allocation callback (port=%d).",
3162                                      dev->data->port_id);
3163                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
3164                 }
3165         /* If parameters allow we are going to choose between the following
3166          * callbacks:
3167          *    - Vector
3168          *    - Bulk Allocation
3169          *    - Single buffer allocation (the simplest one)
3170          */
3171         } else if (ad->rx_vec_allowed) {
3172                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
3173                                     "burst size no less than %d (port=%d).",
3174                              RTE_I40E_DESCS_PER_LOOP,
3175                              dev->data->port_id);
3176
3177                 dev->rx_pkt_burst = i40e_recv_pkts_vec;
3178         } else if (ad->rx_bulk_alloc_allowed) {
3179                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3180                                     "satisfied. Rx Burst Bulk Alloc function "
3181                                     "will be used on port=%d.",
3182                              dev->data->port_id);
3183
3184                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3185         } else {
3186                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
3187                                     "satisfied, or Scattered Rx is requested "
3188                                     "(port=%d).",
3189                              dev->data->port_id);
3190
3191                 dev->rx_pkt_burst = i40e_recv_pkts;
3192         }
3193
3194         /* Propagate information about RX function choice through all queues. */
3195         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3196                 rx_using_sse =
3197                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3198                          dev->rx_pkt_burst == i40e_recv_pkts_vec);
3199
3200                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3201                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3202
3203                         rxq->rx_using_sse = rx_using_sse;
3204                 }
3205         }
3206 }
3207
3208 void __attribute__((cold))
3209 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3210 {
3211         struct i40e_adapter *ad =
3212                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3213
3214         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
3215         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
3216                         && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
3217                 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
3218                         PMD_INIT_LOG(DEBUG, "Vector tx"
3219                                      " can be enabled on this txq.");
3220
3221                 } else {
3222                         ad->tx_vec_allowed = false;
3223                 }
3224         } else {
3225                 ad->tx_simple_allowed = false;
3226         }
3227 }
3228
3229 void __attribute__((cold))
3230 i40e_set_tx_function(struct rte_eth_dev *dev)
3231 {
3232         struct i40e_adapter *ad =
3233                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3234         int i;
3235
3236         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3237                 if (ad->tx_vec_allowed) {
3238                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3239                                 struct i40e_tx_queue *txq =
3240                                         dev->data->tx_queues[i];
3241
3242                                 if (i40e_txq_vec_setup(txq)) {
3243                                         ad->tx_vec_allowed = false;
3244                                         break;
3245                                 }
3246                         }
3247                 }
3248         }
3249
3250         if (ad->tx_simple_allowed) {
3251                 if (ad->tx_vec_allowed) {
3252                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3253                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3254                 } else {
3255                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3256                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3257                 }
3258         } else {
3259                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3260                 dev->tx_pkt_burst = i40e_xmit_pkts;
3261         }
3262 }
3263
3264 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
3265 int __attribute__((weak))
3266 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3267 {
3268         return -1;
3269 }
3270
3271 uint16_t __attribute__((weak))
3272 i40e_recv_pkts_vec(
3273         void __rte_unused *rx_queue,
3274         struct rte_mbuf __rte_unused **rx_pkts,
3275         uint16_t __rte_unused nb_pkts)
3276 {
3277         return 0;
3278 }
3279
3280 uint16_t __attribute__((weak))
3281 i40e_recv_scattered_pkts_vec(
3282         void __rte_unused *rx_queue,
3283         struct rte_mbuf __rte_unused **rx_pkts,
3284         uint16_t __rte_unused nb_pkts)
3285 {
3286         return 0;
3287 }
3288
3289 int __attribute__((weak))
3290 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3291 {
3292         return -1;
3293 }
3294
3295 int __attribute__((weak))
3296 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3297 {
3298         return -1;
3299 }
3300
3301 void __attribute__((weak))
3302 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3303 {
3304         return;
3305 }
3306
3307 uint16_t __attribute__((weak))
3308 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
3309                    struct rte_mbuf __rte_unused **tx_pkts,
3310                    uint16_t __rte_unused nb_pkts)
3311 {
3312         return 0;
3313 }