drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59
  60 #define I40E_MIN_RING_DESC     64
  61 #define I40E_MAX_RING_DESC     4096
  62 #define I40E_ALIGN             128
  63 #define DEFAULT_TX_RS_THRESH   32
  64 #define DEFAULT_TX_FREE_THRESH 32
  65 #define I40E_MAX_PKT_TYPE      256
  66
  67 #define I40E_TX_MAX_BURST  32
  68
  69 #define I40E_DMA_MEM_ALIGN 4096
  70
  71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  72                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  73
  74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  75
  76 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  77                 PKT_TX_IP_CKSUM |                \
  78                 PKT_TX_L4_MASK |                 \
  79                 PKT_TX_OUTER_IP_CKSUM)
  80
  81 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
  82         (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
  83
  84 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
  85         ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
  86
  87 static const struct rte_memzone *
  88 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
  89                            const char *ring_name,
  90                            uint16_t queue_id,
  91                            uint32_t ring_size,
  92                            int socket_id);
  93 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  94                                       struct rte_mbuf **tx_pkts,
  95                                       uint16_t nb_pkts);
  96
  97 static inline void
  98 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  99 {
 100         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 101                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 102                 mb->ol_flags |= PKT_RX_VLAN_PKT;
 103                 mb->vlan_tci =
 104                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 105                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
 106                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
 107         } else {
 108                 mb->vlan_tci = 0;
 109         }
 110 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 111         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 112                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 113                 mb->ol_flags |= PKT_RX_QINQ_PKT;
 114                 mb->vlan_tci_outer = mb->vlan_tci;
 115                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 116                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 117                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 118                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 119         } else {
 120                 mb->vlan_tci_outer = 0;
 121         }
 122 #endif
 123         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 124                    mb->vlan_tci, mb->vlan_tci_outer);
 125 }
 126
 127 /* Translate the rx descriptor status to pkt flags */
 128 static inline uint64_t
 129 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 130 {
 131         uint64_t flags;
 132
 133         /* Check if RSS_HASH */
 134         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 135                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 136                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 137
 138         /* Check if FDIR Match */
 139         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 140                                                         PKT_RX_FDIR : 0);
 141
 142         return flags;
 143 }
 144
 145 static inline uint64_t
 146 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 147 {
 148         uint64_t flags = 0;
 149         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 150
 151 #define I40E_RX_ERR_BITS 0x3f
 152         if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
 153                 return flags;
 154         /* If RXE bit set, all other status bits are meaningless */
 155         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
 156                 flags |= PKT_RX_MAC_ERR;
 157                 return flags;
 158         }
 159
 160         /* If RECIPE bit set, all other status indications should be ignored */
 161         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
 162                 flags |= PKT_RX_RECIP_ERR;
 163                 return flags;
 164         }
 165         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
 166                 flags |= PKT_RX_HBUF_OVERFLOW;
 167         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 168                 flags |= PKT_RX_IP_CKSUM_BAD;
 169         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 170                 flags |= PKT_RX_L4_CKSUM_BAD;
 171         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 172                 flags |= PKT_RX_EIP_CKSUM_BAD;
 173         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
 174                 flags |= PKT_RX_OVERSIZE;
 175
 176         return flags;
 177 }
 178
 179 /* Function to check and set the ieee1588 timesync index and get the
 180  * appropriate flags.
 181  */
 182 #ifdef RTE_LIBRTE_IEEE1588
 183 static inline uint64_t
 184 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 185 {
 186         uint64_t pkt_flags = 0;
 187         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 188                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 189                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 190
 191         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 192                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 193                 pkt_flags = PKT_RX_IEEE1588_PTP;
 194         if (tsyn & 0x04) {
 195                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 196                 mb->timesync = tsyn & 0x03;
 197         }
 198
 199         return pkt_flags;
 200 }
 201 #endif
 202
 203 /* For each value it means, datasheet of hardware can tell more details */
 204 static inline uint32_t
 205 i40e_rxd_pkt_type_mapping(uint8_t ptype)
 206 {
 207         static const uint32_t ptype_table[UINT8_MAX] __rte_cache_aligned = {
 208                 /* L2 types */
 209                 /* [0] reserved */
 210                 [1] = RTE_PTYPE_L2_ETHER,
 211                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
 212                 /* [3] - [5] reserved */
 213                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
 214                 /* [7] - [10] reserved */
 215                 [11] = RTE_PTYPE_L2_ETHER_ARP,
 216                 /* [12] - [21] reserved */
 217
 218                 /* Non tunneled IPv4 */
 219                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 220                         RTE_PTYPE_L4_FRAG,
 221                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 222                         RTE_PTYPE_L4_NONFRAG,
 223                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 224                         RTE_PTYPE_L4_UDP,
 225                 /* [25] reserved */
 226                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 227                         RTE_PTYPE_L4_TCP,
 228                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 229                         RTE_PTYPE_L4_SCTP,
 230                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 231                         RTE_PTYPE_L4_ICMP,
 232
 233                 /* IPv4 --> IPv4 */
 234                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 235                         RTE_PTYPE_TUNNEL_IP |
 236                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 237                         RTE_PTYPE_INNER_L4_FRAG,
 238                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 239                         RTE_PTYPE_TUNNEL_IP |
 240                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 241                         RTE_PTYPE_INNER_L4_NONFRAG,
 242                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 243                         RTE_PTYPE_TUNNEL_IP |
 244                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 245                         RTE_PTYPE_INNER_L4_UDP,
 246                 /* [32] reserved */
 247                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 248                         RTE_PTYPE_TUNNEL_IP |
 249                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 250                         RTE_PTYPE_INNER_L4_TCP,
 251                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 252                         RTE_PTYPE_TUNNEL_IP |
 253                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 254                         RTE_PTYPE_INNER_L4_SCTP,
 255                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 256                         RTE_PTYPE_TUNNEL_IP |
 257                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 258                         RTE_PTYPE_INNER_L4_ICMP,
 259
 260                 /* IPv4 --> IPv6 */
 261                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 262                         RTE_PTYPE_TUNNEL_IP |
 263                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 264                         RTE_PTYPE_INNER_L4_FRAG,
 265                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 266                         RTE_PTYPE_TUNNEL_IP |
 267                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 268                         RTE_PTYPE_INNER_L4_NONFRAG,
 269                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 270                         RTE_PTYPE_TUNNEL_IP |
 271                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 272                         RTE_PTYPE_INNER_L4_UDP,
 273                 /* [39] reserved */
 274                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 275                         RTE_PTYPE_TUNNEL_IP |
 276                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 277                         RTE_PTYPE_INNER_L4_TCP,
 278                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 279                         RTE_PTYPE_TUNNEL_IP |
 280                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 281                         RTE_PTYPE_INNER_L4_SCTP,
 282                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 283                         RTE_PTYPE_TUNNEL_IP |
 284                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 285                         RTE_PTYPE_INNER_L4_ICMP,
 286
 287                 /* IPv4 --> GRE/Teredo/VXLAN */
 288                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 289                         RTE_PTYPE_TUNNEL_GRENAT,
 290
 291                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
 292                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 293                         RTE_PTYPE_TUNNEL_GRENAT |
 294                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 295                         RTE_PTYPE_INNER_L4_FRAG,
 296                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 297                         RTE_PTYPE_TUNNEL_GRENAT |
 298                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 299                         RTE_PTYPE_INNER_L4_NONFRAG,
 300                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 301                         RTE_PTYPE_TUNNEL_GRENAT |
 302                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 303                         RTE_PTYPE_INNER_L4_UDP,
 304                 /* [47] reserved */
 305                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 306                         RTE_PTYPE_TUNNEL_GRENAT |
 307                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 308                         RTE_PTYPE_INNER_L4_TCP,
 309                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 310                         RTE_PTYPE_TUNNEL_GRENAT |
 311                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 312                         RTE_PTYPE_INNER_L4_SCTP,
 313                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 314                         RTE_PTYPE_TUNNEL_GRENAT |
 315                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 316                         RTE_PTYPE_INNER_L4_ICMP,
 317
 318                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
 319                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 320                         RTE_PTYPE_TUNNEL_GRENAT |
 321                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 322                         RTE_PTYPE_INNER_L4_FRAG,
 323                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 324                         RTE_PTYPE_TUNNEL_GRENAT |
 325                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 326                         RTE_PTYPE_INNER_L4_NONFRAG,
 327                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 328                         RTE_PTYPE_TUNNEL_GRENAT |
 329                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 330                         RTE_PTYPE_INNER_L4_UDP,
 331                 /* [54] reserved */
 332                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 333                         RTE_PTYPE_TUNNEL_GRENAT |
 334                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 335                         RTE_PTYPE_INNER_L4_TCP,
 336                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 337                         RTE_PTYPE_TUNNEL_GRENAT |
 338                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 339                         RTE_PTYPE_INNER_L4_SCTP,
 340                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 341                         RTE_PTYPE_TUNNEL_GRENAT |
 342                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 343                         RTE_PTYPE_INNER_L4_ICMP,
 344
 345                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
 346                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 347                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
 348
 349                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
 350                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 351                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 352                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 353                         RTE_PTYPE_INNER_L4_FRAG,
 354                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 355                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 356                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 357                         RTE_PTYPE_INNER_L4_NONFRAG,
 358                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 359                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 360                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 361                         RTE_PTYPE_INNER_L4_UDP,
 362                 /* [62] reserved */
 363                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 364                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 365                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 366                         RTE_PTYPE_INNER_L4_TCP,
 367                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 368                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 369                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 370                         RTE_PTYPE_INNER_L4_SCTP,
 371                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 372                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 373                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 374                         RTE_PTYPE_INNER_L4_ICMP,
 375
 376                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
 377                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 378                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 379                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 380                         RTE_PTYPE_INNER_L4_FRAG,
 381                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 382                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 383                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 384                         RTE_PTYPE_INNER_L4_NONFRAG,
 385                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 386                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 387                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 388                         RTE_PTYPE_INNER_L4_UDP,
 389                 /* [69] reserved */
 390                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 391                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 392                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 393                         RTE_PTYPE_INNER_L4_TCP,
 394                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 395                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 396                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 397                         RTE_PTYPE_INNER_L4_SCTP,
 398                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 399                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 400                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 401                         RTE_PTYPE_INNER_L4_ICMP,
 402
 403                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
 404                 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 405                         RTE_PTYPE_TUNNEL_GRENAT |
 406                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
 407
 408                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
 409                 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 410                         RTE_PTYPE_TUNNEL_GRENAT |
 411                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 412                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 413                         RTE_PTYPE_INNER_L4_FRAG,
 414                 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 415                         RTE_PTYPE_TUNNEL_GRENAT |
 416                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 417                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 418                         RTE_PTYPE_INNER_L4_NONFRAG,
 419                 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 420                         RTE_PTYPE_TUNNEL_GRENAT |
 421                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 422                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 423                         RTE_PTYPE_INNER_L4_UDP,
 424                 /* [77] reserved */
 425                 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 426                         RTE_PTYPE_TUNNEL_GRENAT |
 427                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 428                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 429                         RTE_PTYPE_INNER_L4_TCP,
 430                 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 431                         RTE_PTYPE_TUNNEL_GRENAT |
 432                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 433                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 434                         RTE_PTYPE_INNER_L4_SCTP,
 435                 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 436                         RTE_PTYPE_TUNNEL_GRENAT |
 437                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 438                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 439                         RTE_PTYPE_INNER_L4_ICMP,
 440
 441                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
 442                 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 443                         RTE_PTYPE_TUNNEL_GRENAT |
 444                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 445                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 446                         RTE_PTYPE_INNER_L4_FRAG,
 447                 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 448                         RTE_PTYPE_TUNNEL_GRENAT |
 449                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 450                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 451                         RTE_PTYPE_INNER_L4_NONFRAG,
 452                 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 453                         RTE_PTYPE_TUNNEL_GRENAT |
 454                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 455                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 456                         RTE_PTYPE_INNER_L4_UDP,
 457                 /* [84] reserved */
 458                 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 459                         RTE_PTYPE_TUNNEL_GRENAT |
 460                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 461                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 462                         RTE_PTYPE_INNER_L4_TCP,
 463                 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 464                         RTE_PTYPE_TUNNEL_GRENAT |
 465                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 466                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 467                         RTE_PTYPE_INNER_L4_SCTP,
 468                 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 469                         RTE_PTYPE_TUNNEL_GRENAT |
 470                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 471                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 472                         RTE_PTYPE_INNER_L4_ICMP,
 473
 474                 /* Non tunneled IPv6 */
 475                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 476                         RTE_PTYPE_L4_FRAG,
 477                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 478                         RTE_PTYPE_L4_NONFRAG,
 479                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 480                         RTE_PTYPE_L4_UDP,
 481                 /* [91] reserved */
 482                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 483                         RTE_PTYPE_L4_TCP,
 484                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 485                         RTE_PTYPE_L4_SCTP,
 486                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 487                         RTE_PTYPE_L4_ICMP,
 488
 489                 /* IPv6 --> IPv4 */
 490                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 491                         RTE_PTYPE_TUNNEL_IP |
 492                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 493                         RTE_PTYPE_INNER_L4_FRAG,
 494                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 495                         RTE_PTYPE_TUNNEL_IP |
 496                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 497                         RTE_PTYPE_INNER_L4_NONFRAG,
 498                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 499                         RTE_PTYPE_TUNNEL_IP |
 500                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 501                         RTE_PTYPE_INNER_L4_UDP,
 502                 /* [98] reserved */
 503                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 504                         RTE_PTYPE_TUNNEL_IP |
 505                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 506                         RTE_PTYPE_INNER_L4_TCP,
 507                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 508                         RTE_PTYPE_TUNNEL_IP |
 509                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 510                         RTE_PTYPE_INNER_L4_SCTP,
 511                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 512                         RTE_PTYPE_TUNNEL_IP |
 513                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 514                         RTE_PTYPE_INNER_L4_ICMP,
 515
 516                 /* IPv6 --> IPv6 */
 517                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 518                         RTE_PTYPE_TUNNEL_IP |
 519                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 520                         RTE_PTYPE_INNER_L4_FRAG,
 521                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 522                         RTE_PTYPE_TUNNEL_IP |
 523                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 524                         RTE_PTYPE_INNER_L4_NONFRAG,
 525                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 526                         RTE_PTYPE_TUNNEL_IP |
 527                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 528                         RTE_PTYPE_INNER_L4_UDP,
 529                 /* [105] reserved */
 530                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 531                         RTE_PTYPE_TUNNEL_IP |
 532                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 533                         RTE_PTYPE_INNER_L4_TCP,
 534                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 535                         RTE_PTYPE_TUNNEL_IP |
 536                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 537                         RTE_PTYPE_INNER_L4_SCTP,
 538                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 539                         RTE_PTYPE_TUNNEL_IP |
 540                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 541                         RTE_PTYPE_INNER_L4_ICMP,
 542
 543                 /* IPv6 --> GRE/Teredo/VXLAN */
 544                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 545                         RTE_PTYPE_TUNNEL_GRENAT,
 546
 547                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
 548                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 549                         RTE_PTYPE_TUNNEL_GRENAT |
 550                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 551                         RTE_PTYPE_INNER_L4_FRAG,
 552                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 553                         RTE_PTYPE_TUNNEL_GRENAT |
 554                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 555                         RTE_PTYPE_INNER_L4_NONFRAG,
 556                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 557                         RTE_PTYPE_TUNNEL_GRENAT |
 558                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 559                         RTE_PTYPE_INNER_L4_UDP,
 560                 /* [113] reserved */
 561                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 562                         RTE_PTYPE_TUNNEL_GRENAT |
 563                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 564                         RTE_PTYPE_INNER_L4_TCP,
 565                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 566                         RTE_PTYPE_TUNNEL_GRENAT |
 567                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 568                         RTE_PTYPE_INNER_L4_SCTP,
 569                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 570                         RTE_PTYPE_TUNNEL_GRENAT |
 571                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 572                         RTE_PTYPE_INNER_L4_ICMP,
 573
 574                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
 575                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 576                         RTE_PTYPE_TUNNEL_GRENAT |
 577                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 578                         RTE_PTYPE_INNER_L4_FRAG,
 579                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 580                         RTE_PTYPE_TUNNEL_GRENAT |
 581                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 582                         RTE_PTYPE_INNER_L4_NONFRAG,
 583                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 584                         RTE_PTYPE_TUNNEL_GRENAT |
 585                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 586                         RTE_PTYPE_INNER_L4_UDP,
 587                 /* [120] reserved */
 588                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 589                         RTE_PTYPE_TUNNEL_GRENAT |
 590                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 591                         RTE_PTYPE_INNER_L4_TCP,
 592                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 593                         RTE_PTYPE_TUNNEL_GRENAT |
 594                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 595                         RTE_PTYPE_INNER_L4_SCTP,
 596                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 597                         RTE_PTYPE_TUNNEL_GRENAT |
 598                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 599                         RTE_PTYPE_INNER_L4_ICMP,
 600
 601                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
 602                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 603                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
 604
 605                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
 606                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 607                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 608                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 609                         RTE_PTYPE_INNER_L4_FRAG,
 610                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 611                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 612                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 613                         RTE_PTYPE_INNER_L4_NONFRAG,
 614                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 615                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 616                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 617                         RTE_PTYPE_INNER_L4_UDP,
 618                 /* [128] reserved */
 619                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 620                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 621                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 622                         RTE_PTYPE_INNER_L4_TCP,
 623                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 624                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 625                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 626                         RTE_PTYPE_INNER_L4_SCTP,
 627                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 628                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 629                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 630                         RTE_PTYPE_INNER_L4_ICMP,
 631
 632                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
 633                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 634                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 635                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 636                         RTE_PTYPE_INNER_L4_FRAG,
 637                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 638                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 639                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 640                         RTE_PTYPE_INNER_L4_NONFRAG,
 641                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 642                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 643                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 644                         RTE_PTYPE_INNER_L4_UDP,
 645                 /* [135] reserved */
 646                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 647                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 648                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 649                         RTE_PTYPE_INNER_L4_TCP,
 650                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 651                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 652                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 653                         RTE_PTYPE_INNER_L4_SCTP,
 654                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 655                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 656                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 657                         RTE_PTYPE_INNER_L4_ICMP,
 658
 659                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
 660                 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 661                         RTE_PTYPE_TUNNEL_GRENAT |
 662                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
 663
 664                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
 665                 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 666                         RTE_PTYPE_TUNNEL_GRENAT |
 667                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 668                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 669                         RTE_PTYPE_INNER_L4_FRAG,
 670                 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 671                         RTE_PTYPE_TUNNEL_GRENAT |
 672                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 673                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 674                         RTE_PTYPE_INNER_L4_NONFRAG,
 675                 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 676                         RTE_PTYPE_TUNNEL_GRENAT |
 677                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 678                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 679                         RTE_PTYPE_INNER_L4_UDP,
 680                 /* [143] reserved */
 681                 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 682                         RTE_PTYPE_TUNNEL_GRENAT |
 683                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 684                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 685                         RTE_PTYPE_INNER_L4_TCP,
 686                 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 687                         RTE_PTYPE_TUNNEL_GRENAT |
 688                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 689                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 690                         RTE_PTYPE_INNER_L4_SCTP,
 691                 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 692                         RTE_PTYPE_TUNNEL_GRENAT |
 693                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 694                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 695                         RTE_PTYPE_INNER_L4_ICMP,
 696
 697                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
 698                 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 699                         RTE_PTYPE_TUNNEL_GRENAT |
 700                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 701                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 702                         RTE_PTYPE_INNER_L4_FRAG,
 703                 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 704                         RTE_PTYPE_TUNNEL_GRENAT |
 705                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 706                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 707                         RTE_PTYPE_INNER_L4_NONFRAG,
 708                 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 709                         RTE_PTYPE_TUNNEL_GRENAT |
 710                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 711                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 712                         RTE_PTYPE_INNER_L4_UDP,
 713                 /* [150] reserved */
 714                 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 715                         RTE_PTYPE_TUNNEL_GRENAT |
 716                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 717                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 718                         RTE_PTYPE_INNER_L4_TCP,
 719                 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 720                         RTE_PTYPE_TUNNEL_GRENAT |
 721                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 722                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 723                         RTE_PTYPE_INNER_L4_SCTP,
 724                 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 725                         RTE_PTYPE_TUNNEL_GRENAT |
 726                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 727                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 728                         RTE_PTYPE_INNER_L4_ICMP,
 729
 730                 /* All others reserved */
 731         };
 732
 733         return ptype_table[ptype];
 734 }
 735
 736 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 737 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 738 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 739 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 740 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 741
 742 static inline uint64_t
 743 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 744 {
 745         uint64_t flags = 0;
 746 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 747         uint16_t flexbh, flexbl;
 748
 749         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 750                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 751                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 752         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 753                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 754                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 755
 756
 757         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 758                 mb->hash.fdir.hi =
 759                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 760                 flags |= PKT_RX_FDIR_ID;
 761         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 762                 mb->hash.fdir.hi =
 763                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 764                 flags |= PKT_RX_FDIR_FLX;
 765         }
 766         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 767                 mb->hash.fdir.lo =
 768                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 769                 flags |= PKT_RX_FDIR_FLX;
 770         }
 771 #else
 772         mb->hash.fdir.hi =
 773                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 774         flags |= PKT_RX_FDIR_ID;
 775 #endif
 776         return flags;
 777 }
 778 static inline void
 779 i40e_txd_enable_checksum(uint64_t ol_flags,
 780                         uint32_t *td_cmd,
 781                         uint32_t *td_offset,
 782                         union i40e_tx_offload tx_offload,
 783                         uint32_t *cd_tunneling)
 784 {
 785         /* UDP tunneling packet TX checksum offload */
 786         if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
 787
 788                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 789                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 790
 791                 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 792                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 793                 else if (ol_flags & PKT_TX_OUTER_IPV4)
 794                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 795                 else if (ol_flags & PKT_TX_OUTER_IPV6)
 796                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 797
 798                 /* Now set the ctx descriptor fields */
 799                 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 800                                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
 801                                 (tx_offload.l2_len >> 1) <<
 802                                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 803
 804         } else
 805                 *td_offset |= (tx_offload.l2_len >> 1)
 806                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 807
 808         /* Enable L3 checksum offloads */
 809         if (ol_flags & PKT_TX_IP_CKSUM) {
 810                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 811                 *td_offset |= (tx_offload.l3_len >> 2)
 812                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 813         } else if (ol_flags & PKT_TX_IPV4) {
 814                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 815                 *td_offset |= (tx_offload.l3_len >> 2)
 816                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 817         } else if (ol_flags & PKT_TX_IPV6) {
 818                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 819                 *td_offset |= (tx_offload.l3_len >> 2)
 820                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 821         }
 822
 823         if (ol_flags & PKT_TX_TCP_SEG) {
 824                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 825                 *td_offset |= (tx_offload.l4_len >> 2)
 826                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 827                 return;
 828         }
 829
 830         /* Enable L4 checksum offloads */
 831         switch (ol_flags & PKT_TX_L4_MASK) {
 832         case PKT_TX_TCP_CKSUM:
 833                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 834                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 835                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 836                 break;
 837         case PKT_TX_SCTP_CKSUM:
 838                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 839                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 840                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 841                 break;
 842         case PKT_TX_UDP_CKSUM:
 843                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 844                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 845                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 846                 break;
 847         default:
 848                 break;
 849         }
 850 }
 851
 852 static inline struct rte_mbuf *
 853 rte_rxmbuf_alloc(struct rte_mempool *mp)
 854 {
 855         struct rte_mbuf *m;
 856
 857         m = __rte_mbuf_raw_alloc(mp);
 858         __rte_mbuf_sanity_check_raw(m, 0);
 859
 860         return m;
 861 }
 862
 863 /* Construct the tx flags */
 864 static inline uint64_t
 865 i40e_build_ctob(uint32_t td_cmd,
 866                 uint32_t td_offset,
 867                 unsigned int size,
 868                 uint32_t td_tag)
 869 {
 870         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 871                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 872                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 873                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 874                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 875 }
 876
 877 static inline int
 878 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 879 {
 880         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 881         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 882         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 883         uint16_t nb_tx_desc = txq->nb_tx_desc;
 884         uint16_t desc_to_clean_to;
 885         uint16_t nb_tx_to_clean;
 886
 887         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 888         if (desc_to_clean_to >= nb_tx_desc)
 889                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 890
 891         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 892         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 893                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 894                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 895                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 896                         "(port=%d queue=%d)", desc_to_clean_to,
 897                                 txq->port_id, txq->queue_id);
 898                 return -1;
 899         }
 900
 901         if (last_desc_cleaned > desc_to_clean_to)
 902                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 903                                                         desc_to_clean_to);
 904         else
 905                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 906                                         last_desc_cleaned);
 907
 908         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 909
 910         txq->last_desc_cleaned = desc_to_clean_to;
 911         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 912
 913         return 0;
 914 }
 915
 916 static inline int
 917 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 918 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 919 #else
 920 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 921 #endif
 922 {
 923         int ret = 0;
 924
 925 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 926         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 927                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 928                              "rxq->rx_free_thresh=%d, "
 929                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 930                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 931                 ret = -EINVAL;
 932         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 933                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 934                              "rxq->rx_free_thresh=%d, "
 935                              "rxq->nb_rx_desc=%d",
 936                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 937                 ret = -EINVAL;
 938         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 939                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 940                              "rxq->nb_rx_desc=%d, "
 941                              "rxq->rx_free_thresh=%d",
 942                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 943                 ret = -EINVAL;
 944         } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
 945                                 RTE_PMD_I40E_RX_MAX_BURST))) {
 946                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 947                              "rxq->nb_rx_desc=%d, "
 948                              "I40E_MAX_RING_DESC=%d, "
 949                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 950                              rxq->nb_rx_desc, I40E_MAX_RING_DESC,
 951                              RTE_PMD_I40E_RX_MAX_BURST);
 952                 ret = -EINVAL;
 953         }
 954 #else
 955         ret = -EINVAL;
 956 #endif
 957
 958         return ret;
 959 }
 960
 961 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 962 #define I40E_LOOK_AHEAD 8
 963 #if (I40E_LOOK_AHEAD != 8)
 964 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 965 #endif
 966 static inline int
 967 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 968 {
 969         volatile union i40e_rx_desc *rxdp;
 970         struct i40e_rx_entry *rxep;
 971         struct rte_mbuf *mb;
 972         uint16_t pkt_len;
 973         uint64_t qword1;
 974         uint32_t rx_status;
 975         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 976         int32_t i, j, nb_rx = 0;
 977         uint64_t pkt_flags;
 978
 979         rxdp = &rxq->rx_ring[rxq->rx_tail];
 980         rxep = &rxq->sw_ring[rxq->rx_tail];
 981
 982         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 983         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 984                                 I40E_RXD_QW1_STATUS_SHIFT;
 985
 986         /* Make sure there is at least 1 packet to receive */
 987         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 988                 return 0;
 989
 990         /**
 991          * Scan LOOK_AHEAD descriptors at a time to determine which
 992          * descriptors reference packets that are ready to be received.
 993          */
 994         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 995                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 996                 /* Read desc statuses backwards to avoid race condition */
 997                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 998                         qword1 = rte_le_to_cpu_64(\
 999                                 rxdp[j].wb.qword1.status_error_len);
1000                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1001                                         I40E_RXD_QW1_STATUS_SHIFT;
1002                 }
1003
1004                 /* Compute how many status bits were set */
1005                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
1006                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
1007
1008                 nb_rx += nb_dd;
1009
1010                 /* Translate descriptor info to mbuf parameters */
1011                 for (j = 0; j < nb_dd; j++) {
1012                         mb = rxep[j].mbuf;
1013                         qword1 = rte_le_to_cpu_64(\
1014                                 rxdp[j].wb.qword1.status_error_len);
1015                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1016                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1017                         mb->data_len = pkt_len;
1018                         mb->pkt_len = pkt_len;
1019                         mb->ol_flags = 0;
1020                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
1021                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1022                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1023                         mb->packet_type =
1024                                 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1025                                                 I40E_RXD_QW1_PTYPE_MASK) >>
1026                                                 I40E_RXD_QW1_PTYPE_SHIFT));
1027                         if (pkt_flags & PKT_RX_RSS_HASH)
1028                                 mb->hash.rss = rte_le_to_cpu_32(\
1029                                         rxdp[j].wb.qword0.hi_dword.rss);
1030                         if (pkt_flags & PKT_RX_FDIR)
1031                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
1032
1033 #ifdef RTE_LIBRTE_IEEE1588
1034                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
1035 #endif
1036                         mb->ol_flags |= pkt_flags;
1037
1038                 }
1039
1040                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
1041                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1042
1043                 if (nb_dd != I40E_LOOK_AHEAD)
1044                         break;
1045         }
1046
1047         /* Clear software ring entries */
1048         for (i = 0; i < nb_rx; i++)
1049                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1050
1051         return nb_rx;
1052 }
1053
1054 static inline uint16_t
1055 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
1056                         struct rte_mbuf **rx_pkts,
1057                         uint16_t nb_pkts)
1058 {
1059         uint16_t i;
1060         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1061
1062         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1063
1064         for (i = 0; i < nb_pkts; i++)
1065                 rx_pkts[i] = stage[i];
1066
1067         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1068         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1069
1070         return nb_pkts;
1071 }
1072
1073 static inline int
1074 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
1075 {
1076         volatile union i40e_rx_desc *rxdp;
1077         struct i40e_rx_entry *rxep;
1078         struct rte_mbuf *mb;
1079         uint16_t alloc_idx, i;
1080         uint64_t dma_addr;
1081         int diag;
1082
1083         /* Allocate buffers in bulk */
1084         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1085                                 (rxq->rx_free_thresh - 1));
1086         rxep = &(rxq->sw_ring[alloc_idx]);
1087         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1088                                         rxq->rx_free_thresh);
1089         if (unlikely(diag != 0)) {
1090                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
1091                 return -ENOMEM;
1092         }
1093
1094         rxdp = &rxq->rx_ring[alloc_idx];
1095         for (i = 0; i < rxq->rx_free_thresh; i++) {
1096                 if (likely(i < (rxq->rx_free_thresh - 1)))
1097                         /* Prefetch next mbuf */
1098                         rte_prefetch0(rxep[i + 1].mbuf);
1099
1100                 mb = rxep[i].mbuf;
1101                 rte_mbuf_refcnt_set(mb, 1);
1102                 mb->next = NULL;
1103                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1104                 mb->nb_segs = 1;
1105                 mb->port = rxq->port_id;
1106                 dma_addr = rte_cpu_to_le_64(\
1107                         RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
1108                 rxdp[i].read.hdr_addr = 0;
1109                 rxdp[i].read.pkt_addr = dma_addr;
1110         }
1111
1112         /* Update rx tail regsiter */
1113         rte_wmb();
1114         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1115
1116         rxq->rx_free_trigger =
1117                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1118         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1119                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1120
1121         return 0;
1122 }
1123
1124 static inline uint16_t
1125 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1126 {
1127         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
1128         uint16_t nb_rx = 0;
1129
1130         if (!nb_pkts)
1131                 return 0;
1132
1133         if (rxq->rx_nb_avail)
1134                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1135
1136         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
1137         rxq->rx_next_avail = 0;
1138         rxq->rx_nb_avail = nb_rx;
1139         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1140
1141         if (rxq->rx_tail > rxq->rx_free_trigger) {
1142                 if (i40e_rx_alloc_bufs(rxq) != 0) {
1143                         uint16_t i, j;
1144
1145                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1146                                    "port_id=%u, queue_id=%u",
1147                                    rxq->port_id, rxq->queue_id);
1148                         rxq->rx_nb_avail = 0;
1149                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1150                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1151                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1152
1153                         return 0;
1154                 }
1155         }
1156
1157         if (rxq->rx_tail >= rxq->nb_rx_desc)
1158                 rxq->rx_tail = 0;
1159
1160         if (rxq->rx_nb_avail)
1161                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1162
1163         return 0;
1164 }
1165
1166 static uint16_t
1167 i40e_recv_pkts_bulk_alloc(void *rx_queue,
1168                           struct rte_mbuf **rx_pkts,
1169                           uint16_t nb_pkts)
1170 {
1171         uint16_t nb_rx = 0, n, count;
1172
1173         if (unlikely(nb_pkts == 0))
1174                 return 0;
1175
1176         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
1177                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1178
1179         while (nb_pkts) {
1180                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
1181                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1182                 nb_rx = (uint16_t)(nb_rx + count);
1183                 nb_pkts = (uint16_t)(nb_pkts - count);
1184                 if (count < n)
1185                         break;
1186         }
1187
1188         return nb_rx;
1189 }
1190 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1191
1192 uint16_t
1193 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1194 {
1195         struct i40e_rx_queue *rxq;
1196         volatile union i40e_rx_desc *rx_ring;
1197         volatile union i40e_rx_desc *rxdp;
1198         union i40e_rx_desc rxd;
1199         struct i40e_rx_entry *sw_ring;
1200         struct i40e_rx_entry *rxe;
1201         struct rte_mbuf *rxm;
1202         struct rte_mbuf *nmb;
1203         uint16_t nb_rx;
1204         uint32_t rx_status;
1205         uint64_t qword1;
1206         uint16_t rx_packet_len;
1207         uint16_t rx_id, nb_hold;
1208         uint64_t dma_addr;
1209         uint64_t pkt_flags;
1210
1211         nb_rx = 0;
1212         nb_hold = 0;
1213         rxq = rx_queue;
1214         rx_id = rxq->rx_tail;
1215         rx_ring = rxq->rx_ring;
1216         sw_ring = rxq->sw_ring;
1217
1218         while (nb_rx < nb_pkts) {
1219                 rxdp = &rx_ring[rx_id];
1220                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1221                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1222                                 >> I40E_RXD_QW1_STATUS_SHIFT;
1223
1224                 /* Check the DD bit first */
1225                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1226                         break;
1227
1228                 nmb = rte_rxmbuf_alloc(rxq->mp);
1229                 if (unlikely(!nmb))
1230                         break;
1231                 rxd = *rxdp;
1232
1233                 nb_hold++;
1234                 rxe = &sw_ring[rx_id];
1235                 rx_id++;
1236                 if (unlikely(rx_id == rxq->nb_rx_desc))
1237                         rx_id = 0;
1238
1239                 /* Prefetch next mbuf */
1240                 rte_prefetch0(sw_ring[rx_id].mbuf);
1241
1242                 /**
1243                  * When next RX descriptor is on a cache line boundary,
1244                  * prefetch the next 4 RX descriptors and next 8 pointers
1245                  * to mbufs.
1246                  */
1247                 if ((rx_id & 0x3) == 0) {
1248                         rte_prefetch0(&rx_ring[rx_id]);
1249                         rte_prefetch0(&sw_ring[rx_id]);
1250                 }
1251                 rxm = rxe->mbuf;
1252                 rxe->mbuf = nmb;
1253                 dma_addr =
1254                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1255                 rxdp->read.hdr_addr = 0;
1256                 rxdp->read.pkt_addr = dma_addr;
1257
1258                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1259                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1260
1261                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1262                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1263                 rxm->nb_segs = 1;
1264                 rxm->next = NULL;
1265                 rxm->pkt_len = rx_packet_len;
1266                 rxm->data_len = rx_packet_len;
1267                 rxm->port = rxq->port_id;
1268                 rxm->ol_flags = 0;
1269                 i40e_rxd_to_vlan_tci(rxm, &rxd);
1270                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1271                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1272                 rxm->packet_type =
1273                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1274                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1275                 if (pkt_flags & PKT_RX_RSS_HASH)
1276                         rxm->hash.rss =
1277                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1278                 if (pkt_flags & PKT_RX_FDIR)
1279                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1280
1281 #ifdef RTE_LIBRTE_IEEE1588
1282                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
1283 #endif
1284                 rxm->ol_flags |= pkt_flags;
1285
1286                 rx_pkts[nb_rx++] = rxm;
1287         }
1288         rxq->rx_tail = rx_id;
1289
1290         /**
1291          * If the number of free RX descriptors is greater than the RX free
1292          * threshold of the queue, advance the receive tail register of queue.
1293          * Update that register with the value of the last processed RX
1294          * descriptor minus 1.
1295          */
1296         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1297         if (nb_hold > rxq->rx_free_thresh) {
1298                 rx_id = (uint16_t) ((rx_id == 0) ?
1299                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1300                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1301                 nb_hold = 0;
1302         }
1303         rxq->nb_rx_hold = nb_hold;
1304
1305         return nb_rx;
1306 }
1307
1308 uint16_t
1309 i40e_recv_scattered_pkts(void *rx_queue,
1310                          struct rte_mbuf **rx_pkts,
1311                          uint16_t nb_pkts)
1312 {
1313         struct i40e_rx_queue *rxq = rx_queue;
1314         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
1315         volatile union i40e_rx_desc *rxdp;
1316         union i40e_rx_desc rxd;
1317         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
1318         struct i40e_rx_entry *rxe;
1319         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1320         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1321         struct rte_mbuf *nmb, *rxm;
1322         uint16_t rx_id = rxq->rx_tail;
1323         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1324         uint32_t rx_status;
1325         uint64_t qword1;
1326         uint64_t dma_addr;
1327         uint64_t pkt_flags;
1328
1329         while (nb_rx < nb_pkts) {
1330                 rxdp = &rx_ring[rx_id];
1331                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1332                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1333                                         I40E_RXD_QW1_STATUS_SHIFT;
1334
1335                 /* Check the DD bit */
1336                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1337                         break;
1338
1339                 nmb = rte_rxmbuf_alloc(rxq->mp);
1340                 if (unlikely(!nmb))
1341                         break;
1342                 rxd = *rxdp;
1343                 nb_hold++;
1344                 rxe = &sw_ring[rx_id];
1345                 rx_id++;
1346                 if (rx_id == rxq->nb_rx_desc)
1347                         rx_id = 0;
1348
1349                 /* Prefetch next mbuf */
1350                 rte_prefetch0(sw_ring[rx_id].mbuf);
1351
1352                 /**
1353                  * When next RX descriptor is on a cache line boundary,
1354                  * prefetch the next 4 RX descriptors and next 8 pointers
1355                  * to mbufs.
1356                  */
1357                 if ((rx_id & 0x3) == 0) {
1358                         rte_prefetch0(&rx_ring[rx_id]);
1359                         rte_prefetch0(&sw_ring[rx_id]);
1360                 }
1361
1362                 rxm = rxe->mbuf;
1363                 rxe->mbuf = nmb;
1364                 dma_addr =
1365                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1366
1367                 /* Set data buffer address and data length of the mbuf */
1368                 rxdp->read.hdr_addr = 0;
1369                 rxdp->read.pkt_addr = dma_addr;
1370                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1371                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1372                 rxm->data_len = rx_packet_len;
1373                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1374
1375                 /**
1376                  * If this is the first buffer of the received packet, set the
1377                  * pointer to the first mbuf of the packet and initialize its
1378                  * context. Otherwise, update the total length and the number
1379                  * of segments of the current scattered packet, and update the
1380                  * pointer to the last mbuf of the current packet.
1381                  */
1382                 if (!first_seg) {
1383                         first_seg = rxm;
1384                         first_seg->nb_segs = 1;
1385                         first_seg->pkt_len = rx_packet_len;
1386                 } else {
1387                         first_seg->pkt_len =
1388                                 (uint16_t)(first_seg->pkt_len +
1389                                                 rx_packet_len);
1390                         first_seg->nb_segs++;
1391                         last_seg->next = rxm;
1392                 }
1393
1394                 /**
1395                  * If this is not the last buffer of the received packet,
1396                  * update the pointer to the last mbuf of the current scattered
1397                  * packet and continue to parse the RX ring.
1398                  */
1399                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1400                         last_seg = rxm;
1401                         continue;
1402                 }
1403
1404                 /**
1405                  * This is the last buffer of the received packet. If the CRC
1406                  * is not stripped by the hardware:
1407                  *  - Subtract the CRC length from the total packet length.
1408                  *  - If the last buffer only contains the whole CRC or a part
1409                  *  of it, free the mbuf associated to the last buffer. If part
1410                  *  of the CRC is also contained in the previous mbuf, subtract
1411                  *  the length of that CRC part from the data length of the
1412                  *  previous mbuf.
1413                  */
1414                 rxm->next = NULL;
1415                 if (unlikely(rxq->crc_len > 0)) {
1416                         first_seg->pkt_len -= ETHER_CRC_LEN;
1417                         if (rx_packet_len <= ETHER_CRC_LEN) {
1418                                 rte_pktmbuf_free_seg(rxm);
1419                                 first_seg->nb_segs--;
1420                                 last_seg->data_len =
1421                                         (uint16_t)(last_seg->data_len -
1422                                         (ETHER_CRC_LEN - rx_packet_len));
1423                                 last_seg->next = NULL;
1424                         } else
1425                                 rxm->data_len = (uint16_t)(rx_packet_len -
1426                                                                 ETHER_CRC_LEN);
1427                 }
1428
1429                 first_seg->port = rxq->port_id;
1430                 first_seg->ol_flags = 0;
1431                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
1432                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1433                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1434                 first_seg->packet_type =
1435                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1436                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1437                 if (pkt_flags & PKT_RX_RSS_HASH)
1438                         rxm->hash.rss =
1439                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1440                 if (pkt_flags & PKT_RX_FDIR)
1441                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1442
1443 #ifdef RTE_LIBRTE_IEEE1588
1444                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
1445 #endif
1446                 first_seg->ol_flags |= pkt_flags;
1447
1448                 /* Prefetch data of first segment, if configured to do so. */
1449                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1450                         first_seg->data_off));
1451                 rx_pkts[nb_rx++] = first_seg;
1452                 first_seg = NULL;
1453         }
1454
1455         /* Record index of the next RX descriptor to probe. */
1456         rxq->rx_tail = rx_id;
1457         rxq->pkt_first_seg = first_seg;
1458         rxq->pkt_last_seg = last_seg;
1459
1460         /**
1461          * If the number of free RX descriptors is greater than the RX free
1462          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1463          * register. Update the RDT with the value of the last processed RX
1464          * descriptor minus 1, to guarantee that the RDT register is never
1465          * equal to the RDH register, which creates a "full" ring situtation
1466          * from the hardware point of view.
1467          */
1468         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1469         if (nb_hold > rxq->rx_free_thresh) {
1470                 rx_id = (uint16_t)(rx_id == 0 ?
1471                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1472                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1473                 nb_hold = 0;
1474         }
1475         rxq->nb_rx_hold = nb_hold;
1476
1477         return nb_rx;
1478 }
1479
1480 /* Check if the context descriptor is needed for TX offloading */
1481 static inline uint16_t
1482 i40e_calc_context_desc(uint64_t flags)
1483 {
1484         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
1485                 PKT_TX_TCP_SEG |
1486                 PKT_TX_QINQ_PKT;
1487
1488 #ifdef RTE_LIBRTE_IEEE1588
1489         mask |= PKT_TX_IEEE1588_TMST;
1490 #endif
1491
1492         return ((flags & mask) ? 1 : 0);
1493 }
1494
1495 /* set i40e TSO context descriptor */
1496 static inline uint64_t
1497 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1498 {
1499         uint64_t ctx_desc = 0;
1500         uint32_t cd_cmd, hdr_len, cd_tso_len;
1501
1502         if (!tx_offload.l4_len) {
1503                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1504                 return ctx_desc;
1505         }
1506
1507         /**
1508          * in case of tunneling packet, the outer_l2_len and
1509          * outer_l3_len must be 0.
1510          */
1511         hdr_len = tx_offload.outer_l2_len +
1512                 tx_offload.outer_l3_len +
1513                 tx_offload.l2_len +
1514                 tx_offload.l3_len +
1515                 tx_offload.l4_len;
1516
1517         cd_cmd = I40E_TX_CTX_DESC_TSO;
1518         cd_tso_len = mbuf->pkt_len - hdr_len;
1519         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1520                 ((uint64_t)cd_tso_len <<
1521                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1522                 ((uint64_t)mbuf->tso_segsz <<
1523                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1524
1525         return ctx_desc;
1526 }
1527
1528 uint16_t
1529 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1530 {
1531         struct i40e_tx_queue *txq;
1532         struct i40e_tx_entry *sw_ring;
1533         struct i40e_tx_entry *txe, *txn;
1534         volatile struct i40e_tx_desc *txd;
1535         volatile struct i40e_tx_desc *txr;
1536         struct rte_mbuf *tx_pkt;
1537         struct rte_mbuf *m_seg;
1538         uint32_t cd_tunneling_params;
1539         uint16_t tx_id;
1540         uint16_t nb_tx;
1541         uint32_t td_cmd;
1542         uint32_t td_offset;
1543         uint32_t tx_flags;
1544         uint32_t td_tag;
1545         uint64_t ol_flags;
1546         uint16_t nb_used;
1547         uint16_t nb_ctx;
1548         uint16_t tx_last;
1549         uint16_t slen;
1550         uint64_t buf_dma_addr;
1551         union i40e_tx_offload tx_offload = {0};
1552
1553         txq = tx_queue;
1554         sw_ring = txq->sw_ring;
1555         txr = txq->tx_ring;
1556         tx_id = txq->tx_tail;
1557         txe = &sw_ring[tx_id];
1558
1559         /* Check if the descriptor ring needs to be cleaned. */
1560         if (txq->nb_tx_free < txq->tx_free_thresh)
1561                 i40e_xmit_cleanup(txq);
1562
1563         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1564                 td_cmd = 0;
1565                 td_tag = 0;
1566                 td_offset = 0;
1567                 tx_flags = 0;
1568
1569                 tx_pkt = *tx_pkts++;
1570                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1571
1572                 ol_flags = tx_pkt->ol_flags;
1573                 tx_offload.l2_len = tx_pkt->l2_len;
1574                 tx_offload.l3_len = tx_pkt->l3_len;
1575                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1576                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1577                 tx_offload.l4_len = tx_pkt->l4_len;
1578                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1579
1580                 /* Calculate the number of context descriptors needed. */
1581                 nb_ctx = i40e_calc_context_desc(ol_flags);
1582
1583                 /**
1584                  * The number of descriptors that must be allocated for
1585                  * a packet equals to the number of the segments of that
1586                  * packet plus 1 context descriptor if needed.
1587                  */
1588                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1589                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1590
1591                 /* Circular ring */
1592                 if (tx_last >= txq->nb_tx_desc)
1593                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1594
1595                 if (nb_used > txq->nb_tx_free) {
1596                         if (i40e_xmit_cleanup(txq) != 0) {
1597                                 if (nb_tx == 0)
1598                                         return 0;
1599                                 goto end_of_tx;
1600                         }
1601                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1602                                 while (nb_used > txq->nb_tx_free) {
1603                                         if (i40e_xmit_cleanup(txq) != 0) {
1604                                                 if (nb_tx == 0)
1605                                                         return 0;
1606                                                 goto end_of_tx;
1607                                         }
1608                                 }
1609                         }
1610                 }
1611
1612                 /* Descriptor based VLAN insertion */
1613                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1614                         tx_flags |= tx_pkt->vlan_tci <<
1615                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1616                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1617                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1618                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1619                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1620                 }
1621
1622                 /* Always enable CRC offload insertion */
1623                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1624
1625                 /* Enable checksum offloading */
1626                 cd_tunneling_params = 0;
1627                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK) {
1628                         i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1629                                 tx_offload, &cd_tunneling_params);
1630                 }
1631
1632                 if (nb_ctx) {
1633                         /* Setup TX context descriptor if required */
1634                         volatile struct i40e_tx_context_desc *ctx_txd =
1635                                 (volatile struct i40e_tx_context_desc *)\
1636                                                         &txr[tx_id];
1637                         uint16_t cd_l2tag2 = 0;
1638                         uint64_t cd_type_cmd_tso_mss =
1639                                 I40E_TX_DESC_DTYPE_CONTEXT;
1640
1641                         txn = &sw_ring[txe->next_id];
1642                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1643                         if (txe->mbuf != NULL) {
1644                                 rte_pktmbuf_free_seg(txe->mbuf);
1645                                 txe->mbuf = NULL;
1646                         }
1647
1648                         /* TSO enabled means no timestamp */
1649                         if (ol_flags & PKT_TX_TCP_SEG)
1650                                 cd_type_cmd_tso_mss |=
1651                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1652                         else {
1653 #ifdef RTE_LIBRTE_IEEE1588
1654                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1655                                         cd_type_cmd_tso_mss |=
1656                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1657                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1658 #endif
1659                         }
1660
1661                         ctx_txd->tunneling_params =
1662                                 rte_cpu_to_le_32(cd_tunneling_params);
1663                         if (ol_flags & PKT_TX_QINQ_PKT) {
1664                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1665                                 cd_type_cmd_tso_mss |=
1666                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1667                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1668                         }
1669                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1670                         ctx_txd->type_cmd_tso_mss =
1671                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1672
1673                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1674                                 "tunneling_params: %#x;\n"
1675                                 "l2tag2: %#hx;\n"
1676                                 "rsvd: %#hx;\n"
1677                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1678                                 tx_pkt, tx_id,
1679                                 ctx_txd->tunneling_params,
1680                                 ctx_txd->l2tag2,
1681                                 ctx_txd->rsvd,
1682                                 ctx_txd->type_cmd_tso_mss);
1683
1684                         txe->last_id = tx_last;
1685                         tx_id = txe->next_id;
1686                         txe = txn;
1687                 }
1688
1689                 m_seg = tx_pkt;
1690                 do {
1691                         txd = &txr[tx_id];
1692                         txn = &sw_ring[txe->next_id];
1693
1694                         if (txe->mbuf)
1695                                 rte_pktmbuf_free_seg(txe->mbuf);
1696                         txe->mbuf = m_seg;
1697
1698                         /* Setup TX Descriptor */
1699                         slen = m_seg->data_len;
1700                         buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1701
1702                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1703                                 "buf_dma_addr: %#"PRIx64";\n"
1704                                 "td_cmd: %#x;\n"
1705                                 "td_offset: %#x;\n"
1706                                 "td_len: %u;\n"
1707                                 "td_tag: %#x;\n",
1708                                 tx_pkt, tx_id, buf_dma_addr,
1709                                 td_cmd, td_offset, slen, td_tag);
1710
1711                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1712                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1713                                                 td_offset, slen, td_tag);
1714                         txe->last_id = tx_last;
1715                         tx_id = txe->next_id;
1716                         txe = txn;
1717                         m_seg = m_seg->next;
1718                 } while (m_seg != NULL);
1719
1720                 /* The last packet data descriptor needs End Of Packet (EOP) */
1721                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1722                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1723                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1724
1725                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1726                         PMD_TX_FREE_LOG(DEBUG,
1727                                         "Setting RS bit on TXD id="
1728                                         "%4u (port=%d queue=%d)",
1729                                         tx_last, txq->port_id, txq->queue_id);
1730
1731                         td_cmd |= I40E_TX_DESC_CMD_RS;
1732
1733                         /* Update txq RS bit counters */
1734                         txq->nb_tx_used = 0;
1735                 }
1736
1737                 txd->cmd_type_offset_bsz |=
1738                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1739                                         I40E_TXD_QW1_CMD_SHIFT);
1740         }
1741
1742 end_of_tx:
1743         rte_wmb();
1744
1745         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1746                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1747                    (unsigned) tx_id, (unsigned) nb_tx);
1748
1749         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1750         txq->tx_tail = tx_id;
1751
1752         return nb_tx;
1753 }
1754
1755 static inline int __attribute__((always_inline))
1756 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1757 {
1758         struct i40e_tx_entry *txep;
1759         uint16_t i;
1760
1761         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1762                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1763                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1764                 return 0;
1765
1766         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1767
1768         for (i = 0; i < txq->tx_rs_thresh; i++)
1769                 rte_prefetch0((txep + i)->mbuf);
1770
1771         if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1772                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1773                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1774                         txep->mbuf = NULL;
1775                 }
1776         } else {
1777                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1778                         rte_pktmbuf_free_seg(txep->mbuf);
1779                         txep->mbuf = NULL;
1780                 }
1781         }
1782
1783         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1784         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1785         if (txq->tx_next_dd >= txq->nb_tx_desc)
1786                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1787
1788         return txq->tx_rs_thresh;
1789 }
1790
1791 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
1792                      I40E_TX_DESC_CMD_EOP)
1793
1794 /* Populate 4 descriptors with data from 4 mbufs */
1795 static inline void
1796 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1797 {
1798         uint64_t dma_addr;
1799         uint32_t i;
1800
1801         for (i = 0; i < 4; i++, txdp++, pkts++) {
1802                 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1803                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1804                 txdp->cmd_type_offset_bsz =
1805                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1806                                         (*pkts)->data_len, 0);
1807         }
1808 }
1809
1810 /* Populate 1 descriptor with data from 1 mbuf */
1811 static inline void
1812 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1813 {
1814         uint64_t dma_addr;
1815
1816         dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1817         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1818         txdp->cmd_type_offset_bsz =
1819                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1820                                 (*pkts)->data_len, 0);
1821 }
1822
1823 /* Fill hardware descriptor ring with mbuf data */
1824 static inline void
1825 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1826                      struct rte_mbuf **pkts,
1827                      uint16_t nb_pkts)
1828 {
1829         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1830         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1831         const int N_PER_LOOP = 4;
1832         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1833         int mainpart, leftover;
1834         int i, j;
1835
1836         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1837         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1838         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1839                 for (j = 0; j < N_PER_LOOP; ++j) {
1840                         (txep + i + j)->mbuf = *(pkts + i + j);
1841                 }
1842                 tx4(txdp + i, pkts + i);
1843         }
1844         if (unlikely(leftover > 0)) {
1845                 for (i = 0; i < leftover; ++i) {
1846                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1847                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1848                 }
1849         }
1850 }
1851
1852 static inline uint16_t
1853 tx_xmit_pkts(struct i40e_tx_queue *txq,
1854              struct rte_mbuf **tx_pkts,
1855              uint16_t nb_pkts)
1856 {
1857         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1858         uint16_t n = 0;
1859
1860         /**
1861          * Begin scanning the H/W ring for done descriptors when the number
1862          * of available descriptors drops below tx_free_thresh. For each done
1863          * descriptor, free the associated buffer.
1864          */
1865         if (txq->nb_tx_free < txq->tx_free_thresh)
1866                 i40e_tx_free_bufs(txq);
1867
1868         /* Use available descriptor only */
1869         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1870         if (unlikely(!nb_pkts))
1871                 return 0;
1872
1873         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1874         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1875                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1876                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1877                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1878                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1879                                                 I40E_TXD_QW1_CMD_SHIFT);
1880                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1881                 txq->tx_tail = 0;
1882         }
1883
1884         /* Fill hardware descriptor ring with mbuf data */
1885         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1886         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1887
1888         /* Determin if RS bit needs to be set */
1889         if (txq->tx_tail > txq->tx_next_rs) {
1890                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1891                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1892                                                 I40E_TXD_QW1_CMD_SHIFT);
1893                 txq->tx_next_rs =
1894                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1895                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1896                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1897         }
1898
1899         if (txq->tx_tail >= txq->nb_tx_desc)
1900                 txq->tx_tail = 0;
1901
1902         /* Update the tx tail register */
1903         rte_wmb();
1904         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1905
1906         return nb_pkts;
1907 }
1908
1909 static uint16_t
1910 i40e_xmit_pkts_simple(void *tx_queue,
1911                       struct rte_mbuf **tx_pkts,
1912                       uint16_t nb_pkts)
1913 {
1914         uint16_t nb_tx = 0;
1915
1916         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1917                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1918                                                 tx_pkts, nb_pkts);
1919
1920         while (nb_pkts) {
1921                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1922                                                 I40E_TX_MAX_BURST);
1923
1924                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1925                                                 &tx_pkts[nb_tx], num);
1926                 nb_tx = (uint16_t)(nb_tx + ret);
1927                 nb_pkts = (uint16_t)(nb_pkts - ret);
1928                 if (ret < num)
1929                         break;
1930         }
1931
1932         return nb_tx;
1933 }
1934
1935 /*
1936  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1937  * application used, which assume having sequential ones. But from driver's
1938  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1939  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1940  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1941  * use queue_idx from 0 to 95 to access queues, while real queue would be
1942  * different. This function will do a queue mapping to find VSI the queue
1943  * belongs to.
1944  */
1945 static struct i40e_vsi*
1946 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1947 {
1948         /* the queue in MAIN VSI range */
1949         if (queue_idx < pf->main_vsi->nb_qps)
1950                 return pf->main_vsi;
1951
1952         queue_idx -= pf->main_vsi->nb_qps;
1953
1954         /* queue_idx is greater than VMDQ VSIs range */
1955         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1956                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1957                 return NULL;
1958         }
1959
1960         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1961 }
1962
1963 static uint16_t
1964 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1965 {
1966         /* the queue in MAIN VSI range */
1967         if (queue_idx < pf->main_vsi->nb_qps)
1968                 return queue_idx;
1969
1970         /* It's VMDQ queues */
1971         queue_idx -= pf->main_vsi->nb_qps;
1972
1973         if (pf->nb_cfg_vmdq_vsi)
1974                 return queue_idx % pf->vmdq_nb_qps;
1975         else {
1976                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1977                 return (uint16_t)(-1);
1978         }
1979 }
1980
1981 int
1982 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1983 {
1984         struct i40e_rx_queue *rxq;
1985         int err = -1;
1986         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1987
1988         PMD_INIT_FUNC_TRACE();
1989
1990         if (rx_queue_id < dev->data->nb_rx_queues) {
1991                 rxq = dev->data->rx_queues[rx_queue_id];
1992
1993                 err = i40e_alloc_rx_queue_mbufs(rxq);
1994                 if (err) {
1995                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1996                         return err;
1997                 }
1998
1999                 rte_wmb();
2000
2001                 /* Init the RX tail regieter. */
2002                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2003
2004                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
2005
2006                 if (err) {
2007                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
2008                                     rx_queue_id);
2009
2010                         i40e_rx_queue_release_mbufs(rxq);
2011                         i40e_reset_rx_queue(rxq);
2012                 }
2013         }
2014
2015         return err;
2016 }
2017
2018 int
2019 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2020 {
2021         struct i40e_rx_queue *rxq;
2022         int err;
2023         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2024
2025         if (rx_queue_id < dev->data->nb_rx_queues) {
2026                 rxq = dev->data->rx_queues[rx_queue_id];
2027
2028                 /*
2029                 * rx_queue_id is queue id aplication refers to, while
2030                 * rxq->reg_idx is the real queue index.
2031                 */
2032                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
2033
2034                 if (err) {
2035                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
2036                                     rx_queue_id);
2037                         return err;
2038                 }
2039                 i40e_rx_queue_release_mbufs(rxq);
2040                 i40e_reset_rx_queue(rxq);
2041         }
2042
2043         return 0;
2044 }
2045
2046 int
2047 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2048 {
2049         int err = -1;
2050         struct i40e_tx_queue *txq;
2051         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2052
2053         PMD_INIT_FUNC_TRACE();
2054
2055         if (tx_queue_id < dev->data->nb_tx_queues) {
2056                 txq = dev->data->tx_queues[tx_queue_id];
2057
2058                 /*
2059                 * tx_queue_id is queue id aplication refers to, while
2060                 * rxq->reg_idx is the real queue index.
2061                 */
2062                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
2063                 if (err)
2064                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
2065                                     tx_queue_id);
2066         }
2067
2068         return err;
2069 }
2070
2071 int
2072 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2073 {
2074         struct i40e_tx_queue *txq;
2075         int err;
2076         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2077
2078         if (tx_queue_id < dev->data->nb_tx_queues) {
2079                 txq = dev->data->tx_queues[tx_queue_id];
2080
2081                 /*
2082                 * tx_queue_id is queue id aplication refers to, while
2083                 * txq->reg_idx is the real queue index.
2084                 */
2085                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
2086
2087                 if (err) {
2088                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
2089                                     tx_queue_id);
2090                         return err;
2091                 }
2092
2093                 i40e_tx_queue_release_mbufs(txq);
2094                 i40e_reset_tx_queue(txq);
2095         }
2096
2097         return 0;
2098 }
2099
2100 int
2101 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
2102                         uint16_t queue_idx,
2103                         uint16_t nb_desc,
2104                         unsigned int socket_id,
2105                         const struct rte_eth_rxconf *rx_conf,
2106                         struct rte_mempool *mp)
2107 {
2108         struct i40e_vsi *vsi;
2109         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2110         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2111         struct i40e_rx_queue *rxq;
2112         const struct rte_memzone *rz;
2113         uint32_t ring_size;
2114         uint16_t len;
2115         int use_def_burst_func = 1;
2116
2117         if (hw->mac.type == I40E_MAC_VF) {
2118                 struct i40e_vf *vf =
2119                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2120                 vsi = &vf->vsi;
2121         } else
2122                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2123
2124         if (vsi == NULL) {
2125                 PMD_DRV_LOG(ERR, "VSI not available or queue "
2126                             "index exceeds the maximum");
2127                 return I40E_ERR_PARAM;
2128         }
2129         if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||
2130                                         (nb_desc > I40E_MAX_RING_DESC) ||
2131                                         (nb_desc < I40E_MIN_RING_DESC)) {
2132                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
2133                             "invalid", nb_desc);
2134                 return I40E_ERR_PARAM;
2135         }
2136
2137         /* Free memory if needed */
2138         if (dev->data->rx_queues[queue_idx]) {
2139                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
2140                 dev->data->rx_queues[queue_idx] = NULL;
2141         }
2142
2143         /* Allocate the rx queue data structure */
2144         rxq = rte_zmalloc_socket("i40e rx queue",
2145                                  sizeof(struct i40e_rx_queue),
2146                                  RTE_CACHE_LINE_SIZE,
2147                                  socket_id);
2148         if (!rxq) {
2149                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2150                             "rx queue data structure");
2151                 return (-ENOMEM);
2152         }
2153         rxq->mp = mp;
2154         rxq->nb_rx_desc = nb_desc;
2155         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2156         rxq->queue_id = queue_idx;
2157         if (hw->mac.type == I40E_MAC_VF)
2158                 rxq->reg_idx = queue_idx;
2159         else /* PF device */
2160                 rxq->reg_idx = vsi->base_queue +
2161                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2162
2163         rxq->port_id = dev->data->port_id;
2164         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2165                                                         0 : ETHER_CRC_LEN);
2166         rxq->drop_en = rx_conf->rx_drop_en;
2167         rxq->vsi = vsi;
2168         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2169
2170         /* Allocate the maximun number of RX ring hardware descriptor. */
2171         ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
2172         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2173         rz = i40e_ring_dma_zone_reserve(dev,
2174                                         "rx_ring",
2175                                         queue_idx,
2176                                         ring_size,
2177                                         socket_id);
2178         if (!rz) {
2179                 i40e_dev_rx_queue_release(rxq);
2180                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2181                 return (-ENOMEM);
2182         }
2183
2184         /* Zero all the descriptors in the ring. */
2185         memset(rz->addr, 0, ring_size);
2186
2187 #ifdef RTE_LIBRTE_XEN_DOM0
2188         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2189 #else
2190         rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
2191 #endif
2192
2193         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2194
2195 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2196         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2197 #else
2198         len = nb_desc;
2199 #endif
2200
2201         /* Allocate the software ring. */
2202         rxq->sw_ring =
2203                 rte_zmalloc_socket("i40e rx sw ring",
2204                                    sizeof(struct i40e_rx_entry) * len,
2205                                    RTE_CACHE_LINE_SIZE,
2206                                    socket_id);
2207         if (!rxq->sw_ring) {
2208                 i40e_dev_rx_queue_release(rxq);
2209                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2210                 return (-ENOMEM);
2211         }
2212
2213         i40e_reset_rx_queue(rxq);
2214         rxq->q_set = TRUE;
2215         dev->data->rx_queues[queue_idx] = rxq;
2216
2217         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2218
2219         if (!use_def_burst_func && !dev->data->scattered_rx) {
2220 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2221                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2222                              "satisfied. Rx Burst Bulk Alloc function will be "
2223                              "used on port=%d, queue=%d.",
2224                              rxq->port_id, rxq->queue_id);
2225                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2226 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2227         } else {
2228                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2229                              "not satisfied, Scattered Rx is requested, "
2230                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2231                              "not enabled on port=%d, queue=%d.",
2232                              rxq->port_id, rxq->queue_id);
2233         }
2234
2235         return 0;
2236 }
2237
2238 void
2239 i40e_dev_rx_queue_release(void *rxq)
2240 {
2241         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2242
2243         if (!q) {
2244                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2245                 return;
2246         }
2247
2248         i40e_rx_queue_release_mbufs(q);
2249         rte_free(q->sw_ring);
2250         rte_free(q);
2251 }
2252
2253 uint32_t
2254 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2255 {
2256 #define I40E_RXQ_SCAN_INTERVAL 4
2257         volatile union i40e_rx_desc *rxdp;
2258         struct i40e_rx_queue *rxq;
2259         uint16_t desc = 0;
2260
2261         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
2262                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
2263                 return 0;
2264         }
2265
2266         rxq = dev->data->rx_queues[rx_queue_id];
2267         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2268         while ((desc < rxq->nb_rx_desc) &&
2269                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2270                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2271                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2272                 /**
2273                  * Check the DD bit of a rx descriptor of each 4 in a group,
2274                  * to avoid checking too frequently and downgrading performance
2275                  * too much.
2276                  */
2277                 desc += I40E_RXQ_SCAN_INTERVAL;
2278                 rxdp += I40E_RXQ_SCAN_INTERVAL;
2279                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2280                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2281                                         desc - rxq->nb_rx_desc]);
2282         }
2283
2284         return desc;
2285 }
2286
2287 int
2288 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2289 {
2290         volatile union i40e_rx_desc *rxdp;
2291         struct i40e_rx_queue *rxq = rx_queue;
2292         uint16_t desc;
2293         int ret;
2294
2295         if (unlikely(offset >= rxq->nb_rx_desc)) {
2296                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
2297                 return 0;
2298         }
2299
2300         desc = rxq->rx_tail + offset;
2301         if (desc >= rxq->nb_rx_desc)
2302                 desc -= rxq->nb_rx_desc;
2303
2304         rxdp = &(rxq->rx_ring[desc]);
2305
2306         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2307                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2308                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2309
2310         return ret;
2311 }
2312
2313 int
2314 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2315                         uint16_t queue_idx,
2316                         uint16_t nb_desc,
2317                         unsigned int socket_id,
2318                         const struct rte_eth_txconf *tx_conf)
2319 {
2320         struct i40e_vsi *vsi;
2321         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2322         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2323         struct i40e_tx_queue *txq;
2324         const struct rte_memzone *tz;
2325         uint32_t ring_size;
2326         uint16_t tx_rs_thresh, tx_free_thresh;
2327
2328         if (hw->mac.type == I40E_MAC_VF) {
2329                 struct i40e_vf *vf =
2330                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2331                 vsi = &vf->vsi;
2332         } else
2333                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2334
2335         if (vsi == NULL) {
2336                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2337                             "exceeds the maximum", queue_idx);
2338                 return I40E_ERR_PARAM;
2339         }
2340
2341         if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||
2342                                         (nb_desc > I40E_MAX_RING_DESC) ||
2343                                         (nb_desc < I40E_MIN_RING_DESC)) {
2344                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2345                             "invalid", nb_desc);
2346                 return I40E_ERR_PARAM;
2347         }
2348
2349         /**
2350          * The following two parameters control the setting of the RS bit on
2351          * transmit descriptors. TX descriptors will have their RS bit set
2352          * after txq->tx_rs_thresh descriptors have been used. The TX
2353          * descriptor ring will be cleaned after txq->tx_free_thresh
2354          * descriptors are used or if the number of descriptors required to
2355          * transmit a packet is greater than the number of free TX descriptors.
2356          *
2357          * The following constraints must be satisfied:
2358          *  - tx_rs_thresh must be greater than 0.
2359          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2360          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2361          *  - tx_rs_thresh must be a divisor of the ring size.
2362          *  - tx_free_thresh must be greater than 0.
2363          *  - tx_free_thresh must be less than the size of the ring minus 3.
2364          *
2365          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2366          * race condition, hence the maximum threshold constraints. When set
2367          * to zero use default values.
2368          */
2369         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2370                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2371         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2372                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2373         if (tx_rs_thresh >= (nb_desc - 2)) {
2374                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2375                              "number of TX descriptors minus 2. "
2376                              "(tx_rs_thresh=%u port=%d queue=%d)",
2377                              (unsigned int)tx_rs_thresh,
2378                              (int)dev->data->port_id,
2379                              (int)queue_idx);
2380                 return I40E_ERR_PARAM;
2381         }
2382         if (tx_free_thresh >= (nb_desc - 3)) {
2383                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2384                              "tx_free_thresh must be less than the "
2385                              "number of TX descriptors minus 3. "
2386                              "(tx_free_thresh=%u port=%d queue=%d)",
2387                              (unsigned int)tx_free_thresh,
2388                              (int)dev->data->port_id,
2389                              (int)queue_idx);
2390                 return I40E_ERR_PARAM;
2391         }
2392         if (tx_rs_thresh > tx_free_thresh) {
2393                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2394                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2395                              " tx_rs_thresh=%u port=%d queue=%d)",
2396                              (unsigned int)tx_free_thresh,
2397                              (unsigned int)tx_rs_thresh,
2398                              (int)dev->data->port_id,
2399                              (int)queue_idx);
2400                 return I40E_ERR_PARAM;
2401         }
2402         if ((nb_desc % tx_rs_thresh) != 0) {
2403                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2404                              "number of TX descriptors. (tx_rs_thresh=%u"
2405                              " port=%d queue=%d)",
2406                              (unsigned int)tx_rs_thresh,
2407                              (int)dev->data->port_id,
2408                              (int)queue_idx);
2409                 return I40E_ERR_PARAM;
2410         }
2411         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2412                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2413                              "tx_rs_thresh is greater than 1. "
2414                              "(tx_rs_thresh=%u port=%d queue=%d)",
2415                              (unsigned int)tx_rs_thresh,
2416                              (int)dev->data->port_id,
2417                              (int)queue_idx);
2418                 return I40E_ERR_PARAM;
2419         }
2420
2421         /* Free memory if needed. */
2422         if (dev->data->tx_queues[queue_idx]) {
2423                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2424                 dev->data->tx_queues[queue_idx] = NULL;
2425         }
2426
2427         /* Allocate the TX queue data structure. */
2428         txq = rte_zmalloc_socket("i40e tx queue",
2429                                   sizeof(struct i40e_tx_queue),
2430                                   RTE_CACHE_LINE_SIZE,
2431                                   socket_id);
2432         if (!txq) {
2433                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2434                             "tx queue structure");
2435                 return (-ENOMEM);
2436         }
2437
2438         /* Allocate TX hardware ring descriptors. */
2439         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2440         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2441         tz = i40e_ring_dma_zone_reserve(dev,
2442                                         "tx_ring",
2443                                         queue_idx,
2444                                         ring_size,
2445                                         socket_id);
2446         if (!tz) {
2447                 i40e_dev_tx_queue_release(txq);
2448                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2449                 return (-ENOMEM);
2450         }
2451
2452         txq->nb_tx_desc = nb_desc;
2453         txq->tx_rs_thresh = tx_rs_thresh;
2454         txq->tx_free_thresh = tx_free_thresh;
2455         txq->pthresh = tx_conf->tx_thresh.pthresh;
2456         txq->hthresh = tx_conf->tx_thresh.hthresh;
2457         txq->wthresh = tx_conf->tx_thresh.wthresh;
2458         txq->queue_id = queue_idx;
2459         if (hw->mac.type == I40E_MAC_VF)
2460                 txq->reg_idx = queue_idx;
2461         else /* PF device */
2462                 txq->reg_idx = vsi->base_queue +
2463                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2464
2465         txq->port_id = dev->data->port_id;
2466         txq->txq_flags = tx_conf->txq_flags;
2467         txq->vsi = vsi;
2468         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2469
2470 #ifdef RTE_LIBRTE_XEN_DOM0
2471         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2472 #else
2473         txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2474 #endif
2475         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2476
2477         /* Allocate software ring */
2478         txq->sw_ring =
2479                 rte_zmalloc_socket("i40e tx sw ring",
2480                                    sizeof(struct i40e_tx_entry) * nb_desc,
2481                                    RTE_CACHE_LINE_SIZE,
2482                                    socket_id);
2483         if (!txq->sw_ring) {
2484                 i40e_dev_tx_queue_release(txq);
2485                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2486                 return (-ENOMEM);
2487         }
2488
2489         i40e_reset_tx_queue(txq);
2490         txq->q_set = TRUE;
2491         dev->data->tx_queues[queue_idx] = txq;
2492
2493         /* Use a simple TX queue without offloads or multi segs if possible */
2494         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&
2495                                 (txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {
2496                 PMD_INIT_LOG(INFO, "Using simple tx path");
2497                 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2498         } else {
2499                 PMD_INIT_LOG(INFO, "Using full-featured tx path");
2500                 dev->tx_pkt_burst = i40e_xmit_pkts;
2501         }
2502
2503         return 0;
2504 }
2505
2506 void
2507 i40e_dev_tx_queue_release(void *txq)
2508 {
2509         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2510
2511         if (!q) {
2512                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2513                 return;
2514         }
2515
2516         i40e_tx_queue_release_mbufs(q);
2517         rte_free(q->sw_ring);
2518         rte_free(q);
2519 }
2520
2521 static const struct rte_memzone *
2522 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
2523                            const char *ring_name,
2524                            uint16_t queue_id,
2525                            uint32_t ring_size,
2526                            int socket_id)
2527 {
2528         char z_name[RTE_MEMZONE_NAMESIZE];
2529         const struct rte_memzone *mz;
2530
2531         snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
2532                         dev->driver->pci_drv.name, ring_name,
2533                                 dev->data->port_id, queue_id);
2534         mz = rte_memzone_lookup(z_name);
2535         if (mz)
2536                 return mz;
2537
2538 #ifdef RTE_LIBRTE_XEN_DOM0
2539         return rte_memzone_reserve_bounded(z_name, ring_size,
2540                 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2541 #else
2542         return rte_memzone_reserve_aligned(z_name, ring_size,
2543                                 socket_id, 0, I40E_ALIGN);
2544 #endif
2545 }
2546
2547 const struct rte_memzone *
2548 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2549 {
2550         const struct rte_memzone *mz = NULL;
2551
2552         mz = rte_memzone_lookup(name);
2553         if (mz)
2554                 return mz;
2555 #ifdef RTE_LIBRTE_XEN_DOM0
2556         mz = rte_memzone_reserve_bounded(name, len,
2557                 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2558 #else
2559         mz = rte_memzone_reserve_aligned(name, len,
2560                                 socket_id, 0, I40E_ALIGN);
2561 #endif
2562         return mz;
2563 }
2564
2565 void
2566 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2567 {
2568         uint16_t i;
2569
2570         if (!rxq || !rxq->sw_ring) {
2571                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2572                 return;
2573         }
2574
2575         for (i = 0; i < rxq->nb_rx_desc; i++) {
2576                 if (rxq->sw_ring[i].mbuf) {
2577                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2578                         rxq->sw_ring[i].mbuf = NULL;
2579                 }
2580         }
2581 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2582         if (rxq->rx_nb_avail == 0)
2583                 return;
2584         for (i = 0; i < rxq->rx_nb_avail; i++) {
2585                 struct rte_mbuf *mbuf;
2586
2587                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2588                 rte_pktmbuf_free_seg(mbuf);
2589         }
2590         rxq->rx_nb_avail = 0;
2591 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2592 }
2593
2594 void
2595 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2596 {
2597         unsigned i;
2598         uint16_t len;
2599
2600         if (!rxq) {
2601                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2602                 return;
2603         }
2604
2605 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2606         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2607                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2608         else
2609 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2610                 len = rxq->nb_rx_desc;
2611
2612         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2613                 ((volatile char *)rxq->rx_ring)[i] = 0;
2614
2615 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2616         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2617         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2618                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2619
2620         rxq->rx_nb_avail = 0;
2621         rxq->rx_next_avail = 0;
2622         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2623 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2624         rxq->rx_tail = 0;
2625         rxq->nb_rx_hold = 0;
2626         rxq->pkt_first_seg = NULL;
2627         rxq->pkt_last_seg = NULL;
2628 }
2629
2630 void
2631 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2632 {
2633         uint16_t i;
2634
2635         if (!txq || !txq->sw_ring) {
2636                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2637                 return;
2638         }
2639
2640         for (i = 0; i < txq->nb_tx_desc; i++) {
2641                 if (txq->sw_ring[i].mbuf) {
2642                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2643                         txq->sw_ring[i].mbuf = NULL;
2644                 }
2645         }
2646 }
2647
2648 void
2649 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2650 {
2651         struct i40e_tx_entry *txe;
2652         uint16_t i, prev, size;
2653
2654         if (!txq) {
2655                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2656                 return;
2657         }
2658
2659         txe = txq->sw_ring;
2660         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2661         for (i = 0; i < size; i++)
2662                 ((volatile char *)txq->tx_ring)[i] = 0;
2663
2664         prev = (uint16_t)(txq->nb_tx_desc - 1);
2665         for (i = 0; i < txq->nb_tx_desc; i++) {
2666                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2667
2668                 txd->cmd_type_offset_bsz =
2669                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2670                 txe[i].mbuf =  NULL;
2671                 txe[i].last_id = i;
2672                 txe[prev].next_id = i;
2673                 prev = i;
2674         }
2675
2676         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2677         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2678
2679         txq->tx_tail = 0;
2680         txq->nb_tx_used = 0;
2681
2682         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2683         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2684 }
2685
2686 /* Init the TX queue in hardware */
2687 int
2688 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2689 {
2690         enum i40e_status_code err = I40E_SUCCESS;
2691         struct i40e_vsi *vsi = txq->vsi;
2692         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2693         uint16_t pf_q = txq->reg_idx;
2694         struct i40e_hmc_obj_txq tx_ctx;
2695         uint32_t qtx_ctl;
2696
2697         /* clear the context structure first */
2698         memset(&tx_ctx, 0, sizeof(tx_ctx));
2699         tx_ctx.new_context = 1;
2700         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2701         tx_ctx.qlen = txq->nb_tx_desc;
2702
2703 #ifdef RTE_LIBRTE_IEEE1588
2704         tx_ctx.timesync_ena = 1;
2705 #endif
2706         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
2707         if (vsi->type == I40E_VSI_FDIR)
2708                 tx_ctx.fd_ena = TRUE;
2709
2710         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2711         if (err != I40E_SUCCESS) {
2712                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2713                 return err;
2714         }
2715
2716         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2717         if (err != I40E_SUCCESS) {
2718                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2719                 return err;
2720         }
2721
2722         /* Now associate this queue with this PCI function */
2723         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2724         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2725                                         I40E_QTX_CTL_PF_INDX_MASK);
2726         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2727         I40E_WRITE_FLUSH(hw);
2728
2729         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2730
2731         return err;
2732 }
2733
2734 int
2735 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2736 {
2737         struct i40e_rx_entry *rxe = rxq->sw_ring;
2738         uint64_t dma_addr;
2739         uint16_t i;
2740
2741         for (i = 0; i < rxq->nb_rx_desc; i++) {
2742                 volatile union i40e_rx_desc *rxd;
2743                 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2744
2745                 if (unlikely(!mbuf)) {
2746                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2747                         return -ENOMEM;
2748                 }
2749
2750                 rte_mbuf_refcnt_set(mbuf, 1);
2751                 mbuf->next = NULL;
2752                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2753                 mbuf->nb_segs = 1;
2754                 mbuf->port = rxq->port_id;
2755
2756                 dma_addr =
2757                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2758
2759                 rxd = &rxq->rx_ring[i];
2760                 rxd->read.pkt_addr = dma_addr;
2761                 rxd->read.hdr_addr = 0;
2762 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2763                 rxd->read.rsvd1 = 0;
2764                 rxd->read.rsvd2 = 0;
2765 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2766
2767                 rxe[i].mbuf = mbuf;
2768         }
2769
2770         return 0;
2771 }
2772
2773 /*
2774  * Calculate the buffer length, and check the jumbo frame
2775  * and maximum packet length.
2776  */
2777 static int
2778 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2779 {
2780         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2781         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2782         struct rte_eth_dev_data *data = pf->dev_data;
2783         uint16_t buf_size, len;
2784
2785         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2786                 RTE_PKTMBUF_HEADROOM);
2787
2788         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2789                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2790         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2791                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2792                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2793                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2794                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2795                 rxq->hs_mode = i40e_header_split_enabled;
2796                 break;
2797         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2798         default:
2799                 rxq->rx_hdr_len = 0;
2800                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2801                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2802                 rxq->hs_mode = i40e_header_split_none;
2803                 break;
2804         }
2805
2806         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2807         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2808         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2809                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2810                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2811                         PMD_DRV_LOG(ERR, "maximum packet length must "
2812                                     "be larger than %u and smaller than %u,"
2813                                     "as jumbo frame is enabled",
2814                                     (uint32_t)ETHER_MAX_LEN,
2815                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2816                         return I40E_ERR_CONFIG;
2817                 }
2818         } else {
2819                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2820                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2821                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2822                                     "larger than %u and smaller than %u, "
2823                                     "as jumbo frame is disabled",
2824                                     (uint32_t)ETHER_MIN_LEN,
2825                                     (uint32_t)ETHER_MAX_LEN);
2826                         return I40E_ERR_CONFIG;
2827                 }
2828         }
2829
2830         return 0;
2831 }
2832
2833 /* Init the RX queue in hardware */
2834 int
2835 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2836 {
2837         int err = I40E_SUCCESS;
2838         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2839         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2840         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
2841         uint16_t pf_q = rxq->reg_idx;
2842         uint16_t buf_size;
2843         struct i40e_hmc_obj_rxq rx_ctx;
2844
2845         err = i40e_rx_queue_config(rxq);
2846         if (err < 0) {
2847                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2848                 return err;
2849         }
2850
2851         /* Clear the context structure first */
2852         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2853         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2854         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2855
2856         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2857         rx_ctx.qlen = rxq->nb_rx_desc;
2858 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2859         rx_ctx.dsize = 1;
2860 #endif
2861         rx_ctx.dtype = rxq->hs_mode;
2862         if (rxq->hs_mode)
2863                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2864         else
2865                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2866         rx_ctx.rxmax = rxq->max_pkt_len;
2867         rx_ctx.tphrdesc_ena = 1;
2868         rx_ctx.tphwdesc_ena = 1;
2869         rx_ctx.tphdata_ena = 1;
2870         rx_ctx.tphhead_ena = 1;
2871         rx_ctx.lrxqthresh = 2;
2872         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2873         rx_ctx.l2tsel = 1;
2874         rx_ctx.showiv = 1;
2875         rx_ctx.prefena = 1;
2876
2877         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2878         if (err != I40E_SUCCESS) {
2879                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2880                 return err;
2881         }
2882         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2883         if (err != I40E_SUCCESS) {
2884                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2885                 return err;
2886         }
2887
2888         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2889
2890         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2891                 RTE_PKTMBUF_HEADROOM);
2892
2893         /* Check if scattered RX needs to be used. */
2894         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2895                 dev_data->scattered_rx = 1;
2896                 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2897         }
2898
2899         /* Init the RX tail regieter. */
2900         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2901
2902         return 0;
2903 }
2904
2905 void
2906 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2907 {
2908         uint16_t i;
2909
2910         PMD_INIT_FUNC_TRACE();
2911
2912         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2913                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2914                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2915         }
2916
2917         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2918                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2919                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2920         }
2921 }
2922
2923 void
2924 i40e_dev_free_queues(struct rte_eth_dev *dev)
2925 {
2926         uint16_t i;
2927
2928         PMD_INIT_FUNC_TRACE();
2929
2930         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2931                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2932                 dev->data->rx_queues[i] = NULL;
2933         }
2934         dev->data->nb_rx_queues = 0;
2935
2936         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2937                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2938                 dev->data->tx_queues[i] = NULL;
2939         }
2940         dev->data->nb_tx_queues = 0;
2941 }
2942
2943 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2944 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2945
2946 enum i40e_status_code
2947 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2948 {
2949         struct i40e_tx_queue *txq;
2950         const struct rte_memzone *tz = NULL;
2951         uint32_t ring_size;
2952         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2953
2954         if (!pf) {
2955                 PMD_DRV_LOG(ERR, "PF is not available");
2956                 return I40E_ERR_BAD_PTR;
2957         }
2958
2959         /* Allocate the TX queue data structure. */
2960         txq = rte_zmalloc_socket("i40e fdir tx queue",
2961                                   sizeof(struct i40e_tx_queue),
2962                                   RTE_CACHE_LINE_SIZE,
2963                                   SOCKET_ID_ANY);
2964         if (!txq) {
2965                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2966                                         "tx queue structure.");
2967                 return I40E_ERR_NO_MEMORY;
2968         }
2969
2970         /* Allocate TX hardware ring descriptors. */
2971         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2972         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2973
2974         tz = i40e_ring_dma_zone_reserve(dev,
2975                                         "fdir_tx_ring",
2976                                         I40E_FDIR_QUEUE_ID,
2977                                         ring_size,
2978                                         SOCKET_ID_ANY);
2979         if (!tz) {
2980                 i40e_dev_tx_queue_release(txq);
2981                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2982                 return I40E_ERR_NO_MEMORY;
2983         }
2984
2985         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2986         txq->queue_id = I40E_FDIR_QUEUE_ID;
2987         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2988         txq->vsi = pf->fdir.fdir_vsi;
2989
2990 #ifdef RTE_LIBRTE_XEN_DOM0
2991         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2992 #else
2993         txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2994 #endif
2995         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2996         /*
2997          * don't need to allocate software ring and reset for the fdir
2998          * program queue just set the queue has been configured.
2999          */
3000         txq->q_set = TRUE;
3001         pf->fdir.txq = txq;
3002
3003         return I40E_SUCCESS;
3004 }
3005
3006 enum i40e_status_code
3007 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3008 {
3009         struct i40e_rx_queue *rxq;
3010         const struct rte_memzone *rz = NULL;
3011         uint32_t ring_size;
3012         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3013
3014         if (!pf) {
3015                 PMD_DRV_LOG(ERR, "PF is not available");
3016                 return I40E_ERR_BAD_PTR;
3017         }
3018
3019         /* Allocate the RX queue data structure. */
3020         rxq = rte_zmalloc_socket("i40e fdir rx queue",
3021                                   sizeof(struct i40e_rx_queue),
3022                                   RTE_CACHE_LINE_SIZE,
3023                                   SOCKET_ID_ANY);
3024         if (!rxq) {
3025                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3026                                         "rx queue structure.");
3027                 return I40E_ERR_NO_MEMORY;
3028         }
3029
3030         /* Allocate RX hardware ring descriptors. */
3031         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3032         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3033
3034         rz = i40e_ring_dma_zone_reserve(dev,
3035                                         "fdir_rx_ring",
3036                                         I40E_FDIR_QUEUE_ID,
3037                                         ring_size,
3038                                         SOCKET_ID_ANY);
3039         if (!rz) {
3040                 i40e_dev_rx_queue_release(rxq);
3041                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3042                 return I40E_ERR_NO_MEMORY;
3043         }
3044
3045         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3046         rxq->queue_id = I40E_FDIR_QUEUE_ID;
3047         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3048         rxq->vsi = pf->fdir.fdir_vsi;
3049
3050 #ifdef RTE_LIBRTE_XEN_DOM0
3051         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
3052 #else
3053         rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
3054 #endif
3055         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3056
3057         /*
3058          * Don't need to allocate software ring and reset for the fdir
3059          * rx queue, just set the queue has been configured.
3060          */
3061         rxq->q_set = TRUE;
3062         pf->fdir.rxq = rxq;
3063
3064         return I40E_SUCCESS;
3065 }