drivers/net/i40e/i40e_rxtx_vec.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdint.h>
  35 #include <rte_ethdev.h>
  36 #include <rte_malloc.h>
  37
  38 #include "base/i40e_prototype.h"
  39 #include "base/i40e_type.h"
  40 #include "i40e_ethdev.h"
  41 #include "i40e_rxtx.h"
  42
  43 #include <tmmintrin.h>
  44
  45 #ifndef __INTEL_COMPILER
  46 #pragma GCC diagnostic ignored "-Wcast-qual"
  47 #endif
  48
  49 static inline void
  50 i40e_rxq_rearm(struct i40e_rx_queue *rxq)
  51 {
  52         int i;
  53         uint16_t rx_id;
  54         volatile union i40e_rx_desc *rxdp;
  55         struct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
  56         struct rte_mbuf *mb0, *mb1;
  57         __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
  58                         RTE_PKTMBUF_HEADROOM);
  59         __m128i dma_addr0, dma_addr1;
  60
  61         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  62
  63         /* Pull 'n' more MBUFs into the software ring */
  64         if (rte_mempool_get_bulk(rxq->mp,
  65                                  (void *)rxep,
  66                                  RTE_I40E_RXQ_REARM_THRESH) < 0) {
  67                 if (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=
  68                     rxq->nb_rx_desc) {
  69                         dma_addr0 = _mm_setzero_si128();
  70                         for (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {
  71                                 rxep[i].mbuf = &rxq->fake_mbuf;
  72                                 _mm_store_si128((__m128i *)&rxdp[i].read,
  73                                                 dma_addr0);
  74                         }
  75                 }
  76                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  77                         RTE_I40E_RXQ_REARM_THRESH;
  78                 return;
  79         }
  80
  81         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
  82         for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) {
  83                 __m128i vaddr0, vaddr1;
  84                 uintptr_t p0, p1;
  85
  86                 mb0 = rxep[0].mbuf;
  87                 mb1 = rxep[1].mbuf;
  88
  89                  /* Flush mbuf with pkt template.
  90                  * Data to be rearmed is 6 bytes long.
  91                  * Though, RX will overwrite ol_flags that are coming next
  92                  * anyway. So overwrite whole 8 bytes with one load:
  93                  * 6 bytes of rearm_data plus first 2 bytes of ol_flags.
  94                  */
  95                 p0 = (uintptr_t)&mb0->rearm_data;
  96                 *(uint64_t *)p0 = rxq->mbuf_initializer;
  97                 p1 = (uintptr_t)&mb1->rearm_data;
  98                 *(uint64_t *)p1 = rxq->mbuf_initializer;
  99
 100                 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
 101                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
 102                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
 103
 104                 /* convert pa to dma_addr hdr/data */
 105                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
 106                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
 107
 108                 /* add headroom to pa values */
 109                 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
 110                 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
 111
 112                 /* flush desc with pa dma_addr */
 113                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
 114                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
 115         }
 116
 117         rxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;
 118         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
 119                 rxq->rxrearm_start = 0;
 120
 121         rxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH;
 122
 123         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 124                              (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 125
 126         /* Update the tail pointer on the NIC */
 127         I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 128 }
 129
 130 /* Handling the offload flags (olflags) field takes computation
 131  * time when receiving packets. Therefore we provide a flag to disable
 132  * the processing of the olflags field when they are not needed. This
 133  * gives improved performance, at the cost of losing the offload info
 134  * in the received packet
 135  */
 136 #ifdef RTE_LIBRTE_I40E_RX_OLFLAGS_ENABLE
 137
 138 static inline void
 139 desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
 140 {
 141         __m128i vlan0, vlan1, rss;
 142         union {
 143                 uint16_t e[4];
 144                 uint64_t dword;
 145         } vol;
 146
 147         /* mask everything except rss and vlan flags
 148         *bit2 is for vlan tag, bits 13:12 for rss
 149         */
 150         const __m128i rss_vlan_msk = _mm_set_epi16(
 151                         0x0000, 0x0000, 0x0000, 0x0000,
 152                         0x3004, 0x3004, 0x3004, 0x3004);
 153
 154         /* map rss and vlan type to rss hash and vlan flag */
 155         const __m128i vlan_flags = _mm_set_epi8(0, 0, 0, 0,
 156                         0, 0, 0, 0,
 157                         0, 0, 0, PKT_RX_VLAN_PKT,
 158                         0, 0, 0, 0);
 159
 160         const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
 161                         0, 0, 0, 0,
 162                         0, 0, 0, 0,
 163                         PKT_RX_FDIR, 0, PKT_RX_RSS_HASH, 0);
 164
 165         vlan0 = _mm_unpackhi_epi16(descs[0], descs[1]);
 166         vlan1 = _mm_unpackhi_epi16(descs[2], descs[3]);
 167         vlan0 = _mm_unpacklo_epi32(vlan0, vlan1);
 168
 169         vlan1 = _mm_and_si128(vlan0, rss_vlan_msk);
 170         vlan0 = _mm_shuffle_epi8(vlan_flags, vlan1);
 171
 172         rss = _mm_srli_epi16(vlan1, 12);
 173         rss = _mm_shuffle_epi8(rss_flags, rss);
 174
 175         vlan0 = _mm_or_si128(vlan0, rss);
 176         vol.dword = _mm_cvtsi128_si64(vlan0);
 177
 178         rx_pkts[0]->ol_flags = vol.e[0];
 179         rx_pkts[1]->ol_flags = vol.e[1];
 180         rx_pkts[2]->ol_flags = vol.e[2];
 181         rx_pkts[3]->ol_flags = vol.e[3];
 182 }
 183 #else
 184 #define desc_to_olflags_v(desc, rx_pkts) do {} while (0)
 185 #endif
 186
 187 #define PKTLEN_SHIFT     10
 188
 189  /*
 190  * Notice:
 191  * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
 192  * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
 193  *   numbers of DD bits
 194  */
 195 static inline uint16_t
 196 _recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
 197                    uint16_t nb_pkts, uint8_t *split_packet)
 198 {
 199         volatile union i40e_rx_desc *rxdp;
 200         struct i40e_rx_entry *sw_ring;
 201         uint16_t nb_pkts_recd;
 202         int pos;
 203         uint64_t var;
 204         __m128i shuf_msk;
 205
 206         __m128i crc_adjust = _mm_set_epi16(
 207                                 0, 0, 0,    /* ignore non-length fields */
 208                                 -rxq->crc_len, /* sub crc on data_len */
 209                                 0,          /* ignore high-16bits of pkt_len */
 210                                 -rxq->crc_len, /* sub crc on pkt_len */
 211                                 0, 0            /* ignore pkt_type field */
 212                         );
 213         __m128i dd_check, eop_check;
 214
 215         /* nb_pkts shall be less equal than RTE_I40E_MAX_RX_BURST */
 216         nb_pkts = RTE_MIN(nb_pkts, RTE_I40E_MAX_RX_BURST);
 217
 218         /* nb_pkts has to be floor-aligned to RTE_I40E_DESCS_PER_LOOP */
 219         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_I40E_DESCS_PER_LOOP);
 220
 221         /* Just the act of getting into the function from the application is
 222          * going to cost about 7 cycles
 223          */
 224         rxdp = rxq->rx_ring + rxq->rx_tail;
 225
 226         _mm_prefetch((const void *)rxdp, _MM_HINT_T0);
 227
 228         /* See if we need to rearm the RX queue - gives the prefetch a bit
 229          * of time to act
 230          */
 231         if (rxq->rxrearm_nb > RTE_I40E_RXQ_REARM_THRESH)
 232                 i40e_rxq_rearm(rxq);
 233
 234         /* Before we start moving massive data around, check to see if
 235          * there is actually a packet available
 236          */
 237         if (!(rxdp->wb.qword1.status_error_len &
 238                         rte_cpu_to_le_32(1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 239                 return 0;
 240
 241         /* 4 packets DD mask */
 242         dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
 243
 244         /* 4 packets EOP mask */
 245         eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
 246
 247         /* mask to shuffle from desc. to mbuf */
 248         shuf_msk = _mm_set_epi8(
 249                 7, 6, 5, 4,  /* octet 4~7, 32bits rss */
 250                 3, 2,        /* octet 2~3, low 16 bits vlan_macip */
 251                 15, 14,      /* octet 15~14, 16 bits data_len */
 252                 0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
 253                 15, 14,      /* octet 15~14, low 16 bits pkt_len */
 254                 0xFF, 0xFF,  /* pkt_type set as unknown */
 255                 0xFF, 0xFF  /*pkt_type set as unknown */
 256                 );
 257
 258         /* Cache is empty -> need to scan the buffer rings, but first move
 259          * the next 'n' mbufs into the cache
 260          */
 261         sw_ring = &rxq->sw_ring[rxq->rx_tail];
 262
 263         /* A. load 4 packet in one loop
 264          * [A*. mask out 4 unused dirty field in desc]
 265          * B. copy 4 mbuf point from swring to rx_pkts
 266          * C. calc the number of DD bits among the 4 packets
 267          * [C*. extract the end-of-packet bit, if requested]
 268          * D. fill info. from desc to mbuf
 269          */
 270
 271         for (pos = 0, nb_pkts_recd = 0; pos < RTE_I40E_VPMD_RX_BURST;
 272                         pos += RTE_I40E_DESCS_PER_LOOP,
 273                         rxdp += RTE_I40E_DESCS_PER_LOOP) {
 274                 __m128i descs[RTE_I40E_DESCS_PER_LOOP];
 275                 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
 276                 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
 277                 __m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
 278
 279                 /* B.1 load 1 mbuf point */
 280                 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
 281                 /* Read desc statuses backwards to avoid race condition */
 282                 /* A.1 load 4 pkts desc */
 283                 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
 284
 285                 /* B.2 copy 2 mbuf point into rx_pkts  */
 286                 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
 287
 288                 /* B.1 load 1 mbuf point */
 289                 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
 290
 291                 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
 292                 /* B.1 load 2 mbuf point */
 293                 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
 294                 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
 295
 296                 /* B.2 copy 2 mbuf point into rx_pkts  */
 297                 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
 298
 299                 if (split_packet) {
 300                         rte_prefetch0(&rx_pkts[pos]->cacheline1);
 301                         rte_prefetch0(&rx_pkts[pos + 1]->cacheline1);
 302                         rte_prefetch0(&rx_pkts[pos + 2]->cacheline1);
 303                         rte_prefetch0(&rx_pkts[pos + 3]->cacheline1);
 304                 }
 305
 306                 /* avoid compiler reorder optimization */
 307                 rte_compiler_barrier();
 308
 309                 /* pkt 3,4 shift the pktlen field to be 16-bit aligned*/
 310                 const __m128i len3 = _mm_slli_epi32(descs[3], PKTLEN_SHIFT);
 311                 const __m128i len2 = _mm_slli_epi32(descs[2], PKTLEN_SHIFT);
 312
 313                 /* merge the now-aligned packet length fields back in */
 314                 descs[3] = _mm_blend_epi16(descs[3], len3, 0x80);
 315                 descs[2] = _mm_blend_epi16(descs[2], len2, 0x80);
 316
 317                 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
 318                 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
 319                 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
 320
 321                 /* C.1 4=>2 filter staterr info only */
 322                 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
 323                 /* C.1 4=>2 filter staterr info only */
 324                 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
 325
 326                 desc_to_olflags_v(descs, &rx_pkts[pos]);
 327
 328                 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
 329                 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
 330                 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
 331
 332                 /* pkt 1,2 shift the pktlen field to be 16-bit aligned*/
 333                 const __m128i len1 = _mm_slli_epi32(descs[1], PKTLEN_SHIFT);
 334                 const __m128i len0 = _mm_slli_epi32(descs[0], PKTLEN_SHIFT);
 335
 336                 /* merge the now-aligned packet length fields back in */
 337                 descs[1] = _mm_blend_epi16(descs[1], len1, 0x80);
 338                 descs[0] = _mm_blend_epi16(descs[0], len0, 0x80);
 339
 340                 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
 341                 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
 342                 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
 343
 344                 /* C.2 get 4 pkts staterr value  */
 345                 zero = _mm_xor_si128(dd_check, dd_check);
 346                 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
 347
 348                 /* D.3 copy final 3,4 data to rx_pkts */
 349                 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
 350                                  pkt_mb4);
 351                 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
 352                                  pkt_mb3);
 353
 354                 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
 355                 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
 356                 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
 357
 358                 /* C* extract and record EOP bit */
 359                 if (split_packet) {
 360                         __m128i eop_shuf_mask = _mm_set_epi8(
 361                                         0xFF, 0xFF, 0xFF, 0xFF,
 362                                         0xFF, 0xFF, 0xFF, 0xFF,
 363                                         0xFF, 0xFF, 0xFF, 0xFF,
 364                                         0x04, 0x0C, 0x00, 0x08
 365                                         );
 366
 367                         /* and with mask to extract bits, flipping 1-0 */
 368                         __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
 369                         /* the staterr values are not in order, as the count
 370                          * count of dd bits doesn't care. However, for end of
 371                          * packet tracking, we do care, so shuffle. This also
 372                          * compresses the 32-bit values to 8-bit
 373                          */
 374                         eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
 375                         /* store the resulting 32-bit value */
 376                         *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
 377                         split_packet += RTE_I40E_DESCS_PER_LOOP;
 378
 379                         /* zero-out next pointers */
 380                         rx_pkts[pos]->next = NULL;
 381                         rx_pkts[pos + 1]->next = NULL;
 382                         rx_pkts[pos + 2]->next = NULL;
 383                         rx_pkts[pos + 3]->next = NULL;
 384                 }
 385
 386                 /* C.3 calc available number of desc */
 387                 staterr = _mm_and_si128(staterr, dd_check);
 388                 staterr = _mm_packs_epi32(staterr, zero);
 389
 390                 /* D.3 copy final 1,2 data to rx_pkts */
 391                 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
 392                                  pkt_mb2);
 393                 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
 394                                  pkt_mb1);
 395                 /* C.4 calc avaialbe number of desc */
 396                 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
 397                 nb_pkts_recd += var;
 398                 if (likely(var != RTE_I40E_DESCS_PER_LOOP))
 399                         break;
 400         }
 401
 402         /* Update our internal tail pointer */
 403         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
 404         rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
 405         rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
 406
 407         return nb_pkts_recd;
 408 }
 409
 410  /*
 411  * Notice:
 412  * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
 413  * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
 414  *   numbers of DD bits
 415  */
 416 uint16_t
 417 i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 418                    uint16_t nb_pkts)
 419 {
 420         return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
 421 }
 422
 423 static inline uint16_t
 424 reassemble_packets(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_bufs,
 425                    uint16_t nb_bufs, uint8_t *split_flags)
 426 {
 427         struct rte_mbuf *pkts[RTE_I40E_VPMD_RX_BURST]; /*finished pkts*/
 428         struct rte_mbuf *start = rxq->pkt_first_seg;
 429         struct rte_mbuf *end =  rxq->pkt_last_seg;
 430         unsigned pkt_idx, buf_idx;
 431
 432         for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
 433                 if (end != NULL) {
 434                         /* processing a split packet */
 435                         end->next = rx_bufs[buf_idx];
 436                         rx_bufs[buf_idx]->data_len += rxq->crc_len;
 437
 438                         start->nb_segs++;
 439                         start->pkt_len += rx_bufs[buf_idx]->data_len;
 440                         end = end->next;
 441
 442                         if (!split_flags[buf_idx]) {
 443                                 /* it's the last packet of the set */
 444                                 start->hash = end->hash;
 445                                 start->ol_flags = end->ol_flags;
 446                                 /* we need to strip crc for the whole packet */
 447                                 start->pkt_len -= rxq->crc_len;
 448                                 if (end->data_len > rxq->crc_len) {
 449                                         end->data_len -= rxq->crc_len;
 450                                 } else {
 451                                         /* free up last mbuf */
 452                                         struct rte_mbuf *secondlast = start;
 453
 454                                         while (secondlast->next != end)
 455                                                 secondlast = secondlast->next;
 456                                         secondlast->data_len -= (rxq->crc_len -
 457                                                         end->data_len);
 458                                         secondlast->next = NULL;
 459                                         rte_pktmbuf_free_seg(end);
 460                                         end = secondlast;
 461                                 }
 462                                 pkts[pkt_idx++] = start;
 463                                 start = end = NULL;
 464                         }
 465                 } else {
 466                         /* not processing a split packet */
 467                         if (!split_flags[buf_idx]) {
 468                                 /* not a split packet, save and skip */
 469                                 pkts[pkt_idx++] = rx_bufs[buf_idx];
 470                                 continue;
 471                         }
 472                         end = start = rx_bufs[buf_idx];
 473                         rx_bufs[buf_idx]->data_len += rxq->crc_len;
 474                         rx_bufs[buf_idx]->pkt_len += rxq->crc_len;
 475                 }
 476         }
 477
 478         /* save the partial packet for next time */
 479         rxq->pkt_first_seg = start;
 480         rxq->pkt_last_seg = end;
 481         memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
 482         return pkt_idx;
 483 }
 484
 485  /* vPMD receive routine that reassembles scattered packets
 486  * Notice:
 487  * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
 488  * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
 489  *   numbers of DD bits
 490  */
 491 uint16_t
 492 i40e_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 493                              uint16_t nb_pkts)
 494 {
 495
 496         struct i40e_rx_queue *rxq = rx_queue;
 497         uint8_t split_flags[RTE_I40E_VPMD_RX_BURST] = {0};
 498
 499         /* get some new buffers */
 500         uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
 501                         split_flags);
 502         if (nb_bufs == 0)
 503                 return 0;
 504
 505         /* happy day case, full burst + no packets to be joined */
 506         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 507
 508         if (rxq->pkt_first_seg == NULL &&
 509                         split_fl64[0] == 0 && split_fl64[1] == 0 &&
 510                         split_fl64[2] == 0 && split_fl64[3] == 0)
 511                 return nb_bufs;
 512
 513         /* reassemble any packets that need reassembly*/
 514         unsigned i = 0;
 515
 516         if (rxq->pkt_first_seg == NULL) {
 517                 /* find the first split flag, and only reassemble then*/
 518                 while (i < nb_bufs && !split_flags[i])
 519                         i++;
 520                 if (i == nb_bufs)
 521                         return nb_bufs;
 522         }
 523         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 524                 &split_flags[i]);
 525 }
 526
 527 static inline void
 528 vtx1(volatile struct i40e_tx_desc *txdp,
 529                 struct rte_mbuf *pkt, uint64_t flags)
 530 {
 531         uint64_t high_qw = (I40E_TX_DESC_DTYPE_DATA |
 532                         ((uint64_t)flags  << I40E_TXD_QW1_CMD_SHIFT) |
 533                         ((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));
 534
 535         __m128i descriptor = _mm_set_epi64x(high_qw,
 536                                 pkt->buf_physaddr + pkt->data_off);
 537         _mm_store_si128((__m128i *)txdp, descriptor);
 538 }
 539
 540 static inline void
 541 vtx(volatile struct i40e_tx_desc *txdp,
 542                 struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
 543 {
 544         int i;
 545
 546         for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
 547                 vtx1(txdp, *pkt, flags);
 548 }
 549
 550 static inline int __attribute__((always_inline))
 551 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
 552 {
 553         struct i40e_tx_entry *txep;
 554         uint32_t n;
 555         uint32_t i;
 556         int nb_free = 0;
 557         struct rte_mbuf *m, *free[RTE_I40E_TX_MAX_FREE_BUF_SZ];
 558
 559         /* check DD bits on threshold descriptor */
 560         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
 561                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 562                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
 563                 return 0;
 564
 565         n = txq->tx_rs_thresh;
 566
 567          /* first buffer to free from S/W ring is at index
 568           * tx_next_dd - (tx_rs_thresh-1)
 569           */
 570         txep = &txq->sw_ring[txq->tx_next_dd - (n - 1)];
 571         m = __rte_pktmbuf_prefree_seg(txep[0].mbuf);
 572         if (likely(m != NULL)) {
 573                 free[0] = m;
 574                 nb_free = 1;
 575                 for (i = 1; i < n; i++) {
 576                         m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
 577                         if (likely(m != NULL)) {
 578                                 if (likely(m->pool == free[0]->pool)) {
 579                                         free[nb_free++] = m;
 580                                 } else {
 581                                         rte_mempool_put_bulk(free[0]->pool,
 582                                                              (void *)free,
 583                                                              nb_free);
 584                                         free[0] = m;
 585                                         nb_free = 1;
 586                                 }
 587                         }
 588                 }
 589                 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
 590         } else {
 591                 for (i = 1; i < n; i++) {
 592                         m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
 593                         if (m != NULL)
 594                                 rte_mempool_put(m->pool, m);
 595                 }
 596         }
 597
 598         /* buffers were freed, update counters */
 599         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
 600         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
 601         if (txq->tx_next_dd >= txq->nb_tx_desc)
 602                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 603
 604         return txq->tx_rs_thresh;
 605 }
 606
 607 static inline void __attribute__((always_inline))
 608 tx_backlog_entry(struct i40e_tx_entry *txep,
 609                  struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 610 {
 611         int i;
 612
 613         for (i = 0; i < (int)nb_pkts; ++i)
 614                 txep[i].mbuf = tx_pkts[i];
 615 }
 616
 617 uint16_t
 618 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 619                    uint16_t nb_pkts)
 620 {
 621         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
 622         volatile struct i40e_tx_desc *txdp;
 623         struct i40e_tx_entry *txep;
 624         uint16_t n, nb_commit, tx_id;
 625         uint64_t flags = I40E_TD_CMD;
 626         uint64_t rs = I40E_TX_DESC_CMD_RS | I40E_TD_CMD;
 627         int i;
 628
 629         /* cross rx_thresh boundary is not allowed */
 630         nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 631
 632         if (txq->nb_tx_free < txq->tx_free_thresh)
 633                 i40e_tx_free_bufs(txq);
 634
 635         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
 636         if (unlikely(nb_pkts == 0))
 637                 return 0;
 638
 639         tx_id = txq->tx_tail;
 640         txdp = &txq->tx_ring[tx_id];
 641         txep = &txq->sw_ring[tx_id];
 642
 643         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
 644
 645         n = (uint16_t)(txq->nb_tx_desc - tx_id);
 646         if (nb_commit >= n) {
 647                 tx_backlog_entry(txep, tx_pkts, n);
 648
 649                 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
 650                         vtx1(txdp, *tx_pkts, flags);
 651
 652                 vtx1(txdp, *tx_pkts++, rs);
 653
 654                 nb_commit = (uint16_t)(nb_commit - n);
 655
 656                 tx_id = 0;
 657                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 658
 659                 /* avoid reach the end of ring */
 660                 txdp = &txq->tx_ring[tx_id];
 661                 txep = &txq->sw_ring[tx_id];
 662         }
 663
 664         tx_backlog_entry(txep, tx_pkts, nb_commit);
 665
 666         vtx(txdp, tx_pkts, nb_commit, flags);
 667
 668         tx_id = (uint16_t)(tx_id + nb_commit);
 669         if (tx_id > txq->tx_next_rs) {
 670                 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
 671                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
 672                                                 I40E_TXD_QW1_CMD_SHIFT);
 673                 txq->tx_next_rs =
 674                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
 675         }
 676
 677         txq->tx_tail = tx_id;
 678
 679         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
 680
 681         return nb_pkts;
 682 }
 683
 684 void __attribute__((cold))
 685 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq)
 686 {
 687         const unsigned mask = rxq->nb_rx_desc - 1;
 688         unsigned i;
 689
 690         if (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_rx_desc)
 691                 return;
 692
 693         /* free all mbufs that are valid in the ring */
 694         for (i = rxq->rx_tail; i != rxq->rxrearm_start; i = (i + 1) & mask)
 695                 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 696         rxq->rxrearm_nb = rxq->nb_rx_desc;
 697
 698         /* set all entries to NULL */
 699         memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_rx_desc);
 700 }
 701
 702 int __attribute__((cold))
 703 i40e_rxq_vec_setup(struct i40e_rx_queue *rxq)
 704 {
 705         uintptr_t p;
 706         struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
 707
 708         mb_def.nb_segs = 1;
 709         mb_def.data_off = RTE_PKTMBUF_HEADROOM;
 710         mb_def.port = rxq->port_id;
 711         rte_mbuf_refcnt_set(&mb_def, 1);
 712
 713         /* prevent compiler reordering: rearm_data covers previous fields */
 714         rte_compiler_barrier();
 715         p = (uintptr_t)&mb_def.rearm_data;
 716         rxq->mbuf_initializer = *(uint64_t *)p;
 717         return 0;
 718 }
 719
 720 int __attribute__((cold))
 721 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
 722 {
 723         return 0;
 724 }
 725
 726 int __attribute__((cold))
 727 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
 728 {
 729 #ifndef RTE_LIBRTE_IEEE1588
 730         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
 731         struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
 732
 733         /* need SSE4.1 support */
 734         if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
 735                 return -1;
 736
 737 #ifndef RTE_LIBRTE_I40E_RX_OLFLAGS_ENABLE
 738         /* whithout rx ol_flags, no VP flag report */
 739         if (rxmode->hw_vlan_strip != 0 ||
 740             rxmode->hw_vlan_extend != 0)
 741                 return -1;
 742 #endif
 743
 744         /* no fdir support */
 745         if (fconf->mode != RTE_FDIR_MODE_NONE)
 746                 return -1;
 747
 748          /* - no csum error report support
 749          * - no header split support
 750          */
 751         if (rxmode->hw_ip_checksum == 1 ||
 752             rxmode->header_split == 1)
 753                 return -1;
 754
 755         return 0;
 756 #else
 757         RTE_SET_USED(dev);
 758         return -1;
 759 #endif
 760 }