1 /*******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_api.h"
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
53 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
54 * @hw: pointer to the hardware structure
57 * Returns an error code on error.
59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
63 status = ixgbe_clock_out_i2c_byte(hw, byte);
66 return ixgbe_get_i2c_ack(hw);
70 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
71 * @hw: pointer to the hardware structure
72 * @byte: pointer to a u8 to receive the byte
74 * Returns an error code on error.
76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
80 status = ixgbe_clock_in_i2c_byte(hw, byte);
84 return ixgbe_clock_out_i2c_bit(hw, false);
88 * ixgbe_ones_comp_byte_add - Perform one's complement addition
92 * Returns one's complement 8-bit sum.
94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
96 u16 sum = add1 + add2;
98 sum = (sum & 0xFF) + (sum >> 8);
103 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
104 * @hw: pointer to the hardware structure
105 * @addr: I2C bus address to read from
106 * @reg: I2C device register to read from
107 * @val: pointer to location to receive read value
109 * Returns an error code on error.
111 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
114 u32 swfw_mask = hw->phy.phy_semaphore_mask;
123 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
124 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
127 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
128 return IXGBE_ERR_SWFW_SYNC;
130 /* Device Address and write indication */
131 if (ixgbe_out_i2c_byte_ack(hw, addr))
133 /* Write bits 14:8 */
134 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
137 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
140 if (ixgbe_out_i2c_byte_ack(hw, csum))
142 /* Re-start condition */
144 /* Device Address and read indication */
145 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
148 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
151 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
154 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
157 if (ixgbe_clock_out_i2c_bit(hw, false))
160 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
161 *val = (high_bits << 8) | low_bits;
165 ixgbe_i2c_bus_clear(hw);
166 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
168 if (retry < max_retry)
169 DEBUGOUT("I2C byte read combined error - Retrying.\n");
171 DEBUGOUT("I2C byte read combined error.\n");
172 } while (retry < max_retry);
174 return IXGBE_ERR_I2C;
178 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
179 * @hw: pointer to the hardware structure
180 * @addr: I2C bus address to write to
181 * @reg: I2C device register to write to
182 * @val: value to write
184 * Returns an error code on error.
186 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
187 u8 addr, u16 reg, u16 val)
194 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
195 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
196 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
197 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
201 /* Device Address and write indication */
202 if (ixgbe_out_i2c_byte_ack(hw, addr))
204 /* Write bits 14:8 */
205 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
208 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
210 /* Write data 15:8 */
211 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
214 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
217 if (ixgbe_out_i2c_byte_ack(hw, csum))
223 ixgbe_i2c_bus_clear(hw);
225 if (retry < max_retry)
226 DEBUGOUT("I2C byte write combined error - Retrying.\n");
228 DEBUGOUT("I2C byte write combined error.\n");
229 } while (retry < max_retry);
231 return IXGBE_ERR_I2C;
235 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
236 * @hw: pointer to the hardware structure
238 * Initialize the function pointers.
240 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
242 struct ixgbe_phy_info *phy = &hw->phy;
244 DEBUGFUNC("ixgbe_init_phy_ops_generic");
247 phy->ops.identify = ixgbe_identify_phy_generic;
248 phy->ops.reset = ixgbe_reset_phy_generic;
249 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
250 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
251 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
252 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
253 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
254 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
255 phy->ops.check_link = NULL;
256 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
257 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
258 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
259 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
260 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
261 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
262 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
263 phy->ops.identify_sfp = ixgbe_identify_module_generic;
264 phy->sfp_type = ixgbe_sfp_type_unknown;
265 phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic;
266 phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic;
267 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
268 return IXGBE_SUCCESS;
272 * ixgbe_identify_phy_generic - Get physical layer module
273 * @hw: pointer to hardware structure
275 * Determines the physical layer module found on the current adapter.
277 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
279 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
283 DEBUGFUNC("ixgbe_identify_phy_generic");
285 if (!hw->phy.phy_semaphore_mask) {
287 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
289 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
292 if (hw->phy.type == ixgbe_phy_unknown) {
293 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
294 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
295 hw->phy.addr = phy_addr;
296 ixgbe_get_phy_id(hw);
298 ixgbe_get_phy_type_from_id(hw->phy.id);
300 if (hw->phy.type == ixgbe_phy_unknown) {
301 hw->phy.ops.read_reg(hw,
302 IXGBE_MDIO_PHY_EXT_ABILITY,
303 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
306 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
307 IXGBE_MDIO_PHY_1000BASET_ABILITY))
309 ixgbe_phy_cu_unknown;
315 status = IXGBE_SUCCESS;
320 /* Certain media types do not have a phy so an address will not
321 * be found and the code will take this path. Caller has to
322 * decide if it is an error or not.
324 if (status != IXGBE_SUCCESS) {
328 status = IXGBE_SUCCESS;
335 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
336 * @hw: pointer to the hardware structure
338 * This function checks the MMNGC.MNG_VETO bit to see if there are
339 * any constraints on link from manageability. For MAC's that don't
340 * have this bit just return faluse since the link can not be blocked
343 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
347 DEBUGFUNC("ixgbe_check_reset_blocked");
349 /* If we don't have this bit, it can't be blocking */
350 if (hw->mac.type == ixgbe_mac_82598EB)
353 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
354 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
355 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
356 "MNG_VETO bit detected.\n");
364 * ixgbe_validate_phy_addr - Determines phy address is valid
365 * @hw: pointer to hardware structure
368 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
373 DEBUGFUNC("ixgbe_validate_phy_addr");
375 hw->phy.addr = phy_addr;
376 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
377 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
379 if (phy_id != 0xFFFF && phy_id != 0x0)
386 * ixgbe_get_phy_id - Get the phy type
387 * @hw: pointer to hardware structure
390 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
396 DEBUGFUNC("ixgbe_get_phy_id");
398 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
399 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
402 if (status == IXGBE_SUCCESS) {
403 hw->phy.id = (u32)(phy_id_high << 16);
404 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
405 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
407 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
408 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
414 * ixgbe_get_phy_type_from_id - Get the phy type
415 * @hw: pointer to hardware structure
418 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
420 enum ixgbe_phy_type phy_type;
422 DEBUGFUNC("ixgbe_get_phy_type_from_id");
426 phy_type = ixgbe_phy_tn;
430 phy_type = ixgbe_phy_aq;
433 phy_type = ixgbe_phy_qt;
436 phy_type = ixgbe_phy_nl;
439 phy_type = ixgbe_phy_x550em_ext_t;
442 phy_type = ixgbe_phy_unknown;
446 DEBUGOUT1("phy type found is %d\n", phy_type);
451 * ixgbe_reset_phy_generic - Performs a PHY reset
452 * @hw: pointer to hardware structure
454 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
458 s32 status = IXGBE_SUCCESS;
460 DEBUGFUNC("ixgbe_reset_phy_generic");
462 if (hw->phy.type == ixgbe_phy_unknown)
463 status = ixgbe_identify_phy_generic(hw);
465 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
468 /* Don't reset PHY if it's shut down due to overtemp. */
469 if (!hw->phy.reset_if_overtemp &&
470 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
473 /* Blocked by MNG FW so bail */
474 if (ixgbe_check_reset_blocked(hw))
478 * Perform soft PHY reset to the PHY_XS.
479 * This will cause a soft reset to the PHY
481 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
482 IXGBE_MDIO_PHY_XS_DEV_TYPE,
483 IXGBE_MDIO_PHY_XS_RESET);
486 * Poll for reset bit to self-clear indicating reset is complete.
487 * Some PHYs could take up to 3 seconds to complete and need about
488 * 1.7 usec delay after the reset is complete.
490 for (i = 0; i < 30; i++) {
492 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
493 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
494 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
500 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
501 status = IXGBE_ERR_RESET_FAILED;
502 ERROR_REPORT1(IXGBE_ERROR_POLLING,
503 "PHY reset polling failed to complete.\n");
511 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
513 * @hw: pointer to hardware structure
514 * @reg_addr: 32 bit address of PHY register to read
515 * @phy_data: Pointer to read data from PHY register
517 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
520 u32 i, data, command;
522 /* Setup and write the address cycle command */
523 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
524 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
525 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
526 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
528 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
531 * Check every 10 usec to see if the address cycle completed.
532 * The MDI Command bit will clear when the operation is
535 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
538 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
539 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
544 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
545 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
546 return IXGBE_ERR_PHY;
550 * Address cycle complete, setup and write the read
553 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
554 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
555 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
556 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
558 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
561 * Check every 10 usec to see if the address cycle
562 * completed. The MDI Command bit will clear when the
563 * operation is complete
565 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
568 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
569 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
573 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
574 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
575 return IXGBE_ERR_PHY;
579 * Read operation is complete. Get the data
582 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
583 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
584 *phy_data = (u16)(data);
586 return IXGBE_SUCCESS;
590 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
591 * using the SWFW lock - this function is needed in most cases
592 * @hw: pointer to hardware structure
593 * @reg_addr: 32 bit address of PHY register to read
594 * @phy_data: Pointer to read data from PHY register
596 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
597 u32 device_type, u16 *phy_data)
600 u32 gssr = hw->phy.phy_semaphore_mask;
602 DEBUGFUNC("ixgbe_read_phy_reg_generic");
604 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
605 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
607 hw->mac.ops.release_swfw_sync(hw, gssr);
609 status = IXGBE_ERR_SWFW_SYNC;
616 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
618 * @hw: pointer to hardware structure
619 * @reg_addr: 32 bit PHY register to write
620 * @device_type: 5 bit device type
621 * @phy_data: Data to write to the PHY register
623 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
624 u32 device_type, u16 phy_data)
628 /* Put the data in the MDI single read and write data register*/
629 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
631 /* Setup and write the address cycle command */
632 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
633 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
634 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
635 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
637 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
640 * Check every 10 usec to see if the address cycle completed.
641 * The MDI Command bit will clear when the operation is
644 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
647 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
648 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
652 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
653 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
654 return IXGBE_ERR_PHY;
658 * Address cycle complete, setup and write the write
661 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
662 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
663 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
664 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
666 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
669 * Check every 10 usec to see if the address cycle
670 * completed. The MDI Command bit will clear when the
671 * operation is complete
673 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
676 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
677 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
681 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
682 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
683 return IXGBE_ERR_PHY;
686 return IXGBE_SUCCESS;
690 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
691 * using SWFW lock- this function is needed in most cases
692 * @hw: pointer to hardware structure
693 * @reg_addr: 32 bit PHY register to write
694 * @device_type: 5 bit device type
695 * @phy_data: Data to write to the PHY register
697 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
698 u32 device_type, u16 phy_data)
701 u32 gssr = hw->phy.phy_semaphore_mask;
703 DEBUGFUNC("ixgbe_write_phy_reg_generic");
705 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
706 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
708 hw->mac.ops.release_swfw_sync(hw, gssr);
710 status = IXGBE_ERR_SWFW_SYNC;
717 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
718 * @hw: pointer to hardware structure
720 * Restart auto-negotiation and PHY and waits for completion.
722 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
724 s32 status = IXGBE_SUCCESS;
725 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
726 bool autoneg = false;
727 ixgbe_link_speed speed;
729 DEBUGFUNC("ixgbe_setup_phy_link_generic");
731 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
733 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
734 /* Set or unset auto-negotiation 10G advertisement */
735 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
736 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
739 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
740 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
741 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
743 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
744 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
748 if (hw->mac.type == ixgbe_mac_X550) {
749 if (speed & IXGBE_LINK_SPEED_5GB_FULL) {
750 /* Set or unset auto-negotiation 1G advertisement */
751 hw->phy.ops.read_reg(hw,
752 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
753 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
756 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
757 if (hw->phy.autoneg_advertised &
758 IXGBE_LINK_SPEED_5GB_FULL)
759 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
761 hw->phy.ops.write_reg(hw,
762 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
763 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
767 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {
768 /* Set or unset auto-negotiation 1G advertisement */
769 hw->phy.ops.read_reg(hw,
770 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
771 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
774 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
775 if (hw->phy.autoneg_advertised &
776 IXGBE_LINK_SPEED_2_5GB_FULL)
777 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
779 hw->phy.ops.write_reg(hw,
780 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
781 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
786 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
787 /* Set or unset auto-negotiation 1G advertisement */
788 hw->phy.ops.read_reg(hw,
789 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
790 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
793 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
794 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
795 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
797 hw->phy.ops.write_reg(hw,
798 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
799 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
803 if (speed & IXGBE_LINK_SPEED_100_FULL) {
804 /* Set or unset auto-negotiation 100M advertisement */
805 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
806 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
809 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
810 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
811 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
812 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
814 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
815 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
819 /* Blocked by MNG FW so don't reset PHY */
820 if (ixgbe_check_reset_blocked(hw))
823 /* Restart PHY auto-negotiation. */
824 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
825 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
827 autoneg_reg |= IXGBE_MII_RESTART;
829 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
830 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
836 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
837 * @hw: pointer to hardware structure
838 * @speed: new link speed
840 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
841 ixgbe_link_speed speed,
842 bool autoneg_wait_to_complete)
844 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
846 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
849 * Clear autoneg_advertised and set new values based on input link
852 hw->phy.autoneg_advertised = 0;
854 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
855 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
857 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
858 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
860 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
861 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
863 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
864 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
866 if (speed & IXGBE_LINK_SPEED_100_FULL)
867 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
869 /* Setup link based on the new speed settings */
870 hw->phy.ops.setup_link(hw);
872 return IXGBE_SUCCESS;
876 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
877 * @hw: pointer to hardware structure
878 * @speed: pointer to link speed
879 * @autoneg: boolean auto-negotiation value
881 * Determines the supported link capabilities by reading the PHY auto
882 * negotiation register.
884 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
885 ixgbe_link_speed *speed,
891 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
896 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
897 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
900 if (status == IXGBE_SUCCESS) {
901 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
902 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
903 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
904 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
905 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
906 *speed |= IXGBE_LINK_SPEED_100_FULL;
909 /* Internal PHY does not support 100 Mbps */
910 if (hw->mac.type == ixgbe_mac_X550EM_x)
911 *speed &= ~IXGBE_LINK_SPEED_100_FULL;
913 if (hw->mac.type == ixgbe_mac_X550) {
914 *speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
915 *speed |= IXGBE_LINK_SPEED_5GB_FULL;
922 * ixgbe_check_phy_link_tnx - Determine link and speed status
923 * @hw: pointer to hardware structure
925 * Reads the VS1 register to determine if link is up and the current speed for
928 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
931 s32 status = IXGBE_SUCCESS;
933 u32 max_time_out = 10;
938 DEBUGFUNC("ixgbe_check_phy_link_tnx");
940 /* Initialize speed and link to default case */
942 *speed = IXGBE_LINK_SPEED_10GB_FULL;
945 * Check current speed and link status of the PHY register.
946 * This is a vendor specific register and may have to
947 * be changed for other copper PHYs.
949 for (time_out = 0; time_out < max_time_out; time_out++) {
951 status = hw->phy.ops.read_reg(hw,
952 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
953 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
955 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
956 phy_speed = phy_data &
957 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
958 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
961 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
962 *speed = IXGBE_LINK_SPEED_1GB_FULL;
971 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
972 * @hw: pointer to hardware structure
974 * Restart auto-negotiation and PHY and waits for completion.
976 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
978 s32 status = IXGBE_SUCCESS;
979 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
980 bool autoneg = false;
981 ixgbe_link_speed speed;
983 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
985 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
987 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
988 /* Set or unset auto-negotiation 10G advertisement */
989 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
990 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
993 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
994 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
995 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
997 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
998 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1002 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1003 /* Set or unset auto-negotiation 1G advertisement */
1004 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1005 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1008 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1009 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1010 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1012 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1013 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1017 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1018 /* Set or unset auto-negotiation 100M advertisement */
1019 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1020 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1023 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1024 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1025 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1027 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1028 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1032 /* Blocked by MNG FW so don't reset PHY */
1033 if (ixgbe_check_reset_blocked(hw))
1036 /* Restart PHY auto-negotiation. */
1037 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1038 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1040 autoneg_reg |= IXGBE_MII_RESTART;
1042 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1043 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1049 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1050 * @hw: pointer to hardware structure
1051 * @firmware_version: pointer to the PHY Firmware Version
1053 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1054 u16 *firmware_version)
1058 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1060 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1061 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1068 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1069 * @hw: pointer to hardware structure
1070 * @firmware_version: pointer to the PHY Firmware Version
1072 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1073 u16 *firmware_version)
1077 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1079 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1080 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1087 * ixgbe_reset_phy_nl - Performs a PHY reset
1088 * @hw: pointer to hardware structure
1090 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1092 u16 phy_offset, control, eword, edata, block_crc;
1093 bool end_data = false;
1094 u16 list_offset, data_offset;
1096 s32 ret_val = IXGBE_SUCCESS;
1099 DEBUGFUNC("ixgbe_reset_phy_nl");
1101 /* Blocked by MNG FW so bail */
1102 if (ixgbe_check_reset_blocked(hw))
1105 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1106 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1108 /* reset the PHY and poll for completion */
1109 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1110 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1111 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1113 for (i = 0; i < 100; i++) {
1114 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1115 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1116 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1121 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1122 DEBUGOUT("PHY reset did not complete.\n");
1123 ret_val = IXGBE_ERR_PHY;
1127 /* Get init offsets */
1128 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1130 if (ret_val != IXGBE_SUCCESS)
1133 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1137 * Read control word from PHY init contents offset
1139 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1142 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1143 IXGBE_CONTROL_SHIFT_NL;
1144 edata = eword & IXGBE_DATA_MASK_NL;
1146 case IXGBE_DELAY_NL:
1148 DEBUGOUT1("DELAY: %d MS\n", edata);
1152 DEBUGOUT("DATA:\n");
1154 ret_val = hw->eeprom.ops.read(hw, data_offset,
1159 for (i = 0; i < edata; i++) {
1160 ret_val = hw->eeprom.ops.read(hw, data_offset,
1164 hw->phy.ops.write_reg(hw, phy_offset,
1165 IXGBE_TWINAX_DEV, eword);
1166 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1172 case IXGBE_CONTROL_NL:
1174 DEBUGOUT("CONTROL:\n");
1175 if (edata == IXGBE_CONTROL_EOL_NL) {
1178 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1181 DEBUGOUT("Bad control value\n");
1182 ret_val = IXGBE_ERR_PHY;
1187 DEBUGOUT("Bad control type\n");
1188 ret_val = IXGBE_ERR_PHY;
1197 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1198 "eeprom read at offset %d failed", data_offset);
1199 return IXGBE_ERR_PHY;
1203 * ixgbe_identify_module_generic - Identifies module type
1204 * @hw: pointer to hardware structure
1206 * Determines HW type and calls appropriate function.
1208 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1210 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1212 DEBUGFUNC("ixgbe_identify_module_generic");
1214 switch (hw->mac.ops.get_media_type(hw)) {
1215 case ixgbe_media_type_fiber:
1216 status = ixgbe_identify_sfp_module_generic(hw);
1219 case ixgbe_media_type_fiber_qsfp:
1220 status = ixgbe_identify_qsfp_module_generic(hw);
1224 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1225 status = IXGBE_ERR_SFP_NOT_PRESENT;
1233 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1234 * @hw: pointer to hardware structure
1236 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1238 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1240 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1242 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1244 u8 comp_codes_1g = 0;
1245 u8 comp_codes_10g = 0;
1246 u8 oui_bytes[3] = {0, 0, 0};
1249 u16 enforce_sfp = 0;
1251 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1253 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1254 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1255 status = IXGBE_ERR_SFP_NOT_PRESENT;
1259 /* LAN ID is needed for I2C access */
1260 hw->mac.ops.set_lan_id(hw);
1262 status = hw->phy.ops.read_i2c_eeprom(hw,
1263 IXGBE_SFF_IDENTIFIER,
1266 if (status != IXGBE_SUCCESS)
1267 goto err_read_i2c_eeprom;
1269 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1270 hw->phy.type = ixgbe_phy_sfp_unsupported;
1271 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1273 status = hw->phy.ops.read_i2c_eeprom(hw,
1274 IXGBE_SFF_1GBE_COMP_CODES,
1277 if (status != IXGBE_SUCCESS)
1278 goto err_read_i2c_eeprom;
1280 status = hw->phy.ops.read_i2c_eeprom(hw,
1281 IXGBE_SFF_10GBE_COMP_CODES,
1284 if (status != IXGBE_SUCCESS)
1285 goto err_read_i2c_eeprom;
1286 status = hw->phy.ops.read_i2c_eeprom(hw,
1287 IXGBE_SFF_CABLE_TECHNOLOGY,
1290 if (status != IXGBE_SUCCESS)
1291 goto err_read_i2c_eeprom;
1298 * 3 SFP_DA_CORE0 - 82599-specific
1299 * 4 SFP_DA_CORE1 - 82599-specific
1300 * 5 SFP_SR/LR_CORE0 - 82599-specific
1301 * 6 SFP_SR/LR_CORE1 - 82599-specific
1302 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1303 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1304 * 9 SFP_1g_cu_CORE0 - 82599-specific
1305 * 10 SFP_1g_cu_CORE1 - 82599-specific
1306 * 11 SFP_1g_sx_CORE0 - 82599-specific
1307 * 12 SFP_1g_sx_CORE1 - 82599-specific
1309 if (hw->mac.type == ixgbe_mac_82598EB) {
1310 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1311 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1312 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1313 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1314 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1315 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1317 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1319 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1320 if (hw->bus.lan_id == 0)
1322 ixgbe_sfp_type_da_cu_core0;
1325 ixgbe_sfp_type_da_cu_core1;
1326 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1327 hw->phy.ops.read_i2c_eeprom(
1328 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1331 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1332 if (hw->bus.lan_id == 0)
1334 ixgbe_sfp_type_da_act_lmt_core0;
1337 ixgbe_sfp_type_da_act_lmt_core1;
1340 ixgbe_sfp_type_unknown;
1342 } else if (comp_codes_10g &
1343 (IXGBE_SFF_10GBASESR_CAPABLE |
1344 IXGBE_SFF_10GBASELR_CAPABLE)) {
1345 if (hw->bus.lan_id == 0)
1347 ixgbe_sfp_type_srlr_core0;
1350 ixgbe_sfp_type_srlr_core1;
1351 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1352 if (hw->bus.lan_id == 0)
1354 ixgbe_sfp_type_1g_cu_core0;
1357 ixgbe_sfp_type_1g_cu_core1;
1358 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1359 if (hw->bus.lan_id == 0)
1361 ixgbe_sfp_type_1g_sx_core0;
1364 ixgbe_sfp_type_1g_sx_core1;
1365 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1366 if (hw->bus.lan_id == 0)
1368 ixgbe_sfp_type_1g_lx_core0;
1371 ixgbe_sfp_type_1g_lx_core1;
1373 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1377 if (hw->phy.sfp_type != stored_sfp_type)
1378 hw->phy.sfp_setup_needed = true;
1380 /* Determine if the SFP+ PHY is dual speed or not. */
1381 hw->phy.multispeed_fiber = false;
1382 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1383 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1384 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1385 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1386 hw->phy.multispeed_fiber = true;
1388 /* Determine PHY vendor */
1389 if (hw->phy.type != ixgbe_phy_nl) {
1390 hw->phy.id = identifier;
1391 status = hw->phy.ops.read_i2c_eeprom(hw,
1392 IXGBE_SFF_VENDOR_OUI_BYTE0,
1395 if (status != IXGBE_SUCCESS)
1396 goto err_read_i2c_eeprom;
1398 status = hw->phy.ops.read_i2c_eeprom(hw,
1399 IXGBE_SFF_VENDOR_OUI_BYTE1,
1402 if (status != IXGBE_SUCCESS)
1403 goto err_read_i2c_eeprom;
1405 status = hw->phy.ops.read_i2c_eeprom(hw,
1406 IXGBE_SFF_VENDOR_OUI_BYTE2,
1409 if (status != IXGBE_SUCCESS)
1410 goto err_read_i2c_eeprom;
1413 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1414 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1415 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1417 switch (vendor_oui) {
1418 case IXGBE_SFF_VENDOR_OUI_TYCO:
1419 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1421 ixgbe_phy_sfp_passive_tyco;
1423 case IXGBE_SFF_VENDOR_OUI_FTL:
1424 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1425 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1427 hw->phy.type = ixgbe_phy_sfp_ftl;
1429 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1430 hw->phy.type = ixgbe_phy_sfp_avago;
1432 case IXGBE_SFF_VENDOR_OUI_INTEL:
1433 hw->phy.type = ixgbe_phy_sfp_intel;
1436 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1438 ixgbe_phy_sfp_passive_unknown;
1439 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1441 ixgbe_phy_sfp_active_unknown;
1443 hw->phy.type = ixgbe_phy_sfp_unknown;
1448 /* Allow any DA cable vendor */
1449 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1450 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1451 status = IXGBE_SUCCESS;
1455 /* Verify supported 1G SFP modules */
1456 if (comp_codes_10g == 0 &&
1457 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1458 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1459 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1460 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1461 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1462 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1463 hw->phy.type = ixgbe_phy_sfp_unsupported;
1464 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1468 /* Anything else 82598-based is supported */
1469 if (hw->mac.type == ixgbe_mac_82598EB) {
1470 status = IXGBE_SUCCESS;
1474 ixgbe_get_device_caps(hw, &enforce_sfp);
1475 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1476 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1477 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1478 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1479 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1480 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1481 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1482 /* Make sure we're a supported PHY type */
1483 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1484 status = IXGBE_SUCCESS;
1486 if (hw->allow_unsupported_sfp == true) {
1487 EWARN(hw, "WARNING: Intel (R) Network "
1488 "Connections are quality tested "
1489 "using Intel (R) Ethernet Optics."
1490 " Using untested modules is not "
1491 "supported and may cause unstable"
1492 " operation or damage to the "
1493 "module or the adapter. Intel "
1494 "Corporation is not responsible "
1495 "for any harm caused by using "
1496 "untested modules.\n", status);
1497 status = IXGBE_SUCCESS;
1499 DEBUGOUT("SFP+ module not supported\n");
1501 ixgbe_phy_sfp_unsupported;
1502 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1506 status = IXGBE_SUCCESS;
1513 err_read_i2c_eeprom:
1514 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1515 if (hw->phy.type != ixgbe_phy_nl) {
1517 hw->phy.type = ixgbe_phy_unknown;
1519 return IXGBE_ERR_SFP_NOT_PRESENT;
1523 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1524 * @hw: pointer to hardware structure
1526 * Determines physical layer capabilities of the current SFP.
1528 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1530 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1531 u8 comp_codes_10g = 0;
1532 u8 comp_codes_1g = 0;
1534 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1536 hw->phy.ops.identify_sfp(hw);
1537 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1538 return physical_layer;
1540 switch (hw->phy.type) {
1541 case ixgbe_phy_sfp_passive_tyco:
1542 case ixgbe_phy_sfp_passive_unknown:
1543 case ixgbe_phy_qsfp_passive_unknown:
1544 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1546 case ixgbe_phy_sfp_ftl_active:
1547 case ixgbe_phy_sfp_active_unknown:
1548 case ixgbe_phy_qsfp_active_unknown:
1549 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1551 case ixgbe_phy_sfp_avago:
1552 case ixgbe_phy_sfp_ftl:
1553 case ixgbe_phy_sfp_intel:
1554 case ixgbe_phy_sfp_unknown:
1555 hw->phy.ops.read_i2c_eeprom(hw,
1556 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1557 hw->phy.ops.read_i2c_eeprom(hw,
1558 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1559 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1560 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1561 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1562 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1563 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1564 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1565 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1566 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1568 case ixgbe_phy_qsfp_intel:
1569 case ixgbe_phy_qsfp_unknown:
1570 hw->phy.ops.read_i2c_eeprom(hw,
1571 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1572 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1573 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1574 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1575 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1581 return physical_layer;
1585 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1586 * @hw: pointer to hardware structure
1588 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1590 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1592 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1594 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1596 u8 comp_codes_1g = 0;
1597 u8 comp_codes_10g = 0;
1598 u8 oui_bytes[3] = {0, 0, 0};
1599 u16 enforce_sfp = 0;
1601 u8 cable_length = 0;
1603 bool active_cable = false;
1605 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1607 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1608 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1609 status = IXGBE_ERR_SFP_NOT_PRESENT;
1613 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1616 if (status != IXGBE_SUCCESS)
1617 goto err_read_i2c_eeprom;
1619 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1620 hw->phy.type = ixgbe_phy_sfp_unsupported;
1621 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1625 hw->phy.id = identifier;
1627 /* LAN ID is needed for sfp_type determination */
1628 hw->mac.ops.set_lan_id(hw);
1630 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1633 if (status != IXGBE_SUCCESS)
1634 goto err_read_i2c_eeprom;
1636 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1639 if (status != IXGBE_SUCCESS)
1640 goto err_read_i2c_eeprom;
1642 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1643 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1644 if (hw->bus.lan_id == 0)
1645 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1647 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1648 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1649 IXGBE_SFF_10GBASELR_CAPABLE)) {
1650 if (hw->bus.lan_id == 0)
1651 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1653 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1655 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1656 active_cable = true;
1658 if (!active_cable) {
1659 /* check for active DA cables that pre-date
1661 hw->phy.ops.read_i2c_eeprom(hw,
1662 IXGBE_SFF_QSFP_CONNECTOR,
1665 hw->phy.ops.read_i2c_eeprom(hw,
1666 IXGBE_SFF_QSFP_CABLE_LENGTH,
1669 hw->phy.ops.read_i2c_eeprom(hw,
1670 IXGBE_SFF_QSFP_DEVICE_TECH,
1674 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1675 (cable_length > 0) &&
1676 ((device_tech >> 4) ==
1677 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1678 active_cable = true;
1682 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1683 if (hw->bus.lan_id == 0)
1685 ixgbe_sfp_type_da_act_lmt_core0;
1688 ixgbe_sfp_type_da_act_lmt_core1;
1690 /* unsupported module type */
1691 hw->phy.type = ixgbe_phy_sfp_unsupported;
1692 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1697 if (hw->phy.sfp_type != stored_sfp_type)
1698 hw->phy.sfp_setup_needed = true;
1700 /* Determine if the QSFP+ PHY is dual speed or not. */
1701 hw->phy.multispeed_fiber = false;
1702 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1703 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1704 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1705 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1706 hw->phy.multispeed_fiber = true;
1708 /* Determine PHY vendor for optical modules */
1709 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1710 IXGBE_SFF_10GBASELR_CAPABLE)) {
1711 status = hw->phy.ops.read_i2c_eeprom(hw,
1712 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1715 if (status != IXGBE_SUCCESS)
1716 goto err_read_i2c_eeprom;
1718 status = hw->phy.ops.read_i2c_eeprom(hw,
1719 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1722 if (status != IXGBE_SUCCESS)
1723 goto err_read_i2c_eeprom;
1725 status = hw->phy.ops.read_i2c_eeprom(hw,
1726 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1729 if (status != IXGBE_SUCCESS)
1730 goto err_read_i2c_eeprom;
1733 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1734 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1735 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1737 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1738 hw->phy.type = ixgbe_phy_qsfp_intel;
1740 hw->phy.type = ixgbe_phy_qsfp_unknown;
1742 ixgbe_get_device_caps(hw, &enforce_sfp);
1743 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1744 /* Make sure we're a supported PHY type */
1745 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1746 status = IXGBE_SUCCESS;
1748 if (hw->allow_unsupported_sfp == true) {
1749 EWARN(hw, "WARNING: Intel (R) Network "
1750 "Connections are quality tested "
1751 "using Intel (R) Ethernet Optics."
1752 " Using untested modules is not "
1753 "supported and may cause unstable"
1754 " operation or damage to the "
1755 "module or the adapter. Intel "
1756 "Corporation is not responsible "
1757 "for any harm caused by using "
1758 "untested modules.\n", status);
1759 status = IXGBE_SUCCESS;
1761 DEBUGOUT("QSFP module not supported\n");
1763 ixgbe_phy_sfp_unsupported;
1764 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1768 status = IXGBE_SUCCESS;
1775 err_read_i2c_eeprom:
1776 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1778 hw->phy.type = ixgbe_phy_unknown;
1780 return IXGBE_ERR_SFP_NOT_PRESENT;
1785 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1786 * @hw: pointer to hardware structure
1787 * @list_offset: offset to the SFP ID list
1788 * @data_offset: offset to the SFP data block
1790 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1791 * so it returns the offsets to the phy init sequence block.
1793 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1798 u16 sfp_type = hw->phy.sfp_type;
1800 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1802 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1803 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1805 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1806 return IXGBE_ERR_SFP_NOT_PRESENT;
1808 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1809 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1810 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1813 * Limiting active cables and 1G Phys must be initialized as
1816 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1817 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1818 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1819 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1820 sfp_type = ixgbe_sfp_type_srlr_core0;
1821 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1822 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1823 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1824 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1825 sfp_type = ixgbe_sfp_type_srlr_core1;
1827 /* Read offset to PHY init contents */
1828 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1829 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1830 "eeprom read at offset %d failed",
1831 IXGBE_PHY_INIT_OFFSET_NL);
1832 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1835 if ((!*list_offset) || (*list_offset == 0xFFFF))
1836 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1838 /* Shift offset to first ID word */
1842 * Find the matching SFP ID in the EEPROM
1843 * and program the init sequence
1845 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1848 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1849 if (sfp_id == sfp_type) {
1851 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1853 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1854 DEBUGOUT("SFP+ module not supported\n");
1855 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1860 (*list_offset) += 2;
1861 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1866 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1867 DEBUGOUT("No matching SFP+ module found\n");
1868 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1871 return IXGBE_SUCCESS;
1874 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1875 "eeprom read at offset %d failed", *list_offset);
1876 return IXGBE_ERR_PHY;
1880 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1881 * @hw: pointer to hardware structure
1882 * @byte_offset: EEPROM byte offset to read
1883 * @eeprom_data: value read
1885 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1887 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1890 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1892 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1893 IXGBE_I2C_EEPROM_DEV_ADDR,
1898 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1899 * @hw: pointer to hardware structure
1900 * @byte_offset: byte offset at address 0xA2
1901 * @eeprom_data: value read
1903 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1905 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1908 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1909 IXGBE_I2C_EEPROM_DEV_ADDR2,
1914 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1915 * @hw: pointer to hardware structure
1916 * @byte_offset: EEPROM byte offset to write
1917 * @eeprom_data: value to write
1919 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1921 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1924 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1926 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1927 IXGBE_I2C_EEPROM_DEV_ADDR,
1932 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1933 * @hw: pointer to hardware structure
1934 * @offset: eeprom offset to be read
1935 * @addr: I2C address to be read
1937 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1939 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1940 offset == IXGBE_SFF_IDENTIFIER &&
1941 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1947 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1948 * @hw: pointer to hardware structure
1949 * @byte_offset: byte offset to read
1952 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1953 * a specified device address.
1955 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1956 u8 dev_addr, u8 *data)
1961 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1965 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1967 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
1968 max_retry = IXGBE_SFP_DETECT_RETRIES;
1971 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1972 return IXGBE_ERR_SWFW_SYNC;
1974 ixgbe_i2c_start(hw);
1976 /* Device Address and write indication */
1977 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1978 if (status != IXGBE_SUCCESS)
1981 status = ixgbe_get_i2c_ack(hw);
1982 if (status != IXGBE_SUCCESS)
1985 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1986 if (status != IXGBE_SUCCESS)
1989 status = ixgbe_get_i2c_ack(hw);
1990 if (status != IXGBE_SUCCESS)
1993 ixgbe_i2c_start(hw);
1995 /* Device Address and read indication */
1996 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1997 if (status != IXGBE_SUCCESS)
2000 status = ixgbe_get_i2c_ack(hw);
2001 if (status != IXGBE_SUCCESS)
2004 status = ixgbe_clock_in_i2c_byte(hw, data);
2005 if (status != IXGBE_SUCCESS)
2008 status = ixgbe_clock_out_i2c_bit(hw, nack);
2009 if (status != IXGBE_SUCCESS)
2013 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2014 return IXGBE_SUCCESS;
2017 ixgbe_i2c_bus_clear(hw);
2018 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2021 if (retry < max_retry)
2022 DEBUGOUT("I2C byte read error - Retrying.\n");
2024 DEBUGOUT("I2C byte read error.\n");
2026 } while (retry < max_retry);
2032 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2033 * @hw: pointer to hardware structure
2034 * @byte_offset: byte offset to write
2035 * @data: value to write
2037 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2038 * a specified device address.
2040 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2041 u8 dev_addr, u8 data)
2043 s32 status = IXGBE_SUCCESS;
2046 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2048 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2050 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
2051 status = IXGBE_ERR_SWFW_SYNC;
2052 goto write_byte_out;
2056 ixgbe_i2c_start(hw);
2058 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2059 if (status != IXGBE_SUCCESS)
2062 status = ixgbe_get_i2c_ack(hw);
2063 if (status != IXGBE_SUCCESS)
2066 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2067 if (status != IXGBE_SUCCESS)
2070 status = ixgbe_get_i2c_ack(hw);
2071 if (status != IXGBE_SUCCESS)
2074 status = ixgbe_clock_out_i2c_byte(hw, data);
2075 if (status != IXGBE_SUCCESS)
2078 status = ixgbe_get_i2c_ack(hw);
2079 if (status != IXGBE_SUCCESS)
2083 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2084 return IXGBE_SUCCESS;
2087 ixgbe_i2c_bus_clear(hw);
2089 if (retry < max_retry)
2090 DEBUGOUT("I2C byte write error - Retrying.\n");
2092 DEBUGOUT("I2C byte write error.\n");
2093 } while (retry < max_retry);
2095 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2102 * ixgbe_i2c_start - Sets I2C start condition
2103 * @hw: pointer to hardware structure
2105 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2106 * Set bit-bang mode on X550 hardware.
2108 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2110 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2112 DEBUGFUNC("ixgbe_i2c_start");
2114 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2116 /* Start condition must begin with data and clock high */
2117 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2118 ixgbe_raise_i2c_clk(hw, &i2cctl);
2120 /* Setup time for start condition (4.7us) */
2121 usec_delay(IXGBE_I2C_T_SU_STA);
2123 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2125 /* Hold time for start condition (4us) */
2126 usec_delay(IXGBE_I2C_T_HD_STA);
2128 ixgbe_lower_i2c_clk(hw, &i2cctl);
2130 /* Minimum low period of clock is 4.7 us */
2131 usec_delay(IXGBE_I2C_T_LOW);
2136 * ixgbe_i2c_stop - Sets I2C stop condition
2137 * @hw: pointer to hardware structure
2139 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2140 * Disables bit-bang mode and negates data output enable on X550
2143 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2145 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2146 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2147 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2148 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2150 DEBUGFUNC("ixgbe_i2c_stop");
2152 /* Stop condition must begin with data low and clock high */
2153 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2154 ixgbe_raise_i2c_clk(hw, &i2cctl);
2156 /* Setup time for stop condition (4us) */
2157 usec_delay(IXGBE_I2C_T_SU_STO);
2159 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2161 /* bus free time between stop and start (4.7us)*/
2162 usec_delay(IXGBE_I2C_T_BUF);
2164 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2165 i2cctl &= ~bb_en_bit;
2166 i2cctl |= data_oe_bit | clk_oe_bit;
2167 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2168 IXGBE_WRITE_FLUSH(hw);
2173 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2174 * @hw: pointer to hardware structure
2175 * @data: data byte to clock in
2177 * Clocks in one byte data via I2C data/clock
2179 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2184 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2187 for (i = 7; i >= 0; i--) {
2188 ixgbe_clock_in_i2c_bit(hw, &bit);
2192 return IXGBE_SUCCESS;
2196 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2197 * @hw: pointer to hardware structure
2198 * @data: data byte clocked out
2200 * Clocks out one byte data via I2C data/clock
2202 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2204 s32 status = IXGBE_SUCCESS;
2209 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2211 for (i = 7; i >= 0; i--) {
2212 bit = (data >> i) & 0x1;
2213 status = ixgbe_clock_out_i2c_bit(hw, bit);
2215 if (status != IXGBE_SUCCESS)
2219 /* Release SDA line (set high) */
2220 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2221 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2222 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2223 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2224 IXGBE_WRITE_FLUSH(hw);
2230 * ixgbe_get_i2c_ack - Polls for I2C ACK
2231 * @hw: pointer to hardware structure
2233 * Clocks in/out one bit via I2C data/clock
2235 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2237 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2238 s32 status = IXGBE_SUCCESS;
2240 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2244 DEBUGFUNC("ixgbe_get_i2c_ack");
2247 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2248 i2cctl |= data_oe_bit;
2249 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2250 IXGBE_WRITE_FLUSH(hw);
2252 ixgbe_raise_i2c_clk(hw, &i2cctl);
2254 /* Minimum high period of clock is 4us */
2255 usec_delay(IXGBE_I2C_T_HIGH);
2257 /* Poll for ACK. Note that ACK in I2C spec is
2258 * transition from 1 to 0 */
2259 for (i = 0; i < timeout; i++) {
2260 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2261 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2269 DEBUGOUT("I2C ack was not received.\n");
2270 status = IXGBE_ERR_I2C;
2273 ixgbe_lower_i2c_clk(hw, &i2cctl);
2275 /* Minimum low period of clock is 4.7 us */
2276 usec_delay(IXGBE_I2C_T_LOW);
2282 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2283 * @hw: pointer to hardware structure
2284 * @data: read data value
2286 * Clocks in one bit via I2C data/clock
2288 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2290 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2291 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2293 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2296 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2297 i2cctl |= data_oe_bit;
2298 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2299 IXGBE_WRITE_FLUSH(hw);
2301 ixgbe_raise_i2c_clk(hw, &i2cctl);
2303 /* Minimum high period of clock is 4us */
2304 usec_delay(IXGBE_I2C_T_HIGH);
2306 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2307 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2309 ixgbe_lower_i2c_clk(hw, &i2cctl);
2311 /* Minimum low period of clock is 4.7 us */
2312 usec_delay(IXGBE_I2C_T_LOW);
2314 return IXGBE_SUCCESS;
2318 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2319 * @hw: pointer to hardware structure
2320 * @data: data value to write
2322 * Clocks out one bit via I2C data/clock
2324 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2327 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2329 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2331 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2332 if (status == IXGBE_SUCCESS) {
2333 ixgbe_raise_i2c_clk(hw, &i2cctl);
2335 /* Minimum high period of clock is 4us */
2336 usec_delay(IXGBE_I2C_T_HIGH);
2338 ixgbe_lower_i2c_clk(hw, &i2cctl);
2340 /* Minimum low period of clock is 4.7 us.
2341 * This also takes care of the data hold time.
2343 usec_delay(IXGBE_I2C_T_LOW);
2345 status = IXGBE_ERR_I2C;
2346 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2347 "I2C data was not set to %X\n", data);
2354 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2355 * @hw: pointer to hardware structure
2356 * @i2cctl: Current value of I2CCTL register
2358 * Raises the I2C clock line '0'->'1'
2359 * Negates the I2C clock output enable on X550 hardware.
2361 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2363 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2365 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2368 DEBUGFUNC("ixgbe_raise_i2c_clk");
2371 *i2cctl |= clk_oe_bit;
2372 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2375 for (i = 0; i < timeout; i++) {
2376 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2378 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2379 IXGBE_WRITE_FLUSH(hw);
2380 /* SCL rise time (1000ns) */
2381 usec_delay(IXGBE_I2C_T_RISE);
2383 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2384 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2390 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2391 * @hw: pointer to hardware structure
2392 * @i2cctl: Current value of I2CCTL register
2394 * Lowers the I2C clock line '1'->'0'
2395 * Asserts the I2C clock output enable on X550 hardware.
2397 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2399 DEBUGFUNC("ixgbe_lower_i2c_clk");
2401 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2402 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2404 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2405 IXGBE_WRITE_FLUSH(hw);
2407 /* SCL fall time (300ns) */
2408 usec_delay(IXGBE_I2C_T_FALL);
2412 * ixgbe_set_i2c_data - Sets the I2C data bit
2413 * @hw: pointer to hardware structure
2414 * @i2cctl: Current value of I2CCTL register
2415 * @data: I2C data value (0 or 1) to set
2417 * Sets the I2C data bit
2418 * Asserts the I2C data output enable on X550 hardware.
2420 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2422 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2423 s32 status = IXGBE_SUCCESS;
2425 DEBUGFUNC("ixgbe_set_i2c_data");
2428 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2430 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2431 *i2cctl &= ~data_oe_bit;
2433 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2434 IXGBE_WRITE_FLUSH(hw);
2436 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2437 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2439 if (!data) /* Can't verify data in this case */
2440 return IXGBE_SUCCESS;
2442 *i2cctl |= data_oe_bit;
2443 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2444 IXGBE_WRITE_FLUSH(hw);
2447 /* Verify data was set correctly */
2448 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2449 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2450 status = IXGBE_ERR_I2C;
2451 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2452 "Error - I2C data was not set to %X.\n",
2460 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2461 * @hw: pointer to hardware structure
2462 * @i2cctl: Current value of I2CCTL register
2464 * Returns the I2C data bit value
2465 * Negates the I2C data output enable on X550 hardware.
2467 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2469 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2472 DEBUGFUNC("ixgbe_get_i2c_data");
2475 *i2cctl |= data_oe_bit;
2476 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2477 IXGBE_WRITE_FLUSH(hw);
2478 usec_delay(IXGBE_I2C_T_FALL);
2481 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2490 * ixgbe_i2c_bus_clear - Clears the I2C bus
2491 * @hw: pointer to hardware structure
2493 * Clears the I2C bus by sending nine clock pulses.
2494 * Used when data line is stuck low.
2496 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2501 DEBUGFUNC("ixgbe_i2c_bus_clear");
2503 ixgbe_i2c_start(hw);
2504 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2506 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2508 for (i = 0; i < 9; i++) {
2509 ixgbe_raise_i2c_clk(hw, &i2cctl);
2511 /* Min high period of clock is 4us */
2512 usec_delay(IXGBE_I2C_T_HIGH);
2514 ixgbe_lower_i2c_clk(hw, &i2cctl);
2516 /* Min low period of clock is 4.7us*/
2517 usec_delay(IXGBE_I2C_T_LOW);
2520 ixgbe_i2c_start(hw);
2522 /* Put the i2c bus back to default state */
2527 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2528 * @hw: pointer to hardware structure
2530 * Checks if the LASI temp alarm status was triggered due to overtemp
2532 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2534 s32 status = IXGBE_SUCCESS;
2537 DEBUGFUNC("ixgbe_tn_check_overtemp");
2539 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2542 /* Check that the LASI temp alarm status was triggered */
2543 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2544 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2546 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2549 status = IXGBE_ERR_OVERTEMP;
2550 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2556 * ixgbe_set_copper_phy_power - Control power for copper phy
2557 * @hw: pointer to hardware structure
2558 * @on: true for on, false for off
2560 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2565 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2566 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2572 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2574 if (ixgbe_check_reset_blocked(hw))
2576 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2579 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2580 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,