drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 #include "rte_pmd_ixgbe.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 enum ixgbevf_xcast_modes {
 158         IXGBEVF_XCAST_MODE_NONE = 0,
 159         IXGBEVF_XCAST_MODE_MULTI,
 160         IXGBEVF_XCAST_MODE_ALLMULTI,
 161 };
 162
 163 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 164 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 165
 166 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 167 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 168 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 179                                 int wait_to_complete);
 180 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_stats *stats);
 182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_xstat *xstats, unsigned n);
 184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 185                                   struct rte_eth_xstat *xstats, unsigned n);
 186 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 187 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 188 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 189         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 190 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 192 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 193                                              uint16_t queue_id,
 194                                              uint8_t stat_idx,
 195                                              uint8_t is_rx);
 196 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 197                                struct rte_eth_dev_info *dev_info);
 198 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 199 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 200                                  struct rte_eth_dev_info *dev_info);
 201 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 202
 203 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 204                 uint16_t vlan_id, int on);
 205 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 206                                enum rte_vlan_type vlan_type,
 207                                uint16_t tpid_id);
 208 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 209                 uint16_t queue, bool on);
 210 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 211                 int on);
 212 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 213 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 214 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 215 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 216 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 217
 218 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 220 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 221                                struct rte_eth_fc_conf *fc_conf);
 222 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 223                                struct rte_eth_fc_conf *fc_conf);
 224 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 225                 struct rte_eth_pfc_conf *pfc_conf);
 226 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 227                         struct rte_eth_rss_reta_entry64 *reta_conf,
 228                         uint16_t reta_size);
 229 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 230                         struct rte_eth_rss_reta_entry64 *reta_conf,
 231                         uint16_t reta_size);
 232 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 233 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 234 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 235 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 237                                       struct rte_intr_handle *handle);
 238 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 239                 void *param);
 240 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 241 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 242                 uint32_t index, uint32_t pool);
 243 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 244 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 245                                            struct ether_addr *mac_addr);
 246 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 247
 248 /* For Virtual Function support */
 249 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 250 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 251 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 252 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 253 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 256 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 257 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 258                 struct rte_eth_stats *stats);
 259 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 260 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 261                 uint16_t vlan_id, int on);
 262 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 263                 uint16_t queue, int on);
 264 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id);
 268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 269                                              uint16_t queue_id);
 270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 271                                  uint8_t queue, uint8_t msix_vector);
 272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 273 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 274 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 275
 276 /* For Eth VMDQ APIs support */
 277 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 278                 ether_addr * mac_addr, uint8_t on);
 279 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 280 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 281                 uint16_t rx_mask, uint8_t on);
 282 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 283 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 284 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 285                 uint64_t pool_mask, uint8_t vlan_on);
 286 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 287                 struct rte_eth_mirror_conf *mirror_conf,
 288                 uint8_t rule_id, uint8_t on);
 289 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 290                 uint8_t rule_id);
 291 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 292                                           uint16_t queue_id);
 293 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 294                                            uint16_t queue_id);
 295 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 296                                uint8_t queue, uint8_t msix_vector);
 297 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 298
 299 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 300                 uint16_t queue_idx, uint16_t tx_rate);
 301 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 302                 uint16_t tx_rate, uint64_t q_msk);
 303
 304 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 305                                  struct ether_addr *mac_addr,
 306                                  uint32_t index, uint32_t pool);
 307 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 308 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 309                                              struct ether_addr *mac_addr);
 310 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 311                         struct rte_eth_syn_filter *filter,
 312                         bool add);
 313 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 314                         struct rte_eth_syn_filter *filter);
 315 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 316                         enum rte_filter_op filter_op,
 317                         void *arg);
 318 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 319                         struct ixgbe_5tuple_filter *filter);
 320 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 321                         struct ixgbe_5tuple_filter *filter);
 322 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 323                         struct rte_eth_ntuple_filter *filter,
 324                         bool add);
 325 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 326                                 enum rte_filter_op filter_op,
 327                                 void *arg);
 328 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 329                         struct rte_eth_ntuple_filter *filter);
 330 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 331                         struct rte_eth_ethertype_filter *filter,
 332                         bool add);
 333 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 334                                 enum rte_filter_op filter_op,
 335                                 void *arg);
 336 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 337                         struct rte_eth_ethertype_filter *filter);
 338 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 339                      enum rte_filter_type filter_type,
 340                      enum rte_filter_op filter_op,
 341                      void *arg);
 342 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 343
 344 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 345                                       struct ether_addr *mc_addr_set,
 346                                       uint32_t nb_mc_addr);
 347 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 348                                    struct rte_eth_dcb_info *dcb_info);
 349
 350 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 351 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 352                             struct rte_dev_reg_info *regs);
 353 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 354 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 355                                 struct rte_dev_eeprom_info *eeprom);
 356 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 357                                 struct rte_dev_eeprom_info *eeprom);
 358
 359 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 360 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 361                                 struct rte_dev_reg_info *regs);
 362
 363 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 364 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 365 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 366                                             struct timespec *timestamp,
 367                                             uint32_t flags);
 368 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 369                                             struct timespec *timestamp);
 370 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 371 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 372                                    struct timespec *timestamp);
 373 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 374                                    const struct timespec *timestamp);
 375 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 376                                           void *param);
 377
 378 static int ixgbe_dev_l2_tunnel_eth_type_conf
 379         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 380 static int ixgbe_dev_l2_tunnel_offload_set
 381         (struct rte_eth_dev *dev,
 382          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 383          uint32_t mask,
 384          uint8_t en);
 385 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 386                                              enum rte_filter_op filter_op,
 387                                              void *arg);
 388
 389 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 390                                          struct rte_eth_udp_tunnel *udp_tunnel);
 391 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 392                                          struct rte_eth_udp_tunnel *udp_tunnel);
 393
 394 /*
 395  * Define VF Stats MACRO for Non "cleared on read" register
 396  */
 397 #define UPDATE_VF_STAT(reg, last, cur)                          \
 398 {                                                               \
 399         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 400         cur += (latest - last) & UINT_MAX;                      \
 401         last = latest;                                          \
 402 }
 403
 404 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 405 {                                                                \
 406         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 407         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 408         u64 latest = ((new_msb << 32) | new_lsb);                \
 409         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 410         last = latest;                                           \
 411 }
 412
 413 #define IXGBE_SET_HWSTRIP(h, q) do {\
 414                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 415                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 416                 (h)->bitmap[idx] |= 1 << bit;\
 417         } while (0)
 418
 419 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 420                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 421                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 422                 (h)->bitmap[idx] &= ~(1 << bit);\
 423         } while (0)
 424
 425 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 426                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 427                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 428                 (r) = (h)->bitmap[idx] >> bit & 1;\
 429         } while (0)
 430
 431 /*
 432  * The set of PCI devices this driver supports
 433  */
 434 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 488 #ifdef RTE_NIC_BYPASS
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 490 #endif
 491         { .vendor_id = 0, /* sentinel */ },
 492 };
 493
 494 /*
 495  * The set of PCI devices this driver supports (for 82599 VF)
 496  */
 497 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 505         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 506         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 507         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 508         { .vendor_id = 0, /* sentinel */ },
 509 };
 510
 511 static const struct rte_eth_desc_lim rx_desc_lim = {
 512         .nb_max = IXGBE_MAX_RING_DESC,
 513         .nb_min = IXGBE_MIN_RING_DESC,
 514         .nb_align = IXGBE_RXD_ALIGN,
 515 };
 516
 517 static const struct rte_eth_desc_lim tx_desc_lim = {
 518         .nb_max = IXGBE_MAX_RING_DESC,
 519         .nb_min = IXGBE_MIN_RING_DESC,
 520         .nb_align = IXGBE_TXD_ALIGN,
 521         .nb_seg_max = IXGBE_TX_MAX_SEG,
 522         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 523 };
 524
 525 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 526         .dev_configure        = ixgbe_dev_configure,
 527         .dev_start            = ixgbe_dev_start,
 528         .dev_stop             = ixgbe_dev_stop,
 529         .dev_set_link_up    = ixgbe_dev_set_link_up,
 530         .dev_set_link_down  = ixgbe_dev_set_link_down,
 531         .dev_close            = ixgbe_dev_close,
 532         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 533         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 534         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 535         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 536         .link_update          = ixgbe_dev_link_update,
 537         .stats_get            = ixgbe_dev_stats_get,
 538         .xstats_get           = ixgbe_dev_xstats_get,
 539         .stats_reset          = ixgbe_dev_stats_reset,
 540         .xstats_reset         = ixgbe_dev_xstats_reset,
 541         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 542         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 543         .dev_infos_get        = ixgbe_dev_info_get,
 544         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 545         .mtu_set              = ixgbe_dev_mtu_set,
 546         .vlan_filter_set      = ixgbe_vlan_filter_set,
 547         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 548         .vlan_offload_set     = ixgbe_vlan_offload_set,
 549         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 550         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 551         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 552         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 553         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 554         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 555         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 556         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 557         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 558         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 559         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 560         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 561         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 562         .dev_led_on           = ixgbe_dev_led_on,
 563         .dev_led_off          = ixgbe_dev_led_off,
 564         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 565         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 566         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 567         .mac_addr_add         = ixgbe_add_rar,
 568         .mac_addr_remove      = ixgbe_remove_rar,
 569         .mac_addr_set         = ixgbe_set_default_mac_addr,
 570         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 571         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 572         .mirror_rule_set      = ixgbe_mirror_rule_set,
 573         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 574         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 575         .set_vf_rx            = ixgbe_set_pool_rx,
 576         .set_vf_tx            = ixgbe_set_pool_tx,
 577         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 578         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 579         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 580         .reta_update          = ixgbe_dev_rss_reta_update,
 581         .reta_query           = ixgbe_dev_rss_reta_query,
 582 #ifdef RTE_NIC_BYPASS
 583         .bypass_init          = ixgbe_bypass_init,
 584         .bypass_state_set     = ixgbe_bypass_state_store,
 585         .bypass_state_show    = ixgbe_bypass_state_show,
 586         .bypass_event_set     = ixgbe_bypass_event_store,
 587         .bypass_event_show    = ixgbe_bypass_event_show,
 588         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 589         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 590         .bypass_ver_show      = ixgbe_bypass_ver_show,
 591         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 592 #endif /* RTE_NIC_BYPASS */
 593         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 594         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 595         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 596         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 597         .rxq_info_get         = ixgbe_rxq_info_get,
 598         .txq_info_get         = ixgbe_txq_info_get,
 599         .timesync_enable      = ixgbe_timesync_enable,
 600         .timesync_disable     = ixgbe_timesync_disable,
 601         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 602         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 603         .get_reg              = ixgbe_get_regs,
 604         .get_eeprom_length    = ixgbe_get_eeprom_length,
 605         .get_eeprom           = ixgbe_get_eeprom,
 606         .set_eeprom           = ixgbe_set_eeprom,
 607         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 608         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 609         .timesync_read_time   = ixgbe_timesync_read_time,
 610         .timesync_write_time  = ixgbe_timesync_write_time,
 611         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 612         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 613         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 614         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 615 };
 616
 617 /*
 618  * dev_ops for virtual function, bare necessities for basic vf
 619  * operation have been implemented
 620  */
 621 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 622         .dev_configure        = ixgbevf_dev_configure,
 623         .dev_start            = ixgbevf_dev_start,
 624         .dev_stop             = ixgbevf_dev_stop,
 625         .link_update          = ixgbe_dev_link_update,
 626         .stats_get            = ixgbevf_dev_stats_get,
 627         .xstats_get           = ixgbevf_dev_xstats_get,
 628         .stats_reset          = ixgbevf_dev_stats_reset,
 629         .xstats_reset         = ixgbevf_dev_stats_reset,
 630         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 631         .dev_close            = ixgbevf_dev_close,
 632         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 633         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 634         .dev_infos_get        = ixgbevf_dev_info_get,
 635         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 636         .mtu_set              = ixgbevf_dev_set_mtu,
 637         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 638         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 639         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 640         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 641         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 642         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 643         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 644         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 645         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 646         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 647         .mac_addr_add         = ixgbevf_add_mac_addr,
 648         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 649         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 650         .rxq_info_get         = ixgbe_rxq_info_get,
 651         .txq_info_get         = ixgbe_txq_info_get,
 652         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 653         .get_reg              = ixgbevf_get_regs,
 654         .reta_update          = ixgbe_dev_rss_reta_update,
 655         .reta_query           = ixgbe_dev_rss_reta_query,
 656         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 657         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 658 };
 659
 660 /* store statistics names and its offset in stats structure */
 661 struct rte_ixgbe_xstats_name_off {
 662         char name[RTE_ETH_XSTATS_NAME_SIZE];
 663         unsigned offset;
 664 };
 665
 666 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 667         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 668         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 669         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 670         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 671         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 672         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 673         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 674         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 675         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 676         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 677         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 678         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 679         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 680         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 681         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 682                 prc1023)},
 683         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 684                 prc1522)},
 685         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 686         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 687         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 688         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 689         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 690         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 691         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 692         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 693         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 694         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 695         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 696         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 697         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 698         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 699         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 700         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 701         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 702                 ptc1023)},
 703         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 704                 ptc1522)},
 705         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 706         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 707         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 708         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 709
 710         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 711                 fdirustat_add)},
 712         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 713                 fdirustat_remove)},
 714         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 715                 fdirfstat_fadd)},
 716         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 717                 fdirfstat_fremove)},
 718         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 719                 fdirmatch)},
 720         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 721                 fdirmiss)},
 722
 723         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 724         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 725         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 726                 fclast)},
 727         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 728         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 729         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 730         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 731         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 732                 fcoe_noddp)},
 733         {"rx_fcoe_no_direct_data_placement_ext_buff",
 734                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 735
 736         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 737                 lxontxc)},
 738         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 739                 lxonrxc)},
 740         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 741                 lxofftxc)},
 742         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 743                 lxoffrxc)},
 744         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 745 };
 746
 747 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 748                            sizeof(rte_ixgbe_stats_strings[0]))
 749
 750 /* Per-queue statistics */
 751 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 752         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 753         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 754         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 755         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 756 };
 757
 758 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 759                            sizeof(rte_ixgbe_rxq_strings[0]))
 760 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 761
 762 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 763         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 764         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 765         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 766                 pxon2offc)},
 767 };
 768
 769 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 770                            sizeof(rte_ixgbe_txq_strings[0]))
 771 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 772
 773 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 774         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 775 };
 776
 777 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 778                 sizeof(rte_ixgbevf_stats_strings[0]))
 779
 780 /**
 781  * Atomically reads the link status information from global
 782  * structure rte_eth_dev.
 783  *
 784  * @param dev
 785  *   - Pointer to the structure rte_eth_dev to read from.
 786  *   - Pointer to the buffer to be saved with the link status.
 787  *
 788  * @return
 789  *   - On success, zero.
 790  *   - On failure, negative value.
 791  */
 792 static inline int
 793 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 794                                 struct rte_eth_link *link)
 795 {
 796         struct rte_eth_link *dst = link;
 797         struct rte_eth_link *src = &(dev->data->dev_link);
 798
 799         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 800                                         *(uint64_t *)src) == 0)
 801                 return -1;
 802
 803         return 0;
 804 }
 805
 806 /**
 807  * Atomically writes the link status information into global
 808  * structure rte_eth_dev.
 809  *
 810  * @param dev
 811  *   - Pointer to the structure rte_eth_dev to read from.
 812  *   - Pointer to the buffer to be saved with the link status.
 813  *
 814  * @return
 815  *   - On success, zero.
 816  *   - On failure, negative value.
 817  */
 818 static inline int
 819 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 820                                 struct rte_eth_link *link)
 821 {
 822         struct rte_eth_link *dst = &(dev->data->dev_link);
 823         struct rte_eth_link *src = link;
 824
 825         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 826                                         *(uint64_t *)src) == 0)
 827                 return -1;
 828
 829         return 0;
 830 }
 831
 832 /*
 833  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 834  */
 835 static inline int
 836 ixgbe_is_sfp(struct ixgbe_hw *hw)
 837 {
 838         switch (hw->phy.type) {
 839         case ixgbe_phy_sfp_avago:
 840         case ixgbe_phy_sfp_ftl:
 841         case ixgbe_phy_sfp_intel:
 842         case ixgbe_phy_sfp_unknown:
 843         case ixgbe_phy_sfp_passive_tyco:
 844         case ixgbe_phy_sfp_passive_unknown:
 845                 return 1;
 846         default:
 847                 return 0;
 848         }
 849 }
 850
 851 static inline int32_t
 852 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 853 {
 854         uint32_t ctrl_ext;
 855         int32_t status;
 856
 857         status = ixgbe_reset_hw(hw);
 858
 859         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 860         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 861         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 862         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 863         IXGBE_WRITE_FLUSH(hw);
 864
 865         return status;
 866 }
 867
 868 static inline void
 869 ixgbe_enable_intr(struct rte_eth_dev *dev)
 870 {
 871         struct ixgbe_interrupt *intr =
 872                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 873         struct ixgbe_hw *hw =
 874                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 875
 876         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 877         IXGBE_WRITE_FLUSH(hw);
 878 }
 879
 880 /*
 881  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 882  */
 883 static void
 884 ixgbe_disable_intr(struct ixgbe_hw *hw)
 885 {
 886         PMD_INIT_FUNC_TRACE();
 887
 888         if (hw->mac.type == ixgbe_mac_82598EB) {
 889                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 890         } else {
 891                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 892                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 893                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 894         }
 895         IXGBE_WRITE_FLUSH(hw);
 896 }
 897
 898 /*
 899  * This function resets queue statistics mapping registers.
 900  * From Niantic datasheet, Initialization of Statistics section:
 901  * "...if software requires the queue counters, the RQSMR and TQSM registers
 902  * must be re-programmed following a device reset.
 903  */
 904 static void
 905 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 906 {
 907         uint32_t i;
 908
 909         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 910                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 911                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 912         }
 913 }
 914
 915
 916 static int
 917 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 918                                   uint16_t queue_id,
 919                                   uint8_t stat_idx,
 920                                   uint8_t is_rx)
 921 {
 922 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 923 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 924 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 925
 926         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 927         struct ixgbe_stat_mapping_registers *stat_mappings =
 928                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 929         uint32_t qsmr_mask = 0;
 930         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 931         uint32_t q_map;
 932         uint8_t n, offset;
 933
 934         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 935                 (hw->mac.type != ixgbe_mac_X540) &&
 936                 (hw->mac.type != ixgbe_mac_X550) &&
 937                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 938                 (hw->mac.type != ixgbe_mac_X550EM_a))
 939                 return -ENOSYS;
 940
 941         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 942                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 943                      queue_id, stat_idx);
 944
 945         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 946         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 947                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 948                 return -EIO;
 949         }
 950         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 951
 952         /* Now clear any previous stat_idx set */
 953         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 954         if (!is_rx)
 955                 stat_mappings->tqsm[n] &= ~clearing_mask;
 956         else
 957                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 958
 959         q_map = (uint32_t)stat_idx;
 960         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 961         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 962         if (!is_rx)
 963                 stat_mappings->tqsm[n] |= qsmr_mask;
 964         else
 965                 stat_mappings->rqsmr[n] |= qsmr_mask;
 966
 967         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 968                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 969                      queue_id, stat_idx);
 970         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 971                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 972
 973         /* Now write the mapping in the appropriate register */
 974         if (is_rx) {
 975                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 976                              stat_mappings->rqsmr[n], n);
 977                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 978         } else {
 979                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 980                              stat_mappings->tqsm[n], n);
 981                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 982         }
 983         return 0;
 984 }
 985
 986 static void
 987 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 988 {
 989         struct ixgbe_stat_mapping_registers *stat_mappings =
 990                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 991         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 992         int i;
 993
 994         /* write whatever was in stat mapping table to the NIC */
 995         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 996                 /* rx */
 997                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 998
 999                 /* tx */
1000                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1001         }
1002 }
1003
1004 static void
1005 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1006 {
1007         uint8_t i;
1008         struct ixgbe_dcb_tc_config *tc;
1009         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1010
1011         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1012         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1013         for (i = 0; i < dcb_max_tc; i++) {
1014                 tc = &dcb_config->tc_config[i];
1015                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1016                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1017                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1018                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1019                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1020                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1021                 tc->pfc = ixgbe_dcb_pfc_disabled;
1022         }
1023
1024         /* Initialize default user to priority mapping, UPx->TC0 */
1025         tc = &dcb_config->tc_config[0];
1026         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1027         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1028         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1029                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1030                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1031         }
1032         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1033         dcb_config->pfc_mode_enable = false;
1034         dcb_config->vt_mode = true;
1035         dcb_config->round_robin_enable = false;
1036         /* support all DCB capabilities in 82599 */
1037         dcb_config->support.capabilities = 0xFF;
1038
1039         /*we only support 4 Tcs for X540, X550 */
1040         if (hw->mac.type == ixgbe_mac_X540 ||
1041                 hw->mac.type == ixgbe_mac_X550 ||
1042                 hw->mac.type == ixgbe_mac_X550EM_x ||
1043                 hw->mac.type == ixgbe_mac_X550EM_a) {
1044                 dcb_config->num_tcs.pg_tcs = 4;
1045                 dcb_config->num_tcs.pfc_tcs = 4;
1046         }
1047 }
1048
1049 /*
1050  * Ensure that all locks are released before first NVM or PHY access
1051  */
1052 static void
1053 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1054 {
1055         uint16_t mask;
1056
1057         /*
1058          * Phy lock should not fail in this early stage. If this is the case,
1059          * it is due to an improper exit of the application.
1060          * So force the release of the faulty lock. Release of common lock
1061          * is done automatically by swfw_sync function.
1062          */
1063         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1064         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1065                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1066         }
1067         ixgbe_release_swfw_semaphore(hw, mask);
1068
1069         /*
1070          * These ones are more tricky since they are common to all ports; but
1071          * swfw_sync retries last long enough (1s) to be almost sure that if
1072          * lock can not be taken it is due to an improper lock of the
1073          * semaphore.
1074          */
1075         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1076         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1077                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1078         }
1079         ixgbe_release_swfw_semaphore(hw, mask);
1080 }
1081
1082 /*
1083  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1084  * It returns 0 on success.
1085  */
1086 static int
1087 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1088 {
1089         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1090         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1091         struct ixgbe_hw *hw =
1092                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1093         struct ixgbe_vfta *shadow_vfta =
1094                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1095         struct ixgbe_hwstrip *hwstrip =
1096                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1097         struct ixgbe_dcb_config *dcb_config =
1098                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1099         struct ixgbe_filter_info *filter_info =
1100                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1101         uint32_t ctrl_ext;
1102         uint16_t csum;
1103         int diag, i;
1104
1105         PMD_INIT_FUNC_TRACE();
1106
1107         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1108         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1109         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1110         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1111
1112         /*
1113          * For secondary processes, we don't initialise any further as primary
1114          * has already done this work. Only check we don't need a different
1115          * RX and TX function.
1116          */
1117         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1118                 struct ixgbe_tx_queue *txq;
1119                 /* TX queue function in primary, set by last queue initialized
1120                  * Tx queue may not initialized by primary process
1121                  */
1122                 if (eth_dev->data->tx_queues) {
1123                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1124                         ixgbe_set_tx_function(eth_dev, txq);
1125                 } else {
1126                         /* Use default TX function if we get here */
1127                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1128                                      "Using default TX function.");
1129                 }
1130
1131                 ixgbe_set_rx_function(eth_dev);
1132
1133                 return 0;
1134         }
1135
1136         rte_eth_copy_pci_info(eth_dev, pci_dev);
1137
1138         /* Vendor and Device ID need to be set before init of shared code */
1139         hw->device_id = pci_dev->id.device_id;
1140         hw->vendor_id = pci_dev->id.vendor_id;
1141         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1142         hw->allow_unsupported_sfp = 1;
1143
1144         /* Initialize the shared code (base driver) */
1145 #ifdef RTE_NIC_BYPASS
1146         diag = ixgbe_bypass_init_shared_code(hw);
1147 #else
1148         diag = ixgbe_init_shared_code(hw);
1149 #endif /* RTE_NIC_BYPASS */
1150
1151         if (diag != IXGBE_SUCCESS) {
1152                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1153                 return -EIO;
1154         }
1155
1156         /* pick up the PCI bus settings for reporting later */
1157         ixgbe_get_bus_info(hw);
1158
1159         /* Unlock any pending hardware semaphore */
1160         ixgbe_swfw_lock_reset(hw);
1161
1162         /* Initialize DCB configuration*/
1163         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1164         ixgbe_dcb_init(hw, dcb_config);
1165         /* Get Hardware Flow Control setting */
1166         hw->fc.requested_mode = ixgbe_fc_full;
1167         hw->fc.current_mode = ixgbe_fc_full;
1168         hw->fc.pause_time = IXGBE_FC_PAUSE;
1169         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1170                 hw->fc.low_water[i] = IXGBE_FC_LO;
1171                 hw->fc.high_water[i] = IXGBE_FC_HI;
1172         }
1173         hw->fc.send_xon = 1;
1174
1175         /* Make sure we have a good EEPROM before we read from it */
1176         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1177         if (diag != IXGBE_SUCCESS) {
1178                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1179                 return -EIO;
1180         }
1181
1182 #ifdef RTE_NIC_BYPASS
1183         diag = ixgbe_bypass_init_hw(hw);
1184 #else
1185         diag = ixgbe_init_hw(hw);
1186 #endif /* RTE_NIC_BYPASS */
1187
1188         /*
1189          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1190          * is called too soon after the kernel driver unbinding/binding occurs.
1191          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1192          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1193          * also called. See ixgbe_identify_phy_82599(). The reason for the
1194          * failure is not known, and only occuts when virtualisation features
1195          * are disabled in the bios. A delay of 100ms  was found to be enough by
1196          * trial-and-error, and is doubled to be safe.
1197          */
1198         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1199                 rte_delay_ms(200);
1200                 diag = ixgbe_init_hw(hw);
1201         }
1202
1203         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1204                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1205                              "LOM.  Please be aware there may be issues associated "
1206                              "with your hardware.");
1207                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1208                              "please contact your Intel or hardware representative "
1209                              "who provided you with this hardware.");
1210         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1211                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1212         if (diag) {
1213                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1214                 return -EIO;
1215         }
1216
1217         /* Reset the hw statistics */
1218         ixgbe_dev_stats_reset(eth_dev);
1219
1220         /* disable interrupt */
1221         ixgbe_disable_intr(hw);
1222
1223         /* reset mappings for queue statistics hw counters*/
1224         ixgbe_reset_qstat_mappings(hw);
1225
1226         /* Allocate memory for storing MAC addresses */
1227         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1228                                                hw->mac.num_rar_entries, 0);
1229         if (eth_dev->data->mac_addrs == NULL) {
1230                 PMD_INIT_LOG(ERR,
1231                              "Failed to allocate %u bytes needed to store "
1232                              "MAC addresses",
1233                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1234                 return -ENOMEM;
1235         }
1236         /* Copy the permanent MAC address */
1237         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1238                         &eth_dev->data->mac_addrs[0]);
1239
1240         /* Allocate memory for storing hash filter MAC addresses */
1241         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1242                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1243         if (eth_dev->data->hash_mac_addrs == NULL) {
1244                 PMD_INIT_LOG(ERR,
1245                              "Failed to allocate %d bytes needed to store MAC addresses",
1246                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1247                 return -ENOMEM;
1248         }
1249
1250         /* initialize the vfta */
1251         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1252
1253         /* initialize the hw strip bitmap*/
1254         memset(hwstrip, 0, sizeof(*hwstrip));
1255
1256         /* initialize PF if max_vfs not zero */
1257         ixgbe_pf_host_init(eth_dev);
1258
1259         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1260         /* let hardware know driver is loaded */
1261         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1262         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1263         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1264         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1265         IXGBE_WRITE_FLUSH(hw);
1266
1267         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1268                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1269                              (int) hw->mac.type, (int) hw->phy.type,
1270                              (int) hw->phy.sfp_type);
1271         else
1272                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1273                              (int) hw->mac.type, (int) hw->phy.type);
1274
1275         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1276                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1277                      pci_dev->id.device_id);
1278
1279         rte_intr_callback_register(intr_handle,
1280                                    ixgbe_dev_interrupt_handler, eth_dev);
1281
1282         /* enable uio/vfio intr/eventfd mapping */
1283         rte_intr_enable(intr_handle);
1284
1285         /* enable support intr */
1286         ixgbe_enable_intr(eth_dev);
1287
1288         /* initialize 5tuple filter list */
1289         TAILQ_INIT(&filter_info->fivetuple_list);
1290         memset(filter_info->fivetuple_mask, 0,
1291                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1292
1293         return 0;
1294 }
1295
1296 static int
1297 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1298 {
1299         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1300         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1301         struct ixgbe_hw *hw;
1302
1303         PMD_INIT_FUNC_TRACE();
1304
1305         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1306                 return -EPERM;
1307
1308         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1309
1310         if (hw->adapter_stopped == 0)
1311                 ixgbe_dev_close(eth_dev);
1312
1313         eth_dev->dev_ops = NULL;
1314         eth_dev->rx_pkt_burst = NULL;
1315         eth_dev->tx_pkt_burst = NULL;
1316
1317         /* Unlock any pending hardware semaphore */
1318         ixgbe_swfw_lock_reset(hw);
1319
1320         /* disable uio intr before callback unregister */
1321         rte_intr_disable(intr_handle);
1322         rte_intr_callback_unregister(intr_handle,
1323                                      ixgbe_dev_interrupt_handler, eth_dev);
1324
1325         /* uninitialize PF if max_vfs not zero */
1326         ixgbe_pf_host_uninit(eth_dev);
1327
1328         rte_free(eth_dev->data->mac_addrs);
1329         eth_dev->data->mac_addrs = NULL;
1330
1331         rte_free(eth_dev->data->hash_mac_addrs);
1332         eth_dev->data->hash_mac_addrs = NULL;
1333
1334         return 0;
1335 }
1336
1337 /*
1338  * Negotiate mailbox API version with the PF.
1339  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1340  * Then we try to negotiate starting with the most recent one.
1341  * If all negotiation attempts fail, then we will proceed with
1342  * the default one (ixgbe_mbox_api_10).
1343  */
1344 static void
1345 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1346 {
1347         int32_t i;
1348
1349         /* start with highest supported, proceed down */
1350         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1351                 ixgbe_mbox_api_12,
1352                 ixgbe_mbox_api_11,
1353                 ixgbe_mbox_api_10,
1354         };
1355
1356         for (i = 0;
1357                         i != RTE_DIM(sup_ver) &&
1358                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1359                         i++)
1360                 ;
1361 }
1362
1363 static void
1364 generate_random_mac_addr(struct ether_addr *mac_addr)
1365 {
1366         uint64_t random;
1367
1368         /* Set Organizationally Unique Identifier (OUI) prefix. */
1369         mac_addr->addr_bytes[0] = 0x00;
1370         mac_addr->addr_bytes[1] = 0x09;
1371         mac_addr->addr_bytes[2] = 0xC0;
1372         /* Force indication of locally assigned MAC address. */
1373         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1374         /* Generate the last 3 bytes of the MAC address with a random number. */
1375         random = rte_rand();
1376         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1377 }
1378
1379 /*
1380  * Virtual Function device init
1381  */
1382 static int
1383 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1384 {
1385         int diag;
1386         uint32_t tc, tcs;
1387         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1388         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1389         struct ixgbe_hw *hw =
1390                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1391         struct ixgbe_vfta *shadow_vfta =
1392                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1393         struct ixgbe_hwstrip *hwstrip =
1394                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1395         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1396
1397         PMD_INIT_FUNC_TRACE();
1398
1399         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1400         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1401         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1402
1403         /* for secondary processes, we don't initialise any further as primary
1404          * has already done this work. Only check we don't need a different
1405          * RX function
1406          */
1407         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1408                 struct ixgbe_tx_queue *txq;
1409                 /* TX queue function in primary, set by last queue initialized
1410                  * Tx queue may not initialized by primary process
1411                  */
1412                 if (eth_dev->data->tx_queues) {
1413                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1414                         ixgbe_set_tx_function(eth_dev, txq);
1415                 } else {
1416                         /* Use default TX function if we get here */
1417                         PMD_INIT_LOG(NOTICE,
1418                                      "No TX queues configured yet. Using default TX function.");
1419                 }
1420
1421                 ixgbe_set_rx_function(eth_dev);
1422
1423                 return 0;
1424         }
1425
1426         rte_eth_copy_pci_info(eth_dev, pci_dev);
1427
1428         hw->device_id = pci_dev->id.device_id;
1429         hw->vendor_id = pci_dev->id.vendor_id;
1430         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1431
1432         /* initialize the vfta */
1433         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1434
1435         /* initialize the hw strip bitmap*/
1436         memset(hwstrip, 0, sizeof(*hwstrip));
1437
1438         /* Initialize the shared code (base driver) */
1439         diag = ixgbe_init_shared_code(hw);
1440         if (diag != IXGBE_SUCCESS) {
1441                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1442                 return -EIO;
1443         }
1444
1445         /* init_mailbox_params */
1446         hw->mbx.ops.init_params(hw);
1447
1448         /* Reset the hw statistics */
1449         ixgbevf_dev_stats_reset(eth_dev);
1450
1451         /* Disable the interrupts for VF */
1452         ixgbevf_intr_disable(hw);
1453
1454         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1455         diag = hw->mac.ops.reset_hw(hw);
1456
1457         /*
1458          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1459          * the underlying PF driver has not assigned a MAC address to the VF.
1460          * In this case, assign a random MAC address.
1461          */
1462         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1463                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1464                 return diag;
1465         }
1466
1467         /* negotiate mailbox API version to use with the PF. */
1468         ixgbevf_negotiate_api(hw);
1469
1470         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1471         ixgbevf_get_queues(hw, &tcs, &tc);
1472
1473         /* Allocate memory for storing MAC addresses */
1474         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1475                                                hw->mac.num_rar_entries, 0);
1476         if (eth_dev->data->mac_addrs == NULL) {
1477                 PMD_INIT_LOG(ERR,
1478                              "Failed to allocate %u bytes needed to store "
1479                              "MAC addresses",
1480                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1481                 return -ENOMEM;
1482         }
1483
1484         /* Generate a random MAC address, if none was assigned by PF. */
1485         if (is_zero_ether_addr(perm_addr)) {
1486                 generate_random_mac_addr(perm_addr);
1487                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1488                 if (diag) {
1489                         rte_free(eth_dev->data->mac_addrs);
1490                         eth_dev->data->mac_addrs = NULL;
1491                         return diag;
1492                 }
1493                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1494                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1495                              "%02x:%02x:%02x:%02x:%02x:%02x",
1496                              perm_addr->addr_bytes[0],
1497                              perm_addr->addr_bytes[1],
1498                              perm_addr->addr_bytes[2],
1499                              perm_addr->addr_bytes[3],
1500                              perm_addr->addr_bytes[4],
1501                              perm_addr->addr_bytes[5]);
1502         }
1503
1504         /* Copy the permanent MAC address */
1505         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1506
1507         /* reset the hardware with the new settings */
1508         diag = hw->mac.ops.start_hw(hw);
1509         switch (diag) {
1510         case  0:
1511                 break;
1512
1513         default:
1514                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1515                 return -EIO;
1516         }
1517
1518         rte_intr_callback_register(intr_handle,
1519                                    ixgbevf_dev_interrupt_handler, eth_dev);
1520         rte_intr_enable(intr_handle);
1521         ixgbevf_intr_enable(hw);
1522
1523         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1524                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1525                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1526
1527         return 0;
1528 }
1529
1530 /* Virtual Function device uninit */
1531
1532 static int
1533 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1534 {
1535         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1536         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1537         struct ixgbe_hw *hw;
1538
1539         PMD_INIT_FUNC_TRACE();
1540
1541         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1542                 return -EPERM;
1543
1544         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1545
1546         if (hw->adapter_stopped == 0)
1547                 ixgbevf_dev_close(eth_dev);
1548
1549         eth_dev->dev_ops = NULL;
1550         eth_dev->rx_pkt_burst = NULL;
1551         eth_dev->tx_pkt_burst = NULL;
1552
1553         /* Disable the interrupts for VF */
1554         ixgbevf_intr_disable(hw);
1555
1556         rte_free(eth_dev->data->mac_addrs);
1557         eth_dev->data->mac_addrs = NULL;
1558
1559         rte_intr_disable(intr_handle);
1560         rte_intr_callback_unregister(intr_handle,
1561                                      ixgbevf_dev_interrupt_handler, eth_dev);
1562
1563         return 0;
1564 }
1565
1566 static struct eth_driver rte_ixgbe_pmd = {
1567         .pci_drv = {
1568                 .id_table = pci_id_ixgbe_map,
1569                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1570                         RTE_PCI_DRV_DETACHABLE,
1571                 .probe = rte_eth_dev_pci_probe,
1572                 .remove = rte_eth_dev_pci_remove,
1573         },
1574         .eth_dev_init = eth_ixgbe_dev_init,
1575         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1576         .dev_private_size = sizeof(struct ixgbe_adapter),
1577 };
1578
1579 /*
1580  * virtual function driver struct
1581  */
1582 static struct eth_driver rte_ixgbevf_pmd = {
1583         .pci_drv = {
1584                 .id_table = pci_id_ixgbevf_map,
1585                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1586                 .probe = rte_eth_dev_pci_probe,
1587                 .remove = rte_eth_dev_pci_remove,
1588         },
1589         .eth_dev_init = eth_ixgbevf_dev_init,
1590         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1591         .dev_private_size = sizeof(struct ixgbe_adapter),
1592 };
1593
1594 static int
1595 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1596 {
1597         struct ixgbe_hw *hw =
1598                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1599         struct ixgbe_vfta *shadow_vfta =
1600                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1601         uint32_t vfta;
1602         uint32_t vid_idx;
1603         uint32_t vid_bit;
1604
1605         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1606         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1607         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1608         if (on)
1609                 vfta |= vid_bit;
1610         else
1611                 vfta &= ~vid_bit;
1612         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1613
1614         /* update local VFTA copy */
1615         shadow_vfta->vfta[vid_idx] = vfta;
1616
1617         return 0;
1618 }
1619
1620 static void
1621 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1622 {
1623         if (on)
1624                 ixgbe_vlan_hw_strip_enable(dev, queue);
1625         else
1626                 ixgbe_vlan_hw_strip_disable(dev, queue);
1627 }
1628
1629 static int
1630 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1631                     enum rte_vlan_type vlan_type,
1632                     uint16_t tpid)
1633 {
1634         struct ixgbe_hw *hw =
1635                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1636         int ret = 0;
1637         uint32_t reg;
1638         uint32_t qinq;
1639
1640         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1641         qinq &= IXGBE_DMATXCTL_GDV;
1642
1643         switch (vlan_type) {
1644         case ETH_VLAN_TYPE_INNER:
1645                 if (qinq) {
1646                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1647                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1648                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1649                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1650                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1651                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1652                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1653                 } else {
1654                         ret = -ENOTSUP;
1655                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1656                                     " by single VLAN");
1657                 }
1658                 break;
1659         case ETH_VLAN_TYPE_OUTER:
1660                 if (qinq) {
1661                         /* Only the high 16-bits is valid */
1662                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1663                                         IXGBE_EXVET_VET_EXT_SHIFT);
1664                 } else {
1665                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1666                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1667                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1668                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1669                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1670                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1671                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1672                 }
1673
1674                 break;
1675         default:
1676                 ret = -EINVAL;
1677                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1678                 break;
1679         }
1680
1681         return ret;
1682 }
1683
1684 void
1685 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1686 {
1687         struct ixgbe_hw *hw =
1688                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1689         uint32_t vlnctrl;
1690
1691         PMD_INIT_FUNC_TRACE();
1692
1693         /* Filter Table Disable */
1694         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1695         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1696
1697         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1698 }
1699
1700 void
1701 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1702 {
1703         struct ixgbe_hw *hw =
1704                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1705         struct ixgbe_vfta *shadow_vfta =
1706                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1707         uint32_t vlnctrl;
1708         uint16_t i;
1709
1710         PMD_INIT_FUNC_TRACE();
1711
1712         /* Filter Table Enable */
1713         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1714         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1715         vlnctrl |= IXGBE_VLNCTRL_VFE;
1716
1717         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1718
1719         /* write whatever is in local vfta copy */
1720         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1721                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1722 }
1723
1724 static void
1725 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1726 {
1727         struct ixgbe_hwstrip *hwstrip =
1728                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1729         struct ixgbe_rx_queue *rxq;
1730
1731         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1732                 return;
1733
1734         if (on)
1735                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1736         else
1737                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1738
1739         if (queue >= dev->data->nb_rx_queues)
1740                 return;
1741
1742         rxq = dev->data->rx_queues[queue];
1743
1744         if (on)
1745                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1746         else
1747                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1748 }
1749
1750 static void
1751 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1752 {
1753         struct ixgbe_hw *hw =
1754                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1755         uint32_t ctrl;
1756
1757         PMD_INIT_FUNC_TRACE();
1758
1759         if (hw->mac.type == ixgbe_mac_82598EB) {
1760                 /* No queue level support */
1761                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1762                 return;
1763         }
1764
1765         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1766         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1767         ctrl &= ~IXGBE_RXDCTL_VME;
1768         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1769
1770         /* record those setting for HW strip per queue */
1771         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1772 }
1773
1774 static void
1775 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1776 {
1777         struct ixgbe_hw *hw =
1778                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1779         uint32_t ctrl;
1780
1781         PMD_INIT_FUNC_TRACE();
1782
1783         if (hw->mac.type == ixgbe_mac_82598EB) {
1784                 /* No queue level supported */
1785                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1786                 return;
1787         }
1788
1789         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1790         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1791         ctrl |= IXGBE_RXDCTL_VME;
1792         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1793
1794         /* record those setting for HW strip per queue */
1795         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1796 }
1797
1798 void
1799 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1800 {
1801         struct ixgbe_hw *hw =
1802                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1803         uint32_t ctrl;
1804         uint16_t i;
1805         struct ixgbe_rx_queue *rxq;
1806
1807         PMD_INIT_FUNC_TRACE();
1808
1809         if (hw->mac.type == ixgbe_mac_82598EB) {
1810                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1811                 ctrl &= ~IXGBE_VLNCTRL_VME;
1812                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1813         } else {
1814                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1815                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1816                         rxq = dev->data->rx_queues[i];
1817                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1818                         ctrl &= ~IXGBE_RXDCTL_VME;
1819                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1820
1821                         /* record those setting for HW strip per queue */
1822                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1823                 }
1824         }
1825 }
1826
1827 void
1828 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1829 {
1830         struct ixgbe_hw *hw =
1831                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1832         uint32_t ctrl;
1833         uint16_t i;
1834         struct ixgbe_rx_queue *rxq;
1835
1836         PMD_INIT_FUNC_TRACE();
1837
1838         if (hw->mac.type == ixgbe_mac_82598EB) {
1839                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1840                 ctrl |= IXGBE_VLNCTRL_VME;
1841                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1842         } else {
1843                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1844                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1845                         rxq = dev->data->rx_queues[i];
1846                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1847                         ctrl |= IXGBE_RXDCTL_VME;
1848                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1849
1850                         /* record those setting for HW strip per queue */
1851                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1852                 }
1853         }
1854 }
1855
1856 static void
1857 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1858 {
1859         struct ixgbe_hw *hw =
1860                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1861         uint32_t ctrl;
1862
1863         PMD_INIT_FUNC_TRACE();
1864
1865         /* DMATXCTRL: Geric Double VLAN Disable */
1866         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1867         ctrl &= ~IXGBE_DMATXCTL_GDV;
1868         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1869
1870         /* CTRL_EXT: Global Double VLAN Disable */
1871         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1872         ctrl &= ~IXGBE_EXTENDED_VLAN;
1873         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1874
1875 }
1876
1877 static void
1878 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1879 {
1880         struct ixgbe_hw *hw =
1881                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1882         uint32_t ctrl;
1883
1884         PMD_INIT_FUNC_TRACE();
1885
1886         /* DMATXCTRL: Geric Double VLAN Enable */
1887         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1888         ctrl |= IXGBE_DMATXCTL_GDV;
1889         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1890
1891         /* CTRL_EXT: Global Double VLAN Enable */
1892         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1893         ctrl |= IXGBE_EXTENDED_VLAN;
1894         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1895
1896         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1897         if (hw->mac.type == ixgbe_mac_X550 ||
1898             hw->mac.type == ixgbe_mac_X550EM_x ||
1899             hw->mac.type == ixgbe_mac_X550EM_a) {
1900                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1901                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1902                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1903         }
1904
1905         /*
1906          * VET EXT field in the EXVET register = 0x8100 by default
1907          * So no need to change. Same to VT field of DMATXCTL register
1908          */
1909 }
1910
1911 static void
1912 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1913 {
1914         if (mask & ETH_VLAN_STRIP_MASK) {
1915                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1916                         ixgbe_vlan_hw_strip_enable_all(dev);
1917                 else
1918                         ixgbe_vlan_hw_strip_disable_all(dev);
1919         }
1920
1921         if (mask & ETH_VLAN_FILTER_MASK) {
1922                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1923                         ixgbe_vlan_hw_filter_enable(dev);
1924                 else
1925                         ixgbe_vlan_hw_filter_disable(dev);
1926         }
1927
1928         if (mask & ETH_VLAN_EXTEND_MASK) {
1929                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1930                         ixgbe_vlan_hw_extend_enable(dev);
1931                 else
1932                         ixgbe_vlan_hw_extend_disable(dev);
1933         }
1934 }
1935
1936 static void
1937 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1938 {
1939         struct ixgbe_hw *hw =
1940                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1942         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1943
1944         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1945         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1946 }
1947
1948 static int
1949 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1950 {
1951         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
1952
1953         switch (nb_rx_q) {
1954         case 1:
1955         case 2:
1956                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1957                 break;
1958         case 4:
1959                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1960                 break;
1961         default:
1962                 return -EINVAL;
1963         }
1964
1965         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1966         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
1967
1968         return 0;
1969 }
1970
1971 static int
1972 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1973 {
1974         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1975         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1976         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1977         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1978
1979         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1980                 /* check multi-queue mode */
1981                 switch (dev_conf->rxmode.mq_mode) {
1982                 case ETH_MQ_RX_VMDQ_DCB:
1983                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1984                         break;
1985                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1986                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1987                         PMD_INIT_LOG(ERR, "SRIOV active,"
1988                                         " unsupported mq_mode rx %d.",
1989                                         dev_conf->rxmode.mq_mode);
1990                         return -EINVAL;
1991                 case ETH_MQ_RX_RSS:
1992                 case ETH_MQ_RX_VMDQ_RSS:
1993                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1994                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1995                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1996                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1997                                                 " invalid queue number"
1998                                                 " for VMDQ RSS, allowed"
1999                                                 " value are 1, 2 or 4.");
2000                                         return -EINVAL;
2001                                 }
2002                         break;
2003                 case ETH_MQ_RX_VMDQ_ONLY:
2004                 case ETH_MQ_RX_NONE:
2005                         /* if nothing mq mode configure, use default scheme */
2006                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2007                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2008                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2009                         break;
2010                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2011                         /* SRIOV only works in VMDq enable mode */
2012                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2013                                         " wrong mq_mode rx %d.",
2014                                         dev_conf->rxmode.mq_mode);
2015                         return -EINVAL;
2016                 }
2017
2018                 switch (dev_conf->txmode.mq_mode) {
2019                 case ETH_MQ_TX_VMDQ_DCB:
2020                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2021                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2022                         break;
2023                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2024                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2025                         break;
2026                 }
2027
2028                 /* check valid queue number */
2029                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2030                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2031                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2032                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2033                                         " must be less than or equal to %d.",
2034                                         nb_rx_q, nb_tx_q,
2035                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2036                         return -EINVAL;
2037                 }
2038         } else {
2039                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2040                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2041                                           " not supported.");
2042                         return -EINVAL;
2043                 }
2044                 /* check configuration for vmdb+dcb mode */
2045                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2046                         const struct rte_eth_vmdq_dcb_conf *conf;
2047
2048                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2049                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2050                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2051                                 return -EINVAL;
2052                         }
2053                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2054                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2055                                conf->nb_queue_pools == ETH_32_POOLS)) {
2056                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2057                                                 " nb_queue_pools must be %d or %d.",
2058                                                 ETH_16_POOLS, ETH_32_POOLS);
2059                                 return -EINVAL;
2060                         }
2061                 }
2062                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2063                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2064
2065                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2066                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2067                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2068                                 return -EINVAL;
2069                         }
2070                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2071                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2072                                conf->nb_queue_pools == ETH_32_POOLS)) {
2073                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2074                                                 " nb_queue_pools != %d and"
2075                                                 " nb_queue_pools != %d.",
2076                                                 ETH_16_POOLS, ETH_32_POOLS);
2077                                 return -EINVAL;
2078                         }
2079                 }
2080
2081                 /* For DCB mode check our configuration before we go further */
2082                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2083                         const struct rte_eth_dcb_rx_conf *conf;
2084
2085                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2086                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2087                                                  IXGBE_DCB_NB_QUEUES);
2088                                 return -EINVAL;
2089                         }
2090                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2091                         if (!(conf->nb_tcs == ETH_4_TCS ||
2092                                conf->nb_tcs == ETH_8_TCS)) {
2093                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2094                                                 " and nb_tcs != %d.",
2095                                                 ETH_4_TCS, ETH_8_TCS);
2096                                 return -EINVAL;
2097                         }
2098                 }
2099
2100                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2101                         const struct rte_eth_dcb_tx_conf *conf;
2102
2103                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2104                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2105                                                  IXGBE_DCB_NB_QUEUES);
2106                                 return -EINVAL;
2107                         }
2108                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2109                         if (!(conf->nb_tcs == ETH_4_TCS ||
2110                                conf->nb_tcs == ETH_8_TCS)) {
2111                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2112                                                 " and nb_tcs != %d.",
2113                                                 ETH_4_TCS, ETH_8_TCS);
2114                                 return -EINVAL;
2115                         }
2116                 }
2117
2118                 /*
2119                  * When DCB/VT is off, maximum number of queues changes,
2120                  * except for 82598EB, which remains constant.
2121                  */
2122                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2123                                 hw->mac.type != ixgbe_mac_82598EB) {
2124                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2125                                 PMD_INIT_LOG(ERR,
2126                                              "Neither VT nor DCB are enabled, "
2127                                              "nb_tx_q > %d.",
2128                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2129                                 return -EINVAL;
2130                         }
2131                 }
2132         }
2133         return 0;
2134 }
2135
2136 static int
2137 ixgbe_dev_configure(struct rte_eth_dev *dev)
2138 {
2139         struct ixgbe_interrupt *intr =
2140                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2141         struct ixgbe_adapter *adapter =
2142                 (struct ixgbe_adapter *)dev->data->dev_private;
2143         int ret;
2144
2145         PMD_INIT_FUNC_TRACE();
2146         /* multipe queue mode checking */
2147         ret  = ixgbe_check_mq_mode(dev);
2148         if (ret != 0) {
2149                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2150                             ret);
2151                 return ret;
2152         }
2153
2154         /* set flag to update link status after init */
2155         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2156
2157         /*
2158          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2159          * allocation or vector Rx preconditions we will reset it.
2160          */
2161         adapter->rx_bulk_alloc_allowed = true;
2162         adapter->rx_vec_allowed = true;
2163
2164         return 0;
2165 }
2166
2167 static void
2168 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2169 {
2170         struct ixgbe_hw *hw =
2171                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2172         struct ixgbe_interrupt *intr =
2173                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2174         uint32_t gpie;
2175
2176         /* only set up it on X550EM_X */
2177         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2178                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2179                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2180                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2181                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2182                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2183         }
2184 }
2185
2186 /*
2187  * Configure device link speed and setup link.
2188  * It returns 0 on success.
2189  */
2190 static int
2191 ixgbe_dev_start(struct rte_eth_dev *dev)
2192 {
2193         struct ixgbe_hw *hw =
2194                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2195         struct ixgbe_vf_info *vfinfo =
2196                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2197         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2198         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2199         uint32_t intr_vector = 0;
2200         int err, link_up = 0, negotiate = 0;
2201         uint32_t speed = 0;
2202         int mask = 0;
2203         int status;
2204         uint16_t vf, idx;
2205         uint32_t *link_speeds;
2206
2207         PMD_INIT_FUNC_TRACE();
2208
2209         /* IXGBE devices don't support:
2210         *    - half duplex (checked afterwards for valid speeds)
2211         *    - fixed speed: TODO implement
2212         */
2213         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2214                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2215                              dev->data->port_id);
2216                 return -EINVAL;
2217         }
2218
2219         /* disable uio/vfio intr/eventfd mapping */
2220         rte_intr_disable(intr_handle);
2221
2222         /* stop adapter */
2223         hw->adapter_stopped = 0;
2224         ixgbe_stop_adapter(hw);
2225
2226         /* reinitialize adapter
2227          * this calls reset and start
2228          */
2229         status = ixgbe_pf_reset_hw(hw);
2230         if (status != 0)
2231                 return -1;
2232         hw->mac.ops.start_hw(hw);
2233         hw->mac.get_link_status = true;
2234
2235         /* configure PF module if SRIOV enabled */
2236         ixgbe_pf_host_configure(dev);
2237
2238         ixgbe_dev_phy_intr_setup(dev);
2239
2240         /* check and configure queue intr-vector mapping */
2241         if ((rte_intr_cap_multiple(intr_handle) ||
2242              !RTE_ETH_DEV_SRIOV(dev).active) &&
2243             dev->data->dev_conf.intr_conf.rxq != 0) {
2244                 intr_vector = dev->data->nb_rx_queues;
2245                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2246                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2247                                         IXGBE_MAX_INTR_QUEUE_NUM);
2248                         return -ENOTSUP;
2249                 }
2250                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2251                         return -1;
2252         }
2253
2254         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2255                 intr_handle->intr_vec =
2256                         rte_zmalloc("intr_vec",
2257                                     dev->data->nb_rx_queues * sizeof(int), 0);
2258                 if (intr_handle->intr_vec == NULL) {
2259                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2260                                      " intr_vec\n", dev->data->nb_rx_queues);
2261                         return -ENOMEM;
2262                 }
2263         }
2264
2265         /* confiugre msix for sleep until rx interrupt */
2266         ixgbe_configure_msix(dev);
2267
2268         /* initialize transmission unit */
2269         ixgbe_dev_tx_init(dev);
2270
2271         /* This can fail when allocating mbufs for descriptor rings */
2272         err = ixgbe_dev_rx_init(dev);
2273         if (err) {
2274                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2275                 goto error;
2276         }
2277
2278     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2279                 ETH_VLAN_EXTEND_MASK;
2280         ixgbe_vlan_offload_set(dev, mask);
2281
2282         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2283                 /* Enable vlan filtering for VMDq */
2284                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2285         }
2286
2287         /* Configure DCB hw */
2288         ixgbe_configure_dcb(dev);
2289
2290         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2291                 err = ixgbe_fdir_configure(dev);
2292                 if (err)
2293                         goto error;
2294         }
2295
2296         /* Restore vf rate limit */
2297         if (vfinfo != NULL) {
2298                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2299                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2300                                 if (vfinfo[vf].tx_rate[idx] != 0)
2301                                         ixgbe_set_vf_rate_limit(dev, vf,
2302                                                 vfinfo[vf].tx_rate[idx],
2303                                                 1 << idx);
2304         }
2305
2306         ixgbe_restore_statistics_mapping(dev);
2307
2308         err = ixgbe_dev_rxtx_start(dev);
2309         if (err < 0) {
2310                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2311                 goto error;
2312         }
2313
2314         /* Skip link setup if loopback mode is enabled for 82599. */
2315         if (hw->mac.type == ixgbe_mac_82599EB &&
2316                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2317                 goto skip_link_setup;
2318
2319         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2320                 err = hw->mac.ops.setup_sfp(hw);
2321                 if (err)
2322                         goto error;
2323         }
2324
2325         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2326                 /* Turn on the copper */
2327                 ixgbe_set_phy_power(hw, true);
2328         } else {
2329                 /* Turn on the laser */
2330                 ixgbe_enable_tx_laser(hw);
2331         }
2332
2333         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2334         if (err)
2335                 goto error;
2336         dev->data->dev_link.link_status = link_up;
2337
2338         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2339         if (err)
2340                 goto error;
2341
2342         link_speeds = &dev->data->dev_conf.link_speeds;
2343         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2344                         ETH_LINK_SPEED_10G)) {
2345                 PMD_INIT_LOG(ERR, "Invalid link setting");
2346                 goto error;
2347         }
2348
2349         speed = 0x0;
2350         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2351                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2352                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2353                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2354         } else {
2355                 if (*link_speeds & ETH_LINK_SPEED_10G)
2356                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2357                 if (*link_speeds & ETH_LINK_SPEED_1G)
2358                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2359                 if (*link_speeds & ETH_LINK_SPEED_100M)
2360                         speed |= IXGBE_LINK_SPEED_100_FULL;
2361         }
2362
2363         err = ixgbe_setup_link(hw, speed, link_up);
2364         if (err)
2365                 goto error;
2366
2367 skip_link_setup:
2368
2369         if (rte_intr_allow_others(intr_handle)) {
2370                 /* check if lsc interrupt is enabled */
2371                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2372                         ixgbe_dev_lsc_interrupt_setup(dev);
2373         } else {
2374                 rte_intr_callback_unregister(intr_handle,
2375                                              ixgbe_dev_interrupt_handler, dev);
2376                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2377                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2378                                      " no intr multiplex\n");
2379         }
2380
2381         /* check if rxq interrupt is enabled */
2382         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2383             rte_intr_dp_is_en(intr_handle))
2384                 ixgbe_dev_rxq_interrupt_setup(dev);
2385
2386         /* enable uio/vfio intr/eventfd mapping */
2387         rte_intr_enable(intr_handle);
2388
2389         /* resume enabled intr since hw reset */
2390         ixgbe_enable_intr(dev);
2391
2392         return 0;
2393
2394 error:
2395         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2396         ixgbe_dev_clear_queues(dev);
2397         return -EIO;
2398 }
2399
2400 /*
2401  * Stop device: disable rx and tx functions to allow for reconfiguring.
2402  */
2403 static void
2404 ixgbe_dev_stop(struct rte_eth_dev *dev)
2405 {
2406         struct rte_eth_link link;
2407         struct ixgbe_hw *hw =
2408                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2409         struct ixgbe_vf_info *vfinfo =
2410                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2411         struct ixgbe_filter_info *filter_info =
2412                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2413         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2414         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2415         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2416         int vf;
2417
2418         PMD_INIT_FUNC_TRACE();
2419
2420         /* disable interrupts */
2421         ixgbe_disable_intr(hw);
2422
2423         /* reset the NIC */
2424         ixgbe_pf_reset_hw(hw);
2425         hw->adapter_stopped = 0;
2426
2427         /* stop adapter */
2428         ixgbe_stop_adapter(hw);
2429
2430         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2431                 vfinfo[vf].clear_to_send = false;
2432
2433         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2434                 /* Turn off the copper */
2435                 ixgbe_set_phy_power(hw, false);
2436         } else {
2437                 /* Turn off the laser */
2438                 ixgbe_disable_tx_laser(hw);
2439         }
2440
2441         ixgbe_dev_clear_queues(dev);
2442
2443         /* Clear stored conf */
2444         dev->data->scattered_rx = 0;
2445         dev->data->lro = 0;
2446
2447         /* Clear recorded link status */
2448         memset(&link, 0, sizeof(link));
2449         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2450
2451         /* Remove all ntuple filters of the device */
2452         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2453              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2454                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2455                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2456                              p_5tuple, entries);
2457                 rte_free(p_5tuple);
2458         }
2459         memset(filter_info->fivetuple_mask, 0,
2460                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2461
2462         if (!rte_intr_allow_others(intr_handle))
2463                 /* resume to the default handler */
2464                 rte_intr_callback_register(intr_handle,
2465                                            ixgbe_dev_interrupt_handler,
2466                                            (void *)dev);
2467
2468         /* Clean datapath event and queue/vec mapping */
2469         rte_intr_efd_disable(intr_handle);
2470         if (intr_handle->intr_vec != NULL) {
2471                 rte_free(intr_handle->intr_vec);
2472                 intr_handle->intr_vec = NULL;
2473         }
2474 }
2475
2476 /*
2477  * Set device link up: enable tx.
2478  */
2479 static int
2480 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2481 {
2482         struct ixgbe_hw *hw =
2483                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2484         if (hw->mac.type == ixgbe_mac_82599EB) {
2485 #ifdef RTE_NIC_BYPASS
2486                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2487                         /* Not suported in bypass mode */
2488                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2489                                      "by device id 0x%x", hw->device_id);
2490                         return -ENOTSUP;
2491                 }
2492 #endif
2493         }
2494
2495         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2496                 /* Turn on the copper */
2497                 ixgbe_set_phy_power(hw, true);
2498         } else {
2499                 /* Turn on the laser */
2500                 ixgbe_enable_tx_laser(hw);
2501         }
2502
2503         return 0;
2504 }
2505
2506 /*
2507  * Set device link down: disable tx.
2508  */
2509 static int
2510 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2511 {
2512         struct ixgbe_hw *hw =
2513                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2514         if (hw->mac.type == ixgbe_mac_82599EB) {
2515 #ifdef RTE_NIC_BYPASS
2516                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2517                         /* Not suported in bypass mode */
2518                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2519                                      "by device id 0x%x", hw->device_id);
2520                         return -ENOTSUP;
2521                 }
2522 #endif
2523         }
2524
2525         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2526                 /* Turn off the copper */
2527                 ixgbe_set_phy_power(hw, false);
2528         } else {
2529                 /* Turn off the laser */
2530                 ixgbe_disable_tx_laser(hw);
2531         }
2532
2533         return 0;
2534 }
2535
2536 /*
2537  * Reest and stop device.
2538  */
2539 static void
2540 ixgbe_dev_close(struct rte_eth_dev *dev)
2541 {
2542         struct ixgbe_hw *hw =
2543                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2544
2545         PMD_INIT_FUNC_TRACE();
2546
2547         ixgbe_pf_reset_hw(hw);
2548
2549         ixgbe_dev_stop(dev);
2550         hw->adapter_stopped = 1;
2551
2552         ixgbe_dev_free_queues(dev);
2553
2554         ixgbe_disable_pcie_master(hw);
2555
2556         /* reprogram the RAR[0] in case user changed it. */
2557         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2558 }
2559
2560 static void
2561 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2562                            struct ixgbe_hw_stats *hw_stats,
2563                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2564                            uint64_t *total_qprc, uint64_t *total_qprdc)
2565 {
2566         uint32_t bprc, lxon, lxoff, total;
2567         uint32_t delta_gprc = 0;
2568         unsigned i;
2569         /* Workaround for RX byte count not including CRC bytes when CRC
2570 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2571          * is disabled.
2572 +        */
2573         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2574                         IXGBE_HLREG0_RXCRCSTRP);
2575
2576         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2577         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2578         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2579         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2580
2581         for (i = 0; i < 8; i++) {
2582                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2583
2584                 /* global total per queue */
2585                 hw_stats->mpc[i] += mp;
2586                 /* Running comprehensive total for stats display */
2587                 *total_missed_rx += hw_stats->mpc[i];
2588                 if (hw->mac.type == ixgbe_mac_82598EB) {
2589                         hw_stats->rnbc[i] +=
2590                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2591                         hw_stats->pxonrxc[i] +=
2592                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2593                         hw_stats->pxoffrxc[i] +=
2594                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2595                 } else {
2596                         hw_stats->pxonrxc[i] +=
2597                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2598                         hw_stats->pxoffrxc[i] +=
2599                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2600                         hw_stats->pxon2offc[i] +=
2601                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2602                 }
2603                 hw_stats->pxontxc[i] +=
2604                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2605                 hw_stats->pxofftxc[i] +=
2606                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2607         }
2608         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2609                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2610                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2611                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2612
2613                 delta_gprc += delta_qprc;
2614
2615                 hw_stats->qprc[i] += delta_qprc;
2616                 hw_stats->qptc[i] += delta_qptc;
2617
2618                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2619                 hw_stats->qbrc[i] +=
2620                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2621                 if (crc_strip == 0)
2622                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2623
2624                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2625                 hw_stats->qbtc[i] +=
2626                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2627
2628                 hw_stats->qprdc[i] += delta_qprdc;
2629                 *total_qprdc += hw_stats->qprdc[i];
2630
2631                 *total_qprc += hw_stats->qprc[i];
2632                 *total_qbrc += hw_stats->qbrc[i];
2633         }
2634         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2635         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2636         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2637
2638         /*
2639          * An errata states that gprc actually counts good + missed packets:
2640          * Workaround to set gprc to summated queue packet receives
2641          */
2642         hw_stats->gprc = *total_qprc;
2643
2644         if (hw->mac.type != ixgbe_mac_82598EB) {
2645                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2646                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2647                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2648                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2649                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2650                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2651                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2652                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2653         } else {
2654                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2655                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2656                 /* 82598 only has a counter in the high register */
2657                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2658                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2659                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2660         }
2661         uint64_t old_tpr = hw_stats->tpr;
2662
2663         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2664         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2665
2666         if (crc_strip == 0)
2667                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2668
2669         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2670         hw_stats->gptc += delta_gptc;
2671         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2672         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2673
2674         /*
2675          * Workaround: mprc hardware is incorrectly counting
2676          * broadcasts, so for now we subtract those.
2677          */
2678         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2679         hw_stats->bprc += bprc;
2680         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2681         if (hw->mac.type == ixgbe_mac_82598EB)
2682                 hw_stats->mprc -= bprc;
2683
2684         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2685         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2686         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2687         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2688         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2689         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2690
2691         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2692         hw_stats->lxontxc += lxon;
2693         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2694         hw_stats->lxofftxc += lxoff;
2695         total = lxon + lxoff;
2696
2697         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2698         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2699         hw_stats->gptc -= total;
2700         hw_stats->mptc -= total;
2701         hw_stats->ptc64 -= total;
2702         hw_stats->gotc -= total * ETHER_MIN_LEN;
2703
2704         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2705         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2706         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2707         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2708         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2709         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2710         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2711         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2712         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2713         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2714         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2715         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2716         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2717         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2718         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2719         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2720         /* Only read FCOE on 82599 */
2721         if (hw->mac.type != ixgbe_mac_82598EB) {
2722                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2723                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2724                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2725                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2726                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2727         }
2728
2729         /* Flow Director Stats registers */
2730         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2731         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2732 }
2733
2734 /*
2735  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2736  */
2737 static void
2738 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2739 {
2740         struct ixgbe_hw *hw =
2741                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2742         struct ixgbe_hw_stats *hw_stats =
2743                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2744         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2745         unsigned i;
2746
2747         total_missed_rx = 0;
2748         total_qbrc = 0;
2749         total_qprc = 0;
2750         total_qprdc = 0;
2751
2752         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2753                         &total_qprc, &total_qprdc);
2754
2755         if (stats == NULL)
2756                 return;
2757
2758         /* Fill out the rte_eth_stats statistics structure */
2759         stats->ipackets = total_qprc;
2760         stats->ibytes = total_qbrc;
2761         stats->opackets = hw_stats->gptc;
2762         stats->obytes = hw_stats->gotc;
2763
2764         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2765                 stats->q_ipackets[i] = hw_stats->qprc[i];
2766                 stats->q_opackets[i] = hw_stats->qptc[i];
2767                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2768                 stats->q_obytes[i] = hw_stats->qbtc[i];
2769                 stats->q_errors[i] = hw_stats->qprdc[i];
2770         }
2771
2772         /* Rx Errors */
2773         stats->imissed  = total_missed_rx;
2774         stats->ierrors  = hw_stats->crcerrs +
2775                           hw_stats->mspdc +
2776                           hw_stats->rlec +
2777                           hw_stats->ruc +
2778                           hw_stats->roc +
2779                           hw_stats->illerrc +
2780                           hw_stats->errbc +
2781                           hw_stats->rfc +
2782                           hw_stats->fccrc +
2783                           hw_stats->fclast;
2784
2785         /* Tx Errors */
2786         stats->oerrors  = 0;
2787 }
2788
2789 static void
2790 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2791 {
2792         struct ixgbe_hw_stats *stats =
2793                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2794
2795         /* HW registers are cleared on read */
2796         ixgbe_dev_stats_get(dev, NULL);
2797
2798         /* Reset software totals */
2799         memset(stats, 0, sizeof(*stats));
2800 }
2801
2802 /* This function calculates the number of xstats based on the current config */
2803 static unsigned
2804 ixgbe_xstats_calc_num(void) {
2805         return IXGBE_NB_HW_STATS +
2806                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2807                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2808 }
2809
2810 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2811         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2812 {
2813         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2814         unsigned stat, i, count;
2815
2816         if (xstats_names != NULL) {
2817                 count = 0;
2818
2819                 /* Note: limit >= cnt_stats checked upstream
2820                  * in rte_eth_xstats_names()
2821                  */
2822
2823                 /* Extended stats from ixgbe_hw_stats */
2824                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2825                         snprintf(xstats_names[count].name,
2826                                 sizeof(xstats_names[count].name),
2827                                 "%s",
2828                                 rte_ixgbe_stats_strings[i].name);
2829                         count++;
2830                 }
2831
2832                 /* RX Priority Stats */
2833                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2834                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2835                                 snprintf(xstats_names[count].name,
2836                                         sizeof(xstats_names[count].name),
2837                                         "rx_priority%u_%s", i,
2838                                         rte_ixgbe_rxq_strings[stat].name);
2839                                 count++;
2840                         }
2841                 }
2842
2843                 /* TX Priority Stats */
2844                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2845                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2846                                 snprintf(xstats_names[count].name,
2847                                         sizeof(xstats_names[count].name),
2848                                         "tx_priority%u_%s", i,
2849                                         rte_ixgbe_txq_strings[stat].name);
2850                                 count++;
2851                         }
2852                 }
2853         }
2854         return cnt_stats;
2855 }
2856
2857 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2858         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2859 {
2860         unsigned i;
2861
2862         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2863                 return -ENOMEM;
2864
2865         if (xstats_names != NULL)
2866                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2867                         snprintf(xstats_names[i].name,
2868                                 sizeof(xstats_names[i].name),
2869                                 "%s", rte_ixgbevf_stats_strings[i].name);
2870         return IXGBEVF_NB_XSTATS;
2871 }
2872
2873 static int
2874 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2875                                          unsigned n)
2876 {
2877         struct ixgbe_hw *hw =
2878                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2879         struct ixgbe_hw_stats *hw_stats =
2880                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2881         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2882         unsigned i, stat, count = 0;
2883
2884         count = ixgbe_xstats_calc_num();
2885
2886         if (n < count)
2887                 return count;
2888
2889         total_missed_rx = 0;
2890         total_qbrc = 0;
2891         total_qprc = 0;
2892         total_qprdc = 0;
2893
2894         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2895                                    &total_qprc, &total_qprdc);
2896
2897         /* If this is a reset xstats is NULL, and we have cleared the
2898          * registers by reading them.
2899          */
2900         if (!xstats)
2901                 return 0;
2902
2903         /* Extended stats from ixgbe_hw_stats */
2904         count = 0;
2905         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2906                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2907                                 rte_ixgbe_stats_strings[i].offset);
2908                 xstats[count].id = count;
2909                 count++;
2910         }
2911
2912         /* RX Priority Stats */
2913         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2914                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2915                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2916                                         rte_ixgbe_rxq_strings[stat].offset +
2917                                         (sizeof(uint64_t) * i));
2918                         xstats[count].id = count;
2919                         count++;
2920                 }
2921         }
2922
2923         /* TX Priority Stats */
2924         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2925                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2926                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2927                                         rte_ixgbe_txq_strings[stat].offset +
2928                                         (sizeof(uint64_t) * i));
2929                         xstats[count].id = count;
2930                         count++;
2931                 }
2932         }
2933         return count;
2934 }
2935
2936 static void
2937 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2938 {
2939         struct ixgbe_hw_stats *stats =
2940                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2941
2942         unsigned count = ixgbe_xstats_calc_num();
2943
2944         /* HW registers are cleared on read */
2945         ixgbe_dev_xstats_get(dev, NULL, count);
2946
2947         /* Reset software totals */
2948         memset(stats, 0, sizeof(*stats));
2949 }
2950
2951 static void
2952 ixgbevf_update_stats(struct rte_eth_dev *dev)
2953 {
2954         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2955         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2956                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2957
2958         /* Good Rx packet, include VF loopback */
2959         UPDATE_VF_STAT(IXGBE_VFGPRC,
2960             hw_stats->last_vfgprc, hw_stats->vfgprc);
2961
2962         /* Good Rx octets, include VF loopback */
2963         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2964             hw_stats->last_vfgorc, hw_stats->vfgorc);
2965
2966         /* Good Tx packet, include VF loopback */
2967         UPDATE_VF_STAT(IXGBE_VFGPTC,
2968             hw_stats->last_vfgptc, hw_stats->vfgptc);
2969
2970         /* Good Tx octets, include VF loopback */
2971         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2972             hw_stats->last_vfgotc, hw_stats->vfgotc);
2973
2974         /* Rx Multicst Packet */
2975         UPDATE_VF_STAT(IXGBE_VFMPRC,
2976             hw_stats->last_vfmprc, hw_stats->vfmprc);
2977 }
2978
2979 static int
2980 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2981                        unsigned n)
2982 {
2983         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2984                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2985         unsigned i;
2986
2987         if (n < IXGBEVF_NB_XSTATS)
2988                 return IXGBEVF_NB_XSTATS;
2989
2990         ixgbevf_update_stats(dev);
2991
2992         if (!xstats)
2993                 return 0;
2994
2995         /* Extended stats */
2996         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2997                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2998                         rte_ixgbevf_stats_strings[i].offset);
2999         }
3000
3001         return IXGBEVF_NB_XSTATS;
3002 }
3003
3004 static void
3005 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3006 {
3007         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3008                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3009
3010         ixgbevf_update_stats(dev);
3011
3012         if (stats == NULL)
3013                 return;
3014
3015         stats->ipackets = hw_stats->vfgprc;
3016         stats->ibytes = hw_stats->vfgorc;
3017         stats->opackets = hw_stats->vfgptc;
3018         stats->obytes = hw_stats->vfgotc;
3019 }
3020
3021 static void
3022 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3023 {
3024         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3025                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3026
3027         /* Sync HW register to the last stats */
3028         ixgbevf_dev_stats_get(dev, NULL);
3029
3030         /* reset HW current stats*/
3031         hw_stats->vfgprc = 0;
3032         hw_stats->vfgorc = 0;
3033         hw_stats->vfgptc = 0;
3034         hw_stats->vfgotc = 0;
3035 }
3036
3037 static void
3038 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3039 {
3040         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3041         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3042         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3043
3044         dev_info->pci_dev = pci_dev;
3045         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3046         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3047         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3048                 /*
3049                  * When DCB/VT is off, maximum number of queues changes,
3050                  * except for 82598EB, which remains constant.
3051                  */
3052                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3053                                 hw->mac.type != ixgbe_mac_82598EB)
3054                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3055         }
3056         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3057         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3058         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3059         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3060         dev_info->max_vfs = pci_dev->max_vfs;
3061         if (hw->mac.type == ixgbe_mac_82598EB)
3062                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3063         else
3064                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3065         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3066         dev_info->rx_offload_capa =
3067                 DEV_RX_OFFLOAD_VLAN_STRIP |
3068                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3069                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3070                 DEV_RX_OFFLOAD_TCP_CKSUM;
3071
3072         /*
3073          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3074          * mode.
3075          */
3076         if ((hw->mac.type == ixgbe_mac_82599EB ||
3077              hw->mac.type == ixgbe_mac_X540) &&
3078             !RTE_ETH_DEV_SRIOV(dev).active)
3079                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3080
3081         if (hw->mac.type == ixgbe_mac_X550 ||
3082             hw->mac.type == ixgbe_mac_X550EM_x ||
3083             hw->mac.type == ixgbe_mac_X550EM_a)
3084                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3085
3086         dev_info->tx_offload_capa =
3087                 DEV_TX_OFFLOAD_VLAN_INSERT |
3088                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3089                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3090                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3091                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3092                 DEV_TX_OFFLOAD_TCP_TSO;
3093
3094         if (hw->mac.type == ixgbe_mac_X550 ||
3095             hw->mac.type == ixgbe_mac_X550EM_x ||
3096             hw->mac.type == ixgbe_mac_X550EM_a)
3097                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3098
3099         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3100                 .rx_thresh = {
3101                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3102                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3103                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3104                 },
3105                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3106                 .rx_drop_en = 0,
3107         };
3108
3109         dev_info->default_txconf = (struct rte_eth_txconf) {
3110                 .tx_thresh = {
3111                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3112                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3113                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3114                 },
3115                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3116                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3117                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3118                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3119         };
3120
3121         dev_info->rx_desc_lim = rx_desc_lim;
3122         dev_info->tx_desc_lim = tx_desc_lim;
3123
3124         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3125         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3126         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3127
3128         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3129         if (hw->mac.type == ixgbe_mac_X540 ||
3130             hw->mac.type == ixgbe_mac_X540_vf ||
3131             hw->mac.type == ixgbe_mac_X550 ||
3132             hw->mac.type == ixgbe_mac_X550_vf) {
3133                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3134         }
3135 }
3136
3137 static const uint32_t *
3138 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3139 {
3140         static const uint32_t ptypes[] = {
3141                 /* For non-vec functions,
3142                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3143                  * for vec functions,
3144                  * refers to _recv_raw_pkts_vec().
3145                  */
3146                 RTE_PTYPE_L2_ETHER,
3147                 RTE_PTYPE_L3_IPV4,
3148                 RTE_PTYPE_L3_IPV4_EXT,
3149                 RTE_PTYPE_L3_IPV6,
3150                 RTE_PTYPE_L3_IPV6_EXT,
3151                 RTE_PTYPE_L4_SCTP,
3152                 RTE_PTYPE_L4_TCP,
3153                 RTE_PTYPE_L4_UDP,
3154                 RTE_PTYPE_TUNNEL_IP,
3155                 RTE_PTYPE_INNER_L3_IPV6,
3156                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3157                 RTE_PTYPE_INNER_L4_TCP,
3158                 RTE_PTYPE_INNER_L4_UDP,
3159                 RTE_PTYPE_UNKNOWN
3160         };
3161
3162         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3163             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3164             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3165             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3166                 return ptypes;
3167         return NULL;
3168 }
3169
3170 static void
3171 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3172                      struct rte_eth_dev_info *dev_info)
3173 {
3174         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3175         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3176
3177         dev_info->pci_dev = pci_dev;
3178         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3179         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3180         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3181         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3182         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3183         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3184         dev_info->max_vfs = pci_dev->max_vfs;
3185         if (hw->mac.type == ixgbe_mac_82598EB)
3186                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3187         else
3188                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3189         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3190                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3191                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3192                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3193         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3194                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3195                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3196                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3197                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3198                                 DEV_TX_OFFLOAD_TCP_TSO;
3199
3200         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3201                 .rx_thresh = {
3202                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3203                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3204                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3205                 },
3206                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3207                 .rx_drop_en = 0,
3208         };
3209
3210         dev_info->default_txconf = (struct rte_eth_txconf) {
3211                 .tx_thresh = {
3212                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3213                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3214                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3215                 },
3216                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3217                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3218                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3219                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3220         };
3221
3222         dev_info->rx_desc_lim = rx_desc_lim;
3223         dev_info->tx_desc_lim = tx_desc_lim;
3224 }
3225
3226 /* return 0 means link status changed, -1 means not changed */
3227 static int
3228 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3229 {
3230         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3231         struct rte_eth_link link, old;
3232         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3233         int link_up;
3234         int diag;
3235
3236         link.link_status = ETH_LINK_DOWN;
3237         link.link_speed = 0;
3238         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3239         memset(&old, 0, sizeof(old));
3240         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3241
3242         hw->mac.get_link_status = true;
3243
3244         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3245         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3246                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3247         else
3248                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3249
3250         if (diag != 0) {
3251                 link.link_speed = ETH_SPEED_NUM_100M;
3252                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3253                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3254                 if (link.link_status == old.link_status)
3255                         return -1;
3256                 return 0;
3257         }
3258
3259         if (link_up == 0) {
3260                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3261                 if (link.link_status == old.link_status)
3262                         return -1;
3263                 return 0;
3264         }
3265         link.link_status = ETH_LINK_UP;
3266         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3267
3268         switch (link_speed) {
3269         default:
3270         case IXGBE_LINK_SPEED_UNKNOWN:
3271                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3272                 link.link_speed = ETH_SPEED_NUM_100M;
3273                 break;
3274
3275         case IXGBE_LINK_SPEED_100_FULL:
3276                 link.link_speed = ETH_SPEED_NUM_100M;
3277                 break;
3278
3279         case IXGBE_LINK_SPEED_1GB_FULL:
3280                 link.link_speed = ETH_SPEED_NUM_1G;
3281                 break;
3282
3283         case IXGBE_LINK_SPEED_10GB_FULL:
3284                 link.link_speed = ETH_SPEED_NUM_10G;
3285                 break;
3286         }
3287         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3288
3289         if (link.link_status == old.link_status)
3290                 return -1;
3291
3292         return 0;
3293 }
3294
3295 static void
3296 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3297 {
3298         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3299         uint32_t fctrl;
3300
3301         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3302         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3303         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3304 }
3305
3306 static void
3307 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3308 {
3309         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3310         uint32_t fctrl;
3311
3312         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3313         fctrl &= (~IXGBE_FCTRL_UPE);
3314         if (dev->data->all_multicast == 1)
3315                 fctrl |= IXGBE_FCTRL_MPE;
3316         else
3317                 fctrl &= (~IXGBE_FCTRL_MPE);
3318         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3319 }
3320
3321 static void
3322 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3323 {
3324         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3325         uint32_t fctrl;
3326
3327         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3328         fctrl |= IXGBE_FCTRL_MPE;
3329         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3330 }
3331
3332 static void
3333 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3334 {
3335         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3336         uint32_t fctrl;
3337
3338         if (dev->data->promiscuous == 1)
3339                 return; /* must remain in all_multicast mode */
3340
3341         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3342         fctrl &= (~IXGBE_FCTRL_MPE);
3343         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3344 }
3345
3346 /**
3347  * It clears the interrupt causes and enables the interrupt.
3348  * It will be called once only during nic initialized.
3349  *
3350  * @param dev
3351  *  Pointer to struct rte_eth_dev.
3352  *
3353  * @return
3354  *  - On success, zero.
3355  *  - On failure, a negative value.
3356  */
3357 static int
3358 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3359 {
3360         struct ixgbe_interrupt *intr =
3361                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3362
3363         ixgbe_dev_link_status_print(dev);
3364         intr->mask |= IXGBE_EICR_LSC;
3365
3366         return 0;
3367 }
3368
3369 /**
3370  * It clears the interrupt causes and enables the interrupt.
3371  * It will be called once only during nic initialized.
3372  *
3373  * @param dev
3374  *  Pointer to struct rte_eth_dev.
3375  *
3376  * @return
3377  *  - On success, zero.
3378  *  - On failure, a negative value.
3379  */
3380 static int
3381 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3382 {
3383         struct ixgbe_interrupt *intr =
3384                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3385
3386         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3387
3388         return 0;
3389 }
3390
3391 /*
3392  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3393  *
3394  * @param dev
3395  *  Pointer to struct rte_eth_dev.
3396  *
3397  * @return
3398  *  - On success, zero.
3399  *  - On failure, a negative value.
3400  */
3401 static int
3402 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3403 {
3404         uint32_t eicr;
3405         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3406         struct ixgbe_interrupt *intr =
3407                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3408
3409         /* clear all cause mask */
3410         ixgbe_disable_intr(hw);
3411
3412         /* read-on-clear nic registers here */
3413         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3414         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3415
3416         intr->flags = 0;
3417
3418         /* set flag for async link update */
3419         if (eicr & IXGBE_EICR_LSC)
3420                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3421
3422         if (eicr & IXGBE_EICR_MAILBOX)
3423                 intr->flags |= IXGBE_FLAG_MAILBOX;
3424
3425         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3426             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3427             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3428                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3429
3430         return 0;
3431 }
3432
3433 /**
3434  * It gets and then prints the link status.
3435  *
3436  * @param dev
3437  *  Pointer to struct rte_eth_dev.
3438  *
3439  * @return
3440  *  - On success, zero.
3441  *  - On failure, a negative value.
3442  */
3443 static void
3444 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3445 {
3446         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3447         struct rte_eth_link link;
3448
3449         memset(&link, 0, sizeof(link));
3450         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3451         if (link.link_status) {
3452                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3453                                         (int)(dev->data->port_id),
3454                                         (unsigned)link.link_speed,
3455                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3456                                         "full-duplex" : "half-duplex");
3457         } else {
3458                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3459                                 (int)(dev->data->port_id));
3460         }
3461         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3462                                 pci_dev->addr.domain,
3463                                 pci_dev->addr.bus,
3464                                 pci_dev->addr.devid,
3465                                 pci_dev->addr.function);
3466 }
3467
3468 /*
3469  * It executes link_update after knowing an interrupt occurred.
3470  *
3471  * @param dev
3472  *  Pointer to struct rte_eth_dev.
3473  *
3474  * @return
3475  *  - On success, zero.
3476  *  - On failure, a negative value.
3477  */
3478 static int
3479 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3480                            struct rte_intr_handle *intr_handle)
3481 {
3482         struct ixgbe_interrupt *intr =
3483                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3484         int64_t timeout;
3485         struct rte_eth_link link;
3486         int intr_enable_delay = false;
3487         struct ixgbe_hw *hw =
3488                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3489
3490         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3491
3492         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3493                 ixgbe_pf_mbx_process(dev);
3494                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3495         }
3496
3497         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3498                 ixgbe_handle_lasi(hw);
3499                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3500         }
3501
3502         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3503                 /* get the link status before link update, for predicting later */
3504                 memset(&link, 0, sizeof(link));
3505                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3506
3507                 ixgbe_dev_link_update(dev, 0);
3508
3509                 /* likely to up */
3510                 if (!link.link_status)
3511                         /* handle it 1 sec later, wait it being stable */
3512                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3513                 /* likely to down */
3514                 else
3515                         /* handle it 4 sec later, wait it being stable */
3516                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3517
3518                 ixgbe_dev_link_status_print(dev);
3519
3520                 intr_enable_delay = true;
3521         }
3522
3523         if (intr_enable_delay) {
3524                 if (rte_eal_alarm_set(timeout * 1000,
3525                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3526                         PMD_DRV_LOG(ERR, "Error setting alarm");
3527         } else {
3528                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3529                 ixgbe_enable_intr(dev);
3530                 rte_intr_enable(intr_handle);
3531         }
3532
3533
3534         return 0;
3535 }
3536
3537 /**
3538  * Interrupt handler which shall be registered for alarm callback for delayed
3539  * handling specific interrupt to wait for the stable nic state. As the
3540  * NIC interrupt state is not stable for ixgbe after link is just down,
3541  * it needs to wait 4 seconds to get the stable status.
3542  *
3543  * @param handle
3544  *  Pointer to interrupt handle.
3545  * @param param
3546  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3547  *
3548  * @return
3549  *  void
3550  */
3551 static void
3552 ixgbe_dev_interrupt_delayed_handler(void *param)
3553 {
3554         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3555         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3556         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3557         struct ixgbe_interrupt *intr =
3558                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3559         struct ixgbe_hw *hw =
3560                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3561         uint32_t eicr;
3562
3563         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3564         if (eicr & IXGBE_EICR_MAILBOX)
3565                 ixgbe_pf_mbx_process(dev);
3566
3567         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3568                 ixgbe_handle_lasi(hw);
3569                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3570         }
3571
3572         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3573                 ixgbe_dev_link_update(dev, 0);
3574                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3575                 ixgbe_dev_link_status_print(dev);
3576                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3577         }
3578
3579         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3580         ixgbe_enable_intr(dev);
3581         rte_intr_enable(intr_handle);
3582 }
3583
3584 /**
3585  * Interrupt handler triggered by NIC  for handling
3586  * specific interrupt.
3587  *
3588  * @param handle
3589  *  Pointer to interrupt handle.
3590  * @param param
3591  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3592  *
3593  * @return
3594  *  void
3595  */
3596 static void
3597 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3598                             void *param)
3599 {
3600         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3601
3602         ixgbe_dev_interrupt_get_status(dev);
3603         ixgbe_dev_interrupt_action(dev, handle);
3604 }
3605
3606 static int
3607 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3608 {
3609         struct ixgbe_hw *hw;
3610
3611         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3612         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3613 }
3614
3615 static int
3616 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3617 {
3618         struct ixgbe_hw *hw;
3619
3620         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3621         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3622 }
3623
3624 static int
3625 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3626 {
3627         struct ixgbe_hw *hw;
3628         uint32_t mflcn_reg;
3629         uint32_t fccfg_reg;
3630         int rx_pause;
3631         int tx_pause;
3632
3633         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3634
3635         fc_conf->pause_time = hw->fc.pause_time;
3636         fc_conf->high_water = hw->fc.high_water[0];
3637         fc_conf->low_water = hw->fc.low_water[0];
3638         fc_conf->send_xon = hw->fc.send_xon;
3639         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3640
3641         /*
3642          * Return rx_pause status according to actual setting of
3643          * MFLCN register.
3644          */
3645         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3646         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3647                 rx_pause = 1;
3648         else
3649                 rx_pause = 0;
3650
3651         /*
3652          * Return tx_pause status according to actual setting of
3653          * FCCFG register.
3654          */
3655         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3656         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3657                 tx_pause = 1;
3658         else
3659                 tx_pause = 0;
3660
3661         if (rx_pause && tx_pause)
3662                 fc_conf->mode = RTE_FC_FULL;
3663         else if (rx_pause)
3664                 fc_conf->mode = RTE_FC_RX_PAUSE;
3665         else if (tx_pause)
3666                 fc_conf->mode = RTE_FC_TX_PAUSE;
3667         else
3668                 fc_conf->mode = RTE_FC_NONE;
3669
3670         return 0;
3671 }
3672
3673 static int
3674 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3675 {
3676         struct ixgbe_hw *hw;
3677         int err;
3678         uint32_t rx_buf_size;
3679         uint32_t max_high_water;
3680         uint32_t mflcn;
3681         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3682                 ixgbe_fc_none,
3683                 ixgbe_fc_rx_pause,
3684                 ixgbe_fc_tx_pause,
3685                 ixgbe_fc_full
3686         };
3687
3688         PMD_INIT_FUNC_TRACE();
3689
3690         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3691         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3692         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3693
3694         /*
3695          * At least reserve one Ethernet frame for watermark
3696          * high_water/low_water in kilo bytes for ixgbe
3697          */
3698         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3699         if ((fc_conf->high_water > max_high_water) ||
3700                 (fc_conf->high_water < fc_conf->low_water)) {
3701                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3702                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3703                 return -EINVAL;
3704         }
3705
3706         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3707         hw->fc.pause_time     = fc_conf->pause_time;
3708         hw->fc.high_water[0]  = fc_conf->high_water;
3709         hw->fc.low_water[0]   = fc_conf->low_water;
3710         hw->fc.send_xon       = fc_conf->send_xon;
3711         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3712
3713         err = ixgbe_fc_enable(hw);
3714
3715         /* Not negotiated is not an error case */
3716         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3717
3718                 /* check if we want to forward MAC frames - driver doesn't have native
3719                  * capability to do that, so we'll write the registers ourselves */
3720
3721                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3722
3723                 /* set or clear MFLCN.PMCF bit depending on configuration */
3724                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3725                         mflcn |= IXGBE_MFLCN_PMCF;
3726                 else
3727                         mflcn &= ~IXGBE_MFLCN_PMCF;
3728
3729                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3730                 IXGBE_WRITE_FLUSH(hw);
3731
3732                 return 0;
3733         }
3734
3735         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3736         return -EIO;
3737 }
3738
3739 /**
3740  *  ixgbe_pfc_enable_generic - Enable flow control
3741  *  @hw: pointer to hardware structure
3742  *  @tc_num: traffic class number
3743  *  Enable flow control according to the current settings.
3744  */
3745 static int
3746 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3747 {
3748         int ret_val = 0;
3749         uint32_t mflcn_reg, fccfg_reg;
3750         uint32_t reg;
3751         uint32_t fcrtl, fcrth;
3752         uint8_t i;
3753         uint8_t nb_rx_en;
3754
3755         /* Validate the water mark configuration */
3756         if (!hw->fc.pause_time) {
3757                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3758                 goto out;
3759         }
3760
3761         /* Low water mark of zero causes XOFF floods */
3762         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3763                  /* High/Low water can not be 0 */
3764                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3765                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3766                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3767                         goto out;
3768                 }
3769
3770                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3771                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3772                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3773                         goto out;
3774                 }
3775         }
3776         /* Negotiate the fc mode to use */
3777         ixgbe_fc_autoneg(hw);
3778
3779         /* Disable any previous flow control settings */
3780         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3781         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3782
3783         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3784         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3785
3786         switch (hw->fc.current_mode) {
3787         case ixgbe_fc_none:
3788                 /*
3789                  * If the count of enabled RX Priority Flow control >1,
3790                  * and the TX pause can not be disabled
3791                  */
3792                 nb_rx_en = 0;
3793                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3794                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3795                         if (reg & IXGBE_FCRTH_FCEN)
3796                                 nb_rx_en++;
3797                 }
3798                 if (nb_rx_en > 1)
3799                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3800                 break;
3801         case ixgbe_fc_rx_pause:
3802                 /*
3803                  * Rx Flow control is enabled and Tx Flow control is
3804                  * disabled by software override. Since there really
3805                  * isn't a way to advertise that we are capable of RX
3806                  * Pause ONLY, we will advertise that we support both
3807                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3808                  * disable the adapter's ability to send PAUSE frames.
3809                  */
3810                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3811                 /*
3812                  * If the count of enabled RX Priority Flow control >1,
3813                  * and the TX pause can not be disabled
3814                  */
3815                 nb_rx_en = 0;
3816                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3817                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3818                         if (reg & IXGBE_FCRTH_FCEN)
3819                                 nb_rx_en++;
3820                 }
3821                 if (nb_rx_en > 1)
3822                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3823                 break;
3824         case ixgbe_fc_tx_pause:
3825                 /*
3826                  * Tx Flow control is enabled, and Rx Flow control is
3827                  * disabled by software override.
3828                  */
3829                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3830                 break;
3831         case ixgbe_fc_full:
3832                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3833                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3834                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3835                 break;
3836         default:
3837                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3838                 ret_val = IXGBE_ERR_CONFIG;
3839                 goto out;
3840         }
3841
3842         /* Set 802.3x based flow control settings. */
3843         mflcn_reg |= IXGBE_MFLCN_DPF;
3844         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3845         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3846
3847         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3848         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3849                 hw->fc.high_water[tc_num]) {
3850                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3851                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3852                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3853         } else {
3854                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3855                 /*
3856                  * In order to prevent Tx hangs when the internal Tx
3857                  * switch is enabled we must set the high water mark
3858                  * to the maximum FCRTH value.  This allows the Tx
3859                  * switch to function even under heavy Rx workloads.
3860                  */
3861                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3862         }
3863         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3864
3865         /* Configure pause time (2 TCs per register) */
3866         reg = hw->fc.pause_time * 0x00010001;
3867         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3868                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3869
3870         /* Configure flow control refresh threshold value */
3871         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3872
3873 out:
3874         return ret_val;
3875 }
3876
3877 static int
3878 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3879 {
3880         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3881         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3882
3883         if (hw->mac.type != ixgbe_mac_82598EB) {
3884                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
3885         }
3886         return ret_val;
3887 }
3888
3889 static int
3890 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3891 {
3892         int err;
3893         uint32_t rx_buf_size;
3894         uint32_t max_high_water;
3895         uint8_t tc_num;
3896         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3897         struct ixgbe_hw *hw =
3898                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3899         struct ixgbe_dcb_config *dcb_config =
3900                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3901
3902         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3903                 ixgbe_fc_none,
3904                 ixgbe_fc_rx_pause,
3905                 ixgbe_fc_tx_pause,
3906                 ixgbe_fc_full
3907         };
3908
3909         PMD_INIT_FUNC_TRACE();
3910
3911         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3912         tc_num = map[pfc_conf->priority];
3913         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3914         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3915         /*
3916          * At least reserve one Ethernet frame for watermark
3917          * high_water/low_water in kilo bytes for ixgbe
3918          */
3919         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3920         if ((pfc_conf->fc.high_water > max_high_water) ||
3921             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3922                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3923                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3924                 return -EINVAL;
3925         }
3926
3927         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3928         hw->fc.pause_time = pfc_conf->fc.pause_time;
3929         hw->fc.send_xon = pfc_conf->fc.send_xon;
3930         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3931         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3932
3933         err = ixgbe_dcb_pfc_enable(dev, tc_num);
3934
3935         /* Not negotiated is not an error case */
3936         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3937                 return 0;
3938
3939         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3940         return -EIO;
3941 }
3942
3943 static int
3944 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3945                           struct rte_eth_rss_reta_entry64 *reta_conf,
3946                           uint16_t reta_size)
3947 {
3948         uint16_t i, sp_reta_size;
3949         uint8_t j, mask;
3950         uint32_t reta, r;
3951         uint16_t idx, shift;
3952         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3953         uint32_t reta_reg;
3954
3955         PMD_INIT_FUNC_TRACE();
3956
3957         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3958                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3959                         "NIC.");
3960                 return -ENOTSUP;
3961         }
3962
3963         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3964         if (reta_size != sp_reta_size) {
3965                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3966                         "(%d) doesn't match the number hardware can supported "
3967                         "(%d)\n", reta_size, sp_reta_size);
3968                 return -EINVAL;
3969         }
3970
3971         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3972                 idx = i / RTE_RETA_GROUP_SIZE;
3973                 shift = i % RTE_RETA_GROUP_SIZE;
3974                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3975                                                 IXGBE_4_BIT_MASK);
3976                 if (!mask)
3977                         continue;
3978                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3979                 if (mask == IXGBE_4_BIT_MASK)
3980                         r = 0;
3981                 else
3982                         r = IXGBE_READ_REG(hw, reta_reg);
3983                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3984                         if (mask & (0x1 << j))
3985                                 reta |= reta_conf[idx].reta[shift + j] <<
3986                                                         (CHAR_BIT * j);
3987                         else
3988                                 reta |= r & (IXGBE_8_BIT_MASK <<
3989                                                 (CHAR_BIT * j));
3990                 }
3991                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3992         }
3993
3994         return 0;
3995 }
3996
3997 static int
3998 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3999                          struct rte_eth_rss_reta_entry64 *reta_conf,
4000                          uint16_t reta_size)
4001 {
4002         uint16_t i, sp_reta_size;
4003         uint8_t j, mask;
4004         uint32_t reta;
4005         uint16_t idx, shift;
4006         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4007         uint32_t reta_reg;
4008
4009         PMD_INIT_FUNC_TRACE();
4010         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4011         if (reta_size != sp_reta_size) {
4012                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4013                         "(%d) doesn't match the number hardware can supported "
4014                         "(%d)\n", reta_size, sp_reta_size);
4015                 return -EINVAL;
4016         }
4017
4018         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4019                 idx = i / RTE_RETA_GROUP_SIZE;
4020                 shift = i % RTE_RETA_GROUP_SIZE;
4021                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4022                                                 IXGBE_4_BIT_MASK);
4023                 if (!mask)
4024                         continue;
4025
4026                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4027                 reta = IXGBE_READ_REG(hw, reta_reg);
4028                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4029                         if (mask & (0x1 << j))
4030                                 reta_conf[idx].reta[shift + j] =
4031                                         ((reta >> (CHAR_BIT * j)) &
4032                                                 IXGBE_8_BIT_MASK);
4033                 }
4034         }
4035
4036         return 0;
4037 }
4038
4039 static void
4040 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4041                                 uint32_t index, uint32_t pool)
4042 {
4043         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4044         uint32_t enable_addr = 1;
4045
4046         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4047 }
4048
4049 static void
4050 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4051 {
4052         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4053
4054         ixgbe_clear_rar(hw, index);
4055 }
4056
4057 static void
4058 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4059 {
4060         ixgbe_remove_rar(dev, 0);
4061
4062         ixgbe_add_rar(dev, addr, 0, 0);
4063 }
4064
4065 int
4066 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4067                 struct ether_addr *mac_addr)
4068 {
4069         struct ixgbe_hw *hw;
4070         struct ixgbe_vf_info *vfinfo;
4071         int rar_entry;
4072         uint8_t *new_mac = (uint8_t *)(mac_addr);
4073         struct rte_eth_dev *dev;
4074         struct rte_eth_dev_info dev_info;
4075
4076         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4077
4078         dev = &rte_eth_devices[port];
4079         rte_eth_dev_info_get(port, &dev_info);
4080
4081         if (vf >= dev_info.max_vfs)
4082                 return -EINVAL;
4083
4084         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4085         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4086         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4087
4088         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4089                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4090                                 ETHER_ADDR_LEN);
4091                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4092                                 IXGBE_RAH_AV);
4093         }
4094         return -EINVAL;
4095 }
4096
4097 static int
4098 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4099 {
4100         uint32_t hlreg0;
4101         uint32_t maxfrs;
4102         struct ixgbe_hw *hw;
4103         struct rte_eth_dev_info dev_info;
4104         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4105
4106         ixgbe_dev_info_get(dev, &dev_info);
4107
4108         /* check that mtu is within the allowed range */
4109         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4110                 return -EINVAL;
4111
4112         /* refuse mtu that requires the support of scattered packets when this
4113          * feature has not been enabled before.
4114          */
4115         if (!dev->data->scattered_rx &&
4116             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4117              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4118                 return -EINVAL;
4119
4120         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4121         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4122
4123         /* switch to jumbo mode if needed */
4124         if (frame_size > ETHER_MAX_LEN) {
4125                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4126                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4127         } else {
4128                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4129                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4130         }
4131         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4132
4133         /* update max frame size */
4134         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4135
4136         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4137         maxfrs &= 0x0000FFFF;
4138         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4139         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4140
4141         return 0;
4142 }
4143
4144 /*
4145  * Virtual Function operations
4146  */
4147 static void
4148 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4149 {
4150         PMD_INIT_FUNC_TRACE();
4151
4152         /* Clear interrupt mask to stop from interrupts being generated */
4153         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4154
4155         IXGBE_WRITE_FLUSH(hw);
4156 }
4157
4158 static void
4159 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4160 {
4161         PMD_INIT_FUNC_TRACE();
4162
4163         /* VF enable interrupt autoclean */
4164         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4165         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4166         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4167
4168         IXGBE_WRITE_FLUSH(hw);
4169 }
4170
4171 static int
4172 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4173 {
4174         struct rte_eth_conf *conf = &dev->data->dev_conf;
4175         struct ixgbe_adapter *adapter =
4176                         (struct ixgbe_adapter *)dev->data->dev_private;
4177
4178         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4179                      dev->data->port_id);
4180
4181         /*
4182          * VF has no ability to enable/disable HW CRC
4183          * Keep the persistent behavior the same as Host PF
4184          */
4185 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4186         if (!conf->rxmode.hw_strip_crc) {
4187                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4188                 conf->rxmode.hw_strip_crc = 1;
4189         }
4190 #else
4191         if (conf->rxmode.hw_strip_crc) {
4192                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4193                 conf->rxmode.hw_strip_crc = 0;
4194         }
4195 #endif
4196
4197         /*
4198          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4199          * allocation or vector Rx preconditions we will reset it.
4200          */
4201         adapter->rx_bulk_alloc_allowed = true;
4202         adapter->rx_vec_allowed = true;
4203
4204         return 0;
4205 }
4206
4207 static int
4208 ixgbevf_dev_start(struct rte_eth_dev *dev)
4209 {
4210         struct ixgbe_hw *hw =
4211                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4212         uint32_t intr_vector = 0;
4213         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4214         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4215
4216         int err, mask = 0;
4217
4218         PMD_INIT_FUNC_TRACE();
4219
4220         hw->mac.ops.reset_hw(hw);
4221         hw->mac.get_link_status = true;
4222
4223         /* negotiate mailbox API version to use with the PF. */
4224         ixgbevf_negotiate_api(hw);
4225
4226         ixgbevf_dev_tx_init(dev);
4227
4228         /* This can fail when allocating mbufs for descriptor rings */
4229         err = ixgbevf_dev_rx_init(dev);
4230         if (err) {
4231                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4232                 ixgbe_dev_clear_queues(dev);
4233                 return err;
4234         }
4235
4236         /* Set vfta */
4237         ixgbevf_set_vfta_all(dev, 1);
4238
4239         /* Set HW strip */
4240         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4241                 ETH_VLAN_EXTEND_MASK;
4242         ixgbevf_vlan_offload_set(dev, mask);
4243
4244         ixgbevf_dev_rxtx_start(dev);
4245
4246         /* check and configure queue intr-vector mapping */
4247         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4248                 intr_vector = dev->data->nb_rx_queues;
4249                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4250                         return -1;
4251         }
4252
4253         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4254                 intr_handle->intr_vec =
4255                         rte_zmalloc("intr_vec",
4256                                     dev->data->nb_rx_queues * sizeof(int), 0);
4257                 if (intr_handle->intr_vec == NULL) {
4258                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4259                                      " intr_vec\n", dev->data->nb_rx_queues);
4260                         return -ENOMEM;
4261                 }
4262         }
4263         ixgbevf_configure_msix(dev);
4264
4265         rte_intr_enable(intr_handle);
4266
4267         /* Re-enable interrupt for VF */
4268         ixgbevf_intr_enable(hw);
4269
4270         return 0;
4271 }
4272
4273 static void
4274 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4275 {
4276         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4277         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4278         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4279
4280         PMD_INIT_FUNC_TRACE();
4281
4282         ixgbevf_intr_disable(hw);
4283
4284         hw->adapter_stopped = 1;
4285         ixgbe_stop_adapter(hw);
4286
4287         /*
4288           * Clear what we set, but we still keep shadow_vfta to
4289           * restore after device starts
4290           */
4291         ixgbevf_set_vfta_all(dev, 0);
4292
4293         /* Clear stored conf */
4294         dev->data->scattered_rx = 0;
4295
4296         ixgbe_dev_clear_queues(dev);
4297
4298         /* Clean datapath event and queue/vec mapping */
4299         rte_intr_efd_disable(intr_handle);
4300         if (intr_handle->intr_vec != NULL) {
4301                 rte_free(intr_handle->intr_vec);
4302                 intr_handle->intr_vec = NULL;
4303         }
4304 }
4305
4306 static void
4307 ixgbevf_dev_close(struct rte_eth_dev *dev)
4308 {
4309         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4310
4311         PMD_INIT_FUNC_TRACE();
4312
4313         ixgbe_reset_hw(hw);
4314
4315         ixgbevf_dev_stop(dev);
4316
4317         ixgbe_dev_free_queues(dev);
4318
4319         /**
4320          * Remove the VF MAC address ro ensure
4321          * that the VF traffic goes to the PF
4322          * after stop, close and detach of the VF
4323          **/
4324         ixgbevf_remove_mac_addr(dev, 0);
4325 }
4326
4327 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4328 {
4329         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4330         struct ixgbe_vfta *shadow_vfta =
4331                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4332         int i = 0, j = 0, vfta = 0, mask = 1;
4333
4334         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4335                 vfta = shadow_vfta->vfta[i];
4336                 if (vfta) {
4337                         mask = 1;
4338                         for (j = 0; j < 32; j++) {
4339                                 if (vfta & mask)
4340                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4341                                                        on, false);
4342                                 mask <<= 1;
4343                         }
4344                 }
4345         }
4346
4347 }
4348
4349 static int
4350 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4351 {
4352         struct ixgbe_hw *hw =
4353                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4354         struct ixgbe_vfta *shadow_vfta =
4355                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4356         uint32_t vid_idx = 0;
4357         uint32_t vid_bit = 0;
4358         int ret = 0;
4359
4360         PMD_INIT_FUNC_TRACE();
4361
4362         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4363         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4364         if (ret) {
4365                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4366                 return ret;
4367         }
4368         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4369         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4370
4371         /* Save what we set and retore it after device reset */
4372         if (on)
4373                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4374         else
4375                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4376
4377         return 0;
4378 }
4379
4380 static void
4381 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4382 {
4383         struct ixgbe_hw *hw =
4384                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4385         uint32_t ctrl;
4386
4387         PMD_INIT_FUNC_TRACE();
4388
4389         if (queue >= hw->mac.max_rx_queues)
4390                 return;
4391
4392         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4393         if (on)
4394                 ctrl |= IXGBE_RXDCTL_VME;
4395         else
4396                 ctrl &= ~IXGBE_RXDCTL_VME;
4397         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4398
4399         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4400 }
4401
4402 static void
4403 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4404 {
4405         struct ixgbe_hw *hw =
4406                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4407         uint16_t i;
4408         int on = 0;
4409
4410         /* VF function only support hw strip feature, others are not support */
4411         if (mask & ETH_VLAN_STRIP_MASK) {
4412                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4413
4414                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4415                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4416         }
4417 }
4418
4419 static int
4420 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4421 {
4422         uint32_t reg_val;
4423
4424         /* we only need to do this if VMDq is enabled */
4425         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4426         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4427                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4428                 return -1;
4429         }
4430
4431         return 0;
4432 }
4433
4434 static uint32_t
4435 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4436 {
4437         uint32_t vector = 0;
4438
4439         switch (hw->mac.mc_filter_type) {
4440         case 0:   /* use bits [47:36] of the address */
4441                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4442                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4443                 break;
4444         case 1:   /* use bits [46:35] of the address */
4445                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4446                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4447                 break;
4448         case 2:   /* use bits [45:34] of the address */
4449                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4450                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4451                 break;
4452         case 3:   /* use bits [43:32] of the address */
4453                 vector = ((uc_addr->addr_bytes[4]) |
4454                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4455                 break;
4456         default:  /* Invalid mc_filter_type */
4457                 break;
4458         }
4459
4460         /* vector can only be 12-bits or boundary will be exceeded */
4461         vector &= 0xFFF;
4462         return vector;
4463 }
4464
4465 static int
4466 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4467                         uint8_t on)
4468 {
4469         uint32_t vector;
4470         uint32_t uta_idx;
4471         uint32_t reg_val;
4472         uint32_t uta_shift;
4473         uint32_t rc;
4474         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4475         const uint32_t ixgbe_uta_bit_shift = 5;
4476         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4477         const uint32_t bit1 = 0x1;
4478
4479         struct ixgbe_hw *hw =
4480                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4481         struct ixgbe_uta_info *uta_info =
4482                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4483
4484         /* The UTA table only exists on 82599 hardware and newer */
4485         if (hw->mac.type < ixgbe_mac_82599EB)
4486                 return -ENOTSUP;
4487
4488         vector = ixgbe_uta_vector(hw, mac_addr);
4489         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4490         uta_shift = vector & ixgbe_uta_bit_mask;
4491
4492         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4493         if (rc == on)
4494                 return 0;
4495
4496         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4497         if (on) {
4498                 uta_info->uta_in_use++;
4499                 reg_val |= (bit1 << uta_shift);
4500                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4501         } else {
4502                 uta_info->uta_in_use--;
4503                 reg_val &= ~(bit1 << uta_shift);
4504                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4505         }
4506
4507         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4508
4509         if (uta_info->uta_in_use > 0)
4510                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4511                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4512         else
4513                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4514
4515         return 0;
4516 }
4517
4518 static int
4519 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4520 {
4521         int i;
4522         struct ixgbe_hw *hw =
4523                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4524         struct ixgbe_uta_info *uta_info =
4525                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4526
4527         /* The UTA table only exists on 82599 hardware and newer */
4528         if (hw->mac.type < ixgbe_mac_82599EB)
4529                 return -ENOTSUP;
4530
4531         if (on) {
4532                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4533                         uta_info->uta_shadow[i] = ~0;
4534                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4535                 }
4536         } else {
4537                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4538                         uta_info->uta_shadow[i] = 0;
4539                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4540                 }
4541         }
4542         return 0;
4543
4544 }
4545
4546 uint32_t
4547 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4548 {
4549         uint32_t new_val = orig_val;
4550
4551         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4552                 new_val |= IXGBE_VMOLR_AUPE;
4553         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4554                 new_val |= IXGBE_VMOLR_ROMPE;
4555         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4556                 new_val |= IXGBE_VMOLR_ROPE;
4557         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4558                 new_val |= IXGBE_VMOLR_BAM;
4559         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4560                 new_val |= IXGBE_VMOLR_MPE;
4561
4562         return new_val;
4563 }
4564
4565 static int
4566 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4567                                uint16_t rx_mask, uint8_t on)
4568 {
4569         int val = 0;
4570
4571         struct ixgbe_hw *hw =
4572                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4573         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4574
4575         if (hw->mac.type == ixgbe_mac_82598EB) {
4576                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4577                              " on 82599 hardware and newer");
4578                 return -ENOTSUP;
4579         }
4580         if (ixgbe_vmdq_mode_check(hw) < 0)
4581                 return -ENOTSUP;
4582
4583         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4584
4585         if (on)
4586                 vmolr |= val;
4587         else
4588                 vmolr &= ~val;
4589
4590         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4591
4592         return 0;
4593 }
4594
4595 static int
4596 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4597 {
4598         uint32_t reg, addr;
4599         uint32_t val;
4600         const uint8_t bit1 = 0x1;
4601
4602         struct ixgbe_hw *hw =
4603                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4604
4605         if (ixgbe_vmdq_mode_check(hw) < 0)
4606                 return -ENOTSUP;
4607
4608         if (pool >= ETH_64_POOLS)
4609                 return -EINVAL;
4610
4611         /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4612         if (pool >= 32) {
4613                 addr = IXGBE_VFRE(1);
4614                 val = bit1 << (pool - 32);
4615         } else {
4616                 addr = IXGBE_VFRE(0);
4617                 val = bit1 << pool;
4618         }
4619
4620         reg = IXGBE_READ_REG(hw, addr);
4621
4622         if (on)
4623                 reg |= val;
4624         else
4625                 reg &= ~val;
4626
4627         IXGBE_WRITE_REG(hw, addr, reg);
4628
4629         return 0;
4630 }
4631
4632 static int
4633 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4634 {
4635         uint32_t reg, addr;
4636         uint32_t val;
4637         const uint8_t bit1 = 0x1;
4638
4639         struct ixgbe_hw *hw =
4640                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4641
4642         if (ixgbe_vmdq_mode_check(hw) < 0)
4643                 return -ENOTSUP;
4644
4645         if (pool >= ETH_64_POOLS)
4646                 return -EINVAL;
4647
4648         /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4649         if (pool >= 32) {
4650                 addr = IXGBE_VFTE(1);
4651                 val = bit1 << (pool - 32);
4652         } else {
4653                 addr = IXGBE_VFTE(0);
4654                 val = bit1 << pool;
4655         }
4656
4657         reg = IXGBE_READ_REG(hw, addr);
4658
4659         if (on)
4660                 reg |= val;
4661         else
4662                 reg &= ~val;
4663
4664         IXGBE_WRITE_REG(hw, addr, reg);
4665
4666         return 0;
4667 }
4668
4669 static int
4670 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4671                         uint64_t pool_mask, uint8_t vlan_on)
4672 {
4673         int ret = 0;
4674         uint16_t pool_idx;
4675         struct ixgbe_hw *hw =
4676                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4677
4678         if (ixgbe_vmdq_mode_check(hw) < 0)
4679                 return -ENOTSUP;
4680         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4681                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4682                         ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx,
4683                                                    vlan_on, false);
4684                         if (ret < 0)
4685                                 return ret;
4686                 }
4687         }
4688
4689         return ret;
4690 }
4691
4692 int
4693 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4694 {
4695         struct ixgbe_hw *hw;
4696         struct ixgbe_mac_info *mac;
4697         struct rte_eth_dev *dev;
4698         struct rte_eth_dev_info dev_info;
4699
4700         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4701
4702         dev = &rte_eth_devices[port];
4703         rte_eth_dev_info_get(port, &dev_info);
4704
4705         if (vf >= dev_info.max_vfs)
4706                 return -EINVAL;
4707
4708         if (on > 1)
4709                 return -EINVAL;
4710
4711         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4712         mac = &hw->mac;
4713
4714         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4715
4716         return 0;
4717 }
4718
4719 int
4720 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4721 {
4722         struct ixgbe_hw *hw;
4723         struct ixgbe_mac_info *mac;
4724         struct rte_eth_dev *dev;
4725         struct rte_eth_dev_info dev_info;
4726
4727         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4728
4729         dev = &rte_eth_devices[port];
4730         rte_eth_dev_info_get(port, &dev_info);
4731
4732         if (vf >= dev_info.max_vfs)
4733                 return -EINVAL;
4734
4735         if (on > 1)
4736                 return -EINVAL;
4737
4738         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4739         mac = &hw->mac;
4740         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4741
4742         return 0;
4743 }
4744
4745 int
4746 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4747 {
4748         struct ixgbe_hw *hw;
4749         uint32_t ctrl;
4750         struct rte_eth_dev *dev;
4751         struct rte_eth_dev_info dev_info;
4752
4753         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4754
4755         dev = &rte_eth_devices[port];
4756         rte_eth_dev_info_get(port, &dev_info);
4757
4758         if (vf >= dev_info.max_vfs)
4759                 return -EINVAL;
4760
4761         if (vlan_id > 4095)
4762                 return -EINVAL;
4763
4764         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4765         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4766         if (vlan_id) {
4767                 ctrl = vlan_id;
4768                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4769         } else {
4770                 ctrl = 0;
4771         }
4772
4773         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4774
4775         return 0;
4776 }
4777
4778 int
4779 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4780 {
4781         struct ixgbe_hw *hw;
4782         uint32_t ctrl;
4783         struct rte_eth_dev *dev;
4784
4785         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4786
4787         dev = &rte_eth_devices[port];
4788
4789         if (on > 1)
4790                 return -EINVAL;
4791
4792         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4793         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4794         /* enable or disable VMDQ loopback */
4795         if (on)
4796                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
4797         else
4798                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4799
4800         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
4801
4802         return 0;
4803 }
4804
4805 int
4806 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
4807 {
4808         struct ixgbe_hw *hw;
4809         uint32_t reg_value;
4810         int i;
4811         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
4812         struct rte_eth_dev *dev;
4813
4814         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4815
4816         dev = &rte_eth_devices[port];
4817
4818         if (on > 1)
4819                 return -EINVAL;
4820
4821         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4822         for (i = 0; i <= num_queues; i++) {
4823                 reg_value = IXGBE_QDE_WRITE |
4824                                 (i << IXGBE_QDE_IDX_SHIFT) |
4825                                 (on & IXGBE_QDE_ENABLE);
4826                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
4827         }
4828
4829         return 0;
4830 }
4831
4832 int
4833 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
4834 {
4835         struct ixgbe_hw *hw;
4836         uint32_t reg_value;
4837         struct rte_eth_dev *dev;
4838         struct rte_eth_dev_info dev_info;
4839
4840         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4841
4842         dev = &rte_eth_devices[port];
4843         rte_eth_dev_info_get(port, &dev_info);
4844
4845         /* only support VF's 0 to 63 */
4846         if ((vf >= dev_info.max_vfs) || (vf > 63))
4847                 return -EINVAL;
4848
4849         if (on > 1)
4850                 return -EINVAL;
4851
4852         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4853         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
4854         if (on)
4855                 reg_value |= IXGBE_SRRCTL_DROP_EN;
4856         else
4857                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
4858
4859         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
4860
4861         return 0;
4862 }
4863
4864 int
4865 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
4866 {
4867         struct rte_eth_dev *dev;
4868         struct rte_eth_dev_info dev_info;
4869         uint16_t queues_per_pool;
4870         uint32_t q;
4871
4872         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4873
4874         dev = &rte_eth_devices[port];
4875         rte_eth_dev_info_get(port, &dev_info);
4876
4877         if (vf >= dev_info.max_vfs)
4878                 return -EINVAL;
4879
4880         if (on > 1)
4881                 return -EINVAL;
4882
4883         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
4884
4885         /* The PF has 128 queue pairs and in SRIOV configuration
4886          * those queues will be assigned to VF's, so RXDCTL
4887          * registers will be dealing with queues which will be
4888          * assigned to VF's.
4889          * Let's say we have SRIOV configured with 31 VF's then the
4890          * first 124 queues 0-123 will be allocated to VF's and only
4891          * the last 4 queues 123-127 will be assigned to the PF.
4892          */
4893
4894         queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
4895
4896         for (q = 0; q < queues_per_pool; q++)
4897                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
4898                                 q + vf * queues_per_pool, on);
4899         return 0;
4900 }
4901
4902 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4903 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4904 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4905 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4906 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4907         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4908         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4909
4910 static int
4911 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4912                         struct rte_eth_mirror_conf *mirror_conf,
4913                         uint8_t rule_id, uint8_t on)
4914 {
4915         uint32_t mr_ctl, vlvf;
4916         uint32_t mp_lsb = 0;
4917         uint32_t mv_msb = 0;
4918         uint32_t mv_lsb = 0;
4919         uint32_t mp_msb = 0;
4920         uint8_t i = 0;
4921         int reg_index = 0;
4922         uint64_t vlan_mask = 0;
4923
4924         const uint8_t pool_mask_offset = 32;
4925         const uint8_t vlan_mask_offset = 32;
4926         const uint8_t dst_pool_offset = 8;
4927         const uint8_t rule_mr_offset  = 4;
4928         const uint8_t mirror_rule_mask = 0x0F;
4929
4930         struct ixgbe_mirror_info *mr_info =
4931                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4932         struct ixgbe_hw *hw =
4933                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4934         uint8_t mirror_type = 0;
4935
4936         if (ixgbe_vmdq_mode_check(hw) < 0)
4937                 return -ENOTSUP;
4938
4939         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4940                 return -EINVAL;
4941
4942         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4943                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4944                         mirror_conf->rule_type);
4945                 return -EINVAL;
4946         }
4947
4948         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4949                 mirror_type |= IXGBE_MRCTL_VLME;
4950                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4951                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
4952                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4953                                 /* search vlan id related pool vlan filter index */
4954                                 reg_index = ixgbe_find_vlvf_slot(hw,
4955                                                  mirror_conf->vlan.vlan_id[i],
4956                                                  false);
4957                                 if (reg_index < 0)
4958                                         return -EINVAL;
4959                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4960                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4961                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4962                                       mirror_conf->vlan.vlan_id[i]))
4963                                         vlan_mask |= (1ULL << reg_index);
4964                                 else
4965                                         return -EINVAL;
4966                         }
4967                 }
4968
4969                 if (on) {
4970                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4971                         mv_msb = vlan_mask >> vlan_mask_offset;
4972
4973                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4974                                                 mirror_conf->vlan.vlan_mask;
4975                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4976                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4977                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4978                                                 mirror_conf->vlan.vlan_id[i];
4979                         }
4980                 } else {
4981                         mv_lsb = 0;
4982                         mv_msb = 0;
4983                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4984                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4985                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4986                 }
4987         }
4988
4989         /*
4990          * if enable pool mirror, write related pool mask register,if disable
4991          * pool mirror, clear PFMRVM register
4992          */
4993         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4994                 mirror_type |= IXGBE_MRCTL_VPME;
4995                 if (on) {
4996                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4997                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4998                         mr_info->mr_conf[rule_id].pool_mask =
4999                                         mirror_conf->pool_mask;
5000
5001                 } else {
5002                         mp_lsb = 0;
5003                         mp_msb = 0;
5004                         mr_info->mr_conf[rule_id].pool_mask = 0;
5005                 }
5006         }
5007         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5008                 mirror_type |= IXGBE_MRCTL_UPME;
5009         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5010                 mirror_type |= IXGBE_MRCTL_DPME;
5011
5012         /* read  mirror control register and recalculate it */
5013         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5014
5015         if (on) {
5016                 mr_ctl |= mirror_type;
5017                 mr_ctl &= mirror_rule_mask;
5018                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5019         } else
5020                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5021
5022         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5023         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5024
5025         /* write mirrror control  register */
5026         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5027
5028         /* write pool mirrror control  register */
5029         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5030                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5031                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5032                                 mp_msb);
5033         }
5034         /* write VLAN mirrror control  register */
5035         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5036                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5037                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5038                                 mv_msb);
5039         }
5040
5041         return 0;
5042 }
5043
5044 static int
5045 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5046 {
5047         int mr_ctl = 0;
5048         uint32_t lsb_val = 0;
5049         uint32_t msb_val = 0;
5050         const uint8_t rule_mr_offset = 4;
5051
5052         struct ixgbe_hw *hw =
5053                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5054         struct ixgbe_mirror_info *mr_info =
5055                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5056
5057         if (ixgbe_vmdq_mode_check(hw) < 0)
5058                 return -ENOTSUP;
5059
5060         memset(&mr_info->mr_conf[rule_id], 0,
5061                 sizeof(struct rte_eth_mirror_conf));
5062
5063         /* clear PFVMCTL register */
5064         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5065
5066         /* clear pool mask register */
5067         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5068         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5069
5070         /* clear vlan mask register */
5071         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5072         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5073
5074         return 0;
5075 }
5076
5077 static int
5078 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5079 {
5080         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5081         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5082         uint32_t mask;
5083         struct ixgbe_hw *hw =
5084                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5085
5086         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5087         mask |= (1 << IXGBE_MISC_VEC_ID);
5088         RTE_SET_USED(queue_id);
5089         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5090
5091         rte_intr_enable(intr_handle);
5092
5093         return 0;
5094 }
5095
5096 static int
5097 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5098 {
5099         uint32_t mask;
5100         struct ixgbe_hw *hw =
5101                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5102
5103         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5104         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5105         RTE_SET_USED(queue_id);
5106         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5107
5108         return 0;
5109 }
5110
5111 static int
5112 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5113 {
5114         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5115         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5116         uint32_t mask;
5117         struct ixgbe_hw *hw =
5118                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5119         struct ixgbe_interrupt *intr =
5120                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5121
5122         if (queue_id < 16) {
5123                 ixgbe_disable_intr(hw);
5124                 intr->mask |= (1 << queue_id);
5125                 ixgbe_enable_intr(dev);
5126         } else if (queue_id < 32) {
5127                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5128                 mask &= (1 << queue_id);
5129                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5130         } else if (queue_id < 64) {
5131                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5132                 mask &= (1 << (queue_id - 32));
5133                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5134         }
5135         rte_intr_enable(intr_handle);
5136
5137         return 0;
5138 }
5139
5140 static int
5141 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5142 {
5143         uint32_t mask;
5144         struct ixgbe_hw *hw =
5145                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5146         struct ixgbe_interrupt *intr =
5147                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5148
5149         if (queue_id < 16) {
5150                 ixgbe_disable_intr(hw);
5151                 intr->mask &= ~(1 << queue_id);
5152                 ixgbe_enable_intr(dev);
5153         } else if (queue_id < 32) {
5154                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5155                 mask &= ~(1 << queue_id);
5156                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5157         } else if (queue_id < 64) {
5158                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5159                 mask &= ~(1 << (queue_id - 32));
5160                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5161         }
5162
5163         return 0;
5164 }
5165
5166 static void
5167 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5168                      uint8_t queue, uint8_t msix_vector)
5169 {
5170         uint32_t tmp, idx;
5171
5172         if (direction == -1) {
5173                 /* other causes */
5174                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5175                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5176                 tmp &= ~0xFF;
5177                 tmp |= msix_vector;
5178                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5179         } else {
5180                 /* rx or tx cause */
5181                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5182                 idx = ((16 * (queue & 1)) + (8 * direction));
5183                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5184                 tmp &= ~(0xFF << idx);
5185                 tmp |= (msix_vector << idx);
5186                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5187         }
5188 }
5189
5190 /**
5191  * set the IVAR registers, mapping interrupt causes to vectors
5192  * @param hw
5193  *  pointer to ixgbe_hw struct
5194  * @direction
5195  *  0 for Rx, 1 for Tx, -1 for other causes
5196  * @queue
5197  *  queue to map the corresponding interrupt to
5198  * @msix_vector
5199  *  the vector to map to the corresponding queue
5200  */
5201 static void
5202 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5203                    uint8_t queue, uint8_t msix_vector)
5204 {
5205         uint32_t tmp, idx;
5206
5207         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5208         if (hw->mac.type == ixgbe_mac_82598EB) {
5209                 if (direction == -1)
5210                         direction = 0;
5211                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5212                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5213                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5214                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5215                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5216         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5217                         (hw->mac.type == ixgbe_mac_X540)) {
5218                 if (direction == -1) {
5219                         /* other causes */
5220                         idx = ((queue & 1) * 8);
5221                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5222                         tmp &= ~(0xFF << idx);
5223                         tmp |= (msix_vector << idx);
5224                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5225                 } else {
5226                         /* rx or tx causes */
5227                         idx = ((16 * (queue & 1)) + (8 * direction));
5228                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5229                         tmp &= ~(0xFF << idx);
5230                         tmp |= (msix_vector << idx);
5231                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5232                 }
5233         }
5234 }
5235
5236 static void
5237 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5238 {
5239         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5240         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5241         struct ixgbe_hw *hw =
5242                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5243         uint32_t q_idx;
5244         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5245
5246         /* Configure VF other cause ivar */
5247         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5248
5249         /* won't configure msix register if no mapping is done
5250          * between intr vector and event fd.
5251          */
5252         if (!rte_intr_dp_is_en(intr_handle))
5253                 return;
5254
5255         /* Configure all RX queues of VF */
5256         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5257                 /* Force all queue use vector 0,
5258                  * as IXGBE_VF_MAXMSIVECOTR = 1
5259                  */
5260                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5261                 intr_handle->intr_vec[q_idx] = vector_idx;
5262         }
5263 }
5264
5265 /**
5266  * Sets up the hardware to properly generate MSI-X interrupts
5267  * @hw
5268  *  board private structure
5269  */
5270 static void
5271 ixgbe_configure_msix(struct rte_eth_dev *dev)
5272 {
5273         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5274         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5275         struct ixgbe_hw *hw =
5276                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5277         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5278         uint32_t vec = IXGBE_MISC_VEC_ID;
5279         uint32_t mask;
5280         uint32_t gpie;
5281
5282         /* won't configure msix register if no mapping is done
5283          * between intr vector and event fd
5284          */
5285         if (!rte_intr_dp_is_en(intr_handle))
5286                 return;
5287
5288         if (rte_intr_allow_others(intr_handle))
5289                 vec = base = IXGBE_RX_VEC_START;
5290
5291         /* setup GPIE for MSI-x mode */
5292         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5293         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5294                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5295         /* auto clearing and auto setting corresponding bits in EIMS
5296          * when MSI-X interrupt is triggered
5297          */
5298         if (hw->mac.type == ixgbe_mac_82598EB) {
5299                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5300         } else {
5301                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5302                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5303         }
5304         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5305
5306         /* Populate the IVAR table and set the ITR values to the
5307          * corresponding register.
5308          */
5309         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5310              queue_id++) {
5311                 /* by default, 1:1 mapping */
5312                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5313                 intr_handle->intr_vec[queue_id] = vec;
5314                 if (vec < base + intr_handle->nb_efd - 1)
5315                         vec++;
5316         }
5317
5318         switch (hw->mac.type) {
5319         case ixgbe_mac_82598EB:
5320                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5321                                    IXGBE_MISC_VEC_ID);
5322                 break;
5323         case ixgbe_mac_82599EB:
5324         case ixgbe_mac_X540:
5325                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5326                 break;
5327         default:
5328                 break;
5329         }
5330         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5331                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5332
5333         /* set up to autoclear timer, and the vectors */
5334         mask = IXGBE_EIMS_ENABLE_MASK;
5335         mask &= ~(IXGBE_EIMS_OTHER |
5336                   IXGBE_EIMS_MAILBOX |
5337                   IXGBE_EIMS_LSC);
5338
5339         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5340 }
5341
5342 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5343         uint16_t queue_idx, uint16_t tx_rate)
5344 {
5345         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5346         uint32_t rf_dec, rf_int;
5347         uint32_t bcnrc_val;
5348         uint16_t link_speed = dev->data->dev_link.link_speed;
5349
5350         if (queue_idx >= hw->mac.max_tx_queues)
5351                 return -EINVAL;
5352
5353         if (tx_rate != 0) {
5354                 /* Calculate the rate factor values to set */
5355                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5356                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5357                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5358
5359                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5360                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5361                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5362                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5363         } else {
5364                 bcnrc_val = 0;
5365         }
5366
5367         /*
5368          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5369          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5370          * set as 0x4.
5371          */
5372         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5373                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5374                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5375                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5376                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5377         else
5378                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5379                         IXGBE_MMW_SIZE_DEFAULT);
5380
5381         /* Set RTTBCNRC of queue X */
5382         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5383         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5384         IXGBE_WRITE_FLUSH(hw);
5385
5386         return 0;
5387 }
5388
5389 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5390         uint16_t tx_rate, uint64_t q_msk)
5391 {
5392         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5393         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5394         struct ixgbe_vf_info *vfinfo =
5395                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5396         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5397         uint32_t queue_stride =
5398                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5399         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5400         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5401         uint16_t total_rate = 0;
5402
5403         if (queue_end >= hw->mac.max_tx_queues)
5404                 return -EINVAL;
5405
5406         if (vfinfo != NULL) {
5407                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5408                         if (vf_idx == vf)
5409                                 continue;
5410                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5411                                 idx++)
5412                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5413                 }
5414         } else
5415                 return -EINVAL;
5416
5417         /* Store tx_rate for this vf. */
5418         for (idx = 0; idx < nb_q_per_pool; idx++) {
5419                 if (((uint64_t)0x1 << idx) & q_msk) {
5420                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5421                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5422                         total_rate += tx_rate;
5423                 }
5424         }
5425
5426         if (total_rate > dev->data->dev_link.link_speed) {
5427                 /*
5428                  * Reset stored TX rate of the VF if it causes exceed
5429                  * link speed.
5430                  */
5431                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5432                 return -EINVAL;
5433         }
5434
5435         /* Set RTTBCNRC of each queue/pool for vf X  */
5436         for (; queue_idx <= queue_end; queue_idx++) {
5437                 if (0x1 & q_msk)
5438                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5439                 q_msk = q_msk >> 1;
5440         }
5441
5442         return 0;
5443 }
5444
5445 static void
5446 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5447                      __attribute__((unused)) uint32_t index,
5448                      __attribute__((unused)) uint32_t pool)
5449 {
5450         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5451         int diag;
5452
5453         /*
5454          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5455          * operation. Trap this case to avoid exhausting the [very limited]
5456          * set of PF resources used to store VF MAC addresses.
5457          */
5458         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5459                 return;
5460         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5461         if (diag == 0)
5462                 return;
5463         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5464 }
5465
5466 static void
5467 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5468 {
5469         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5470         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5471         struct ether_addr *mac_addr;
5472         uint32_t i;
5473         int diag;
5474
5475         /*
5476          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5477          * not support the deletion of a given MAC address.
5478          * Instead, it imposes to delete all MAC addresses, then to add again
5479          * all MAC addresses with the exception of the one to be deleted.
5480          */
5481         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5482
5483         /*
5484          * Add again all MAC addresses, with the exception of the deleted one
5485          * and of the permanent MAC address.
5486          */
5487         for (i = 0, mac_addr = dev->data->mac_addrs;
5488              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5489                 /* Skip the deleted MAC address */
5490                 if (i == index)
5491                         continue;
5492                 /* Skip NULL MAC addresses */
5493                 if (is_zero_ether_addr(mac_addr))
5494                         continue;
5495                 /* Skip the permanent MAC address */
5496                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5497                         continue;
5498                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5499                 if (diag != 0)
5500                         PMD_DRV_LOG(ERR,
5501                                     "Adding again MAC address "
5502                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5503                                     "diag=%d",
5504                                     mac_addr->addr_bytes[0],
5505                                     mac_addr->addr_bytes[1],
5506                                     mac_addr->addr_bytes[2],
5507                                     mac_addr->addr_bytes[3],
5508                                     mac_addr->addr_bytes[4],
5509                                     mac_addr->addr_bytes[5],
5510                                     diag);
5511         }
5512 }
5513
5514 static void
5515 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5516 {
5517         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5518
5519         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5520 }
5521
5522 #define MAC_TYPE_FILTER_SUP(type)    do {\
5523         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5524                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5525                 (type) != ixgbe_mac_X550EM_a)\
5526                 return -ENOTSUP;\
5527 } while (0)
5528
5529 static int
5530 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5531                         struct rte_eth_syn_filter *filter,
5532                         bool add)
5533 {
5534         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5535         uint32_t synqf;
5536
5537         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5538                 return -EINVAL;
5539
5540         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5541
5542         if (add) {
5543                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5544                         return -EINVAL;
5545                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5546                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5547
5548                 if (filter->hig_pri)
5549                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5550                 else
5551                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5552         } else {
5553                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5554                         return -ENOENT;
5555                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5556         }
5557         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5558         IXGBE_WRITE_FLUSH(hw);
5559         return 0;
5560 }
5561
5562 static int
5563 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5564                         struct rte_eth_syn_filter *filter)
5565 {
5566         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5567         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5568
5569         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5570                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5571                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5572                 return 0;
5573         }
5574         return -ENOENT;
5575 }
5576
5577 static int
5578 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5579                         enum rte_filter_op filter_op,
5580                         void *arg)
5581 {
5582         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5583         int ret;
5584
5585         MAC_TYPE_FILTER_SUP(hw->mac.type);
5586
5587         if (filter_op == RTE_ETH_FILTER_NOP)
5588                 return 0;
5589
5590         if (arg == NULL) {
5591                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5592                             filter_op);
5593                 return -EINVAL;
5594         }
5595
5596         switch (filter_op) {
5597         case RTE_ETH_FILTER_ADD:
5598                 ret = ixgbe_syn_filter_set(dev,
5599                                 (struct rte_eth_syn_filter *)arg,
5600                                 TRUE);
5601                 break;
5602         case RTE_ETH_FILTER_DELETE:
5603                 ret = ixgbe_syn_filter_set(dev,
5604                                 (struct rte_eth_syn_filter *)arg,
5605                                 FALSE);
5606                 break;
5607         case RTE_ETH_FILTER_GET:
5608                 ret = ixgbe_syn_filter_get(dev,
5609                                 (struct rte_eth_syn_filter *)arg);
5610                 break;
5611         default:
5612                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5613                 ret = -EINVAL;
5614                 break;
5615         }
5616
5617         return ret;
5618 }
5619
5620
5621 static inline enum ixgbe_5tuple_protocol
5622 convert_protocol_type(uint8_t protocol_value)
5623 {
5624         if (protocol_value == IPPROTO_TCP)
5625                 return IXGBE_FILTER_PROTOCOL_TCP;
5626         else if (protocol_value == IPPROTO_UDP)
5627                 return IXGBE_FILTER_PROTOCOL_UDP;
5628         else if (protocol_value == IPPROTO_SCTP)
5629                 return IXGBE_FILTER_PROTOCOL_SCTP;
5630         else
5631                 return IXGBE_FILTER_PROTOCOL_NONE;
5632 }
5633
5634 /*
5635  * add a 5tuple filter
5636  *
5637  * @param
5638  * dev: Pointer to struct rte_eth_dev.
5639  * index: the index the filter allocates.
5640  * filter: ponter to the filter that will be added.
5641  * rx_queue: the queue id the filter assigned to.
5642  *
5643  * @return
5644  *    - On success, zero.
5645  *    - On failure, a negative value.
5646  */
5647 static int
5648 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5649                         struct ixgbe_5tuple_filter *filter)
5650 {
5651         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5652         struct ixgbe_filter_info *filter_info =
5653                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5654         int i, idx, shift;
5655         uint32_t ftqf, sdpqf;
5656         uint32_t l34timir = 0;
5657         uint8_t mask = 0xff;
5658
5659         /*
5660          * look for an unused 5tuple filter index,
5661          * and insert the filter to list.
5662          */
5663         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5664                 idx = i / (sizeof(uint32_t) * NBBY);
5665                 shift = i % (sizeof(uint32_t) * NBBY);
5666                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5667                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5668                         filter->index = i;
5669                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5670                                           filter,
5671                                           entries);
5672                         break;
5673                 }
5674         }
5675         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5676                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5677                 return -ENOSYS;
5678         }
5679
5680         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5681                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5682         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5683
5684         ftqf = (uint32_t)(filter->filter_info.proto &
5685                 IXGBE_FTQF_PROTOCOL_MASK);
5686         ftqf |= (uint32_t)((filter->filter_info.priority &
5687                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5688         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5689                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5690         if (filter->filter_info.dst_ip_mask == 0)
5691                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5692         if (filter->filter_info.src_port_mask == 0)
5693                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5694         if (filter->filter_info.dst_port_mask == 0)
5695                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5696         if (filter->filter_info.proto_mask == 0)
5697                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5698         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5699         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5700         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5701
5702         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5703         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5704         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5705         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5706
5707         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5708         l34timir |= (uint32_t)(filter->queue <<
5709                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5710         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5711         return 0;
5712 }
5713
5714 /*
5715  * remove a 5tuple filter
5716  *
5717  * @param
5718  * dev: Pointer to struct rte_eth_dev.
5719  * filter: the pointer of the filter will be removed.
5720  */
5721 static void
5722 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5723                         struct ixgbe_5tuple_filter *filter)
5724 {
5725         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5726         struct ixgbe_filter_info *filter_info =
5727                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5728         uint16_t index = filter->index;
5729
5730         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5731                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5732         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5733         rte_free(filter);
5734
5735         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5736         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5737         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5738         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5739         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5740 }
5741
5742 static int
5743 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5744 {
5745         struct ixgbe_hw *hw;
5746         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5747
5748         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5749
5750         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5751                 return -EINVAL;
5752
5753         /* refuse mtu that requires the support of scattered packets when this
5754          * feature has not been enabled before.
5755          */
5756         if (!dev->data->scattered_rx &&
5757             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5758              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5759                 return -EINVAL;
5760
5761         /*
5762          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5763          * request of the version 2.0 of the mailbox API.
5764          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5765          * of the mailbox API.
5766          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5767          * prior to 3.11.33 which contains the following change:
5768          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5769          */
5770         ixgbevf_rlpml_set_vf(hw, max_frame);
5771
5772         /* update max frame size */
5773         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5774         return 0;
5775 }
5776
5777 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5778         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5779                 return -ENOTSUP;\
5780 } while (0)
5781
5782 static inline struct ixgbe_5tuple_filter *
5783 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5784                         struct ixgbe_5tuple_filter_info *key)
5785 {
5786         struct ixgbe_5tuple_filter *it;
5787
5788         TAILQ_FOREACH(it, filter_list, entries) {
5789                 if (memcmp(key, &it->filter_info,
5790                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5791                         return it;
5792                 }
5793         }
5794         return NULL;
5795 }
5796
5797 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5798 static inline int
5799 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5800                         struct ixgbe_5tuple_filter_info *filter_info)
5801 {
5802         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5803                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5804                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5805                 return -EINVAL;
5806
5807         switch (filter->dst_ip_mask) {
5808         case UINT32_MAX:
5809                 filter_info->dst_ip_mask = 0;
5810                 filter_info->dst_ip = filter->dst_ip;
5811                 break;
5812         case 0:
5813                 filter_info->dst_ip_mask = 1;
5814                 break;
5815         default:
5816                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5817                 return -EINVAL;
5818         }
5819
5820         switch (filter->src_ip_mask) {
5821         case UINT32_MAX:
5822                 filter_info->src_ip_mask = 0;
5823                 filter_info->src_ip = filter->src_ip;
5824                 break;
5825         case 0:
5826                 filter_info->src_ip_mask = 1;
5827                 break;
5828         default:
5829                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5830                 return -EINVAL;
5831         }
5832
5833         switch (filter->dst_port_mask) {
5834         case UINT16_MAX:
5835                 filter_info->dst_port_mask = 0;
5836                 filter_info->dst_port = filter->dst_port;
5837                 break;
5838         case 0:
5839                 filter_info->dst_port_mask = 1;
5840                 break;
5841         default:
5842                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5843                 return -EINVAL;
5844         }
5845
5846         switch (filter->src_port_mask) {
5847         case UINT16_MAX:
5848                 filter_info->src_port_mask = 0;
5849                 filter_info->src_port = filter->src_port;
5850                 break;
5851         case 0:
5852                 filter_info->src_port_mask = 1;
5853                 break;
5854         default:
5855                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5856                 return -EINVAL;
5857         }
5858
5859         switch (filter->proto_mask) {
5860         case UINT8_MAX:
5861                 filter_info->proto_mask = 0;
5862                 filter_info->proto =
5863                         convert_protocol_type(filter->proto);
5864                 break;
5865         case 0:
5866                 filter_info->proto_mask = 1;
5867                 break;
5868         default:
5869                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5870                 return -EINVAL;
5871         }
5872
5873         filter_info->priority = (uint8_t)filter->priority;
5874         return 0;
5875 }
5876
5877 /*
5878  * add or delete a ntuple filter
5879  *
5880  * @param
5881  * dev: Pointer to struct rte_eth_dev.
5882  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5883  * add: if true, add filter, if false, remove filter
5884  *
5885  * @return
5886  *    - On success, zero.
5887  *    - On failure, a negative value.
5888  */
5889 static int
5890 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5891                         struct rte_eth_ntuple_filter *ntuple_filter,
5892                         bool add)
5893 {
5894         struct ixgbe_filter_info *filter_info =
5895                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5896         struct ixgbe_5tuple_filter_info filter_5tuple;
5897         struct ixgbe_5tuple_filter *filter;
5898         int ret;
5899
5900         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5901                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5902                 return -EINVAL;
5903         }
5904
5905         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5906         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5907         if (ret < 0)
5908                 return ret;
5909
5910         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5911                                          &filter_5tuple);
5912         if (filter != NULL && add) {
5913                 PMD_DRV_LOG(ERR, "filter exists.");
5914                 return -EEXIST;
5915         }
5916         if (filter == NULL && !add) {
5917                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5918                 return -ENOENT;
5919         }
5920
5921         if (add) {
5922                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5923                                 sizeof(struct ixgbe_5tuple_filter), 0);
5924                 if (filter == NULL)
5925                         return -ENOMEM;
5926                 (void)rte_memcpy(&filter->filter_info,
5927                                  &filter_5tuple,
5928                                  sizeof(struct ixgbe_5tuple_filter_info));
5929                 filter->queue = ntuple_filter->queue;
5930                 ret = ixgbe_add_5tuple_filter(dev, filter);
5931                 if (ret < 0) {
5932                         rte_free(filter);
5933                         return ret;
5934                 }
5935         } else
5936                 ixgbe_remove_5tuple_filter(dev, filter);
5937
5938         return 0;
5939 }
5940
5941 /*
5942  * get a ntuple filter
5943  *
5944  * @param
5945  * dev: Pointer to struct rte_eth_dev.
5946  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5947  *
5948  * @return
5949  *    - On success, zero.
5950  *    - On failure, a negative value.
5951  */
5952 static int
5953 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5954                         struct rte_eth_ntuple_filter *ntuple_filter)
5955 {
5956         struct ixgbe_filter_info *filter_info =
5957                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5958         struct ixgbe_5tuple_filter_info filter_5tuple;
5959         struct ixgbe_5tuple_filter *filter;
5960         int ret;
5961
5962         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5963                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5964                 return -EINVAL;
5965         }
5966
5967         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5968         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5969         if (ret < 0)
5970                 return ret;
5971
5972         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5973                                          &filter_5tuple);
5974         if (filter == NULL) {
5975                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5976                 return -ENOENT;
5977         }
5978         ntuple_filter->queue = filter->queue;
5979         return 0;
5980 }
5981
5982 /*
5983  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5984  * @dev: pointer to rte_eth_dev structure
5985  * @filter_op:operation will be taken.
5986  * @arg: a pointer to specific structure corresponding to the filter_op
5987  *
5988  * @return
5989  *    - On success, zero.
5990  *    - On failure, a negative value.
5991  */
5992 static int
5993 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5994                                 enum rte_filter_op filter_op,
5995                                 void *arg)
5996 {
5997         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5998         int ret;
5999
6000         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6001
6002         if (filter_op == RTE_ETH_FILTER_NOP)
6003                 return 0;
6004
6005         if (arg == NULL) {
6006                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6007                             filter_op);
6008                 return -EINVAL;
6009         }
6010
6011         switch (filter_op) {
6012         case RTE_ETH_FILTER_ADD:
6013                 ret = ixgbe_add_del_ntuple_filter(dev,
6014                         (struct rte_eth_ntuple_filter *)arg,
6015                         TRUE);
6016                 break;
6017         case RTE_ETH_FILTER_DELETE:
6018                 ret = ixgbe_add_del_ntuple_filter(dev,
6019                         (struct rte_eth_ntuple_filter *)arg,
6020                         FALSE);
6021                 break;
6022         case RTE_ETH_FILTER_GET:
6023                 ret = ixgbe_get_ntuple_filter(dev,
6024                         (struct rte_eth_ntuple_filter *)arg);
6025                 break;
6026         default:
6027                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6028                 ret = -EINVAL;
6029                 break;
6030         }
6031         return ret;
6032 }
6033
6034 static inline int
6035 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
6036                         uint16_t ethertype)
6037 {
6038         int i;
6039
6040         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6041                 if (filter_info->ethertype_filters[i] == ethertype &&
6042                     (filter_info->ethertype_mask & (1 << i)))
6043                         return i;
6044         }
6045         return -1;
6046 }
6047
6048 static inline int
6049 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
6050                         uint16_t ethertype)
6051 {
6052         int i;
6053
6054         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6055                 if (!(filter_info->ethertype_mask & (1 << i))) {
6056                         filter_info->ethertype_mask |= 1 << i;
6057                         filter_info->ethertype_filters[i] = ethertype;
6058                         return i;
6059                 }
6060         }
6061         return -1;
6062 }
6063
6064 static inline int
6065 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
6066                         uint8_t idx)
6067 {
6068         if (idx >= IXGBE_MAX_ETQF_FILTERS)
6069                 return -1;
6070         filter_info->ethertype_mask &= ~(1 << idx);
6071         filter_info->ethertype_filters[idx] = 0;
6072         return idx;
6073 }
6074
6075 static int
6076 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6077                         struct rte_eth_ethertype_filter *filter,
6078                         bool add)
6079 {
6080         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6081         struct ixgbe_filter_info *filter_info =
6082                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6083         uint32_t etqf = 0;
6084         uint32_t etqs = 0;
6085         int ret;
6086
6087         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6088                 return -EINVAL;
6089
6090         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6091                 filter->ether_type == ETHER_TYPE_IPv6) {
6092                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6093                         " ethertype filter.", filter->ether_type);
6094                 return -EINVAL;
6095         }
6096
6097         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6098                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6099                 return -EINVAL;
6100         }
6101         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6102                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6103                 return -EINVAL;
6104         }
6105
6106         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6107         if (ret >= 0 && add) {
6108                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6109                             filter->ether_type);
6110                 return -EEXIST;
6111         }
6112         if (ret < 0 && !add) {
6113                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6114                             filter->ether_type);
6115                 return -ENOENT;
6116         }
6117
6118         if (add) {
6119                 ret = ixgbe_ethertype_filter_insert(filter_info,
6120                         filter->ether_type);
6121                 if (ret < 0) {
6122                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6123                         return -ENOSYS;
6124                 }
6125                 etqf = IXGBE_ETQF_FILTER_EN;
6126                 etqf |= (uint32_t)filter->ether_type;
6127                 etqs |= (uint32_t)((filter->queue <<
6128                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6129                                     IXGBE_ETQS_RX_QUEUE);
6130                 etqs |= IXGBE_ETQS_QUEUE_EN;
6131         } else {
6132                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6133                 if (ret < 0)
6134                         return -ENOSYS;
6135         }
6136         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6137         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6138         IXGBE_WRITE_FLUSH(hw);
6139
6140         return 0;
6141 }
6142
6143 static int
6144 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6145                         struct rte_eth_ethertype_filter *filter)
6146 {
6147         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6148         struct ixgbe_filter_info *filter_info =
6149                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6150         uint32_t etqf, etqs;
6151         int ret;
6152
6153         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6154         if (ret < 0) {
6155                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6156                             filter->ether_type);
6157                 return -ENOENT;
6158         }
6159
6160         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6161         if (etqf & IXGBE_ETQF_FILTER_EN) {
6162                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6163                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6164                 filter->flags = 0;
6165                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6166                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6167                 return 0;
6168         }
6169         return -ENOENT;
6170 }
6171
6172 /*
6173  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6174  * @dev: pointer to rte_eth_dev structure
6175  * @filter_op:operation will be taken.
6176  * @arg: a pointer to specific structure corresponding to the filter_op
6177  */
6178 static int
6179 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6180                                 enum rte_filter_op filter_op,
6181                                 void *arg)
6182 {
6183         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6184         int ret;
6185
6186         MAC_TYPE_FILTER_SUP(hw->mac.type);
6187
6188         if (filter_op == RTE_ETH_FILTER_NOP)
6189                 return 0;
6190
6191         if (arg == NULL) {
6192                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6193                             filter_op);
6194                 return -EINVAL;
6195         }
6196
6197         switch (filter_op) {
6198         case RTE_ETH_FILTER_ADD:
6199                 ret = ixgbe_add_del_ethertype_filter(dev,
6200                         (struct rte_eth_ethertype_filter *)arg,
6201                         TRUE);
6202                 break;
6203         case RTE_ETH_FILTER_DELETE:
6204                 ret = ixgbe_add_del_ethertype_filter(dev,
6205                         (struct rte_eth_ethertype_filter *)arg,
6206                         FALSE);
6207                 break;
6208         case RTE_ETH_FILTER_GET:
6209                 ret = ixgbe_get_ethertype_filter(dev,
6210                         (struct rte_eth_ethertype_filter *)arg);
6211                 break;
6212         default:
6213                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6214                 ret = -EINVAL;
6215                 break;
6216         }
6217         return ret;
6218 }
6219
6220 static int
6221 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6222                      enum rte_filter_type filter_type,
6223                      enum rte_filter_op filter_op,
6224                      void *arg)
6225 {
6226         int ret = -EINVAL;
6227
6228         switch (filter_type) {
6229         case RTE_ETH_FILTER_NTUPLE:
6230                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6231                 break;
6232         case RTE_ETH_FILTER_ETHERTYPE:
6233                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6234                 break;
6235         case RTE_ETH_FILTER_SYN:
6236                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6237                 break;
6238         case RTE_ETH_FILTER_FDIR:
6239                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6240                 break;
6241         case RTE_ETH_FILTER_L2_TUNNEL:
6242                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6243                 break;
6244         default:
6245                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6246                                                         filter_type);
6247                 break;
6248         }
6249
6250         return ret;
6251 }
6252
6253 static u8 *
6254 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6255                         u8 **mc_addr_ptr, u32 *vmdq)
6256 {
6257         u8 *mc_addr;
6258
6259         *vmdq = 0;
6260         mc_addr = *mc_addr_ptr;
6261         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6262         return mc_addr;
6263 }
6264
6265 static int
6266 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6267                           struct ether_addr *mc_addr_set,
6268                           uint32_t nb_mc_addr)
6269 {
6270         struct ixgbe_hw *hw;
6271         u8 *mc_addr_list;
6272
6273         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6274         mc_addr_list = (u8 *)mc_addr_set;
6275         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6276                                          ixgbe_dev_addr_list_itr, TRUE);
6277 }
6278
6279 static uint64_t
6280 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6281 {
6282         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6283         uint64_t systime_cycles;
6284
6285         switch (hw->mac.type) {
6286         case ixgbe_mac_X550:
6287         case ixgbe_mac_X550EM_x:
6288         case ixgbe_mac_X550EM_a:
6289                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6290                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6291                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6292                                 * NSEC_PER_SEC;
6293                 break;
6294         default:
6295                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6296                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6297                                 << 32;
6298         }
6299
6300         return systime_cycles;
6301 }
6302
6303 static uint64_t
6304 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6305 {
6306         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6307         uint64_t rx_tstamp_cycles;
6308
6309         switch (hw->mac.type) {
6310         case ixgbe_mac_X550:
6311         case ixgbe_mac_X550EM_x:
6312         case ixgbe_mac_X550EM_a:
6313                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6314                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6315                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6316                                 * NSEC_PER_SEC;
6317                 break;
6318         default:
6319                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6320                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6321                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6322                                 << 32;
6323         }
6324
6325         return rx_tstamp_cycles;
6326 }
6327
6328 static uint64_t
6329 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6330 {
6331         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6332         uint64_t tx_tstamp_cycles;
6333
6334         switch (hw->mac.type) {
6335         case ixgbe_mac_X550:
6336         case ixgbe_mac_X550EM_x:
6337         case ixgbe_mac_X550EM_a:
6338                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6339                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6340                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6341                                 * NSEC_PER_SEC;
6342                 break;
6343         default:
6344                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6345                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6346                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6347                                 << 32;
6348         }
6349
6350         return tx_tstamp_cycles;
6351 }
6352
6353 static void
6354 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6355 {
6356         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6357         struct ixgbe_adapter *adapter =
6358                 (struct ixgbe_adapter *)dev->data->dev_private;
6359         struct rte_eth_link link;
6360         uint32_t incval = 0;
6361         uint32_t shift = 0;
6362
6363         /* Get current link speed. */
6364         memset(&link, 0, sizeof(link));
6365         ixgbe_dev_link_update(dev, 1);
6366         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6367
6368         switch (link.link_speed) {
6369         case ETH_SPEED_NUM_100M:
6370                 incval = IXGBE_INCVAL_100;
6371                 shift = IXGBE_INCVAL_SHIFT_100;
6372                 break;
6373         case ETH_SPEED_NUM_1G:
6374                 incval = IXGBE_INCVAL_1GB;
6375                 shift = IXGBE_INCVAL_SHIFT_1GB;
6376                 break;
6377         case ETH_SPEED_NUM_10G:
6378         default:
6379                 incval = IXGBE_INCVAL_10GB;
6380                 shift = IXGBE_INCVAL_SHIFT_10GB;
6381                 break;
6382         }
6383
6384         switch (hw->mac.type) {
6385         case ixgbe_mac_X550:
6386         case ixgbe_mac_X550EM_x:
6387         case ixgbe_mac_X550EM_a:
6388                 /* Independent of link speed. */
6389                 incval = 1;
6390                 /* Cycles read will be interpreted as ns. */
6391                 shift = 0;
6392                 /* Fall-through */
6393         case ixgbe_mac_X540:
6394                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6395                 break;
6396         case ixgbe_mac_82599EB:
6397                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6398                 shift -= IXGBE_INCVAL_SHIFT_82599;
6399                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6400                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6401                 break;
6402         default:
6403                 /* Not supported. */
6404                 return;
6405         }
6406
6407         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6408         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6409         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6410
6411         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6412         adapter->systime_tc.cc_shift = shift;
6413         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6414
6415         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6416         adapter->rx_tstamp_tc.cc_shift = shift;
6417         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6418
6419         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6420         adapter->tx_tstamp_tc.cc_shift = shift;
6421         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6422 }
6423
6424 static int
6425 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6426 {
6427         struct ixgbe_adapter *adapter =
6428                         (struct ixgbe_adapter *)dev->data->dev_private;
6429
6430         adapter->systime_tc.nsec += delta;
6431         adapter->rx_tstamp_tc.nsec += delta;
6432         adapter->tx_tstamp_tc.nsec += delta;
6433
6434         return 0;
6435 }
6436
6437 static int
6438 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6439 {
6440         uint64_t ns;
6441         struct ixgbe_adapter *adapter =
6442                         (struct ixgbe_adapter *)dev->data->dev_private;
6443
6444         ns = rte_timespec_to_ns(ts);
6445         /* Set the timecounters to a new value. */
6446         adapter->systime_tc.nsec = ns;
6447         adapter->rx_tstamp_tc.nsec = ns;
6448         adapter->tx_tstamp_tc.nsec = ns;
6449
6450         return 0;
6451 }
6452
6453 static int
6454 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6455 {
6456         uint64_t ns, systime_cycles;
6457         struct ixgbe_adapter *adapter =
6458                         (struct ixgbe_adapter *)dev->data->dev_private;
6459
6460         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6461         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6462         *ts = rte_ns_to_timespec(ns);
6463
6464         return 0;
6465 }
6466
6467 static int
6468 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6469 {
6470         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6471         uint32_t tsync_ctl;
6472         uint32_t tsauxc;
6473
6474         /* Stop the timesync system time. */
6475         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6476         /* Reset the timesync system time value. */
6477         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6478         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6479
6480         /* Enable system time for platforms where it isn't on by default. */
6481         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6482         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6483         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6484
6485         ixgbe_start_timecounters(dev);
6486
6487         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6488         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6489                         (ETHER_TYPE_1588 |
6490                          IXGBE_ETQF_FILTER_EN |
6491                          IXGBE_ETQF_1588));
6492
6493         /* Enable timestamping of received PTP packets. */
6494         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6495         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6496         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6497
6498         /* Enable timestamping of transmitted PTP packets. */
6499         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6500         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6501         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6502
6503         IXGBE_WRITE_FLUSH(hw);
6504
6505         return 0;
6506 }
6507
6508 static int
6509 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6510 {
6511         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6512         uint32_t tsync_ctl;
6513
6514         /* Disable timestamping of transmitted PTP packets. */
6515         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6516         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6517         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6518
6519         /* Disable timestamping of received PTP packets. */
6520         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6521         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6522         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6523
6524         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6525         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6526
6527         /* Stop incrementating the System Time registers. */
6528         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6529
6530         return 0;
6531 }
6532
6533 static int
6534 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6535                                  struct timespec *timestamp,
6536                                  uint32_t flags __rte_unused)
6537 {
6538         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6539         struct ixgbe_adapter *adapter =
6540                 (struct ixgbe_adapter *)dev->data->dev_private;
6541         uint32_t tsync_rxctl;
6542         uint64_t rx_tstamp_cycles;
6543         uint64_t ns;
6544
6545         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6546         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6547                 return -EINVAL;
6548
6549         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6550         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6551         *timestamp = rte_ns_to_timespec(ns);
6552
6553         return  0;
6554 }
6555
6556 static int
6557 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6558                                  struct timespec *timestamp)
6559 {
6560         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6561         struct ixgbe_adapter *adapter =
6562                 (struct ixgbe_adapter *)dev->data->dev_private;
6563         uint32_t tsync_txctl;
6564         uint64_t tx_tstamp_cycles;
6565         uint64_t ns;
6566
6567         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6568         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6569                 return -EINVAL;
6570
6571         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6572         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6573         *timestamp = rte_ns_to_timespec(ns);
6574
6575         return 0;
6576 }
6577
6578 static int
6579 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6580 {
6581         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6582         int count = 0;
6583         int g_ind = 0;
6584         const struct reg_info *reg_group;
6585         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6586                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6587
6588         while ((reg_group = reg_set[g_ind++]))
6589                 count += ixgbe_regs_group_count(reg_group);
6590
6591         return count;
6592 }
6593
6594 static int
6595 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6596 {
6597         int count = 0;
6598         int g_ind = 0;
6599         const struct reg_info *reg_group;
6600
6601         while ((reg_group = ixgbevf_regs[g_ind++]))
6602                 count += ixgbe_regs_group_count(reg_group);
6603
6604         return count;
6605 }
6606
6607 static int
6608 ixgbe_get_regs(struct rte_eth_dev *dev,
6609               struct rte_dev_reg_info *regs)
6610 {
6611         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6612         uint32_t *data = regs->data;
6613         int g_ind = 0;
6614         int count = 0;
6615         const struct reg_info *reg_group;
6616         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6617                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6618
6619         if (data == NULL) {
6620                 regs->length = ixgbe_get_reg_length(dev);
6621                 regs->width = sizeof(uint32_t);
6622                 return 0;
6623         }
6624
6625         /* Support only full register dump */
6626         if ((regs->length == 0) ||
6627             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6628                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6629                         hw->device_id;
6630                 while ((reg_group = reg_set[g_ind++]))
6631                         count += ixgbe_read_regs_group(dev, &data[count],
6632                                 reg_group);
6633                 return 0;
6634         }
6635
6636         return -ENOTSUP;
6637 }
6638
6639 static int
6640 ixgbevf_get_regs(struct rte_eth_dev *dev,
6641                 struct rte_dev_reg_info *regs)
6642 {
6643         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6644         uint32_t *data = regs->data;
6645         int g_ind = 0;
6646         int count = 0;
6647         const struct reg_info *reg_group;
6648
6649         if (data == NULL) {
6650                 regs->length = ixgbevf_get_reg_length(dev);
6651                 regs->width = sizeof(uint32_t);
6652                 return 0;
6653         }
6654
6655         /* Support only full register dump */
6656         if ((regs->length == 0) ||
6657             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6658                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6659                         hw->device_id;
6660                 while ((reg_group = ixgbevf_regs[g_ind++]))
6661                         count += ixgbe_read_regs_group(dev, &data[count],
6662                                                       reg_group);
6663                 return 0;
6664         }
6665
6666         return -ENOTSUP;
6667 }
6668
6669 static int
6670 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6671 {
6672         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6673
6674         /* Return unit is byte count */
6675         return hw->eeprom.word_size * 2;
6676 }
6677
6678 static int
6679 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6680                 struct rte_dev_eeprom_info *in_eeprom)
6681 {
6682         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6683         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6684         uint16_t *data = in_eeprom->data;
6685         int first, length;
6686
6687         first = in_eeprom->offset >> 1;
6688         length = in_eeprom->length >> 1;
6689         if ((first > hw->eeprom.word_size) ||
6690             ((first + length) > hw->eeprom.word_size))
6691                 return -EINVAL;
6692
6693         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6694
6695         return eeprom->ops.read_buffer(hw, first, length, data);
6696 }
6697
6698 static int
6699 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6700                 struct rte_dev_eeprom_info *in_eeprom)
6701 {
6702         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6703         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6704         uint16_t *data = in_eeprom->data;
6705         int first, length;
6706
6707         first = in_eeprom->offset >> 1;
6708         length = in_eeprom->length >> 1;
6709         if ((first > hw->eeprom.word_size) ||
6710             ((first + length) > hw->eeprom.word_size))
6711                 return -EINVAL;
6712
6713         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6714
6715         return eeprom->ops.write_buffer(hw,  first, length, data);
6716 }
6717
6718 uint16_t
6719 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6720         switch (mac_type) {
6721         case ixgbe_mac_X550:
6722         case ixgbe_mac_X550EM_x:
6723         case ixgbe_mac_X550EM_a:
6724                 return ETH_RSS_RETA_SIZE_512;
6725         case ixgbe_mac_X550_vf:
6726         case ixgbe_mac_X550EM_x_vf:
6727         case ixgbe_mac_X550EM_a_vf:
6728                 return ETH_RSS_RETA_SIZE_64;
6729         default:
6730                 return ETH_RSS_RETA_SIZE_128;
6731         }
6732 }
6733
6734 uint32_t
6735 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6736         switch (mac_type) {
6737         case ixgbe_mac_X550:
6738         case ixgbe_mac_X550EM_x:
6739         case ixgbe_mac_X550EM_a:
6740                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6741                         return IXGBE_RETA(reta_idx >> 2);
6742                 else
6743                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6744         case ixgbe_mac_X550_vf:
6745         case ixgbe_mac_X550EM_x_vf:
6746         case ixgbe_mac_X550EM_a_vf:
6747                 return IXGBE_VFRETA(reta_idx >> 2);
6748         default:
6749                 return IXGBE_RETA(reta_idx >> 2);
6750         }
6751 }
6752
6753 uint32_t
6754 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6755         switch (mac_type) {
6756         case ixgbe_mac_X550_vf:
6757         case ixgbe_mac_X550EM_x_vf:
6758         case ixgbe_mac_X550EM_a_vf:
6759                 return IXGBE_VFMRQC;
6760         default:
6761                 return IXGBE_MRQC;
6762         }
6763 }
6764
6765 uint32_t
6766 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6767         switch (mac_type) {
6768         case ixgbe_mac_X550_vf:
6769         case ixgbe_mac_X550EM_x_vf:
6770         case ixgbe_mac_X550EM_a_vf:
6771                 return IXGBE_VFRSSRK(i);
6772         default:
6773                 return IXGBE_RSSRK(i);
6774         }
6775 }
6776
6777 bool
6778 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6779         switch (mac_type) {
6780         case ixgbe_mac_82599_vf:
6781         case ixgbe_mac_X540_vf:
6782                 return 0;
6783         default:
6784                 return 1;
6785         }
6786 }
6787
6788 static int
6789 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6790                         struct rte_eth_dcb_info *dcb_info)
6791 {
6792         struct ixgbe_dcb_config *dcb_config =
6793                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6794         struct ixgbe_dcb_tc_config *tc;
6795         uint8_t i, j;
6796
6797         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6798                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6799         else
6800                 dcb_info->nb_tcs = 1;
6801
6802         if (dcb_config->vt_mode) { /* vt is enabled*/
6803                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6804                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6805                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6806                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6807                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6808                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6809                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6810                                                 i * dcb_info->nb_tcs + j;
6811                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6812                                 dcb_info->tc_queue.tc_txq[i][j].base =
6813                                                 i * dcb_info->nb_tcs + j;
6814                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6815                         }
6816                 }
6817         } else { /* vt is disabled*/
6818                 struct rte_eth_dcb_rx_conf *rx_conf =
6819                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6820                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6821                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6822                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6823                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6824                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6825                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6826                         }
6827                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6828                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6829                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6830                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6831                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6832                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6833                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6834                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6835                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6836                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6837                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6838                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6839                         }
6840                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6841                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6842                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6843                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6844                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6845                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6846                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6847                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6848                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6849                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6850                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6851                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6852                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6853                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6854                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6855                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6856                 }
6857         }
6858         for (i = 0; i < dcb_info->nb_tcs; i++) {
6859                 tc = &dcb_config->tc_config[i];
6860                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6861         }
6862         return 0;
6863 }
6864
6865 /* Update e-tag ether type */
6866 static int
6867 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6868                             uint16_t ether_type)
6869 {
6870         uint32_t etag_etype;
6871
6872         if (hw->mac.type != ixgbe_mac_X550 &&
6873             hw->mac.type != ixgbe_mac_X550EM_x &&
6874             hw->mac.type != ixgbe_mac_X550EM_a) {
6875                 return -ENOTSUP;
6876         }
6877
6878         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6879         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6880         etag_etype |= ether_type;
6881         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6882         IXGBE_WRITE_FLUSH(hw);
6883
6884         return 0;
6885 }
6886
6887 /* Config l2 tunnel ether type */
6888 static int
6889 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6890                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6891 {
6892         int ret = 0;
6893         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6894
6895         if (l2_tunnel == NULL)
6896                 return -EINVAL;
6897
6898         switch (l2_tunnel->l2_tunnel_type) {
6899         case RTE_L2_TUNNEL_TYPE_E_TAG:
6900                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6901                 break;
6902         default:
6903                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6904                 ret = -EINVAL;
6905                 break;
6906         }
6907
6908         return ret;
6909 }
6910
6911 /* Enable e-tag tunnel */
6912 static int
6913 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6914 {
6915         uint32_t etag_etype;
6916
6917         if (hw->mac.type != ixgbe_mac_X550 &&
6918             hw->mac.type != ixgbe_mac_X550EM_x &&
6919             hw->mac.type != ixgbe_mac_X550EM_a) {
6920                 return -ENOTSUP;
6921         }
6922
6923         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6924         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6925         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6926         IXGBE_WRITE_FLUSH(hw);
6927
6928         return 0;
6929 }
6930
6931 /* Enable l2 tunnel */
6932 static int
6933 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6934                            enum rte_eth_tunnel_type l2_tunnel_type)
6935 {
6936         int ret = 0;
6937         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6938
6939         switch (l2_tunnel_type) {
6940         case RTE_L2_TUNNEL_TYPE_E_TAG:
6941                 ret = ixgbe_e_tag_enable(hw);
6942                 break;
6943         default:
6944                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6945                 ret = -EINVAL;
6946                 break;
6947         }
6948
6949         return ret;
6950 }
6951
6952 /* Disable e-tag tunnel */
6953 static int
6954 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6955 {
6956         uint32_t etag_etype;
6957
6958         if (hw->mac.type != ixgbe_mac_X550 &&
6959             hw->mac.type != ixgbe_mac_X550EM_x &&
6960             hw->mac.type != ixgbe_mac_X550EM_a) {
6961                 return -ENOTSUP;
6962         }
6963
6964         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6965         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6966         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6967         IXGBE_WRITE_FLUSH(hw);
6968
6969         return 0;
6970 }
6971
6972 /* Disable l2 tunnel */
6973 static int
6974 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6975                             enum rte_eth_tunnel_type l2_tunnel_type)
6976 {
6977         int ret = 0;
6978         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6979
6980         switch (l2_tunnel_type) {
6981         case RTE_L2_TUNNEL_TYPE_E_TAG:
6982                 ret = ixgbe_e_tag_disable(hw);
6983                 break;
6984         default:
6985                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6986                 ret = -EINVAL;
6987                 break;
6988         }
6989
6990         return ret;
6991 }
6992
6993 static int
6994 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6995                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6996 {
6997         int ret = 0;
6998         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6999         uint32_t i, rar_entries;
7000         uint32_t rar_low, rar_high;
7001
7002         if (hw->mac.type != ixgbe_mac_X550 &&
7003             hw->mac.type != ixgbe_mac_X550EM_x &&
7004             hw->mac.type != ixgbe_mac_X550EM_a) {
7005                 return -ENOTSUP;
7006         }
7007
7008         rar_entries = ixgbe_get_num_rx_addrs(hw);
7009
7010         for (i = 1; i < rar_entries; i++) {
7011                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7012                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7013                 if ((rar_high & IXGBE_RAH_AV) &&
7014                     (rar_high & IXGBE_RAH_ADTYPE) &&
7015                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7016                      l2_tunnel->tunnel_id)) {
7017                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7018                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7019
7020                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7021
7022                         return ret;
7023                 }
7024         }
7025
7026         return ret;
7027 }
7028
7029 static int
7030 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7031                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7032 {
7033         int ret = 0;
7034         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7035         uint32_t i, rar_entries;
7036         uint32_t rar_low, rar_high;
7037
7038         if (hw->mac.type != ixgbe_mac_X550 &&
7039             hw->mac.type != ixgbe_mac_X550EM_x &&
7040             hw->mac.type != ixgbe_mac_X550EM_a) {
7041                 return -ENOTSUP;
7042         }
7043
7044         /* One entry for one tunnel. Try to remove potential existing entry. */
7045         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7046
7047         rar_entries = ixgbe_get_num_rx_addrs(hw);
7048
7049         for (i = 1; i < rar_entries; i++) {
7050                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7051                 if (rar_high & IXGBE_RAH_AV) {
7052                         continue;
7053                 } else {
7054                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7055                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7056                         rar_low = l2_tunnel->tunnel_id;
7057
7058                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7059                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7060
7061                         return ret;
7062                 }
7063         }
7064
7065         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7066                      " Please remove a rule before adding a new one.");
7067         return -EINVAL;
7068 }
7069
7070 /* Add l2 tunnel filter */
7071 static int
7072 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7073                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7074 {
7075         int ret = 0;
7076
7077         switch (l2_tunnel->l2_tunnel_type) {
7078         case RTE_L2_TUNNEL_TYPE_E_TAG:
7079                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7080                 break;
7081         default:
7082                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7083                 ret = -EINVAL;
7084                 break;
7085         }
7086
7087         return ret;
7088 }
7089
7090 /* Delete l2 tunnel filter */
7091 static int
7092 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7093                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7094 {
7095         int ret = 0;
7096
7097         switch (l2_tunnel->l2_tunnel_type) {
7098         case RTE_L2_TUNNEL_TYPE_E_TAG:
7099                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7100                 break;
7101         default:
7102                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7103                 ret = -EINVAL;
7104                 break;
7105         }
7106
7107         return ret;
7108 }
7109
7110 /**
7111  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7112  * @dev: pointer to rte_eth_dev structure
7113  * @filter_op:operation will be taken.
7114  * @arg: a pointer to specific structure corresponding to the filter_op
7115  */
7116 static int
7117 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7118                                   enum rte_filter_op filter_op,
7119                                   void *arg)
7120 {
7121         int ret = 0;
7122
7123         if (filter_op == RTE_ETH_FILTER_NOP)
7124                 return 0;
7125
7126         if (arg == NULL) {
7127                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7128                             filter_op);
7129                 return -EINVAL;
7130         }
7131
7132         switch (filter_op) {
7133         case RTE_ETH_FILTER_ADD:
7134                 ret = ixgbe_dev_l2_tunnel_filter_add
7135                         (dev,
7136                          (struct rte_eth_l2_tunnel_conf *)arg);
7137                 break;
7138         case RTE_ETH_FILTER_DELETE:
7139                 ret = ixgbe_dev_l2_tunnel_filter_del
7140                         (dev,
7141                          (struct rte_eth_l2_tunnel_conf *)arg);
7142                 break;
7143         default:
7144                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7145                 ret = -EINVAL;
7146                 break;
7147         }
7148         return ret;
7149 }
7150
7151 static int
7152 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7153 {
7154         int ret = 0;
7155         uint32_t ctrl;
7156         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7157
7158         if (hw->mac.type != ixgbe_mac_X550 &&
7159             hw->mac.type != ixgbe_mac_X550EM_x &&
7160             hw->mac.type != ixgbe_mac_X550EM_a) {
7161                 return -ENOTSUP;
7162         }
7163
7164         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7165         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7166         if (en)
7167                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7168         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7169
7170         return ret;
7171 }
7172
7173 /* Enable l2 tunnel forwarding */
7174 static int
7175 ixgbe_dev_l2_tunnel_forwarding_enable
7176         (struct rte_eth_dev *dev,
7177          enum rte_eth_tunnel_type l2_tunnel_type)
7178 {
7179         int ret = 0;
7180
7181         switch (l2_tunnel_type) {
7182         case RTE_L2_TUNNEL_TYPE_E_TAG:
7183                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7184                 break;
7185         default:
7186                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7187                 ret = -EINVAL;
7188                 break;
7189         }
7190
7191         return ret;
7192 }
7193
7194 /* Disable l2 tunnel forwarding */
7195 static int
7196 ixgbe_dev_l2_tunnel_forwarding_disable
7197         (struct rte_eth_dev *dev,
7198          enum rte_eth_tunnel_type l2_tunnel_type)
7199 {
7200         int ret = 0;
7201
7202         switch (l2_tunnel_type) {
7203         case RTE_L2_TUNNEL_TYPE_E_TAG:
7204                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7205                 break;
7206         default:
7207                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7208                 ret = -EINVAL;
7209                 break;
7210         }
7211
7212         return ret;
7213 }
7214
7215 static int
7216 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7217                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7218                              bool en)
7219 {
7220         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7221         int ret = 0;
7222         uint32_t vmtir, vmvir;
7223         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7224
7225         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7226                 PMD_DRV_LOG(ERR,
7227                             "VF id %u should be less than %u",
7228                             l2_tunnel->vf_id,
7229                             pci_dev->max_vfs);
7230                 return -EINVAL;
7231         }
7232
7233         if (hw->mac.type != ixgbe_mac_X550 &&
7234             hw->mac.type != ixgbe_mac_X550EM_x &&
7235             hw->mac.type != ixgbe_mac_X550EM_a) {
7236                 return -ENOTSUP;
7237         }
7238
7239         if (en)
7240                 vmtir = l2_tunnel->tunnel_id;
7241         else
7242                 vmtir = 0;
7243
7244         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7245
7246         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7247         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7248         if (en)
7249                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7250         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7251
7252         return ret;
7253 }
7254
7255 /* Enable l2 tunnel tag insertion */
7256 static int
7257 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7258                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7259 {
7260         int ret = 0;
7261
7262         switch (l2_tunnel->l2_tunnel_type) {
7263         case RTE_L2_TUNNEL_TYPE_E_TAG:
7264                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7265                 break;
7266         default:
7267                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7268                 ret = -EINVAL;
7269                 break;
7270         }
7271
7272         return ret;
7273 }
7274
7275 /* Disable l2 tunnel tag insertion */
7276 static int
7277 ixgbe_dev_l2_tunnel_insertion_disable
7278         (struct rte_eth_dev *dev,
7279          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7280 {
7281         int ret = 0;
7282
7283         switch (l2_tunnel->l2_tunnel_type) {
7284         case RTE_L2_TUNNEL_TYPE_E_TAG:
7285                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7286                 break;
7287         default:
7288                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7289                 ret = -EINVAL;
7290                 break;
7291         }
7292
7293         return ret;
7294 }
7295
7296 static int
7297 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7298                              bool en)
7299 {
7300         int ret = 0;
7301         uint32_t qde;
7302         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7303
7304         if (hw->mac.type != ixgbe_mac_X550 &&
7305             hw->mac.type != ixgbe_mac_X550EM_x &&
7306             hw->mac.type != ixgbe_mac_X550EM_a) {
7307                 return -ENOTSUP;
7308         }
7309
7310         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7311         if (en)
7312                 qde |= IXGBE_QDE_STRIP_TAG;
7313         else
7314                 qde &= ~IXGBE_QDE_STRIP_TAG;
7315         qde &= ~IXGBE_QDE_READ;
7316         qde |= IXGBE_QDE_WRITE;
7317         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7318
7319         return ret;
7320 }
7321
7322 /* Enable l2 tunnel tag stripping */
7323 static int
7324 ixgbe_dev_l2_tunnel_stripping_enable
7325         (struct rte_eth_dev *dev,
7326          enum rte_eth_tunnel_type l2_tunnel_type)
7327 {
7328         int ret = 0;
7329
7330         switch (l2_tunnel_type) {
7331         case RTE_L2_TUNNEL_TYPE_E_TAG:
7332                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7333                 break;
7334         default:
7335                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7336                 ret = -EINVAL;
7337                 break;
7338         }
7339
7340         return ret;
7341 }
7342
7343 /* Disable l2 tunnel tag stripping */
7344 static int
7345 ixgbe_dev_l2_tunnel_stripping_disable
7346         (struct rte_eth_dev *dev,
7347          enum rte_eth_tunnel_type l2_tunnel_type)
7348 {
7349         int ret = 0;
7350
7351         switch (l2_tunnel_type) {
7352         case RTE_L2_TUNNEL_TYPE_E_TAG:
7353                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7354                 break;
7355         default:
7356                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7357                 ret = -EINVAL;
7358                 break;
7359         }
7360
7361         return ret;
7362 }
7363
7364 /* Enable/disable l2 tunnel offload functions */
7365 static int
7366 ixgbe_dev_l2_tunnel_offload_set
7367         (struct rte_eth_dev *dev,
7368          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7369          uint32_t mask,
7370          uint8_t en)
7371 {
7372         int ret = 0;
7373
7374         if (l2_tunnel == NULL)
7375                 return -EINVAL;
7376
7377         ret = -EINVAL;
7378         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7379                 if (en)
7380                         ret = ixgbe_dev_l2_tunnel_enable(
7381                                 dev,
7382                                 l2_tunnel->l2_tunnel_type);
7383                 else
7384                         ret = ixgbe_dev_l2_tunnel_disable(
7385                                 dev,
7386                                 l2_tunnel->l2_tunnel_type);
7387         }
7388
7389         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7390                 if (en)
7391                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7392                                 dev,
7393                                 l2_tunnel);
7394                 else
7395                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7396                                 dev,
7397                                 l2_tunnel);
7398         }
7399
7400         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7401                 if (en)
7402                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7403                                 dev,
7404                                 l2_tunnel->l2_tunnel_type);
7405                 else
7406                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7407                                 dev,
7408                                 l2_tunnel->l2_tunnel_type);
7409         }
7410
7411         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7412                 if (en)
7413                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7414                                 dev,
7415                                 l2_tunnel->l2_tunnel_type);
7416                 else
7417                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7418                                 dev,
7419                                 l2_tunnel->l2_tunnel_type);
7420         }
7421
7422         return ret;
7423 }
7424
7425 static int
7426 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7427                         uint16_t port)
7428 {
7429         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7430         IXGBE_WRITE_FLUSH(hw);
7431
7432         return 0;
7433 }
7434
7435 /* There's only one register for VxLAN UDP port.
7436  * So, we cannot add several ports. Will update it.
7437  */
7438 static int
7439 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7440                      uint16_t port)
7441 {
7442         if (port == 0) {
7443                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7444                 return -EINVAL;
7445         }
7446
7447         return ixgbe_update_vxlan_port(hw, port);
7448 }
7449
7450 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7451  * UDP port, it must have a value.
7452  * So, will reset it to the original value 0.
7453  */
7454 static int
7455 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7456                      uint16_t port)
7457 {
7458         uint16_t cur_port;
7459
7460         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7461
7462         if (cur_port != port) {
7463                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7464                 return -EINVAL;
7465         }
7466
7467         return ixgbe_update_vxlan_port(hw, 0);
7468 }
7469
7470 /* Add UDP tunneling port */
7471 static int
7472 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7473                               struct rte_eth_udp_tunnel *udp_tunnel)
7474 {
7475         int ret = 0;
7476         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7477
7478         if (hw->mac.type != ixgbe_mac_X550 &&
7479             hw->mac.type != ixgbe_mac_X550EM_x &&
7480             hw->mac.type != ixgbe_mac_X550EM_a) {
7481                 return -ENOTSUP;
7482         }
7483
7484         if (udp_tunnel == NULL)
7485                 return -EINVAL;
7486
7487         switch (udp_tunnel->prot_type) {
7488         case RTE_TUNNEL_TYPE_VXLAN:
7489                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7490                 break;
7491
7492         case RTE_TUNNEL_TYPE_GENEVE:
7493         case RTE_TUNNEL_TYPE_TEREDO:
7494                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7495                 ret = -EINVAL;
7496                 break;
7497
7498         default:
7499                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7500                 ret = -EINVAL;
7501                 break;
7502         }
7503
7504         return ret;
7505 }
7506
7507 /* Remove UDP tunneling port */
7508 static int
7509 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7510                               struct rte_eth_udp_tunnel *udp_tunnel)
7511 {
7512         int ret = 0;
7513         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7514
7515         if (hw->mac.type != ixgbe_mac_X550 &&
7516             hw->mac.type != ixgbe_mac_X550EM_x &&
7517             hw->mac.type != ixgbe_mac_X550EM_a) {
7518                 return -ENOTSUP;
7519         }
7520
7521         if (udp_tunnel == NULL)
7522                 return -EINVAL;
7523
7524         switch (udp_tunnel->prot_type) {
7525         case RTE_TUNNEL_TYPE_VXLAN:
7526                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7527                 break;
7528         case RTE_TUNNEL_TYPE_GENEVE:
7529         case RTE_TUNNEL_TYPE_TEREDO:
7530                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7531                 ret = -EINVAL;
7532                 break;
7533         default:
7534                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7535                 ret = -EINVAL;
7536                 break;
7537         }
7538
7539         return ret;
7540 }
7541
7542 static void
7543 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7544 {
7545         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7546
7547         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7548 }
7549
7550 static void
7551 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7552 {
7553         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7554
7555         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7556 }
7557
7558 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7559 {
7560         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7561         u32 in_msg = 0;
7562
7563         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7564                 return;
7565
7566         /* PF reset VF event */
7567         if (in_msg == IXGBE_PF_CONTROL_MSG)
7568                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7569 }
7570
7571 static int
7572 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7573 {
7574         uint32_t eicr;
7575         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7576         struct ixgbe_interrupt *intr =
7577                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7578         ixgbevf_intr_disable(hw);
7579
7580         /* read-on-clear nic registers here */
7581         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7582         intr->flags = 0;
7583
7584         /* only one misc vector supported - mailbox */
7585         eicr &= IXGBE_VTEICR_MASK;
7586         if (eicr == IXGBE_MISC_VEC_ID)
7587                 intr->flags |= IXGBE_FLAG_MAILBOX;
7588
7589         return 0;
7590 }
7591
7592 static int
7593 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7594 {
7595         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7596         struct ixgbe_interrupt *intr =
7597                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7598
7599         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7600                 ixgbevf_mbx_process(dev);
7601                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7602         }
7603
7604         ixgbevf_intr_enable(hw);
7605
7606         return 0;
7607 }
7608
7609 static void
7610 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7611                               void *param)
7612 {
7613         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7614
7615         ixgbevf_dev_interrupt_get_status(dev);
7616         ixgbevf_dev_interrupt_action(dev);
7617 }
7618
7619 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
7620 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
7621 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
7622 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
7623 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
7624 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");