drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63 #include <rte_hash_crc.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "base/ixgbe_api.h"
  67 #include "base/ixgbe_vf.h"
  68 #include "base/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72 #include "base/ixgbe_type.h"
  73 #include "base/ixgbe_phy.h"
  74 #include "ixgbe_regs.h"
  75
  76 #include "rte_pmd_ixgbe.h"
  77
  78 /*
  79  * High threshold controlling when to start sending XOFF frames. Must be at
  80  * least 8 bytes less than receive packet buffer size. This value is in units
  81  * of 1024 bytes.
  82  */
  83 #define IXGBE_FC_HI    0x80
  84
  85 /*
  86  * Low threshold controlling when to start sending XON frames. This value is
  87  * in units of 1024 bytes.
  88  */
  89 #define IXGBE_FC_LO    0x40
  90
  91 /* Default minimum inter-interrupt interval for EITR configuration */
  92 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  93
  94 /* Timer value included in XOFF frames. */
  95 #define IXGBE_FC_PAUSE 0x680
  96
  97 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  98 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  99 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
 100
 101 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 102 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 103 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 104
 105 /*
 106  *  Default values for RX/TX configuration
 107  */
 108 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 109 #define IXGBE_DEFAULT_RX_PTHRESH      8
 110 #define IXGBE_DEFAULT_RX_HTHRESH      8
 111 #define IXGBE_DEFAULT_RX_WTHRESH      0
 112
 113 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 114 #define IXGBE_DEFAULT_TX_PTHRESH      32
 115 #define IXGBE_DEFAULT_TX_HTHRESH      0
 116 #define IXGBE_DEFAULT_TX_WTHRESH      0
 117 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 118
 119 /* Bit shift and mask */
 120 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 121 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 122 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 123 #define IXGBE_8_BIT_MASK   UINT8_MAX
 124
 125 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 126
 127 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 128
 129 #define IXGBE_HKEY_MAX_INDEX 10
 130
 131 /* Additional timesync values. */
 132 #define NSEC_PER_SEC             1000000000L
 133 #define IXGBE_INCVAL_10GB        0x66666666
 134 #define IXGBE_INCVAL_1GB         0x40000000
 135 #define IXGBE_INCVAL_100         0x50000000
 136 #define IXGBE_INCVAL_SHIFT_10GB  28
 137 #define IXGBE_INCVAL_SHIFT_1GB   24
 138 #define IXGBE_INCVAL_SHIFT_100   21
 139 #define IXGBE_INCVAL_SHIFT_82599 7
 140 #define IXGBE_INCPER_SHIFT_82599 24
 141
 142 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 143
 144 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 145 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 146 #define DEFAULT_ETAG_ETYPE                     0x893f
 147 #define IXGBE_ETAG_ETYPE                       0x00005084
 148 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 149 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 150 #define IXGBE_RAH_ADTYPE                       0x40000000
 151 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 152 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 153 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 154 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 155 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 156 #define IXGBE_VTEICR_MASK                      0x07
 157
 158 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 159 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 160
 161 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 162 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 163 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 166 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 167 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 168 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 179                                 int wait_to_complete);
 180 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_stats *stats);
 182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_xstat *xstats, unsigned n);
 184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 185                                   struct rte_eth_xstat *xstats, unsigned n);
 186 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 187 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 188 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 189         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 190 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 192 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 193                                              uint16_t queue_id,
 194                                              uint8_t stat_idx,
 195                                              uint8_t is_rx);
 196 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 197                                  size_t fw_size);
 198 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 199                                struct rte_eth_dev_info *dev_info);
 200 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 201 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 202                                  struct rte_eth_dev_info *dev_info);
 203 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 204
 205 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 206                 uint16_t vlan_id, int on);
 207 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 208                                enum rte_vlan_type vlan_type,
 209                                uint16_t tpid_id);
 210 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 211                 uint16_t queue, bool on);
 212 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 213                 int on);
 214 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 215 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 216 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 217 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 218 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 219
 220 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 222 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 223                                struct rte_eth_fc_conf *fc_conf);
 224 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 225                                struct rte_eth_fc_conf *fc_conf);
 226 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 227                 struct rte_eth_pfc_conf *pfc_conf);
 228 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 229                         struct rte_eth_rss_reta_entry64 *reta_conf,
 230                         uint16_t reta_size);
 231 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 232                         struct rte_eth_rss_reta_entry64 *reta_conf,
 233                         uint16_t reta_size);
 234 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 235 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 237 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 238 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 239 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 240                                       struct rte_intr_handle *handle);
 241 static void ixgbe_dev_interrupt_handler(void *param);
 242 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 243 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 244                 uint32_t index, uint32_t pool);
 245 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 246 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 247                                            struct ether_addr *mac_addr);
 248 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 249 static bool is_device_supported(struct rte_eth_dev *dev,
 250                                 struct eth_driver *drv);
 251
 252 /* For Virtual Function support */
 253 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 254 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 255 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 256 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 257 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 258 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 259 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 260 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 261 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 262                 struct rte_eth_stats *stats);
 263 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 264 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 265                 uint16_t vlan_id, int on);
 266 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 267                 uint16_t queue, int on);
 268 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 269 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 270 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 271                                             uint16_t queue_id);
 272 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 273                                              uint16_t queue_id);
 274 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 275                                  uint8_t queue, uint8_t msix_vector);
 276 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 277 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 298                 uint16_t queue_idx, uint16_t tx_rate);
 299
 300 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 301                                  struct ether_addr *mac_addr,
 302                                  uint32_t index, uint32_t pool);
 303 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 304 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 305                                              struct ether_addr *mac_addr);
 306 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 307                         struct rte_eth_syn_filter *filter);
 308 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 309                         enum rte_filter_op filter_op,
 310                         void *arg);
 311 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 312                         struct ixgbe_5tuple_filter *filter);
 313 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 314                         struct ixgbe_5tuple_filter *filter);
 315 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 316                                 enum rte_filter_op filter_op,
 317                                 void *arg);
 318 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 319                         struct rte_eth_ntuple_filter *filter);
 320 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 321                                 enum rte_filter_op filter_op,
 322                                 void *arg);
 323 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 324                         struct rte_eth_ethertype_filter *filter);
 325 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 326                      enum rte_filter_type filter_type,
 327                      enum rte_filter_op filter_op,
 328                      void *arg);
 329 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 330
 331 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 332                                       struct ether_addr *mc_addr_set,
 333                                       uint32_t nb_mc_addr);
 334 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 335                                    struct rte_eth_dcb_info *dcb_info);
 336
 337 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 338 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 339                             struct rte_dev_reg_info *regs);
 340 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 341 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 342                                 struct rte_dev_eeprom_info *eeprom);
 343 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 344                                 struct rte_dev_eeprom_info *eeprom);
 345
 346 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 347 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 348                                 struct rte_dev_reg_info *regs);
 349
 350 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 351 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 352 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 353                                             struct timespec *timestamp,
 354                                             uint32_t flags);
 355 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 356                                             struct timespec *timestamp);
 357 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 358 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 359                                    struct timespec *timestamp);
 360 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 361                                    const struct timespec *timestamp);
 362 static void ixgbevf_dev_interrupt_handler(void *param);
 363
 364 static int ixgbe_dev_l2_tunnel_eth_type_conf
 365         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 366 static int ixgbe_dev_l2_tunnel_offload_set
 367         (struct rte_eth_dev *dev,
 368          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 369          uint32_t mask,
 370          uint8_t en);
 371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 372                                              enum rte_filter_op filter_op,
 373                                              void *arg);
 374
 375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 376                                          struct rte_eth_udp_tunnel *udp_tunnel);
 377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 380 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 381
 382 /*
 383  * Define VF Stats MACRO for Non "cleared on read" register
 384  */
 385 #define UPDATE_VF_STAT(reg, last, cur)                          \
 386 {                                                               \
 387         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 388         cur += (latest - last) & UINT_MAX;                      \
 389         last = latest;                                          \
 390 }
 391
 392 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 393 {                                                                \
 394         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 395         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 396         u64 latest = ((new_msb << 32) | new_lsb);                \
 397         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 398         last = latest;                                           \
 399 }
 400
 401 #define IXGBE_SET_HWSTRIP(h, q) do {\
 402                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 403                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 404                 (h)->bitmap[idx] |= 1 << bit;\
 405         } while (0)
 406
 407 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 408                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 409                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 410                 (h)->bitmap[idx] &= ~(1 << bit);\
 411         } while (0)
 412
 413 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 414                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 415                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 416                 (r) = (h)->bitmap[idx] >> bit & 1;\
 417         } while (0)
 418
 419 /*
 420  * The set of PCI devices this driver supports
 421  */
 422 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 476 #ifdef RTE_NIC_BYPASS
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 478 #endif
 479         { .vendor_id = 0, /* sentinel */ },
 480 };
 481
 482 /*
 483  * The set of PCI devices this driver supports (for 82599 VF)
 484  */
 485 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 496         { .vendor_id = 0, /* sentinel */ },
 497 };
 498
 499 static const struct rte_eth_desc_lim rx_desc_lim = {
 500         .nb_max = IXGBE_MAX_RING_DESC,
 501         .nb_min = IXGBE_MIN_RING_DESC,
 502         .nb_align = IXGBE_RXD_ALIGN,
 503 };
 504
 505 static const struct rte_eth_desc_lim tx_desc_lim = {
 506         .nb_max = IXGBE_MAX_RING_DESC,
 507         .nb_min = IXGBE_MIN_RING_DESC,
 508         .nb_align = IXGBE_TXD_ALIGN,
 509         .nb_seg_max = IXGBE_TX_MAX_SEG,
 510         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 511 };
 512
 513 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 514         .dev_configure        = ixgbe_dev_configure,
 515         .dev_start            = ixgbe_dev_start,
 516         .dev_stop             = ixgbe_dev_stop,
 517         .dev_set_link_up    = ixgbe_dev_set_link_up,
 518         .dev_set_link_down  = ixgbe_dev_set_link_down,
 519         .dev_close            = ixgbe_dev_close,
 520         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 521         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 522         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 523         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 524         .link_update          = ixgbe_dev_link_update,
 525         .stats_get            = ixgbe_dev_stats_get,
 526         .xstats_get           = ixgbe_dev_xstats_get,
 527         .stats_reset          = ixgbe_dev_stats_reset,
 528         .xstats_reset         = ixgbe_dev_xstats_reset,
 529         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 530         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 531         .fw_version_get       = ixgbe_fw_version_get,
 532         .dev_infos_get        = ixgbe_dev_info_get,
 533         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 534         .mtu_set              = ixgbe_dev_mtu_set,
 535         .vlan_filter_set      = ixgbe_vlan_filter_set,
 536         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 537         .vlan_offload_set     = ixgbe_vlan_offload_set,
 538         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 539         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 540         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 541         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 542         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 543         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 544         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 545         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 546         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 547         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 548         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 549         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 550         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 551         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 552         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 553         .dev_led_on           = ixgbe_dev_led_on,
 554         .dev_led_off          = ixgbe_dev_led_off,
 555         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 556         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 557         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 558         .mac_addr_add         = ixgbe_add_rar,
 559         .mac_addr_remove      = ixgbe_remove_rar,
 560         .mac_addr_set         = ixgbe_set_default_mac_addr,
 561         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 562         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 563         .mirror_rule_set      = ixgbe_mirror_rule_set,
 564         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 565         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 566         .reta_update          = ixgbe_dev_rss_reta_update,
 567         .reta_query           = ixgbe_dev_rss_reta_query,
 568 #ifdef RTE_NIC_BYPASS
 569         .bypass_init          = ixgbe_bypass_init,
 570         .bypass_state_set     = ixgbe_bypass_state_store,
 571         .bypass_state_show    = ixgbe_bypass_state_show,
 572         .bypass_event_set     = ixgbe_bypass_event_store,
 573         .bypass_event_show    = ixgbe_bypass_event_show,
 574         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 575         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 576         .bypass_ver_show      = ixgbe_bypass_ver_show,
 577         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 578 #endif /* RTE_NIC_BYPASS */
 579         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 580         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 581         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 582         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 583         .rxq_info_get         = ixgbe_rxq_info_get,
 584         .txq_info_get         = ixgbe_txq_info_get,
 585         .timesync_enable      = ixgbe_timesync_enable,
 586         .timesync_disable     = ixgbe_timesync_disable,
 587         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 588         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 589         .get_reg              = ixgbe_get_regs,
 590         .get_eeprom_length    = ixgbe_get_eeprom_length,
 591         .get_eeprom           = ixgbe_get_eeprom,
 592         .set_eeprom           = ixgbe_set_eeprom,
 593         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 594         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 595         .timesync_read_time   = ixgbe_timesync_read_time,
 596         .timesync_write_time  = ixgbe_timesync_write_time,
 597         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 598         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 599         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 600         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 601 };
 602
 603 /*
 604  * dev_ops for virtual function, bare necessities for basic vf
 605  * operation have been implemented
 606  */
 607 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 608         .dev_configure        = ixgbevf_dev_configure,
 609         .dev_start            = ixgbevf_dev_start,
 610         .dev_stop             = ixgbevf_dev_stop,
 611         .link_update          = ixgbe_dev_link_update,
 612         .stats_get            = ixgbevf_dev_stats_get,
 613         .xstats_get           = ixgbevf_dev_xstats_get,
 614         .stats_reset          = ixgbevf_dev_stats_reset,
 615         .xstats_reset         = ixgbevf_dev_stats_reset,
 616         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 617         .dev_close            = ixgbevf_dev_close,
 618         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 619         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 620         .dev_infos_get        = ixgbevf_dev_info_get,
 621         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 622         .mtu_set              = ixgbevf_dev_set_mtu,
 623         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 624         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 625         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 626         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 627         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 628         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 629         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 630         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 631         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 632         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 633         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 634         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 635         .mac_addr_add         = ixgbevf_add_mac_addr,
 636         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 637         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 638         .rxq_info_get         = ixgbe_rxq_info_get,
 639         .txq_info_get         = ixgbe_txq_info_get,
 640         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 641         .get_reg              = ixgbevf_get_regs,
 642         .reta_update          = ixgbe_dev_rss_reta_update,
 643         .reta_query           = ixgbe_dev_rss_reta_query,
 644         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 645         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 646 };
 647
 648 /* store statistics names and its offset in stats structure */
 649 struct rte_ixgbe_xstats_name_off {
 650         char name[RTE_ETH_XSTATS_NAME_SIZE];
 651         unsigned offset;
 652 };
 653
 654 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 655         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 656         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 657         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 658         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 659         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 660         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 661         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 662         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 663         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 664         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 665         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 666         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 667         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 668         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 669         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 670                 prc1023)},
 671         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 672                 prc1522)},
 673         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 674         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 675         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 676         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 677         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 678         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 679         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 680         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 681         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 682         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 683         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 684         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 685         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 686         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 687         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 688         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 689         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 690                 ptc1023)},
 691         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 692                 ptc1522)},
 693         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 694         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 695         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 696         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 697
 698         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 699                 fdirustat_add)},
 700         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 701                 fdirustat_remove)},
 702         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 703                 fdirfstat_fadd)},
 704         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 705                 fdirfstat_fremove)},
 706         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 707                 fdirmatch)},
 708         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 709                 fdirmiss)},
 710
 711         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 712         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 713         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 714                 fclast)},
 715         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 716         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 717         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 718         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 719         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 720                 fcoe_noddp)},
 721         {"rx_fcoe_no_direct_data_placement_ext_buff",
 722                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 723
 724         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 725                 lxontxc)},
 726         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 727                 lxonrxc)},
 728         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 729                 lxofftxc)},
 730         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 731                 lxoffrxc)},
 732         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 733 };
 734
 735 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 736                            sizeof(rte_ixgbe_stats_strings[0]))
 737
 738 /* MACsec statistics */
 739 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 740         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 741                 out_pkts_untagged)},
 742         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 743                 out_pkts_encrypted)},
 744         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 745                 out_pkts_protected)},
 746         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 747                 out_octets_encrypted)},
 748         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 749                 out_octets_protected)},
 750         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_untagged)},
 752         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_badtag)},
 754         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_nosci)},
 756         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 757                 in_pkts_unknownsci)},
 758         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 759                 in_octets_decrypted)},
 760         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 761                 in_octets_validated)},
 762         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_unchecked)},
 764         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 765                 in_pkts_delayed)},
 766         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_late)},
 768         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_ok)},
 770         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 771                 in_pkts_invalid)},
 772         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_notvalid)},
 774         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_unusedsa)},
 776         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 777                 in_pkts_notusingsa)},
 778 };
 779
 780 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 781                            sizeof(rte_ixgbe_macsec_strings[0]))
 782
 783 /* Per-queue statistics */
 784 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 785         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 786         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 787         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 788         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 789 };
 790
 791 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 792                            sizeof(rte_ixgbe_rxq_strings[0]))
 793 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 794
 795 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 796         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 797         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 798         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 799                 pxon2offc)},
 800 };
 801
 802 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 803                            sizeof(rte_ixgbe_txq_strings[0]))
 804 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 805
 806 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 807         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 808 };
 809
 810 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 811                 sizeof(rte_ixgbevf_stats_strings[0]))
 812
 813 /**
 814  * Atomically reads the link status information from global
 815  * structure rte_eth_dev.
 816  *
 817  * @param dev
 818  *   - Pointer to the structure rte_eth_dev to read from.
 819  *   - Pointer to the buffer to be saved with the link status.
 820  *
 821  * @return
 822  *   - On success, zero.
 823  *   - On failure, negative value.
 824  */
 825 static inline int
 826 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 827                                 struct rte_eth_link *link)
 828 {
 829         struct rte_eth_link *dst = link;
 830         struct rte_eth_link *src = &(dev->data->dev_link);
 831
 832         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 833                                         *(uint64_t *)src) == 0)
 834                 return -1;
 835
 836         return 0;
 837 }
 838
 839 /**
 840  * Atomically writes the link status information into global
 841  * structure rte_eth_dev.
 842  *
 843  * @param dev
 844  *   - Pointer to the structure rte_eth_dev to read from.
 845  *   - Pointer to the buffer to be saved with the link status.
 846  *
 847  * @return
 848  *   - On success, zero.
 849  *   - On failure, negative value.
 850  */
 851 static inline int
 852 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 853                                 struct rte_eth_link *link)
 854 {
 855         struct rte_eth_link *dst = &(dev->data->dev_link);
 856         struct rte_eth_link *src = link;
 857
 858         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 859                                         *(uint64_t *)src) == 0)
 860                 return -1;
 861
 862         return 0;
 863 }
 864
 865 /*
 866  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 867  */
 868 static inline int
 869 ixgbe_is_sfp(struct ixgbe_hw *hw)
 870 {
 871         switch (hw->phy.type) {
 872         case ixgbe_phy_sfp_avago:
 873         case ixgbe_phy_sfp_ftl:
 874         case ixgbe_phy_sfp_intel:
 875         case ixgbe_phy_sfp_unknown:
 876         case ixgbe_phy_sfp_passive_tyco:
 877         case ixgbe_phy_sfp_passive_unknown:
 878                 return 1;
 879         default:
 880                 return 0;
 881         }
 882 }
 883
 884 static inline int32_t
 885 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 886 {
 887         uint32_t ctrl_ext;
 888         int32_t status;
 889
 890         status = ixgbe_reset_hw(hw);
 891
 892         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 893         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 894         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 895         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 896         IXGBE_WRITE_FLUSH(hw);
 897
 898         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 899                 status = IXGBE_SUCCESS;
 900         return status;
 901 }
 902
 903 static inline void
 904 ixgbe_enable_intr(struct rte_eth_dev *dev)
 905 {
 906         struct ixgbe_interrupt *intr =
 907                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 908         struct ixgbe_hw *hw =
 909                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 910
 911         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 912         IXGBE_WRITE_FLUSH(hw);
 913 }
 914
 915 /*
 916  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 917  */
 918 static void
 919 ixgbe_disable_intr(struct ixgbe_hw *hw)
 920 {
 921         PMD_INIT_FUNC_TRACE();
 922
 923         if (hw->mac.type == ixgbe_mac_82598EB) {
 924                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 925         } else {
 926                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 927                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 928                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 929         }
 930         IXGBE_WRITE_FLUSH(hw);
 931 }
 932
 933 /*
 934  * This function resets queue statistics mapping registers.
 935  * From Niantic datasheet, Initialization of Statistics section:
 936  * "...if software requires the queue counters, the RQSMR and TQSM registers
 937  * must be re-programmed following a device reset.
 938  */
 939 static void
 940 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 941 {
 942         uint32_t i;
 943
 944         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 945                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 946                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 947         }
 948 }
 949
 950
 951 static int
 952 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 953                                   uint16_t queue_id,
 954                                   uint8_t stat_idx,
 955                                   uint8_t is_rx)
 956 {
 957 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 958 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 959 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 960
 961         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 962         struct ixgbe_stat_mapping_registers *stat_mappings =
 963                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 964         uint32_t qsmr_mask = 0;
 965         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 966         uint32_t q_map;
 967         uint8_t n, offset;
 968
 969         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 970                 (hw->mac.type != ixgbe_mac_X540) &&
 971                 (hw->mac.type != ixgbe_mac_X550) &&
 972                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 973                 (hw->mac.type != ixgbe_mac_X550EM_a))
 974                 return -ENOSYS;
 975
 976         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 977                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 978                      queue_id, stat_idx);
 979
 980         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 981         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 982                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 983                 return -EIO;
 984         }
 985         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 986
 987         /* Now clear any previous stat_idx set */
 988         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 989         if (!is_rx)
 990                 stat_mappings->tqsm[n] &= ~clearing_mask;
 991         else
 992                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 993
 994         q_map = (uint32_t)stat_idx;
 995         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 996         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 997         if (!is_rx)
 998                 stat_mappings->tqsm[n] |= qsmr_mask;
 999         else
1000                 stat_mappings->rqsmr[n] |= qsmr_mask;
1001
1002         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1003                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1004                      queue_id, stat_idx);
1005         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1006                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1007
1008         /* Now write the mapping in the appropriate register */
1009         if (is_rx) {
1010                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1011                              stat_mappings->rqsmr[n], n);
1012                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1013         } else {
1014                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1015                              stat_mappings->tqsm[n], n);
1016                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1017         }
1018         return 0;
1019 }
1020
1021 static void
1022 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1023 {
1024         struct ixgbe_stat_mapping_registers *stat_mappings =
1025                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1026         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1027         int i;
1028
1029         /* write whatever was in stat mapping table to the NIC */
1030         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1031                 /* rx */
1032                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1033
1034                 /* tx */
1035                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1036         }
1037 }
1038
1039 static void
1040 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1041 {
1042         uint8_t i;
1043         struct ixgbe_dcb_tc_config *tc;
1044         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1045
1046         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1047         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1048         for (i = 0; i < dcb_max_tc; i++) {
1049                 tc = &dcb_config->tc_config[i];
1050                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1051                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1052                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1053                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1054                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1055                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1056                 tc->pfc = ixgbe_dcb_pfc_disabled;
1057         }
1058
1059         /* Initialize default user to priority mapping, UPx->TC0 */
1060         tc = &dcb_config->tc_config[0];
1061         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1062         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1063         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1064                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1065                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1066         }
1067         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1068         dcb_config->pfc_mode_enable = false;
1069         dcb_config->vt_mode = true;
1070         dcb_config->round_robin_enable = false;
1071         /* support all DCB capabilities in 82599 */
1072         dcb_config->support.capabilities = 0xFF;
1073
1074         /*we only support 4 Tcs for X540, X550 */
1075         if (hw->mac.type == ixgbe_mac_X540 ||
1076                 hw->mac.type == ixgbe_mac_X550 ||
1077                 hw->mac.type == ixgbe_mac_X550EM_x ||
1078                 hw->mac.type == ixgbe_mac_X550EM_a) {
1079                 dcb_config->num_tcs.pg_tcs = 4;
1080                 dcb_config->num_tcs.pfc_tcs = 4;
1081         }
1082 }
1083
1084 /*
1085  * Ensure that all locks are released before first NVM or PHY access
1086  */
1087 static void
1088 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1089 {
1090         uint16_t mask;
1091
1092         /*
1093          * Phy lock should not fail in this early stage. If this is the case,
1094          * it is due to an improper exit of the application.
1095          * So force the release of the faulty lock. Release of common lock
1096          * is done automatically by swfw_sync function.
1097          */
1098         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1099         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1100                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1101         }
1102         ixgbe_release_swfw_semaphore(hw, mask);
1103
1104         /*
1105          * These ones are more tricky since they are common to all ports; but
1106          * swfw_sync retries last long enough (1s) to be almost sure that if
1107          * lock can not be taken it is due to an improper lock of the
1108          * semaphore.
1109          */
1110         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1111         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1112                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1113         }
1114         ixgbe_release_swfw_semaphore(hw, mask);
1115 }
1116
1117 /*
1118  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1119  * It returns 0 on success.
1120  */
1121 static int
1122 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1123 {
1124         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1125         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1126         struct ixgbe_hw *hw =
1127                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1128         struct ixgbe_vfta *shadow_vfta =
1129                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1130         struct ixgbe_hwstrip *hwstrip =
1131                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1132         struct ixgbe_dcb_config *dcb_config =
1133                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1134         struct ixgbe_filter_info *filter_info =
1135                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1136         struct ixgbe_bw_conf *bw_conf =
1137                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1138         uint32_t ctrl_ext;
1139         uint16_t csum;
1140         int diag, i;
1141
1142         PMD_INIT_FUNC_TRACE();
1143
1144         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1145         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1146         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1147         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1148
1149         /*
1150          * For secondary processes, we don't initialise any further as primary
1151          * has already done this work. Only check we don't need a different
1152          * RX and TX function.
1153          */
1154         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1155                 struct ixgbe_tx_queue *txq;
1156                 /* TX queue function in primary, set by last queue initialized
1157                  * Tx queue may not initialized by primary process
1158                  */
1159                 if (eth_dev->data->tx_queues) {
1160                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1161                         ixgbe_set_tx_function(eth_dev, txq);
1162                 } else {
1163                         /* Use default TX function if we get here */
1164                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1165                                      "Using default TX function.");
1166                 }
1167
1168                 ixgbe_set_rx_function(eth_dev);
1169
1170                 return 0;
1171         }
1172
1173         rte_eth_copy_pci_info(eth_dev, pci_dev);
1174         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1175
1176         /* Vendor and Device ID need to be set before init of shared code */
1177         hw->device_id = pci_dev->id.device_id;
1178         hw->vendor_id = pci_dev->id.vendor_id;
1179         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1180         hw->allow_unsupported_sfp = 1;
1181
1182         /* Initialize the shared code (base driver) */
1183 #ifdef RTE_NIC_BYPASS
1184         diag = ixgbe_bypass_init_shared_code(hw);
1185 #else
1186         diag = ixgbe_init_shared_code(hw);
1187 #endif /* RTE_NIC_BYPASS */
1188
1189         if (diag != IXGBE_SUCCESS) {
1190                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1191                 return -EIO;
1192         }
1193
1194         /* pick up the PCI bus settings for reporting later */
1195         ixgbe_get_bus_info(hw);
1196
1197         /* Unlock any pending hardware semaphore */
1198         ixgbe_swfw_lock_reset(hw);
1199
1200         /* Initialize DCB configuration*/
1201         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1202         ixgbe_dcb_init(hw, dcb_config);
1203         /* Get Hardware Flow Control setting */
1204         hw->fc.requested_mode = ixgbe_fc_full;
1205         hw->fc.current_mode = ixgbe_fc_full;
1206         hw->fc.pause_time = IXGBE_FC_PAUSE;
1207         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1208                 hw->fc.low_water[i] = IXGBE_FC_LO;
1209                 hw->fc.high_water[i] = IXGBE_FC_HI;
1210         }
1211         hw->fc.send_xon = 1;
1212
1213         /* Make sure we have a good EEPROM before we read from it */
1214         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1215         if (diag != IXGBE_SUCCESS) {
1216                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1217                 return -EIO;
1218         }
1219
1220 #ifdef RTE_NIC_BYPASS
1221         diag = ixgbe_bypass_init_hw(hw);
1222 #else
1223         diag = ixgbe_init_hw(hw);
1224 #endif /* RTE_NIC_BYPASS */
1225
1226         /*
1227          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1228          * is called too soon after the kernel driver unbinding/binding occurs.
1229          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1230          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1231          * also called. See ixgbe_identify_phy_82599(). The reason for the
1232          * failure is not known, and only occuts when virtualisation features
1233          * are disabled in the bios. A delay of 100ms  was found to be enough by
1234          * trial-and-error, and is doubled to be safe.
1235          */
1236         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1237                 rte_delay_ms(200);
1238                 diag = ixgbe_init_hw(hw);
1239         }
1240
1241         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1242                 diag = IXGBE_SUCCESS;
1243
1244         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1245                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1246                              "LOM.  Please be aware there may be issues associated "
1247                              "with your hardware.");
1248                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1249                              "please contact your Intel or hardware representative "
1250                              "who provided you with this hardware.");
1251         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1252                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1253         if (diag) {
1254                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1255                 return -EIO;
1256         }
1257
1258         /* Reset the hw statistics */
1259         ixgbe_dev_stats_reset(eth_dev);
1260
1261         /* disable interrupt */
1262         ixgbe_disable_intr(hw);
1263
1264         /* reset mappings for queue statistics hw counters*/
1265         ixgbe_reset_qstat_mappings(hw);
1266
1267         /* Allocate memory for storing MAC addresses */
1268         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1269                                                hw->mac.num_rar_entries, 0);
1270         if (eth_dev->data->mac_addrs == NULL) {
1271                 PMD_INIT_LOG(ERR,
1272                              "Failed to allocate %u bytes needed to store "
1273                              "MAC addresses",
1274                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1275                 return -ENOMEM;
1276         }
1277         /* Copy the permanent MAC address */
1278         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1279                         &eth_dev->data->mac_addrs[0]);
1280
1281         /* Allocate memory for storing hash filter MAC addresses */
1282         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1283                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1284         if (eth_dev->data->hash_mac_addrs == NULL) {
1285                 PMD_INIT_LOG(ERR,
1286                              "Failed to allocate %d bytes needed to store MAC addresses",
1287                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1288                 return -ENOMEM;
1289         }
1290
1291         /* initialize the vfta */
1292         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1293
1294         /* initialize the hw strip bitmap*/
1295         memset(hwstrip, 0, sizeof(*hwstrip));
1296
1297         /* initialize PF if max_vfs not zero */
1298         ixgbe_pf_host_init(eth_dev);
1299
1300         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1301         /* let hardware know driver is loaded */
1302         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1303         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1304         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1305         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1306         IXGBE_WRITE_FLUSH(hw);
1307
1308         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1309                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1310                              (int) hw->mac.type, (int) hw->phy.type,
1311                              (int) hw->phy.sfp_type);
1312         else
1313                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1314                              (int) hw->mac.type, (int) hw->phy.type);
1315
1316         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1317                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1318                      pci_dev->id.device_id);
1319
1320         rte_intr_callback_register(intr_handle,
1321                                    ixgbe_dev_interrupt_handler, eth_dev);
1322
1323         /* enable uio/vfio intr/eventfd mapping */
1324         rte_intr_enable(intr_handle);
1325
1326         /* enable support intr */
1327         ixgbe_enable_intr(eth_dev);
1328
1329         /* initialize filter info */
1330         memset(filter_info, 0,
1331                sizeof(struct ixgbe_filter_info));
1332
1333         /* initialize 5tuple filter list */
1334         TAILQ_INIT(&filter_info->fivetuple_list);
1335
1336         /* initialize flow director filter list & hash */
1337         ixgbe_fdir_filter_init(eth_dev);
1338
1339         /* initialize l2 tunnel filter list & hash */
1340         ixgbe_l2_tn_filter_init(eth_dev);
1341
1342         TAILQ_INIT(&filter_ntuple_list);
1343         TAILQ_INIT(&filter_ethertype_list);
1344         TAILQ_INIT(&filter_syn_list);
1345         TAILQ_INIT(&filter_fdir_list);
1346         TAILQ_INIT(&filter_l2_tunnel_list);
1347         TAILQ_INIT(&ixgbe_flow_list);
1348
1349         /* initialize bandwidth configuration info */
1350         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1351
1352         return 0;
1353 }
1354
1355 static int
1356 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1357 {
1358         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1359         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1360         struct ixgbe_hw *hw;
1361
1362         PMD_INIT_FUNC_TRACE();
1363
1364         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1365                 return -EPERM;
1366
1367         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1368
1369         if (hw->adapter_stopped == 0)
1370                 ixgbe_dev_close(eth_dev);
1371
1372         eth_dev->dev_ops = NULL;
1373         eth_dev->rx_pkt_burst = NULL;
1374         eth_dev->tx_pkt_burst = NULL;
1375
1376         /* Unlock any pending hardware semaphore */
1377         ixgbe_swfw_lock_reset(hw);
1378
1379         /* disable uio intr before callback unregister */
1380         rte_intr_disable(intr_handle);
1381         rte_intr_callback_unregister(intr_handle,
1382                                      ixgbe_dev_interrupt_handler, eth_dev);
1383
1384         /* uninitialize PF if max_vfs not zero */
1385         ixgbe_pf_host_uninit(eth_dev);
1386
1387         rte_free(eth_dev->data->mac_addrs);
1388         eth_dev->data->mac_addrs = NULL;
1389
1390         rte_free(eth_dev->data->hash_mac_addrs);
1391         eth_dev->data->hash_mac_addrs = NULL;
1392
1393         /* remove all the fdir filters & hash */
1394         ixgbe_fdir_filter_uninit(eth_dev);
1395
1396         /* remove all the L2 tunnel filters & hash */
1397         ixgbe_l2_tn_filter_uninit(eth_dev);
1398
1399         /* Remove all ntuple filters of the device */
1400         ixgbe_ntuple_filter_uninit(eth_dev);
1401
1402         /* clear all the filters list */
1403         ixgbe_filterlist_flush();
1404
1405         return 0;
1406 }
1407
1408 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1409 {
1410         struct ixgbe_filter_info *filter_info =
1411                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1412         struct ixgbe_5tuple_filter *p_5tuple;
1413
1414         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1415                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1416                              p_5tuple,
1417                              entries);
1418                 rte_free(p_5tuple);
1419         }
1420         memset(filter_info->fivetuple_mask, 0,
1421                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1422
1423         return 0;
1424 }
1425
1426 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1427 {
1428         struct ixgbe_hw_fdir_info *fdir_info =
1429                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1430         struct ixgbe_fdir_filter *fdir_filter;
1431
1432                 if (fdir_info->hash_map)
1433                 rte_free(fdir_info->hash_map);
1434         if (fdir_info->hash_handle)
1435                 rte_hash_free(fdir_info->hash_handle);
1436
1437         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1438                 TAILQ_REMOVE(&fdir_info->fdir_list,
1439                              fdir_filter,
1440                              entries);
1441                 rte_free(fdir_filter);
1442         }
1443
1444         return 0;
1445 }
1446
1447 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1448 {
1449         struct ixgbe_l2_tn_info *l2_tn_info =
1450                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1451         struct ixgbe_l2_tn_filter *l2_tn_filter;
1452
1453         if (l2_tn_info->hash_map)
1454                 rte_free(l2_tn_info->hash_map);
1455         if (l2_tn_info->hash_handle)
1456                 rte_hash_free(l2_tn_info->hash_handle);
1457
1458         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1459                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1460                              l2_tn_filter,
1461                              entries);
1462                 rte_free(l2_tn_filter);
1463         }
1464
1465         return 0;
1466 }
1467
1468 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1469 {
1470         struct ixgbe_hw_fdir_info *fdir_info =
1471                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1472         char fdir_hash_name[RTE_HASH_NAMESIZE];
1473         struct rte_hash_parameters fdir_hash_params = {
1474                 .name = fdir_hash_name,
1475                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1476                 .key_len = sizeof(union ixgbe_atr_input),
1477                 .hash_func = rte_hash_crc,
1478                 .hash_func_init_val = 0,
1479                 .socket_id = rte_socket_id(),
1480         };
1481
1482         TAILQ_INIT(&fdir_info->fdir_list);
1483         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1484                  "fdir_%s", eth_dev->data->name);
1485         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1486         if (!fdir_info->hash_handle) {
1487                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1488                 return -EINVAL;
1489         }
1490         fdir_info->hash_map = rte_zmalloc("ixgbe",
1491                                           sizeof(struct ixgbe_fdir_filter *) *
1492                                           IXGBE_MAX_FDIR_FILTER_NUM,
1493                                           0);
1494         if (!fdir_info->hash_map) {
1495                 PMD_INIT_LOG(ERR,
1496                              "Failed to allocate memory for fdir hash map!");
1497                 return -ENOMEM;
1498         }
1499         fdir_info->mask_added = FALSE;
1500
1501         return 0;
1502 }
1503
1504 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1505 {
1506         struct ixgbe_l2_tn_info *l2_tn_info =
1507                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1508         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1509         struct rte_hash_parameters l2_tn_hash_params = {
1510                 .name = l2_tn_hash_name,
1511                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1512                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1513                 .hash_func = rte_hash_crc,
1514                 .hash_func_init_val = 0,
1515                 .socket_id = rte_socket_id(),
1516         };
1517
1518         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1519         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1520                  "l2_tn_%s", eth_dev->data->name);
1521         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1522         if (!l2_tn_info->hash_handle) {
1523                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1524                 return -EINVAL;
1525         }
1526         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1527                                    sizeof(struct ixgbe_l2_tn_filter *) *
1528                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1529                                    0);
1530         if (!l2_tn_info->hash_map) {
1531                 PMD_INIT_LOG(ERR,
1532                         "Failed to allocate memory for L2 TN hash map!");
1533                 return -ENOMEM;
1534         }
1535         l2_tn_info->e_tag_en = FALSE;
1536         l2_tn_info->e_tag_fwd_en = FALSE;
1537         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1538
1539         return 0;
1540 }
1541 /*
1542  * Negotiate mailbox API version with the PF.
1543  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1544  * Then we try to negotiate starting with the most recent one.
1545  * If all negotiation attempts fail, then we will proceed with
1546  * the default one (ixgbe_mbox_api_10).
1547  */
1548 static void
1549 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1550 {
1551         int32_t i;
1552
1553         /* start with highest supported, proceed down */
1554         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1555                 ixgbe_mbox_api_12,
1556                 ixgbe_mbox_api_11,
1557                 ixgbe_mbox_api_10,
1558         };
1559
1560         for (i = 0;
1561                         i != RTE_DIM(sup_ver) &&
1562                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1563                         i++)
1564                 ;
1565 }
1566
1567 static void
1568 generate_random_mac_addr(struct ether_addr *mac_addr)
1569 {
1570         uint64_t random;
1571
1572         /* Set Organizationally Unique Identifier (OUI) prefix. */
1573         mac_addr->addr_bytes[0] = 0x00;
1574         mac_addr->addr_bytes[1] = 0x09;
1575         mac_addr->addr_bytes[2] = 0xC0;
1576         /* Force indication of locally assigned MAC address. */
1577         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1578         /* Generate the last 3 bytes of the MAC address with a random number. */
1579         random = rte_rand();
1580         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1581 }
1582
1583 /*
1584  * Virtual Function device init
1585  */
1586 static int
1587 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1588 {
1589         int diag;
1590         uint32_t tc, tcs;
1591         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1592         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1593         struct ixgbe_hw *hw =
1594                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1595         struct ixgbe_vfta *shadow_vfta =
1596                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1597         struct ixgbe_hwstrip *hwstrip =
1598                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1599         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1600
1601         PMD_INIT_FUNC_TRACE();
1602
1603         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1604         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1605         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1606
1607         /* for secondary processes, we don't initialise any further as primary
1608          * has already done this work. Only check we don't need a different
1609          * RX function
1610          */
1611         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1612                 struct ixgbe_tx_queue *txq;
1613                 /* TX queue function in primary, set by last queue initialized
1614                  * Tx queue may not initialized by primary process
1615                  */
1616                 if (eth_dev->data->tx_queues) {
1617                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1618                         ixgbe_set_tx_function(eth_dev, txq);
1619                 } else {
1620                         /* Use default TX function if we get here */
1621                         PMD_INIT_LOG(NOTICE,
1622                                      "No TX queues configured yet. Using default TX function.");
1623                 }
1624
1625                 ixgbe_set_rx_function(eth_dev);
1626
1627                 return 0;
1628         }
1629
1630         rte_eth_copy_pci_info(eth_dev, pci_dev);
1631         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1632
1633         hw->device_id = pci_dev->id.device_id;
1634         hw->vendor_id = pci_dev->id.vendor_id;
1635         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1636
1637         /* initialize the vfta */
1638         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1639
1640         /* initialize the hw strip bitmap*/
1641         memset(hwstrip, 0, sizeof(*hwstrip));
1642
1643         /* Initialize the shared code (base driver) */
1644         diag = ixgbe_init_shared_code(hw);
1645         if (diag != IXGBE_SUCCESS) {
1646                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1647                 return -EIO;
1648         }
1649
1650         /* init_mailbox_params */
1651         hw->mbx.ops.init_params(hw);
1652
1653         /* Reset the hw statistics */
1654         ixgbevf_dev_stats_reset(eth_dev);
1655
1656         /* Disable the interrupts for VF */
1657         ixgbevf_intr_disable(hw);
1658
1659         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1660         diag = hw->mac.ops.reset_hw(hw);
1661
1662         /*
1663          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1664          * the underlying PF driver has not assigned a MAC address to the VF.
1665          * In this case, assign a random MAC address.
1666          */
1667         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1668                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1669                 return diag;
1670         }
1671
1672         /* negotiate mailbox API version to use with the PF. */
1673         ixgbevf_negotiate_api(hw);
1674
1675         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1676         ixgbevf_get_queues(hw, &tcs, &tc);
1677
1678         /* Allocate memory for storing MAC addresses */
1679         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1680                                                hw->mac.num_rar_entries, 0);
1681         if (eth_dev->data->mac_addrs == NULL) {
1682                 PMD_INIT_LOG(ERR,
1683                              "Failed to allocate %u bytes needed to store "
1684                              "MAC addresses",
1685                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1686                 return -ENOMEM;
1687         }
1688
1689         /* Generate a random MAC address, if none was assigned by PF. */
1690         if (is_zero_ether_addr(perm_addr)) {
1691                 generate_random_mac_addr(perm_addr);
1692                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1693                 if (diag) {
1694                         rte_free(eth_dev->data->mac_addrs);
1695                         eth_dev->data->mac_addrs = NULL;
1696                         return diag;
1697                 }
1698                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1699                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1700                              "%02x:%02x:%02x:%02x:%02x:%02x",
1701                              perm_addr->addr_bytes[0],
1702                              perm_addr->addr_bytes[1],
1703                              perm_addr->addr_bytes[2],
1704                              perm_addr->addr_bytes[3],
1705                              perm_addr->addr_bytes[4],
1706                              perm_addr->addr_bytes[5]);
1707         }
1708
1709         /* Copy the permanent MAC address */
1710         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1711
1712         /* reset the hardware with the new settings */
1713         diag = hw->mac.ops.start_hw(hw);
1714         switch (diag) {
1715         case  0:
1716                 break;
1717
1718         default:
1719                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1720                 return -EIO;
1721         }
1722
1723         rte_intr_callback_register(intr_handle,
1724                                    ixgbevf_dev_interrupt_handler, eth_dev);
1725         rte_intr_enable(intr_handle);
1726         ixgbevf_intr_enable(hw);
1727
1728         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1729                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1730                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1731
1732         return 0;
1733 }
1734
1735 /* Virtual Function device uninit */
1736
1737 static int
1738 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1739 {
1740         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1741         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1742         struct ixgbe_hw *hw;
1743
1744         PMD_INIT_FUNC_TRACE();
1745
1746         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1747                 return -EPERM;
1748
1749         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1750
1751         if (hw->adapter_stopped == 0)
1752                 ixgbevf_dev_close(eth_dev);
1753
1754         eth_dev->dev_ops = NULL;
1755         eth_dev->rx_pkt_burst = NULL;
1756         eth_dev->tx_pkt_burst = NULL;
1757
1758         /* Disable the interrupts for VF */
1759         ixgbevf_intr_disable(hw);
1760
1761         rte_free(eth_dev->data->mac_addrs);
1762         eth_dev->data->mac_addrs = NULL;
1763
1764         rte_intr_disable(intr_handle);
1765         rte_intr_callback_unregister(intr_handle,
1766                                      ixgbevf_dev_interrupt_handler, eth_dev);
1767
1768         return 0;
1769 }
1770
1771 static struct eth_driver rte_ixgbe_pmd = {
1772         .pci_drv = {
1773                 .id_table = pci_id_ixgbe_map,
1774                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1775                 .probe = rte_eth_dev_pci_probe,
1776                 .remove = rte_eth_dev_pci_remove,
1777         },
1778         .eth_dev_init = eth_ixgbe_dev_init,
1779         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1780         .dev_private_size = sizeof(struct ixgbe_adapter),
1781 };
1782
1783 /*
1784  * virtual function driver struct
1785  */
1786 static struct eth_driver rte_ixgbevf_pmd = {
1787         .pci_drv = {
1788                 .id_table = pci_id_ixgbevf_map,
1789                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1790                 .probe = rte_eth_dev_pci_probe,
1791                 .remove = rte_eth_dev_pci_remove,
1792         },
1793         .eth_dev_init = eth_ixgbevf_dev_init,
1794         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1795         .dev_private_size = sizeof(struct ixgbe_adapter),
1796 };
1797
1798 static int
1799 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1800 {
1801         struct ixgbe_hw *hw =
1802                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1803         struct ixgbe_vfta *shadow_vfta =
1804                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1805         uint32_t vfta;
1806         uint32_t vid_idx;
1807         uint32_t vid_bit;
1808
1809         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1810         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1811         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1812         if (on)
1813                 vfta |= vid_bit;
1814         else
1815                 vfta &= ~vid_bit;
1816         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1817
1818         /* update local VFTA copy */
1819         shadow_vfta->vfta[vid_idx] = vfta;
1820
1821         return 0;
1822 }
1823
1824 static void
1825 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1826 {
1827         if (on)
1828                 ixgbe_vlan_hw_strip_enable(dev, queue);
1829         else
1830                 ixgbe_vlan_hw_strip_disable(dev, queue);
1831 }
1832
1833 static int
1834 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1835                     enum rte_vlan_type vlan_type,
1836                     uint16_t tpid)
1837 {
1838         struct ixgbe_hw *hw =
1839                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1840         int ret = 0;
1841         uint32_t reg;
1842         uint32_t qinq;
1843
1844         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1845         qinq &= IXGBE_DMATXCTL_GDV;
1846
1847         switch (vlan_type) {
1848         case ETH_VLAN_TYPE_INNER:
1849                 if (qinq) {
1850                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1851                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1852                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1853                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1854                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1855                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1856                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1857                 } else {
1858                         ret = -ENOTSUP;
1859                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1860                                     " by single VLAN");
1861                 }
1862                 break;
1863         case ETH_VLAN_TYPE_OUTER:
1864                 if (qinq) {
1865                         /* Only the high 16-bits is valid */
1866                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1867                                         IXGBE_EXVET_VET_EXT_SHIFT);
1868                 } else {
1869                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1870                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1871                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1872                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1873                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1874                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1875                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1876                 }
1877
1878                 break;
1879         default:
1880                 ret = -EINVAL;
1881                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1882                 break;
1883         }
1884
1885         return ret;
1886 }
1887
1888 void
1889 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1890 {
1891         struct ixgbe_hw *hw =
1892                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1893         uint32_t vlnctrl;
1894
1895         PMD_INIT_FUNC_TRACE();
1896
1897         /* Filter Table Disable */
1898         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1899         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1900
1901         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1902 }
1903
1904 void
1905 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1906 {
1907         struct ixgbe_hw *hw =
1908                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1909         struct ixgbe_vfta *shadow_vfta =
1910                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1911         uint32_t vlnctrl;
1912         uint16_t i;
1913
1914         PMD_INIT_FUNC_TRACE();
1915
1916         /* Filter Table Enable */
1917         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1918         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1919         vlnctrl |= IXGBE_VLNCTRL_VFE;
1920
1921         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1922
1923         /* write whatever is in local vfta copy */
1924         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1925                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1926 }
1927
1928 static void
1929 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1930 {
1931         struct ixgbe_hwstrip *hwstrip =
1932                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1933         struct ixgbe_rx_queue *rxq;
1934
1935         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1936                 return;
1937
1938         if (on)
1939                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1940         else
1941                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1942
1943         if (queue >= dev->data->nb_rx_queues)
1944                 return;
1945
1946         rxq = dev->data->rx_queues[queue];
1947
1948         if (on)
1949                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1950         else
1951                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1952 }
1953
1954 static void
1955 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1956 {
1957         struct ixgbe_hw *hw =
1958                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1959         uint32_t ctrl;
1960
1961         PMD_INIT_FUNC_TRACE();
1962
1963         if (hw->mac.type == ixgbe_mac_82598EB) {
1964                 /* No queue level support */
1965                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1966                 return;
1967         }
1968
1969         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1970         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1971         ctrl &= ~IXGBE_RXDCTL_VME;
1972         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1973
1974         /* record those setting for HW strip per queue */
1975         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1976 }
1977
1978 static void
1979 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1980 {
1981         struct ixgbe_hw *hw =
1982                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1983         uint32_t ctrl;
1984
1985         PMD_INIT_FUNC_TRACE();
1986
1987         if (hw->mac.type == ixgbe_mac_82598EB) {
1988                 /* No queue level supported */
1989                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1990                 return;
1991         }
1992
1993         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1994         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1995         ctrl |= IXGBE_RXDCTL_VME;
1996         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1997
1998         /* record those setting for HW strip per queue */
1999         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2000 }
2001
2002 void
2003 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2004 {
2005         struct ixgbe_hw *hw =
2006                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2007         uint32_t ctrl;
2008         uint16_t i;
2009         struct ixgbe_rx_queue *rxq;
2010
2011         PMD_INIT_FUNC_TRACE();
2012
2013         if (hw->mac.type == ixgbe_mac_82598EB) {
2014                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2015                 ctrl &= ~IXGBE_VLNCTRL_VME;
2016                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2017         } else {
2018                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2019                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2020                         rxq = dev->data->rx_queues[i];
2021                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2022                         ctrl &= ~IXGBE_RXDCTL_VME;
2023                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2024
2025                         /* record those setting for HW strip per queue */
2026                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2027                 }
2028         }
2029 }
2030
2031 void
2032 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2033 {
2034         struct ixgbe_hw *hw =
2035                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2036         uint32_t ctrl;
2037         uint16_t i;
2038         struct ixgbe_rx_queue *rxq;
2039
2040         PMD_INIT_FUNC_TRACE();
2041
2042         if (hw->mac.type == ixgbe_mac_82598EB) {
2043                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2044                 ctrl |= IXGBE_VLNCTRL_VME;
2045                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2046         } else {
2047                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2048                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2049                         rxq = dev->data->rx_queues[i];
2050                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2051                         ctrl |= IXGBE_RXDCTL_VME;
2052                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2053
2054                         /* record those setting for HW strip per queue */
2055                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2056                 }
2057         }
2058 }
2059
2060 static void
2061 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2062 {
2063         struct ixgbe_hw *hw =
2064                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065         uint32_t ctrl;
2066
2067         PMD_INIT_FUNC_TRACE();
2068
2069         /* DMATXCTRL: Geric Double VLAN Disable */
2070         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2071         ctrl &= ~IXGBE_DMATXCTL_GDV;
2072         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2073
2074         /* CTRL_EXT: Global Double VLAN Disable */
2075         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2076         ctrl &= ~IXGBE_EXTENDED_VLAN;
2077         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2078
2079 }
2080
2081 static void
2082 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2083 {
2084         struct ixgbe_hw *hw =
2085                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2086         uint32_t ctrl;
2087
2088         PMD_INIT_FUNC_TRACE();
2089
2090         /* DMATXCTRL: Geric Double VLAN Enable */
2091         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2092         ctrl |= IXGBE_DMATXCTL_GDV;
2093         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2094
2095         /* CTRL_EXT: Global Double VLAN Enable */
2096         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2097         ctrl |= IXGBE_EXTENDED_VLAN;
2098         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2099
2100         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2101         if (hw->mac.type == ixgbe_mac_X550 ||
2102             hw->mac.type == ixgbe_mac_X550EM_x ||
2103             hw->mac.type == ixgbe_mac_X550EM_a) {
2104                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2105                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2106                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2107         }
2108
2109         /*
2110          * VET EXT field in the EXVET register = 0x8100 by default
2111          * So no need to change. Same to VT field of DMATXCTL register
2112          */
2113 }
2114
2115 static void
2116 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2117 {
2118         if (mask & ETH_VLAN_STRIP_MASK) {
2119                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2120                         ixgbe_vlan_hw_strip_enable_all(dev);
2121                 else
2122                         ixgbe_vlan_hw_strip_disable_all(dev);
2123         }
2124
2125         if (mask & ETH_VLAN_FILTER_MASK) {
2126                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2127                         ixgbe_vlan_hw_filter_enable(dev);
2128                 else
2129                         ixgbe_vlan_hw_filter_disable(dev);
2130         }
2131
2132         if (mask & ETH_VLAN_EXTEND_MASK) {
2133                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2134                         ixgbe_vlan_hw_extend_enable(dev);
2135                 else
2136                         ixgbe_vlan_hw_extend_disable(dev);
2137         }
2138 }
2139
2140 static void
2141 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2142 {
2143         struct ixgbe_hw *hw =
2144                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2145         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2146         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2147
2148         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2149         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2150 }
2151
2152 static int
2153 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2154 {
2155         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2156
2157         switch (nb_rx_q) {
2158         case 1:
2159         case 2:
2160                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2161                 break;
2162         case 4:
2163                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2164                 break;
2165         default:
2166                 return -EINVAL;
2167         }
2168
2169         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2170         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2171
2172         return 0;
2173 }
2174
2175 static int
2176 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2177 {
2178         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2179         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2180         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2181         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2182
2183         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2184                 /* check multi-queue mode */
2185                 switch (dev_conf->rxmode.mq_mode) {
2186                 case ETH_MQ_RX_VMDQ_DCB:
2187                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2188                         break;
2189                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2190                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2191                         PMD_INIT_LOG(ERR, "SRIOV active,"
2192                                         " unsupported mq_mode rx %d.",
2193                                         dev_conf->rxmode.mq_mode);
2194                         return -EINVAL;
2195                 case ETH_MQ_RX_RSS:
2196                 case ETH_MQ_RX_VMDQ_RSS:
2197                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2198                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2199                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2200                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2201                                                 " invalid queue number"
2202                                                 " for VMDQ RSS, allowed"
2203                                                 " value are 1, 2 or 4.");
2204                                         return -EINVAL;
2205                                 }
2206                         break;
2207                 case ETH_MQ_RX_VMDQ_ONLY:
2208                 case ETH_MQ_RX_NONE:
2209                         /* if nothing mq mode configure, use default scheme */
2210                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2211                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2212                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2213                         break;
2214                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2215                         /* SRIOV only works in VMDq enable mode */
2216                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2217                                         " wrong mq_mode rx %d.",
2218                                         dev_conf->rxmode.mq_mode);
2219                         return -EINVAL;
2220                 }
2221
2222                 switch (dev_conf->txmode.mq_mode) {
2223                 case ETH_MQ_TX_VMDQ_DCB:
2224                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2225                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2226                         break;
2227                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2228                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2229                         break;
2230                 }
2231
2232                 /* check valid queue number */
2233                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2234                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2235                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2236                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2237                                         " must be less than or equal to %d.",
2238                                         nb_rx_q, nb_tx_q,
2239                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2240                         return -EINVAL;
2241                 }
2242         } else {
2243                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2244                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2245                                           " not supported.");
2246                         return -EINVAL;
2247                 }
2248                 /* check configuration for vmdb+dcb mode */
2249                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2250                         const struct rte_eth_vmdq_dcb_conf *conf;
2251
2252                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2253                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2254                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2255                                 return -EINVAL;
2256                         }
2257                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2258                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2259                                conf->nb_queue_pools == ETH_32_POOLS)) {
2260                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2261                                                 " nb_queue_pools must be %d or %d.",
2262                                                 ETH_16_POOLS, ETH_32_POOLS);
2263                                 return -EINVAL;
2264                         }
2265                 }
2266                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2267                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2268
2269                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2270                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2271                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2272                                 return -EINVAL;
2273                         }
2274                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2275                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2276                                conf->nb_queue_pools == ETH_32_POOLS)) {
2277                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2278                                                 " nb_queue_pools != %d and"
2279                                                 " nb_queue_pools != %d.",
2280                                                 ETH_16_POOLS, ETH_32_POOLS);
2281                                 return -EINVAL;
2282                         }
2283                 }
2284
2285                 /* For DCB mode check our configuration before we go further */
2286                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2287                         const struct rte_eth_dcb_rx_conf *conf;
2288
2289                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2290                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2291                                                  IXGBE_DCB_NB_QUEUES);
2292                                 return -EINVAL;
2293                         }
2294                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2295                         if (!(conf->nb_tcs == ETH_4_TCS ||
2296                                conf->nb_tcs == ETH_8_TCS)) {
2297                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2298                                                 " and nb_tcs != %d.",
2299                                                 ETH_4_TCS, ETH_8_TCS);
2300                                 return -EINVAL;
2301                         }
2302                 }
2303
2304                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2305                         const struct rte_eth_dcb_tx_conf *conf;
2306
2307                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2308                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2309                                                  IXGBE_DCB_NB_QUEUES);
2310                                 return -EINVAL;
2311                         }
2312                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2313                         if (!(conf->nb_tcs == ETH_4_TCS ||
2314                                conf->nb_tcs == ETH_8_TCS)) {
2315                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2316                                                 " and nb_tcs != %d.",
2317                                                 ETH_4_TCS, ETH_8_TCS);
2318                                 return -EINVAL;
2319                         }
2320                 }
2321
2322                 /*
2323                  * When DCB/VT is off, maximum number of queues changes,
2324                  * except for 82598EB, which remains constant.
2325                  */
2326                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2327                                 hw->mac.type != ixgbe_mac_82598EB) {
2328                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2329                                 PMD_INIT_LOG(ERR,
2330                                              "Neither VT nor DCB are enabled, "
2331                                              "nb_tx_q > %d.",
2332                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2333                                 return -EINVAL;
2334                         }
2335                 }
2336         }
2337         return 0;
2338 }
2339
2340 static int
2341 ixgbe_dev_configure(struct rte_eth_dev *dev)
2342 {
2343         struct ixgbe_interrupt *intr =
2344                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2345         struct ixgbe_adapter *adapter =
2346                 (struct ixgbe_adapter *)dev->data->dev_private;
2347         int ret;
2348
2349         PMD_INIT_FUNC_TRACE();
2350         /* multipe queue mode checking */
2351         ret  = ixgbe_check_mq_mode(dev);
2352         if (ret != 0) {
2353                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2354                             ret);
2355                 return ret;
2356         }
2357
2358         /* set flag to update link status after init */
2359         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2360
2361         /*
2362          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2363          * allocation or vector Rx preconditions we will reset it.
2364          */
2365         adapter->rx_bulk_alloc_allowed = true;
2366         adapter->rx_vec_allowed = true;
2367
2368         return 0;
2369 }
2370
2371 static void
2372 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2373 {
2374         struct ixgbe_hw *hw =
2375                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2376         struct ixgbe_interrupt *intr =
2377                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2378         uint32_t gpie;
2379
2380         /* only set up it on X550EM_X */
2381         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2382                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2383                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2384                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2385                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2386                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2387         }
2388 }
2389
2390 /*
2391  * Configure device link speed and setup link.
2392  * It returns 0 on success.
2393  */
2394 static int
2395 ixgbe_dev_start(struct rte_eth_dev *dev)
2396 {
2397         struct ixgbe_hw *hw =
2398                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2399         struct ixgbe_vf_info *vfinfo =
2400                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2401         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2402         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2403         uint32_t intr_vector = 0;
2404         int err, link_up = 0, negotiate = 0;
2405         uint32_t speed = 0;
2406         int mask = 0;
2407         int status;
2408         uint16_t vf, idx;
2409         uint32_t *link_speeds;
2410
2411         PMD_INIT_FUNC_TRACE();
2412
2413         /* IXGBE devices don't support:
2414         *    - half duplex (checked afterwards for valid speeds)
2415         *    - fixed speed: TODO implement
2416         */
2417         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2418                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2419                              dev->data->port_id);
2420                 return -EINVAL;
2421         }
2422
2423         /* disable uio/vfio intr/eventfd mapping */
2424         rte_intr_disable(intr_handle);
2425
2426         /* stop adapter */
2427         hw->adapter_stopped = 0;
2428         ixgbe_stop_adapter(hw);
2429
2430         /* reinitialize adapter
2431          * this calls reset and start
2432          */
2433         status = ixgbe_pf_reset_hw(hw);
2434         if (status != 0)
2435                 return -1;
2436         hw->mac.ops.start_hw(hw);
2437         hw->mac.get_link_status = true;
2438
2439         /* configure PF module if SRIOV enabled */
2440         ixgbe_pf_host_configure(dev);
2441
2442         ixgbe_dev_phy_intr_setup(dev);
2443
2444         /* check and configure queue intr-vector mapping */
2445         if ((rte_intr_cap_multiple(intr_handle) ||
2446              !RTE_ETH_DEV_SRIOV(dev).active) &&
2447             dev->data->dev_conf.intr_conf.rxq != 0) {
2448                 intr_vector = dev->data->nb_rx_queues;
2449                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2450                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2451                                         IXGBE_MAX_INTR_QUEUE_NUM);
2452                         return -ENOTSUP;
2453                 }
2454                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2455                         return -1;
2456         }
2457
2458         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2459                 intr_handle->intr_vec =
2460                         rte_zmalloc("intr_vec",
2461                                     dev->data->nb_rx_queues * sizeof(int), 0);
2462                 if (intr_handle->intr_vec == NULL) {
2463                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2464                                      " intr_vec", dev->data->nb_rx_queues);
2465                         return -ENOMEM;
2466                 }
2467         }
2468
2469         /* confiugre msix for sleep until rx interrupt */
2470         ixgbe_configure_msix(dev);
2471
2472         /* initialize transmission unit */
2473         ixgbe_dev_tx_init(dev);
2474
2475         /* This can fail when allocating mbufs for descriptor rings */
2476         err = ixgbe_dev_rx_init(dev);
2477         if (err) {
2478                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2479                 goto error;
2480         }
2481
2482     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2483                 ETH_VLAN_EXTEND_MASK;
2484         ixgbe_vlan_offload_set(dev, mask);
2485
2486         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2487                 /* Enable vlan filtering for VMDq */
2488                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2489         }
2490
2491         /* Configure DCB hw */
2492         ixgbe_configure_dcb(dev);
2493
2494         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2495                 err = ixgbe_fdir_configure(dev);
2496                 if (err)
2497                         goto error;
2498         }
2499
2500         /* Restore vf rate limit */
2501         if (vfinfo != NULL) {
2502                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2503                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2504                                 if (vfinfo[vf].tx_rate[idx] != 0)
2505                                         rte_pmd_ixgbe_set_vf_rate_limit(
2506                                                 dev->data->port_id, vf,
2507                                                 vfinfo[vf].tx_rate[idx],
2508                                                 1 << idx);
2509         }
2510
2511         ixgbe_restore_statistics_mapping(dev);
2512
2513         err = ixgbe_dev_rxtx_start(dev);
2514         if (err < 0) {
2515                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2516                 goto error;
2517         }
2518
2519         /* Skip link setup if loopback mode is enabled for 82599. */
2520         if (hw->mac.type == ixgbe_mac_82599EB &&
2521                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2522                 goto skip_link_setup;
2523
2524         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2525                 err = hw->mac.ops.setup_sfp(hw);
2526                 if (err)
2527                         goto error;
2528         }
2529
2530         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2531                 /* Turn on the copper */
2532                 ixgbe_set_phy_power(hw, true);
2533         } else {
2534                 /* Turn on the laser */
2535                 ixgbe_enable_tx_laser(hw);
2536         }
2537
2538         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2539         if (err)
2540                 goto error;
2541         dev->data->dev_link.link_status = link_up;
2542
2543         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2544         if (err)
2545                 goto error;
2546
2547         link_speeds = &dev->data->dev_conf.link_speeds;
2548         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2549                         ETH_LINK_SPEED_10G)) {
2550                 PMD_INIT_LOG(ERR, "Invalid link setting");
2551                 goto error;
2552         }
2553
2554         speed = 0x0;
2555         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2556                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2557                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2558                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2559         } else {
2560                 if (*link_speeds & ETH_LINK_SPEED_10G)
2561                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2562                 if (*link_speeds & ETH_LINK_SPEED_1G)
2563                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2564                 if (*link_speeds & ETH_LINK_SPEED_100M)
2565                         speed |= IXGBE_LINK_SPEED_100_FULL;
2566         }
2567
2568         err = ixgbe_setup_link(hw, speed, link_up);
2569         if (err)
2570                 goto error;
2571
2572 skip_link_setup:
2573
2574         if (rte_intr_allow_others(intr_handle)) {
2575                 /* check if lsc interrupt is enabled */
2576                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2577                         ixgbe_dev_lsc_interrupt_setup(dev);
2578                 ixgbe_dev_macsec_interrupt_setup(dev);
2579         } else {
2580                 rte_intr_callback_unregister(intr_handle,
2581                                              ixgbe_dev_interrupt_handler, dev);
2582                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2583                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2584                                      " no intr multiplex");
2585         }
2586
2587         /* check if rxq interrupt is enabled */
2588         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2589             rte_intr_dp_is_en(intr_handle))
2590                 ixgbe_dev_rxq_interrupt_setup(dev);
2591
2592         /* enable uio/vfio intr/eventfd mapping */
2593         rte_intr_enable(intr_handle);
2594
2595         /* resume enabled intr since hw reset */
2596         ixgbe_enable_intr(dev);
2597         ixgbe_l2_tunnel_conf(dev);
2598         ixgbe_filter_restore(dev);
2599
2600         return 0;
2601
2602 error:
2603         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2604         ixgbe_dev_clear_queues(dev);
2605         return -EIO;
2606 }
2607
2608 /*
2609  * Stop device: disable rx and tx functions to allow for reconfiguring.
2610  */
2611 static void
2612 ixgbe_dev_stop(struct rte_eth_dev *dev)
2613 {
2614         struct rte_eth_link link;
2615         struct ixgbe_hw *hw =
2616                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2617         struct ixgbe_vf_info *vfinfo =
2618                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2619         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2620         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2621         int vf;
2622
2623         PMD_INIT_FUNC_TRACE();
2624
2625         /* disable interrupts */
2626         ixgbe_disable_intr(hw);
2627
2628         /* reset the NIC */
2629         ixgbe_pf_reset_hw(hw);
2630         hw->adapter_stopped = 0;
2631
2632         /* stop adapter */
2633         ixgbe_stop_adapter(hw);
2634
2635         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2636                 vfinfo[vf].clear_to_send = false;
2637
2638         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2639                 /* Turn off the copper */
2640                 ixgbe_set_phy_power(hw, false);
2641         } else {
2642                 /* Turn off the laser */
2643                 ixgbe_disable_tx_laser(hw);
2644         }
2645
2646         ixgbe_dev_clear_queues(dev);
2647
2648         /* Clear stored conf */
2649         dev->data->scattered_rx = 0;
2650         dev->data->lro = 0;
2651
2652         /* Clear recorded link status */
2653         memset(&link, 0, sizeof(link));
2654         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2655
2656         if (!rte_intr_allow_others(intr_handle))
2657                 /* resume to the default handler */
2658                 rte_intr_callback_register(intr_handle,
2659                                            ixgbe_dev_interrupt_handler,
2660                                            (void *)dev);
2661
2662         /* Clean datapath event and queue/vec mapping */
2663         rte_intr_efd_disable(intr_handle);
2664         if (intr_handle->intr_vec != NULL) {
2665                 rte_free(intr_handle->intr_vec);
2666                 intr_handle->intr_vec = NULL;
2667         }
2668 }
2669
2670 /*
2671  * Set device link up: enable tx.
2672  */
2673 static int
2674 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2675 {
2676         struct ixgbe_hw *hw =
2677                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2678         if (hw->mac.type == ixgbe_mac_82599EB) {
2679 #ifdef RTE_NIC_BYPASS
2680                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2681                         /* Not suported in bypass mode */
2682                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2683                                      "by device id 0x%x", hw->device_id);
2684                         return -ENOTSUP;
2685                 }
2686 #endif
2687         }
2688
2689         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2690                 /* Turn on the copper */
2691                 ixgbe_set_phy_power(hw, true);
2692         } else {
2693                 /* Turn on the laser */
2694                 ixgbe_enable_tx_laser(hw);
2695         }
2696
2697         return 0;
2698 }
2699
2700 /*
2701  * Set device link down: disable tx.
2702  */
2703 static int
2704 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2705 {
2706         struct ixgbe_hw *hw =
2707                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2708         if (hw->mac.type == ixgbe_mac_82599EB) {
2709 #ifdef RTE_NIC_BYPASS
2710                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2711                         /* Not suported in bypass mode */
2712                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2713                                      "by device id 0x%x", hw->device_id);
2714                         return -ENOTSUP;
2715                 }
2716 #endif
2717         }
2718
2719         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2720                 /* Turn off the copper */
2721                 ixgbe_set_phy_power(hw, false);
2722         } else {
2723                 /* Turn off the laser */
2724                 ixgbe_disable_tx_laser(hw);
2725         }
2726
2727         return 0;
2728 }
2729
2730 /*
2731  * Reest and stop device.
2732  */
2733 static void
2734 ixgbe_dev_close(struct rte_eth_dev *dev)
2735 {
2736         struct ixgbe_hw *hw =
2737                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2738
2739         PMD_INIT_FUNC_TRACE();
2740
2741         ixgbe_pf_reset_hw(hw);
2742
2743         ixgbe_dev_stop(dev);
2744         hw->adapter_stopped = 1;
2745
2746         ixgbe_dev_free_queues(dev);
2747
2748         ixgbe_disable_pcie_master(hw);
2749
2750         /* reprogram the RAR[0] in case user changed it. */
2751         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2752 }
2753
2754 static void
2755 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2756                            struct ixgbe_hw_stats *hw_stats,
2757                            struct ixgbe_macsec_stats *macsec_stats,
2758                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2759                            uint64_t *total_qprc, uint64_t *total_qprdc)
2760 {
2761         uint32_t bprc, lxon, lxoff, total;
2762         uint32_t delta_gprc = 0;
2763         unsigned i;
2764         /* Workaround for RX byte count not including CRC bytes when CRC
2765          * strip is enabled. CRC bytes are removed from counters when crc_strip
2766          * is disabled.
2767          */
2768         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2769                         IXGBE_HLREG0_RXCRCSTRP);
2770
2771         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2772         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2773         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2774         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2775
2776         for (i = 0; i < 8; i++) {
2777                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2778
2779                 /* global total per queue */
2780                 hw_stats->mpc[i] += mp;
2781                 /* Running comprehensive total for stats display */
2782                 *total_missed_rx += hw_stats->mpc[i];
2783                 if (hw->mac.type == ixgbe_mac_82598EB) {
2784                         hw_stats->rnbc[i] +=
2785                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2786                         hw_stats->pxonrxc[i] +=
2787                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2788                         hw_stats->pxoffrxc[i] +=
2789                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2790                 } else {
2791                         hw_stats->pxonrxc[i] +=
2792                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2793                         hw_stats->pxoffrxc[i] +=
2794                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2795                         hw_stats->pxon2offc[i] +=
2796                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2797                 }
2798                 hw_stats->pxontxc[i] +=
2799                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2800                 hw_stats->pxofftxc[i] +=
2801                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2802         }
2803         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2804                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2805                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2806                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2807
2808                 delta_gprc += delta_qprc;
2809
2810                 hw_stats->qprc[i] += delta_qprc;
2811                 hw_stats->qptc[i] += delta_qptc;
2812
2813                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2814                 hw_stats->qbrc[i] +=
2815                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2816                 if (crc_strip == 0)
2817                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2818
2819                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2820                 hw_stats->qbtc[i] +=
2821                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2822
2823                 hw_stats->qprdc[i] += delta_qprdc;
2824                 *total_qprdc += hw_stats->qprdc[i];
2825
2826                 *total_qprc += hw_stats->qprc[i];
2827                 *total_qbrc += hw_stats->qbrc[i];
2828         }
2829         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2830         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2831         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2832
2833         /*
2834          * An errata states that gprc actually counts good + missed packets:
2835          * Workaround to set gprc to summated queue packet receives
2836          */
2837         hw_stats->gprc = *total_qprc;
2838
2839         if (hw->mac.type != ixgbe_mac_82598EB) {
2840                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2841                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2842                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2843                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2844                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2845                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2846                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2847                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2848         } else {
2849                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2850                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2851                 /* 82598 only has a counter in the high register */
2852                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2853                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2854                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2855         }
2856         uint64_t old_tpr = hw_stats->tpr;
2857
2858         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2859         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2860
2861         if (crc_strip == 0)
2862                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2863
2864         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2865         hw_stats->gptc += delta_gptc;
2866         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2867         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2868
2869         /*
2870          * Workaround: mprc hardware is incorrectly counting
2871          * broadcasts, so for now we subtract those.
2872          */
2873         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2874         hw_stats->bprc += bprc;
2875         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2876         if (hw->mac.type == ixgbe_mac_82598EB)
2877                 hw_stats->mprc -= bprc;
2878
2879         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2880         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2881         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2882         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2883         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2884         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2885
2886         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2887         hw_stats->lxontxc += lxon;
2888         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2889         hw_stats->lxofftxc += lxoff;
2890         total = lxon + lxoff;
2891
2892         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2893         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2894         hw_stats->gptc -= total;
2895         hw_stats->mptc -= total;
2896         hw_stats->ptc64 -= total;
2897         hw_stats->gotc -= total * ETHER_MIN_LEN;
2898
2899         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2900         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2901         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2902         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2903         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2904         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2905         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2906         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2907         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2908         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2909         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2910         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2911         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2912         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2913         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2914         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2915         /* Only read FCOE on 82599 */
2916         if (hw->mac.type != ixgbe_mac_82598EB) {
2917                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2918                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2919                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2920                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2921                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2922         }
2923
2924         /* Flow Director Stats registers */
2925         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2926         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2927
2928         /* MACsec Stats registers */
2929         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2930         macsec_stats->out_pkts_encrypted +=
2931                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2932         macsec_stats->out_pkts_protected +=
2933                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2934         macsec_stats->out_octets_encrypted +=
2935                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2936         macsec_stats->out_octets_protected +=
2937                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2938         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2939         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2940         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2941         macsec_stats->in_pkts_unknownsci +=
2942                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2943         macsec_stats->in_octets_decrypted +=
2944                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2945         macsec_stats->in_octets_validated +=
2946                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2947         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2948         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2949         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2950         for (i = 0; i < 2; i++) {
2951                 macsec_stats->in_pkts_ok +=
2952                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2953                 macsec_stats->in_pkts_invalid +=
2954                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2955                 macsec_stats->in_pkts_notvalid +=
2956                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2957         }
2958         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2959         macsec_stats->in_pkts_notusingsa +=
2960                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2961 }
2962
2963 /*
2964  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2965  */
2966 static void
2967 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2968 {
2969         struct ixgbe_hw *hw =
2970                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971         struct ixgbe_hw_stats *hw_stats =
2972                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2973         struct ixgbe_macsec_stats *macsec_stats =
2974                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2975                                 dev->data->dev_private);
2976         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2977         unsigned i;
2978
2979         total_missed_rx = 0;
2980         total_qbrc = 0;
2981         total_qprc = 0;
2982         total_qprdc = 0;
2983
2984         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2985                         &total_qbrc, &total_qprc, &total_qprdc);
2986
2987         if (stats == NULL)
2988                 return;
2989
2990         /* Fill out the rte_eth_stats statistics structure */
2991         stats->ipackets = total_qprc;
2992         stats->ibytes = total_qbrc;
2993         stats->opackets = hw_stats->gptc;
2994         stats->obytes = hw_stats->gotc;
2995
2996         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2997                 stats->q_ipackets[i] = hw_stats->qprc[i];
2998                 stats->q_opackets[i] = hw_stats->qptc[i];
2999                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3000                 stats->q_obytes[i] = hw_stats->qbtc[i];
3001                 stats->q_errors[i] = hw_stats->qprdc[i];
3002         }
3003
3004         /* Rx Errors */
3005         stats->imissed  = total_missed_rx;
3006         stats->ierrors  = hw_stats->crcerrs +
3007                           hw_stats->mspdc +
3008                           hw_stats->rlec +
3009                           hw_stats->ruc +
3010                           hw_stats->roc +
3011                           hw_stats->illerrc +
3012                           hw_stats->errbc +
3013                           hw_stats->rfc +
3014                           hw_stats->fccrc +
3015                           hw_stats->fclast;
3016
3017         /* Tx Errors */
3018         stats->oerrors  = 0;
3019 }
3020
3021 static void
3022 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3023 {
3024         struct ixgbe_hw_stats *stats =
3025                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3026
3027         /* HW registers are cleared on read */
3028         ixgbe_dev_stats_get(dev, NULL);
3029
3030         /* Reset software totals */
3031         memset(stats, 0, sizeof(*stats));
3032 }
3033
3034 /* This function calculates the number of xstats based on the current config */
3035 static unsigned
3036 ixgbe_xstats_calc_num(void) {
3037         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3038                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3039                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3040 }
3041
3042 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3043         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
3044 {
3045         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3046         unsigned stat, i, count;
3047
3048         if (xstats_names != NULL) {
3049                 count = 0;
3050
3051                 /* Note: limit >= cnt_stats checked upstream
3052                  * in rte_eth_xstats_names()
3053                  */
3054
3055                 /* Extended stats from ixgbe_hw_stats */
3056                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3057                         snprintf(xstats_names[count].name,
3058                                 sizeof(xstats_names[count].name),
3059                                 "%s",
3060                                 rte_ixgbe_stats_strings[i].name);
3061                         count++;
3062                 }
3063
3064                 /* MACsec Stats */
3065                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3066                         snprintf(xstats_names[count].name,
3067                                 sizeof(xstats_names[count].name),
3068                                 "%s",
3069                                 rte_ixgbe_macsec_strings[i].name);
3070                         count++;
3071                 }
3072
3073                 /* RX Priority Stats */
3074                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3075                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3076                                 snprintf(xstats_names[count].name,
3077                                         sizeof(xstats_names[count].name),
3078                                         "rx_priority%u_%s", i,
3079                                         rte_ixgbe_rxq_strings[stat].name);
3080                                 count++;
3081                         }
3082                 }
3083
3084                 /* TX Priority Stats */
3085                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3086                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3087                                 snprintf(xstats_names[count].name,
3088                                         sizeof(xstats_names[count].name),
3089                                         "tx_priority%u_%s", i,
3090                                         rte_ixgbe_txq_strings[stat].name);
3091                                 count++;
3092                         }
3093                 }
3094         }
3095         return cnt_stats;
3096 }
3097
3098 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3099         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3100 {
3101         unsigned i;
3102
3103         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3104                 return -ENOMEM;
3105
3106         if (xstats_names != NULL)
3107                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3108                         snprintf(xstats_names[i].name,
3109                                 sizeof(xstats_names[i].name),
3110                                 "%s", rte_ixgbevf_stats_strings[i].name);
3111         return IXGBEVF_NB_XSTATS;
3112 }
3113
3114 static int
3115 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3116                                          unsigned n)
3117 {
3118         struct ixgbe_hw *hw =
3119                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3120         struct ixgbe_hw_stats *hw_stats =
3121                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3122         struct ixgbe_macsec_stats *macsec_stats =
3123                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3124                                 dev->data->dev_private);
3125         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3126         unsigned i, stat, count = 0;
3127
3128         count = ixgbe_xstats_calc_num();
3129
3130         if (n < count)
3131                 return count;
3132
3133         total_missed_rx = 0;
3134         total_qbrc = 0;
3135         total_qprc = 0;
3136         total_qprdc = 0;
3137
3138         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3139                         &total_qbrc, &total_qprc, &total_qprdc);
3140
3141         /* If this is a reset xstats is NULL, and we have cleared the
3142          * registers by reading them.
3143          */
3144         if (!xstats)
3145                 return 0;
3146
3147         /* Extended stats from ixgbe_hw_stats */
3148         count = 0;
3149         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3150                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3151                                 rte_ixgbe_stats_strings[i].offset);
3152                 xstats[count].id = count;
3153                 count++;
3154         }
3155
3156         /* MACsec Stats */
3157         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3158                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3159                                 rte_ixgbe_macsec_strings[i].offset);
3160                 xstats[count].id = count;
3161                 count++;
3162         }
3163
3164         /* RX Priority Stats */
3165         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3166                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3167                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3168                                         rte_ixgbe_rxq_strings[stat].offset +
3169                                         (sizeof(uint64_t) * i));
3170                         xstats[count].id = count;
3171                         count++;
3172                 }
3173         }
3174
3175         /* TX Priority Stats */
3176         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3177                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3178                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3179                                         rte_ixgbe_txq_strings[stat].offset +
3180                                         (sizeof(uint64_t) * i));
3181                         xstats[count].id = count;
3182                         count++;
3183                 }
3184         }
3185         return count;
3186 }
3187
3188 static void
3189 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3190 {
3191         struct ixgbe_hw_stats *stats =
3192                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3193         struct ixgbe_macsec_stats *macsec_stats =
3194                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3195                                 dev->data->dev_private);
3196
3197         unsigned count = ixgbe_xstats_calc_num();
3198
3199         /* HW registers are cleared on read */
3200         ixgbe_dev_xstats_get(dev, NULL, count);
3201
3202         /* Reset software totals */
3203         memset(stats, 0, sizeof(*stats));
3204         memset(macsec_stats, 0, sizeof(*macsec_stats));
3205 }
3206
3207 static void
3208 ixgbevf_update_stats(struct rte_eth_dev *dev)
3209 {
3210         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3211         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3212                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3213
3214         /* Good Rx packet, include VF loopback */
3215         UPDATE_VF_STAT(IXGBE_VFGPRC,
3216             hw_stats->last_vfgprc, hw_stats->vfgprc);
3217
3218         /* Good Rx octets, include VF loopback */
3219         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3220             hw_stats->last_vfgorc, hw_stats->vfgorc);
3221
3222         /* Good Tx packet, include VF loopback */
3223         UPDATE_VF_STAT(IXGBE_VFGPTC,
3224             hw_stats->last_vfgptc, hw_stats->vfgptc);
3225
3226         /* Good Tx octets, include VF loopback */
3227         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3228             hw_stats->last_vfgotc, hw_stats->vfgotc);
3229
3230         /* Rx Multicst Packet */
3231         UPDATE_VF_STAT(IXGBE_VFMPRC,
3232             hw_stats->last_vfmprc, hw_stats->vfmprc);
3233 }
3234
3235 static int
3236 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3237                        unsigned n)
3238 {
3239         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3240                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3241         unsigned i;
3242
3243         if (n < IXGBEVF_NB_XSTATS)
3244                 return IXGBEVF_NB_XSTATS;
3245
3246         ixgbevf_update_stats(dev);
3247
3248         if (!xstats)
3249                 return 0;
3250
3251         /* Extended stats */
3252         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3253                 xstats[i].id = i;
3254                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3255                         rte_ixgbevf_stats_strings[i].offset);
3256         }
3257
3258         return IXGBEVF_NB_XSTATS;
3259 }
3260
3261 static void
3262 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3263 {
3264         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3265                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3266
3267         ixgbevf_update_stats(dev);
3268
3269         if (stats == NULL)
3270                 return;
3271
3272         stats->ipackets = hw_stats->vfgprc;
3273         stats->ibytes = hw_stats->vfgorc;
3274         stats->opackets = hw_stats->vfgptc;
3275         stats->obytes = hw_stats->vfgotc;
3276 }
3277
3278 static void
3279 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3280 {
3281         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3282                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3283
3284         /* Sync HW register to the last stats */
3285         ixgbevf_dev_stats_get(dev, NULL);
3286
3287         /* reset HW current stats*/
3288         hw_stats->vfgprc = 0;
3289         hw_stats->vfgorc = 0;
3290         hw_stats->vfgptc = 0;
3291         hw_stats->vfgotc = 0;
3292 }
3293
3294 static int
3295 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3296 {
3297         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3298         u16 eeprom_verh, eeprom_verl;
3299         u32 etrack_id;
3300         int ret;
3301
3302         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3303         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3304
3305         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3306         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3307
3308         ret += 1; /* add the size of '\0' */
3309         if (fw_size < (u32)ret)
3310                 return ret;
3311         else
3312                 return 0;
3313 }
3314
3315 static void
3316 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3317 {
3318         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3319         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3320         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3321
3322         dev_info->pci_dev = pci_dev;
3323         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3324         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3325         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3326                 /*
3327                  * When DCB/VT is off, maximum number of queues changes,
3328                  * except for 82598EB, which remains constant.
3329                  */
3330                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3331                                 hw->mac.type != ixgbe_mac_82598EB)
3332                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3333         }
3334         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3335         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3336         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3337         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3338         dev_info->max_vfs = pci_dev->max_vfs;
3339         if (hw->mac.type == ixgbe_mac_82598EB)
3340                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3341         else
3342                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3343         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3344         dev_info->rx_offload_capa =
3345                 DEV_RX_OFFLOAD_VLAN_STRIP |
3346                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3347                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3348                 DEV_RX_OFFLOAD_TCP_CKSUM;
3349
3350         /*
3351          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3352          * mode.
3353          */
3354         if ((hw->mac.type == ixgbe_mac_82599EB ||
3355              hw->mac.type == ixgbe_mac_X540) &&
3356             !RTE_ETH_DEV_SRIOV(dev).active)
3357                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3358
3359         if (hw->mac.type == ixgbe_mac_82599EB ||
3360             hw->mac.type == ixgbe_mac_X540)
3361                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3362
3363         if (hw->mac.type == ixgbe_mac_X550 ||
3364             hw->mac.type == ixgbe_mac_X550EM_x ||
3365             hw->mac.type == ixgbe_mac_X550EM_a)
3366                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3367
3368         dev_info->tx_offload_capa =
3369                 DEV_TX_OFFLOAD_VLAN_INSERT |
3370                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3371                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3372                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3373                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3374                 DEV_TX_OFFLOAD_TCP_TSO;
3375
3376         if (hw->mac.type == ixgbe_mac_82599EB ||
3377             hw->mac.type == ixgbe_mac_X540)
3378                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3379
3380         if (hw->mac.type == ixgbe_mac_X550 ||
3381             hw->mac.type == ixgbe_mac_X550EM_x ||
3382             hw->mac.type == ixgbe_mac_X550EM_a)
3383                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3384
3385         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3386                 .rx_thresh = {
3387                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3388                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3389                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3390                 },
3391                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3392                 .rx_drop_en = 0,
3393         };
3394
3395         dev_info->default_txconf = (struct rte_eth_txconf) {
3396                 .tx_thresh = {
3397                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3398                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3399                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3400                 },
3401                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3402                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3403                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3404                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3405         };
3406
3407         dev_info->rx_desc_lim = rx_desc_lim;
3408         dev_info->tx_desc_lim = tx_desc_lim;
3409
3410         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3411         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3412         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3413
3414         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3415         if (hw->mac.type == ixgbe_mac_X540 ||
3416             hw->mac.type == ixgbe_mac_X540_vf ||
3417             hw->mac.type == ixgbe_mac_X550 ||
3418             hw->mac.type == ixgbe_mac_X550_vf) {
3419                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3420         }
3421 }
3422
3423 static const uint32_t *
3424 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3425 {
3426         static const uint32_t ptypes[] = {
3427                 /* For non-vec functions,
3428                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3429                  * for vec functions,
3430                  * refers to _recv_raw_pkts_vec().
3431                  */
3432                 RTE_PTYPE_L2_ETHER,
3433                 RTE_PTYPE_L3_IPV4,
3434                 RTE_PTYPE_L3_IPV4_EXT,
3435                 RTE_PTYPE_L3_IPV6,
3436                 RTE_PTYPE_L3_IPV6_EXT,
3437                 RTE_PTYPE_L4_SCTP,
3438                 RTE_PTYPE_L4_TCP,
3439                 RTE_PTYPE_L4_UDP,
3440                 RTE_PTYPE_TUNNEL_IP,
3441                 RTE_PTYPE_INNER_L3_IPV6,
3442                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3443                 RTE_PTYPE_INNER_L4_TCP,
3444                 RTE_PTYPE_INNER_L4_UDP,
3445                 RTE_PTYPE_UNKNOWN
3446         };
3447
3448         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3449             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3450             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3451             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3452                 return ptypes;
3453         return NULL;
3454 }
3455
3456 static void
3457 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3458                      struct rte_eth_dev_info *dev_info)
3459 {
3460         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3461         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3462
3463         dev_info->pci_dev = pci_dev;
3464         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3465         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3466         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3467         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3468         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3469         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3470         dev_info->max_vfs = pci_dev->max_vfs;
3471         if (hw->mac.type == ixgbe_mac_82598EB)
3472                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3473         else
3474                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3475         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3476                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3477                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3478                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3479         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3480                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3481                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3482                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3483                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3484                                 DEV_TX_OFFLOAD_TCP_TSO;
3485
3486         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3487                 .rx_thresh = {
3488                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3489                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3490                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3491                 },
3492                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3493                 .rx_drop_en = 0,
3494         };
3495
3496         dev_info->default_txconf = (struct rte_eth_txconf) {
3497                 .tx_thresh = {
3498                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3499                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3500                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3501                 },
3502                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3503                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3504                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3505                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3506         };
3507
3508         dev_info->rx_desc_lim = rx_desc_lim;
3509         dev_info->tx_desc_lim = tx_desc_lim;
3510 }
3511
3512 /* return 0 means link status changed, -1 means not changed */
3513 static int
3514 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3515 {
3516         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3517         struct rte_eth_link link, old;
3518         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3519         int link_up;
3520         int diag;
3521
3522         link.link_status = ETH_LINK_DOWN;
3523         link.link_speed = 0;
3524         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3525         memset(&old, 0, sizeof(old));
3526         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3527
3528         hw->mac.get_link_status = true;
3529
3530         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3531         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3532                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3533         else
3534                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3535
3536         if (diag != 0) {
3537                 link.link_speed = ETH_SPEED_NUM_100M;
3538                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3539                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3540                 if (link.link_status == old.link_status)
3541                         return -1;
3542                 return 0;
3543         }
3544
3545         if (link_up == 0) {
3546                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3547                 if (link.link_status == old.link_status)
3548                         return -1;
3549                 return 0;
3550         }
3551         link.link_status = ETH_LINK_UP;
3552         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3553
3554         switch (link_speed) {
3555         default:
3556         case IXGBE_LINK_SPEED_UNKNOWN:
3557                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3558                 link.link_speed = ETH_SPEED_NUM_100M;
3559                 break;
3560
3561         case IXGBE_LINK_SPEED_100_FULL:
3562                 link.link_speed = ETH_SPEED_NUM_100M;
3563                 break;
3564
3565         case IXGBE_LINK_SPEED_1GB_FULL:
3566                 link.link_speed = ETH_SPEED_NUM_1G;
3567                 break;
3568
3569         case IXGBE_LINK_SPEED_10GB_FULL:
3570                 link.link_speed = ETH_SPEED_NUM_10G;
3571                 break;
3572         }
3573         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3574
3575         if (link.link_status == old.link_status)
3576                 return -1;
3577
3578         return 0;
3579 }
3580
3581 static void
3582 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3583 {
3584         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3585         uint32_t fctrl;
3586
3587         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3588         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3589         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3590 }
3591
3592 static void
3593 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3594 {
3595         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3596         uint32_t fctrl;
3597
3598         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3599         fctrl &= (~IXGBE_FCTRL_UPE);
3600         if (dev->data->all_multicast == 1)
3601                 fctrl |= IXGBE_FCTRL_MPE;
3602         else
3603                 fctrl &= (~IXGBE_FCTRL_MPE);
3604         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3605 }
3606
3607 static void
3608 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3609 {
3610         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3611         uint32_t fctrl;
3612
3613         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3614         fctrl |= IXGBE_FCTRL_MPE;
3615         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3616 }
3617
3618 static void
3619 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3620 {
3621         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3622         uint32_t fctrl;
3623
3624         if (dev->data->promiscuous == 1)
3625                 return; /* must remain in all_multicast mode */
3626
3627         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3628         fctrl &= (~IXGBE_FCTRL_MPE);
3629         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3630 }
3631
3632 /**
3633  * It clears the interrupt causes and enables the interrupt.
3634  * It will be called once only during nic initialized.
3635  *
3636  * @param dev
3637  *  Pointer to struct rte_eth_dev.
3638  *
3639  * @return
3640  *  - On success, zero.
3641  *  - On failure, a negative value.
3642  */
3643 static int
3644 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3645 {
3646         struct ixgbe_interrupt *intr =
3647                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3648
3649         ixgbe_dev_link_status_print(dev);
3650         intr->mask |= IXGBE_EICR_LSC;
3651
3652         return 0;
3653 }
3654
3655 /**
3656  * It clears the interrupt causes and enables the interrupt.
3657  * It will be called once only during nic initialized.
3658  *
3659  * @param dev
3660  *  Pointer to struct rte_eth_dev.
3661  *
3662  * @return
3663  *  - On success, zero.
3664  *  - On failure, a negative value.
3665  */
3666 static int
3667 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3668 {
3669         struct ixgbe_interrupt *intr =
3670                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3671
3672         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3673
3674         return 0;
3675 }
3676
3677 /**
3678  * It clears the interrupt causes and enables the interrupt.
3679  * It will be called once only during nic initialized.
3680  *
3681  * @param dev
3682  *  Pointer to struct rte_eth_dev.
3683  *
3684  * @return
3685  *  - On success, zero.
3686  *  - On failure, a negative value.
3687  */
3688 static int
3689 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3690 {
3691         struct ixgbe_interrupt *intr =
3692                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3693
3694         intr->mask |= IXGBE_EICR_LINKSEC;
3695
3696         return 0;
3697 }
3698
3699 /*
3700  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3701  *
3702  * @param dev
3703  *  Pointer to struct rte_eth_dev.
3704  *
3705  * @return
3706  *  - On success, zero.
3707  *  - On failure, a negative value.
3708  */
3709 static int
3710 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3711 {
3712         uint32_t eicr;
3713         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3714         struct ixgbe_interrupt *intr =
3715                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3716
3717         /* clear all cause mask */
3718         ixgbe_disable_intr(hw);
3719
3720         /* read-on-clear nic registers here */
3721         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3722         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3723
3724         intr->flags = 0;
3725
3726         /* set flag for async link update */
3727         if (eicr & IXGBE_EICR_LSC)
3728                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3729
3730         if (eicr & IXGBE_EICR_MAILBOX)
3731                 intr->flags |= IXGBE_FLAG_MAILBOX;
3732
3733         if (eicr & IXGBE_EICR_LINKSEC)
3734                 intr->flags |= IXGBE_FLAG_MACSEC;
3735
3736         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3737             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3738             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3739                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3740
3741         return 0;
3742 }
3743
3744 /**
3745  * It gets and then prints the link status.
3746  *
3747  * @param dev
3748  *  Pointer to struct rte_eth_dev.
3749  *
3750  * @return
3751  *  - On success, zero.
3752  *  - On failure, a negative value.
3753  */
3754 static void
3755 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3756 {
3757         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3758         struct rte_eth_link link;
3759
3760         memset(&link, 0, sizeof(link));
3761         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3762         if (link.link_status) {
3763                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3764                                         (int)(dev->data->port_id),
3765                                         (unsigned)link.link_speed,
3766                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3767                                         "full-duplex" : "half-duplex");
3768         } else {
3769                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3770                                 (int)(dev->data->port_id));
3771         }
3772         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3773                                 pci_dev->addr.domain,
3774                                 pci_dev->addr.bus,
3775                                 pci_dev->addr.devid,
3776                                 pci_dev->addr.function);
3777 }
3778
3779 /*
3780  * It executes link_update after knowing an interrupt occurred.
3781  *
3782  * @param dev
3783  *  Pointer to struct rte_eth_dev.
3784  *
3785  * @return
3786  *  - On success, zero.
3787  *  - On failure, a negative value.
3788  */
3789 static int
3790 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3791                            struct rte_intr_handle *intr_handle)
3792 {
3793         struct ixgbe_interrupt *intr =
3794                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3795         int64_t timeout;
3796         struct rte_eth_link link;
3797         struct ixgbe_hw *hw =
3798                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3799
3800         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3801
3802         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3803                 ixgbe_pf_mbx_process(dev);
3804                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3805         }
3806
3807         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3808                 ixgbe_handle_lasi(hw);
3809                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3810         }
3811
3812         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3813                 /* get the link status before link update, for predicting later */
3814                 memset(&link, 0, sizeof(link));
3815                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3816
3817                 ixgbe_dev_link_update(dev, 0);
3818
3819                 /* likely to up */
3820                 if (!link.link_status)
3821                         /* handle it 1 sec later, wait it being stable */
3822                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3823                 /* likely to down */
3824                 else
3825                         /* handle it 4 sec later, wait it being stable */
3826                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3827
3828                 ixgbe_dev_link_status_print(dev);
3829                 intr->mask_original = intr->mask;
3830                 /* only disable lsc interrupt */
3831                 intr->mask &= ~IXGBE_EIMS_LSC;
3832                 if (rte_eal_alarm_set(timeout * 1000,
3833                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3834                         PMD_DRV_LOG(ERR, "Error setting alarm");
3835                 else
3836                         intr->mask = intr->mask_original;
3837         }
3838
3839         PMD_DRV_LOG(DEBUG, "enable intr immediately");
3840         ixgbe_enable_intr(dev);
3841         rte_intr_enable(intr_handle);
3842
3843         return 0;
3844 }
3845
3846 /**
3847  * Interrupt handler which shall be registered for alarm callback for delayed
3848  * handling specific interrupt to wait for the stable nic state. As the
3849  * NIC interrupt state is not stable for ixgbe after link is just down,
3850  * it needs to wait 4 seconds to get the stable status.
3851  *
3852  * @param handle
3853  *  Pointer to interrupt handle.
3854  * @param param
3855  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3856  *
3857  * @return
3858  *  void
3859  */
3860 static void
3861 ixgbe_dev_interrupt_delayed_handler(void *param)
3862 {
3863         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3864         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3865         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3866         struct ixgbe_interrupt *intr =
3867                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3868         struct ixgbe_hw *hw =
3869                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3870         uint32_t eicr;
3871
3872         ixgbe_disable_intr(hw);
3873
3874         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3875         if (eicr & IXGBE_EICR_MAILBOX)
3876                 ixgbe_pf_mbx_process(dev);
3877
3878         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3879                 ixgbe_handle_lasi(hw);
3880                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3881         }
3882
3883         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3884                 ixgbe_dev_link_update(dev, 0);
3885                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3886                 ixgbe_dev_link_status_print(dev);
3887                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3888         }
3889
3890         if (intr->flags & IXGBE_FLAG_MACSEC) {
3891                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3892                                               NULL);
3893                 intr->flags &= ~IXGBE_FLAG_MACSEC;
3894         }
3895
3896         /* restore original mask */
3897         intr->mask = intr->mask_original;
3898         intr->mask_original = 0;
3899
3900         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3901         ixgbe_enable_intr(dev);
3902         rte_intr_enable(intr_handle);
3903 }
3904
3905 /**
3906  * Interrupt handler triggered by NIC  for handling
3907  * specific interrupt.
3908  *
3909  * @param handle
3910  *  Pointer to interrupt handle.
3911  * @param param
3912  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3913  *
3914  * @return
3915  *  void
3916  */
3917 static void
3918 ixgbe_dev_interrupt_handler(void *param)
3919 {
3920         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3921
3922         ixgbe_dev_interrupt_get_status(dev);
3923         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
3924 }
3925
3926 static int
3927 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3928 {
3929         struct ixgbe_hw *hw;
3930
3931         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3932         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3933 }
3934
3935 static int
3936 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3937 {
3938         struct ixgbe_hw *hw;
3939
3940         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3941         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3942 }
3943
3944 static int
3945 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3946 {
3947         struct ixgbe_hw *hw;
3948         uint32_t mflcn_reg;
3949         uint32_t fccfg_reg;
3950         int rx_pause;
3951         int tx_pause;
3952
3953         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3954
3955         fc_conf->pause_time = hw->fc.pause_time;
3956         fc_conf->high_water = hw->fc.high_water[0];
3957         fc_conf->low_water = hw->fc.low_water[0];
3958         fc_conf->send_xon = hw->fc.send_xon;
3959         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3960
3961         /*
3962          * Return rx_pause status according to actual setting of
3963          * MFLCN register.
3964          */
3965         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3966         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3967                 rx_pause = 1;
3968         else
3969                 rx_pause = 0;
3970
3971         /*
3972          * Return tx_pause status according to actual setting of
3973          * FCCFG register.
3974          */
3975         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3976         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3977                 tx_pause = 1;
3978         else
3979                 tx_pause = 0;
3980
3981         if (rx_pause && tx_pause)
3982                 fc_conf->mode = RTE_FC_FULL;
3983         else if (rx_pause)
3984                 fc_conf->mode = RTE_FC_RX_PAUSE;
3985         else if (tx_pause)
3986                 fc_conf->mode = RTE_FC_TX_PAUSE;
3987         else
3988                 fc_conf->mode = RTE_FC_NONE;
3989
3990         return 0;
3991 }
3992
3993 static int
3994 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3995 {
3996         struct ixgbe_hw *hw;
3997         int err;
3998         uint32_t rx_buf_size;
3999         uint32_t max_high_water;
4000         uint32_t mflcn;
4001         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4002                 ixgbe_fc_none,
4003                 ixgbe_fc_rx_pause,
4004                 ixgbe_fc_tx_pause,
4005                 ixgbe_fc_full
4006         };
4007
4008         PMD_INIT_FUNC_TRACE();
4009
4010         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4011         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4012         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4013
4014         /*
4015          * At least reserve one Ethernet frame for watermark
4016          * high_water/low_water in kilo bytes for ixgbe
4017          */
4018         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4019         if ((fc_conf->high_water > max_high_water) ||
4020                 (fc_conf->high_water < fc_conf->low_water)) {
4021                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4022                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4023                 return -EINVAL;
4024         }
4025
4026         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4027         hw->fc.pause_time     = fc_conf->pause_time;
4028         hw->fc.high_water[0]  = fc_conf->high_water;
4029         hw->fc.low_water[0]   = fc_conf->low_water;
4030         hw->fc.send_xon       = fc_conf->send_xon;
4031         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4032
4033         err = ixgbe_fc_enable(hw);
4034
4035         /* Not negotiated is not an error case */
4036         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4037
4038                 /* check if we want to forward MAC frames - driver doesn't have native
4039                  * capability to do that, so we'll write the registers ourselves */
4040
4041                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4042
4043                 /* set or clear MFLCN.PMCF bit depending on configuration */
4044                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4045                         mflcn |= IXGBE_MFLCN_PMCF;
4046                 else
4047                         mflcn &= ~IXGBE_MFLCN_PMCF;
4048
4049                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4050                 IXGBE_WRITE_FLUSH(hw);
4051
4052                 return 0;
4053         }
4054
4055         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4056         return -EIO;
4057 }
4058
4059 /**
4060  *  ixgbe_pfc_enable_generic - Enable flow control
4061  *  @hw: pointer to hardware structure
4062  *  @tc_num: traffic class number
4063  *  Enable flow control according to the current settings.
4064  */
4065 static int
4066 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4067 {
4068         int ret_val = 0;
4069         uint32_t mflcn_reg, fccfg_reg;
4070         uint32_t reg;
4071         uint32_t fcrtl, fcrth;
4072         uint8_t i;
4073         uint8_t nb_rx_en;
4074
4075         /* Validate the water mark configuration */
4076         if (!hw->fc.pause_time) {
4077                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4078                 goto out;
4079         }
4080
4081         /* Low water mark of zero causes XOFF floods */
4082         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4083                  /* High/Low water can not be 0 */
4084                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4085                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4086                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4087                         goto out;
4088                 }
4089
4090                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4091                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4092                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4093                         goto out;
4094                 }
4095         }
4096         /* Negotiate the fc mode to use */
4097         ixgbe_fc_autoneg(hw);
4098
4099         /* Disable any previous flow control settings */
4100         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4101         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4102
4103         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4104         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4105
4106         switch (hw->fc.current_mode) {
4107         case ixgbe_fc_none:
4108                 /*
4109                  * If the count of enabled RX Priority Flow control >1,
4110                  * and the TX pause can not be disabled
4111                  */
4112                 nb_rx_en = 0;
4113                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4114                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4115                         if (reg & IXGBE_FCRTH_FCEN)
4116                                 nb_rx_en++;
4117                 }
4118                 if (nb_rx_en > 1)
4119                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4120                 break;
4121         case ixgbe_fc_rx_pause:
4122                 /*
4123                  * Rx Flow control is enabled and Tx Flow control is
4124                  * disabled by software override. Since there really
4125                  * isn't a way to advertise that we are capable of RX
4126                  * Pause ONLY, we will advertise that we support both
4127                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4128                  * disable the adapter's ability to send PAUSE frames.
4129                  */
4130                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4131                 /*
4132                  * If the count of enabled RX Priority Flow control >1,
4133                  * and the TX pause can not be disabled
4134                  */
4135                 nb_rx_en = 0;
4136                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4137                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4138                         if (reg & IXGBE_FCRTH_FCEN)
4139                                 nb_rx_en++;
4140                 }
4141                 if (nb_rx_en > 1)
4142                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4143                 break;
4144         case ixgbe_fc_tx_pause:
4145                 /*
4146                  * Tx Flow control is enabled, and Rx Flow control is
4147                  * disabled by software override.
4148                  */
4149                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4150                 break;
4151         case ixgbe_fc_full:
4152                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4153                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4154                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4155                 break;
4156         default:
4157                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4158                 ret_val = IXGBE_ERR_CONFIG;
4159                 goto out;
4160         }
4161
4162         /* Set 802.3x based flow control settings. */
4163         mflcn_reg |= IXGBE_MFLCN_DPF;
4164         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4165         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4166
4167         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4168         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4169                 hw->fc.high_water[tc_num]) {
4170                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4171                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4172                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4173         } else {
4174                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4175                 /*
4176                  * In order to prevent Tx hangs when the internal Tx
4177                  * switch is enabled we must set the high water mark
4178                  * to the maximum FCRTH value.  This allows the Tx
4179                  * switch to function even under heavy Rx workloads.
4180                  */
4181                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4182         }
4183         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4184
4185         /* Configure pause time (2 TCs per register) */
4186         reg = hw->fc.pause_time * 0x00010001;
4187         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4188                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4189
4190         /* Configure flow control refresh threshold value */
4191         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4192
4193 out:
4194         return ret_val;
4195 }
4196
4197 static int
4198 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4199 {
4200         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4201         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4202
4203         if (hw->mac.type != ixgbe_mac_82598EB) {
4204                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4205         }
4206         return ret_val;
4207 }
4208
4209 static int
4210 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4211 {
4212         int err;
4213         uint32_t rx_buf_size;
4214         uint32_t max_high_water;
4215         uint8_t tc_num;
4216         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4217         struct ixgbe_hw *hw =
4218                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4219         struct ixgbe_dcb_config *dcb_config =
4220                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4221
4222         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4223                 ixgbe_fc_none,
4224                 ixgbe_fc_rx_pause,
4225                 ixgbe_fc_tx_pause,
4226                 ixgbe_fc_full
4227         };
4228
4229         PMD_INIT_FUNC_TRACE();
4230
4231         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4232         tc_num = map[pfc_conf->priority];
4233         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4234         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4235         /*
4236          * At least reserve one Ethernet frame for watermark
4237          * high_water/low_water in kilo bytes for ixgbe
4238          */
4239         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4240         if ((pfc_conf->fc.high_water > max_high_water) ||
4241             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4242                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4243                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4244                 return -EINVAL;
4245         }
4246
4247         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4248         hw->fc.pause_time = pfc_conf->fc.pause_time;
4249         hw->fc.send_xon = pfc_conf->fc.send_xon;
4250         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4251         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4252
4253         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4254
4255         /* Not negotiated is not an error case */
4256         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4257                 return 0;
4258
4259         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4260         return -EIO;
4261 }
4262
4263 static int
4264 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4265                           struct rte_eth_rss_reta_entry64 *reta_conf,
4266                           uint16_t reta_size)
4267 {
4268         uint16_t i, sp_reta_size;
4269         uint8_t j, mask;
4270         uint32_t reta, r;
4271         uint16_t idx, shift;
4272         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4273         uint32_t reta_reg;
4274
4275         PMD_INIT_FUNC_TRACE();
4276
4277         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4278                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4279                         "NIC.");
4280                 return -ENOTSUP;
4281         }
4282
4283         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4284         if (reta_size != sp_reta_size) {
4285                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4286                         "(%d) doesn't match the number hardware can supported "
4287                         "(%d)", reta_size, sp_reta_size);
4288                 return -EINVAL;
4289         }
4290
4291         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4292                 idx = i / RTE_RETA_GROUP_SIZE;
4293                 shift = i % RTE_RETA_GROUP_SIZE;
4294                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4295                                                 IXGBE_4_BIT_MASK);
4296                 if (!mask)
4297                         continue;
4298                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4299                 if (mask == IXGBE_4_BIT_MASK)
4300                         r = 0;
4301                 else
4302                         r = IXGBE_READ_REG(hw, reta_reg);
4303                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4304                         if (mask & (0x1 << j))
4305                                 reta |= reta_conf[idx].reta[shift + j] <<
4306                                                         (CHAR_BIT * j);
4307                         else
4308                                 reta |= r & (IXGBE_8_BIT_MASK <<
4309                                                 (CHAR_BIT * j));
4310                 }
4311                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4312         }
4313
4314         return 0;
4315 }
4316
4317 static int
4318 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4319                          struct rte_eth_rss_reta_entry64 *reta_conf,
4320                          uint16_t reta_size)
4321 {
4322         uint16_t i, sp_reta_size;
4323         uint8_t j, mask;
4324         uint32_t reta;
4325         uint16_t idx, shift;
4326         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4327         uint32_t reta_reg;
4328
4329         PMD_INIT_FUNC_TRACE();
4330         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4331         if (reta_size != sp_reta_size) {
4332                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4333                         "(%d) doesn't match the number hardware can supported "
4334                         "(%d)", reta_size, sp_reta_size);
4335                 return -EINVAL;
4336         }
4337
4338         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4339                 idx = i / RTE_RETA_GROUP_SIZE;
4340                 shift = i % RTE_RETA_GROUP_SIZE;
4341                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4342                                                 IXGBE_4_BIT_MASK);
4343                 if (!mask)
4344                         continue;
4345
4346                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4347                 reta = IXGBE_READ_REG(hw, reta_reg);
4348                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4349                         if (mask & (0x1 << j))
4350                                 reta_conf[idx].reta[shift + j] =
4351                                         ((reta >> (CHAR_BIT * j)) &
4352                                                 IXGBE_8_BIT_MASK);
4353                 }
4354         }
4355
4356         return 0;
4357 }
4358
4359 static void
4360 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4361                                 uint32_t index, uint32_t pool)
4362 {
4363         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4364         uint32_t enable_addr = 1;
4365
4366         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4367 }
4368
4369 static void
4370 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4371 {
4372         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4373
4374         ixgbe_clear_rar(hw, index);
4375 }
4376
4377 static void
4378 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4379 {
4380         ixgbe_remove_rar(dev, 0);
4381
4382         ixgbe_add_rar(dev, addr, 0, 0);
4383 }
4384
4385 static bool
4386 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
4387 {
4388         if (strcmp(dev->driver->pci_drv.driver.name,
4389                    drv->pci_drv.driver.name))
4390                 return false;
4391
4392         return true;
4393 }
4394
4395 int
4396 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4397                 struct ether_addr *mac_addr)
4398 {
4399         struct ixgbe_hw *hw;
4400         struct ixgbe_vf_info *vfinfo;
4401         int rar_entry;
4402         uint8_t *new_mac = (uint8_t *)(mac_addr);
4403         struct rte_eth_dev *dev;
4404         struct rte_pci_device *pci_dev;
4405
4406         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4407
4408         dev = &rte_eth_devices[port];
4409         pci_dev = IXGBE_DEV_TO_PCI(dev);
4410
4411         if (!is_device_supported(dev, &rte_ixgbe_pmd))
4412                 return -ENOTSUP;
4413
4414         if (vf >= pci_dev->max_vfs)
4415                 return -EINVAL;
4416
4417         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4418         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4419         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4420
4421         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4422                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4423                                 ETHER_ADDR_LEN);
4424                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4425                                 IXGBE_RAH_AV);
4426         }
4427         return -EINVAL;
4428 }
4429
4430 static int
4431 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4432 {
4433         uint32_t hlreg0;
4434         uint32_t maxfrs;
4435         struct ixgbe_hw *hw;
4436         struct rte_eth_dev_info dev_info;
4437         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4438
4439         ixgbe_dev_info_get(dev, &dev_info);
4440
4441         /* check that mtu is within the allowed range */
4442         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4443                 return -EINVAL;
4444
4445         /* refuse mtu that requires the support of scattered packets when this
4446          * feature has not been enabled before.
4447          */
4448         if (!dev->data->scattered_rx &&
4449             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4450              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4451                 return -EINVAL;
4452
4453         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4454         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4455
4456         /* switch to jumbo mode if needed */
4457         if (frame_size > ETHER_MAX_LEN) {
4458                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4459                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4460         } else {
4461                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4462                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4463         }
4464         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4465
4466         /* update max frame size */
4467         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4468
4469         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4470         maxfrs &= 0x0000FFFF;
4471         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4472         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4473
4474         return 0;
4475 }
4476
4477 /*
4478  * Virtual Function operations
4479  */
4480 static void
4481 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4482 {
4483         PMD_INIT_FUNC_TRACE();
4484
4485         /* Clear interrupt mask to stop from interrupts being generated */
4486         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4487
4488         IXGBE_WRITE_FLUSH(hw);
4489 }
4490
4491 static void
4492 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4493 {
4494         PMD_INIT_FUNC_TRACE();
4495
4496         /* VF enable interrupt autoclean */
4497         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4498         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4499         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4500
4501         IXGBE_WRITE_FLUSH(hw);
4502 }
4503
4504 static int
4505 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4506 {
4507         struct rte_eth_conf *conf = &dev->data->dev_conf;
4508         struct ixgbe_adapter *adapter =
4509                         (struct ixgbe_adapter *)dev->data->dev_private;
4510
4511         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4512                      dev->data->port_id);
4513
4514         /*
4515          * VF has no ability to enable/disable HW CRC
4516          * Keep the persistent behavior the same as Host PF
4517          */
4518 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4519         if (!conf->rxmode.hw_strip_crc) {
4520                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4521                 conf->rxmode.hw_strip_crc = 1;
4522         }
4523 #else
4524         if (conf->rxmode.hw_strip_crc) {
4525                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4526                 conf->rxmode.hw_strip_crc = 0;
4527         }
4528 #endif
4529
4530         /*
4531          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4532          * allocation or vector Rx preconditions we will reset it.
4533          */
4534         adapter->rx_bulk_alloc_allowed = true;
4535         adapter->rx_vec_allowed = true;
4536
4537         return 0;
4538 }
4539
4540 static int
4541 ixgbevf_dev_start(struct rte_eth_dev *dev)
4542 {
4543         struct ixgbe_hw *hw =
4544                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4545         uint32_t intr_vector = 0;
4546         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4547         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4548
4549         int err, mask = 0;
4550
4551         PMD_INIT_FUNC_TRACE();
4552
4553         hw->mac.ops.reset_hw(hw);
4554         hw->mac.get_link_status = true;
4555
4556         /* negotiate mailbox API version to use with the PF. */
4557         ixgbevf_negotiate_api(hw);
4558
4559         ixgbevf_dev_tx_init(dev);
4560
4561         /* This can fail when allocating mbufs for descriptor rings */
4562         err = ixgbevf_dev_rx_init(dev);
4563         if (err) {
4564                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4565                 ixgbe_dev_clear_queues(dev);
4566                 return err;
4567         }
4568
4569         /* Set vfta */
4570         ixgbevf_set_vfta_all(dev, 1);
4571
4572         /* Set HW strip */
4573         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4574                 ETH_VLAN_EXTEND_MASK;
4575         ixgbevf_vlan_offload_set(dev, mask);
4576
4577         ixgbevf_dev_rxtx_start(dev);
4578
4579         /* check and configure queue intr-vector mapping */
4580         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4581                 intr_vector = dev->data->nb_rx_queues;
4582                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4583                         return -1;
4584         }
4585
4586         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4587                 intr_handle->intr_vec =
4588                         rte_zmalloc("intr_vec",
4589                                     dev->data->nb_rx_queues * sizeof(int), 0);
4590                 if (intr_handle->intr_vec == NULL) {
4591                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4592                                      " intr_vec", dev->data->nb_rx_queues);
4593                         return -ENOMEM;
4594                 }
4595         }
4596         ixgbevf_configure_msix(dev);
4597
4598         rte_intr_enable(intr_handle);
4599
4600         /* Re-enable interrupt for VF */
4601         ixgbevf_intr_enable(hw);
4602
4603         return 0;
4604 }
4605
4606 static void
4607 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4608 {
4609         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4610         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4611         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4612
4613         PMD_INIT_FUNC_TRACE();
4614
4615         ixgbevf_intr_disable(hw);
4616
4617         hw->adapter_stopped = 1;
4618         ixgbe_stop_adapter(hw);
4619
4620         /*
4621           * Clear what we set, but we still keep shadow_vfta to
4622           * restore after device starts
4623           */
4624         ixgbevf_set_vfta_all(dev, 0);
4625
4626         /* Clear stored conf */
4627         dev->data->scattered_rx = 0;
4628
4629         ixgbe_dev_clear_queues(dev);
4630
4631         /* Clean datapath event and queue/vec mapping */
4632         rte_intr_efd_disable(intr_handle);
4633         if (intr_handle->intr_vec != NULL) {
4634                 rte_free(intr_handle->intr_vec);
4635                 intr_handle->intr_vec = NULL;
4636         }
4637 }
4638
4639 static void
4640 ixgbevf_dev_close(struct rte_eth_dev *dev)
4641 {
4642         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4643
4644         PMD_INIT_FUNC_TRACE();
4645
4646         ixgbe_reset_hw(hw);
4647
4648         ixgbevf_dev_stop(dev);
4649
4650         ixgbe_dev_free_queues(dev);
4651
4652         /**
4653          * Remove the VF MAC address ro ensure
4654          * that the VF traffic goes to the PF
4655          * after stop, close and detach of the VF
4656          **/
4657         ixgbevf_remove_mac_addr(dev, 0);
4658 }
4659
4660 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4661 {
4662         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4663         struct ixgbe_vfta *shadow_vfta =
4664                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4665         int i = 0, j = 0, vfta = 0, mask = 1;
4666
4667         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4668                 vfta = shadow_vfta->vfta[i];
4669                 if (vfta) {
4670                         mask = 1;
4671                         for (j = 0; j < 32; j++) {
4672                                 if (vfta & mask)
4673                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4674                                                        on, false);
4675                                 mask <<= 1;
4676                         }
4677                 }
4678         }
4679
4680 }
4681
4682 static int
4683 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4684 {
4685         struct ixgbe_hw *hw =
4686                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4687         struct ixgbe_vfta *shadow_vfta =
4688                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4689         uint32_t vid_idx = 0;
4690         uint32_t vid_bit = 0;
4691         int ret = 0;
4692
4693         PMD_INIT_FUNC_TRACE();
4694
4695         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4696         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4697         if (ret) {
4698                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4699                 return ret;
4700         }
4701         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4702         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4703
4704         /* Save what we set and retore it after device reset */
4705         if (on)
4706                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4707         else
4708                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4709
4710         return 0;
4711 }
4712
4713 static void
4714 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4715 {
4716         struct ixgbe_hw *hw =
4717                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4718         uint32_t ctrl;
4719
4720         PMD_INIT_FUNC_TRACE();
4721
4722         if (queue >= hw->mac.max_rx_queues)
4723                 return;
4724
4725         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4726         if (on)
4727                 ctrl |= IXGBE_RXDCTL_VME;
4728         else
4729                 ctrl &= ~IXGBE_RXDCTL_VME;
4730         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4731
4732         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4733 }
4734
4735 static void
4736 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4737 {
4738         struct ixgbe_hw *hw =
4739                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4740         uint16_t i;
4741         int on = 0;
4742
4743         /* VF function only support hw strip feature, others are not support */
4744         if (mask & ETH_VLAN_STRIP_MASK) {
4745                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4746
4747                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4748                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4749         }
4750 }
4751
4752 static int
4753 ixgbe_vt_check(struct ixgbe_hw *hw)
4754 {
4755         uint32_t reg_val;
4756
4757         /* if Virtualization Technology is enabled */
4758         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4759         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4760                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4761                 return -1;
4762         }
4763
4764         return 0;
4765 }
4766
4767 static uint32_t
4768 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4769 {
4770         uint32_t vector = 0;
4771
4772         switch (hw->mac.mc_filter_type) {
4773         case 0:   /* use bits [47:36] of the address */
4774                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4775                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4776                 break;
4777         case 1:   /* use bits [46:35] of the address */
4778                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4779                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4780                 break;
4781         case 2:   /* use bits [45:34] of the address */
4782                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4783                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4784                 break;
4785         case 3:   /* use bits [43:32] of the address */
4786                 vector = ((uc_addr->addr_bytes[4]) |
4787                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4788                 break;
4789         default:  /* Invalid mc_filter_type */
4790                 break;
4791         }
4792
4793         /* vector can only be 12-bits or boundary will be exceeded */
4794         vector &= 0xFFF;
4795         return vector;
4796 }
4797
4798 static int
4799 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4800                         uint8_t on)
4801 {
4802         uint32_t vector;
4803         uint32_t uta_idx;
4804         uint32_t reg_val;
4805         uint32_t uta_shift;
4806         uint32_t rc;
4807         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4808         const uint32_t ixgbe_uta_bit_shift = 5;
4809         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4810         const uint32_t bit1 = 0x1;
4811
4812         struct ixgbe_hw *hw =
4813                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4814         struct ixgbe_uta_info *uta_info =
4815                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4816
4817         /* The UTA table only exists on 82599 hardware and newer */
4818         if (hw->mac.type < ixgbe_mac_82599EB)
4819                 return -ENOTSUP;
4820
4821         vector = ixgbe_uta_vector(hw, mac_addr);
4822         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4823         uta_shift = vector & ixgbe_uta_bit_mask;
4824
4825         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4826         if (rc == on)
4827                 return 0;
4828
4829         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4830         if (on) {
4831                 uta_info->uta_in_use++;
4832                 reg_val |= (bit1 << uta_shift);
4833                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4834         } else {
4835                 uta_info->uta_in_use--;
4836                 reg_val &= ~(bit1 << uta_shift);
4837                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4838         }
4839
4840         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4841
4842         if (uta_info->uta_in_use > 0)
4843                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4844                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4845         else
4846                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4847
4848         return 0;
4849 }
4850
4851 static int
4852 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4853 {
4854         int i;
4855         struct ixgbe_hw *hw =
4856                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4857         struct ixgbe_uta_info *uta_info =
4858                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4859
4860         /* The UTA table only exists on 82599 hardware and newer */
4861         if (hw->mac.type < ixgbe_mac_82599EB)
4862                 return -ENOTSUP;
4863
4864         if (on) {
4865                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4866                         uta_info->uta_shadow[i] = ~0;
4867                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4868                 }
4869         } else {
4870                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4871                         uta_info->uta_shadow[i] = 0;
4872                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4873                 }
4874         }
4875         return 0;
4876
4877 }
4878
4879 uint32_t
4880 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4881 {
4882         uint32_t new_val = orig_val;
4883
4884         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4885                 new_val |= IXGBE_VMOLR_AUPE;
4886         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4887                 new_val |= IXGBE_VMOLR_ROMPE;
4888         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4889                 new_val |= IXGBE_VMOLR_ROPE;
4890         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4891                 new_val |= IXGBE_VMOLR_BAM;
4892         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4893                 new_val |= IXGBE_VMOLR_MPE;
4894
4895         return new_val;
4896 }
4897
4898 int
4899 rte_pmd_ixgbe_ping_vf(uint8_t port, uint16_t vf)
4900 {
4901         struct ixgbe_hw *hw;
4902         struct ixgbe_vf_info *vfinfo;
4903         struct rte_eth_dev *dev;
4904         struct rte_pci_device *pci_dev;
4905         uint32_t ctrl;
4906
4907         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4908
4909         dev = &rte_eth_devices[port];
4910         pci_dev = IXGBE_DEV_TO_PCI(dev);
4911
4912         if (!is_device_supported(dev, &rte_ixgbe_pmd))
4913                 return -ENOTSUP;
4914
4915         if (vf >= pci_dev->max_vfs)
4916                 return -EINVAL;
4917
4918         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4919         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4920
4921         ctrl = IXGBE_PF_CONTROL_MSG;
4922         if (vfinfo[vf].clear_to_send)
4923                 ctrl |= IXGBE_VT_MSGTYPE_CTS;
4924
4925         ixgbe_write_mbx(hw, &ctrl, 1, vf);
4926
4927         return 0;
4928 }
4929
4930 int
4931 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4932 {
4933         struct ixgbe_hw *hw;
4934         struct ixgbe_mac_info *mac;
4935         struct rte_eth_dev *dev;
4936         struct rte_pci_device *pci_dev;
4937
4938         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4939
4940         dev = &rte_eth_devices[port];
4941         pci_dev = IXGBE_DEV_TO_PCI(dev);
4942
4943         if (!is_device_supported(dev, &rte_ixgbe_pmd))
4944                 return -ENOTSUP;
4945
4946         if (vf >= pci_dev->max_vfs)
4947                 return -EINVAL;
4948
4949         if (on > 1)
4950                 return -EINVAL;
4951
4952         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4953         mac = &hw->mac;
4954
4955         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4956
4957         return 0;
4958 }
4959
4960 int
4961 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4962 {
4963         struct ixgbe_hw *hw;
4964         struct ixgbe_mac_info *mac;
4965         struct rte_eth_dev *dev;
4966         struct rte_pci_device *pci_dev;
4967
4968         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4969
4970         dev = &rte_eth_devices[port];
4971         pci_dev = IXGBE_DEV_TO_PCI(dev);
4972
4973         if (!is_device_supported(dev, &rte_ixgbe_pmd))
4974                 return -ENOTSUP;
4975
4976         if (vf >= pci_dev->max_vfs)
4977                 return -EINVAL;
4978
4979         if (on > 1)
4980                 return -EINVAL;
4981
4982         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4983         mac = &hw->mac;
4984         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4985
4986         return 0;
4987 }
4988
4989 int
4990 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4991 {
4992         struct ixgbe_hw *hw;
4993         uint32_t ctrl;
4994         struct rte_eth_dev *dev;
4995         struct rte_pci_device *pci_dev;
4996
4997         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4998
4999         dev = &rte_eth_devices[port];
5000         pci_dev = IXGBE_DEV_TO_PCI(dev);
5001
5002         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5003                 return -ENOTSUP;
5004
5005         if (vf >= pci_dev->max_vfs)
5006                 return -EINVAL;
5007
5008         if (vlan_id > ETHER_MAX_VLAN_ID)
5009                 return -EINVAL;
5010
5011         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5012         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
5013         if (vlan_id) {
5014                 ctrl = vlan_id;
5015                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
5016         } else {
5017                 ctrl = 0;
5018         }
5019
5020         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
5021
5022         return 0;
5023 }
5024
5025 int
5026 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
5027 {
5028         struct ixgbe_hw *hw;
5029         uint32_t ctrl;
5030         struct rte_eth_dev *dev;
5031
5032         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5033
5034         dev = &rte_eth_devices[port];
5035
5036         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5037                 return -ENOTSUP;
5038
5039         if (on > 1)
5040                 return -EINVAL;
5041
5042         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5043         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5044         /* enable or disable VMDQ loopback */
5045         if (on)
5046                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
5047         else
5048                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5049
5050         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
5051
5052         return 0;
5053 }
5054
5055 int
5056 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
5057 {
5058         struct ixgbe_hw *hw;
5059         uint32_t reg_value;
5060         int i;
5061         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
5062         struct rte_eth_dev *dev;
5063
5064         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5065
5066         dev = &rte_eth_devices[port];
5067
5068         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5069                 return -ENOTSUP;
5070
5071         if (on > 1)
5072                 return -EINVAL;
5073
5074         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5075         for (i = 0; i <= num_queues; i++) {
5076                 reg_value = IXGBE_QDE_WRITE |
5077                                 (i << IXGBE_QDE_IDX_SHIFT) |
5078                                 (on & IXGBE_QDE_ENABLE);
5079                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
5080         }
5081
5082         return 0;
5083 }
5084
5085 int
5086 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
5087 {
5088         struct ixgbe_hw *hw;
5089         uint32_t reg_value;
5090         struct rte_eth_dev *dev;
5091         struct rte_pci_device *pci_dev;
5092
5093         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5094
5095         dev = &rte_eth_devices[port];
5096         pci_dev = IXGBE_DEV_TO_PCI(dev);
5097
5098         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5099                 return -ENOTSUP;
5100
5101         /* only support VF's 0 to 63 */
5102         if ((vf >= pci_dev->max_vfs) || (vf > 63))
5103                 return -EINVAL;
5104
5105         if (on > 1)
5106                 return -EINVAL;
5107
5108         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5109         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
5110         if (on)
5111                 reg_value |= IXGBE_SRRCTL_DROP_EN;
5112         else
5113                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
5114
5115         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
5116
5117         return 0;
5118 }
5119
5120 int
5121 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
5122 {
5123         struct rte_eth_dev *dev;
5124         struct rte_pci_device *pci_dev;
5125         struct ixgbe_hw *hw;
5126         uint16_t queues_per_pool;
5127         uint32_t q;
5128
5129         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5130
5131         dev = &rte_eth_devices[port];
5132         pci_dev = IXGBE_DEV_TO_PCI(dev);
5133         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5134
5135         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5136                 return -ENOTSUP;
5137
5138         if (vf >= pci_dev->max_vfs)
5139                 return -EINVAL;
5140
5141         if (on > 1)
5142                 return -EINVAL;
5143
5144         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5145
5146         /* The PF has 128 queue pairs and in SRIOV configuration
5147          * those queues will be assigned to VF's, so RXDCTL
5148          * registers will be dealing with queues which will be
5149          * assigned to VF's.
5150          * Let's say we have SRIOV configured with 31 VF's then the
5151          * first 124 queues 0-123 will be allocated to VF's and only
5152          * the last 4 queues 123-127 will be assigned to the PF.
5153          */
5154         if (hw->mac.type == ixgbe_mac_82598EB)
5155                 queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
5156                                   ETH_16_POOLS;
5157         else
5158                 queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
5159                                   ETH_64_POOLS;
5160
5161         for (q = 0; q < queues_per_pool; q++)
5162                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5163                                 q + vf * queues_per_pool, on);
5164         return 0;
5165 }
5166
5167 int
5168 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
5169 {
5170         int val = 0;
5171         struct rte_eth_dev *dev;
5172         struct rte_pci_device *pci_dev;
5173         struct ixgbe_hw *hw;
5174         uint32_t vmolr;
5175
5176         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5177
5178         dev = &rte_eth_devices[port];
5179         pci_dev = IXGBE_DEV_TO_PCI(dev);
5180
5181         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5182                 return -ENOTSUP;
5183
5184         if (vf >= pci_dev->max_vfs)
5185                 return -EINVAL;
5186
5187         if (on > 1)
5188                 return -EINVAL;
5189
5190         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5191         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5192
5193         if (hw->mac.type == ixgbe_mac_82598EB) {
5194                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5195                              " on 82599 hardware and newer");
5196                 return -ENOTSUP;
5197         }
5198         if (ixgbe_vt_check(hw) < 0)
5199                 return -ENOTSUP;
5200
5201         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5202
5203         if (on)
5204                 vmolr |= val;
5205         else
5206                 vmolr &= ~val;
5207
5208         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5209
5210         return 0;
5211 }
5212
5213 int
5214 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5215 {
5216         struct rte_eth_dev *dev;
5217         struct rte_pci_device *pci_dev;
5218         uint32_t reg, addr;
5219         uint32_t val;
5220         const uint8_t bit1 = 0x1;
5221         struct ixgbe_hw *hw;
5222
5223         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5224
5225         dev = &rte_eth_devices[port];
5226         pci_dev = IXGBE_DEV_TO_PCI(dev);
5227
5228         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5229                 return -ENOTSUP;
5230
5231         if (vf >= pci_dev->max_vfs)
5232                 return -EINVAL;
5233
5234         if (on > 1)
5235                 return -EINVAL;
5236
5237         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5238
5239         if (ixgbe_vt_check(hw) < 0)
5240                 return -ENOTSUP;
5241
5242         /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5243         if (vf >= 32) {
5244                 addr = IXGBE_VFRE(1);
5245                 val = bit1 << (vf - 32);
5246         } else {
5247                 addr = IXGBE_VFRE(0);
5248                 val = bit1 << vf;
5249         }
5250
5251         reg = IXGBE_READ_REG(hw, addr);
5252
5253         if (on)
5254                 reg |= val;
5255         else
5256                 reg &= ~val;
5257
5258         IXGBE_WRITE_REG(hw, addr, reg);
5259
5260         return 0;
5261 }
5262
5263 int
5264 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5265 {
5266         struct rte_eth_dev *dev;
5267         struct rte_pci_device *pci_dev;
5268         uint32_t reg, addr;
5269         uint32_t val;
5270         const uint8_t bit1 = 0x1;
5271
5272         struct ixgbe_hw *hw;
5273
5274         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5275
5276         dev = &rte_eth_devices[port];
5277         pci_dev = IXGBE_DEV_TO_PCI(dev);
5278
5279         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5280                 return -ENOTSUP;
5281
5282         if (vf >= pci_dev->max_vfs)
5283                 return -EINVAL;
5284
5285         if (on > 1)
5286                 return -EINVAL;
5287
5288         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5289         if (ixgbe_vt_check(hw) < 0)
5290                 return -ENOTSUP;
5291
5292         /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5293         if (vf >= 32) {
5294                 addr = IXGBE_VFTE(1);
5295                 val = bit1 << (vf - 32);
5296         } else {
5297                 addr = IXGBE_VFTE(0);
5298                 val = bit1 << vf;
5299         }
5300
5301         reg = IXGBE_READ_REG(hw, addr);
5302
5303         if (on)
5304                 reg |= val;
5305         else
5306                 reg &= ~val;
5307
5308         IXGBE_WRITE_REG(hw, addr, reg);
5309
5310         return 0;
5311 }
5312
5313 int
5314 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5315                         uint64_t vf_mask, uint8_t vlan_on)
5316 {
5317         struct rte_eth_dev *dev;
5318         int ret = 0;
5319         uint16_t vf_idx;
5320         struct ixgbe_hw *hw;
5321
5322         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5323
5324         dev = &rte_eth_devices[port];
5325
5326         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5327                 return -ENOTSUP;
5328
5329         if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5330                 return -EINVAL;
5331
5332         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5333         if (ixgbe_vt_check(hw) < 0)
5334                 return -ENOTSUP;
5335
5336         for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5337                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5338                         ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5339                                                    vlan_on, false);
5340                         if (ret < 0)
5341                                 return ret;
5342                 }
5343         }
5344
5345         return ret;
5346 }
5347
5348 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5349         uint16_t tx_rate, uint64_t q_msk)
5350 {
5351         struct rte_eth_dev *dev;
5352         struct ixgbe_hw *hw;
5353         struct ixgbe_vf_info *vfinfo;
5354         struct rte_eth_link link;
5355         uint8_t  nb_q_per_pool;
5356         uint32_t queue_stride;
5357         uint32_t queue_idx, idx = 0, vf_idx;
5358         uint32_t queue_end;
5359         uint16_t total_rate = 0;
5360         struct rte_pci_device *pci_dev;
5361
5362         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5363
5364         dev = &rte_eth_devices[port];
5365         pci_dev = IXGBE_DEV_TO_PCI(dev);
5366         rte_eth_link_get_nowait(port, &link);
5367
5368         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5369                 return -ENOTSUP;
5370
5371         if (vf >= pci_dev->max_vfs)
5372                 return -EINVAL;
5373
5374         if (tx_rate > link.link_speed)
5375                 return -EINVAL;
5376
5377         if (q_msk == 0)
5378                 return 0;
5379
5380         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5381         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5382         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5383         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5384         queue_idx = vf * queue_stride;
5385         queue_end = queue_idx + nb_q_per_pool - 1;
5386         if (queue_end >= hw->mac.max_tx_queues)
5387                 return -EINVAL;
5388
5389         if (vfinfo) {
5390                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5391                         if (vf_idx == vf)
5392                                 continue;
5393                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5394                                 idx++)
5395                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5396                 }
5397         } else {
5398                 return -EINVAL;
5399         }
5400
5401         /* Store tx_rate for this vf. */
5402         for (idx = 0; idx < nb_q_per_pool; idx++) {
5403                 if (((uint64_t)0x1 << idx) & q_msk) {
5404                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5405                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5406                         total_rate += tx_rate;
5407                 }
5408         }
5409
5410         if (total_rate > dev->data->dev_link.link_speed) {
5411                 /* Reset stored TX rate of the VF if it causes exceed
5412                  * link speed.
5413                  */
5414                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5415                 return -EINVAL;
5416         }
5417
5418         /* Set RTTBCNRC of each queue/pool for vf X  */
5419         for (; queue_idx <= queue_end; queue_idx++) {
5420                 if (0x1 & q_msk)
5421                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5422                 q_msk = q_msk >> 1;
5423         }
5424
5425         return 0;
5426 }
5427
5428 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5429 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5430 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5431 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5432 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5433         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5434         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5435
5436 static int
5437 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5438                         struct rte_eth_mirror_conf *mirror_conf,
5439                         uint8_t rule_id, uint8_t on)
5440 {
5441         uint32_t mr_ctl, vlvf;
5442         uint32_t mp_lsb = 0;
5443         uint32_t mv_msb = 0;
5444         uint32_t mv_lsb = 0;
5445         uint32_t mp_msb = 0;
5446         uint8_t i = 0;
5447         int reg_index = 0;
5448         uint64_t vlan_mask = 0;
5449
5450         const uint8_t pool_mask_offset = 32;
5451         const uint8_t vlan_mask_offset = 32;
5452         const uint8_t dst_pool_offset = 8;
5453         const uint8_t rule_mr_offset  = 4;
5454         const uint8_t mirror_rule_mask = 0x0F;
5455
5456         struct ixgbe_mirror_info *mr_info =
5457                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5458         struct ixgbe_hw *hw =
5459                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5460         uint8_t mirror_type = 0;
5461
5462         if (ixgbe_vt_check(hw) < 0)
5463                 return -ENOTSUP;
5464
5465         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5466                 return -EINVAL;
5467
5468         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5469                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5470                         mirror_conf->rule_type);
5471                 return -EINVAL;
5472         }
5473
5474         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5475                 mirror_type |= IXGBE_MRCTL_VLME;
5476                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5477                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5478                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5479                                 /* search vlan id related pool vlan filter index */
5480                                 reg_index = ixgbe_find_vlvf_slot(hw,
5481                                                  mirror_conf->vlan.vlan_id[i],
5482                                                  false);
5483                                 if (reg_index < 0)
5484                                         return -EINVAL;
5485                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5486                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5487                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5488                                       mirror_conf->vlan.vlan_id[i]))
5489                                         vlan_mask |= (1ULL << reg_index);
5490                                 else
5491                                         return -EINVAL;
5492                         }
5493                 }
5494
5495                 if (on) {
5496                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5497                         mv_msb = vlan_mask >> vlan_mask_offset;
5498
5499                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5500                                                 mirror_conf->vlan.vlan_mask;
5501                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5502                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5503                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5504                                                 mirror_conf->vlan.vlan_id[i];
5505                         }
5506                 } else {
5507                         mv_lsb = 0;
5508                         mv_msb = 0;
5509                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5510                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5511                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5512                 }
5513         }
5514
5515         /*
5516          * if enable pool mirror, write related pool mask register,if disable
5517          * pool mirror, clear PFMRVM register
5518          */
5519         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5520                 mirror_type |= IXGBE_MRCTL_VPME;
5521                 if (on) {
5522                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5523                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5524                         mr_info->mr_conf[rule_id].pool_mask =
5525                                         mirror_conf->pool_mask;
5526
5527                 } else {
5528                         mp_lsb = 0;
5529                         mp_msb = 0;
5530                         mr_info->mr_conf[rule_id].pool_mask = 0;
5531                 }
5532         }
5533         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5534                 mirror_type |= IXGBE_MRCTL_UPME;
5535         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5536                 mirror_type |= IXGBE_MRCTL_DPME;
5537
5538         /* read  mirror control register and recalculate it */
5539         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5540
5541         if (on) {
5542                 mr_ctl |= mirror_type;
5543                 mr_ctl &= mirror_rule_mask;
5544                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5545         } else
5546                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5547
5548         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5549         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5550
5551         /* write mirrror control  register */
5552         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5553
5554         /* write pool mirrror control  register */
5555         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5556                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5557                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5558                                 mp_msb);
5559         }
5560         /* write VLAN mirrror control  register */
5561         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5562                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5563                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5564                                 mv_msb);
5565         }
5566
5567         return 0;
5568 }
5569
5570 static int
5571 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5572 {
5573         int mr_ctl = 0;
5574         uint32_t lsb_val = 0;
5575         uint32_t msb_val = 0;
5576         const uint8_t rule_mr_offset = 4;
5577
5578         struct ixgbe_hw *hw =
5579                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5580         struct ixgbe_mirror_info *mr_info =
5581                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5582
5583         if (ixgbe_vt_check(hw) < 0)
5584                 return -ENOTSUP;
5585
5586         memset(&mr_info->mr_conf[rule_id], 0,
5587                 sizeof(struct rte_eth_mirror_conf));
5588
5589         /* clear PFVMCTL register */
5590         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5591
5592         /* clear pool mask register */
5593         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5594         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5595
5596         /* clear vlan mask register */
5597         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5598         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5599
5600         return 0;
5601 }
5602
5603 static int
5604 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5605 {
5606         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5607         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5608         uint32_t mask;
5609         struct ixgbe_hw *hw =
5610                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5611
5612         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5613         mask |= (1 << IXGBE_MISC_VEC_ID);
5614         RTE_SET_USED(queue_id);
5615         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5616
5617         rte_intr_enable(intr_handle);
5618
5619         return 0;
5620 }
5621
5622 static int
5623 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5624 {
5625         uint32_t mask;
5626         struct ixgbe_hw *hw =
5627                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5628
5629         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5630         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5631         RTE_SET_USED(queue_id);
5632         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5633
5634         return 0;
5635 }
5636
5637 static int
5638 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5639 {
5640         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5641         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5642         uint32_t mask;
5643         struct ixgbe_hw *hw =
5644                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5645         struct ixgbe_interrupt *intr =
5646                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5647
5648         if (queue_id < 16) {
5649                 ixgbe_disable_intr(hw);
5650                 intr->mask |= (1 << queue_id);
5651                 ixgbe_enable_intr(dev);
5652         } else if (queue_id < 32) {
5653                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5654                 mask &= (1 << queue_id);
5655                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5656         } else if (queue_id < 64) {
5657                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5658                 mask &= (1 << (queue_id - 32));
5659                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5660         }
5661         rte_intr_enable(intr_handle);
5662
5663         return 0;
5664 }
5665
5666 static int
5667 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5668 {
5669         uint32_t mask;
5670         struct ixgbe_hw *hw =
5671                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5672         struct ixgbe_interrupt *intr =
5673                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5674
5675         if (queue_id < 16) {
5676                 ixgbe_disable_intr(hw);
5677                 intr->mask &= ~(1 << queue_id);
5678                 ixgbe_enable_intr(dev);
5679         } else if (queue_id < 32) {
5680                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5681                 mask &= ~(1 << queue_id);
5682                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5683         } else if (queue_id < 64) {
5684                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5685                 mask &= ~(1 << (queue_id - 32));
5686                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5687         }
5688
5689         return 0;
5690 }
5691
5692 static void
5693 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5694                      uint8_t queue, uint8_t msix_vector)
5695 {
5696         uint32_t tmp, idx;
5697
5698         if (direction == -1) {
5699                 /* other causes */
5700                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5701                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5702                 tmp &= ~0xFF;
5703                 tmp |= msix_vector;
5704                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5705         } else {
5706                 /* rx or tx cause */
5707                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5708                 idx = ((16 * (queue & 1)) + (8 * direction));
5709                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5710                 tmp &= ~(0xFF << idx);
5711                 tmp |= (msix_vector << idx);
5712                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5713         }
5714 }
5715
5716 /**
5717  * set the IVAR registers, mapping interrupt causes to vectors
5718  * @param hw
5719  *  pointer to ixgbe_hw struct
5720  * @direction
5721  *  0 for Rx, 1 for Tx, -1 for other causes
5722  * @queue
5723  *  queue to map the corresponding interrupt to
5724  * @msix_vector
5725  *  the vector to map to the corresponding queue
5726  */
5727 static void
5728 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5729                    uint8_t queue, uint8_t msix_vector)
5730 {
5731         uint32_t tmp, idx;
5732
5733         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5734         if (hw->mac.type == ixgbe_mac_82598EB) {
5735                 if (direction == -1)
5736                         direction = 0;
5737                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5738                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5739                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5740                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5741                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5742         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5743                         (hw->mac.type == ixgbe_mac_X540)) {
5744                 if (direction == -1) {
5745                         /* other causes */
5746                         idx = ((queue & 1) * 8);
5747                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5748                         tmp &= ~(0xFF << idx);
5749                         tmp |= (msix_vector << idx);
5750                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5751                 } else {
5752                         /* rx or tx causes */
5753                         idx = ((16 * (queue & 1)) + (8 * direction));
5754                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5755                         tmp &= ~(0xFF << idx);
5756                         tmp |= (msix_vector << idx);
5757                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5758                 }
5759         }
5760 }
5761
5762 static void
5763 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5764 {
5765         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5766         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5767         struct ixgbe_hw *hw =
5768                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5769         uint32_t q_idx;
5770         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5771
5772         /* Configure VF other cause ivar */
5773         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5774
5775         /* won't configure msix register if no mapping is done
5776          * between intr vector and event fd.
5777          */
5778         if (!rte_intr_dp_is_en(intr_handle))
5779                 return;
5780
5781         /* Configure all RX queues of VF */
5782         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5783                 /* Force all queue use vector 0,
5784                  * as IXGBE_VF_MAXMSIVECOTR = 1
5785                  */
5786                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5787                 intr_handle->intr_vec[q_idx] = vector_idx;
5788         }
5789 }
5790
5791 /**
5792  * Sets up the hardware to properly generate MSI-X interrupts
5793  * @hw
5794  *  board private structure
5795  */
5796 static void
5797 ixgbe_configure_msix(struct rte_eth_dev *dev)
5798 {
5799         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5800         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5801         struct ixgbe_hw *hw =
5802                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5803         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5804         uint32_t vec = IXGBE_MISC_VEC_ID;
5805         uint32_t mask;
5806         uint32_t gpie;
5807
5808         /* won't configure msix register if no mapping is done
5809          * between intr vector and event fd
5810          */
5811         if (!rte_intr_dp_is_en(intr_handle))
5812                 return;
5813
5814         if (rte_intr_allow_others(intr_handle))
5815                 vec = base = IXGBE_RX_VEC_START;
5816
5817         /* setup GPIE for MSI-x mode */
5818         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5819         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5820                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5821         /* auto clearing and auto setting corresponding bits in EIMS
5822          * when MSI-X interrupt is triggered
5823          */
5824         if (hw->mac.type == ixgbe_mac_82598EB) {
5825                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5826         } else {
5827                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5828                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5829         }
5830         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5831
5832         /* Populate the IVAR table and set the ITR values to the
5833          * corresponding register.
5834          */
5835         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5836              queue_id++) {
5837                 /* by default, 1:1 mapping */
5838                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5839                 intr_handle->intr_vec[queue_id] = vec;
5840                 if (vec < base + intr_handle->nb_efd - 1)
5841                         vec++;
5842         }
5843
5844         switch (hw->mac.type) {
5845         case ixgbe_mac_82598EB:
5846                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5847                                    IXGBE_MISC_VEC_ID);
5848                 break;
5849         case ixgbe_mac_82599EB:
5850         case ixgbe_mac_X540:
5851                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5852                 break;
5853         default:
5854                 break;
5855         }
5856         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5857                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5858
5859         /* set up to autoclear timer, and the vectors */
5860         mask = IXGBE_EIMS_ENABLE_MASK;
5861         mask &= ~(IXGBE_EIMS_OTHER |
5862                   IXGBE_EIMS_MAILBOX |
5863                   IXGBE_EIMS_LSC);
5864
5865         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5866 }
5867
5868 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5869         uint16_t queue_idx, uint16_t tx_rate)
5870 {
5871         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5872         uint32_t rf_dec, rf_int;
5873         uint32_t bcnrc_val;
5874         uint16_t link_speed = dev->data->dev_link.link_speed;
5875
5876         if (queue_idx >= hw->mac.max_tx_queues)
5877                 return -EINVAL;
5878
5879         if (tx_rate != 0) {
5880                 /* Calculate the rate factor values to set */
5881                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5882                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5883                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5884
5885                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5886                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5887                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5888                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5889         } else {
5890                 bcnrc_val = 0;
5891         }
5892
5893         /*
5894          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5895          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5896          * set as 0x4.
5897          */
5898         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5899                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5900                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5901                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5902                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5903         else
5904                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5905                         IXGBE_MMW_SIZE_DEFAULT);
5906
5907         /* Set RTTBCNRC of queue X */
5908         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5909         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5910         IXGBE_WRITE_FLUSH(hw);
5911
5912         return 0;
5913 }
5914
5915 static void
5916 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5917                      __attribute__((unused)) uint32_t index,
5918                      __attribute__((unused)) uint32_t pool)
5919 {
5920         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5921         int diag;
5922
5923         /*
5924          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5925          * operation. Trap this case to avoid exhausting the [very limited]
5926          * set of PF resources used to store VF MAC addresses.
5927          */
5928         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5929                 return;
5930         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5931         if (diag == 0)
5932                 return;
5933         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5934 }
5935
5936 static void
5937 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5938 {
5939         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5940         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5941         struct ether_addr *mac_addr;
5942         uint32_t i;
5943         int diag;
5944
5945         /*
5946          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5947          * not support the deletion of a given MAC address.
5948          * Instead, it imposes to delete all MAC addresses, then to add again
5949          * all MAC addresses with the exception of the one to be deleted.
5950          */
5951         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5952
5953         /*
5954          * Add again all MAC addresses, with the exception of the deleted one
5955          * and of the permanent MAC address.
5956          */
5957         for (i = 0, mac_addr = dev->data->mac_addrs;
5958              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5959                 /* Skip the deleted MAC address */
5960                 if (i == index)
5961                         continue;
5962                 /* Skip NULL MAC addresses */
5963                 if (is_zero_ether_addr(mac_addr))
5964                         continue;
5965                 /* Skip the permanent MAC address */
5966                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5967                         continue;
5968                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5969                 if (diag != 0)
5970                         PMD_DRV_LOG(ERR,
5971                                     "Adding again MAC address "
5972                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5973                                     "diag=%d",
5974                                     mac_addr->addr_bytes[0],
5975                                     mac_addr->addr_bytes[1],
5976                                     mac_addr->addr_bytes[2],
5977                                     mac_addr->addr_bytes[3],
5978                                     mac_addr->addr_bytes[4],
5979                                     mac_addr->addr_bytes[5],
5980                                     diag);
5981         }
5982 }
5983
5984 static void
5985 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5986 {
5987         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5988
5989         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5990 }
5991
5992 int
5993 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5994                         struct rte_eth_syn_filter *filter,
5995                         bool add)
5996 {
5997         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5998         struct ixgbe_filter_info *filter_info =
5999                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6000         uint32_t syn_info;
6001         uint32_t synqf;
6002
6003         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6004                 return -EINVAL;
6005
6006         syn_info = filter_info->syn_info;
6007
6008         if (add) {
6009                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6010                         return -EINVAL;
6011                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6012                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6013
6014                 if (filter->hig_pri)
6015                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6016                 else
6017                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6018         } else {
6019                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6020                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6021                         return -ENOENT;
6022                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6023         }
6024
6025         filter_info->syn_info = synqf;
6026         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6027         IXGBE_WRITE_FLUSH(hw);
6028         return 0;
6029 }
6030
6031 static int
6032 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6033                         struct rte_eth_syn_filter *filter)
6034 {
6035         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6036         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6037
6038         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6039                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6040                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6041                 return 0;
6042         }
6043         return -ENOENT;
6044 }
6045
6046 static int
6047 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6048                         enum rte_filter_op filter_op,
6049                         void *arg)
6050 {
6051         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6052         int ret;
6053
6054         MAC_TYPE_FILTER_SUP(hw->mac.type);
6055
6056         if (filter_op == RTE_ETH_FILTER_NOP)
6057                 return 0;
6058
6059         if (arg == NULL) {
6060                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6061                             filter_op);
6062                 return -EINVAL;
6063         }
6064
6065         switch (filter_op) {
6066         case RTE_ETH_FILTER_ADD:
6067                 ret = ixgbe_syn_filter_set(dev,
6068                                 (struct rte_eth_syn_filter *)arg,
6069                                 TRUE);
6070                 break;
6071         case RTE_ETH_FILTER_DELETE:
6072                 ret = ixgbe_syn_filter_set(dev,
6073                                 (struct rte_eth_syn_filter *)arg,
6074                                 FALSE);
6075                 break;
6076         case RTE_ETH_FILTER_GET:
6077                 ret = ixgbe_syn_filter_get(dev,
6078                                 (struct rte_eth_syn_filter *)arg);
6079                 break;
6080         default:
6081                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6082                 ret = -EINVAL;
6083                 break;
6084         }
6085
6086         return ret;
6087 }
6088
6089
6090 static inline enum ixgbe_5tuple_protocol
6091 convert_protocol_type(uint8_t protocol_value)
6092 {
6093         if (protocol_value == IPPROTO_TCP)
6094                 return IXGBE_FILTER_PROTOCOL_TCP;
6095         else if (protocol_value == IPPROTO_UDP)
6096                 return IXGBE_FILTER_PROTOCOL_UDP;
6097         else if (protocol_value == IPPROTO_SCTP)
6098                 return IXGBE_FILTER_PROTOCOL_SCTP;
6099         else
6100                 return IXGBE_FILTER_PROTOCOL_NONE;
6101 }
6102
6103 /* inject a 5-tuple filter to HW */
6104 static inline void
6105 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6106                            struct ixgbe_5tuple_filter *filter)
6107 {
6108         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6109         int i;
6110         uint32_t ftqf, sdpqf;
6111         uint32_t l34timir = 0;
6112         uint8_t mask = 0xff;
6113
6114         i = filter->index;
6115
6116         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6117                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6118         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6119
6120         ftqf = (uint32_t)(filter->filter_info.proto &
6121                 IXGBE_FTQF_PROTOCOL_MASK);
6122         ftqf |= (uint32_t)((filter->filter_info.priority &
6123                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6124         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6125                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6126         if (filter->filter_info.dst_ip_mask == 0)
6127                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6128         if (filter->filter_info.src_port_mask == 0)
6129                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6130         if (filter->filter_info.dst_port_mask == 0)
6131                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6132         if (filter->filter_info.proto_mask == 0)
6133                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6134         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6135         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6136         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6137
6138         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6139         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6140         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6141         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6142
6143         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6144         l34timir |= (uint32_t)(filter->queue <<
6145                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6146         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6147 }
6148
6149 /*
6150  * add a 5tuple filter
6151  *
6152  * @param
6153  * dev: Pointer to struct rte_eth_dev.
6154  * index: the index the filter allocates.
6155  * filter: ponter to the filter that will be added.
6156  * rx_queue: the queue id the filter assigned to.
6157  *
6158  * @return
6159  *    - On success, zero.
6160  *    - On failure, a negative value.
6161  */
6162 static int
6163 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6164                         struct ixgbe_5tuple_filter *filter)
6165 {
6166         struct ixgbe_filter_info *filter_info =
6167                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6168         int i, idx, shift;
6169
6170         /*
6171          * look for an unused 5tuple filter index,
6172          * and insert the filter to list.
6173          */
6174         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6175                 idx = i / (sizeof(uint32_t) * NBBY);
6176                 shift = i % (sizeof(uint32_t) * NBBY);
6177                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6178                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6179                         filter->index = i;
6180                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6181                                           filter,
6182                                           entries);
6183                         break;
6184                 }
6185         }
6186         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6187                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6188                 return -ENOSYS;
6189         }
6190
6191         ixgbe_inject_5tuple_filter(dev, filter);
6192
6193         return 0;
6194 }
6195
6196 /*
6197  * remove a 5tuple filter
6198  *
6199  * @param
6200  * dev: Pointer to struct rte_eth_dev.
6201  * filter: the pointer of the filter will be removed.
6202  */
6203 static void
6204 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6205                         struct ixgbe_5tuple_filter *filter)
6206 {
6207         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6208         struct ixgbe_filter_info *filter_info =
6209                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6210         uint16_t index = filter->index;
6211
6212         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6213                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6214         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6215         rte_free(filter);
6216
6217         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6218         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6219         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6220         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6221         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6222 }
6223
6224 static int
6225 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6226 {
6227         struct ixgbe_hw *hw;
6228         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6229
6230         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6231
6232         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6233                 return -EINVAL;
6234
6235         /* refuse mtu that requires the support of scattered packets when this
6236          * feature has not been enabled before.
6237          */
6238         if (!dev->data->scattered_rx &&
6239             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6240              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6241                 return -EINVAL;
6242
6243         /*
6244          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6245          * request of the version 2.0 of the mailbox API.
6246          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6247          * of the mailbox API.
6248          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6249          * prior to 3.11.33 which contains the following change:
6250          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6251          */
6252         ixgbevf_rlpml_set_vf(hw, max_frame);
6253
6254         /* update max frame size */
6255         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6256         return 0;
6257 }
6258
6259 static inline struct ixgbe_5tuple_filter *
6260 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6261                         struct ixgbe_5tuple_filter_info *key)
6262 {
6263         struct ixgbe_5tuple_filter *it;
6264
6265         TAILQ_FOREACH(it, filter_list, entries) {
6266                 if (memcmp(key, &it->filter_info,
6267                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6268                         return it;
6269                 }
6270         }
6271         return NULL;
6272 }
6273
6274 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6275 static inline int
6276 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6277                         struct ixgbe_5tuple_filter_info *filter_info)
6278 {
6279         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6280                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6281                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6282                 return -EINVAL;
6283
6284         switch (filter->dst_ip_mask) {
6285         case UINT32_MAX:
6286                 filter_info->dst_ip_mask = 0;
6287                 filter_info->dst_ip = filter->dst_ip;
6288                 break;
6289         case 0:
6290                 filter_info->dst_ip_mask = 1;
6291                 break;
6292         default:
6293                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6294                 return -EINVAL;
6295         }
6296
6297         switch (filter->src_ip_mask) {
6298         case UINT32_MAX:
6299                 filter_info->src_ip_mask = 0;
6300                 filter_info->src_ip = filter->src_ip;
6301                 break;
6302         case 0:
6303                 filter_info->src_ip_mask = 1;
6304                 break;
6305         default:
6306                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6307                 return -EINVAL;
6308         }
6309
6310         switch (filter->dst_port_mask) {
6311         case UINT16_MAX:
6312                 filter_info->dst_port_mask = 0;
6313                 filter_info->dst_port = filter->dst_port;
6314                 break;
6315         case 0:
6316                 filter_info->dst_port_mask = 1;
6317                 break;
6318         default:
6319                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6320                 return -EINVAL;
6321         }
6322
6323         switch (filter->src_port_mask) {
6324         case UINT16_MAX:
6325                 filter_info->src_port_mask = 0;
6326                 filter_info->src_port = filter->src_port;
6327                 break;
6328         case 0:
6329                 filter_info->src_port_mask = 1;
6330                 break;
6331         default:
6332                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6333                 return -EINVAL;
6334         }
6335
6336         switch (filter->proto_mask) {
6337         case UINT8_MAX:
6338                 filter_info->proto_mask = 0;
6339                 filter_info->proto =
6340                         convert_protocol_type(filter->proto);
6341                 break;
6342         case 0:
6343                 filter_info->proto_mask = 1;
6344                 break;
6345         default:
6346                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6347                 return -EINVAL;
6348         }
6349
6350         filter_info->priority = (uint8_t)filter->priority;
6351         return 0;
6352 }
6353
6354 /*
6355  * add or delete a ntuple filter
6356  *
6357  * @param
6358  * dev: Pointer to struct rte_eth_dev.
6359  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6360  * add: if true, add filter, if false, remove filter
6361  *
6362  * @return
6363  *    - On success, zero.
6364  *    - On failure, a negative value.
6365  */
6366 int
6367 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6368                         struct rte_eth_ntuple_filter *ntuple_filter,
6369                         bool add)
6370 {
6371         struct ixgbe_filter_info *filter_info =
6372                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6373         struct ixgbe_5tuple_filter_info filter_5tuple;
6374         struct ixgbe_5tuple_filter *filter;
6375         int ret;
6376
6377         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6378                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6379                 return -EINVAL;
6380         }
6381
6382         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6383         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6384         if (ret < 0)
6385                 return ret;
6386
6387         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6388                                          &filter_5tuple);
6389         if (filter != NULL && add) {
6390                 PMD_DRV_LOG(ERR, "filter exists.");
6391                 return -EEXIST;
6392         }
6393         if (filter == NULL && !add) {
6394                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6395                 return -ENOENT;
6396         }
6397
6398         if (add) {
6399                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6400                                 sizeof(struct ixgbe_5tuple_filter), 0);
6401                 if (filter == NULL)
6402                         return -ENOMEM;
6403                 (void)rte_memcpy(&filter->filter_info,
6404                                  &filter_5tuple,
6405                                  sizeof(struct ixgbe_5tuple_filter_info));
6406                 filter->queue = ntuple_filter->queue;
6407                 ret = ixgbe_add_5tuple_filter(dev, filter);
6408                 if (ret < 0) {
6409                         rte_free(filter);
6410                         return ret;
6411                 }
6412         } else
6413                 ixgbe_remove_5tuple_filter(dev, filter);
6414
6415         return 0;
6416 }
6417
6418 /*
6419  * get a ntuple filter
6420  *
6421  * @param
6422  * dev: Pointer to struct rte_eth_dev.
6423  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6424  *
6425  * @return
6426  *    - On success, zero.
6427  *    - On failure, a negative value.
6428  */
6429 static int
6430 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6431                         struct rte_eth_ntuple_filter *ntuple_filter)
6432 {
6433         struct ixgbe_filter_info *filter_info =
6434                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6435         struct ixgbe_5tuple_filter_info filter_5tuple;
6436         struct ixgbe_5tuple_filter *filter;
6437         int ret;
6438
6439         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6440                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6441                 return -EINVAL;
6442         }
6443
6444         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6445         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6446         if (ret < 0)
6447                 return ret;
6448
6449         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6450                                          &filter_5tuple);
6451         if (filter == NULL) {
6452                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6453                 return -ENOENT;
6454         }
6455         ntuple_filter->queue = filter->queue;
6456         return 0;
6457 }
6458
6459 /*
6460  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6461  * @dev: pointer to rte_eth_dev structure
6462  * @filter_op:operation will be taken.
6463  * @arg: a pointer to specific structure corresponding to the filter_op
6464  *
6465  * @return
6466  *    - On success, zero.
6467  *    - On failure, a negative value.
6468  */
6469 static int
6470 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6471                                 enum rte_filter_op filter_op,
6472                                 void *arg)
6473 {
6474         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6475         int ret;
6476
6477         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6478
6479         if (filter_op == RTE_ETH_FILTER_NOP)
6480                 return 0;
6481
6482         if (arg == NULL) {
6483                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6484                             filter_op);
6485                 return -EINVAL;
6486         }
6487
6488         switch (filter_op) {
6489         case RTE_ETH_FILTER_ADD:
6490                 ret = ixgbe_add_del_ntuple_filter(dev,
6491                         (struct rte_eth_ntuple_filter *)arg,
6492                         TRUE);
6493                 break;
6494         case RTE_ETH_FILTER_DELETE:
6495                 ret = ixgbe_add_del_ntuple_filter(dev,
6496                         (struct rte_eth_ntuple_filter *)arg,
6497                         FALSE);
6498                 break;
6499         case RTE_ETH_FILTER_GET:
6500                 ret = ixgbe_get_ntuple_filter(dev,
6501                         (struct rte_eth_ntuple_filter *)arg);
6502                 break;
6503         default:
6504                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6505                 ret = -EINVAL;
6506                 break;
6507         }
6508         return ret;
6509 }
6510
6511 int
6512 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6513                         struct rte_eth_ethertype_filter *filter,
6514                         bool add)
6515 {
6516         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6517         struct ixgbe_filter_info *filter_info =
6518                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6519         uint32_t etqf = 0;
6520         uint32_t etqs = 0;
6521         int ret;
6522         struct ixgbe_ethertype_filter ethertype_filter;
6523
6524         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6525                 return -EINVAL;
6526
6527         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6528                 filter->ether_type == ETHER_TYPE_IPv6) {
6529                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6530                         " ethertype filter.", filter->ether_type);
6531                 return -EINVAL;
6532         }
6533
6534         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6535                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6536                 return -EINVAL;
6537         }
6538         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6539                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6540                 return -EINVAL;
6541         }
6542
6543         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6544         if (ret >= 0 && add) {
6545                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6546                             filter->ether_type);
6547                 return -EEXIST;
6548         }
6549         if (ret < 0 && !add) {
6550                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6551                             filter->ether_type);
6552                 return -ENOENT;
6553         }
6554
6555         if (add) {
6556                 etqf = IXGBE_ETQF_FILTER_EN;
6557                 etqf |= (uint32_t)filter->ether_type;
6558                 etqs |= (uint32_t)((filter->queue <<
6559                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6560                                     IXGBE_ETQS_RX_QUEUE);
6561                 etqs |= IXGBE_ETQS_QUEUE_EN;
6562
6563                 ethertype_filter.ethertype = filter->ether_type;
6564                 ethertype_filter.etqf = etqf;
6565                 ethertype_filter.etqs = etqs;
6566                 ethertype_filter.conf = FALSE;
6567                 ret = ixgbe_ethertype_filter_insert(filter_info,
6568                                                     &ethertype_filter);
6569                 if (ret < 0) {
6570                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6571                         return -ENOSPC;
6572                 }
6573         } else {
6574                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6575                 if (ret < 0)
6576                         return -ENOSYS;
6577         }
6578         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6579         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6580         IXGBE_WRITE_FLUSH(hw);
6581
6582         return 0;
6583 }
6584
6585 static int
6586 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6587                         struct rte_eth_ethertype_filter *filter)
6588 {
6589         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6590         struct ixgbe_filter_info *filter_info =
6591                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6592         uint32_t etqf, etqs;
6593         int ret;
6594
6595         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6596         if (ret < 0) {
6597                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6598                             filter->ether_type);
6599                 return -ENOENT;
6600         }
6601
6602         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6603         if (etqf & IXGBE_ETQF_FILTER_EN) {
6604                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6605                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6606                 filter->flags = 0;
6607                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6608                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6609                 return 0;
6610         }
6611         return -ENOENT;
6612 }
6613
6614 /*
6615  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6616  * @dev: pointer to rte_eth_dev structure
6617  * @filter_op:operation will be taken.
6618  * @arg: a pointer to specific structure corresponding to the filter_op
6619  */
6620 static int
6621 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6622                                 enum rte_filter_op filter_op,
6623                                 void *arg)
6624 {
6625         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6626         int ret;
6627
6628         MAC_TYPE_FILTER_SUP(hw->mac.type);
6629
6630         if (filter_op == RTE_ETH_FILTER_NOP)
6631                 return 0;
6632
6633         if (arg == NULL) {
6634                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6635                             filter_op);
6636                 return -EINVAL;
6637         }
6638
6639         switch (filter_op) {
6640         case RTE_ETH_FILTER_ADD:
6641                 ret = ixgbe_add_del_ethertype_filter(dev,
6642                         (struct rte_eth_ethertype_filter *)arg,
6643                         TRUE);
6644                 break;
6645         case RTE_ETH_FILTER_DELETE:
6646                 ret = ixgbe_add_del_ethertype_filter(dev,
6647                         (struct rte_eth_ethertype_filter *)arg,
6648                         FALSE);
6649                 break;
6650         case RTE_ETH_FILTER_GET:
6651                 ret = ixgbe_get_ethertype_filter(dev,
6652                         (struct rte_eth_ethertype_filter *)arg);
6653                 break;
6654         default:
6655                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6656                 ret = -EINVAL;
6657                 break;
6658         }
6659         return ret;
6660 }
6661
6662 static int
6663 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6664                      enum rte_filter_type filter_type,
6665                      enum rte_filter_op filter_op,
6666                      void *arg)
6667 {
6668         int ret = 0;
6669
6670         switch (filter_type) {
6671         case RTE_ETH_FILTER_NTUPLE:
6672                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6673                 break;
6674         case RTE_ETH_FILTER_ETHERTYPE:
6675                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6676                 break;
6677         case RTE_ETH_FILTER_SYN:
6678                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6679                 break;
6680         case RTE_ETH_FILTER_FDIR:
6681                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6682                 break;
6683         case RTE_ETH_FILTER_L2_TUNNEL:
6684                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6685                 break;
6686         case RTE_ETH_FILTER_GENERIC:
6687                 if (filter_op != RTE_ETH_FILTER_GET)
6688                         return -EINVAL;
6689                 *(const void **)arg = &ixgbe_flow_ops;
6690                 break;
6691         default:
6692                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6693                                                         filter_type);
6694                 ret = -EINVAL;
6695                 break;
6696         }
6697
6698         return ret;
6699 }
6700
6701 static u8 *
6702 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6703                         u8 **mc_addr_ptr, u32 *vmdq)
6704 {
6705         u8 *mc_addr;
6706
6707         *vmdq = 0;
6708         mc_addr = *mc_addr_ptr;
6709         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6710         return mc_addr;
6711 }
6712
6713 static int
6714 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6715                           struct ether_addr *mc_addr_set,
6716                           uint32_t nb_mc_addr)
6717 {
6718         struct ixgbe_hw *hw;
6719         u8 *mc_addr_list;
6720
6721         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6722         mc_addr_list = (u8 *)mc_addr_set;
6723         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6724                                          ixgbe_dev_addr_list_itr, TRUE);
6725 }
6726
6727 static uint64_t
6728 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6729 {
6730         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6731         uint64_t systime_cycles;
6732
6733         switch (hw->mac.type) {
6734         case ixgbe_mac_X550:
6735         case ixgbe_mac_X550EM_x:
6736         case ixgbe_mac_X550EM_a:
6737                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6738                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6739                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6740                                 * NSEC_PER_SEC;
6741                 break;
6742         default:
6743                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6744                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6745                                 << 32;
6746         }
6747
6748         return systime_cycles;
6749 }
6750
6751 static uint64_t
6752 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6753 {
6754         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6755         uint64_t rx_tstamp_cycles;
6756
6757         switch (hw->mac.type) {
6758         case ixgbe_mac_X550:
6759         case ixgbe_mac_X550EM_x:
6760         case ixgbe_mac_X550EM_a:
6761                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6762                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6763                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6764                                 * NSEC_PER_SEC;
6765                 break;
6766         default:
6767                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6768                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6769                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6770                                 << 32;
6771         }
6772
6773         return rx_tstamp_cycles;
6774 }
6775
6776 static uint64_t
6777 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6778 {
6779         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6780         uint64_t tx_tstamp_cycles;
6781
6782         switch (hw->mac.type) {
6783         case ixgbe_mac_X550:
6784         case ixgbe_mac_X550EM_x:
6785         case ixgbe_mac_X550EM_a:
6786                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6787                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6788                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6789                                 * NSEC_PER_SEC;
6790                 break;
6791         default:
6792                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6793                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6794                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6795                                 << 32;
6796         }
6797
6798         return tx_tstamp_cycles;
6799 }
6800
6801 static void
6802 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6803 {
6804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6805         struct ixgbe_adapter *adapter =
6806                 (struct ixgbe_adapter *)dev->data->dev_private;
6807         struct rte_eth_link link;
6808         uint32_t incval = 0;
6809         uint32_t shift = 0;
6810
6811         /* Get current link speed. */
6812         memset(&link, 0, sizeof(link));
6813         ixgbe_dev_link_update(dev, 1);
6814         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6815
6816         switch (link.link_speed) {
6817         case ETH_SPEED_NUM_100M:
6818                 incval = IXGBE_INCVAL_100;
6819                 shift = IXGBE_INCVAL_SHIFT_100;
6820                 break;
6821         case ETH_SPEED_NUM_1G:
6822                 incval = IXGBE_INCVAL_1GB;
6823                 shift = IXGBE_INCVAL_SHIFT_1GB;
6824                 break;
6825         case ETH_SPEED_NUM_10G:
6826         default:
6827                 incval = IXGBE_INCVAL_10GB;
6828                 shift = IXGBE_INCVAL_SHIFT_10GB;
6829                 break;
6830         }
6831
6832         switch (hw->mac.type) {
6833         case ixgbe_mac_X550:
6834         case ixgbe_mac_X550EM_x:
6835         case ixgbe_mac_X550EM_a:
6836                 /* Independent of link speed. */
6837                 incval = 1;
6838                 /* Cycles read will be interpreted as ns. */
6839                 shift = 0;
6840                 /* Fall-through */
6841         case ixgbe_mac_X540:
6842                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6843                 break;
6844         case ixgbe_mac_82599EB:
6845                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6846                 shift -= IXGBE_INCVAL_SHIFT_82599;
6847                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6848                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6849                 break;
6850         default:
6851                 /* Not supported. */
6852                 return;
6853         }
6854
6855         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6856         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6857         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6858
6859         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6860         adapter->systime_tc.cc_shift = shift;
6861         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6862
6863         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6864         adapter->rx_tstamp_tc.cc_shift = shift;
6865         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6866
6867         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6868         adapter->tx_tstamp_tc.cc_shift = shift;
6869         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6870 }
6871
6872 static int
6873 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6874 {
6875         struct ixgbe_adapter *adapter =
6876                         (struct ixgbe_adapter *)dev->data->dev_private;
6877
6878         adapter->systime_tc.nsec += delta;
6879         adapter->rx_tstamp_tc.nsec += delta;
6880         adapter->tx_tstamp_tc.nsec += delta;
6881
6882         return 0;
6883 }
6884
6885 static int
6886 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6887 {
6888         uint64_t ns;
6889         struct ixgbe_adapter *adapter =
6890                         (struct ixgbe_adapter *)dev->data->dev_private;
6891
6892         ns = rte_timespec_to_ns(ts);
6893         /* Set the timecounters to a new value. */
6894         adapter->systime_tc.nsec = ns;
6895         adapter->rx_tstamp_tc.nsec = ns;
6896         adapter->tx_tstamp_tc.nsec = ns;
6897
6898         return 0;
6899 }
6900
6901 static int
6902 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6903 {
6904         uint64_t ns, systime_cycles;
6905         struct ixgbe_adapter *adapter =
6906                         (struct ixgbe_adapter *)dev->data->dev_private;
6907
6908         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6909         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6910         *ts = rte_ns_to_timespec(ns);
6911
6912         return 0;
6913 }
6914
6915 static int
6916 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6917 {
6918         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6919         uint32_t tsync_ctl;
6920         uint32_t tsauxc;
6921
6922         /* Stop the timesync system time. */
6923         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6924         /* Reset the timesync system time value. */
6925         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6926         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6927
6928         /* Enable system time for platforms where it isn't on by default. */
6929         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6930         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6931         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6932
6933         ixgbe_start_timecounters(dev);
6934
6935         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6936         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6937                         (ETHER_TYPE_1588 |
6938                          IXGBE_ETQF_FILTER_EN |
6939                          IXGBE_ETQF_1588));
6940
6941         /* Enable timestamping of received PTP packets. */
6942         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6943         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6944         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6945
6946         /* Enable timestamping of transmitted PTP packets. */
6947         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6948         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6949         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6950
6951         IXGBE_WRITE_FLUSH(hw);
6952
6953         return 0;
6954 }
6955
6956 static int
6957 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6958 {
6959         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6960         uint32_t tsync_ctl;
6961
6962         /* Disable timestamping of transmitted PTP packets. */
6963         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6964         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6965         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6966
6967         /* Disable timestamping of received PTP packets. */
6968         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6969         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6970         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6971
6972         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6973         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6974
6975         /* Stop incrementating the System Time registers. */
6976         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6977
6978         return 0;
6979 }
6980
6981 static int
6982 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6983                                  struct timespec *timestamp,
6984                                  uint32_t flags __rte_unused)
6985 {
6986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6987         struct ixgbe_adapter *adapter =
6988                 (struct ixgbe_adapter *)dev->data->dev_private;
6989         uint32_t tsync_rxctl;
6990         uint64_t rx_tstamp_cycles;
6991         uint64_t ns;
6992
6993         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6994         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6995                 return -EINVAL;
6996
6997         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6998         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6999         *timestamp = rte_ns_to_timespec(ns);
7000
7001         return  0;
7002 }
7003
7004 static int
7005 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7006                                  struct timespec *timestamp)
7007 {
7008         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7009         struct ixgbe_adapter *adapter =
7010                 (struct ixgbe_adapter *)dev->data->dev_private;
7011         uint32_t tsync_txctl;
7012         uint64_t tx_tstamp_cycles;
7013         uint64_t ns;
7014
7015         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7016         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7017                 return -EINVAL;
7018
7019         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7020         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7021         *timestamp = rte_ns_to_timespec(ns);
7022
7023         return 0;
7024 }
7025
7026 static int
7027 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7028 {
7029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7030         int count = 0;
7031         int g_ind = 0;
7032         const struct reg_info *reg_group;
7033         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7034                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7035
7036         while ((reg_group = reg_set[g_ind++]))
7037                 count += ixgbe_regs_group_count(reg_group);
7038
7039         return count;
7040 }
7041
7042 static int
7043 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7044 {
7045         int count = 0;
7046         int g_ind = 0;
7047         const struct reg_info *reg_group;
7048
7049         while ((reg_group = ixgbevf_regs[g_ind++]))
7050                 count += ixgbe_regs_group_count(reg_group);
7051
7052         return count;
7053 }
7054
7055 static int
7056 ixgbe_get_regs(struct rte_eth_dev *dev,
7057               struct rte_dev_reg_info *regs)
7058 {
7059         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7060         uint32_t *data = regs->data;
7061         int g_ind = 0;
7062         int count = 0;
7063         const struct reg_info *reg_group;
7064         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7065                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7066
7067         if (data == NULL) {
7068                 regs->length = ixgbe_get_reg_length(dev);
7069                 regs->width = sizeof(uint32_t);
7070                 return 0;
7071         }
7072
7073         /* Support only full register dump */
7074         if ((regs->length == 0) ||
7075             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7076                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7077                         hw->device_id;
7078                 while ((reg_group = reg_set[g_ind++]))
7079                         count += ixgbe_read_regs_group(dev, &data[count],
7080                                 reg_group);
7081                 return 0;
7082         }
7083
7084         return -ENOTSUP;
7085 }
7086
7087 static int
7088 ixgbevf_get_regs(struct rte_eth_dev *dev,
7089                 struct rte_dev_reg_info *regs)
7090 {
7091         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7092         uint32_t *data = regs->data;
7093         int g_ind = 0;
7094         int count = 0;
7095         const struct reg_info *reg_group;
7096
7097         if (data == NULL) {
7098                 regs->length = ixgbevf_get_reg_length(dev);
7099                 regs->width = sizeof(uint32_t);
7100                 return 0;
7101         }
7102
7103         /* Support only full register dump */
7104         if ((regs->length == 0) ||
7105             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7106                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7107                         hw->device_id;
7108                 while ((reg_group = ixgbevf_regs[g_ind++]))
7109                         count += ixgbe_read_regs_group(dev, &data[count],
7110                                                       reg_group);
7111                 return 0;
7112         }
7113
7114         return -ENOTSUP;
7115 }
7116
7117 static int
7118 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7119 {
7120         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7121
7122         /* Return unit is byte count */
7123         return hw->eeprom.word_size * 2;
7124 }
7125
7126 static int
7127 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7128                 struct rte_dev_eeprom_info *in_eeprom)
7129 {
7130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7131         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7132         uint16_t *data = in_eeprom->data;
7133         int first, length;
7134
7135         first = in_eeprom->offset >> 1;
7136         length = in_eeprom->length >> 1;
7137         if ((first > hw->eeprom.word_size) ||
7138             ((first + length) > hw->eeprom.word_size))
7139                 return -EINVAL;
7140
7141         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7142
7143         return eeprom->ops.read_buffer(hw, first, length, data);
7144 }
7145
7146 static int
7147 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7148                 struct rte_dev_eeprom_info *in_eeprom)
7149 {
7150         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7151         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7152         uint16_t *data = in_eeprom->data;
7153         int first, length;
7154
7155         first = in_eeprom->offset >> 1;
7156         length = in_eeprom->length >> 1;
7157         if ((first > hw->eeprom.word_size) ||
7158             ((first + length) > hw->eeprom.word_size))
7159                 return -EINVAL;
7160
7161         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7162
7163         return eeprom->ops.write_buffer(hw,  first, length, data);
7164 }
7165
7166 uint16_t
7167 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7168         switch (mac_type) {
7169         case ixgbe_mac_X550:
7170         case ixgbe_mac_X550EM_x:
7171         case ixgbe_mac_X550EM_a:
7172                 return ETH_RSS_RETA_SIZE_512;
7173         case ixgbe_mac_X550_vf:
7174         case ixgbe_mac_X550EM_x_vf:
7175         case ixgbe_mac_X550EM_a_vf:
7176                 return ETH_RSS_RETA_SIZE_64;
7177         default:
7178                 return ETH_RSS_RETA_SIZE_128;
7179         }
7180 }
7181
7182 uint32_t
7183 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7184         switch (mac_type) {
7185         case ixgbe_mac_X550:
7186         case ixgbe_mac_X550EM_x:
7187         case ixgbe_mac_X550EM_a:
7188                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7189                         return IXGBE_RETA(reta_idx >> 2);
7190                 else
7191                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7192         case ixgbe_mac_X550_vf:
7193         case ixgbe_mac_X550EM_x_vf:
7194         case ixgbe_mac_X550EM_a_vf:
7195                 return IXGBE_VFRETA(reta_idx >> 2);
7196         default:
7197                 return IXGBE_RETA(reta_idx >> 2);
7198         }
7199 }
7200
7201 uint32_t
7202 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7203         switch (mac_type) {
7204         case ixgbe_mac_X550_vf:
7205         case ixgbe_mac_X550EM_x_vf:
7206         case ixgbe_mac_X550EM_a_vf:
7207                 return IXGBE_VFMRQC;
7208         default:
7209                 return IXGBE_MRQC;
7210         }
7211 }
7212
7213 uint32_t
7214 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7215         switch (mac_type) {
7216         case ixgbe_mac_X550_vf:
7217         case ixgbe_mac_X550EM_x_vf:
7218         case ixgbe_mac_X550EM_a_vf:
7219                 return IXGBE_VFRSSRK(i);
7220         default:
7221                 return IXGBE_RSSRK(i);
7222         }
7223 }
7224
7225 bool
7226 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7227         switch (mac_type) {
7228         case ixgbe_mac_82599_vf:
7229         case ixgbe_mac_X540_vf:
7230                 return 0;
7231         default:
7232                 return 1;
7233         }
7234 }
7235
7236 static int
7237 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7238                         struct rte_eth_dcb_info *dcb_info)
7239 {
7240         struct ixgbe_dcb_config *dcb_config =
7241                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7242         struct ixgbe_dcb_tc_config *tc;
7243         uint8_t i, j;
7244
7245         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7246                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7247         else
7248                 dcb_info->nb_tcs = 1;
7249
7250         if (dcb_config->vt_mode) { /* vt is enabled*/
7251                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7252                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7253                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7254                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7255                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7256                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7257                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7258                                                 i * dcb_info->nb_tcs + j;
7259                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7260                                 dcb_info->tc_queue.tc_txq[i][j].base =
7261                                                 i * dcb_info->nb_tcs + j;
7262                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7263                         }
7264                 }
7265         } else { /* vt is disabled*/
7266                 struct rte_eth_dcb_rx_conf *rx_conf =
7267                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7268                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7269                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7270                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7271                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7272                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7273                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7274                         }
7275                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7276                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7277                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7278                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7279                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7280                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7281                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7282                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7283                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7284                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7285                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7286                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7287                         }
7288                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7289                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7290                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7291                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7292                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7293                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7294                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7295                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7296                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7297                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7298                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7299                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7300                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7301                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7302                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7303                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7304                 }
7305         }
7306         for (i = 0; i < dcb_info->nb_tcs; i++) {
7307                 tc = &dcb_config->tc_config[i];
7308                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7309         }
7310         return 0;
7311 }
7312
7313 /* Update e-tag ether type */
7314 static int
7315 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7316                             uint16_t ether_type)
7317 {
7318         uint32_t etag_etype;
7319
7320         if (hw->mac.type != ixgbe_mac_X550 &&
7321             hw->mac.type != ixgbe_mac_X550EM_x &&
7322             hw->mac.type != ixgbe_mac_X550EM_a) {
7323                 return -ENOTSUP;
7324         }
7325
7326         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7327         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7328         etag_etype |= ether_type;
7329         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7330         IXGBE_WRITE_FLUSH(hw);
7331
7332         return 0;
7333 }
7334
7335 /* Config l2 tunnel ether type */
7336 static int
7337 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7338                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7339 {
7340         int ret = 0;
7341         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7342         struct ixgbe_l2_tn_info *l2_tn_info =
7343                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7344
7345         if (l2_tunnel == NULL)
7346                 return -EINVAL;
7347
7348         switch (l2_tunnel->l2_tunnel_type) {
7349         case RTE_L2_TUNNEL_TYPE_E_TAG:
7350                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7351                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7352                 break;
7353         default:
7354                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7355                 ret = -EINVAL;
7356                 break;
7357         }
7358
7359         return ret;
7360 }
7361
7362 /* Enable e-tag tunnel */
7363 static int
7364 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7365 {
7366         uint32_t etag_etype;
7367
7368         if (hw->mac.type != ixgbe_mac_X550 &&
7369             hw->mac.type != ixgbe_mac_X550EM_x &&
7370             hw->mac.type != ixgbe_mac_X550EM_a) {
7371                 return -ENOTSUP;
7372         }
7373
7374         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7375         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7376         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7377         IXGBE_WRITE_FLUSH(hw);
7378
7379         return 0;
7380 }
7381
7382 /* Enable l2 tunnel */
7383 static int
7384 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7385                            enum rte_eth_tunnel_type l2_tunnel_type)
7386 {
7387         int ret = 0;
7388         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7389         struct ixgbe_l2_tn_info *l2_tn_info =
7390                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7391
7392         switch (l2_tunnel_type) {
7393         case RTE_L2_TUNNEL_TYPE_E_TAG:
7394                 l2_tn_info->e_tag_en = TRUE;
7395                 ret = ixgbe_e_tag_enable(hw);
7396                 break;
7397         default:
7398                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7399                 ret = -EINVAL;
7400                 break;
7401         }
7402
7403         return ret;
7404 }
7405
7406 /* Disable e-tag tunnel */
7407 static int
7408 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7409 {
7410         uint32_t etag_etype;
7411
7412         if (hw->mac.type != ixgbe_mac_X550 &&
7413             hw->mac.type != ixgbe_mac_X550EM_x &&
7414             hw->mac.type != ixgbe_mac_X550EM_a) {
7415                 return -ENOTSUP;
7416         }
7417
7418         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7419         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7420         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7421         IXGBE_WRITE_FLUSH(hw);
7422
7423         return 0;
7424 }
7425
7426 /* Disable l2 tunnel */
7427 static int
7428 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7429                             enum rte_eth_tunnel_type l2_tunnel_type)
7430 {
7431         int ret = 0;
7432         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7433         struct ixgbe_l2_tn_info *l2_tn_info =
7434                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7435
7436         switch (l2_tunnel_type) {
7437         case RTE_L2_TUNNEL_TYPE_E_TAG:
7438                 l2_tn_info->e_tag_en = FALSE;
7439                 ret = ixgbe_e_tag_disable(hw);
7440                 break;
7441         default:
7442                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7443                 ret = -EINVAL;
7444                 break;
7445         }
7446
7447         return ret;
7448 }
7449
7450 static int
7451 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7452                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7453 {
7454         int ret = 0;
7455         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7456         uint32_t i, rar_entries;
7457         uint32_t rar_low, rar_high;
7458
7459         if (hw->mac.type != ixgbe_mac_X550 &&
7460             hw->mac.type != ixgbe_mac_X550EM_x &&
7461             hw->mac.type != ixgbe_mac_X550EM_a) {
7462                 return -ENOTSUP;
7463         }
7464
7465         rar_entries = ixgbe_get_num_rx_addrs(hw);
7466
7467         for (i = 1; i < rar_entries; i++) {
7468                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7469                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7470                 if ((rar_high & IXGBE_RAH_AV) &&
7471                     (rar_high & IXGBE_RAH_ADTYPE) &&
7472                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7473                      l2_tunnel->tunnel_id)) {
7474                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7475                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7476
7477                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7478
7479                         return ret;
7480                 }
7481         }
7482
7483         return ret;
7484 }
7485
7486 static int
7487 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7488                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7489 {
7490         int ret = 0;
7491         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7492         uint32_t i, rar_entries;
7493         uint32_t rar_low, rar_high;
7494
7495         if (hw->mac.type != ixgbe_mac_X550 &&
7496             hw->mac.type != ixgbe_mac_X550EM_x &&
7497             hw->mac.type != ixgbe_mac_X550EM_a) {
7498                 return -ENOTSUP;
7499         }
7500
7501         /* One entry for one tunnel. Try to remove potential existing entry. */
7502         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7503
7504         rar_entries = ixgbe_get_num_rx_addrs(hw);
7505
7506         for (i = 1; i < rar_entries; i++) {
7507                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7508                 if (rar_high & IXGBE_RAH_AV) {
7509                         continue;
7510                 } else {
7511                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7512                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7513                         rar_low = l2_tunnel->tunnel_id;
7514
7515                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7516                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7517
7518                         return ret;
7519                 }
7520         }
7521
7522         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7523                      " Please remove a rule before adding a new one.");
7524         return -EINVAL;
7525 }
7526
7527 static inline struct ixgbe_l2_tn_filter *
7528 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7529                           struct ixgbe_l2_tn_key *key)
7530 {
7531         int ret;
7532
7533         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7534         if (ret < 0)
7535                 return NULL;
7536
7537         return l2_tn_info->hash_map[ret];
7538 }
7539
7540 static inline int
7541 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7542                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7543 {
7544         int ret;
7545
7546         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7547                                &l2_tn_filter->key);
7548
7549         if (ret < 0) {
7550                 PMD_DRV_LOG(ERR,
7551                             "Failed to insert L2 tunnel filter"
7552                             " to hash table %d!",
7553                             ret);
7554                 return ret;
7555         }
7556
7557         l2_tn_info->hash_map[ret] = l2_tn_filter;
7558
7559         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7560
7561         return 0;
7562 }
7563
7564 static inline int
7565 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7566                           struct ixgbe_l2_tn_key *key)
7567 {
7568         int ret;
7569         struct ixgbe_l2_tn_filter *l2_tn_filter;
7570
7571         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7572
7573         if (ret < 0) {
7574                 PMD_DRV_LOG(ERR,
7575                             "No such L2 tunnel filter to delete %d!",
7576                             ret);
7577                 return ret;
7578         }
7579
7580         l2_tn_filter = l2_tn_info->hash_map[ret];
7581         l2_tn_info->hash_map[ret] = NULL;
7582
7583         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7584         rte_free(l2_tn_filter);
7585
7586         return 0;
7587 }
7588
7589 /* Add l2 tunnel filter */
7590 int
7591 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7592                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7593                                bool restore)
7594 {
7595         int ret;
7596         struct ixgbe_l2_tn_info *l2_tn_info =
7597                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7598         struct ixgbe_l2_tn_key key;
7599         struct ixgbe_l2_tn_filter *node;
7600
7601         if (!restore) {
7602                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7603                 key.tn_id = l2_tunnel->tunnel_id;
7604
7605                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7606
7607                 if (node) {
7608                         PMD_DRV_LOG(ERR,
7609                                     "The L2 tunnel filter already exists!");
7610                         return -EINVAL;
7611                 }
7612
7613                 node = rte_zmalloc("ixgbe_l2_tn",
7614                                    sizeof(struct ixgbe_l2_tn_filter),
7615                                    0);
7616                 if (!node)
7617                         return -ENOMEM;
7618
7619                 (void)rte_memcpy(&node->key,
7620                                  &key,
7621                                  sizeof(struct ixgbe_l2_tn_key));
7622                 node->pool = l2_tunnel->pool;
7623                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7624                 if (ret < 0) {
7625                         rte_free(node);
7626                         return ret;
7627                 }
7628         }
7629
7630         switch (l2_tunnel->l2_tunnel_type) {
7631         case RTE_L2_TUNNEL_TYPE_E_TAG:
7632                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7633                 break;
7634         default:
7635                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7636                 ret = -EINVAL;
7637                 break;
7638         }
7639
7640         if ((!restore) && (ret < 0))
7641                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7642
7643         return ret;
7644 }
7645
7646 /* Delete l2 tunnel filter */
7647 int
7648 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7649                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7650 {
7651         int ret;
7652         struct ixgbe_l2_tn_info *l2_tn_info =
7653                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7654         struct ixgbe_l2_tn_key key;
7655
7656         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7657         key.tn_id = l2_tunnel->tunnel_id;
7658         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7659         if (ret < 0)
7660                 return ret;
7661
7662         switch (l2_tunnel->l2_tunnel_type) {
7663         case RTE_L2_TUNNEL_TYPE_E_TAG:
7664                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7665                 break;
7666         default:
7667                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7668                 ret = -EINVAL;
7669                 break;
7670         }
7671
7672         return ret;
7673 }
7674
7675 /**
7676  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7677  * @dev: pointer to rte_eth_dev structure
7678  * @filter_op:operation will be taken.
7679  * @arg: a pointer to specific structure corresponding to the filter_op
7680  */
7681 static int
7682 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7683                                   enum rte_filter_op filter_op,
7684                                   void *arg)
7685 {
7686         int ret;
7687
7688         if (filter_op == RTE_ETH_FILTER_NOP)
7689                 return 0;
7690
7691         if (arg == NULL) {
7692                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7693                             filter_op);
7694                 return -EINVAL;
7695         }
7696
7697         switch (filter_op) {
7698         case RTE_ETH_FILTER_ADD:
7699                 ret = ixgbe_dev_l2_tunnel_filter_add
7700                         (dev,
7701                          (struct rte_eth_l2_tunnel_conf *)arg,
7702                          FALSE);
7703                 break;
7704         case RTE_ETH_FILTER_DELETE:
7705                 ret = ixgbe_dev_l2_tunnel_filter_del
7706                         (dev,
7707                          (struct rte_eth_l2_tunnel_conf *)arg);
7708                 break;
7709         default:
7710                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7711                 ret = -EINVAL;
7712                 break;
7713         }
7714         return ret;
7715 }
7716
7717 static int
7718 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7719 {
7720         int ret = 0;
7721         uint32_t ctrl;
7722         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7723
7724         if (hw->mac.type != ixgbe_mac_X550 &&
7725             hw->mac.type != ixgbe_mac_X550EM_x &&
7726             hw->mac.type != ixgbe_mac_X550EM_a) {
7727                 return -ENOTSUP;
7728         }
7729
7730         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7731         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7732         if (en)
7733                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7734         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7735
7736         return ret;
7737 }
7738
7739 /* Enable l2 tunnel forwarding */
7740 static int
7741 ixgbe_dev_l2_tunnel_forwarding_enable
7742         (struct rte_eth_dev *dev,
7743          enum rte_eth_tunnel_type l2_tunnel_type)
7744 {
7745         struct ixgbe_l2_tn_info *l2_tn_info =
7746                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7747         int ret = 0;
7748
7749         switch (l2_tunnel_type) {
7750         case RTE_L2_TUNNEL_TYPE_E_TAG:
7751                 l2_tn_info->e_tag_fwd_en = TRUE;
7752                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7753                 break;
7754         default:
7755                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7756                 ret = -EINVAL;
7757                 break;
7758         }
7759
7760         return ret;
7761 }
7762
7763 /* Disable l2 tunnel forwarding */
7764 static int
7765 ixgbe_dev_l2_tunnel_forwarding_disable
7766         (struct rte_eth_dev *dev,
7767          enum rte_eth_tunnel_type l2_tunnel_type)
7768 {
7769         struct ixgbe_l2_tn_info *l2_tn_info =
7770                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7771         int ret = 0;
7772
7773         switch (l2_tunnel_type) {
7774         case RTE_L2_TUNNEL_TYPE_E_TAG:
7775                 l2_tn_info->e_tag_fwd_en = FALSE;
7776                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7777                 break;
7778         default:
7779                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7780                 ret = -EINVAL;
7781                 break;
7782         }
7783
7784         return ret;
7785 }
7786
7787 static int
7788 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7789                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7790                              bool en)
7791 {
7792         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7793         int ret = 0;
7794         uint32_t vmtir, vmvir;
7795         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7796
7797         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7798                 PMD_DRV_LOG(ERR,
7799                             "VF id %u should be less than %u",
7800                             l2_tunnel->vf_id,
7801                             pci_dev->max_vfs);
7802                 return -EINVAL;
7803         }
7804
7805         if (hw->mac.type != ixgbe_mac_X550 &&
7806             hw->mac.type != ixgbe_mac_X550EM_x &&
7807             hw->mac.type != ixgbe_mac_X550EM_a) {
7808                 return -ENOTSUP;
7809         }
7810
7811         if (en)
7812                 vmtir = l2_tunnel->tunnel_id;
7813         else
7814                 vmtir = 0;
7815
7816         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7817
7818         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7819         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7820         if (en)
7821                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7822         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7823
7824         return ret;
7825 }
7826
7827 /* Enable l2 tunnel tag insertion */
7828 static int
7829 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7830                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7831 {
7832         int ret = 0;
7833
7834         switch (l2_tunnel->l2_tunnel_type) {
7835         case RTE_L2_TUNNEL_TYPE_E_TAG:
7836                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7837                 break;
7838         default:
7839                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7840                 ret = -EINVAL;
7841                 break;
7842         }
7843
7844         return ret;
7845 }
7846
7847 /* Disable l2 tunnel tag insertion */
7848 static int
7849 ixgbe_dev_l2_tunnel_insertion_disable
7850         (struct rte_eth_dev *dev,
7851          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7852 {
7853         int ret = 0;
7854
7855         switch (l2_tunnel->l2_tunnel_type) {
7856         case RTE_L2_TUNNEL_TYPE_E_TAG:
7857                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7858                 break;
7859         default:
7860                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7861                 ret = -EINVAL;
7862                 break;
7863         }
7864
7865         return ret;
7866 }
7867
7868 static int
7869 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7870                              bool en)
7871 {
7872         int ret = 0;
7873         uint32_t qde;
7874         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7875
7876         if (hw->mac.type != ixgbe_mac_X550 &&
7877             hw->mac.type != ixgbe_mac_X550EM_x &&
7878             hw->mac.type != ixgbe_mac_X550EM_a) {
7879                 return -ENOTSUP;
7880         }
7881
7882         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7883         if (en)
7884                 qde |= IXGBE_QDE_STRIP_TAG;
7885         else
7886                 qde &= ~IXGBE_QDE_STRIP_TAG;
7887         qde &= ~IXGBE_QDE_READ;
7888         qde |= IXGBE_QDE_WRITE;
7889         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7890
7891         return ret;
7892 }
7893
7894 /* Enable l2 tunnel tag stripping */
7895 static int
7896 ixgbe_dev_l2_tunnel_stripping_enable
7897         (struct rte_eth_dev *dev,
7898          enum rte_eth_tunnel_type l2_tunnel_type)
7899 {
7900         int ret = 0;
7901
7902         switch (l2_tunnel_type) {
7903         case RTE_L2_TUNNEL_TYPE_E_TAG:
7904                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7905                 break;
7906         default:
7907                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7908                 ret = -EINVAL;
7909                 break;
7910         }
7911
7912         return ret;
7913 }
7914
7915 /* Disable l2 tunnel tag stripping */
7916 static int
7917 ixgbe_dev_l2_tunnel_stripping_disable
7918         (struct rte_eth_dev *dev,
7919          enum rte_eth_tunnel_type l2_tunnel_type)
7920 {
7921         int ret = 0;
7922
7923         switch (l2_tunnel_type) {
7924         case RTE_L2_TUNNEL_TYPE_E_TAG:
7925                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7926                 break;
7927         default:
7928                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7929                 ret = -EINVAL;
7930                 break;
7931         }
7932
7933         return ret;
7934 }
7935
7936 /* Enable/disable l2 tunnel offload functions */
7937 static int
7938 ixgbe_dev_l2_tunnel_offload_set
7939         (struct rte_eth_dev *dev,
7940          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7941          uint32_t mask,
7942          uint8_t en)
7943 {
7944         int ret = 0;
7945
7946         if (l2_tunnel == NULL)
7947                 return -EINVAL;
7948
7949         ret = -EINVAL;
7950         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7951                 if (en)
7952                         ret = ixgbe_dev_l2_tunnel_enable(
7953                                 dev,
7954                                 l2_tunnel->l2_tunnel_type);
7955                 else
7956                         ret = ixgbe_dev_l2_tunnel_disable(
7957                                 dev,
7958                                 l2_tunnel->l2_tunnel_type);
7959         }
7960
7961         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7962                 if (en)
7963                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7964                                 dev,
7965                                 l2_tunnel);
7966                 else
7967                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7968                                 dev,
7969                                 l2_tunnel);
7970         }
7971
7972         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7973                 if (en)
7974                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7975                                 dev,
7976                                 l2_tunnel->l2_tunnel_type);
7977                 else
7978                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7979                                 dev,
7980                                 l2_tunnel->l2_tunnel_type);
7981         }
7982
7983         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7984                 if (en)
7985                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7986                                 dev,
7987                                 l2_tunnel->l2_tunnel_type);
7988                 else
7989                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7990                                 dev,
7991                                 l2_tunnel->l2_tunnel_type);
7992         }
7993
7994         return ret;
7995 }
7996
7997 static int
7998 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7999                         uint16_t port)
8000 {
8001         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8002         IXGBE_WRITE_FLUSH(hw);
8003
8004         return 0;
8005 }
8006
8007 /* There's only one register for VxLAN UDP port.
8008  * So, we cannot add several ports. Will update it.
8009  */
8010 static int
8011 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8012                      uint16_t port)
8013 {
8014         if (port == 0) {
8015                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8016                 return -EINVAL;
8017         }
8018
8019         return ixgbe_update_vxlan_port(hw, port);
8020 }
8021
8022 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8023  * UDP port, it must have a value.
8024  * So, will reset it to the original value 0.
8025  */
8026 static int
8027 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8028                      uint16_t port)
8029 {
8030         uint16_t cur_port;
8031
8032         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8033
8034         if (cur_port != port) {
8035                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8036                 return -EINVAL;
8037         }
8038
8039         return ixgbe_update_vxlan_port(hw, 0);
8040 }
8041
8042 /* Add UDP tunneling port */
8043 static int
8044 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8045                               struct rte_eth_udp_tunnel *udp_tunnel)
8046 {
8047         int ret = 0;
8048         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8049
8050         if (hw->mac.type != ixgbe_mac_X550 &&
8051             hw->mac.type != ixgbe_mac_X550EM_x &&
8052             hw->mac.type != ixgbe_mac_X550EM_a) {
8053                 return -ENOTSUP;
8054         }
8055
8056         if (udp_tunnel == NULL)
8057                 return -EINVAL;
8058
8059         switch (udp_tunnel->prot_type) {
8060         case RTE_TUNNEL_TYPE_VXLAN:
8061                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8062                 break;
8063
8064         case RTE_TUNNEL_TYPE_GENEVE:
8065         case RTE_TUNNEL_TYPE_TEREDO:
8066                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8067                 ret = -EINVAL;
8068                 break;
8069
8070         default:
8071                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8072                 ret = -EINVAL;
8073                 break;
8074         }
8075
8076         return ret;
8077 }
8078
8079 /* Remove UDP tunneling port */
8080 static int
8081 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8082                               struct rte_eth_udp_tunnel *udp_tunnel)
8083 {
8084         int ret = 0;
8085         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8086
8087         if (hw->mac.type != ixgbe_mac_X550 &&
8088             hw->mac.type != ixgbe_mac_X550EM_x &&
8089             hw->mac.type != ixgbe_mac_X550EM_a) {
8090                 return -ENOTSUP;
8091         }
8092
8093         if (udp_tunnel == NULL)
8094                 return -EINVAL;
8095
8096         switch (udp_tunnel->prot_type) {
8097         case RTE_TUNNEL_TYPE_VXLAN:
8098                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8099                 break;
8100         case RTE_TUNNEL_TYPE_GENEVE:
8101         case RTE_TUNNEL_TYPE_TEREDO:
8102                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8103                 ret = -EINVAL;
8104                 break;
8105         default:
8106                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8107                 ret = -EINVAL;
8108                 break;
8109         }
8110
8111         return ret;
8112 }
8113
8114 static void
8115 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8116 {
8117         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8118
8119         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8120 }
8121
8122 static void
8123 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8124 {
8125         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8126
8127         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8128 }
8129
8130 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8131 {
8132         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8133         u32 in_msg = 0;
8134
8135         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8136                 return;
8137
8138         /* PF reset VF event */
8139         if (in_msg == IXGBE_PF_CONTROL_MSG)
8140                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
8141 }
8142
8143 static int
8144 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8145 {
8146         uint32_t eicr;
8147         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8148         struct ixgbe_interrupt *intr =
8149                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8150         ixgbevf_intr_disable(hw);
8151
8152         /* read-on-clear nic registers here */
8153         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8154         intr->flags = 0;
8155
8156         /* only one misc vector supported - mailbox */
8157         eicr &= IXGBE_VTEICR_MASK;
8158         if (eicr == IXGBE_MISC_VEC_ID)
8159                 intr->flags |= IXGBE_FLAG_MAILBOX;
8160
8161         return 0;
8162 }
8163
8164 static int
8165 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8166 {
8167         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8168         struct ixgbe_interrupt *intr =
8169                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8170
8171         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8172                 ixgbevf_mbx_process(dev);
8173                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8174         }
8175
8176         ixgbevf_intr_enable(hw);
8177
8178         return 0;
8179 }
8180
8181 static void
8182 ixgbevf_dev_interrupt_handler(void *param)
8183 {
8184         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8185
8186         ixgbevf_dev_interrupt_get_status(dev);
8187         ixgbevf_dev_interrupt_action(dev);
8188 }
8189
8190 /**
8191  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8192  *  @hw: pointer to hardware structure
8193  *
8194  *  Stops the transmit data path and waits for the HW to internally empty
8195  *  the Tx security block
8196  **/
8197 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8198 {
8199 #define IXGBE_MAX_SECTX_POLL 40
8200
8201         int i;
8202         int sectxreg;
8203
8204         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8205         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8206         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8207         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8208                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8209                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8210                         break;
8211                 /* Use interrupt-safe sleep just in case */
8212                 usec_delay(1000);
8213         }
8214
8215         /* For informational purposes only */
8216         if (i >= IXGBE_MAX_SECTX_POLL)
8217                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8218                          "path fully disabled.  Continuing with init.");
8219
8220         return IXGBE_SUCCESS;
8221 }
8222
8223 /**
8224  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8225  *  @hw: pointer to hardware structure
8226  *
8227  *  Enables the transmit data path.
8228  **/
8229 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8230 {
8231         uint32_t sectxreg;
8232
8233         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8234         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8235         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8236         IXGBE_WRITE_FLUSH(hw);
8237
8238         return IXGBE_SUCCESS;
8239 }
8240
8241 int
8242 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
8243 {
8244         struct ixgbe_hw *hw;
8245         struct rte_eth_dev *dev;
8246         uint32_t ctrl;
8247
8248         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8249
8250         dev = &rte_eth_devices[port];
8251
8252         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8253                 return -ENOTSUP;
8254
8255         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8256
8257         /* Stop the data paths */
8258         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8259                 return -ENOTSUP;
8260         /*
8261          * Workaround:
8262          * As no ixgbe_disable_sec_rx_path equivalent is
8263          * implemented for tx in the base code, and we are
8264          * not allowed to modify the base code in DPDK, so
8265          * just call the hand-written one directly for now.
8266          * The hardware support has been checked by
8267          * ixgbe_disable_sec_rx_path().
8268          */
8269         ixgbe_disable_sec_tx_path_generic(hw);
8270
8271         /* Enable Ethernet CRC (required by MACsec offload) */
8272         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8273         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8274         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8275
8276         /* Enable the TX and RX crypto engines */
8277         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8278         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8279         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8280
8281         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8282         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8283         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8284
8285         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8286         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8287         ctrl |= 0x3;
8288         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8289
8290         /* Enable SA lookup */
8291         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8292         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8293         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8294                      IXGBE_LSECTXCTRL_AUTH;
8295         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8296         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8297         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8298         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8299
8300         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8301         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8302         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8303         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8304         if (rp)
8305                 ctrl |= IXGBE_LSECRXCTRL_RP;
8306         else
8307                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8308         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8309
8310         /* Start the data paths */
8311         ixgbe_enable_sec_rx_path(hw);
8312         /*
8313          * Workaround:
8314          * As no ixgbe_enable_sec_rx_path equivalent is
8315          * implemented for tx in the base code, and we are
8316          * not allowed to modify the base code in DPDK, so
8317          * just call the hand-written one directly for now.
8318          */
8319         ixgbe_enable_sec_tx_path_generic(hw);
8320
8321         return 0;
8322 }
8323
8324 int
8325 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8326 {
8327         struct ixgbe_hw *hw;
8328         struct rte_eth_dev *dev;
8329         uint32_t ctrl;
8330
8331         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8332
8333         dev = &rte_eth_devices[port];
8334
8335         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8336                 return -ENOTSUP;
8337
8338         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8339
8340         /* Stop the data paths */
8341         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8342                 return -ENOTSUP;
8343         /*
8344          * Workaround:
8345          * As no ixgbe_disable_sec_rx_path equivalent is
8346          * implemented for tx in the base code, and we are
8347          * not allowed to modify the base code in DPDK, so
8348          * just call the hand-written one directly for now.
8349          * The hardware support has been checked by
8350          * ixgbe_disable_sec_rx_path().
8351          */
8352         ixgbe_disable_sec_tx_path_generic(hw);
8353
8354         /* Disable the TX and RX crypto engines */
8355         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8356         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8357         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8358
8359         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8360         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8361         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8362
8363         /* Disable SA lookup */
8364         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8365         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8366         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8367         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8368
8369         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8370         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8371         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8372         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8373
8374         /* Start the data paths */
8375         ixgbe_enable_sec_rx_path(hw);
8376         /*
8377          * Workaround:
8378          * As no ixgbe_enable_sec_rx_path equivalent is
8379          * implemented for tx in the base code, and we are
8380          * not allowed to modify the base code in DPDK, so
8381          * just call the hand-written one directly for now.
8382          */
8383         ixgbe_enable_sec_tx_path_generic(hw);
8384
8385         return 0;
8386 }
8387
8388 int
8389 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8390 {
8391         struct ixgbe_hw *hw;
8392         struct rte_eth_dev *dev;
8393         uint32_t ctrl;
8394
8395         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8396
8397         dev = &rte_eth_devices[port];
8398
8399         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8400                 return -ENOTSUP;
8401
8402         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8403
8404         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8405         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8406
8407         ctrl = mac[4] | (mac[5] << 8);
8408         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8409
8410         return 0;
8411 }
8412
8413 int
8414 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8415 {
8416         struct ixgbe_hw *hw;
8417         struct rte_eth_dev *dev;
8418         uint32_t ctrl;
8419
8420         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8421
8422         dev = &rte_eth_devices[port];
8423
8424         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8425                 return -ENOTSUP;
8426
8427         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8428
8429         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8430         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8431
8432         pi = rte_cpu_to_be_16(pi);
8433         ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8434         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8435
8436         return 0;
8437 }
8438
8439 int
8440 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8441                                  uint32_t pn, uint8_t *key)
8442 {
8443         struct ixgbe_hw *hw;
8444         struct rte_eth_dev *dev;
8445         uint32_t ctrl, i;
8446
8447         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8448
8449         dev = &rte_eth_devices[port];
8450
8451         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8452                 return -ENOTSUP;
8453
8454         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8455
8456         if (idx != 0 && idx != 1)
8457                 return -EINVAL;
8458
8459         if (an >= 4)
8460                 return -EINVAL;
8461
8462         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8463
8464         /* Set the PN and key */
8465         pn = rte_cpu_to_be_32(pn);
8466         if (idx == 0) {
8467                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8468
8469                 for (i = 0; i < 4; i++) {
8470                         ctrl = (key[i * 4 + 0] <<  0) |
8471                                (key[i * 4 + 1] <<  8) |
8472                                (key[i * 4 + 2] << 16) |
8473                                (key[i * 4 + 3] << 24);
8474                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8475                 }
8476         } else {
8477                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8478
8479                 for (i = 0; i < 4; i++) {
8480                         ctrl = (key[i * 4 + 0] <<  0) |
8481                                (key[i * 4 + 1] <<  8) |
8482                                (key[i * 4 + 2] << 16) |
8483                                (key[i * 4 + 3] << 24);
8484                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8485                 }
8486         }
8487
8488         /* Set AN and select the SA */
8489         ctrl = (an << idx * 2) | (idx << 4);
8490         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8491
8492         return 0;
8493 }
8494
8495 int
8496 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8497                                  uint32_t pn, uint8_t *key)
8498 {
8499         struct ixgbe_hw *hw;
8500         struct rte_eth_dev *dev;
8501         uint32_t ctrl, i;
8502
8503         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8504
8505         dev = &rte_eth_devices[port];
8506
8507         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8508                 return -ENOTSUP;
8509
8510         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8511
8512         if (idx != 0 && idx != 1)
8513                 return -EINVAL;
8514
8515         if (an >= 4)
8516                 return -EINVAL;
8517
8518         /* Set the PN */
8519         pn = rte_cpu_to_be_32(pn);
8520         IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8521
8522         /* Set the key */
8523         for (i = 0; i < 4; i++) {
8524                 ctrl = (key[i * 4 + 0] <<  0) |
8525                        (key[i * 4 + 1] <<  8) |
8526                        (key[i * 4 + 2] << 16) |
8527                        (key[i * 4 + 3] << 24);
8528                 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8529         }
8530
8531         /* Set the AN and validate the SA */
8532         ctrl = an | (1 << 2);
8533         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8534
8535         return 0;
8536 }
8537
8538 /* restore n-tuple filter */
8539 static inline void
8540 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8541 {
8542         struct ixgbe_filter_info *filter_info =
8543                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8544         struct ixgbe_5tuple_filter *node;
8545
8546         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8547                 ixgbe_inject_5tuple_filter(dev, node);
8548         }
8549 }
8550
8551 /* restore ethernet type filter */
8552 static inline void
8553 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8554 {
8555         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8556         struct ixgbe_filter_info *filter_info =
8557                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8558         int i;
8559
8560         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8561                 if (filter_info->ethertype_mask & (1 << i)) {
8562                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8563                                         filter_info->ethertype_filters[i].etqf);
8564                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8565                                         filter_info->ethertype_filters[i].etqs);
8566                         IXGBE_WRITE_FLUSH(hw);
8567                 }
8568         }
8569 }
8570
8571 /* restore SYN filter */
8572 static inline void
8573 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8574 {
8575         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8576         struct ixgbe_filter_info *filter_info =
8577                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8578         uint32_t synqf;
8579
8580         synqf = filter_info->syn_info;
8581
8582         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8583                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8584                 IXGBE_WRITE_FLUSH(hw);
8585         }
8586 }
8587
8588 /* restore L2 tunnel filter */
8589 static inline void
8590 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8591 {
8592         struct ixgbe_l2_tn_info *l2_tn_info =
8593                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8594         struct ixgbe_l2_tn_filter *node;
8595         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8596
8597         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8598                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8599                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8600                 l2_tn_conf.pool           = node->pool;
8601                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8602         }
8603 }
8604
8605 static int
8606 ixgbe_filter_restore(struct rte_eth_dev *dev)
8607 {
8608         ixgbe_ntuple_filter_restore(dev);
8609         ixgbe_ethertype_filter_restore(dev);
8610         ixgbe_syn_filter_restore(dev);
8611         ixgbe_fdir_filter_restore(dev);
8612         ixgbe_l2_tn_filter_restore(dev);
8613
8614         return 0;
8615 }
8616
8617 static void
8618 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8619 {
8620         struct ixgbe_l2_tn_info *l2_tn_info =
8621                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8622         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8623
8624         if (l2_tn_info->e_tag_en)
8625                 (void)ixgbe_e_tag_enable(hw);
8626
8627         if (l2_tn_info->e_tag_fwd_en)
8628                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8629
8630         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8631 }
8632
8633 /* remove all the n-tuple filters */
8634 void
8635 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8636 {
8637         struct ixgbe_filter_info *filter_info =
8638                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8639         struct ixgbe_5tuple_filter *p_5tuple;
8640
8641         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8642                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8643 }
8644
8645 /* remove all the ether type filters */
8646 void
8647 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8648 {
8649         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8650         struct ixgbe_filter_info *filter_info =
8651                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8652         int i;
8653
8654         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8655                 if (filter_info->ethertype_mask & (1 << i) &&
8656                     !filter_info->ethertype_filters[i].conf) {
8657                         (void)ixgbe_ethertype_filter_remove(filter_info,
8658                                                             (uint8_t)i);
8659                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8660                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8661                         IXGBE_WRITE_FLUSH(hw);
8662                 }
8663         }
8664 }
8665
8666 /* remove the SYN filter */
8667 void
8668 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8669 {
8670         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8671         struct ixgbe_filter_info *filter_info =
8672                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8673
8674         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8675                 filter_info->syn_info = 0;
8676
8677                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8678                 IXGBE_WRITE_FLUSH(hw);
8679         }
8680 }
8681
8682 /* remove all the L2 tunnel filters */
8683 int
8684 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8685 {
8686         struct ixgbe_l2_tn_info *l2_tn_info =
8687                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8688         struct ixgbe_l2_tn_filter *l2_tn_filter;
8689         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8690         int ret = 0;
8691
8692         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8693                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8694                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8695                 l2_tn_conf.pool           = l2_tn_filter->pool;
8696                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8697                 if (ret < 0)
8698                         return ret;
8699         }
8700
8701         return 0;
8702 }
8703
8704 int
8705 rte_pmd_ixgbe_set_tc_bw_alloc(uint8_t port,
8706                               uint8_t tc_num,
8707                               uint8_t *bw_weight)
8708 {
8709         struct rte_eth_dev *dev;
8710         struct ixgbe_dcb_config *dcb_config;
8711         struct ixgbe_dcb_tc_config *tc;
8712         struct rte_eth_conf *eth_conf;
8713         struct ixgbe_bw_conf *bw_conf;
8714         uint8_t i;
8715         uint8_t nb_tcs;
8716         uint16_t sum;
8717
8718         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8719
8720         dev = &rte_eth_devices[port];
8721
8722         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8723                 return -ENOTSUP;
8724
8725         if (tc_num > IXGBE_DCB_MAX_TRAFFIC_CLASS) {
8726                 PMD_DRV_LOG(ERR, "TCs should be no more than %d.",
8727                             IXGBE_DCB_MAX_TRAFFIC_CLASS);
8728                 return -EINVAL;
8729         }
8730
8731         dcb_config = IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
8732         bw_conf = IXGBE_DEV_PRIVATE_TO_BW_CONF(dev->data->dev_private);
8733         eth_conf = &dev->data->dev_conf;
8734
8735         if (eth_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
8736                 nb_tcs = eth_conf->tx_adv_conf.dcb_tx_conf.nb_tcs;
8737         } else if (eth_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
8738                 if (eth_conf->tx_adv_conf.vmdq_dcb_tx_conf.nb_queue_pools ==
8739                     ETH_32_POOLS)
8740                         nb_tcs = ETH_4_TCS;
8741                 else
8742                         nb_tcs = ETH_8_TCS;
8743         } else {
8744                 nb_tcs = 1;
8745         }
8746
8747         if (nb_tcs != tc_num) {
8748                 PMD_DRV_LOG(ERR,
8749                             "Weight should be set for all %d enabled TCs.",
8750                             nb_tcs);
8751                 return -EINVAL;
8752         }
8753
8754         sum = 0;
8755         for (i = 0; i < nb_tcs; i++)
8756                 sum += bw_weight[i];
8757         if (sum != 100) {
8758                 PMD_DRV_LOG(ERR,
8759                             "The summary of the TC weight should be 100.");
8760                 return -EINVAL;
8761         }
8762
8763         for (i = 0; i < nb_tcs; i++) {
8764                 tc = &dcb_config->tc_config[i];
8765                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = bw_weight[i];
8766         }
8767         for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
8768                 tc = &dcb_config->tc_config[i];
8769                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
8770         }
8771
8772         bw_conf->tc_num = nb_tcs;
8773
8774         return 0;
8775 }
8776
8777 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8778 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8779 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8780 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8781 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8782 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");