drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64 #include <rte_hash_crc.h>
  65
  66 #include "ixgbe_logs.h"
  67 #include "base/ixgbe_api.h"
  68 #include "base/ixgbe_vf.h"
  69 #include "base/ixgbe_common.h"
  70 #include "ixgbe_ethdev.h"
  71 #include "ixgbe_bypass.h"
  72 #include "ixgbe_rxtx.h"
  73 #include "base/ixgbe_type.h"
  74 #include "base/ixgbe_phy.h"
  75 #include "ixgbe_regs.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 158 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 163 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 166 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 167 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 168 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 172 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 177 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 178                                 int wait_to_complete);
 179 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 180                                 struct rte_eth_stats *stats);
 181 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 182                                 struct rte_eth_xstat *xstats, unsigned n);
 183 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 184                                   struct rte_eth_xstat *xstats, unsigned n);
 185 static int
 186 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 187                 uint64_t *values, unsigned int n);
 188 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 189 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 190 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names,
 192         unsigned int size);
 193 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 194         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 195 static int ixgbe_dev_xstats_get_names_by_id(
 196         struct rte_eth_dev *dev,
 197         struct rte_eth_xstat_name *xstats_names,
 198         const uint64_t *ids,
 199         unsigned int limit);
 200 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 201                                              uint16_t queue_id,
 202                                              uint8_t stat_idx,
 203                                              uint8_t is_rx);
 204 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 205                                  size_t fw_size);
 206 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 207                                struct rte_eth_dev_info *dev_info);
 208 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 209 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 210                                  struct rte_eth_dev_info *dev_info);
 211 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 212
 213 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 214                 uint16_t vlan_id, int on);
 215 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 216                                enum rte_vlan_type vlan_type,
 217                                uint16_t tpid_id);
 218 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 219                 uint16_t queue, bool on);
 220 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 221                 int on);
 222 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 223 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 224 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 225 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 226 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 227
 228 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 230 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 231                                struct rte_eth_fc_conf *fc_conf);
 232 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 233                                struct rte_eth_fc_conf *fc_conf);
 234 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 235                 struct rte_eth_pfc_conf *pfc_conf);
 236 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 237                         struct rte_eth_rss_reta_entry64 *reta_conf,
 238                         uint16_t reta_size);
 239 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 240                         struct rte_eth_rss_reta_entry64 *reta_conf,
 241                         uint16_t reta_size);
 242 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 243 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 244 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 245 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 246 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 247 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 248                                       struct rte_intr_handle *handle);
 249 static void ixgbe_dev_interrupt_handler(void *param);
 250 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 251 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 252                          uint32_t index, uint32_t pool);
 253 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 254 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 255                                            struct ether_addr *mac_addr);
 256 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 257 static bool is_device_supported(struct rte_eth_dev *dev,
 258                                 struct rte_pci_driver *drv);
 259
 260 /* For Virtual Function support */
 261 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 262 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 263 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 264 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 266 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 267 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 268 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 269 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 270                 struct rte_eth_stats *stats);
 271 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 272 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 273                 uint16_t vlan_id, int on);
 274 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 275                 uint16_t queue, int on);
 276 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 277 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 278 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 279                                             uint16_t queue_id);
 280 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 281                                              uint16_t queue_id);
 282 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 283                                  uint8_t queue, uint8_t msix_vector);
 284 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 285 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 286 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 287
 288 /* For Eth VMDQ APIs support */
 289 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 290                 ether_addr * mac_addr, uint8_t on);
 291 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 292 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 293                 struct rte_eth_mirror_conf *mirror_conf,
 294                 uint8_t rule_id, uint8_t on);
 295 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 296                 uint8_t rule_id);
 297 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 298                                           uint16_t queue_id);
 299 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 300                                            uint16_t queue_id);
 301 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 302                                uint8_t queue, uint8_t msix_vector);
 303 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 304
 305 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 306                 uint16_t queue_idx, uint16_t tx_rate);
 307
 308 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 309                                 struct ether_addr *mac_addr,
 310                                 uint32_t index, uint32_t pool);
 311 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 312 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 313                                              struct ether_addr *mac_addr);
 314 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 315                         struct rte_eth_syn_filter *filter);
 316 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 317                         enum rte_filter_op filter_op,
 318                         void *arg);
 319 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 320                         struct ixgbe_5tuple_filter *filter);
 321 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 322                         struct ixgbe_5tuple_filter *filter);
 323 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 327                         struct rte_eth_ntuple_filter *filter);
 328 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 329                                 enum rte_filter_op filter_op,
 330                                 void *arg);
 331 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 332                         struct rte_eth_ethertype_filter *filter);
 333 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 334                      enum rte_filter_type filter_type,
 335                      enum rte_filter_op filter_op,
 336                      void *arg);
 337 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 338
 339 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 340                                       struct ether_addr *mc_addr_set,
 341                                       uint32_t nb_mc_addr);
 342 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 343                                    struct rte_eth_dcb_info *dcb_info);
 344
 345 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 346 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 347                             struct rte_dev_reg_info *regs);
 348 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 349 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 350                                 struct rte_dev_eeprom_info *eeprom);
 351 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 352                                 struct rte_dev_eeprom_info *eeprom);
 353
 354 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 355 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 356                                 struct rte_dev_reg_info *regs);
 357
 358 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 359 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 360 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 361                                             struct timespec *timestamp,
 362                                             uint32_t flags);
 363 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 364                                             struct timespec *timestamp);
 365 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 366 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 367                                    struct timespec *timestamp);
 368 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 369                                    const struct timespec *timestamp);
 370 static void ixgbevf_dev_interrupt_handler(void *param);
 371
 372 static int ixgbe_dev_l2_tunnel_eth_type_conf
 373         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 374 static int ixgbe_dev_l2_tunnel_offload_set
 375         (struct rte_eth_dev *dev,
 376          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 377          uint32_t mask,
 378          uint8_t en);
 379 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 380                                              enum rte_filter_op filter_op,
 381                                              void *arg);
 382
 383 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 384                                          struct rte_eth_udp_tunnel *udp_tunnel);
 385 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 386                                          struct rte_eth_udp_tunnel *udp_tunnel);
 387 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 388 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 389
 390 /*
 391  * Define VF Stats MACRO for Non "cleared on read" register
 392  */
 393 #define UPDATE_VF_STAT(reg, last, cur)                          \
 394 {                                                               \
 395         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 396         cur += (latest - last) & UINT_MAX;                      \
 397         last = latest;                                          \
 398 }
 399
 400 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 401 {                                                                \
 402         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 403         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 404         u64 latest = ((new_msb << 32) | new_lsb);                \
 405         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 406         last = latest;                                           \
 407 }
 408
 409 #define IXGBE_SET_HWSTRIP(h, q) do {\
 410                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 411                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 412                 (h)->bitmap[idx] |= 1 << bit;\
 413         } while (0)
 414
 415 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 416                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 417                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 418                 (h)->bitmap[idx] &= ~(1 << bit);\
 419         } while (0)
 420
 421 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 422                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 423                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 424                 (r) = (h)->bitmap[idx] >> bit & 1;\
 425         } while (0)
 426
 427 /*
 428  * The set of PCI devices this driver supports
 429  */
 430 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 484 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 486 #endif
 487         { .vendor_id = 0, /* sentinel */ },
 488 };
 489
 490 /*
 491  * The set of PCI devices this driver supports (for 82599 VF)
 492  */
 493 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 504         { .vendor_id = 0, /* sentinel */ },
 505 };
 506
 507 static const struct rte_eth_desc_lim rx_desc_lim = {
 508         .nb_max = IXGBE_MAX_RING_DESC,
 509         .nb_min = IXGBE_MIN_RING_DESC,
 510         .nb_align = IXGBE_RXD_ALIGN,
 511 };
 512
 513 static const struct rte_eth_desc_lim tx_desc_lim = {
 514         .nb_max = IXGBE_MAX_RING_DESC,
 515         .nb_min = IXGBE_MIN_RING_DESC,
 516         .nb_align = IXGBE_TXD_ALIGN,
 517         .nb_seg_max = IXGBE_TX_MAX_SEG,
 518         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 519 };
 520
 521 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 522         .dev_configure        = ixgbe_dev_configure,
 523         .dev_start            = ixgbe_dev_start,
 524         .dev_stop             = ixgbe_dev_stop,
 525         .dev_set_link_up    = ixgbe_dev_set_link_up,
 526         .dev_set_link_down  = ixgbe_dev_set_link_down,
 527         .dev_close            = ixgbe_dev_close,
 528         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 529         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 530         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 531         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 532         .link_update          = ixgbe_dev_link_update,
 533         .stats_get            = ixgbe_dev_stats_get,
 534         .xstats_get           = ixgbe_dev_xstats_get,
 535         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 536         .stats_reset          = ixgbe_dev_stats_reset,
 537         .xstats_reset         = ixgbe_dev_xstats_reset,
 538         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 539         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 540         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 541         .fw_version_get       = ixgbe_fw_version_get,
 542         .dev_infos_get        = ixgbe_dev_info_get,
 543         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 544         .mtu_set              = ixgbe_dev_mtu_set,
 545         .vlan_filter_set      = ixgbe_vlan_filter_set,
 546         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 547         .vlan_offload_set     = ixgbe_vlan_offload_set,
 548         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 549         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 550         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 551         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 552         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 553         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 554         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 555         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 556         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 557         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 558         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 559         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 560         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 561         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 562         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 563         .dev_led_on           = ixgbe_dev_led_on,
 564         .dev_led_off          = ixgbe_dev_led_off,
 565         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 566         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 567         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 568         .mac_addr_add         = ixgbe_add_rar,
 569         .mac_addr_remove      = ixgbe_remove_rar,
 570         .mac_addr_set         = ixgbe_set_default_mac_addr,
 571         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 572         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 573         .mirror_rule_set      = ixgbe_mirror_rule_set,
 574         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 575         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 576         .reta_update          = ixgbe_dev_rss_reta_update,
 577         .reta_query           = ixgbe_dev_rss_reta_query,
 578         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 579         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 580         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 581         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 582         .rxq_info_get         = ixgbe_rxq_info_get,
 583         .txq_info_get         = ixgbe_txq_info_get,
 584         .timesync_enable      = ixgbe_timesync_enable,
 585         .timesync_disable     = ixgbe_timesync_disable,
 586         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 587         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 588         .get_reg              = ixgbe_get_regs,
 589         .get_eeprom_length    = ixgbe_get_eeprom_length,
 590         .get_eeprom           = ixgbe_get_eeprom,
 591         .set_eeprom           = ixgbe_set_eeprom,
 592         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 593         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 594         .timesync_read_time   = ixgbe_timesync_read_time,
 595         .timesync_write_time  = ixgbe_timesync_write_time,
 596         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 597         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 598         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 599         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 600 };
 601
 602 /*
 603  * dev_ops for virtual function, bare necessities for basic vf
 604  * operation have been implemented
 605  */
 606 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 607         .dev_configure        = ixgbevf_dev_configure,
 608         .dev_start            = ixgbevf_dev_start,
 609         .dev_stop             = ixgbevf_dev_stop,
 610         .link_update          = ixgbe_dev_link_update,
 611         .stats_get            = ixgbevf_dev_stats_get,
 612         .xstats_get           = ixgbevf_dev_xstats_get,
 613         .stats_reset          = ixgbevf_dev_stats_reset,
 614         .xstats_reset         = ixgbevf_dev_stats_reset,
 615         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 616         .dev_close            = ixgbevf_dev_close,
 617         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 618         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 619         .dev_infos_get        = ixgbevf_dev_info_get,
 620         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 621         .mtu_set              = ixgbevf_dev_set_mtu,
 622         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 623         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 624         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 625         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 626         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 627         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 628         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 629         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 630         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 631         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 632         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 633         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 634         .mac_addr_add         = ixgbevf_add_mac_addr,
 635         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 636         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 637         .rxq_info_get         = ixgbe_rxq_info_get,
 638         .txq_info_get         = ixgbe_txq_info_get,
 639         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 640         .get_reg              = ixgbevf_get_regs,
 641         .reta_update          = ixgbe_dev_rss_reta_update,
 642         .reta_query           = ixgbe_dev_rss_reta_query,
 643         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 644         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 645 };
 646
 647 /* store statistics names and its offset in stats structure */
 648 struct rte_ixgbe_xstats_name_off {
 649         char name[RTE_ETH_XSTATS_NAME_SIZE];
 650         unsigned offset;
 651 };
 652
 653 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 654         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 655         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 656         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 657         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 658         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 659         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 660         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 661         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 662         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 663         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 664         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 665         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 666         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 667         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 668         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 669                 prc1023)},
 670         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 671                 prc1522)},
 672         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 673         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 674         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 675         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 676         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 677         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 678         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 679         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 680         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 681         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 682         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 683         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 684         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 685         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 686         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 687         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 688         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 689                 ptc1023)},
 690         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 691                 ptc1522)},
 692         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 693         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 694         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 695         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 696
 697         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 698                 fdirustat_add)},
 699         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 700                 fdirustat_remove)},
 701         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 702                 fdirfstat_fadd)},
 703         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 704                 fdirfstat_fremove)},
 705         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 706                 fdirmatch)},
 707         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 708                 fdirmiss)},
 709
 710         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 711         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 712         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 713                 fclast)},
 714         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 715         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 716         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 717         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 718         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 719                 fcoe_noddp)},
 720         {"rx_fcoe_no_direct_data_placement_ext_buff",
 721                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 722
 723         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 724                 lxontxc)},
 725         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 726                 lxonrxc)},
 727         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 728                 lxofftxc)},
 729         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 730                 lxoffrxc)},
 731         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 732 };
 733
 734 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 735                            sizeof(rte_ixgbe_stats_strings[0]))
 736
 737 /* MACsec statistics */
 738 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 739         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 740                 out_pkts_untagged)},
 741         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 742                 out_pkts_encrypted)},
 743         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 744                 out_pkts_protected)},
 745         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 746                 out_octets_encrypted)},
 747         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 748                 out_octets_protected)},
 749         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_untagged)},
 751         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_badtag)},
 753         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_nosci)},
 755         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_unknownsci)},
 757         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 758                 in_octets_decrypted)},
 759         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 760                 in_octets_validated)},
 761         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_unchecked)},
 763         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_delayed)},
 765         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_late)},
 767         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_ok)},
 769         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 770                 in_pkts_invalid)},
 771         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 772                 in_pkts_notvalid)},
 773         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 774                 in_pkts_unusedsa)},
 775         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 776                 in_pkts_notusingsa)},
 777 };
 778
 779 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 780                            sizeof(rte_ixgbe_macsec_strings[0]))
 781
 782 /* Per-queue statistics */
 783 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 784         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 785         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 786         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 787         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 788 };
 789
 790 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 791                            sizeof(rte_ixgbe_rxq_strings[0]))
 792 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 793
 794 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 795         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 796         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 797         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 798                 pxon2offc)},
 799 };
 800
 801 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 802                            sizeof(rte_ixgbe_txq_strings[0]))
 803 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 804
 805 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 806         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 807 };
 808
 809 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 810                 sizeof(rte_ixgbevf_stats_strings[0]))
 811
 812 /**
 813  * Atomically reads the link status information from global
 814  * structure rte_eth_dev.
 815  *
 816  * @param dev
 817  *   - Pointer to the structure rte_eth_dev to read from.
 818  *   - Pointer to the buffer to be saved with the link status.
 819  *
 820  * @return
 821  *   - On success, zero.
 822  *   - On failure, negative value.
 823  */
 824 static inline int
 825 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 826                                 struct rte_eth_link *link)
 827 {
 828         struct rte_eth_link *dst = link;
 829         struct rte_eth_link *src = &(dev->data->dev_link);
 830
 831         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 832                                         *(uint64_t *)src) == 0)
 833                 return -1;
 834
 835         return 0;
 836 }
 837
 838 /**
 839  * Atomically writes the link status information into global
 840  * structure rte_eth_dev.
 841  *
 842  * @param dev
 843  *   - Pointer to the structure rte_eth_dev to read from.
 844  *   - Pointer to the buffer to be saved with the link status.
 845  *
 846  * @return
 847  *   - On success, zero.
 848  *   - On failure, negative value.
 849  */
 850 static inline int
 851 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 852                                 struct rte_eth_link *link)
 853 {
 854         struct rte_eth_link *dst = &(dev->data->dev_link);
 855         struct rte_eth_link *src = link;
 856
 857         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 858                                         *(uint64_t *)src) == 0)
 859                 return -1;
 860
 861         return 0;
 862 }
 863
 864 /*
 865  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 866  */
 867 static inline int
 868 ixgbe_is_sfp(struct ixgbe_hw *hw)
 869 {
 870         switch (hw->phy.type) {
 871         case ixgbe_phy_sfp_avago:
 872         case ixgbe_phy_sfp_ftl:
 873         case ixgbe_phy_sfp_intel:
 874         case ixgbe_phy_sfp_unknown:
 875         case ixgbe_phy_sfp_passive_tyco:
 876         case ixgbe_phy_sfp_passive_unknown:
 877                 return 1;
 878         default:
 879                 return 0;
 880         }
 881 }
 882
 883 static inline int32_t
 884 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 885 {
 886         uint32_t ctrl_ext;
 887         int32_t status;
 888
 889         status = ixgbe_reset_hw(hw);
 890
 891         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 892         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 893         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 894         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 895         IXGBE_WRITE_FLUSH(hw);
 896
 897         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 898                 status = IXGBE_SUCCESS;
 899         return status;
 900 }
 901
 902 static inline void
 903 ixgbe_enable_intr(struct rte_eth_dev *dev)
 904 {
 905         struct ixgbe_interrupt *intr =
 906                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 907         struct ixgbe_hw *hw =
 908                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 909
 910         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 911         IXGBE_WRITE_FLUSH(hw);
 912 }
 913
 914 /*
 915  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 916  */
 917 static void
 918 ixgbe_disable_intr(struct ixgbe_hw *hw)
 919 {
 920         PMD_INIT_FUNC_TRACE();
 921
 922         if (hw->mac.type == ixgbe_mac_82598EB) {
 923                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 924         } else {
 925                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 926                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 927                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 928         }
 929         IXGBE_WRITE_FLUSH(hw);
 930 }
 931
 932 /*
 933  * This function resets queue statistics mapping registers.
 934  * From Niantic datasheet, Initialization of Statistics section:
 935  * "...if software requires the queue counters, the RQSMR and TQSM registers
 936  * must be re-programmed following a device reset.
 937  */
 938 static void
 939 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 940 {
 941         uint32_t i;
 942
 943         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 944                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 945                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 946         }
 947 }
 948
 949
 950 static int
 951 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 952                                   uint16_t queue_id,
 953                                   uint8_t stat_idx,
 954                                   uint8_t is_rx)
 955 {
 956 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 957 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 958 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 959
 960         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 961         struct ixgbe_stat_mapping_registers *stat_mappings =
 962                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 963         uint32_t qsmr_mask = 0;
 964         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 965         uint32_t q_map;
 966         uint8_t n, offset;
 967
 968         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 969                 (hw->mac.type != ixgbe_mac_X540) &&
 970                 (hw->mac.type != ixgbe_mac_X550) &&
 971                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 972                 (hw->mac.type != ixgbe_mac_X550EM_a))
 973                 return -ENOSYS;
 974
 975         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 976                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 977                      queue_id, stat_idx);
 978
 979         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 980         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 981                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 982                 return -EIO;
 983         }
 984         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 985
 986         /* Now clear any previous stat_idx set */
 987         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 988         if (!is_rx)
 989                 stat_mappings->tqsm[n] &= ~clearing_mask;
 990         else
 991                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 992
 993         q_map = (uint32_t)stat_idx;
 994         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 995         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 996         if (!is_rx)
 997                 stat_mappings->tqsm[n] |= qsmr_mask;
 998         else
 999                 stat_mappings->rqsmr[n] |= qsmr_mask;
1000
1001         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1002                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1003                      queue_id, stat_idx);
1004         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1005                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1006
1007         /* Now write the mapping in the appropriate register */
1008         if (is_rx) {
1009                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1010                              stat_mappings->rqsmr[n], n);
1011                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1012         } else {
1013                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1014                              stat_mappings->tqsm[n], n);
1015                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1016         }
1017         return 0;
1018 }
1019
1020 static void
1021 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1022 {
1023         struct ixgbe_stat_mapping_registers *stat_mappings =
1024                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1025         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1026         int i;
1027
1028         /* write whatever was in stat mapping table to the NIC */
1029         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1030                 /* rx */
1031                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1032
1033                 /* tx */
1034                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1035         }
1036 }
1037
1038 static void
1039 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1040 {
1041         uint8_t i;
1042         struct ixgbe_dcb_tc_config *tc;
1043         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1044
1045         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1046         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1047         for (i = 0; i < dcb_max_tc; i++) {
1048                 tc = &dcb_config->tc_config[i];
1049                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1050                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1051                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1052                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1053                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1054                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1055                 tc->pfc = ixgbe_dcb_pfc_disabled;
1056         }
1057
1058         /* Initialize default user to priority mapping, UPx->TC0 */
1059         tc = &dcb_config->tc_config[0];
1060         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1061         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1062         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1063                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1064                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1065         }
1066         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1067         dcb_config->pfc_mode_enable = false;
1068         dcb_config->vt_mode = true;
1069         dcb_config->round_robin_enable = false;
1070         /* support all DCB capabilities in 82599 */
1071         dcb_config->support.capabilities = 0xFF;
1072
1073         /*we only support 4 Tcs for X540, X550 */
1074         if (hw->mac.type == ixgbe_mac_X540 ||
1075                 hw->mac.type == ixgbe_mac_X550 ||
1076                 hw->mac.type == ixgbe_mac_X550EM_x ||
1077                 hw->mac.type == ixgbe_mac_X550EM_a) {
1078                 dcb_config->num_tcs.pg_tcs = 4;
1079                 dcb_config->num_tcs.pfc_tcs = 4;
1080         }
1081 }
1082
1083 /*
1084  * Ensure that all locks are released before first NVM or PHY access
1085  */
1086 static void
1087 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1088 {
1089         uint16_t mask;
1090
1091         /*
1092          * Phy lock should not fail in this early stage. If this is the case,
1093          * it is due to an improper exit of the application.
1094          * So force the release of the faulty lock. Release of common lock
1095          * is done automatically by swfw_sync function.
1096          */
1097         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1098         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1099                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1100         }
1101         ixgbe_release_swfw_semaphore(hw, mask);
1102
1103         /*
1104          * These ones are more tricky since they are common to all ports; but
1105          * swfw_sync retries last long enough (1s) to be almost sure that if
1106          * lock can not be taken it is due to an improper lock of the
1107          * semaphore.
1108          */
1109         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1110         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1111                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1112         }
1113         ixgbe_release_swfw_semaphore(hw, mask);
1114 }
1115
1116 /*
1117  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1118  * It returns 0 on success.
1119  */
1120 static int
1121 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1122 {
1123         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1124         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1125         struct ixgbe_hw *hw =
1126                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1127         struct ixgbe_vfta *shadow_vfta =
1128                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1129         struct ixgbe_hwstrip *hwstrip =
1130                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1131         struct ixgbe_dcb_config *dcb_config =
1132                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1133         struct ixgbe_filter_info *filter_info =
1134                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1135         struct ixgbe_bw_conf *bw_conf =
1136                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1137         uint32_t ctrl_ext;
1138         uint16_t csum;
1139         int diag, i;
1140
1141         PMD_INIT_FUNC_TRACE();
1142
1143         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1144         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1145         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1146         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1147
1148         /*
1149          * For secondary processes, we don't initialise any further as primary
1150          * has already done this work. Only check we don't need a different
1151          * RX and TX function.
1152          */
1153         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1154                 struct ixgbe_tx_queue *txq;
1155                 /* TX queue function in primary, set by last queue initialized
1156                  * Tx queue may not initialized by primary process
1157                  */
1158                 if (eth_dev->data->tx_queues) {
1159                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1160                         ixgbe_set_tx_function(eth_dev, txq);
1161                 } else {
1162                         /* Use default TX function if we get here */
1163                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1164                                      "Using default TX function.");
1165                 }
1166
1167                 ixgbe_set_rx_function(eth_dev);
1168
1169                 return 0;
1170         }
1171
1172         rte_eth_copy_pci_info(eth_dev, pci_dev);
1173         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1174
1175         /* Vendor and Device ID need to be set before init of shared code */
1176         hw->device_id = pci_dev->id.device_id;
1177         hw->vendor_id = pci_dev->id.vendor_id;
1178         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1179         hw->allow_unsupported_sfp = 1;
1180
1181         /* Initialize the shared code (base driver) */
1182 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1183         diag = ixgbe_bypass_init_shared_code(hw);
1184 #else
1185         diag = ixgbe_init_shared_code(hw);
1186 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1187
1188         if (diag != IXGBE_SUCCESS) {
1189                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1190                 return -EIO;
1191         }
1192
1193         /* pick up the PCI bus settings for reporting later */
1194         ixgbe_get_bus_info(hw);
1195
1196         /* Unlock any pending hardware semaphore */
1197         ixgbe_swfw_lock_reset(hw);
1198
1199         /* Initialize DCB configuration*/
1200         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1201         ixgbe_dcb_init(hw, dcb_config);
1202         /* Get Hardware Flow Control setting */
1203         hw->fc.requested_mode = ixgbe_fc_full;
1204         hw->fc.current_mode = ixgbe_fc_full;
1205         hw->fc.pause_time = IXGBE_FC_PAUSE;
1206         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1207                 hw->fc.low_water[i] = IXGBE_FC_LO;
1208                 hw->fc.high_water[i] = IXGBE_FC_HI;
1209         }
1210         hw->fc.send_xon = 1;
1211
1212         /* Make sure we have a good EEPROM before we read from it */
1213         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1214         if (diag != IXGBE_SUCCESS) {
1215                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1216                 return -EIO;
1217         }
1218
1219 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1220         diag = ixgbe_bypass_init_hw(hw);
1221 #else
1222         diag = ixgbe_init_hw(hw);
1223 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1224
1225         /*
1226          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1227          * is called too soon after the kernel driver unbinding/binding occurs.
1228          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1229          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1230          * also called. See ixgbe_identify_phy_82599(). The reason for the
1231          * failure is not known, and only occuts when virtualisation features
1232          * are disabled in the bios. A delay of 100ms  was found to be enough by
1233          * trial-and-error, and is doubled to be safe.
1234          */
1235         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1236                 rte_delay_ms(200);
1237                 diag = ixgbe_init_hw(hw);
1238         }
1239
1240         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1241                 diag = IXGBE_SUCCESS;
1242
1243         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1244                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1245                              "LOM.  Please be aware there may be issues associated "
1246                              "with your hardware.");
1247                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1248                              "please contact your Intel or hardware representative "
1249                              "who provided you with this hardware.");
1250         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1251                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1252         if (diag) {
1253                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1254                 return -EIO;
1255         }
1256
1257         /* Reset the hw statistics */
1258         ixgbe_dev_stats_reset(eth_dev);
1259
1260         /* disable interrupt */
1261         ixgbe_disable_intr(hw);
1262
1263         /* reset mappings for queue statistics hw counters*/
1264         ixgbe_reset_qstat_mappings(hw);
1265
1266         /* Allocate memory for storing MAC addresses */
1267         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1268                                                hw->mac.num_rar_entries, 0);
1269         if (eth_dev->data->mac_addrs == NULL) {
1270                 PMD_INIT_LOG(ERR,
1271                              "Failed to allocate %u bytes needed to store "
1272                              "MAC addresses",
1273                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1274                 return -ENOMEM;
1275         }
1276         /* Copy the permanent MAC address */
1277         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1278                         &eth_dev->data->mac_addrs[0]);
1279
1280         /* Allocate memory for storing hash filter MAC addresses */
1281         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1282                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1283         if (eth_dev->data->hash_mac_addrs == NULL) {
1284                 PMD_INIT_LOG(ERR,
1285                              "Failed to allocate %d bytes needed to store MAC addresses",
1286                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1287                 return -ENOMEM;
1288         }
1289
1290         /* initialize the vfta */
1291         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1292
1293         /* initialize the hw strip bitmap*/
1294         memset(hwstrip, 0, sizeof(*hwstrip));
1295
1296         /* initialize PF if max_vfs not zero */
1297         ixgbe_pf_host_init(eth_dev);
1298
1299         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1300         /* let hardware know driver is loaded */
1301         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1302         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1303         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1304         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1305         IXGBE_WRITE_FLUSH(hw);
1306
1307         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1308                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1309                              (int) hw->mac.type, (int) hw->phy.type,
1310                              (int) hw->phy.sfp_type);
1311         else
1312                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1313                              (int) hw->mac.type, (int) hw->phy.type);
1314
1315         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1316                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1317                      pci_dev->id.device_id);
1318
1319         rte_intr_callback_register(intr_handle,
1320                                    ixgbe_dev_interrupt_handler, eth_dev);
1321
1322         /* enable uio/vfio intr/eventfd mapping */
1323         rte_intr_enable(intr_handle);
1324
1325         /* enable support intr */
1326         ixgbe_enable_intr(eth_dev);
1327
1328         /* initialize filter info */
1329         memset(filter_info, 0,
1330                sizeof(struct ixgbe_filter_info));
1331
1332         /* initialize 5tuple filter list */
1333         TAILQ_INIT(&filter_info->fivetuple_list);
1334
1335         /* initialize flow director filter list & hash */
1336         ixgbe_fdir_filter_init(eth_dev);
1337
1338         /* initialize l2 tunnel filter list & hash */
1339         ixgbe_l2_tn_filter_init(eth_dev);
1340
1341         TAILQ_INIT(&filter_ntuple_list);
1342         TAILQ_INIT(&filter_ethertype_list);
1343         TAILQ_INIT(&filter_syn_list);
1344         TAILQ_INIT(&filter_fdir_list);
1345         TAILQ_INIT(&filter_l2_tunnel_list);
1346         TAILQ_INIT(&ixgbe_flow_list);
1347
1348         /* initialize bandwidth configuration info */
1349         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1350
1351         return 0;
1352 }
1353
1354 static int
1355 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1356 {
1357         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1358         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1359         struct ixgbe_hw *hw;
1360
1361         PMD_INIT_FUNC_TRACE();
1362
1363         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1364                 return -EPERM;
1365
1366         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1367
1368         if (hw->adapter_stopped == 0)
1369                 ixgbe_dev_close(eth_dev);
1370
1371         eth_dev->dev_ops = NULL;
1372         eth_dev->rx_pkt_burst = NULL;
1373         eth_dev->tx_pkt_burst = NULL;
1374
1375         /* Unlock any pending hardware semaphore */
1376         ixgbe_swfw_lock_reset(hw);
1377
1378         /* disable uio intr before callback unregister */
1379         rte_intr_disable(intr_handle);
1380         rte_intr_callback_unregister(intr_handle,
1381                                      ixgbe_dev_interrupt_handler, eth_dev);
1382
1383         /* uninitialize PF if max_vfs not zero */
1384         ixgbe_pf_host_uninit(eth_dev);
1385
1386         rte_free(eth_dev->data->mac_addrs);
1387         eth_dev->data->mac_addrs = NULL;
1388
1389         rte_free(eth_dev->data->hash_mac_addrs);
1390         eth_dev->data->hash_mac_addrs = NULL;
1391
1392         /* remove all the fdir filters & hash */
1393         ixgbe_fdir_filter_uninit(eth_dev);
1394
1395         /* remove all the L2 tunnel filters & hash */
1396         ixgbe_l2_tn_filter_uninit(eth_dev);
1397
1398         /* Remove all ntuple filters of the device */
1399         ixgbe_ntuple_filter_uninit(eth_dev);
1400
1401         /* clear all the filters list */
1402         ixgbe_filterlist_flush();
1403
1404         return 0;
1405 }
1406
1407 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1408 {
1409         struct ixgbe_filter_info *filter_info =
1410                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1411         struct ixgbe_5tuple_filter *p_5tuple;
1412
1413         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1414                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1415                              p_5tuple,
1416                              entries);
1417                 rte_free(p_5tuple);
1418         }
1419         memset(filter_info->fivetuple_mask, 0,
1420                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1421
1422         return 0;
1423 }
1424
1425 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1426 {
1427         struct ixgbe_hw_fdir_info *fdir_info =
1428                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1429         struct ixgbe_fdir_filter *fdir_filter;
1430
1431                 if (fdir_info->hash_map)
1432                 rte_free(fdir_info->hash_map);
1433         if (fdir_info->hash_handle)
1434                 rte_hash_free(fdir_info->hash_handle);
1435
1436         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1437                 TAILQ_REMOVE(&fdir_info->fdir_list,
1438                              fdir_filter,
1439                              entries);
1440                 rte_free(fdir_filter);
1441         }
1442
1443         return 0;
1444 }
1445
1446 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1447 {
1448         struct ixgbe_l2_tn_info *l2_tn_info =
1449                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1450         struct ixgbe_l2_tn_filter *l2_tn_filter;
1451
1452         if (l2_tn_info->hash_map)
1453                 rte_free(l2_tn_info->hash_map);
1454         if (l2_tn_info->hash_handle)
1455                 rte_hash_free(l2_tn_info->hash_handle);
1456
1457         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1458                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1459                              l2_tn_filter,
1460                              entries);
1461                 rte_free(l2_tn_filter);
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1468 {
1469         struct ixgbe_hw_fdir_info *fdir_info =
1470                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1471         char fdir_hash_name[RTE_HASH_NAMESIZE];
1472         struct rte_hash_parameters fdir_hash_params = {
1473                 .name = fdir_hash_name,
1474                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1475                 .key_len = sizeof(union ixgbe_atr_input),
1476                 .hash_func = rte_hash_crc,
1477                 .hash_func_init_val = 0,
1478                 .socket_id = rte_socket_id(),
1479         };
1480
1481         TAILQ_INIT(&fdir_info->fdir_list);
1482         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1483                  "fdir_%s", eth_dev->data->name);
1484         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1485         if (!fdir_info->hash_handle) {
1486                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1487                 return -EINVAL;
1488         }
1489         fdir_info->hash_map = rte_zmalloc("ixgbe",
1490                                           sizeof(struct ixgbe_fdir_filter *) *
1491                                           IXGBE_MAX_FDIR_FILTER_NUM,
1492                                           0);
1493         if (!fdir_info->hash_map) {
1494                 PMD_INIT_LOG(ERR,
1495                              "Failed to allocate memory for fdir hash map!");
1496                 return -ENOMEM;
1497         }
1498         fdir_info->mask_added = FALSE;
1499
1500         return 0;
1501 }
1502
1503 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1504 {
1505         struct ixgbe_l2_tn_info *l2_tn_info =
1506                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1507         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1508         struct rte_hash_parameters l2_tn_hash_params = {
1509                 .name = l2_tn_hash_name,
1510                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1511                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1512                 .hash_func = rte_hash_crc,
1513                 .hash_func_init_val = 0,
1514                 .socket_id = rte_socket_id(),
1515         };
1516
1517         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1518         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1519                  "l2_tn_%s", eth_dev->data->name);
1520         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1521         if (!l2_tn_info->hash_handle) {
1522                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1523                 return -EINVAL;
1524         }
1525         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1526                                    sizeof(struct ixgbe_l2_tn_filter *) *
1527                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1528                                    0);
1529         if (!l2_tn_info->hash_map) {
1530                 PMD_INIT_LOG(ERR,
1531                         "Failed to allocate memory for L2 TN hash map!");
1532                 return -ENOMEM;
1533         }
1534         l2_tn_info->e_tag_en = FALSE;
1535         l2_tn_info->e_tag_fwd_en = FALSE;
1536         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1537
1538         return 0;
1539 }
1540 /*
1541  * Negotiate mailbox API version with the PF.
1542  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1543  * Then we try to negotiate starting with the most recent one.
1544  * If all negotiation attempts fail, then we will proceed with
1545  * the default one (ixgbe_mbox_api_10).
1546  */
1547 static void
1548 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1549 {
1550         int32_t i;
1551
1552         /* start with highest supported, proceed down */
1553         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1554                 ixgbe_mbox_api_12,
1555                 ixgbe_mbox_api_11,
1556                 ixgbe_mbox_api_10,
1557         };
1558
1559         for (i = 0;
1560                         i != RTE_DIM(sup_ver) &&
1561                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1562                         i++)
1563                 ;
1564 }
1565
1566 static void
1567 generate_random_mac_addr(struct ether_addr *mac_addr)
1568 {
1569         uint64_t random;
1570
1571         /* Set Organizationally Unique Identifier (OUI) prefix. */
1572         mac_addr->addr_bytes[0] = 0x00;
1573         mac_addr->addr_bytes[1] = 0x09;
1574         mac_addr->addr_bytes[2] = 0xC0;
1575         /* Force indication of locally assigned MAC address. */
1576         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1577         /* Generate the last 3 bytes of the MAC address with a random number. */
1578         random = rte_rand();
1579         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1580 }
1581
1582 /*
1583  * Virtual Function device init
1584  */
1585 static int
1586 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1587 {
1588         int diag;
1589         uint32_t tc, tcs;
1590         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1591         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1592         struct ixgbe_hw *hw =
1593                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1594         struct ixgbe_vfta *shadow_vfta =
1595                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1596         struct ixgbe_hwstrip *hwstrip =
1597                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1598         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1599
1600         PMD_INIT_FUNC_TRACE();
1601
1602         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1603         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1604         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1605
1606         /* for secondary processes, we don't initialise any further as primary
1607          * has already done this work. Only check we don't need a different
1608          * RX function
1609          */
1610         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1611                 struct ixgbe_tx_queue *txq;
1612                 /* TX queue function in primary, set by last queue initialized
1613                  * Tx queue may not initialized by primary process
1614                  */
1615                 if (eth_dev->data->tx_queues) {
1616                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1617                         ixgbe_set_tx_function(eth_dev, txq);
1618                 } else {
1619                         /* Use default TX function if we get here */
1620                         PMD_INIT_LOG(NOTICE,
1621                                      "No TX queues configured yet. Using default TX function.");
1622                 }
1623
1624                 ixgbe_set_rx_function(eth_dev);
1625
1626                 return 0;
1627         }
1628
1629         rte_eth_copy_pci_info(eth_dev, pci_dev);
1630         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1631
1632         hw->device_id = pci_dev->id.device_id;
1633         hw->vendor_id = pci_dev->id.vendor_id;
1634         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1635
1636         /* initialize the vfta */
1637         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1638
1639         /* initialize the hw strip bitmap*/
1640         memset(hwstrip, 0, sizeof(*hwstrip));
1641
1642         /* Initialize the shared code (base driver) */
1643         diag = ixgbe_init_shared_code(hw);
1644         if (diag != IXGBE_SUCCESS) {
1645                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1646                 return -EIO;
1647         }
1648
1649         /* init_mailbox_params */
1650         hw->mbx.ops.init_params(hw);
1651
1652         /* Reset the hw statistics */
1653         ixgbevf_dev_stats_reset(eth_dev);
1654
1655         /* Disable the interrupts for VF */
1656         ixgbevf_intr_disable(hw);
1657
1658         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1659         diag = hw->mac.ops.reset_hw(hw);
1660
1661         /*
1662          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1663          * the underlying PF driver has not assigned a MAC address to the VF.
1664          * In this case, assign a random MAC address.
1665          */
1666         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1667                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1668                 return diag;
1669         }
1670
1671         /* negotiate mailbox API version to use with the PF. */
1672         ixgbevf_negotiate_api(hw);
1673
1674         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1675         ixgbevf_get_queues(hw, &tcs, &tc);
1676
1677         /* Allocate memory for storing MAC addresses */
1678         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1679                                                hw->mac.num_rar_entries, 0);
1680         if (eth_dev->data->mac_addrs == NULL) {
1681                 PMD_INIT_LOG(ERR,
1682                              "Failed to allocate %u bytes needed to store "
1683                              "MAC addresses",
1684                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1685                 return -ENOMEM;
1686         }
1687
1688         /* Generate a random MAC address, if none was assigned by PF. */
1689         if (is_zero_ether_addr(perm_addr)) {
1690                 generate_random_mac_addr(perm_addr);
1691                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1692                 if (diag) {
1693                         rte_free(eth_dev->data->mac_addrs);
1694                         eth_dev->data->mac_addrs = NULL;
1695                         return diag;
1696                 }
1697                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1698                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1699                              "%02x:%02x:%02x:%02x:%02x:%02x",
1700                              perm_addr->addr_bytes[0],
1701                              perm_addr->addr_bytes[1],
1702                              perm_addr->addr_bytes[2],
1703                              perm_addr->addr_bytes[3],
1704                              perm_addr->addr_bytes[4],
1705                              perm_addr->addr_bytes[5]);
1706         }
1707
1708         /* Copy the permanent MAC address */
1709         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1710
1711         /* reset the hardware with the new settings */
1712         diag = hw->mac.ops.start_hw(hw);
1713         switch (diag) {
1714         case  0:
1715                 break;
1716
1717         default:
1718                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1719                 return -EIO;
1720         }
1721
1722         rte_intr_callback_register(intr_handle,
1723                                    ixgbevf_dev_interrupt_handler, eth_dev);
1724         rte_intr_enable(intr_handle);
1725         ixgbevf_intr_enable(hw);
1726
1727         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1728                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1729                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1730
1731         return 0;
1732 }
1733
1734 /* Virtual Function device uninit */
1735
1736 static int
1737 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1738 {
1739         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1740         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1741         struct ixgbe_hw *hw;
1742
1743         PMD_INIT_FUNC_TRACE();
1744
1745         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1746                 return -EPERM;
1747
1748         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1749
1750         if (hw->adapter_stopped == 0)
1751                 ixgbevf_dev_close(eth_dev);
1752
1753         eth_dev->dev_ops = NULL;
1754         eth_dev->rx_pkt_burst = NULL;
1755         eth_dev->tx_pkt_burst = NULL;
1756
1757         /* Disable the interrupts for VF */
1758         ixgbevf_intr_disable(hw);
1759
1760         rte_free(eth_dev->data->mac_addrs);
1761         eth_dev->data->mac_addrs = NULL;
1762
1763         rte_intr_disable(intr_handle);
1764         rte_intr_callback_unregister(intr_handle,
1765                                      ixgbevf_dev_interrupt_handler, eth_dev);
1766
1767         return 0;
1768 }
1769
1770 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1771         struct rte_pci_device *pci_dev)
1772 {
1773         return rte_eth_dev_pci_generic_probe(pci_dev,
1774                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1775 }
1776
1777 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1778 {
1779         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1780 }
1781
1782 static struct rte_pci_driver rte_ixgbe_pmd = {
1783         .id_table = pci_id_ixgbe_map,
1784         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1785         .probe = eth_ixgbe_pci_probe,
1786         .remove = eth_ixgbe_pci_remove,
1787 };
1788
1789 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1790         struct rte_pci_device *pci_dev)
1791 {
1792         return rte_eth_dev_pci_generic_probe(pci_dev,
1793                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1794 }
1795
1796 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1797 {
1798         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1799 }
1800
1801 /*
1802  * virtual function driver struct
1803  */
1804 static struct rte_pci_driver rte_ixgbevf_pmd = {
1805         .id_table = pci_id_ixgbevf_map,
1806         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1807         .probe = eth_ixgbevf_pci_probe,
1808         .remove = eth_ixgbevf_pci_remove,
1809 };
1810
1811 static int
1812 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1813 {
1814         struct ixgbe_hw *hw =
1815                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1816         struct ixgbe_vfta *shadow_vfta =
1817                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1818         uint32_t vfta;
1819         uint32_t vid_idx;
1820         uint32_t vid_bit;
1821
1822         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1823         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1824         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1825         if (on)
1826                 vfta |= vid_bit;
1827         else
1828                 vfta &= ~vid_bit;
1829         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1830
1831         /* update local VFTA copy */
1832         shadow_vfta->vfta[vid_idx] = vfta;
1833
1834         return 0;
1835 }
1836
1837 static void
1838 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1839 {
1840         if (on)
1841                 ixgbe_vlan_hw_strip_enable(dev, queue);
1842         else
1843                 ixgbe_vlan_hw_strip_disable(dev, queue);
1844 }
1845
1846 static int
1847 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1848                     enum rte_vlan_type vlan_type,
1849                     uint16_t tpid)
1850 {
1851         struct ixgbe_hw *hw =
1852                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853         int ret = 0;
1854         uint32_t reg;
1855         uint32_t qinq;
1856
1857         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1858         qinq &= IXGBE_DMATXCTL_GDV;
1859
1860         switch (vlan_type) {
1861         case ETH_VLAN_TYPE_INNER:
1862                 if (qinq) {
1863                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1864                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1865                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1866                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1867                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1868                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1869                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1870                 } else {
1871                         ret = -ENOTSUP;
1872                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1873                                     " by single VLAN");
1874                 }
1875                 break;
1876         case ETH_VLAN_TYPE_OUTER:
1877                 if (qinq) {
1878                         /* Only the high 16-bits is valid */
1879                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1880                                         IXGBE_EXVET_VET_EXT_SHIFT);
1881                 } else {
1882                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1883                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1884                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1885                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1886                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1887                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1888                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1889                 }
1890
1891                 break;
1892         default:
1893                 ret = -EINVAL;
1894                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1895                 break;
1896         }
1897
1898         return ret;
1899 }
1900
1901 void
1902 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1903 {
1904         struct ixgbe_hw *hw =
1905                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1906         uint32_t vlnctrl;
1907
1908         PMD_INIT_FUNC_TRACE();
1909
1910         /* Filter Table Disable */
1911         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1912         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1913
1914         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1915 }
1916
1917 void
1918 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1919 {
1920         struct ixgbe_hw *hw =
1921                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         struct ixgbe_vfta *shadow_vfta =
1923                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1924         uint32_t vlnctrl;
1925         uint16_t i;
1926
1927         PMD_INIT_FUNC_TRACE();
1928
1929         /* Filter Table Enable */
1930         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1931         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1932         vlnctrl |= IXGBE_VLNCTRL_VFE;
1933
1934         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1935
1936         /* write whatever is in local vfta copy */
1937         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1938                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1939 }
1940
1941 static void
1942 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1943 {
1944         struct ixgbe_hwstrip *hwstrip =
1945                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1946         struct ixgbe_rx_queue *rxq;
1947
1948         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1949                 return;
1950
1951         if (on)
1952                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1953         else
1954                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1955
1956         if (queue >= dev->data->nb_rx_queues)
1957                 return;
1958
1959         rxq = dev->data->rx_queues[queue];
1960
1961         if (on)
1962                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1963         else
1964                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1965 }
1966
1967 static void
1968 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1969 {
1970         struct ixgbe_hw *hw =
1971                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1972         uint32_t ctrl;
1973
1974         PMD_INIT_FUNC_TRACE();
1975
1976         if (hw->mac.type == ixgbe_mac_82598EB) {
1977                 /* No queue level support */
1978                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1979                 return;
1980         }
1981
1982         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1983         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1984         ctrl &= ~IXGBE_RXDCTL_VME;
1985         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1986
1987         /* record those setting for HW strip per queue */
1988         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1989 }
1990
1991 static void
1992 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1993 {
1994         struct ixgbe_hw *hw =
1995                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1996         uint32_t ctrl;
1997
1998         PMD_INIT_FUNC_TRACE();
1999
2000         if (hw->mac.type == ixgbe_mac_82598EB) {
2001                 /* No queue level supported */
2002                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2003                 return;
2004         }
2005
2006         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2007         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2008         ctrl |= IXGBE_RXDCTL_VME;
2009         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2010
2011         /* record those setting for HW strip per queue */
2012         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2013 }
2014
2015 void
2016 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2017 {
2018         struct ixgbe_hw *hw =
2019                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2020         uint32_t ctrl;
2021         uint16_t i;
2022         struct ixgbe_rx_queue *rxq;
2023
2024         PMD_INIT_FUNC_TRACE();
2025
2026         if (hw->mac.type == ixgbe_mac_82598EB) {
2027                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2028                 ctrl &= ~IXGBE_VLNCTRL_VME;
2029                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2030         } else {
2031                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2032                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2033                         rxq = dev->data->rx_queues[i];
2034                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2035                         ctrl &= ~IXGBE_RXDCTL_VME;
2036                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2037
2038                         /* record those setting for HW strip per queue */
2039                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2040                 }
2041         }
2042 }
2043
2044 void
2045 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2046 {
2047         struct ixgbe_hw *hw =
2048                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2049         uint32_t ctrl;
2050         uint16_t i;
2051         struct ixgbe_rx_queue *rxq;
2052
2053         PMD_INIT_FUNC_TRACE();
2054
2055         if (hw->mac.type == ixgbe_mac_82598EB) {
2056                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2057                 ctrl |= IXGBE_VLNCTRL_VME;
2058                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2059         } else {
2060                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2061                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2062                         rxq = dev->data->rx_queues[i];
2063                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2064                         ctrl |= IXGBE_RXDCTL_VME;
2065                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2066
2067                         /* record those setting for HW strip per queue */
2068                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2069                 }
2070         }
2071 }
2072
2073 static void
2074 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2075 {
2076         struct ixgbe_hw *hw =
2077                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2078         uint32_t ctrl;
2079
2080         PMD_INIT_FUNC_TRACE();
2081
2082         /* DMATXCTRL: Geric Double VLAN Disable */
2083         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2084         ctrl &= ~IXGBE_DMATXCTL_GDV;
2085         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2086
2087         /* CTRL_EXT: Global Double VLAN Disable */
2088         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2089         ctrl &= ~IXGBE_EXTENDED_VLAN;
2090         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2091
2092 }
2093
2094 static void
2095 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2096 {
2097         struct ixgbe_hw *hw =
2098                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099         uint32_t ctrl;
2100
2101         PMD_INIT_FUNC_TRACE();
2102
2103         /* DMATXCTRL: Geric Double VLAN Enable */
2104         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2105         ctrl |= IXGBE_DMATXCTL_GDV;
2106         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2107
2108         /* CTRL_EXT: Global Double VLAN Enable */
2109         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2110         ctrl |= IXGBE_EXTENDED_VLAN;
2111         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2112
2113         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2114         if (hw->mac.type == ixgbe_mac_X550 ||
2115             hw->mac.type == ixgbe_mac_X550EM_x ||
2116             hw->mac.type == ixgbe_mac_X550EM_a) {
2117                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2118                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2119                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2120         }
2121
2122         /*
2123          * VET EXT field in the EXVET register = 0x8100 by default
2124          * So no need to change. Same to VT field of DMATXCTL register
2125          */
2126 }
2127
2128 static void
2129 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2130 {
2131         if (mask & ETH_VLAN_STRIP_MASK) {
2132                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2133                         ixgbe_vlan_hw_strip_enable_all(dev);
2134                 else
2135                         ixgbe_vlan_hw_strip_disable_all(dev);
2136         }
2137
2138         if (mask & ETH_VLAN_FILTER_MASK) {
2139                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2140                         ixgbe_vlan_hw_filter_enable(dev);
2141                 else
2142                         ixgbe_vlan_hw_filter_disable(dev);
2143         }
2144
2145         if (mask & ETH_VLAN_EXTEND_MASK) {
2146                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2147                         ixgbe_vlan_hw_extend_enable(dev);
2148                 else
2149                         ixgbe_vlan_hw_extend_disable(dev);
2150         }
2151 }
2152
2153 static void
2154 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2155 {
2156         struct ixgbe_hw *hw =
2157                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2158         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2159         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2160
2161         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2162         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2163 }
2164
2165 static int
2166 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2167 {
2168         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2169
2170         switch (nb_rx_q) {
2171         case 1:
2172         case 2:
2173                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2174                 break;
2175         case 4:
2176                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2177                 break;
2178         default:
2179                 return -EINVAL;
2180         }
2181
2182         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2183         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2184
2185         return 0;
2186 }
2187
2188 static int
2189 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2190 {
2191         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2192         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2193         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2194         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2195
2196         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2197                 /* check multi-queue mode */
2198                 switch (dev_conf->rxmode.mq_mode) {
2199                 case ETH_MQ_RX_VMDQ_DCB:
2200                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2201                         break;
2202                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2203                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2204                         PMD_INIT_LOG(ERR, "SRIOV active,"
2205                                         " unsupported mq_mode rx %d.",
2206                                         dev_conf->rxmode.mq_mode);
2207                         return -EINVAL;
2208                 case ETH_MQ_RX_RSS:
2209                 case ETH_MQ_RX_VMDQ_RSS:
2210                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2211                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2212                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2213                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2214                                                 " invalid queue number"
2215                                                 " for VMDQ RSS, allowed"
2216                                                 " value are 1, 2 or 4.");
2217                                         return -EINVAL;
2218                                 }
2219                         break;
2220                 case ETH_MQ_RX_VMDQ_ONLY:
2221                 case ETH_MQ_RX_NONE:
2222                         /* if nothing mq mode configure, use default scheme */
2223                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2224                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2225                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2226                         break;
2227                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2228                         /* SRIOV only works in VMDq enable mode */
2229                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2230                                         " wrong mq_mode rx %d.",
2231                                         dev_conf->rxmode.mq_mode);
2232                         return -EINVAL;
2233                 }
2234
2235                 switch (dev_conf->txmode.mq_mode) {
2236                 case ETH_MQ_TX_VMDQ_DCB:
2237                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2238                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2239                         break;
2240                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2241                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2242                         break;
2243                 }
2244
2245                 /* check valid queue number */
2246                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2247                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2248                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2249                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2250                                         " must be less than or equal to %d.",
2251                                         nb_rx_q, nb_tx_q,
2252                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2253                         return -EINVAL;
2254                 }
2255         } else {
2256                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2257                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2258                                           " not supported.");
2259                         return -EINVAL;
2260                 }
2261                 /* check configuration for vmdb+dcb mode */
2262                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2263                         const struct rte_eth_vmdq_dcb_conf *conf;
2264
2265                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2266                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2267                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2268                                 return -EINVAL;
2269                         }
2270                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2271                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2272                                conf->nb_queue_pools == ETH_32_POOLS)) {
2273                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2274                                                 " nb_queue_pools must be %d or %d.",
2275                                                 ETH_16_POOLS, ETH_32_POOLS);
2276                                 return -EINVAL;
2277                         }
2278                 }
2279                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2280                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2281
2282                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2283                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2284                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2285                                 return -EINVAL;
2286                         }
2287                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2288                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2289                                conf->nb_queue_pools == ETH_32_POOLS)) {
2290                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2291                                                 " nb_queue_pools != %d and"
2292                                                 " nb_queue_pools != %d.",
2293                                                 ETH_16_POOLS, ETH_32_POOLS);
2294                                 return -EINVAL;
2295                         }
2296                 }
2297
2298                 /* For DCB mode check our configuration before we go further */
2299                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2300                         const struct rte_eth_dcb_rx_conf *conf;
2301
2302                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2303                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2304                                                  IXGBE_DCB_NB_QUEUES);
2305                                 return -EINVAL;
2306                         }
2307                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2308                         if (!(conf->nb_tcs == ETH_4_TCS ||
2309                                conf->nb_tcs == ETH_8_TCS)) {
2310                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2311                                                 " and nb_tcs != %d.",
2312                                                 ETH_4_TCS, ETH_8_TCS);
2313                                 return -EINVAL;
2314                         }
2315                 }
2316
2317                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2318                         const struct rte_eth_dcb_tx_conf *conf;
2319
2320                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2321                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2322                                                  IXGBE_DCB_NB_QUEUES);
2323                                 return -EINVAL;
2324                         }
2325                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2326                         if (!(conf->nb_tcs == ETH_4_TCS ||
2327                                conf->nb_tcs == ETH_8_TCS)) {
2328                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2329                                                 " and nb_tcs != %d.",
2330                                                 ETH_4_TCS, ETH_8_TCS);
2331                                 return -EINVAL;
2332                         }
2333                 }
2334
2335                 /*
2336                  * When DCB/VT is off, maximum number of queues changes,
2337                  * except for 82598EB, which remains constant.
2338                  */
2339                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2340                                 hw->mac.type != ixgbe_mac_82598EB) {
2341                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2342                                 PMD_INIT_LOG(ERR,
2343                                              "Neither VT nor DCB are enabled, "
2344                                              "nb_tx_q > %d.",
2345                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2346                                 return -EINVAL;
2347                         }
2348                 }
2349         }
2350         return 0;
2351 }
2352
2353 static int
2354 ixgbe_dev_configure(struct rte_eth_dev *dev)
2355 {
2356         struct ixgbe_interrupt *intr =
2357                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2358         struct ixgbe_adapter *adapter =
2359                 (struct ixgbe_adapter *)dev->data->dev_private;
2360         int ret;
2361
2362         PMD_INIT_FUNC_TRACE();
2363         /* multipe queue mode checking */
2364         ret  = ixgbe_check_mq_mode(dev);
2365         if (ret != 0) {
2366                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2367                             ret);
2368                 return ret;
2369         }
2370
2371         /* set flag to update link status after init */
2372         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2373
2374         /*
2375          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2376          * allocation or vector Rx preconditions we will reset it.
2377          */
2378         adapter->rx_bulk_alloc_allowed = true;
2379         adapter->rx_vec_allowed = true;
2380
2381         return 0;
2382 }
2383
2384 static void
2385 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2386 {
2387         struct ixgbe_hw *hw =
2388                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389         struct ixgbe_interrupt *intr =
2390                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2391         uint32_t gpie;
2392
2393         /* only set up it on X550EM_X */
2394         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2395                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2396                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2397                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2398                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2399                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2400         }
2401 }
2402
2403 int
2404 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2405                         uint16_t tx_rate, uint64_t q_msk)
2406 {
2407         struct ixgbe_hw *hw;
2408         struct ixgbe_vf_info *vfinfo;
2409         struct rte_eth_link link;
2410         uint8_t  nb_q_per_pool;
2411         uint32_t queue_stride;
2412         uint32_t queue_idx, idx = 0, vf_idx;
2413         uint32_t queue_end;
2414         uint16_t total_rate = 0;
2415         struct rte_pci_device *pci_dev;
2416
2417         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2418         rte_eth_link_get_nowait(dev->data->port_id, &link);
2419
2420         if (vf >= pci_dev->max_vfs)
2421                 return -EINVAL;
2422
2423         if (tx_rate > link.link_speed)
2424                 return -EINVAL;
2425
2426         if (q_msk == 0)
2427                 return 0;
2428
2429         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2430         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2431         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2432         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2433         queue_idx = vf * queue_stride;
2434         queue_end = queue_idx + nb_q_per_pool - 1;
2435         if (queue_end >= hw->mac.max_tx_queues)
2436                 return -EINVAL;
2437
2438         if (vfinfo) {
2439                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2440                         if (vf_idx == vf)
2441                                 continue;
2442                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2443                                 idx++)
2444                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2445                 }
2446         } else {
2447                 return -EINVAL;
2448         }
2449
2450         /* Store tx_rate for this vf. */
2451         for (idx = 0; idx < nb_q_per_pool; idx++) {
2452                 if (((uint64_t)0x1 << idx) & q_msk) {
2453                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2454                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2455                         total_rate += tx_rate;
2456                 }
2457         }
2458
2459         if (total_rate > dev->data->dev_link.link_speed) {
2460                 /* Reset stored TX rate of the VF if it causes exceed
2461                  * link speed.
2462                  */
2463                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2464                 return -EINVAL;
2465         }
2466
2467         /* Set RTTBCNRC of each queue/pool for vf X  */
2468         for (; queue_idx <= queue_end; queue_idx++) {
2469                 if (0x1 & q_msk)
2470                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2471                 q_msk = q_msk >> 1;
2472         }
2473
2474         return 0;
2475 }
2476
2477 /*
2478  * Configure device link speed and setup link.
2479  * It returns 0 on success.
2480  */
2481 static int
2482 ixgbe_dev_start(struct rte_eth_dev *dev)
2483 {
2484         struct ixgbe_hw *hw =
2485                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486         struct ixgbe_vf_info *vfinfo =
2487                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2488         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2489         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2490         uint32_t intr_vector = 0;
2491         int err, link_up = 0, negotiate = 0;
2492         uint32_t speed = 0;
2493         int mask = 0;
2494         int status;
2495         uint16_t vf, idx;
2496         uint32_t *link_speeds;
2497
2498         PMD_INIT_FUNC_TRACE();
2499
2500         /* IXGBE devices don't support:
2501         *    - half duplex (checked afterwards for valid speeds)
2502         *    - fixed speed: TODO implement
2503         */
2504         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2505                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2506                              dev->data->port_id);
2507                 return -EINVAL;
2508         }
2509
2510         /* disable uio/vfio intr/eventfd mapping */
2511         rte_intr_disable(intr_handle);
2512
2513         /* stop adapter */
2514         hw->adapter_stopped = 0;
2515         ixgbe_stop_adapter(hw);
2516
2517         /* reinitialize adapter
2518          * this calls reset and start
2519          */
2520         status = ixgbe_pf_reset_hw(hw);
2521         if (status != 0)
2522                 return -1;
2523         hw->mac.ops.start_hw(hw);
2524         hw->mac.get_link_status = true;
2525
2526         /* configure PF module if SRIOV enabled */
2527         ixgbe_pf_host_configure(dev);
2528
2529         ixgbe_dev_phy_intr_setup(dev);
2530
2531         /* check and configure queue intr-vector mapping */
2532         if ((rte_intr_cap_multiple(intr_handle) ||
2533              !RTE_ETH_DEV_SRIOV(dev).active) &&
2534             dev->data->dev_conf.intr_conf.rxq != 0) {
2535                 intr_vector = dev->data->nb_rx_queues;
2536                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2537                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2538                                         IXGBE_MAX_INTR_QUEUE_NUM);
2539                         return -ENOTSUP;
2540                 }
2541                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2542                         return -1;
2543         }
2544
2545         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2546                 intr_handle->intr_vec =
2547                         rte_zmalloc("intr_vec",
2548                                     dev->data->nb_rx_queues * sizeof(int), 0);
2549                 if (intr_handle->intr_vec == NULL) {
2550                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2551                                      " intr_vec", dev->data->nb_rx_queues);
2552                         return -ENOMEM;
2553                 }
2554         }
2555
2556         /* confiugre msix for sleep until rx interrupt */
2557         ixgbe_configure_msix(dev);
2558
2559         /* initialize transmission unit */
2560         ixgbe_dev_tx_init(dev);
2561
2562         /* This can fail when allocating mbufs for descriptor rings */
2563         err = ixgbe_dev_rx_init(dev);
2564         if (err) {
2565                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2566                 goto error;
2567         }
2568
2569     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2570                 ETH_VLAN_EXTEND_MASK;
2571         ixgbe_vlan_offload_set(dev, mask);
2572
2573         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2574                 /* Enable vlan filtering for VMDq */
2575                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2576         }
2577
2578         /* Configure DCB hw */
2579         ixgbe_configure_dcb(dev);
2580
2581         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2582                 err = ixgbe_fdir_configure(dev);
2583                 if (err)
2584                         goto error;
2585         }
2586
2587         /* Restore vf rate limit */
2588         if (vfinfo != NULL) {
2589                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2590                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2591                                 if (vfinfo[vf].tx_rate[idx] != 0)
2592                                         ixgbe_set_vf_rate_limit(
2593                                                 dev, vf,
2594                                                 vfinfo[vf].tx_rate[idx],
2595                                                 1 << idx);
2596         }
2597
2598         ixgbe_restore_statistics_mapping(dev);
2599
2600         err = ixgbe_dev_rxtx_start(dev);
2601         if (err < 0) {
2602                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2603                 goto error;
2604         }
2605
2606         /* Skip link setup if loopback mode is enabled for 82599. */
2607         if (hw->mac.type == ixgbe_mac_82599EB &&
2608                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2609                 goto skip_link_setup;
2610
2611         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2612                 err = hw->mac.ops.setup_sfp(hw);
2613                 if (err)
2614                         goto error;
2615         }
2616
2617         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2618                 /* Turn on the copper */
2619                 ixgbe_set_phy_power(hw, true);
2620         } else {
2621                 /* Turn on the laser */
2622                 ixgbe_enable_tx_laser(hw);
2623         }
2624
2625         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2626         if (err)
2627                 goto error;
2628         dev->data->dev_link.link_status = link_up;
2629
2630         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2631         if (err)
2632                 goto error;
2633
2634         link_speeds = &dev->data->dev_conf.link_speeds;
2635         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2636                         ETH_LINK_SPEED_10G)) {
2637                 PMD_INIT_LOG(ERR, "Invalid link setting");
2638                 goto error;
2639         }
2640
2641         speed = 0x0;
2642         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2643                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2644                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2645                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2646         } else {
2647                 if (*link_speeds & ETH_LINK_SPEED_10G)
2648                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2649                 if (*link_speeds & ETH_LINK_SPEED_1G)
2650                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2651                 if (*link_speeds & ETH_LINK_SPEED_100M)
2652                         speed |= IXGBE_LINK_SPEED_100_FULL;
2653         }
2654
2655         err = ixgbe_setup_link(hw, speed, link_up);
2656         if (err)
2657                 goto error;
2658
2659 skip_link_setup:
2660
2661         if (rte_intr_allow_others(intr_handle)) {
2662                 /* check if lsc interrupt is enabled */
2663                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2664                         ixgbe_dev_lsc_interrupt_setup(dev);
2665                 ixgbe_dev_macsec_interrupt_setup(dev);
2666         } else {
2667                 rte_intr_callback_unregister(intr_handle,
2668                                              ixgbe_dev_interrupt_handler, dev);
2669                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2670                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2671                                      " no intr multiplex");
2672         }
2673
2674         /* check if rxq interrupt is enabled */
2675         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2676             rte_intr_dp_is_en(intr_handle))
2677                 ixgbe_dev_rxq_interrupt_setup(dev);
2678
2679         /* enable uio/vfio intr/eventfd mapping */
2680         rte_intr_enable(intr_handle);
2681
2682         /* resume enabled intr since hw reset */
2683         ixgbe_enable_intr(dev);
2684         ixgbe_l2_tunnel_conf(dev);
2685         ixgbe_filter_restore(dev);
2686
2687         return 0;
2688
2689 error:
2690         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2691         ixgbe_dev_clear_queues(dev);
2692         return -EIO;
2693 }
2694
2695 /*
2696  * Stop device: disable rx and tx functions to allow for reconfiguring.
2697  */
2698 static void
2699 ixgbe_dev_stop(struct rte_eth_dev *dev)
2700 {
2701         struct rte_eth_link link;
2702         struct ixgbe_hw *hw =
2703                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2704         struct ixgbe_vf_info *vfinfo =
2705                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2706         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2707         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2708         int vf;
2709
2710         PMD_INIT_FUNC_TRACE();
2711
2712         /* disable interrupts */
2713         ixgbe_disable_intr(hw);
2714
2715         /* reset the NIC */
2716         ixgbe_pf_reset_hw(hw);
2717         hw->adapter_stopped = 0;
2718
2719         /* stop adapter */
2720         ixgbe_stop_adapter(hw);
2721
2722         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2723                 vfinfo[vf].clear_to_send = false;
2724
2725         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2726                 /* Turn off the copper */
2727                 ixgbe_set_phy_power(hw, false);
2728         } else {
2729                 /* Turn off the laser */
2730                 ixgbe_disable_tx_laser(hw);
2731         }
2732
2733         ixgbe_dev_clear_queues(dev);
2734
2735         /* Clear stored conf */
2736         dev->data->scattered_rx = 0;
2737         dev->data->lro = 0;
2738
2739         /* Clear recorded link status */
2740         memset(&link, 0, sizeof(link));
2741         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2742
2743         if (!rte_intr_allow_others(intr_handle))
2744                 /* resume to the default handler */
2745                 rte_intr_callback_register(intr_handle,
2746                                            ixgbe_dev_interrupt_handler,
2747                                            (void *)dev);
2748
2749         /* Clean datapath event and queue/vec mapping */
2750         rte_intr_efd_disable(intr_handle);
2751         if (intr_handle->intr_vec != NULL) {
2752                 rte_free(intr_handle->intr_vec);
2753                 intr_handle->intr_vec = NULL;
2754         }
2755 }
2756
2757 /*
2758  * Set device link up: enable tx.
2759  */
2760 static int
2761 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2762 {
2763         struct ixgbe_hw *hw =
2764                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2765         if (hw->mac.type == ixgbe_mac_82599EB) {
2766 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2767                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2768                         /* Not suported in bypass mode */
2769                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2770                                      "by device id 0x%x", hw->device_id);
2771                         return -ENOTSUP;
2772                 }
2773 #endif
2774         }
2775
2776         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2777                 /* Turn on the copper */
2778                 ixgbe_set_phy_power(hw, true);
2779         } else {
2780                 /* Turn on the laser */
2781                 ixgbe_enable_tx_laser(hw);
2782         }
2783
2784         return 0;
2785 }
2786
2787 /*
2788  * Set device link down: disable tx.
2789  */
2790 static int
2791 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2792 {
2793         struct ixgbe_hw *hw =
2794                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2795         if (hw->mac.type == ixgbe_mac_82599EB) {
2796 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2797                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2798                         /* Not suported in bypass mode */
2799                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2800                                      "by device id 0x%x", hw->device_id);
2801                         return -ENOTSUP;
2802                 }
2803 #endif
2804         }
2805
2806         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2807                 /* Turn off the copper */
2808                 ixgbe_set_phy_power(hw, false);
2809         } else {
2810                 /* Turn off the laser */
2811                 ixgbe_disable_tx_laser(hw);
2812         }
2813
2814         return 0;
2815 }
2816
2817 /*
2818  * Reest and stop device.
2819  */
2820 static void
2821 ixgbe_dev_close(struct rte_eth_dev *dev)
2822 {
2823         struct ixgbe_hw *hw =
2824                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2825
2826         PMD_INIT_FUNC_TRACE();
2827
2828         ixgbe_pf_reset_hw(hw);
2829
2830         ixgbe_dev_stop(dev);
2831         hw->adapter_stopped = 1;
2832
2833         ixgbe_dev_free_queues(dev);
2834
2835         ixgbe_disable_pcie_master(hw);
2836
2837         /* reprogram the RAR[0] in case user changed it. */
2838         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2839 }
2840
2841 static void
2842 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2843                            struct ixgbe_hw_stats *hw_stats,
2844                            struct ixgbe_macsec_stats *macsec_stats,
2845                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2846                            uint64_t *total_qprc, uint64_t *total_qprdc)
2847 {
2848         uint32_t bprc, lxon, lxoff, total;
2849         uint32_t delta_gprc = 0;
2850         unsigned i;
2851         /* Workaround for RX byte count not including CRC bytes when CRC
2852          * strip is enabled. CRC bytes are removed from counters when crc_strip
2853          * is disabled.
2854          */
2855         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2856                         IXGBE_HLREG0_RXCRCSTRP);
2857
2858         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2859         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2860         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2861         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2862
2863         for (i = 0; i < 8; i++) {
2864                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2865
2866                 /* global total per queue */
2867                 hw_stats->mpc[i] += mp;
2868                 /* Running comprehensive total for stats display */
2869                 *total_missed_rx += hw_stats->mpc[i];
2870                 if (hw->mac.type == ixgbe_mac_82598EB) {
2871                         hw_stats->rnbc[i] +=
2872                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2873                         hw_stats->pxonrxc[i] +=
2874                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2875                         hw_stats->pxoffrxc[i] +=
2876                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2877                 } else {
2878                         hw_stats->pxonrxc[i] +=
2879                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2880                         hw_stats->pxoffrxc[i] +=
2881                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2882                         hw_stats->pxon2offc[i] +=
2883                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2884                 }
2885                 hw_stats->pxontxc[i] +=
2886                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2887                 hw_stats->pxofftxc[i] +=
2888                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2889         }
2890         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2891                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2892                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2893                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2894
2895                 delta_gprc += delta_qprc;
2896
2897                 hw_stats->qprc[i] += delta_qprc;
2898                 hw_stats->qptc[i] += delta_qptc;
2899
2900                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2901                 hw_stats->qbrc[i] +=
2902                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2903                 if (crc_strip == 0)
2904                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2905
2906                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2907                 hw_stats->qbtc[i] +=
2908                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2909
2910                 hw_stats->qprdc[i] += delta_qprdc;
2911                 *total_qprdc += hw_stats->qprdc[i];
2912
2913                 *total_qprc += hw_stats->qprc[i];
2914                 *total_qbrc += hw_stats->qbrc[i];
2915         }
2916         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2917         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2918         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2919
2920         /*
2921          * An errata states that gprc actually counts good + missed packets:
2922          * Workaround to set gprc to summated queue packet receives
2923          */
2924         hw_stats->gprc = *total_qprc;
2925
2926         if (hw->mac.type != ixgbe_mac_82598EB) {
2927                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2928                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2929                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2930                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2931                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2932                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2933                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2934                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2935         } else {
2936                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2937                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2938                 /* 82598 only has a counter in the high register */
2939                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2940                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2941                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2942         }
2943         uint64_t old_tpr = hw_stats->tpr;
2944
2945         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2946         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2947
2948         if (crc_strip == 0)
2949                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2950
2951         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2952         hw_stats->gptc += delta_gptc;
2953         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2954         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2955
2956         /*
2957          * Workaround: mprc hardware is incorrectly counting
2958          * broadcasts, so for now we subtract those.
2959          */
2960         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2961         hw_stats->bprc += bprc;
2962         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2963         if (hw->mac.type == ixgbe_mac_82598EB)
2964                 hw_stats->mprc -= bprc;
2965
2966         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2967         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2968         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2969         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2970         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2971         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2972
2973         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2974         hw_stats->lxontxc += lxon;
2975         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2976         hw_stats->lxofftxc += lxoff;
2977         total = lxon + lxoff;
2978
2979         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2980         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2981         hw_stats->gptc -= total;
2982         hw_stats->mptc -= total;
2983         hw_stats->ptc64 -= total;
2984         hw_stats->gotc -= total * ETHER_MIN_LEN;
2985
2986         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2987         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2988         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2989         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2990         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2991         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2992         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2993         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2994         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2995         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2996         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2997         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2998         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2999         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3000         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3001         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3002         /* Only read FCOE on 82599 */
3003         if (hw->mac.type != ixgbe_mac_82598EB) {
3004                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3005                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3006                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3007                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3008                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3009         }
3010
3011         /* Flow Director Stats registers */
3012         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3013         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3014
3015         /* MACsec Stats registers */
3016         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3017         macsec_stats->out_pkts_encrypted +=
3018                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3019         macsec_stats->out_pkts_protected +=
3020                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3021         macsec_stats->out_octets_encrypted +=
3022                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3023         macsec_stats->out_octets_protected +=
3024                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3025         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3026         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3027         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3028         macsec_stats->in_pkts_unknownsci +=
3029                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3030         macsec_stats->in_octets_decrypted +=
3031                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3032         macsec_stats->in_octets_validated +=
3033                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3034         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3035         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3036         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3037         for (i = 0; i < 2; i++) {
3038                 macsec_stats->in_pkts_ok +=
3039                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3040                 macsec_stats->in_pkts_invalid +=
3041                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3042                 macsec_stats->in_pkts_notvalid +=
3043                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3044         }
3045         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3046         macsec_stats->in_pkts_notusingsa +=
3047                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3048 }
3049
3050 /*
3051  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3052  */
3053 static void
3054 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3055 {
3056         struct ixgbe_hw *hw =
3057                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3058         struct ixgbe_hw_stats *hw_stats =
3059                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3060         struct ixgbe_macsec_stats *macsec_stats =
3061                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3062                                 dev->data->dev_private);
3063         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3064         unsigned i;
3065
3066         total_missed_rx = 0;
3067         total_qbrc = 0;
3068         total_qprc = 0;
3069         total_qprdc = 0;
3070
3071         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3072                         &total_qbrc, &total_qprc, &total_qprdc);
3073
3074         if (stats == NULL)
3075                 return;
3076
3077         /* Fill out the rte_eth_stats statistics structure */
3078         stats->ipackets = total_qprc;
3079         stats->ibytes = total_qbrc;
3080         stats->opackets = hw_stats->gptc;
3081         stats->obytes = hw_stats->gotc;
3082
3083         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3084                 stats->q_ipackets[i] = hw_stats->qprc[i];
3085                 stats->q_opackets[i] = hw_stats->qptc[i];
3086                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3087                 stats->q_obytes[i] = hw_stats->qbtc[i];
3088                 stats->q_errors[i] = hw_stats->qprdc[i];
3089         }
3090
3091         /* Rx Errors */
3092         stats->imissed  = total_missed_rx;
3093         stats->ierrors  = hw_stats->crcerrs +
3094                           hw_stats->mspdc +
3095                           hw_stats->rlec +
3096                           hw_stats->ruc +
3097                           hw_stats->roc +
3098                           hw_stats->illerrc +
3099                           hw_stats->errbc +
3100                           hw_stats->rfc +
3101                           hw_stats->fccrc +
3102                           hw_stats->fclast;
3103
3104         /* Tx Errors */
3105         stats->oerrors  = 0;
3106 }
3107
3108 static void
3109 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3110 {
3111         struct ixgbe_hw_stats *stats =
3112                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3113
3114         /* HW registers are cleared on read */
3115         ixgbe_dev_stats_get(dev, NULL);
3116
3117         /* Reset software totals */
3118         memset(stats, 0, sizeof(*stats));
3119 }
3120
3121 /* This function calculates the number of xstats based on the current config */
3122 static unsigned
3123 ixgbe_xstats_calc_num(void) {
3124         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3125                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3126                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3127 }
3128
3129 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3130         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3131 {
3132         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3133         unsigned stat, i, count;
3134
3135         if (xstats_names != NULL) {
3136                 count = 0;
3137
3138                 /* Note: limit >= cnt_stats checked upstream
3139                  * in rte_eth_xstats_names()
3140                  */
3141
3142                 /* Extended stats from ixgbe_hw_stats */
3143                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3144                         snprintf(xstats_names[count].name,
3145                                 sizeof(xstats_names[count].name),
3146                                 "%s",
3147                                 rte_ixgbe_stats_strings[i].name);
3148                         count++;
3149                 }
3150
3151                 /* MACsec Stats */
3152                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3153                         snprintf(xstats_names[count].name,
3154                                 sizeof(xstats_names[count].name),
3155                                 "%s",
3156                                 rte_ixgbe_macsec_strings[i].name);
3157                         count++;
3158                 }
3159
3160                 /* RX Priority Stats */
3161                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3162                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3163                                 snprintf(xstats_names[count].name,
3164                                         sizeof(xstats_names[count].name),
3165                                         "rx_priority%u_%s", i,
3166                                         rte_ixgbe_rxq_strings[stat].name);
3167                                 count++;
3168                         }
3169                 }
3170
3171                 /* TX Priority Stats */
3172                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3173                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3174                                 snprintf(xstats_names[count].name,
3175                                         sizeof(xstats_names[count].name),
3176                                         "tx_priority%u_%s", i,
3177                                         rte_ixgbe_txq_strings[stat].name);
3178                                 count++;
3179                         }
3180                 }
3181         }
3182         return cnt_stats;
3183 }
3184
3185 static int ixgbe_dev_xstats_get_names_by_id(
3186         struct rte_eth_dev *dev,
3187         struct rte_eth_xstat_name *xstats_names,
3188         const uint64_t *ids,
3189         unsigned int limit)
3190 {
3191         if (!ids) {
3192                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3193                 unsigned int stat, i, count;
3194
3195                 if (xstats_names != NULL) {
3196                         count = 0;
3197
3198                         /* Note: limit >= cnt_stats checked upstream
3199                          * in rte_eth_xstats_names()
3200                          */
3201
3202                         /* Extended stats from ixgbe_hw_stats */
3203                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3204                                 snprintf(xstats_names[count].name,
3205                                         sizeof(xstats_names[count].name),
3206                                         "%s",
3207                                         rte_ixgbe_stats_strings[i].name);
3208                                 count++;
3209                         }
3210
3211                         /* MACsec Stats */
3212                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3213                                 snprintf(xstats_names[count].name,
3214                                         sizeof(xstats_names[count].name),
3215                                         "%s",
3216                                         rte_ixgbe_macsec_strings[i].name);
3217                                 count++;
3218                         }
3219
3220                         /* RX Priority Stats */
3221                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3222                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3223                                         snprintf(xstats_names[count].name,
3224                                             sizeof(xstats_names[count].name),
3225                                             "rx_priority%u_%s", i,
3226                                             rte_ixgbe_rxq_strings[stat].name);
3227                                         count++;
3228                                 }
3229                         }
3230
3231                         /* TX Priority Stats */
3232                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3233                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3234                                         snprintf(xstats_names[count].name,
3235                                             sizeof(xstats_names[count].name),
3236                                             "tx_priority%u_%s", i,
3237                                             rte_ixgbe_txq_strings[stat].name);
3238                                         count++;
3239                                 }
3240                         }
3241                 }
3242                 return cnt_stats;
3243         }
3244
3245         uint16_t i;
3246         uint16_t size = ixgbe_xstats_calc_num();
3247         struct rte_eth_xstat_name xstats_names_copy[size];
3248
3249         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3250                         size);
3251
3252         for (i = 0; i < limit; i++) {
3253                 if (ids[i] >= size) {
3254                         PMD_INIT_LOG(ERR, "id value isn't valid");
3255                         return -1;
3256                 }
3257                 strcpy(xstats_names[i].name,
3258                                 xstats_names_copy[ids[i]].name);
3259         }
3260         return limit;
3261 }
3262
3263 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3264         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3265 {
3266         unsigned i;
3267
3268         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3269                 return -ENOMEM;
3270
3271         if (xstats_names != NULL)
3272                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3273                         snprintf(xstats_names[i].name,
3274                                 sizeof(xstats_names[i].name),
3275                                 "%s", rte_ixgbevf_stats_strings[i].name);
3276         return IXGBEVF_NB_XSTATS;
3277 }
3278
3279 static int
3280 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3281                                          unsigned n)
3282 {
3283         struct ixgbe_hw *hw =
3284                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3285         struct ixgbe_hw_stats *hw_stats =
3286                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3287         struct ixgbe_macsec_stats *macsec_stats =
3288                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3289                                 dev->data->dev_private);
3290         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3291         unsigned i, stat, count = 0;
3292
3293         count = ixgbe_xstats_calc_num();
3294
3295         if (n < count)
3296                 return count;
3297
3298         total_missed_rx = 0;
3299         total_qbrc = 0;
3300         total_qprc = 0;
3301         total_qprdc = 0;
3302
3303         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3304                         &total_qbrc, &total_qprc, &total_qprdc);
3305
3306         /* If this is a reset xstats is NULL, and we have cleared the
3307          * registers by reading them.
3308          */
3309         if (!xstats)
3310                 return 0;
3311
3312         /* Extended stats from ixgbe_hw_stats */
3313         count = 0;
3314         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3315                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3316                                 rte_ixgbe_stats_strings[i].offset);
3317                 xstats[count].id = count;
3318                 count++;
3319         }
3320
3321         /* MACsec Stats */
3322         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3323                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3324                                 rte_ixgbe_macsec_strings[i].offset);
3325                 xstats[count].id = count;
3326                 count++;
3327         }
3328
3329         /* RX Priority Stats */
3330         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3331                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3332                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3333                                         rte_ixgbe_rxq_strings[stat].offset +
3334                                         (sizeof(uint64_t) * i));
3335                         xstats[count].id = count;
3336                         count++;
3337                 }
3338         }
3339
3340         /* TX Priority Stats */
3341         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3342                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3343                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3344                                         rte_ixgbe_txq_strings[stat].offset +
3345                                         (sizeof(uint64_t) * i));
3346                         xstats[count].id = count;
3347                         count++;
3348                 }
3349         }
3350         return count;
3351 }
3352
3353 static int
3354 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3355                 uint64_t *values, unsigned int n)
3356 {
3357         if (!ids) {
3358                 struct ixgbe_hw *hw =
3359                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3360                 struct ixgbe_hw_stats *hw_stats =
3361                                 IXGBE_DEV_PRIVATE_TO_STATS(
3362                                                 dev->data->dev_private);
3363                 struct ixgbe_macsec_stats *macsec_stats =
3364                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3365                                         dev->data->dev_private);
3366                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3367                 unsigned int i, stat, count = 0;
3368
3369                 count = ixgbe_xstats_calc_num();
3370
3371                 if (!ids && n < count)
3372                         return count;
3373
3374                 total_missed_rx = 0;
3375                 total_qbrc = 0;
3376                 total_qprc = 0;
3377                 total_qprdc = 0;
3378
3379                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3380                                 &total_missed_rx, &total_qbrc, &total_qprc,
3381                                 &total_qprdc);
3382
3383                 /* If this is a reset xstats is NULL, and we have cleared the
3384                  * registers by reading them.
3385                  */
3386                 if (!ids && !values)
3387                         return 0;
3388
3389                 /* Extended stats from ixgbe_hw_stats */
3390                 count = 0;
3391                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3392                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3393                                         rte_ixgbe_stats_strings[i].offset);
3394                         count++;
3395                 }
3396
3397                 /* MACsec Stats */
3398                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3399                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3400                                         rte_ixgbe_macsec_strings[i].offset);
3401                         count++;
3402                 }
3403
3404                 /* RX Priority Stats */
3405                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3406                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3407                                 values[count] =
3408                                         *(uint64_t *)(((char *)hw_stats) +
3409                                         rte_ixgbe_rxq_strings[stat].offset +
3410                                         (sizeof(uint64_t) * i));
3411                                 count++;
3412                         }
3413                 }
3414
3415                 /* TX Priority Stats */
3416                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3417                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3418                                 values[count] =
3419                                         *(uint64_t *)(((char *)hw_stats) +
3420                                         rte_ixgbe_txq_strings[stat].offset +
3421                                         (sizeof(uint64_t) * i));
3422                                 count++;
3423                         }
3424                 }
3425                 return count;
3426         }
3427
3428         uint16_t i;
3429         uint16_t size = ixgbe_xstats_calc_num();
3430         uint64_t values_copy[size];
3431
3432         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3433
3434         for (i = 0; i < n; i++) {
3435                 if (ids[i] >= size) {
3436                         PMD_INIT_LOG(ERR, "id value isn't valid");
3437                         return -1;
3438                 }
3439                 values[i] = values_copy[ids[i]];
3440         }
3441         return n;
3442 }
3443
3444 static void
3445 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3446 {
3447         struct ixgbe_hw_stats *stats =
3448                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3449         struct ixgbe_macsec_stats *macsec_stats =
3450                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3451                                 dev->data->dev_private);
3452
3453         unsigned count = ixgbe_xstats_calc_num();
3454
3455         /* HW registers are cleared on read */
3456         ixgbe_dev_xstats_get(dev, NULL, count);
3457
3458         /* Reset software totals */
3459         memset(stats, 0, sizeof(*stats));
3460         memset(macsec_stats, 0, sizeof(*macsec_stats));
3461 }
3462
3463 static void
3464 ixgbevf_update_stats(struct rte_eth_dev *dev)
3465 {
3466         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3467         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3468                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3469
3470         /* Good Rx packet, include VF loopback */
3471         UPDATE_VF_STAT(IXGBE_VFGPRC,
3472             hw_stats->last_vfgprc, hw_stats->vfgprc);
3473
3474         /* Good Rx octets, include VF loopback */
3475         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3476             hw_stats->last_vfgorc, hw_stats->vfgorc);
3477
3478         /* Good Tx packet, include VF loopback */
3479         UPDATE_VF_STAT(IXGBE_VFGPTC,
3480             hw_stats->last_vfgptc, hw_stats->vfgptc);
3481
3482         /* Good Tx octets, include VF loopback */
3483         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3484             hw_stats->last_vfgotc, hw_stats->vfgotc);
3485
3486         /* Rx Multicst Packet */
3487         UPDATE_VF_STAT(IXGBE_VFMPRC,
3488             hw_stats->last_vfmprc, hw_stats->vfmprc);
3489 }
3490
3491 static int
3492 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3493                        unsigned n)
3494 {
3495         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3496                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3497         unsigned i;
3498
3499         if (n < IXGBEVF_NB_XSTATS)
3500                 return IXGBEVF_NB_XSTATS;
3501
3502         ixgbevf_update_stats(dev);
3503
3504         if (!xstats)
3505                 return 0;
3506
3507         /* Extended stats */
3508         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3509                 xstats[i].id = i;
3510                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3511                         rte_ixgbevf_stats_strings[i].offset);
3512         }
3513
3514         return IXGBEVF_NB_XSTATS;
3515 }
3516
3517 static void
3518 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3519 {
3520         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3521                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3522
3523         ixgbevf_update_stats(dev);
3524
3525         if (stats == NULL)
3526                 return;
3527
3528         stats->ipackets = hw_stats->vfgprc;
3529         stats->ibytes = hw_stats->vfgorc;
3530         stats->opackets = hw_stats->vfgptc;
3531         stats->obytes = hw_stats->vfgotc;
3532 }
3533
3534 static void
3535 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3536 {
3537         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3538                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3539
3540         /* Sync HW register to the last stats */
3541         ixgbevf_dev_stats_get(dev, NULL);
3542
3543         /* reset HW current stats*/
3544         hw_stats->vfgprc = 0;
3545         hw_stats->vfgorc = 0;
3546         hw_stats->vfgptc = 0;
3547         hw_stats->vfgotc = 0;
3548 }
3549
3550 static int
3551 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3552 {
3553         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3554         u16 eeprom_verh, eeprom_verl;
3555         u32 etrack_id;
3556         int ret;
3557
3558         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3559         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3560
3561         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3562         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3563
3564         ret += 1; /* add the size of '\0' */
3565         if (fw_size < (u32)ret)
3566                 return ret;
3567         else
3568                 return 0;
3569 }
3570
3571 static void
3572 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3573 {
3574         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3575         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3576         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3577
3578         dev_info->pci_dev = pci_dev;
3579         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3580         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3581         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3582                 /*
3583                  * When DCB/VT is off, maximum number of queues changes,
3584                  * except for 82598EB, which remains constant.
3585                  */
3586                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3587                                 hw->mac.type != ixgbe_mac_82598EB)
3588                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3589         }
3590         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3591         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3592         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3593         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3594         dev_info->max_vfs = pci_dev->max_vfs;
3595         if (hw->mac.type == ixgbe_mac_82598EB)
3596                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3597         else
3598                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3599         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3600         dev_info->rx_offload_capa =
3601                 DEV_RX_OFFLOAD_VLAN_STRIP |
3602                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3603                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3604                 DEV_RX_OFFLOAD_TCP_CKSUM;
3605
3606         /*
3607          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3608          * mode.
3609          */
3610         if ((hw->mac.type == ixgbe_mac_82599EB ||
3611              hw->mac.type == ixgbe_mac_X540) &&
3612             !RTE_ETH_DEV_SRIOV(dev).active)
3613                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3614
3615         if (hw->mac.type == ixgbe_mac_82599EB ||
3616             hw->mac.type == ixgbe_mac_X540)
3617                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3618
3619         if (hw->mac.type == ixgbe_mac_X550 ||
3620             hw->mac.type == ixgbe_mac_X550EM_x ||
3621             hw->mac.type == ixgbe_mac_X550EM_a)
3622                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3623
3624         dev_info->tx_offload_capa =
3625                 DEV_TX_OFFLOAD_VLAN_INSERT |
3626                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3627                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3628                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3629                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3630                 DEV_TX_OFFLOAD_TCP_TSO;
3631
3632         if (hw->mac.type == ixgbe_mac_82599EB ||
3633             hw->mac.type == ixgbe_mac_X540)
3634                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3635
3636         if (hw->mac.type == ixgbe_mac_X550 ||
3637             hw->mac.type == ixgbe_mac_X550EM_x ||
3638             hw->mac.type == ixgbe_mac_X550EM_a)
3639                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3640
3641         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3642                 .rx_thresh = {
3643                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3644                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3645                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3646                 },
3647                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3648                 .rx_drop_en = 0,
3649         };
3650
3651         dev_info->default_txconf = (struct rte_eth_txconf) {
3652                 .tx_thresh = {
3653                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3654                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3655                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3656                 },
3657                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3658                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3659                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3660                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3661         };
3662
3663         dev_info->rx_desc_lim = rx_desc_lim;
3664         dev_info->tx_desc_lim = tx_desc_lim;
3665
3666         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3667         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3668         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3669
3670         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3671         if (hw->mac.type == ixgbe_mac_X540 ||
3672             hw->mac.type == ixgbe_mac_X540_vf ||
3673             hw->mac.type == ixgbe_mac_X550 ||
3674             hw->mac.type == ixgbe_mac_X550_vf) {
3675                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3676         }
3677 }
3678
3679 static const uint32_t *
3680 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3681 {
3682         static const uint32_t ptypes[] = {
3683                 /* For non-vec functions,
3684                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3685                  * for vec functions,
3686                  * refers to _recv_raw_pkts_vec().
3687                  */
3688                 RTE_PTYPE_L2_ETHER,
3689                 RTE_PTYPE_L3_IPV4,
3690                 RTE_PTYPE_L3_IPV4_EXT,
3691                 RTE_PTYPE_L3_IPV6,
3692                 RTE_PTYPE_L3_IPV6_EXT,
3693                 RTE_PTYPE_L4_SCTP,
3694                 RTE_PTYPE_L4_TCP,
3695                 RTE_PTYPE_L4_UDP,
3696                 RTE_PTYPE_TUNNEL_IP,
3697                 RTE_PTYPE_INNER_L3_IPV6,
3698                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3699                 RTE_PTYPE_INNER_L4_TCP,
3700                 RTE_PTYPE_INNER_L4_UDP,
3701                 RTE_PTYPE_UNKNOWN
3702         };
3703
3704         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3705             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3706             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3707             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3708                 return ptypes;
3709         return NULL;
3710 }
3711
3712 static void
3713 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3714                      struct rte_eth_dev_info *dev_info)
3715 {
3716         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3717         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3718
3719         dev_info->pci_dev = pci_dev;
3720         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3721         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3722         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3723         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3724         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3725         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3726         dev_info->max_vfs = pci_dev->max_vfs;
3727         if (hw->mac.type == ixgbe_mac_82598EB)
3728                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3729         else
3730                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3731         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3732                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3733                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3734                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3735         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3736                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3737                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3738                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3739                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3740                                 DEV_TX_OFFLOAD_TCP_TSO;
3741
3742         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3743                 .rx_thresh = {
3744                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3745                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3746                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3747                 },
3748                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3749                 .rx_drop_en = 0,
3750         };
3751
3752         dev_info->default_txconf = (struct rte_eth_txconf) {
3753                 .tx_thresh = {
3754                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3755                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3756                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3757                 },
3758                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3759                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3760                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3761                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3762         };
3763
3764         dev_info->rx_desc_lim = rx_desc_lim;
3765         dev_info->tx_desc_lim = tx_desc_lim;
3766 }
3767
3768 /* return 0 means link status changed, -1 means not changed */
3769 static int
3770 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3771 {
3772         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3773         struct rte_eth_link link, old;
3774         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3775         struct ixgbe_interrupt *intr =
3776                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3777         int link_up;
3778         int diag;
3779         u32 speed = 0;
3780         bool autoneg = false;
3781
3782         link.link_status = ETH_LINK_DOWN;
3783         link.link_speed = 0;
3784         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3785         memset(&old, 0, sizeof(old));
3786         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3787
3788         hw->mac.get_link_status = true;
3789
3790         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3791                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3792                 speed = hw->phy.autoneg_advertised;
3793                 if (!speed)
3794                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3795                 ixgbe_setup_link(hw, speed, true);
3796         }
3797
3798         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3799         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3800                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3801         else
3802                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3803
3804         if (diag != 0) {
3805                 link.link_speed = ETH_SPEED_NUM_100M;
3806                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3807                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3808                 if (link.link_status == old.link_status)
3809                         return -1;
3810                 return 0;
3811         }
3812
3813         if (link_up == 0) {
3814                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3815                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3816                 if (link.link_status == old.link_status)
3817                         return -1;
3818                 return 0;
3819         }
3820         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3821         link.link_status = ETH_LINK_UP;
3822         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3823
3824         switch (link_speed) {
3825         default:
3826         case IXGBE_LINK_SPEED_UNKNOWN:
3827                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3828                 link.link_speed = ETH_SPEED_NUM_100M;
3829                 break;
3830
3831         case IXGBE_LINK_SPEED_100_FULL:
3832                 link.link_speed = ETH_SPEED_NUM_100M;
3833                 break;
3834
3835         case IXGBE_LINK_SPEED_1GB_FULL:
3836                 link.link_speed = ETH_SPEED_NUM_1G;
3837                 break;
3838
3839         case IXGBE_LINK_SPEED_10GB_FULL:
3840                 link.link_speed = ETH_SPEED_NUM_10G;
3841                 break;
3842         }
3843         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3844
3845         if (link.link_status == old.link_status)
3846                 return -1;
3847
3848         return 0;
3849 }
3850
3851 static void
3852 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3853 {
3854         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3855         uint32_t fctrl;
3856
3857         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3858         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3859         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3860 }
3861
3862 static void
3863 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3864 {
3865         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3866         uint32_t fctrl;
3867
3868         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3869         fctrl &= (~IXGBE_FCTRL_UPE);
3870         if (dev->data->all_multicast == 1)
3871                 fctrl |= IXGBE_FCTRL_MPE;
3872         else
3873                 fctrl &= (~IXGBE_FCTRL_MPE);
3874         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3875 }
3876
3877 static void
3878 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3879 {
3880         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3881         uint32_t fctrl;
3882
3883         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3884         fctrl |= IXGBE_FCTRL_MPE;
3885         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3886 }
3887
3888 static void
3889 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3890 {
3891         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3892         uint32_t fctrl;
3893
3894         if (dev->data->promiscuous == 1)
3895                 return; /* must remain in all_multicast mode */
3896
3897         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3898         fctrl &= (~IXGBE_FCTRL_MPE);
3899         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3900 }
3901
3902 /**
3903  * It clears the interrupt causes and enables the interrupt.
3904  * It will be called once only during nic initialized.
3905  *
3906  * @param dev
3907  *  Pointer to struct rte_eth_dev.
3908  *
3909  * @return
3910  *  - On success, zero.
3911  *  - On failure, a negative value.
3912  */
3913 static int
3914 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3915 {
3916         struct ixgbe_interrupt *intr =
3917                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3918
3919         ixgbe_dev_link_status_print(dev);
3920         intr->mask |= IXGBE_EICR_LSC;
3921
3922         return 0;
3923 }
3924
3925 /**
3926  * It clears the interrupt causes and enables the interrupt.
3927  * It will be called once only during nic initialized.
3928  *
3929  * @param dev
3930  *  Pointer to struct rte_eth_dev.
3931  *
3932  * @return
3933  *  - On success, zero.
3934  *  - On failure, a negative value.
3935  */
3936 static int
3937 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3938 {
3939         struct ixgbe_interrupt *intr =
3940                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3941
3942         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3943
3944         return 0;
3945 }
3946
3947 /**
3948  * It clears the interrupt causes and enables the interrupt.
3949  * It will be called once only during nic initialized.
3950  *
3951  * @param dev
3952  *  Pointer to struct rte_eth_dev.
3953  *
3954  * @return
3955  *  - On success, zero.
3956  *  - On failure, a negative value.
3957  */
3958 static int
3959 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3960 {
3961         struct ixgbe_interrupt *intr =
3962                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3963
3964         intr->mask |= IXGBE_EICR_LINKSEC;
3965
3966         return 0;
3967 }
3968
3969 /*
3970  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3971  *
3972  * @param dev
3973  *  Pointer to struct rte_eth_dev.
3974  *
3975  * @return
3976  *  - On success, zero.
3977  *  - On failure, a negative value.
3978  */
3979 static int
3980 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3981 {
3982         uint32_t eicr;
3983         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3984         struct ixgbe_interrupt *intr =
3985                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3986
3987         /* clear all cause mask */
3988         ixgbe_disable_intr(hw);
3989
3990         /* read-on-clear nic registers here */
3991         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3992         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3993
3994         intr->flags = 0;
3995
3996         /* set flag for async link update */
3997         if (eicr & IXGBE_EICR_LSC)
3998                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3999
4000         if (eicr & IXGBE_EICR_MAILBOX)
4001                 intr->flags |= IXGBE_FLAG_MAILBOX;
4002
4003         if (eicr & IXGBE_EICR_LINKSEC)
4004                 intr->flags |= IXGBE_FLAG_MACSEC;
4005
4006         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4007             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4008             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4009                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4010
4011         return 0;
4012 }
4013
4014 /**
4015  * It gets and then prints the link status.
4016  *
4017  * @param dev
4018  *  Pointer to struct rte_eth_dev.
4019  *
4020  * @return
4021  *  - On success, zero.
4022  *  - On failure, a negative value.
4023  */
4024 static void
4025 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4026 {
4027         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4028         struct rte_eth_link link;
4029
4030         memset(&link, 0, sizeof(link));
4031         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4032         if (link.link_status) {
4033                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4034                                         (int)(dev->data->port_id),
4035                                         (unsigned)link.link_speed,
4036                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4037                                         "full-duplex" : "half-duplex");
4038         } else {
4039                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4040                                 (int)(dev->data->port_id));
4041         }
4042         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4043                                 pci_dev->addr.domain,
4044                                 pci_dev->addr.bus,
4045                                 pci_dev->addr.devid,
4046                                 pci_dev->addr.function);
4047 }
4048
4049 /*
4050  * It executes link_update after knowing an interrupt occurred.
4051  *
4052  * @param dev
4053  *  Pointer to struct rte_eth_dev.
4054  *
4055  * @return
4056  *  - On success, zero.
4057  *  - On failure, a negative value.
4058  */
4059 static int
4060 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4061                            struct rte_intr_handle *intr_handle)
4062 {
4063         struct ixgbe_interrupt *intr =
4064                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4065         int64_t timeout;
4066         struct rte_eth_link link;
4067         struct ixgbe_hw *hw =
4068                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4069
4070         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4071
4072         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4073                 ixgbe_pf_mbx_process(dev);
4074                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4075         }
4076
4077         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4078                 ixgbe_handle_lasi(hw);
4079                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4080         }
4081
4082         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4083                 /* get the link status before link update, for predicting later */
4084                 memset(&link, 0, sizeof(link));
4085                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4086
4087                 ixgbe_dev_link_update(dev, 0);
4088
4089                 /* likely to up */
4090                 if (!link.link_status)
4091                         /* handle it 1 sec later, wait it being stable */
4092                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4093                 /* likely to down */
4094                 else
4095                         /* handle it 4 sec later, wait it being stable */
4096                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4097
4098                 ixgbe_dev_link_status_print(dev);
4099                 if (rte_eal_alarm_set(timeout * 1000,
4100                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4101                         PMD_DRV_LOG(ERR, "Error setting alarm");
4102                 else {
4103                         /* remember original mask */
4104                         intr->mask_original = intr->mask;
4105                         /* only disable lsc interrupt */
4106                         intr->mask &= ~IXGBE_EIMS_LSC;
4107                 }
4108         }
4109
4110         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4111         ixgbe_enable_intr(dev);
4112         rte_intr_enable(intr_handle);
4113
4114         return 0;
4115 }
4116
4117 /**
4118  * Interrupt handler which shall be registered for alarm callback for delayed
4119  * handling specific interrupt to wait for the stable nic state. As the
4120  * NIC interrupt state is not stable for ixgbe after link is just down,
4121  * it needs to wait 4 seconds to get the stable status.
4122  *
4123  * @param handle
4124  *  Pointer to interrupt handle.
4125  * @param param
4126  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4127  *
4128  * @return
4129  *  void
4130  */
4131 static void
4132 ixgbe_dev_interrupt_delayed_handler(void *param)
4133 {
4134         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4135         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4136         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4137         struct ixgbe_interrupt *intr =
4138                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4139         struct ixgbe_hw *hw =
4140                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4141         uint32_t eicr;
4142
4143         ixgbe_disable_intr(hw);
4144
4145         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4146         if (eicr & IXGBE_EICR_MAILBOX)
4147                 ixgbe_pf_mbx_process(dev);
4148
4149         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4150                 ixgbe_handle_lasi(hw);
4151                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4152         }
4153
4154         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4155                 ixgbe_dev_link_update(dev, 0);
4156                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4157                 ixgbe_dev_link_status_print(dev);
4158                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4159                                               NULL, NULL);
4160         }
4161
4162         if (intr->flags & IXGBE_FLAG_MACSEC) {
4163                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4164                                               NULL, NULL);
4165                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4166         }
4167
4168         /* restore original mask */
4169         intr->mask = intr->mask_original;
4170         intr->mask_original = 0;
4171
4172         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4173         ixgbe_enable_intr(dev);
4174         rte_intr_enable(intr_handle);
4175 }
4176
4177 /**
4178  * Interrupt handler triggered by NIC  for handling
4179  * specific interrupt.
4180  *
4181  * @param handle
4182  *  Pointer to interrupt handle.
4183  * @param param
4184  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4185  *
4186  * @return
4187  *  void
4188  */
4189 static void
4190 ixgbe_dev_interrupt_handler(void *param)
4191 {
4192         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4193
4194         ixgbe_dev_interrupt_get_status(dev);
4195         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4196 }
4197
4198 static int
4199 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4200 {
4201         struct ixgbe_hw *hw;
4202
4203         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4204         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4205 }
4206
4207 static int
4208 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4209 {
4210         struct ixgbe_hw *hw;
4211
4212         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4213         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4214 }
4215
4216 static int
4217 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4218 {
4219         struct ixgbe_hw *hw;
4220         uint32_t mflcn_reg;
4221         uint32_t fccfg_reg;
4222         int rx_pause;
4223         int tx_pause;
4224
4225         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4226
4227         fc_conf->pause_time = hw->fc.pause_time;
4228         fc_conf->high_water = hw->fc.high_water[0];
4229         fc_conf->low_water = hw->fc.low_water[0];
4230         fc_conf->send_xon = hw->fc.send_xon;
4231         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4232
4233         /*
4234          * Return rx_pause status according to actual setting of
4235          * MFLCN register.
4236          */
4237         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4238         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4239                 rx_pause = 1;
4240         else
4241                 rx_pause = 0;
4242
4243         /*
4244          * Return tx_pause status according to actual setting of
4245          * FCCFG register.
4246          */
4247         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4248         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4249                 tx_pause = 1;
4250         else
4251                 tx_pause = 0;
4252
4253         if (rx_pause && tx_pause)
4254                 fc_conf->mode = RTE_FC_FULL;
4255         else if (rx_pause)
4256                 fc_conf->mode = RTE_FC_RX_PAUSE;
4257         else if (tx_pause)
4258                 fc_conf->mode = RTE_FC_TX_PAUSE;
4259         else
4260                 fc_conf->mode = RTE_FC_NONE;
4261
4262         return 0;
4263 }
4264
4265 static int
4266 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4267 {
4268         struct ixgbe_hw *hw;
4269         int err;
4270         uint32_t rx_buf_size;
4271         uint32_t max_high_water;
4272         uint32_t mflcn;
4273         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4274                 ixgbe_fc_none,
4275                 ixgbe_fc_rx_pause,
4276                 ixgbe_fc_tx_pause,
4277                 ixgbe_fc_full
4278         };
4279
4280         PMD_INIT_FUNC_TRACE();
4281
4282         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4283         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4284         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4285
4286         /*
4287          * At least reserve one Ethernet frame for watermark
4288          * high_water/low_water in kilo bytes for ixgbe
4289          */
4290         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4291         if ((fc_conf->high_water > max_high_water) ||
4292                 (fc_conf->high_water < fc_conf->low_water)) {
4293                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4294                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4295                 return -EINVAL;
4296         }
4297
4298         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4299         hw->fc.pause_time     = fc_conf->pause_time;
4300         hw->fc.high_water[0]  = fc_conf->high_water;
4301         hw->fc.low_water[0]   = fc_conf->low_water;
4302         hw->fc.send_xon       = fc_conf->send_xon;
4303         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4304
4305         err = ixgbe_fc_enable(hw);
4306
4307         /* Not negotiated is not an error case */
4308         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4309
4310                 /* check if we want to forward MAC frames - driver doesn't have native
4311                  * capability to do that, so we'll write the registers ourselves */
4312
4313                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4314
4315                 /* set or clear MFLCN.PMCF bit depending on configuration */
4316                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4317                         mflcn |= IXGBE_MFLCN_PMCF;
4318                 else
4319                         mflcn &= ~IXGBE_MFLCN_PMCF;
4320
4321                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4322                 IXGBE_WRITE_FLUSH(hw);
4323
4324                 return 0;
4325         }
4326
4327         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4328         return -EIO;
4329 }
4330
4331 /**
4332  *  ixgbe_pfc_enable_generic - Enable flow control
4333  *  @hw: pointer to hardware structure
4334  *  @tc_num: traffic class number
4335  *  Enable flow control according to the current settings.
4336  */
4337 static int
4338 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4339 {
4340         int ret_val = 0;
4341         uint32_t mflcn_reg, fccfg_reg;
4342         uint32_t reg;
4343         uint32_t fcrtl, fcrth;
4344         uint8_t i;
4345         uint8_t nb_rx_en;
4346
4347         /* Validate the water mark configuration */
4348         if (!hw->fc.pause_time) {
4349                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4350                 goto out;
4351         }
4352
4353         /* Low water mark of zero causes XOFF floods */
4354         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4355                  /* High/Low water can not be 0 */
4356                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4357                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4358                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4359                         goto out;
4360                 }
4361
4362                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4363                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4364                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4365                         goto out;
4366                 }
4367         }
4368         /* Negotiate the fc mode to use */
4369         ixgbe_fc_autoneg(hw);
4370
4371         /* Disable any previous flow control settings */
4372         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4373         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4374
4375         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4376         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4377
4378         switch (hw->fc.current_mode) {
4379         case ixgbe_fc_none:
4380                 /*
4381                  * If the count of enabled RX Priority Flow control >1,
4382                  * and the TX pause can not be disabled
4383                  */
4384                 nb_rx_en = 0;
4385                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4386                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4387                         if (reg & IXGBE_FCRTH_FCEN)
4388                                 nb_rx_en++;
4389                 }
4390                 if (nb_rx_en > 1)
4391                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4392                 break;
4393         case ixgbe_fc_rx_pause:
4394                 /*
4395                  * Rx Flow control is enabled and Tx Flow control is
4396                  * disabled by software override. Since there really
4397                  * isn't a way to advertise that we are capable of RX
4398                  * Pause ONLY, we will advertise that we support both
4399                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4400                  * disable the adapter's ability to send PAUSE frames.
4401                  */
4402                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4403                 /*
4404                  * If the count of enabled RX Priority Flow control >1,
4405                  * and the TX pause can not be disabled
4406                  */
4407                 nb_rx_en = 0;
4408                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4409                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4410                         if (reg & IXGBE_FCRTH_FCEN)
4411                                 nb_rx_en++;
4412                 }
4413                 if (nb_rx_en > 1)
4414                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4415                 break;
4416         case ixgbe_fc_tx_pause:
4417                 /*
4418                  * Tx Flow control is enabled, and Rx Flow control is
4419                  * disabled by software override.
4420                  */
4421                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4422                 break;
4423         case ixgbe_fc_full:
4424                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4425                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4426                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4427                 break;
4428         default:
4429                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4430                 ret_val = IXGBE_ERR_CONFIG;
4431                 goto out;
4432         }
4433
4434         /* Set 802.3x based flow control settings. */
4435         mflcn_reg |= IXGBE_MFLCN_DPF;
4436         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4437         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4438
4439         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4440         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4441                 hw->fc.high_water[tc_num]) {
4442                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4443                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4444                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4445         } else {
4446                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4447                 /*
4448                  * In order to prevent Tx hangs when the internal Tx
4449                  * switch is enabled we must set the high water mark
4450                  * to the maximum FCRTH value.  This allows the Tx
4451                  * switch to function even under heavy Rx workloads.
4452                  */
4453                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4454         }
4455         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4456
4457         /* Configure pause time (2 TCs per register) */
4458         reg = hw->fc.pause_time * 0x00010001;
4459         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4460                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4461
4462         /* Configure flow control refresh threshold value */
4463         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4464
4465 out:
4466         return ret_val;
4467 }
4468
4469 static int
4470 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4471 {
4472         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4473         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4474
4475         if (hw->mac.type != ixgbe_mac_82598EB) {
4476                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4477         }
4478         return ret_val;
4479 }
4480
4481 static int
4482 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4483 {
4484         int err;
4485         uint32_t rx_buf_size;
4486         uint32_t max_high_water;
4487         uint8_t tc_num;
4488         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4489         struct ixgbe_hw *hw =
4490                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4491         struct ixgbe_dcb_config *dcb_config =
4492                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4493
4494         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4495                 ixgbe_fc_none,
4496                 ixgbe_fc_rx_pause,
4497                 ixgbe_fc_tx_pause,
4498                 ixgbe_fc_full
4499         };
4500
4501         PMD_INIT_FUNC_TRACE();
4502
4503         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4504         tc_num = map[pfc_conf->priority];
4505         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4506         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4507         /*
4508          * At least reserve one Ethernet frame for watermark
4509          * high_water/low_water in kilo bytes for ixgbe
4510          */
4511         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4512         if ((pfc_conf->fc.high_water > max_high_water) ||
4513             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4514                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4515                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4516                 return -EINVAL;
4517         }
4518
4519         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4520         hw->fc.pause_time = pfc_conf->fc.pause_time;
4521         hw->fc.send_xon = pfc_conf->fc.send_xon;
4522         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4523         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4524
4525         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4526
4527         /* Not negotiated is not an error case */
4528         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4529                 return 0;
4530
4531         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4532         return -EIO;
4533 }
4534
4535 static int
4536 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4537                           struct rte_eth_rss_reta_entry64 *reta_conf,
4538                           uint16_t reta_size)
4539 {
4540         uint16_t i, sp_reta_size;
4541         uint8_t j, mask;
4542         uint32_t reta, r;
4543         uint16_t idx, shift;
4544         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4545         uint32_t reta_reg;
4546
4547         PMD_INIT_FUNC_TRACE();
4548
4549         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4550                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4551                         "NIC.");
4552                 return -ENOTSUP;
4553         }
4554
4555         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4556         if (reta_size != sp_reta_size) {
4557                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4558                         "(%d) doesn't match the number hardware can supported "
4559                         "(%d)", reta_size, sp_reta_size);
4560                 return -EINVAL;
4561         }
4562
4563         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4564                 idx = i / RTE_RETA_GROUP_SIZE;
4565                 shift = i % RTE_RETA_GROUP_SIZE;
4566                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4567                                                 IXGBE_4_BIT_MASK);
4568                 if (!mask)
4569                         continue;
4570                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4571                 if (mask == IXGBE_4_BIT_MASK)
4572                         r = 0;
4573                 else
4574                         r = IXGBE_READ_REG(hw, reta_reg);
4575                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4576                         if (mask & (0x1 << j))
4577                                 reta |= reta_conf[idx].reta[shift + j] <<
4578                                                         (CHAR_BIT * j);
4579                         else
4580                                 reta |= r & (IXGBE_8_BIT_MASK <<
4581                                                 (CHAR_BIT * j));
4582                 }
4583                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4584         }
4585
4586         return 0;
4587 }
4588
4589 static int
4590 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4591                          struct rte_eth_rss_reta_entry64 *reta_conf,
4592                          uint16_t reta_size)
4593 {
4594         uint16_t i, sp_reta_size;
4595         uint8_t j, mask;
4596         uint32_t reta;
4597         uint16_t idx, shift;
4598         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4599         uint32_t reta_reg;
4600
4601         PMD_INIT_FUNC_TRACE();
4602         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4603         if (reta_size != sp_reta_size) {
4604                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4605                         "(%d) doesn't match the number hardware can supported "
4606                         "(%d)", reta_size, sp_reta_size);
4607                 return -EINVAL;
4608         }
4609
4610         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4611                 idx = i / RTE_RETA_GROUP_SIZE;
4612                 shift = i % RTE_RETA_GROUP_SIZE;
4613                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4614                                                 IXGBE_4_BIT_MASK);
4615                 if (!mask)
4616                         continue;
4617
4618                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4619                 reta = IXGBE_READ_REG(hw, reta_reg);
4620                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4621                         if (mask & (0x1 << j))
4622                                 reta_conf[idx].reta[shift + j] =
4623                                         ((reta >> (CHAR_BIT * j)) &
4624                                                 IXGBE_8_BIT_MASK);
4625                 }
4626         }
4627
4628         return 0;
4629 }
4630
4631 static int
4632 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4633                                 uint32_t index, uint32_t pool)
4634 {
4635         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4636         uint32_t enable_addr = 1;
4637
4638         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4639                              pool, enable_addr);
4640 }
4641
4642 static void
4643 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4644 {
4645         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4646
4647         ixgbe_clear_rar(hw, index);
4648 }
4649
4650 static void
4651 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4652 {
4653         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4654
4655         ixgbe_remove_rar(dev, 0);
4656
4657         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4658 }
4659
4660 static bool
4661 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4662 {
4663         if (strcmp(dev->device->driver->name, drv->driver.name))
4664                 return false;
4665
4666         return true;
4667 }
4668
4669 bool
4670 is_ixgbe_supported(struct rte_eth_dev *dev)
4671 {
4672         return is_device_supported(dev, &rte_ixgbe_pmd);
4673 }
4674
4675 static int
4676 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4677 {
4678         uint32_t hlreg0;
4679         uint32_t maxfrs;
4680         struct ixgbe_hw *hw;
4681         struct rte_eth_dev_info dev_info;
4682         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4683         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4684
4685         ixgbe_dev_info_get(dev, &dev_info);
4686
4687         /* check that mtu is within the allowed range */
4688         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4689                 return -EINVAL;
4690
4691         /* refuse mtu that requires the support of scattered packets when this
4692          * feature has not been enabled before.
4693          */
4694         if (!rx_conf->enable_scatter &&
4695             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4696              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4697                 return -EINVAL;
4698
4699         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4700         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4701
4702         /* switch to jumbo mode if needed */
4703         if (frame_size > ETHER_MAX_LEN) {
4704                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4705                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4706         } else {
4707                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4708                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4709         }
4710         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4711
4712         /* update max frame size */
4713         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4714
4715         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4716         maxfrs &= 0x0000FFFF;
4717         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4718         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4719
4720         return 0;
4721 }
4722
4723 /*
4724  * Virtual Function operations
4725  */
4726 static void
4727 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4728 {
4729         PMD_INIT_FUNC_TRACE();
4730
4731         /* Clear interrupt mask to stop from interrupts being generated */
4732         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4733
4734         IXGBE_WRITE_FLUSH(hw);
4735 }
4736
4737 static void
4738 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4739 {
4740         PMD_INIT_FUNC_TRACE();
4741
4742         /* VF enable interrupt autoclean */
4743         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4744         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4745         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4746
4747         IXGBE_WRITE_FLUSH(hw);
4748 }
4749
4750 static int
4751 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4752 {
4753         struct rte_eth_conf *conf = &dev->data->dev_conf;
4754         struct ixgbe_adapter *adapter =
4755                         (struct ixgbe_adapter *)dev->data->dev_private;
4756
4757         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4758                      dev->data->port_id);
4759
4760         /*
4761          * VF has no ability to enable/disable HW CRC
4762          * Keep the persistent behavior the same as Host PF
4763          */
4764 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4765         if (!conf->rxmode.hw_strip_crc) {
4766                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4767                 conf->rxmode.hw_strip_crc = 1;
4768         }
4769 #else
4770         if (conf->rxmode.hw_strip_crc) {
4771                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4772                 conf->rxmode.hw_strip_crc = 0;
4773         }
4774 #endif
4775
4776         /*
4777          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4778          * allocation or vector Rx preconditions we will reset it.
4779          */
4780         adapter->rx_bulk_alloc_allowed = true;
4781         adapter->rx_vec_allowed = true;
4782
4783         return 0;
4784 }
4785
4786 static int
4787 ixgbevf_dev_start(struct rte_eth_dev *dev)
4788 {
4789         struct ixgbe_hw *hw =
4790                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4791         uint32_t intr_vector = 0;
4792         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4793         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4794
4795         int err, mask = 0;
4796
4797         PMD_INIT_FUNC_TRACE();
4798
4799         hw->mac.ops.reset_hw(hw);
4800         hw->mac.get_link_status = true;
4801
4802         /* negotiate mailbox API version to use with the PF. */
4803         ixgbevf_negotiate_api(hw);
4804
4805         ixgbevf_dev_tx_init(dev);
4806
4807         /* This can fail when allocating mbufs for descriptor rings */
4808         err = ixgbevf_dev_rx_init(dev);
4809         if (err) {
4810                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4811                 ixgbe_dev_clear_queues(dev);
4812                 return err;
4813         }
4814
4815         /* Set vfta */
4816         ixgbevf_set_vfta_all(dev, 1);
4817
4818         /* Set HW strip */
4819         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4820                 ETH_VLAN_EXTEND_MASK;
4821         ixgbevf_vlan_offload_set(dev, mask);
4822
4823         ixgbevf_dev_rxtx_start(dev);
4824
4825         /* check and configure queue intr-vector mapping */
4826         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4827                 intr_vector = dev->data->nb_rx_queues;
4828                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4829                         return -1;
4830         }
4831
4832         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4833                 intr_handle->intr_vec =
4834                         rte_zmalloc("intr_vec",
4835                                     dev->data->nb_rx_queues * sizeof(int), 0);
4836                 if (intr_handle->intr_vec == NULL) {
4837                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4838                                      " intr_vec", dev->data->nb_rx_queues);
4839                         return -ENOMEM;
4840                 }
4841         }
4842         ixgbevf_configure_msix(dev);
4843
4844         rte_intr_enable(intr_handle);
4845
4846         /* Re-enable interrupt for VF */
4847         ixgbevf_intr_enable(hw);
4848
4849         return 0;
4850 }
4851
4852 static void
4853 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4854 {
4855         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4856         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4857         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4858
4859         PMD_INIT_FUNC_TRACE();
4860
4861         ixgbevf_intr_disable(hw);
4862
4863         hw->adapter_stopped = 1;
4864         ixgbe_stop_adapter(hw);
4865
4866         /*
4867           * Clear what we set, but we still keep shadow_vfta to
4868           * restore after device starts
4869           */
4870         ixgbevf_set_vfta_all(dev, 0);
4871
4872         /* Clear stored conf */
4873         dev->data->scattered_rx = 0;
4874
4875         ixgbe_dev_clear_queues(dev);
4876
4877         /* Clean datapath event and queue/vec mapping */
4878         rte_intr_efd_disable(intr_handle);
4879         if (intr_handle->intr_vec != NULL) {
4880                 rte_free(intr_handle->intr_vec);
4881                 intr_handle->intr_vec = NULL;
4882         }
4883 }
4884
4885 static void
4886 ixgbevf_dev_close(struct rte_eth_dev *dev)
4887 {
4888         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4889
4890         PMD_INIT_FUNC_TRACE();
4891
4892         ixgbe_reset_hw(hw);
4893
4894         ixgbevf_dev_stop(dev);
4895
4896         ixgbe_dev_free_queues(dev);
4897
4898         /**
4899          * Remove the VF MAC address ro ensure
4900          * that the VF traffic goes to the PF
4901          * after stop, close and detach of the VF
4902          **/
4903         ixgbevf_remove_mac_addr(dev, 0);
4904 }
4905
4906 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4907 {
4908         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4909         struct ixgbe_vfta *shadow_vfta =
4910                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4911         int i = 0, j = 0, vfta = 0, mask = 1;
4912
4913         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4914                 vfta = shadow_vfta->vfta[i];
4915                 if (vfta) {
4916                         mask = 1;
4917                         for (j = 0; j < 32; j++) {
4918                                 if (vfta & mask)
4919                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4920                                                        on, false);
4921                                 mask <<= 1;
4922                         }
4923                 }
4924         }
4925
4926 }
4927
4928 static int
4929 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4930 {
4931         struct ixgbe_hw *hw =
4932                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4933         struct ixgbe_vfta *shadow_vfta =
4934                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4935         uint32_t vid_idx = 0;
4936         uint32_t vid_bit = 0;
4937         int ret = 0;
4938
4939         PMD_INIT_FUNC_TRACE();
4940
4941         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4942         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4943         if (ret) {
4944                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4945                 return ret;
4946         }
4947         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4948         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4949
4950         /* Save what we set and retore it after device reset */
4951         if (on)
4952                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4953         else
4954                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4955
4956         return 0;
4957 }
4958
4959 static void
4960 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4961 {
4962         struct ixgbe_hw *hw =
4963                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4964         uint32_t ctrl;
4965
4966         PMD_INIT_FUNC_TRACE();
4967
4968         if (queue >= hw->mac.max_rx_queues)
4969                 return;
4970
4971         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4972         if (on)
4973                 ctrl |= IXGBE_RXDCTL_VME;
4974         else
4975                 ctrl &= ~IXGBE_RXDCTL_VME;
4976         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4977
4978         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4979 }
4980
4981 static void
4982 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4983 {
4984         struct ixgbe_hw *hw =
4985                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4986         uint16_t i;
4987         int on = 0;
4988
4989         /* VF function only support hw strip feature, others are not support */
4990         if (mask & ETH_VLAN_STRIP_MASK) {
4991                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4992
4993                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4994                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4995         }
4996 }
4997
4998 int
4999 ixgbe_vt_check(struct ixgbe_hw *hw)
5000 {
5001         uint32_t reg_val;
5002
5003         /* if Virtualization Technology is enabled */
5004         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5005         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5006                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5007                 return -1;
5008         }
5009
5010         return 0;
5011 }
5012
5013 static uint32_t
5014 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5015 {
5016         uint32_t vector = 0;
5017
5018         switch (hw->mac.mc_filter_type) {
5019         case 0:   /* use bits [47:36] of the address */
5020                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5021                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5022                 break;
5023         case 1:   /* use bits [46:35] of the address */
5024                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5025                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5026                 break;
5027         case 2:   /* use bits [45:34] of the address */
5028                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5029                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5030                 break;
5031         case 3:   /* use bits [43:32] of the address */
5032                 vector = ((uc_addr->addr_bytes[4]) |
5033                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5034                 break;
5035         default:  /* Invalid mc_filter_type */
5036                 break;
5037         }
5038
5039         /* vector can only be 12-bits or boundary will be exceeded */
5040         vector &= 0xFFF;
5041         return vector;
5042 }
5043
5044 static int
5045 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5046                         uint8_t on)
5047 {
5048         uint32_t vector;
5049         uint32_t uta_idx;
5050         uint32_t reg_val;
5051         uint32_t uta_shift;
5052         uint32_t rc;
5053         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5054         const uint32_t ixgbe_uta_bit_shift = 5;
5055         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5056         const uint32_t bit1 = 0x1;
5057
5058         struct ixgbe_hw *hw =
5059                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5060         struct ixgbe_uta_info *uta_info =
5061                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5062
5063         /* The UTA table only exists on 82599 hardware and newer */
5064         if (hw->mac.type < ixgbe_mac_82599EB)
5065                 return -ENOTSUP;
5066
5067         vector = ixgbe_uta_vector(hw, mac_addr);
5068         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5069         uta_shift = vector & ixgbe_uta_bit_mask;
5070
5071         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5072         if (rc == on)
5073                 return 0;
5074
5075         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5076         if (on) {
5077                 uta_info->uta_in_use++;
5078                 reg_val |= (bit1 << uta_shift);
5079                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5080         } else {
5081                 uta_info->uta_in_use--;
5082                 reg_val &= ~(bit1 << uta_shift);
5083                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5084         }
5085
5086         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5087
5088         if (uta_info->uta_in_use > 0)
5089                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5090                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5091         else
5092                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5093
5094         return 0;
5095 }
5096
5097 static int
5098 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5099 {
5100         int i;
5101         struct ixgbe_hw *hw =
5102                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5103         struct ixgbe_uta_info *uta_info =
5104                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5105
5106         /* The UTA table only exists on 82599 hardware and newer */
5107         if (hw->mac.type < ixgbe_mac_82599EB)
5108                 return -ENOTSUP;
5109
5110         if (on) {
5111                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5112                         uta_info->uta_shadow[i] = ~0;
5113                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5114                 }
5115         } else {
5116                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5117                         uta_info->uta_shadow[i] = 0;
5118                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5119                 }
5120         }
5121         return 0;
5122
5123 }
5124
5125 uint32_t
5126 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5127 {
5128         uint32_t new_val = orig_val;
5129
5130         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5131                 new_val |= IXGBE_VMOLR_AUPE;
5132         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5133                 new_val |= IXGBE_VMOLR_ROMPE;
5134         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5135                 new_val |= IXGBE_VMOLR_ROPE;
5136         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5137                 new_val |= IXGBE_VMOLR_BAM;
5138         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5139                 new_val |= IXGBE_VMOLR_MPE;
5140
5141         return new_val;
5142 }
5143
5144 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5145 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5146 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5147 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5148 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5149         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5150         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5151
5152 static int
5153 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5154                       struct rte_eth_mirror_conf *mirror_conf,
5155                       uint8_t rule_id, uint8_t on)
5156 {
5157         uint32_t mr_ctl, vlvf;
5158         uint32_t mp_lsb = 0;
5159         uint32_t mv_msb = 0;
5160         uint32_t mv_lsb = 0;
5161         uint32_t mp_msb = 0;
5162         uint8_t i = 0;
5163         int reg_index = 0;
5164         uint64_t vlan_mask = 0;
5165
5166         const uint8_t pool_mask_offset = 32;
5167         const uint8_t vlan_mask_offset = 32;
5168         const uint8_t dst_pool_offset = 8;
5169         const uint8_t rule_mr_offset  = 4;
5170         const uint8_t mirror_rule_mask = 0x0F;
5171
5172         struct ixgbe_mirror_info *mr_info =
5173                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5174         struct ixgbe_hw *hw =
5175                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5176         uint8_t mirror_type = 0;
5177
5178         if (ixgbe_vt_check(hw) < 0)
5179                 return -ENOTSUP;
5180
5181         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5182                 return -EINVAL;
5183
5184         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5185                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5186                             mirror_conf->rule_type);
5187                 return -EINVAL;
5188         }
5189
5190         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5191                 mirror_type |= IXGBE_MRCTL_VLME;
5192                 /* Check if vlan id is valid and find conresponding VLAN ID
5193                  * index in VLVF
5194                  */
5195                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5196                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5197                                 /* search vlan id related pool vlan filter
5198                                  * index
5199                                  */
5200                                 reg_index = ixgbe_find_vlvf_slot(
5201                                                 hw,
5202                                                 mirror_conf->vlan.vlan_id[i],
5203                                                 false);
5204                                 if (reg_index < 0)
5205                                         return -EINVAL;
5206                                 vlvf = IXGBE_READ_REG(hw,
5207                                                       IXGBE_VLVF(reg_index));
5208                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5209                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5210                                       mirror_conf->vlan.vlan_id[i]))
5211                                         vlan_mask |= (1ULL << reg_index);
5212                                 else
5213                                         return -EINVAL;
5214                         }
5215                 }
5216
5217                 if (on) {
5218                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5219                         mv_msb = vlan_mask >> vlan_mask_offset;
5220
5221                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5222                                                 mirror_conf->vlan.vlan_mask;
5223                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5224                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5225                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5226                                                 mirror_conf->vlan.vlan_id[i];
5227                         }
5228                 } else {
5229                         mv_lsb = 0;
5230                         mv_msb = 0;
5231                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5232                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5233                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5234                 }
5235         }
5236
5237         /**
5238          * if enable pool mirror, write related pool mask register,if disable
5239          * pool mirror, clear PFMRVM register
5240          */
5241         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5242                 mirror_type |= IXGBE_MRCTL_VPME;
5243                 if (on) {
5244                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5245                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5246                         mr_info->mr_conf[rule_id].pool_mask =
5247                                         mirror_conf->pool_mask;
5248
5249                 } else {
5250                         mp_lsb = 0;
5251                         mp_msb = 0;
5252                         mr_info->mr_conf[rule_id].pool_mask = 0;
5253                 }
5254         }
5255         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5256                 mirror_type |= IXGBE_MRCTL_UPME;
5257         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5258                 mirror_type |= IXGBE_MRCTL_DPME;
5259
5260         /* read  mirror control register and recalculate it */
5261         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5262
5263         if (on) {
5264                 mr_ctl |= mirror_type;
5265                 mr_ctl &= mirror_rule_mask;
5266                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5267         } else {
5268                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5269         }
5270
5271         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5272         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5273
5274         /* write mirrror control  register */
5275         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5276
5277         /* write pool mirrror control  register */
5278         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5279                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5280                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5281                                 mp_msb);
5282         }
5283         /* write VLAN mirrror control  register */
5284         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5285                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5286                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5287                                 mv_msb);
5288         }
5289
5290         return 0;
5291 }
5292
5293 static int
5294 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5295 {
5296         int mr_ctl = 0;
5297         uint32_t lsb_val = 0;
5298         uint32_t msb_val = 0;
5299         const uint8_t rule_mr_offset = 4;
5300
5301         struct ixgbe_hw *hw =
5302                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5303         struct ixgbe_mirror_info *mr_info =
5304                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5305
5306         if (ixgbe_vt_check(hw) < 0)
5307                 return -ENOTSUP;
5308
5309         memset(&mr_info->mr_conf[rule_id], 0,
5310                sizeof(struct rte_eth_mirror_conf));
5311
5312         /* clear PFVMCTL register */
5313         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5314
5315         /* clear pool mask register */
5316         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5317         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5318
5319         /* clear vlan mask register */
5320         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5321         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5322
5323         return 0;
5324 }
5325
5326 static int
5327 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5328 {
5329         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5330         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5331         uint32_t mask;
5332         struct ixgbe_hw *hw =
5333                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5334
5335         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5336         mask |= (1 << IXGBE_MISC_VEC_ID);
5337         RTE_SET_USED(queue_id);
5338         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5339
5340         rte_intr_enable(intr_handle);
5341
5342         return 0;
5343 }
5344
5345 static int
5346 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5347 {
5348         uint32_t mask;
5349         struct ixgbe_hw *hw =
5350                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5351
5352         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5353         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5354         RTE_SET_USED(queue_id);
5355         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5356
5357         return 0;
5358 }
5359
5360 static int
5361 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5362 {
5363         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5364         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5365         uint32_t mask;
5366         struct ixgbe_hw *hw =
5367                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5368         struct ixgbe_interrupt *intr =
5369                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5370
5371         if (queue_id < 16) {
5372                 ixgbe_disable_intr(hw);
5373                 intr->mask |= (1 << queue_id);
5374                 ixgbe_enable_intr(dev);
5375         } else if (queue_id < 32) {
5376                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5377                 mask &= (1 << queue_id);
5378                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5379         } else if (queue_id < 64) {
5380                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5381                 mask &= (1 << (queue_id - 32));
5382                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5383         }
5384         rte_intr_enable(intr_handle);
5385
5386         return 0;
5387 }
5388
5389 static int
5390 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5391 {
5392         uint32_t mask;
5393         struct ixgbe_hw *hw =
5394                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5395         struct ixgbe_interrupt *intr =
5396                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5397
5398         if (queue_id < 16) {
5399                 ixgbe_disable_intr(hw);
5400                 intr->mask &= ~(1 << queue_id);
5401                 ixgbe_enable_intr(dev);
5402         } else if (queue_id < 32) {
5403                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5404                 mask &= ~(1 << queue_id);
5405                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5406         } else if (queue_id < 64) {
5407                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5408                 mask &= ~(1 << (queue_id - 32));
5409                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5410         }
5411
5412         return 0;
5413 }
5414
5415 static void
5416 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5417                      uint8_t queue, uint8_t msix_vector)
5418 {
5419         uint32_t tmp, idx;
5420
5421         if (direction == -1) {
5422                 /* other causes */
5423                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5424                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5425                 tmp &= ~0xFF;
5426                 tmp |= msix_vector;
5427                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5428         } else {
5429                 /* rx or tx cause */
5430                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5431                 idx = ((16 * (queue & 1)) + (8 * direction));
5432                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5433                 tmp &= ~(0xFF << idx);
5434                 tmp |= (msix_vector << idx);
5435                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5436         }
5437 }
5438
5439 /**
5440  * set the IVAR registers, mapping interrupt causes to vectors
5441  * @param hw
5442  *  pointer to ixgbe_hw struct
5443  * @direction
5444  *  0 for Rx, 1 for Tx, -1 for other causes
5445  * @queue
5446  *  queue to map the corresponding interrupt to
5447  * @msix_vector
5448  *  the vector to map to the corresponding queue
5449  */
5450 static void
5451 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5452                    uint8_t queue, uint8_t msix_vector)
5453 {
5454         uint32_t tmp, idx;
5455
5456         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5457         if (hw->mac.type == ixgbe_mac_82598EB) {
5458                 if (direction == -1)
5459                         direction = 0;
5460                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5461                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5462                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5463                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5464                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5465         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5466                         (hw->mac.type == ixgbe_mac_X540)) {
5467                 if (direction == -1) {
5468                         /* other causes */
5469                         idx = ((queue & 1) * 8);
5470                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5471                         tmp &= ~(0xFF << idx);
5472                         tmp |= (msix_vector << idx);
5473                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5474                 } else {
5475                         /* rx or tx causes */
5476                         idx = ((16 * (queue & 1)) + (8 * direction));
5477                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5478                         tmp &= ~(0xFF << idx);
5479                         tmp |= (msix_vector << idx);
5480                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5481                 }
5482         }
5483 }
5484
5485 static void
5486 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5487 {
5488         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5489         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5490         struct ixgbe_hw *hw =
5491                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5492         uint32_t q_idx;
5493         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5494
5495         /* Configure VF other cause ivar */
5496         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5497
5498         /* won't configure msix register if no mapping is done
5499          * between intr vector and event fd.
5500          */
5501         if (!rte_intr_dp_is_en(intr_handle))
5502                 return;
5503
5504         /* Configure all RX queues of VF */
5505         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5506                 /* Force all queue use vector 0,
5507                  * as IXGBE_VF_MAXMSIVECOTR = 1
5508                  */
5509                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5510                 intr_handle->intr_vec[q_idx] = vector_idx;
5511         }
5512 }
5513
5514 /**
5515  * Sets up the hardware to properly generate MSI-X interrupts
5516  * @hw
5517  *  board private structure
5518  */
5519 static void
5520 ixgbe_configure_msix(struct rte_eth_dev *dev)
5521 {
5522         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5523         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5524         struct ixgbe_hw *hw =
5525                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5526         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5527         uint32_t vec = IXGBE_MISC_VEC_ID;
5528         uint32_t mask;
5529         uint32_t gpie;
5530
5531         /* won't configure msix register if no mapping is done
5532          * between intr vector and event fd
5533          */
5534         if (!rte_intr_dp_is_en(intr_handle))
5535                 return;
5536
5537         if (rte_intr_allow_others(intr_handle))
5538                 vec = base = IXGBE_RX_VEC_START;
5539
5540         /* setup GPIE for MSI-x mode */
5541         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5542         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5543                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5544         /* auto clearing and auto setting corresponding bits in EIMS
5545          * when MSI-X interrupt is triggered
5546          */
5547         if (hw->mac.type == ixgbe_mac_82598EB) {
5548                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5549         } else {
5550                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5551                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5552         }
5553         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5554
5555         /* Populate the IVAR table and set the ITR values to the
5556          * corresponding register.
5557          */
5558         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5559              queue_id++) {
5560                 /* by default, 1:1 mapping */
5561                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5562                 intr_handle->intr_vec[queue_id] = vec;
5563                 if (vec < base + intr_handle->nb_efd - 1)
5564                         vec++;
5565         }
5566
5567         switch (hw->mac.type) {
5568         case ixgbe_mac_82598EB:
5569                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5570                                    IXGBE_MISC_VEC_ID);
5571                 break;
5572         case ixgbe_mac_82599EB:
5573         case ixgbe_mac_X540:
5574                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5575                 break;
5576         default:
5577                 break;
5578         }
5579         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5580                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5581
5582         /* set up to autoclear timer, and the vectors */
5583         mask = IXGBE_EIMS_ENABLE_MASK;
5584         mask &= ~(IXGBE_EIMS_OTHER |
5585                   IXGBE_EIMS_MAILBOX |
5586                   IXGBE_EIMS_LSC);
5587
5588         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5589 }
5590
5591 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5592         uint16_t queue_idx, uint16_t tx_rate)
5593 {
5594         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5595         uint32_t rf_dec, rf_int;
5596         uint32_t bcnrc_val;
5597         uint16_t link_speed = dev->data->dev_link.link_speed;
5598
5599         if (queue_idx >= hw->mac.max_tx_queues)
5600                 return -EINVAL;
5601
5602         if (tx_rate != 0) {
5603                 /* Calculate the rate factor values to set */
5604                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5605                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5606                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5607
5608                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5609                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5610                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5611                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5612         } else {
5613                 bcnrc_val = 0;
5614         }
5615
5616         /*
5617          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5618          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5619          * set as 0x4.
5620          */
5621         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5622                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5623                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5624                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5625                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5626         else
5627                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5628                         IXGBE_MMW_SIZE_DEFAULT);
5629
5630         /* Set RTTBCNRC of queue X */
5631         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5632         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5633         IXGBE_WRITE_FLUSH(hw);
5634
5635         return 0;
5636 }
5637
5638 static int
5639 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5640                      __attribute__((unused)) uint32_t index,
5641                      __attribute__((unused)) uint32_t pool)
5642 {
5643         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5644         int diag;
5645
5646         /*
5647          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5648          * operation. Trap this case to avoid exhausting the [very limited]
5649          * set of PF resources used to store VF MAC addresses.
5650          */
5651         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5652                 return -1;
5653         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5654         if (diag != 0)
5655                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5656                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5657                             mac_addr->addr_bytes[0],
5658                             mac_addr->addr_bytes[1],
5659                             mac_addr->addr_bytes[2],
5660                             mac_addr->addr_bytes[3],
5661                             mac_addr->addr_bytes[4],
5662                             mac_addr->addr_bytes[5],
5663                             diag);
5664         return diag;
5665 }
5666
5667 static void
5668 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5669 {
5670         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5671         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5672         struct ether_addr *mac_addr;
5673         uint32_t i;
5674         int diag;
5675
5676         /*
5677          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5678          * not support the deletion of a given MAC address.
5679          * Instead, it imposes to delete all MAC addresses, then to add again
5680          * all MAC addresses with the exception of the one to be deleted.
5681          */
5682         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5683
5684         /*
5685          * Add again all MAC addresses, with the exception of the deleted one
5686          * and of the permanent MAC address.
5687          */
5688         for (i = 0, mac_addr = dev->data->mac_addrs;
5689              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5690                 /* Skip the deleted MAC address */
5691                 if (i == index)
5692                         continue;
5693                 /* Skip NULL MAC addresses */
5694                 if (is_zero_ether_addr(mac_addr))
5695                         continue;
5696                 /* Skip the permanent MAC address */
5697                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5698                         continue;
5699                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5700                 if (diag != 0)
5701                         PMD_DRV_LOG(ERR,
5702                                     "Adding again MAC address "
5703                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5704                                     "diag=%d",
5705                                     mac_addr->addr_bytes[0],
5706                                     mac_addr->addr_bytes[1],
5707                                     mac_addr->addr_bytes[2],
5708                                     mac_addr->addr_bytes[3],
5709                                     mac_addr->addr_bytes[4],
5710                                     mac_addr->addr_bytes[5],
5711                                     diag);
5712         }
5713 }
5714
5715 static void
5716 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5717 {
5718         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5719
5720         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5721 }
5722
5723 int
5724 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5725                         struct rte_eth_syn_filter *filter,
5726                         bool add)
5727 {
5728         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5729         struct ixgbe_filter_info *filter_info =
5730                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5731         uint32_t syn_info;
5732         uint32_t synqf;
5733
5734         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5735                 return -EINVAL;
5736
5737         syn_info = filter_info->syn_info;
5738
5739         if (add) {
5740                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5741                         return -EINVAL;
5742                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5743                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5744
5745                 if (filter->hig_pri)
5746                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5747                 else
5748                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5749         } else {
5750                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5751                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5752                         return -ENOENT;
5753                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5754         }
5755
5756         filter_info->syn_info = synqf;
5757         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5758         IXGBE_WRITE_FLUSH(hw);
5759         return 0;
5760 }
5761
5762 static int
5763 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5764                         struct rte_eth_syn_filter *filter)
5765 {
5766         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5767         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5768
5769         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5770                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5771                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5772                 return 0;
5773         }
5774         return -ENOENT;
5775 }
5776
5777 static int
5778 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5779                         enum rte_filter_op filter_op,
5780                         void *arg)
5781 {
5782         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5783         int ret;
5784
5785         MAC_TYPE_FILTER_SUP(hw->mac.type);
5786
5787         if (filter_op == RTE_ETH_FILTER_NOP)
5788                 return 0;
5789
5790         if (arg == NULL) {
5791                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5792                             filter_op);
5793                 return -EINVAL;
5794         }
5795
5796         switch (filter_op) {
5797         case RTE_ETH_FILTER_ADD:
5798                 ret = ixgbe_syn_filter_set(dev,
5799                                 (struct rte_eth_syn_filter *)arg,
5800                                 TRUE);
5801                 break;
5802         case RTE_ETH_FILTER_DELETE:
5803                 ret = ixgbe_syn_filter_set(dev,
5804                                 (struct rte_eth_syn_filter *)arg,
5805                                 FALSE);
5806                 break;
5807         case RTE_ETH_FILTER_GET:
5808                 ret = ixgbe_syn_filter_get(dev,
5809                                 (struct rte_eth_syn_filter *)arg);
5810                 break;
5811         default:
5812                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
5813                 ret = -EINVAL;
5814                 break;
5815         }
5816
5817         return ret;
5818 }
5819
5820
5821 static inline enum ixgbe_5tuple_protocol
5822 convert_protocol_type(uint8_t protocol_value)
5823 {
5824         if (protocol_value == IPPROTO_TCP)
5825                 return IXGBE_FILTER_PROTOCOL_TCP;
5826         else if (protocol_value == IPPROTO_UDP)
5827                 return IXGBE_FILTER_PROTOCOL_UDP;
5828         else if (protocol_value == IPPROTO_SCTP)
5829                 return IXGBE_FILTER_PROTOCOL_SCTP;
5830         else
5831                 return IXGBE_FILTER_PROTOCOL_NONE;
5832 }
5833
5834 /* inject a 5-tuple filter to HW */
5835 static inline void
5836 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
5837                            struct ixgbe_5tuple_filter *filter)
5838 {
5839         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5840         int i;
5841         uint32_t ftqf, sdpqf;
5842         uint32_t l34timir = 0;
5843         uint8_t mask = 0xff;
5844
5845         i = filter->index;
5846
5847         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5848                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5849         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5850
5851         ftqf = (uint32_t)(filter->filter_info.proto &
5852                 IXGBE_FTQF_PROTOCOL_MASK);
5853         ftqf |= (uint32_t)((filter->filter_info.priority &
5854                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5855         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5856                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5857         if (filter->filter_info.dst_ip_mask == 0)
5858                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5859         if (filter->filter_info.src_port_mask == 0)
5860                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5861         if (filter->filter_info.dst_port_mask == 0)
5862                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5863         if (filter->filter_info.proto_mask == 0)
5864                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5865         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5866         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5867         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5868
5869         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5870         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5871         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5872         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5873
5874         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5875         l34timir |= (uint32_t)(filter->queue <<
5876                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5877         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5878 }
5879
5880 /*
5881  * add a 5tuple filter
5882  *
5883  * @param
5884  * dev: Pointer to struct rte_eth_dev.
5885  * index: the index the filter allocates.
5886  * filter: ponter to the filter that will be added.
5887  * rx_queue: the queue id the filter assigned to.
5888  *
5889  * @return
5890  *    - On success, zero.
5891  *    - On failure, a negative value.
5892  */
5893 static int
5894 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5895                         struct ixgbe_5tuple_filter *filter)
5896 {
5897         struct ixgbe_filter_info *filter_info =
5898                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5899         int i, idx, shift;
5900
5901         /*
5902          * look for an unused 5tuple filter index,
5903          * and insert the filter to list.
5904          */
5905         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5906                 idx = i / (sizeof(uint32_t) * NBBY);
5907                 shift = i % (sizeof(uint32_t) * NBBY);
5908                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5909                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5910                         filter->index = i;
5911                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5912                                           filter,
5913                                           entries);
5914                         break;
5915                 }
5916         }
5917         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5918                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5919                 return -ENOSYS;
5920         }
5921
5922         ixgbe_inject_5tuple_filter(dev, filter);
5923
5924         return 0;
5925 }
5926
5927 /*
5928  * remove a 5tuple filter
5929  *
5930  * @param
5931  * dev: Pointer to struct rte_eth_dev.
5932  * filter: the pointer of the filter will be removed.
5933  */
5934 static void
5935 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5936                         struct ixgbe_5tuple_filter *filter)
5937 {
5938         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5939         struct ixgbe_filter_info *filter_info =
5940                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5941         uint16_t index = filter->index;
5942
5943         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5944                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5945         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5946         rte_free(filter);
5947
5948         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5949         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5950         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5951         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5952         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5953 }
5954
5955 static int
5956 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5957 {
5958         struct ixgbe_hw *hw;
5959         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5960         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
5961
5962         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5963
5964         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5965                 return -EINVAL;
5966
5967         /* refuse mtu that requires the support of scattered packets when this
5968          * feature has not been enabled before.
5969          */
5970         if (!rx_conf->enable_scatter &&
5971             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5972              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5973                 return -EINVAL;
5974
5975         /*
5976          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5977          * request of the version 2.0 of the mailbox API.
5978          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5979          * of the mailbox API.
5980          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5981          * prior to 3.11.33 which contains the following change:
5982          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5983          */
5984         ixgbevf_rlpml_set_vf(hw, max_frame);
5985
5986         /* update max frame size */
5987         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5988         return 0;
5989 }
5990
5991 static inline struct ixgbe_5tuple_filter *
5992 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5993                         struct ixgbe_5tuple_filter_info *key)
5994 {
5995         struct ixgbe_5tuple_filter *it;
5996
5997         TAILQ_FOREACH(it, filter_list, entries) {
5998                 if (memcmp(key, &it->filter_info,
5999                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6000                         return it;
6001                 }
6002         }
6003         return NULL;
6004 }
6005
6006 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6007 static inline int
6008 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6009                         struct ixgbe_5tuple_filter_info *filter_info)
6010 {
6011         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6012                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6013                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6014                 return -EINVAL;
6015
6016         switch (filter->dst_ip_mask) {
6017         case UINT32_MAX:
6018                 filter_info->dst_ip_mask = 0;
6019                 filter_info->dst_ip = filter->dst_ip;
6020                 break;
6021         case 0:
6022                 filter_info->dst_ip_mask = 1;
6023                 break;
6024         default:
6025                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6026                 return -EINVAL;
6027         }
6028
6029         switch (filter->src_ip_mask) {
6030         case UINT32_MAX:
6031                 filter_info->src_ip_mask = 0;
6032                 filter_info->src_ip = filter->src_ip;
6033                 break;
6034         case 0:
6035                 filter_info->src_ip_mask = 1;
6036                 break;
6037         default:
6038                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6039                 return -EINVAL;
6040         }
6041
6042         switch (filter->dst_port_mask) {
6043         case UINT16_MAX:
6044                 filter_info->dst_port_mask = 0;
6045                 filter_info->dst_port = filter->dst_port;
6046                 break;
6047         case 0:
6048                 filter_info->dst_port_mask = 1;
6049                 break;
6050         default:
6051                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6052                 return -EINVAL;
6053         }
6054
6055         switch (filter->src_port_mask) {
6056         case UINT16_MAX:
6057                 filter_info->src_port_mask = 0;
6058                 filter_info->src_port = filter->src_port;
6059                 break;
6060         case 0:
6061                 filter_info->src_port_mask = 1;
6062                 break;
6063         default:
6064                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6065                 return -EINVAL;
6066         }
6067
6068         switch (filter->proto_mask) {
6069         case UINT8_MAX:
6070                 filter_info->proto_mask = 0;
6071                 filter_info->proto =
6072                         convert_protocol_type(filter->proto);
6073                 break;
6074         case 0:
6075                 filter_info->proto_mask = 1;
6076                 break;
6077         default:
6078                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6079                 return -EINVAL;
6080         }
6081
6082         filter_info->priority = (uint8_t)filter->priority;
6083         return 0;
6084 }
6085
6086 /*
6087  * add or delete a ntuple filter
6088  *
6089  * @param
6090  * dev: Pointer to struct rte_eth_dev.
6091  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6092  * add: if true, add filter, if false, remove filter
6093  *
6094  * @return
6095  *    - On success, zero.
6096  *    - On failure, a negative value.
6097  */
6098 int
6099 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6100                         struct rte_eth_ntuple_filter *ntuple_filter,
6101                         bool add)
6102 {
6103         struct ixgbe_filter_info *filter_info =
6104                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6105         struct ixgbe_5tuple_filter_info filter_5tuple;
6106         struct ixgbe_5tuple_filter *filter;
6107         int ret;
6108
6109         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6110                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6111                 return -EINVAL;
6112         }
6113
6114         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6115         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6116         if (ret < 0)
6117                 return ret;
6118
6119         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6120                                          &filter_5tuple);
6121         if (filter != NULL && add) {
6122                 PMD_DRV_LOG(ERR, "filter exists.");
6123                 return -EEXIST;
6124         }
6125         if (filter == NULL && !add) {
6126                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6127                 return -ENOENT;
6128         }
6129
6130         if (add) {
6131                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6132                                 sizeof(struct ixgbe_5tuple_filter), 0);
6133                 if (filter == NULL)
6134                         return -ENOMEM;
6135                 (void)rte_memcpy(&filter->filter_info,
6136                                  &filter_5tuple,
6137                                  sizeof(struct ixgbe_5tuple_filter_info));
6138                 filter->queue = ntuple_filter->queue;
6139                 ret = ixgbe_add_5tuple_filter(dev, filter);
6140                 if (ret < 0) {
6141                         rte_free(filter);
6142                         return ret;
6143                 }
6144         } else
6145                 ixgbe_remove_5tuple_filter(dev, filter);
6146
6147         return 0;
6148 }
6149
6150 /*
6151  * get a ntuple filter
6152  *
6153  * @param
6154  * dev: Pointer to struct rte_eth_dev.
6155  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6156  *
6157  * @return
6158  *    - On success, zero.
6159  *    - On failure, a negative value.
6160  */
6161 static int
6162 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6163                         struct rte_eth_ntuple_filter *ntuple_filter)
6164 {
6165         struct ixgbe_filter_info *filter_info =
6166                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6167         struct ixgbe_5tuple_filter_info filter_5tuple;
6168         struct ixgbe_5tuple_filter *filter;
6169         int ret;
6170
6171         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6172                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6173                 return -EINVAL;
6174         }
6175
6176         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6177         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6178         if (ret < 0)
6179                 return ret;
6180
6181         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6182                                          &filter_5tuple);
6183         if (filter == NULL) {
6184                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6185                 return -ENOENT;
6186         }
6187         ntuple_filter->queue = filter->queue;
6188         return 0;
6189 }
6190
6191 /*
6192  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6193  * @dev: pointer to rte_eth_dev structure
6194  * @filter_op:operation will be taken.
6195  * @arg: a pointer to specific structure corresponding to the filter_op
6196  *
6197  * @return
6198  *    - On success, zero.
6199  *    - On failure, a negative value.
6200  */
6201 static int
6202 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6203                                 enum rte_filter_op filter_op,
6204                                 void *arg)
6205 {
6206         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6207         int ret;
6208
6209         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6210
6211         if (filter_op == RTE_ETH_FILTER_NOP)
6212                 return 0;
6213
6214         if (arg == NULL) {
6215                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6216                             filter_op);
6217                 return -EINVAL;
6218         }
6219
6220         switch (filter_op) {
6221         case RTE_ETH_FILTER_ADD:
6222                 ret = ixgbe_add_del_ntuple_filter(dev,
6223                         (struct rte_eth_ntuple_filter *)arg,
6224                         TRUE);
6225                 break;
6226         case RTE_ETH_FILTER_DELETE:
6227                 ret = ixgbe_add_del_ntuple_filter(dev,
6228                         (struct rte_eth_ntuple_filter *)arg,
6229                         FALSE);
6230                 break;
6231         case RTE_ETH_FILTER_GET:
6232                 ret = ixgbe_get_ntuple_filter(dev,
6233                         (struct rte_eth_ntuple_filter *)arg);
6234                 break;
6235         default:
6236                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6237                 ret = -EINVAL;
6238                 break;
6239         }
6240         return ret;
6241 }
6242
6243 int
6244 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6245                         struct rte_eth_ethertype_filter *filter,
6246                         bool add)
6247 {
6248         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6249         struct ixgbe_filter_info *filter_info =
6250                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6251         uint32_t etqf = 0;
6252         uint32_t etqs = 0;
6253         int ret;
6254         struct ixgbe_ethertype_filter ethertype_filter;
6255
6256         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6257                 return -EINVAL;
6258
6259         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6260                 filter->ether_type == ETHER_TYPE_IPv6) {
6261                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6262                         " ethertype filter.", filter->ether_type);
6263                 return -EINVAL;
6264         }
6265
6266         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6267                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6268                 return -EINVAL;
6269         }
6270         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6271                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6272                 return -EINVAL;
6273         }
6274
6275         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6276         if (ret >= 0 && add) {
6277                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6278                             filter->ether_type);
6279                 return -EEXIST;
6280         }
6281         if (ret < 0 && !add) {
6282                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6283                             filter->ether_type);
6284                 return -ENOENT;
6285         }
6286
6287         if (add) {
6288                 etqf = IXGBE_ETQF_FILTER_EN;
6289                 etqf |= (uint32_t)filter->ether_type;
6290                 etqs |= (uint32_t)((filter->queue <<
6291                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6292                                     IXGBE_ETQS_RX_QUEUE);
6293                 etqs |= IXGBE_ETQS_QUEUE_EN;
6294
6295                 ethertype_filter.ethertype = filter->ether_type;
6296                 ethertype_filter.etqf = etqf;
6297                 ethertype_filter.etqs = etqs;
6298                 ethertype_filter.conf = FALSE;
6299                 ret = ixgbe_ethertype_filter_insert(filter_info,
6300                                                     &ethertype_filter);
6301                 if (ret < 0) {
6302                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6303                         return -ENOSPC;
6304                 }
6305         } else {
6306                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6307                 if (ret < 0)
6308                         return -ENOSYS;
6309         }
6310         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6311         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6312         IXGBE_WRITE_FLUSH(hw);
6313
6314         return 0;
6315 }
6316
6317 static int
6318 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6319                         struct rte_eth_ethertype_filter *filter)
6320 {
6321         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6322         struct ixgbe_filter_info *filter_info =
6323                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6324         uint32_t etqf, etqs;
6325         int ret;
6326
6327         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6328         if (ret < 0) {
6329                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6330                             filter->ether_type);
6331                 return -ENOENT;
6332         }
6333
6334         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6335         if (etqf & IXGBE_ETQF_FILTER_EN) {
6336                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6337                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6338                 filter->flags = 0;
6339                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6340                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6341                 return 0;
6342         }
6343         return -ENOENT;
6344 }
6345
6346 /*
6347  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6348  * @dev: pointer to rte_eth_dev structure
6349  * @filter_op:operation will be taken.
6350  * @arg: a pointer to specific structure corresponding to the filter_op
6351  */
6352 static int
6353 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6354                                 enum rte_filter_op filter_op,
6355                                 void *arg)
6356 {
6357         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6358         int ret;
6359
6360         MAC_TYPE_FILTER_SUP(hw->mac.type);
6361
6362         if (filter_op == RTE_ETH_FILTER_NOP)
6363                 return 0;
6364
6365         if (arg == NULL) {
6366                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6367                             filter_op);
6368                 return -EINVAL;
6369         }
6370
6371         switch (filter_op) {
6372         case RTE_ETH_FILTER_ADD:
6373                 ret = ixgbe_add_del_ethertype_filter(dev,
6374                         (struct rte_eth_ethertype_filter *)arg,
6375                         TRUE);
6376                 break;
6377         case RTE_ETH_FILTER_DELETE:
6378                 ret = ixgbe_add_del_ethertype_filter(dev,
6379                         (struct rte_eth_ethertype_filter *)arg,
6380                         FALSE);
6381                 break;
6382         case RTE_ETH_FILTER_GET:
6383                 ret = ixgbe_get_ethertype_filter(dev,
6384                         (struct rte_eth_ethertype_filter *)arg);
6385                 break;
6386         default:
6387                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6388                 ret = -EINVAL;
6389                 break;
6390         }
6391         return ret;
6392 }
6393
6394 static int
6395 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6396                      enum rte_filter_type filter_type,
6397                      enum rte_filter_op filter_op,
6398                      void *arg)
6399 {
6400         int ret = 0;
6401
6402         switch (filter_type) {
6403         case RTE_ETH_FILTER_NTUPLE:
6404                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6405                 break;
6406         case RTE_ETH_FILTER_ETHERTYPE:
6407                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6408                 break;
6409         case RTE_ETH_FILTER_SYN:
6410                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6411                 break;
6412         case RTE_ETH_FILTER_FDIR:
6413                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6414                 break;
6415         case RTE_ETH_FILTER_L2_TUNNEL:
6416                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6417                 break;
6418         case RTE_ETH_FILTER_GENERIC:
6419                 if (filter_op != RTE_ETH_FILTER_GET)
6420                         return -EINVAL;
6421                 *(const void **)arg = &ixgbe_flow_ops;
6422                 break;
6423         default:
6424                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6425                                                         filter_type);
6426                 ret = -EINVAL;
6427                 break;
6428         }
6429
6430         return ret;
6431 }
6432
6433 static u8 *
6434 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6435                         u8 **mc_addr_ptr, u32 *vmdq)
6436 {
6437         u8 *mc_addr;
6438
6439         *vmdq = 0;
6440         mc_addr = *mc_addr_ptr;
6441         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6442         return mc_addr;
6443 }
6444
6445 static int
6446 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6447                           struct ether_addr *mc_addr_set,
6448                           uint32_t nb_mc_addr)
6449 {
6450         struct ixgbe_hw *hw;
6451         u8 *mc_addr_list;
6452
6453         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6454         mc_addr_list = (u8 *)mc_addr_set;
6455         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6456                                          ixgbe_dev_addr_list_itr, TRUE);
6457 }
6458
6459 static uint64_t
6460 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6461 {
6462         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6463         uint64_t systime_cycles;
6464
6465         switch (hw->mac.type) {
6466         case ixgbe_mac_X550:
6467         case ixgbe_mac_X550EM_x:
6468         case ixgbe_mac_X550EM_a:
6469                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6470                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6471                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6472                                 * NSEC_PER_SEC;
6473                 break;
6474         default:
6475                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6476                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6477                                 << 32;
6478         }
6479
6480         return systime_cycles;
6481 }
6482
6483 static uint64_t
6484 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6485 {
6486         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6487         uint64_t rx_tstamp_cycles;
6488
6489         switch (hw->mac.type) {
6490         case ixgbe_mac_X550:
6491         case ixgbe_mac_X550EM_x:
6492         case ixgbe_mac_X550EM_a:
6493                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6494                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6495                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6496                                 * NSEC_PER_SEC;
6497                 break;
6498         default:
6499                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6500                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6501                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6502                                 << 32;
6503         }
6504
6505         return rx_tstamp_cycles;
6506 }
6507
6508 static uint64_t
6509 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6510 {
6511         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6512         uint64_t tx_tstamp_cycles;
6513
6514         switch (hw->mac.type) {
6515         case ixgbe_mac_X550:
6516         case ixgbe_mac_X550EM_x:
6517         case ixgbe_mac_X550EM_a:
6518                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6519                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6520                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6521                                 * NSEC_PER_SEC;
6522                 break;
6523         default:
6524                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6525                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6526                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6527                                 << 32;
6528         }
6529
6530         return tx_tstamp_cycles;
6531 }
6532
6533 static void
6534 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6535 {
6536         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6537         struct ixgbe_adapter *adapter =
6538                 (struct ixgbe_adapter *)dev->data->dev_private;
6539         struct rte_eth_link link;
6540         uint32_t incval = 0;
6541         uint32_t shift = 0;
6542
6543         /* Get current link speed. */
6544         memset(&link, 0, sizeof(link));
6545         ixgbe_dev_link_update(dev, 1);
6546         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6547
6548         switch (link.link_speed) {
6549         case ETH_SPEED_NUM_100M:
6550                 incval = IXGBE_INCVAL_100;
6551                 shift = IXGBE_INCVAL_SHIFT_100;
6552                 break;
6553         case ETH_SPEED_NUM_1G:
6554                 incval = IXGBE_INCVAL_1GB;
6555                 shift = IXGBE_INCVAL_SHIFT_1GB;
6556                 break;
6557         case ETH_SPEED_NUM_10G:
6558         default:
6559                 incval = IXGBE_INCVAL_10GB;
6560                 shift = IXGBE_INCVAL_SHIFT_10GB;
6561                 break;
6562         }
6563
6564         switch (hw->mac.type) {
6565         case ixgbe_mac_X550:
6566         case ixgbe_mac_X550EM_x:
6567         case ixgbe_mac_X550EM_a:
6568                 /* Independent of link speed. */
6569                 incval = 1;
6570                 /* Cycles read will be interpreted as ns. */
6571                 shift = 0;
6572                 /* Fall-through */
6573         case ixgbe_mac_X540:
6574                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6575                 break;
6576         case ixgbe_mac_82599EB:
6577                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6578                 shift -= IXGBE_INCVAL_SHIFT_82599;
6579                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6580                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6581                 break;
6582         default:
6583                 /* Not supported. */
6584                 return;
6585         }
6586
6587         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6588         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6589         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6590
6591         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6592         adapter->systime_tc.cc_shift = shift;
6593         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6594
6595         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6596         adapter->rx_tstamp_tc.cc_shift = shift;
6597         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6598
6599         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6600         adapter->tx_tstamp_tc.cc_shift = shift;
6601         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6602 }
6603
6604 static int
6605 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6606 {
6607         struct ixgbe_adapter *adapter =
6608                         (struct ixgbe_adapter *)dev->data->dev_private;
6609
6610         adapter->systime_tc.nsec += delta;
6611         adapter->rx_tstamp_tc.nsec += delta;
6612         adapter->tx_tstamp_tc.nsec += delta;
6613
6614         return 0;
6615 }
6616
6617 static int
6618 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6619 {
6620         uint64_t ns;
6621         struct ixgbe_adapter *adapter =
6622                         (struct ixgbe_adapter *)dev->data->dev_private;
6623
6624         ns = rte_timespec_to_ns(ts);
6625         /* Set the timecounters to a new value. */
6626         adapter->systime_tc.nsec = ns;
6627         adapter->rx_tstamp_tc.nsec = ns;
6628         adapter->tx_tstamp_tc.nsec = ns;
6629
6630         return 0;
6631 }
6632
6633 static int
6634 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6635 {
6636         uint64_t ns, systime_cycles;
6637         struct ixgbe_adapter *adapter =
6638                         (struct ixgbe_adapter *)dev->data->dev_private;
6639
6640         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6641         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6642         *ts = rte_ns_to_timespec(ns);
6643
6644         return 0;
6645 }
6646
6647 static int
6648 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6649 {
6650         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6651         uint32_t tsync_ctl;
6652         uint32_t tsauxc;
6653
6654         /* Stop the timesync system time. */
6655         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6656         /* Reset the timesync system time value. */
6657         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6658         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6659
6660         /* Enable system time for platforms where it isn't on by default. */
6661         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6662         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6663         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6664
6665         ixgbe_start_timecounters(dev);
6666
6667         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6668         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6669                         (ETHER_TYPE_1588 |
6670                          IXGBE_ETQF_FILTER_EN |
6671                          IXGBE_ETQF_1588));
6672
6673         /* Enable timestamping of received PTP packets. */
6674         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6675         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6676         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6677
6678         /* Enable timestamping of transmitted PTP packets. */
6679         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6680         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6681         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6682
6683         IXGBE_WRITE_FLUSH(hw);
6684
6685         return 0;
6686 }
6687
6688 static int
6689 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6690 {
6691         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6692         uint32_t tsync_ctl;
6693
6694         /* Disable timestamping of transmitted PTP packets. */
6695         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6696         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6697         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6698
6699         /* Disable timestamping of received PTP packets. */
6700         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6701         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6702         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6703
6704         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6705         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6706
6707         /* Stop incrementating the System Time registers. */
6708         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6709
6710         return 0;
6711 }
6712
6713 static int
6714 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6715                                  struct timespec *timestamp,
6716                                  uint32_t flags __rte_unused)
6717 {
6718         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6719         struct ixgbe_adapter *adapter =
6720                 (struct ixgbe_adapter *)dev->data->dev_private;
6721         uint32_t tsync_rxctl;
6722         uint64_t rx_tstamp_cycles;
6723         uint64_t ns;
6724
6725         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6726         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6727                 return -EINVAL;
6728
6729         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6730         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6731         *timestamp = rte_ns_to_timespec(ns);
6732
6733         return  0;
6734 }
6735
6736 static int
6737 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6738                                  struct timespec *timestamp)
6739 {
6740         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6741         struct ixgbe_adapter *adapter =
6742                 (struct ixgbe_adapter *)dev->data->dev_private;
6743         uint32_t tsync_txctl;
6744         uint64_t tx_tstamp_cycles;
6745         uint64_t ns;
6746
6747         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6748         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6749                 return -EINVAL;
6750
6751         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6752         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6753         *timestamp = rte_ns_to_timespec(ns);
6754
6755         return 0;
6756 }
6757
6758 static int
6759 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6760 {
6761         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6762         int count = 0;
6763         int g_ind = 0;
6764         const struct reg_info *reg_group;
6765         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6766                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6767
6768         while ((reg_group = reg_set[g_ind++]))
6769                 count += ixgbe_regs_group_count(reg_group);
6770
6771         return count;
6772 }
6773
6774 static int
6775 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6776 {
6777         int count = 0;
6778         int g_ind = 0;
6779         const struct reg_info *reg_group;
6780
6781         while ((reg_group = ixgbevf_regs[g_ind++]))
6782                 count += ixgbe_regs_group_count(reg_group);
6783
6784         return count;
6785 }
6786
6787 static int
6788 ixgbe_get_regs(struct rte_eth_dev *dev,
6789               struct rte_dev_reg_info *regs)
6790 {
6791         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6792         uint32_t *data = regs->data;
6793         int g_ind = 0;
6794         int count = 0;
6795         const struct reg_info *reg_group;
6796         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6797                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6798
6799         if (data == NULL) {
6800                 regs->length = ixgbe_get_reg_length(dev);
6801                 regs->width = sizeof(uint32_t);
6802                 return 0;
6803         }
6804
6805         /* Support only full register dump */
6806         if ((regs->length == 0) ||
6807             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6808                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6809                         hw->device_id;
6810                 while ((reg_group = reg_set[g_ind++]))
6811                         count += ixgbe_read_regs_group(dev, &data[count],
6812                                 reg_group);
6813                 return 0;
6814         }
6815
6816         return -ENOTSUP;
6817 }
6818
6819 static int
6820 ixgbevf_get_regs(struct rte_eth_dev *dev,
6821                 struct rte_dev_reg_info *regs)
6822 {
6823         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6824         uint32_t *data = regs->data;
6825         int g_ind = 0;
6826         int count = 0;
6827         const struct reg_info *reg_group;
6828
6829         if (data == NULL) {
6830                 regs->length = ixgbevf_get_reg_length(dev);
6831                 regs->width = sizeof(uint32_t);
6832                 return 0;
6833         }
6834
6835         /* Support only full register dump */
6836         if ((regs->length == 0) ||
6837             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6838                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6839                         hw->device_id;
6840                 while ((reg_group = ixgbevf_regs[g_ind++]))
6841                         count += ixgbe_read_regs_group(dev, &data[count],
6842                                                       reg_group);
6843                 return 0;
6844         }
6845
6846         return -ENOTSUP;
6847 }
6848
6849 static int
6850 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6851 {
6852         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6853
6854         /* Return unit is byte count */
6855         return hw->eeprom.word_size * 2;
6856 }
6857
6858 static int
6859 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6860                 struct rte_dev_eeprom_info *in_eeprom)
6861 {
6862         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6863         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6864         uint16_t *data = in_eeprom->data;
6865         int first, length;
6866
6867         first = in_eeprom->offset >> 1;
6868         length = in_eeprom->length >> 1;
6869         if ((first > hw->eeprom.word_size) ||
6870             ((first + length) > hw->eeprom.word_size))
6871                 return -EINVAL;
6872
6873         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6874
6875         return eeprom->ops.read_buffer(hw, first, length, data);
6876 }
6877
6878 static int
6879 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6880                 struct rte_dev_eeprom_info *in_eeprom)
6881 {
6882         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6883         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6884         uint16_t *data = in_eeprom->data;
6885         int first, length;
6886
6887         first = in_eeprom->offset >> 1;
6888         length = in_eeprom->length >> 1;
6889         if ((first > hw->eeprom.word_size) ||
6890             ((first + length) > hw->eeprom.word_size))
6891                 return -EINVAL;
6892
6893         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6894
6895         return eeprom->ops.write_buffer(hw,  first, length, data);
6896 }
6897
6898 uint16_t
6899 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6900         switch (mac_type) {
6901         case ixgbe_mac_X550:
6902         case ixgbe_mac_X550EM_x:
6903         case ixgbe_mac_X550EM_a:
6904                 return ETH_RSS_RETA_SIZE_512;
6905         case ixgbe_mac_X550_vf:
6906         case ixgbe_mac_X550EM_x_vf:
6907         case ixgbe_mac_X550EM_a_vf:
6908                 return ETH_RSS_RETA_SIZE_64;
6909         default:
6910                 return ETH_RSS_RETA_SIZE_128;
6911         }
6912 }
6913
6914 uint32_t
6915 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6916         switch (mac_type) {
6917         case ixgbe_mac_X550:
6918         case ixgbe_mac_X550EM_x:
6919         case ixgbe_mac_X550EM_a:
6920                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6921                         return IXGBE_RETA(reta_idx >> 2);
6922                 else
6923                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6924         case ixgbe_mac_X550_vf:
6925         case ixgbe_mac_X550EM_x_vf:
6926         case ixgbe_mac_X550EM_a_vf:
6927                 return IXGBE_VFRETA(reta_idx >> 2);
6928         default:
6929                 return IXGBE_RETA(reta_idx >> 2);
6930         }
6931 }
6932
6933 uint32_t
6934 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6935         switch (mac_type) {
6936         case ixgbe_mac_X550_vf:
6937         case ixgbe_mac_X550EM_x_vf:
6938         case ixgbe_mac_X550EM_a_vf:
6939                 return IXGBE_VFMRQC;
6940         default:
6941                 return IXGBE_MRQC;
6942         }
6943 }
6944
6945 uint32_t
6946 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6947         switch (mac_type) {
6948         case ixgbe_mac_X550_vf:
6949         case ixgbe_mac_X550EM_x_vf:
6950         case ixgbe_mac_X550EM_a_vf:
6951                 return IXGBE_VFRSSRK(i);
6952         default:
6953                 return IXGBE_RSSRK(i);
6954         }
6955 }
6956
6957 bool
6958 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6959         switch (mac_type) {
6960         case ixgbe_mac_82599_vf:
6961         case ixgbe_mac_X540_vf:
6962                 return 0;
6963         default:
6964                 return 1;
6965         }
6966 }
6967
6968 static int
6969 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6970                         struct rte_eth_dcb_info *dcb_info)
6971 {
6972         struct ixgbe_dcb_config *dcb_config =
6973                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6974         struct ixgbe_dcb_tc_config *tc;
6975         uint8_t i, j;
6976
6977         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6978                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6979         else
6980                 dcb_info->nb_tcs = 1;
6981
6982         if (dcb_config->vt_mode) { /* vt is enabled*/
6983                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6984                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6985                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6986                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6987                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6988                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6989                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6990                                                 i * dcb_info->nb_tcs + j;
6991                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6992                                 dcb_info->tc_queue.tc_txq[i][j].base =
6993                                                 i * dcb_info->nb_tcs + j;
6994                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6995                         }
6996                 }
6997         } else { /* vt is disabled*/
6998                 struct rte_eth_dcb_rx_conf *rx_conf =
6999                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7000                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7001                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7002                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7003                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7004                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7005                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7006                         }
7007                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7008                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7009                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7010                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7011                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7012                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7013                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7014                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7015                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7016                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7017                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7018                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7019                         }
7020                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7021                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7022                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7023                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7024                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7025                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7026                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7027                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7028                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7029                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7030                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7031                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7032                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7033                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7034                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7035                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7036                 }
7037         }
7038         for (i = 0; i < dcb_info->nb_tcs; i++) {
7039                 tc = &dcb_config->tc_config[i];
7040                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7041         }
7042         return 0;
7043 }
7044
7045 /* Update e-tag ether type */
7046 static int
7047 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7048                             uint16_t ether_type)
7049 {
7050         uint32_t etag_etype;
7051
7052         if (hw->mac.type != ixgbe_mac_X550 &&
7053             hw->mac.type != ixgbe_mac_X550EM_x &&
7054             hw->mac.type != ixgbe_mac_X550EM_a) {
7055                 return -ENOTSUP;
7056         }
7057
7058         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7059         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7060         etag_etype |= ether_type;
7061         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7062         IXGBE_WRITE_FLUSH(hw);
7063
7064         return 0;
7065 }
7066
7067 /* Config l2 tunnel ether type */
7068 static int
7069 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7070                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7071 {
7072         int ret = 0;
7073         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7074         struct ixgbe_l2_tn_info *l2_tn_info =
7075                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7076
7077         if (l2_tunnel == NULL)
7078                 return -EINVAL;
7079
7080         switch (l2_tunnel->l2_tunnel_type) {
7081         case RTE_L2_TUNNEL_TYPE_E_TAG:
7082                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7083                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7084                 break;
7085         default:
7086                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7087                 ret = -EINVAL;
7088                 break;
7089         }
7090
7091         return ret;
7092 }
7093
7094 /* Enable e-tag tunnel */
7095 static int
7096 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7097 {
7098         uint32_t etag_etype;
7099
7100         if (hw->mac.type != ixgbe_mac_X550 &&
7101             hw->mac.type != ixgbe_mac_X550EM_x &&
7102             hw->mac.type != ixgbe_mac_X550EM_a) {
7103                 return -ENOTSUP;
7104         }
7105
7106         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7107         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7108         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7109         IXGBE_WRITE_FLUSH(hw);
7110
7111         return 0;
7112 }
7113
7114 /* Enable l2 tunnel */
7115 static int
7116 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7117                            enum rte_eth_tunnel_type l2_tunnel_type)
7118 {
7119         int ret = 0;
7120         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7121         struct ixgbe_l2_tn_info *l2_tn_info =
7122                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7123
7124         switch (l2_tunnel_type) {
7125         case RTE_L2_TUNNEL_TYPE_E_TAG:
7126                 l2_tn_info->e_tag_en = TRUE;
7127                 ret = ixgbe_e_tag_enable(hw);
7128                 break;
7129         default:
7130                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7131                 ret = -EINVAL;
7132                 break;
7133         }
7134
7135         return ret;
7136 }
7137
7138 /* Disable e-tag tunnel */
7139 static int
7140 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7141 {
7142         uint32_t etag_etype;
7143
7144         if (hw->mac.type != ixgbe_mac_X550 &&
7145             hw->mac.type != ixgbe_mac_X550EM_x &&
7146             hw->mac.type != ixgbe_mac_X550EM_a) {
7147                 return -ENOTSUP;
7148         }
7149
7150         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7151         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7152         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7153         IXGBE_WRITE_FLUSH(hw);
7154
7155         return 0;
7156 }
7157
7158 /* Disable l2 tunnel */
7159 static int
7160 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7161                             enum rte_eth_tunnel_type l2_tunnel_type)
7162 {
7163         int ret = 0;
7164         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7165         struct ixgbe_l2_tn_info *l2_tn_info =
7166                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7167
7168         switch (l2_tunnel_type) {
7169         case RTE_L2_TUNNEL_TYPE_E_TAG:
7170                 l2_tn_info->e_tag_en = FALSE;
7171                 ret = ixgbe_e_tag_disable(hw);
7172                 break;
7173         default:
7174                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7175                 ret = -EINVAL;
7176                 break;
7177         }
7178
7179         return ret;
7180 }
7181
7182 static int
7183 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7184                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7185 {
7186         int ret = 0;
7187         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7188         uint32_t i, rar_entries;
7189         uint32_t rar_low, rar_high;
7190
7191         if (hw->mac.type != ixgbe_mac_X550 &&
7192             hw->mac.type != ixgbe_mac_X550EM_x &&
7193             hw->mac.type != ixgbe_mac_X550EM_a) {
7194                 return -ENOTSUP;
7195         }
7196
7197         rar_entries = ixgbe_get_num_rx_addrs(hw);
7198
7199         for (i = 1; i < rar_entries; i++) {
7200                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7201                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7202                 if ((rar_high & IXGBE_RAH_AV) &&
7203                     (rar_high & IXGBE_RAH_ADTYPE) &&
7204                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7205                      l2_tunnel->tunnel_id)) {
7206                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7207                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7208
7209                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7210
7211                         return ret;
7212                 }
7213         }
7214
7215         return ret;
7216 }
7217
7218 static int
7219 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7220                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7221 {
7222         int ret = 0;
7223         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7224         uint32_t i, rar_entries;
7225         uint32_t rar_low, rar_high;
7226
7227         if (hw->mac.type != ixgbe_mac_X550 &&
7228             hw->mac.type != ixgbe_mac_X550EM_x &&
7229             hw->mac.type != ixgbe_mac_X550EM_a) {
7230                 return -ENOTSUP;
7231         }
7232
7233         /* One entry for one tunnel. Try to remove potential existing entry. */
7234         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7235
7236         rar_entries = ixgbe_get_num_rx_addrs(hw);
7237
7238         for (i = 1; i < rar_entries; i++) {
7239                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7240                 if (rar_high & IXGBE_RAH_AV) {
7241                         continue;
7242                 } else {
7243                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7244                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7245                         rar_low = l2_tunnel->tunnel_id;
7246
7247                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7248                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7249
7250                         return ret;
7251                 }
7252         }
7253
7254         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7255                      " Please remove a rule before adding a new one.");
7256         return -EINVAL;
7257 }
7258
7259 static inline struct ixgbe_l2_tn_filter *
7260 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7261                           struct ixgbe_l2_tn_key *key)
7262 {
7263         int ret;
7264
7265         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7266         if (ret < 0)
7267                 return NULL;
7268
7269         return l2_tn_info->hash_map[ret];
7270 }
7271
7272 static inline int
7273 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7274                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7275 {
7276         int ret;
7277
7278         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7279                                &l2_tn_filter->key);
7280
7281         if (ret < 0) {
7282                 PMD_DRV_LOG(ERR,
7283                             "Failed to insert L2 tunnel filter"
7284                             " to hash table %d!",
7285                             ret);
7286                 return ret;
7287         }
7288
7289         l2_tn_info->hash_map[ret] = l2_tn_filter;
7290
7291         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7292
7293         return 0;
7294 }
7295
7296 static inline int
7297 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7298                           struct ixgbe_l2_tn_key *key)
7299 {
7300         int ret;
7301         struct ixgbe_l2_tn_filter *l2_tn_filter;
7302
7303         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7304
7305         if (ret < 0) {
7306                 PMD_DRV_LOG(ERR,
7307                             "No such L2 tunnel filter to delete %d!",
7308                             ret);
7309                 return ret;
7310         }
7311
7312         l2_tn_filter = l2_tn_info->hash_map[ret];
7313         l2_tn_info->hash_map[ret] = NULL;
7314
7315         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7316         rte_free(l2_tn_filter);
7317
7318         return 0;
7319 }
7320
7321 /* Add l2 tunnel filter */
7322 int
7323 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7324                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7325                                bool restore)
7326 {
7327         int ret;
7328         struct ixgbe_l2_tn_info *l2_tn_info =
7329                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7330         struct ixgbe_l2_tn_key key;
7331         struct ixgbe_l2_tn_filter *node;
7332
7333         if (!restore) {
7334                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7335                 key.tn_id = l2_tunnel->tunnel_id;
7336
7337                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7338
7339                 if (node) {
7340                         PMD_DRV_LOG(ERR,
7341                                     "The L2 tunnel filter already exists!");
7342                         return -EINVAL;
7343                 }
7344
7345                 node = rte_zmalloc("ixgbe_l2_tn",
7346                                    sizeof(struct ixgbe_l2_tn_filter),
7347                                    0);
7348                 if (!node)
7349                         return -ENOMEM;
7350
7351                 (void)rte_memcpy(&node->key,
7352                                  &key,
7353                                  sizeof(struct ixgbe_l2_tn_key));
7354                 node->pool = l2_tunnel->pool;
7355                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7356                 if (ret < 0) {
7357                         rte_free(node);
7358                         return ret;
7359                 }
7360         }
7361
7362         switch (l2_tunnel->l2_tunnel_type) {
7363         case RTE_L2_TUNNEL_TYPE_E_TAG:
7364                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7365                 break;
7366         default:
7367                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7368                 ret = -EINVAL;
7369                 break;
7370         }
7371
7372         if ((!restore) && (ret < 0))
7373                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7374
7375         return ret;
7376 }
7377
7378 /* Delete l2 tunnel filter */
7379 int
7380 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7381                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7382 {
7383         int ret;
7384         struct ixgbe_l2_tn_info *l2_tn_info =
7385                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7386         struct ixgbe_l2_tn_key key;
7387
7388         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7389         key.tn_id = l2_tunnel->tunnel_id;
7390         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7391         if (ret < 0)
7392                 return ret;
7393
7394         switch (l2_tunnel->l2_tunnel_type) {
7395         case RTE_L2_TUNNEL_TYPE_E_TAG:
7396                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7397                 break;
7398         default:
7399                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7400                 ret = -EINVAL;
7401                 break;
7402         }
7403
7404         return ret;
7405 }
7406
7407 /**
7408  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7409  * @dev: pointer to rte_eth_dev structure
7410  * @filter_op:operation will be taken.
7411  * @arg: a pointer to specific structure corresponding to the filter_op
7412  */
7413 static int
7414 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7415                                   enum rte_filter_op filter_op,
7416                                   void *arg)
7417 {
7418         int ret;
7419
7420         if (filter_op == RTE_ETH_FILTER_NOP)
7421                 return 0;
7422
7423         if (arg == NULL) {
7424                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7425                             filter_op);
7426                 return -EINVAL;
7427         }
7428
7429         switch (filter_op) {
7430         case RTE_ETH_FILTER_ADD:
7431                 ret = ixgbe_dev_l2_tunnel_filter_add
7432                         (dev,
7433                          (struct rte_eth_l2_tunnel_conf *)arg,
7434                          FALSE);
7435                 break;
7436         case RTE_ETH_FILTER_DELETE:
7437                 ret = ixgbe_dev_l2_tunnel_filter_del
7438                         (dev,
7439                          (struct rte_eth_l2_tunnel_conf *)arg);
7440                 break;
7441         default:
7442                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7443                 ret = -EINVAL;
7444                 break;
7445         }
7446         return ret;
7447 }
7448
7449 static int
7450 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7451 {
7452         int ret = 0;
7453         uint32_t ctrl;
7454         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7455
7456         if (hw->mac.type != ixgbe_mac_X550 &&
7457             hw->mac.type != ixgbe_mac_X550EM_x &&
7458             hw->mac.type != ixgbe_mac_X550EM_a) {
7459                 return -ENOTSUP;
7460         }
7461
7462         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7463         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7464         if (en)
7465                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7466         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7467
7468         return ret;
7469 }
7470
7471 /* Enable l2 tunnel forwarding */
7472 static int
7473 ixgbe_dev_l2_tunnel_forwarding_enable
7474         (struct rte_eth_dev *dev,
7475          enum rte_eth_tunnel_type l2_tunnel_type)
7476 {
7477         struct ixgbe_l2_tn_info *l2_tn_info =
7478                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7479         int ret = 0;
7480
7481         switch (l2_tunnel_type) {
7482         case RTE_L2_TUNNEL_TYPE_E_TAG:
7483                 l2_tn_info->e_tag_fwd_en = TRUE;
7484                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7485                 break;
7486         default:
7487                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7488                 ret = -EINVAL;
7489                 break;
7490         }
7491
7492         return ret;
7493 }
7494
7495 /* Disable l2 tunnel forwarding */
7496 static int
7497 ixgbe_dev_l2_tunnel_forwarding_disable
7498         (struct rte_eth_dev *dev,
7499          enum rte_eth_tunnel_type l2_tunnel_type)
7500 {
7501         struct ixgbe_l2_tn_info *l2_tn_info =
7502                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7503         int ret = 0;
7504
7505         switch (l2_tunnel_type) {
7506         case RTE_L2_TUNNEL_TYPE_E_TAG:
7507                 l2_tn_info->e_tag_fwd_en = FALSE;
7508                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7509                 break;
7510         default:
7511                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7512                 ret = -EINVAL;
7513                 break;
7514         }
7515
7516         return ret;
7517 }
7518
7519 static int
7520 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7521                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7522                              bool en)
7523 {
7524         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7525         int ret = 0;
7526         uint32_t vmtir, vmvir;
7527         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7528
7529         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7530                 PMD_DRV_LOG(ERR,
7531                             "VF id %u should be less than %u",
7532                             l2_tunnel->vf_id,
7533                             pci_dev->max_vfs);
7534                 return -EINVAL;
7535         }
7536
7537         if (hw->mac.type != ixgbe_mac_X550 &&
7538             hw->mac.type != ixgbe_mac_X550EM_x &&
7539             hw->mac.type != ixgbe_mac_X550EM_a) {
7540                 return -ENOTSUP;
7541         }
7542
7543         if (en)
7544                 vmtir = l2_tunnel->tunnel_id;
7545         else
7546                 vmtir = 0;
7547
7548         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7549
7550         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7551         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7552         if (en)
7553                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7554         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7555
7556         return ret;
7557 }
7558
7559 /* Enable l2 tunnel tag insertion */
7560 static int
7561 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7562                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7563 {
7564         int ret = 0;
7565
7566         switch (l2_tunnel->l2_tunnel_type) {
7567         case RTE_L2_TUNNEL_TYPE_E_TAG:
7568                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7569                 break;
7570         default:
7571                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7572                 ret = -EINVAL;
7573                 break;
7574         }
7575
7576         return ret;
7577 }
7578
7579 /* Disable l2 tunnel tag insertion */
7580 static int
7581 ixgbe_dev_l2_tunnel_insertion_disable
7582         (struct rte_eth_dev *dev,
7583          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7584 {
7585         int ret = 0;
7586
7587         switch (l2_tunnel->l2_tunnel_type) {
7588         case RTE_L2_TUNNEL_TYPE_E_TAG:
7589                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7590                 break;
7591         default:
7592                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7593                 ret = -EINVAL;
7594                 break;
7595         }
7596
7597         return ret;
7598 }
7599
7600 static int
7601 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7602                              bool en)
7603 {
7604         int ret = 0;
7605         uint32_t qde;
7606         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7607
7608         if (hw->mac.type != ixgbe_mac_X550 &&
7609             hw->mac.type != ixgbe_mac_X550EM_x &&
7610             hw->mac.type != ixgbe_mac_X550EM_a) {
7611                 return -ENOTSUP;
7612         }
7613
7614         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7615         if (en)
7616                 qde |= IXGBE_QDE_STRIP_TAG;
7617         else
7618                 qde &= ~IXGBE_QDE_STRIP_TAG;
7619         qde &= ~IXGBE_QDE_READ;
7620         qde |= IXGBE_QDE_WRITE;
7621         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7622
7623         return ret;
7624 }
7625
7626 /* Enable l2 tunnel tag stripping */
7627 static int
7628 ixgbe_dev_l2_tunnel_stripping_enable
7629         (struct rte_eth_dev *dev,
7630          enum rte_eth_tunnel_type l2_tunnel_type)
7631 {
7632         int ret = 0;
7633
7634         switch (l2_tunnel_type) {
7635         case RTE_L2_TUNNEL_TYPE_E_TAG:
7636                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7637                 break;
7638         default:
7639                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7640                 ret = -EINVAL;
7641                 break;
7642         }
7643
7644         return ret;
7645 }
7646
7647 /* Disable l2 tunnel tag stripping */
7648 static int
7649 ixgbe_dev_l2_tunnel_stripping_disable
7650         (struct rte_eth_dev *dev,
7651          enum rte_eth_tunnel_type l2_tunnel_type)
7652 {
7653         int ret = 0;
7654
7655         switch (l2_tunnel_type) {
7656         case RTE_L2_TUNNEL_TYPE_E_TAG:
7657                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7658                 break;
7659         default:
7660                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7661                 ret = -EINVAL;
7662                 break;
7663         }
7664
7665         return ret;
7666 }
7667
7668 /* Enable/disable l2 tunnel offload functions */
7669 static int
7670 ixgbe_dev_l2_tunnel_offload_set
7671         (struct rte_eth_dev *dev,
7672          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7673          uint32_t mask,
7674          uint8_t en)
7675 {
7676         int ret = 0;
7677
7678         if (l2_tunnel == NULL)
7679                 return -EINVAL;
7680
7681         ret = -EINVAL;
7682         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7683                 if (en)
7684                         ret = ixgbe_dev_l2_tunnel_enable(
7685                                 dev,
7686                                 l2_tunnel->l2_tunnel_type);
7687                 else
7688                         ret = ixgbe_dev_l2_tunnel_disable(
7689                                 dev,
7690                                 l2_tunnel->l2_tunnel_type);
7691         }
7692
7693         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7694                 if (en)
7695                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7696                                 dev,
7697                                 l2_tunnel);
7698                 else
7699                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7700                                 dev,
7701                                 l2_tunnel);
7702         }
7703
7704         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7705                 if (en)
7706                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7707                                 dev,
7708                                 l2_tunnel->l2_tunnel_type);
7709                 else
7710                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7711                                 dev,
7712                                 l2_tunnel->l2_tunnel_type);
7713         }
7714
7715         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7716                 if (en)
7717                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7718                                 dev,
7719                                 l2_tunnel->l2_tunnel_type);
7720                 else
7721                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7722                                 dev,
7723                                 l2_tunnel->l2_tunnel_type);
7724         }
7725
7726         return ret;
7727 }
7728
7729 static int
7730 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7731                         uint16_t port)
7732 {
7733         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7734         IXGBE_WRITE_FLUSH(hw);
7735
7736         return 0;
7737 }
7738
7739 /* There's only one register for VxLAN UDP port.
7740  * So, we cannot add several ports. Will update it.
7741  */
7742 static int
7743 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7744                      uint16_t port)
7745 {
7746         if (port == 0) {
7747                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7748                 return -EINVAL;
7749         }
7750
7751         return ixgbe_update_vxlan_port(hw, port);
7752 }
7753
7754 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7755  * UDP port, it must have a value.
7756  * So, will reset it to the original value 0.
7757  */
7758 static int
7759 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7760                      uint16_t port)
7761 {
7762         uint16_t cur_port;
7763
7764         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7765
7766         if (cur_port != port) {
7767                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7768                 return -EINVAL;
7769         }
7770
7771         return ixgbe_update_vxlan_port(hw, 0);
7772 }
7773
7774 /* Add UDP tunneling port */
7775 static int
7776 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7777                               struct rte_eth_udp_tunnel *udp_tunnel)
7778 {
7779         int ret = 0;
7780         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7781
7782         if (hw->mac.type != ixgbe_mac_X550 &&
7783             hw->mac.type != ixgbe_mac_X550EM_x &&
7784             hw->mac.type != ixgbe_mac_X550EM_a) {
7785                 return -ENOTSUP;
7786         }
7787
7788         if (udp_tunnel == NULL)
7789                 return -EINVAL;
7790
7791         switch (udp_tunnel->prot_type) {
7792         case RTE_TUNNEL_TYPE_VXLAN:
7793                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7794                 break;
7795
7796         case RTE_TUNNEL_TYPE_GENEVE:
7797         case RTE_TUNNEL_TYPE_TEREDO:
7798                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7799                 ret = -EINVAL;
7800                 break;
7801
7802         default:
7803                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7804                 ret = -EINVAL;
7805                 break;
7806         }
7807
7808         return ret;
7809 }
7810
7811 /* Remove UDP tunneling port */
7812 static int
7813 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7814                               struct rte_eth_udp_tunnel *udp_tunnel)
7815 {
7816         int ret = 0;
7817         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7818
7819         if (hw->mac.type != ixgbe_mac_X550 &&
7820             hw->mac.type != ixgbe_mac_X550EM_x &&
7821             hw->mac.type != ixgbe_mac_X550EM_a) {
7822                 return -ENOTSUP;
7823         }
7824
7825         if (udp_tunnel == NULL)
7826                 return -EINVAL;
7827
7828         switch (udp_tunnel->prot_type) {
7829         case RTE_TUNNEL_TYPE_VXLAN:
7830                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7831                 break;
7832         case RTE_TUNNEL_TYPE_GENEVE:
7833         case RTE_TUNNEL_TYPE_TEREDO:
7834                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7835                 ret = -EINVAL;
7836                 break;
7837         default:
7838                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7839                 ret = -EINVAL;
7840                 break;
7841         }
7842
7843         return ret;
7844 }
7845
7846 static void
7847 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7848 {
7849         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7850
7851         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7852 }
7853
7854 static void
7855 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7856 {
7857         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7858
7859         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
7860 }
7861
7862 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7863 {
7864         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7865         u32 in_msg = 0;
7866
7867         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7868                 return;
7869
7870         /* PF reset VF event */
7871         if (in_msg == IXGBE_PF_CONTROL_MSG)
7872                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
7873                                               NULL, NULL);
7874 }
7875
7876 static int
7877 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7878 {
7879         uint32_t eicr;
7880         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7881         struct ixgbe_interrupt *intr =
7882                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7883         ixgbevf_intr_disable(hw);
7884
7885         /* read-on-clear nic registers here */
7886         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7887         intr->flags = 0;
7888
7889         /* only one misc vector supported - mailbox */
7890         eicr &= IXGBE_VTEICR_MASK;
7891         if (eicr == IXGBE_MISC_VEC_ID)
7892                 intr->flags |= IXGBE_FLAG_MAILBOX;
7893
7894         return 0;
7895 }
7896
7897 static int
7898 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7899 {
7900         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7901         struct ixgbe_interrupt *intr =
7902                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7903
7904         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7905                 ixgbevf_mbx_process(dev);
7906                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7907         }
7908
7909         ixgbevf_intr_enable(hw);
7910
7911         return 0;
7912 }
7913
7914 static void
7915 ixgbevf_dev_interrupt_handler(void *param)
7916 {
7917         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7918
7919         ixgbevf_dev_interrupt_get_status(dev);
7920         ixgbevf_dev_interrupt_action(dev);
7921 }
7922
7923 /**
7924  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
7925  *  @hw: pointer to hardware structure
7926  *
7927  *  Stops the transmit data path and waits for the HW to internally empty
7928  *  the Tx security block
7929  **/
7930 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
7931 {
7932 #define IXGBE_MAX_SECTX_POLL 40
7933
7934         int i;
7935         int sectxreg;
7936
7937         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7938         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
7939         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7940         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
7941                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
7942                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
7943                         break;
7944                 /* Use interrupt-safe sleep just in case */
7945                 usec_delay(1000);
7946         }
7947
7948         /* For informational purposes only */
7949         if (i >= IXGBE_MAX_SECTX_POLL)
7950                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
7951                          "path fully disabled.  Continuing with init.");
7952
7953         return IXGBE_SUCCESS;
7954 }
7955
7956 /**
7957  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
7958  *  @hw: pointer to hardware structure
7959  *
7960  *  Enables the transmit data path.
7961  **/
7962 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
7963 {
7964         uint32_t sectxreg;
7965
7966         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7967         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
7968         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7969         IXGBE_WRITE_FLUSH(hw);
7970
7971         return IXGBE_SUCCESS;
7972 }
7973
7974 /* restore n-tuple filter */
7975 static inline void
7976 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
7977 {
7978         struct ixgbe_filter_info *filter_info =
7979                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7980         struct ixgbe_5tuple_filter *node;
7981
7982         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
7983                 ixgbe_inject_5tuple_filter(dev, node);
7984         }
7985 }
7986
7987 /* restore ethernet type filter */
7988 static inline void
7989 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
7990 {
7991         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7992         struct ixgbe_filter_info *filter_info =
7993                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7994         int i;
7995
7996         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
7997                 if (filter_info->ethertype_mask & (1 << i)) {
7998                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
7999                                         filter_info->ethertype_filters[i].etqf);
8000                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8001                                         filter_info->ethertype_filters[i].etqs);
8002                         IXGBE_WRITE_FLUSH(hw);
8003                 }
8004         }
8005 }
8006
8007 /* restore SYN filter */
8008 static inline void
8009 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8010 {
8011         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8012         struct ixgbe_filter_info *filter_info =
8013                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8014         uint32_t synqf;
8015
8016         synqf = filter_info->syn_info;
8017
8018         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8019                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8020                 IXGBE_WRITE_FLUSH(hw);
8021         }
8022 }
8023
8024 /* restore L2 tunnel filter */
8025 static inline void
8026 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8027 {
8028         struct ixgbe_l2_tn_info *l2_tn_info =
8029                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8030         struct ixgbe_l2_tn_filter *node;
8031         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8032
8033         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8034                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8035                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8036                 l2_tn_conf.pool           = node->pool;
8037                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8038         }
8039 }
8040
8041 static int
8042 ixgbe_filter_restore(struct rte_eth_dev *dev)
8043 {
8044         ixgbe_ntuple_filter_restore(dev);
8045         ixgbe_ethertype_filter_restore(dev);
8046         ixgbe_syn_filter_restore(dev);
8047         ixgbe_fdir_filter_restore(dev);
8048         ixgbe_l2_tn_filter_restore(dev);
8049
8050         return 0;
8051 }
8052
8053 static void
8054 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8055 {
8056         struct ixgbe_l2_tn_info *l2_tn_info =
8057                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8058         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8059
8060         if (l2_tn_info->e_tag_en)
8061                 (void)ixgbe_e_tag_enable(hw);
8062
8063         if (l2_tn_info->e_tag_fwd_en)
8064                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8065
8066         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8067 }
8068
8069 /* remove all the n-tuple filters */
8070 void
8071 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8072 {
8073         struct ixgbe_filter_info *filter_info =
8074                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8075         struct ixgbe_5tuple_filter *p_5tuple;
8076
8077         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8078                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8079 }
8080
8081 /* remove all the ether type filters */
8082 void
8083 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8084 {
8085         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8086         struct ixgbe_filter_info *filter_info =
8087                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8088         int i;
8089
8090         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8091                 if (filter_info->ethertype_mask & (1 << i) &&
8092                     !filter_info->ethertype_filters[i].conf) {
8093                         (void)ixgbe_ethertype_filter_remove(filter_info,
8094                                                             (uint8_t)i);
8095                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8096                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8097                         IXGBE_WRITE_FLUSH(hw);
8098                 }
8099         }
8100 }
8101
8102 /* remove the SYN filter */
8103 void
8104 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8105 {
8106         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8107         struct ixgbe_filter_info *filter_info =
8108                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8109
8110         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8111                 filter_info->syn_info = 0;
8112
8113                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8114                 IXGBE_WRITE_FLUSH(hw);
8115         }
8116 }
8117
8118 /* remove all the L2 tunnel filters */
8119 int
8120 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8121 {
8122         struct ixgbe_l2_tn_info *l2_tn_info =
8123                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8124         struct ixgbe_l2_tn_filter *l2_tn_filter;
8125         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8126         int ret = 0;
8127
8128         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8129                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8130                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8131                 l2_tn_conf.pool           = l2_tn_filter->pool;
8132                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8133                 if (ret < 0)
8134                         return ret;
8135         }
8136
8137         return 0;
8138 }
8139
8140 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8141 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8142 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8143 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8144 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8145 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");