drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153
 154 enum ixgbevf_xcast_modes {
 155         IXGBEVF_XCAST_MODE_NONE = 0,
 156         IXGBEVF_XCAST_MODE_MULTI,
 157         IXGBEVF_XCAST_MODE_ALLMULTI,
 158 };
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 163 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 164 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 165 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 166 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 167 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 172 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 173                                 int wait_to_complete);
 174 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 175                                 struct rte_eth_stats *stats);
 176 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 177                                 struct rte_eth_xstats *xstats, unsigned n);
 178 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 179                                   struct rte_eth_xstats *xstats, unsigned n);
 180 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 181 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 182 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 183                                              uint16_t queue_id,
 184                                              uint8_t stat_idx,
 185                                              uint8_t is_rx);
 186 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 187                                struct rte_eth_dev_info *dev_info);
 188 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                  struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 202 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 203 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 204 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 205 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 206
 207 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 208 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 209 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 210                                struct rte_eth_fc_conf *fc_conf);
 211 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 212                                struct rte_eth_fc_conf *fc_conf);
 213 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 214                 struct rte_eth_pfc_conf *pfc_conf);
 215 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 216                         struct rte_eth_rss_reta_entry64 *reta_conf,
 217                         uint16_t reta_size);
 218 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 222 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 224 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 226 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 227                 void *param);
 228 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 229 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 230                 uint32_t index, uint32_t pool);
 231 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 232 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 233                                            struct ether_addr *mac_addr);
 234 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 235
 236 /* For Virtual Function support */
 237 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 238 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 239 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 240 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 241 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 243 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 244 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 245 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 246                 struct rte_eth_stats *stats);
 247 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 248 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 249                 uint16_t vlan_id, int on);
 250 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 251                 uint16_t queue, int on);
 252 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 254 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 255                                             uint16_t queue_id);
 256 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 257                                              uint16_t queue_id);
 258 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 259                                  uint8_t queue, uint8_t msix_vector);
 260 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 261 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 263
 264 /* For Eth VMDQ APIs support */
 265 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 266                 ether_addr* mac_addr,uint8_t on);
 267 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 268 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 269                 uint16_t rx_mask, uint8_t on);
 270 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 271 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 272 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 273                 uint64_t pool_mask,uint8_t vlan_on);
 274 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 275                 struct rte_eth_mirror_conf *mirror_conf,
 276                 uint8_t rule_id, uint8_t on);
 277 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 278                 uint8_t rule_id);
 279 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 280                                           uint16_t queue_id);
 281 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 282                                            uint16_t queue_id);
 283 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 284                                uint8_t queue, uint8_t msix_vector);
 285 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 286
 287 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 288                 uint16_t queue_idx, uint16_t tx_rate);
 289 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 290                 uint16_t tx_rate, uint64_t q_msk);
 291
 292 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 293                                  struct ether_addr *mac_addr,
 294                                  uint32_t index, uint32_t pool);
 295 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 296 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 297                                              struct ether_addr *mac_addr);
 298 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 299                         struct rte_eth_syn_filter *filter,
 300                         bool add);
 301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 302                         struct rte_eth_syn_filter *filter);
 303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 304                         enum rte_filter_op filter_op,
 305                         void *arg);
 306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 307                         struct ixgbe_5tuple_filter *filter);
 308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 311                         struct rte_eth_ntuple_filter *filter,
 312                         bool add);
 313 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 314                                 enum rte_filter_op filter_op,
 315                                 void *arg);
 316 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 317                         struct rte_eth_ntuple_filter *filter);
 318 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 319                         struct rte_eth_ethertype_filter *filter,
 320                         bool add);
 321 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 322                                 enum rte_filter_op filter_op,
 323                                 void *arg);
 324 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 325                         struct rte_eth_ethertype_filter *filter);
 326 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 327                      enum rte_filter_type filter_type,
 328                      enum rte_filter_op filter_op,
 329                      void *arg);
 330 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 331
 332 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 333                                       struct ether_addr *mc_addr_set,
 334                                       uint32_t nb_mc_addr);
 335 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 336                                    struct rte_eth_dcb_info *dcb_info);
 337
 338 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 339 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 340                             struct rte_dev_reg_info *regs);
 341 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 342 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 343                                 struct rte_dev_eeprom_info *eeprom);
 344 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 345                                 struct rte_dev_eeprom_info *eeprom);
 346
 347 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 348 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 349                                 struct rte_dev_reg_info *regs);
 350
 351 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 352 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 354                                             struct timespec *timestamp,
 355                                             uint32_t flags);
 356 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 357                                             struct timespec *timestamp);
 358 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 359 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 360                                    struct timespec *timestamp);
 361 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 362                                    const struct timespec *timestamp);
 363
 364 static int ixgbe_dev_l2_tunnel_eth_type_conf
 365         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 366 static int ixgbe_dev_l2_tunnel_offload_set
 367         (struct rte_eth_dev *dev,
 368          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 369          uint32_t mask,
 370          uint8_t en);
 371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 372                                              enum rte_filter_op filter_op,
 373                                              void *arg);
 374
 375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 376                                          struct rte_eth_udp_tunnel *udp_tunnel);
 377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379
 380 /*
 381  * Define VF Stats MACRO for Non "cleared on read" register
 382  */
 383 #define UPDATE_VF_STAT(reg, last, cur)                          \
 384 {                                                               \
 385         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 386         cur += (latest - last) & UINT_MAX;                      \
 387         last = latest;                                          \
 388 }
 389
 390 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 391 {                                                                \
 392         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 393         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 394         u64 latest = ((new_msb << 32) | new_lsb);                \
 395         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 396         last = latest;                                           \
 397 }
 398
 399 #define IXGBE_SET_HWSTRIP(h, q) do{\
 400                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 401                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 402                 (h)->bitmap[idx] |= 1 << bit;\
 403         } while (0)
 404
 405 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 406                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 407                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 408                 (h)->bitmap[idx] &= ~(1 << bit);\
 409         } while (0)
 410
 411 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 412                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 413                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 414                 (r) = (h)->bitmap[idx] >> bit & 1;\
 415         } while (0)
 416
 417 /*
 418  * The set of PCI devices this driver supports
 419  */
 420 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 421
 422 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 423 #include "rte_pci_dev_ids.h"
 424
 425 { .vendor_id = 0, /* sentinel */ },
 426 };
 427
 428
 429 /*
 430  * The set of PCI devices this driver supports (for 82599 VF)
 431  */
 432 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 433
 434 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 435 #include "rte_pci_dev_ids.h"
 436 { .vendor_id = 0, /* sentinel */ },
 437
 438 };
 439
 440 static const struct rte_eth_desc_lim rx_desc_lim = {
 441         .nb_max = IXGBE_MAX_RING_DESC,
 442         .nb_min = IXGBE_MIN_RING_DESC,
 443         .nb_align = IXGBE_RXD_ALIGN,
 444 };
 445
 446 static const struct rte_eth_desc_lim tx_desc_lim = {
 447         .nb_max = IXGBE_MAX_RING_DESC,
 448         .nb_min = IXGBE_MIN_RING_DESC,
 449         .nb_align = IXGBE_TXD_ALIGN,
 450 };
 451
 452 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 453         .dev_configure        = ixgbe_dev_configure,
 454         .dev_start            = ixgbe_dev_start,
 455         .dev_stop             = ixgbe_dev_stop,
 456         .dev_set_link_up    = ixgbe_dev_set_link_up,
 457         .dev_set_link_down  = ixgbe_dev_set_link_down,
 458         .dev_close            = ixgbe_dev_close,
 459         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 460         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 461         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 462         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 463         .link_update          = ixgbe_dev_link_update,
 464         .stats_get            = ixgbe_dev_stats_get,
 465         .xstats_get           = ixgbe_dev_xstats_get,
 466         .stats_reset          = ixgbe_dev_stats_reset,
 467         .xstats_reset         = ixgbe_dev_xstats_reset,
 468         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 469         .dev_infos_get        = ixgbe_dev_info_get,
 470         .mtu_set              = ixgbe_dev_mtu_set,
 471         .vlan_filter_set      = ixgbe_vlan_filter_set,
 472         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 473         .vlan_offload_set     = ixgbe_vlan_offload_set,
 474         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 475         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 476         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 477         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 478         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 479         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 480         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 481         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 482         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 483         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 484         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 485         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 486         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 487         .dev_led_on           = ixgbe_dev_led_on,
 488         .dev_led_off          = ixgbe_dev_led_off,
 489         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 490         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 491         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 492         .mac_addr_add         = ixgbe_add_rar,
 493         .mac_addr_remove      = ixgbe_remove_rar,
 494         .mac_addr_set         = ixgbe_set_default_mac_addr,
 495         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 496         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 497         .mirror_rule_set      = ixgbe_mirror_rule_set,
 498         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 499         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 500         .set_vf_rx            = ixgbe_set_pool_rx,
 501         .set_vf_tx            = ixgbe_set_pool_tx,
 502         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 503         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 504         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 505         .reta_update          = ixgbe_dev_rss_reta_update,
 506         .reta_query           = ixgbe_dev_rss_reta_query,
 507 #ifdef RTE_NIC_BYPASS
 508         .bypass_init          = ixgbe_bypass_init,
 509         .bypass_state_set     = ixgbe_bypass_state_store,
 510         .bypass_state_show    = ixgbe_bypass_state_show,
 511         .bypass_event_set     = ixgbe_bypass_event_store,
 512         .bypass_event_show    = ixgbe_bypass_event_show,
 513         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 514         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 515         .bypass_ver_show      = ixgbe_bypass_ver_show,
 516         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 517 #endif /* RTE_NIC_BYPASS */
 518         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 519         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 520         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 521         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 522         .rxq_info_get         = ixgbe_rxq_info_get,
 523         .txq_info_get         = ixgbe_txq_info_get,
 524         .timesync_enable      = ixgbe_timesync_enable,
 525         .timesync_disable     = ixgbe_timesync_disable,
 526         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 527         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 528         .get_reg_length       = ixgbe_get_reg_length,
 529         .get_reg              = ixgbe_get_regs,
 530         .get_eeprom_length    = ixgbe_get_eeprom_length,
 531         .get_eeprom           = ixgbe_get_eeprom,
 532         .set_eeprom           = ixgbe_set_eeprom,
 533         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 534         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 535         .timesync_read_time   = ixgbe_timesync_read_time,
 536         .timesync_write_time  = ixgbe_timesync_write_time,
 537         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 538         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 539         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 540         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 541 };
 542
 543 /*
 544  * dev_ops for virtual function, bare necessities for basic vf
 545  * operation have been implemented
 546  */
 547 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 548         .dev_configure        = ixgbevf_dev_configure,
 549         .dev_start            = ixgbevf_dev_start,
 550         .dev_stop             = ixgbevf_dev_stop,
 551         .link_update          = ixgbe_dev_link_update,
 552         .stats_get            = ixgbevf_dev_stats_get,
 553         .xstats_get           = ixgbevf_dev_xstats_get,
 554         .stats_reset          = ixgbevf_dev_stats_reset,
 555         .xstats_reset         = ixgbevf_dev_stats_reset,
 556         .dev_close            = ixgbevf_dev_close,
 557         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 558         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 559         .dev_infos_get        = ixgbevf_dev_info_get,
 560         .mtu_set              = ixgbevf_dev_set_mtu,
 561         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 562         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 563         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 564         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 565         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 566         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 567         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 568         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 569         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 570         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 571         .mac_addr_add         = ixgbevf_add_mac_addr,
 572         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 573         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 574         .rxq_info_get         = ixgbe_rxq_info_get,
 575         .txq_info_get         = ixgbe_txq_info_get,
 576         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 577         .get_reg_length       = ixgbevf_get_reg_length,
 578         .get_reg              = ixgbevf_get_regs,
 579         .reta_update          = ixgbe_dev_rss_reta_update,
 580         .reta_query           = ixgbe_dev_rss_reta_query,
 581         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 582         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 583 };
 584
 585 /* store statistics names and its offset in stats structure */
 586 struct rte_ixgbe_xstats_name_off {
 587         char name[RTE_ETH_XSTATS_NAME_SIZE];
 588         unsigned offset;
 589 };
 590
 591 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 592         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 593         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 594         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 595         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 596         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 597         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 598         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 599         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 600         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 601         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 602         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 603         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 604         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 605         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 606         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 607                 prc1023)},
 608         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 609                 prc1522)},
 610         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 611         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 612         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 613         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 614         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 615         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 616         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 617         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 618         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 619         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 620         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 621         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 622         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 623         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 624         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 625         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 626         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 627                 ptc1023)},
 628         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 629                 ptc1522)},
 630         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 631         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 632         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 633         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 634
 635         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 636                 fdirustat_add)},
 637         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 638                 fdirustat_remove)},
 639         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 640                 fdirfstat_fadd)},
 641         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 642                 fdirfstat_fremove)},
 643         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 644                 fdirmatch)},
 645         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 646                 fdirmiss)},
 647
 648         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 649         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 650         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 651                 fclast)},
 652         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 653         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 654         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 655         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 656         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 657                 fcoe_noddp)},
 658         {"rx_fcoe_no_direct_data_placement_ext_buff",
 659                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 660
 661         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 662                 lxontxc)},
 663         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 664                 lxonrxc)},
 665         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 666                 lxofftxc)},
 667         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 668                 lxoffrxc)},
 669         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 670 };
 671
 672 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 673                            sizeof(rte_ixgbe_stats_strings[0]))
 674
 675 /* Per-queue statistics */
 676 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 677         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 678         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 679         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 680         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 681 };
 682
 683 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 684                            sizeof(rte_ixgbe_rxq_strings[0]))
 685
 686 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 687         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 688         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 689         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 690                 pxon2offc)},
 691 };
 692
 693 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 694                            sizeof(rte_ixgbe_txq_strings[0]))
 695
 696 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 697         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 698 };
 699
 700 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 701                 sizeof(rte_ixgbevf_stats_strings[0]))
 702
 703 /**
 704  * Atomically reads the link status information from global
 705  * structure rte_eth_dev.
 706  *
 707  * @param dev
 708  *   - Pointer to the structure rte_eth_dev to read from.
 709  *   - Pointer to the buffer to be saved with the link status.
 710  *
 711  * @return
 712  *   - On success, zero.
 713  *   - On failure, negative value.
 714  */
 715 static inline int
 716 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 717                                 struct rte_eth_link *link)
 718 {
 719         struct rte_eth_link *dst = link;
 720         struct rte_eth_link *src = &(dev->data->dev_link);
 721
 722         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 723                                         *(uint64_t *)src) == 0)
 724                 return -1;
 725
 726         return 0;
 727 }
 728
 729 /**
 730  * Atomically writes the link status information into global
 731  * structure rte_eth_dev.
 732  *
 733  * @param dev
 734  *   - Pointer to the structure rte_eth_dev to read from.
 735  *   - Pointer to the buffer to be saved with the link status.
 736  *
 737  * @return
 738  *   - On success, zero.
 739  *   - On failure, negative value.
 740  */
 741 static inline int
 742 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 743                                 struct rte_eth_link *link)
 744 {
 745         struct rte_eth_link *dst = &(dev->data->dev_link);
 746         struct rte_eth_link *src = link;
 747
 748         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 749                                         *(uint64_t *)src) == 0)
 750                 return -1;
 751
 752         return 0;
 753 }
 754
 755 /*
 756  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 757  */
 758 static inline int
 759 ixgbe_is_sfp(struct ixgbe_hw *hw)
 760 {
 761         switch (hw->phy.type) {
 762         case ixgbe_phy_sfp_avago:
 763         case ixgbe_phy_sfp_ftl:
 764         case ixgbe_phy_sfp_intel:
 765         case ixgbe_phy_sfp_unknown:
 766         case ixgbe_phy_sfp_passive_tyco:
 767         case ixgbe_phy_sfp_passive_unknown:
 768                 return 1;
 769         default:
 770                 return 0;
 771         }
 772 }
 773
 774 static inline int32_t
 775 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 776 {
 777         uint32_t ctrl_ext;
 778         int32_t status;
 779
 780         status = ixgbe_reset_hw(hw);
 781
 782         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 783         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 784         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 785         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 786         IXGBE_WRITE_FLUSH(hw);
 787
 788         return status;
 789 }
 790
 791 static inline void
 792 ixgbe_enable_intr(struct rte_eth_dev *dev)
 793 {
 794         struct ixgbe_interrupt *intr =
 795                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 796         struct ixgbe_hw *hw =
 797                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 798
 799         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 800         IXGBE_WRITE_FLUSH(hw);
 801 }
 802
 803 /*
 804  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 805  */
 806 static void
 807 ixgbe_disable_intr(struct ixgbe_hw *hw)
 808 {
 809         PMD_INIT_FUNC_TRACE();
 810
 811         if (hw->mac.type == ixgbe_mac_82598EB) {
 812                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 813         } else {
 814                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 815                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 816                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 817         }
 818         IXGBE_WRITE_FLUSH(hw);
 819 }
 820
 821 /*
 822  * This function resets queue statistics mapping registers.
 823  * From Niantic datasheet, Initialization of Statistics section:
 824  * "...if software requires the queue counters, the RQSMR and TQSM registers
 825  * must be re-programmed following a device reset.
 826  */
 827 static void
 828 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 829 {
 830         uint32_t i;
 831
 832         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 833                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 834                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 835         }
 836 }
 837
 838
 839 static int
 840 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 841                                   uint16_t queue_id,
 842                                   uint8_t stat_idx,
 843                                   uint8_t is_rx)
 844 {
 845 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 846 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 847 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 848
 849         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 850         struct ixgbe_stat_mapping_registers *stat_mappings =
 851                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 852         uint32_t qsmr_mask = 0;
 853         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 854         uint32_t q_map;
 855         uint8_t n, offset;
 856
 857         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 858                 (hw->mac.type != ixgbe_mac_X540) &&
 859                 (hw->mac.type != ixgbe_mac_X550) &&
 860                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 861                 (hw->mac.type != ixgbe_mac_X550EM_a))
 862                 return -ENOSYS;
 863
 864         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 865                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 866                      queue_id, stat_idx);
 867
 868         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 869         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 870                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 871                 return -EIO;
 872         }
 873         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 874
 875         /* Now clear any previous stat_idx set */
 876         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 877         if (!is_rx)
 878                 stat_mappings->tqsm[n] &= ~clearing_mask;
 879         else
 880                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 881
 882         q_map = (uint32_t)stat_idx;
 883         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 884         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 885         if (!is_rx)
 886                 stat_mappings->tqsm[n] |= qsmr_mask;
 887         else
 888                 stat_mappings->rqsmr[n] |= qsmr_mask;
 889
 890         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 891                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 892                      queue_id, stat_idx);
 893         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 894                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 895
 896         /* Now write the mapping in the appropriate register */
 897         if (is_rx) {
 898                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 899                              stat_mappings->rqsmr[n], n);
 900                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 901         }
 902         else {
 903                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 904                              stat_mappings->tqsm[n], n);
 905                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 906         }
 907         return 0;
 908 }
 909
 910 static void
 911 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 912 {
 913         struct ixgbe_stat_mapping_registers *stat_mappings =
 914                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 915         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 916         int i;
 917
 918         /* write whatever was in stat mapping table to the NIC */
 919         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 920                 /* rx */
 921                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 922
 923                 /* tx */
 924                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 925         }
 926 }
 927
 928 static void
 929 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 930 {
 931         uint8_t i;
 932         struct ixgbe_dcb_tc_config *tc;
 933         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 934
 935         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 936         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 937         for (i = 0; i < dcb_max_tc; i++) {
 938                 tc = &dcb_config->tc_config[i];
 939                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 940                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 941                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 942                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 943                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 944                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 945                 tc->pfc = ixgbe_dcb_pfc_disabled;
 946         }
 947
 948         /* Initialize default user to priority mapping, UPx->TC0 */
 949         tc = &dcb_config->tc_config[0];
 950         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 951         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 952         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 953                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 954                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 955         }
 956         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 957         dcb_config->pfc_mode_enable = false;
 958         dcb_config->vt_mode = true;
 959         dcb_config->round_robin_enable = false;
 960         /* support all DCB capabilities in 82599 */
 961         dcb_config->support.capabilities = 0xFF;
 962
 963         /*we only support 4 Tcs for X540, X550 */
 964         if (hw->mac.type == ixgbe_mac_X540 ||
 965                 hw->mac.type == ixgbe_mac_X550 ||
 966                 hw->mac.type == ixgbe_mac_X550EM_x ||
 967                 hw->mac.type == ixgbe_mac_X550EM_a) {
 968                 dcb_config->num_tcs.pg_tcs = 4;
 969                 dcb_config->num_tcs.pfc_tcs = 4;
 970         }
 971 }
 972
 973 /*
 974  * Ensure that all locks are released before first NVM or PHY access
 975  */
 976 static void
 977 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 978 {
 979         uint16_t mask;
 980
 981         /*
 982          * Phy lock should not fail in this early stage. If this is the case,
 983          * it is due to an improper exit of the application.
 984          * So force the release of the faulty lock. Release of common lock
 985          * is done automatically by swfw_sync function.
 986          */
 987         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 988         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 989                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 990         }
 991         ixgbe_release_swfw_semaphore(hw, mask);
 992
 993         /*
 994          * These ones are more tricky since they are common to all ports; but
 995          * swfw_sync retries last long enough (1s) to be almost sure that if
 996          * lock can not be taken it is due to an improper lock of the
 997          * semaphore.
 998          */
 999         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1000         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1001                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1002         }
1003         ixgbe_release_swfw_semaphore(hw, mask);
1004 }
1005
1006 /*
1007  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1008  * It returns 0 on success.
1009  */
1010 static int
1011 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1012 {
1013         struct rte_pci_device *pci_dev;
1014         struct ixgbe_hw *hw =
1015                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1016         struct ixgbe_vfta * shadow_vfta =
1017                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1018         struct ixgbe_hwstrip *hwstrip =
1019                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1020         struct ixgbe_dcb_config *dcb_config =
1021                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1022         struct ixgbe_filter_info *filter_info =
1023                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1024         uint32_t ctrl_ext;
1025         uint16_t csum;
1026         int diag, i;
1027
1028         PMD_INIT_FUNC_TRACE();
1029
1030         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1031         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1032         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1033
1034         /*
1035          * For secondary processes, we don't initialise any further as primary
1036          * has already done this work. Only check we don't need a different
1037          * RX and TX function.
1038          */
1039         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1040                 struct ixgbe_tx_queue *txq;
1041                 /* TX queue function in primary, set by last queue initialized
1042                  * Tx queue may not initialized by primary process */
1043                 if (eth_dev->data->tx_queues) {
1044                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1045                         ixgbe_set_tx_function(eth_dev, txq);
1046                 } else {
1047                         /* Use default TX function if we get here */
1048                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1049                                              "Using default TX function.");
1050                 }
1051
1052                 ixgbe_set_rx_function(eth_dev);
1053
1054                 return 0;
1055         }
1056         pci_dev = eth_dev->pci_dev;
1057
1058         rte_eth_copy_pci_info(eth_dev, pci_dev);
1059
1060         /* Vendor and Device ID need to be set before init of shared code */
1061         hw->device_id = pci_dev->id.device_id;
1062         hw->vendor_id = pci_dev->id.vendor_id;
1063         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1064         hw->allow_unsupported_sfp = 1;
1065
1066         /* Initialize the shared code (base driver) */
1067 #ifdef RTE_NIC_BYPASS
1068         diag = ixgbe_bypass_init_shared_code(hw);
1069 #else
1070         diag = ixgbe_init_shared_code(hw);
1071 #endif /* RTE_NIC_BYPASS */
1072
1073         if (diag != IXGBE_SUCCESS) {
1074                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1075                 return -EIO;
1076         }
1077
1078         /* pick up the PCI bus settings for reporting later */
1079         ixgbe_get_bus_info(hw);
1080
1081         /* Unlock any pending hardware semaphore */
1082         ixgbe_swfw_lock_reset(hw);
1083
1084         /* Initialize DCB configuration*/
1085         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1086         ixgbe_dcb_init(hw,dcb_config);
1087         /* Get Hardware Flow Control setting */
1088         hw->fc.requested_mode = ixgbe_fc_full;
1089         hw->fc.current_mode = ixgbe_fc_full;
1090         hw->fc.pause_time = IXGBE_FC_PAUSE;
1091         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1092                 hw->fc.low_water[i] = IXGBE_FC_LO;
1093                 hw->fc.high_water[i] = IXGBE_FC_HI;
1094         }
1095         hw->fc.send_xon = 1;
1096
1097         /* Make sure we have a good EEPROM before we read from it */
1098         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1099         if (diag != IXGBE_SUCCESS) {
1100                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1101                 return -EIO;
1102         }
1103
1104 #ifdef RTE_NIC_BYPASS
1105         diag = ixgbe_bypass_init_hw(hw);
1106 #else
1107         diag = ixgbe_init_hw(hw);
1108 #endif /* RTE_NIC_BYPASS */
1109
1110         /*
1111          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1112          * is called too soon after the kernel driver unbinding/binding occurs.
1113          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1114          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1115          * also called. See ixgbe_identify_phy_82599(). The reason for the
1116          * failure is not known, and only occuts when virtualisation features
1117          * are disabled in the bios. A delay of 100ms  was found to be enough by
1118          * trial-and-error, and is doubled to be safe.
1119          */
1120         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1121                 rte_delay_ms(200);
1122                 diag = ixgbe_init_hw(hw);
1123         }
1124
1125         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1126                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1127                     "LOM.  Please be aware there may be issues associated "
1128                     "with your hardware.");
1129                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1130                     "please contact your Intel or hardware representative "
1131                     "who provided you with this hardware.");
1132         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1133                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1134         if (diag) {
1135                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1136                 return -EIO;
1137         }
1138
1139         /* Reset the hw statistics */
1140         ixgbe_dev_stats_reset(eth_dev);
1141
1142         /* disable interrupt */
1143         ixgbe_disable_intr(hw);
1144
1145         /* reset mappings for queue statistics hw counters*/
1146         ixgbe_reset_qstat_mappings(hw);
1147
1148         /* Allocate memory for storing MAC addresses */
1149         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1150                         hw->mac.num_rar_entries, 0);
1151         if (eth_dev->data->mac_addrs == NULL) {
1152                 PMD_INIT_LOG(ERR,
1153                         "Failed to allocate %u bytes needed to store "
1154                         "MAC addresses",
1155                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1156                 return -ENOMEM;
1157         }
1158         /* Copy the permanent MAC address */
1159         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1160                         &eth_dev->data->mac_addrs[0]);
1161
1162         /* Allocate memory for storing hash filter MAC addresses */
1163         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1164                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1165         if (eth_dev->data->hash_mac_addrs == NULL) {
1166                 PMD_INIT_LOG(ERR,
1167                         "Failed to allocate %d bytes needed to store MAC addresses",
1168                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1169                 return -ENOMEM;
1170         }
1171
1172         /* initialize the vfta */
1173         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1174
1175         /* initialize the hw strip bitmap*/
1176         memset(hwstrip, 0, sizeof(*hwstrip));
1177
1178         /* initialize PF if max_vfs not zero */
1179         ixgbe_pf_host_init(eth_dev);
1180
1181         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1182         /* let hardware know driver is loaded */
1183         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1184         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1185         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1186         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1187         IXGBE_WRITE_FLUSH(hw);
1188
1189         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1190                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1191                              (int) hw->mac.type, (int) hw->phy.type,
1192                              (int) hw->phy.sfp_type);
1193         else
1194                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1195                              (int) hw->mac.type, (int) hw->phy.type);
1196
1197         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1198                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1199                         pci_dev->id.device_id);
1200
1201         rte_intr_callback_register(&pci_dev->intr_handle,
1202                                    ixgbe_dev_interrupt_handler,
1203                                    (void *)eth_dev);
1204
1205         /* enable uio/vfio intr/eventfd mapping */
1206         rte_intr_enable(&pci_dev->intr_handle);
1207
1208         /* enable support intr */
1209         ixgbe_enable_intr(eth_dev);
1210
1211         /* initialize 5tuple filter list */
1212         TAILQ_INIT(&filter_info->fivetuple_list);
1213         memset(filter_info->fivetuple_mask, 0,
1214                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1215
1216         return 0;
1217 }
1218
1219 static int
1220 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1221 {
1222         struct rte_pci_device *pci_dev;
1223         struct ixgbe_hw *hw;
1224
1225         PMD_INIT_FUNC_TRACE();
1226
1227         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1228                 return -EPERM;
1229
1230         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1231         pci_dev = eth_dev->pci_dev;
1232
1233         if (hw->adapter_stopped == 0)
1234                 ixgbe_dev_close(eth_dev);
1235
1236         eth_dev->dev_ops = NULL;
1237         eth_dev->rx_pkt_burst = NULL;
1238         eth_dev->tx_pkt_burst = NULL;
1239
1240         /* Unlock any pending hardware semaphore */
1241         ixgbe_swfw_lock_reset(hw);
1242
1243         /* disable uio intr before callback unregister */
1244         rte_intr_disable(&(pci_dev->intr_handle));
1245         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1246                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1247
1248         /* uninitialize PF if max_vfs not zero */
1249         ixgbe_pf_host_uninit(eth_dev);
1250
1251         rte_free(eth_dev->data->mac_addrs);
1252         eth_dev->data->mac_addrs = NULL;
1253
1254         rte_free(eth_dev->data->hash_mac_addrs);
1255         eth_dev->data->hash_mac_addrs = NULL;
1256
1257         return 0;
1258 }
1259
1260 /*
1261  * Negotiate mailbox API version with the PF.
1262  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1263  * Then we try to negotiate starting with the most recent one.
1264  * If all negotiation attempts fail, then we will proceed with
1265  * the default one (ixgbe_mbox_api_10).
1266  */
1267 static void
1268 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1269 {
1270         int32_t i;
1271
1272         /* start with highest supported, proceed down */
1273         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1274                 ixgbe_mbox_api_12,
1275                 ixgbe_mbox_api_11,
1276                 ixgbe_mbox_api_10,
1277         };
1278
1279         for (i = 0;
1280                         i != RTE_DIM(sup_ver) &&
1281                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1282                         i++)
1283                 ;
1284 }
1285
1286 static void
1287 generate_random_mac_addr(struct ether_addr *mac_addr)
1288 {
1289         uint64_t random;
1290
1291         /* Set Organizationally Unique Identifier (OUI) prefix. */
1292         mac_addr->addr_bytes[0] = 0x00;
1293         mac_addr->addr_bytes[1] = 0x09;
1294         mac_addr->addr_bytes[2] = 0xC0;
1295         /* Force indication of locally assigned MAC address. */
1296         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1297         /* Generate the last 3 bytes of the MAC address with a random number. */
1298         random = rte_rand();
1299         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1300 }
1301
1302 /*
1303  * Virtual Function device init
1304  */
1305 static int
1306 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1307 {
1308         int diag;
1309         uint32_t tc, tcs;
1310         struct rte_pci_device *pci_dev;
1311         struct ixgbe_hw *hw =
1312                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1313         struct ixgbe_vfta * shadow_vfta =
1314                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1315         struct ixgbe_hwstrip *hwstrip =
1316                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1317         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1318
1319         PMD_INIT_FUNC_TRACE();
1320
1321         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1322         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1323         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1324
1325         /* for secondary processes, we don't initialise any further as primary
1326          * has already done this work. Only check we don't need a different
1327          * RX function */
1328         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1329                 struct ixgbe_tx_queue *txq;
1330                 /* TX queue function in primary, set by last queue initialized
1331                  * Tx queue may not initialized by primary process
1332                  */
1333                 if (eth_dev->data->tx_queues) {
1334                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1335                         ixgbe_set_tx_function(eth_dev, txq);
1336                 } else {
1337                         /* Use default TX function if we get here */
1338                         PMD_INIT_LOG(NOTICE,
1339                                 "No TX queues configured yet. Using default TX function.");
1340                 }
1341
1342                 ixgbe_set_rx_function(eth_dev);
1343
1344                 return 0;
1345         }
1346
1347         pci_dev = eth_dev->pci_dev;
1348
1349         rte_eth_copy_pci_info(eth_dev, pci_dev);
1350
1351         hw->device_id = pci_dev->id.device_id;
1352         hw->vendor_id = pci_dev->id.vendor_id;
1353         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1354
1355         /* initialize the vfta */
1356         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1357
1358         /* initialize the hw strip bitmap*/
1359         memset(hwstrip, 0, sizeof(*hwstrip));
1360
1361         /* Initialize the shared code (base driver) */
1362         diag = ixgbe_init_shared_code(hw);
1363         if (diag != IXGBE_SUCCESS) {
1364                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1365                 return -EIO;
1366         }
1367
1368         /* init_mailbox_params */
1369         hw->mbx.ops.init_params(hw);
1370
1371         /* Reset the hw statistics */
1372         ixgbevf_dev_stats_reset(eth_dev);
1373
1374         /* Disable the interrupts for VF */
1375         ixgbevf_intr_disable(hw);
1376
1377         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1378         diag = hw->mac.ops.reset_hw(hw);
1379
1380         /*
1381          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1382          * the underlying PF driver has not assigned a MAC address to the VF.
1383          * In this case, assign a random MAC address.
1384          */
1385         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1386                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1387                 return diag;
1388         }
1389
1390         /* negotiate mailbox API version to use with the PF. */
1391         ixgbevf_negotiate_api(hw);
1392
1393         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1394         ixgbevf_get_queues(hw, &tcs, &tc);
1395
1396         /* Allocate memory for storing MAC addresses */
1397         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1398                         hw->mac.num_rar_entries, 0);
1399         if (eth_dev->data->mac_addrs == NULL) {
1400                 PMD_INIT_LOG(ERR,
1401                         "Failed to allocate %u bytes needed to store "
1402                         "MAC addresses",
1403                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1404                 return -ENOMEM;
1405         }
1406
1407         /* Generate a random MAC address, if none was assigned by PF. */
1408         if (is_zero_ether_addr(perm_addr)) {
1409                 generate_random_mac_addr(perm_addr);
1410                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1411                 if (diag) {
1412                         rte_free(eth_dev->data->mac_addrs);
1413                         eth_dev->data->mac_addrs = NULL;
1414                         return diag;
1415                 }
1416                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1417                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1418                              "%02x:%02x:%02x:%02x:%02x:%02x",
1419                              perm_addr->addr_bytes[0],
1420                              perm_addr->addr_bytes[1],
1421                              perm_addr->addr_bytes[2],
1422                              perm_addr->addr_bytes[3],
1423                              perm_addr->addr_bytes[4],
1424                              perm_addr->addr_bytes[5]);
1425         }
1426
1427         /* Copy the permanent MAC address */
1428         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1429
1430         /* reset the hardware with the new settings */
1431         diag = hw->mac.ops.start_hw(hw);
1432         switch (diag) {
1433                 case  0:
1434                         break;
1435
1436                 default:
1437                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1438                         return -EIO;
1439         }
1440
1441         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1442                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1443                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1444
1445         return 0;
1446 }
1447
1448 /* Virtual Function device uninit */
1449
1450 static int
1451 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1452 {
1453         struct ixgbe_hw *hw;
1454
1455         PMD_INIT_FUNC_TRACE();
1456
1457         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1458                 return -EPERM;
1459
1460         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1461
1462         if (hw->adapter_stopped == 0)
1463                 ixgbevf_dev_close(eth_dev);
1464
1465         eth_dev->dev_ops = NULL;
1466         eth_dev->rx_pkt_burst = NULL;
1467         eth_dev->tx_pkt_burst = NULL;
1468
1469         /* Disable the interrupts for VF */
1470         ixgbevf_intr_disable(hw);
1471
1472         rte_free(eth_dev->data->mac_addrs);
1473         eth_dev->data->mac_addrs = NULL;
1474
1475         return 0;
1476 }
1477
1478 static struct eth_driver rte_ixgbe_pmd = {
1479         .pci_drv = {
1480                 .name = "rte_ixgbe_pmd",
1481                 .id_table = pci_id_ixgbe_map,
1482                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1483                         RTE_PCI_DRV_DETACHABLE,
1484         },
1485         .eth_dev_init = eth_ixgbe_dev_init,
1486         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1487         .dev_private_size = sizeof(struct ixgbe_adapter),
1488 };
1489
1490 /*
1491  * virtual function driver struct
1492  */
1493 static struct eth_driver rte_ixgbevf_pmd = {
1494         .pci_drv = {
1495                 .name = "rte_ixgbevf_pmd",
1496                 .id_table = pci_id_ixgbevf_map,
1497                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1498         },
1499         .eth_dev_init = eth_ixgbevf_dev_init,
1500         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1501         .dev_private_size = sizeof(struct ixgbe_adapter),
1502 };
1503
1504 /*
1505  * Driver initialization routine.
1506  * Invoked once at EAL init time.
1507  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1508  */
1509 static int
1510 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1511 {
1512         PMD_INIT_FUNC_TRACE();
1513
1514         rte_eth_driver_register(&rte_ixgbe_pmd);
1515         return 0;
1516 }
1517
1518 /*
1519  * VF Driver initialization routine.
1520  * Invoked one at EAL init time.
1521  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1522  */
1523 static int
1524 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1525 {
1526         PMD_INIT_FUNC_TRACE();
1527
1528         rte_eth_driver_register(&rte_ixgbevf_pmd);
1529         return 0;
1530 }
1531
1532 static int
1533 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1534 {
1535         struct ixgbe_hw *hw =
1536                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1537         struct ixgbe_vfta * shadow_vfta =
1538                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1539         uint32_t vfta;
1540         uint32_t vid_idx;
1541         uint32_t vid_bit;
1542
1543         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1544         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1545         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1546         if (on)
1547                 vfta |= vid_bit;
1548         else
1549                 vfta &= ~vid_bit;
1550         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1551
1552         /* update local VFTA copy */
1553         shadow_vfta->vfta[vid_idx] = vfta;
1554
1555         return 0;
1556 }
1557
1558 static void
1559 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1560 {
1561         if (on)
1562                 ixgbe_vlan_hw_strip_enable(dev, queue);
1563         else
1564                 ixgbe_vlan_hw_strip_disable(dev, queue);
1565 }
1566
1567 static int
1568 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1569                     enum rte_vlan_type vlan_type,
1570                     uint16_t tpid)
1571 {
1572         struct ixgbe_hw *hw =
1573                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1574         int ret = 0;
1575
1576         switch (vlan_type) {
1577         case ETH_VLAN_TYPE_INNER:
1578                 /* Only the high 16-bits is valid */
1579                 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1580                 break;
1581         default:
1582                 ret = -EINVAL;
1583                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1584                 break;
1585         }
1586
1587         return ret;
1588 }
1589
1590 void
1591 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1592 {
1593         struct ixgbe_hw *hw =
1594                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1595         uint32_t vlnctrl;
1596
1597         PMD_INIT_FUNC_TRACE();
1598
1599         /* Filter Table Disable */
1600         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1601         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1602
1603         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1604 }
1605
1606 void
1607 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1608 {
1609         struct ixgbe_hw *hw =
1610                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1611         struct ixgbe_vfta * shadow_vfta =
1612                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1613         uint32_t vlnctrl;
1614         uint16_t i;
1615
1616         PMD_INIT_FUNC_TRACE();
1617
1618         /* Filter Table Enable */
1619         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1620         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1621         vlnctrl |= IXGBE_VLNCTRL_VFE;
1622
1623         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1624
1625         /* write whatever is in local vfta copy */
1626         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1627                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1628 }
1629
1630 static void
1631 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1632 {
1633         struct ixgbe_hwstrip *hwstrip =
1634                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1635
1636         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1637                 return;
1638
1639         if (on)
1640                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1641         else
1642                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1643 }
1644
1645 static void
1646 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1647 {
1648         struct ixgbe_hw *hw =
1649                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1650         uint32_t ctrl;
1651
1652         PMD_INIT_FUNC_TRACE();
1653
1654         if (hw->mac.type == ixgbe_mac_82598EB) {
1655                 /* No queue level support */
1656                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1657                 return;
1658         }
1659         else {
1660                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1661                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1662                 ctrl &= ~IXGBE_RXDCTL_VME;
1663                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1664         }
1665         /* record those setting for HW strip per queue */
1666         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1667 }
1668
1669 static void
1670 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1671 {
1672         struct ixgbe_hw *hw =
1673                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1674         uint32_t ctrl;
1675
1676         PMD_INIT_FUNC_TRACE();
1677
1678         if (hw->mac.type == ixgbe_mac_82598EB) {
1679                 /* No queue level supported */
1680                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1681                 return;
1682         }
1683         else {
1684                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1685                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1686                 ctrl |= IXGBE_RXDCTL_VME;
1687                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1688         }
1689         /* record those setting for HW strip per queue */
1690         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1691 }
1692
1693 void
1694 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1695 {
1696         struct ixgbe_hw *hw =
1697                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1698         uint32_t ctrl;
1699         uint16_t i;
1700
1701         PMD_INIT_FUNC_TRACE();
1702
1703         if (hw->mac.type == ixgbe_mac_82598EB) {
1704                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1705                 ctrl &= ~IXGBE_VLNCTRL_VME;
1706                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1707         }
1708         else {
1709                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1710                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1711                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1712                         ctrl &= ~IXGBE_RXDCTL_VME;
1713                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1714
1715                         /* record those setting for HW strip per queue */
1716                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1717                 }
1718         }
1719 }
1720
1721 void
1722 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1723 {
1724         struct ixgbe_hw *hw =
1725                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726         uint32_t ctrl;
1727         uint16_t i;
1728
1729         PMD_INIT_FUNC_TRACE();
1730
1731         if (hw->mac.type == ixgbe_mac_82598EB) {
1732                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1733                 ctrl |= IXGBE_VLNCTRL_VME;
1734                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1735         }
1736         else {
1737                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1738                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1739                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1740                         ctrl |= IXGBE_RXDCTL_VME;
1741                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1742
1743                         /* record those setting for HW strip per queue */
1744                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1745                 }
1746         }
1747 }
1748
1749 static void
1750 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1751 {
1752         struct ixgbe_hw *hw =
1753                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1754         uint32_t ctrl;
1755
1756         PMD_INIT_FUNC_TRACE();
1757
1758         /* DMATXCTRL: Geric Double VLAN Disable */
1759         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1760         ctrl &= ~IXGBE_DMATXCTL_GDV;
1761         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1762
1763         /* CTRL_EXT: Global Double VLAN Disable */
1764         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1765         ctrl &= ~IXGBE_EXTENDED_VLAN;
1766         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1767
1768 }
1769
1770 static void
1771 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1772 {
1773         struct ixgbe_hw *hw =
1774                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1775         uint32_t ctrl;
1776
1777         PMD_INIT_FUNC_TRACE();
1778
1779         /* DMATXCTRL: Geric Double VLAN Enable */
1780         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1781         ctrl |= IXGBE_DMATXCTL_GDV;
1782         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1783
1784         /* CTRL_EXT: Global Double VLAN Enable */
1785         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1786         ctrl |= IXGBE_EXTENDED_VLAN;
1787         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1788
1789         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1790         if (hw->mac.type == ixgbe_mac_X550 ||
1791             hw->mac.type == ixgbe_mac_X550EM_x) {
1792                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1793                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1794                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1795         }
1796
1797         /*
1798          * VET EXT field in the EXVET register = 0x8100 by default
1799          * So no need to change. Same to VT field of DMATXCTL register
1800          */
1801 }
1802
1803 static void
1804 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1805 {
1806         if (mask & ETH_VLAN_STRIP_MASK) {
1807                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1808                         ixgbe_vlan_hw_strip_enable_all(dev);
1809                 else
1810                         ixgbe_vlan_hw_strip_disable_all(dev);
1811         }
1812
1813         if (mask & ETH_VLAN_FILTER_MASK) {
1814                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1815                         ixgbe_vlan_hw_filter_enable(dev);
1816                 else
1817                         ixgbe_vlan_hw_filter_disable(dev);
1818         }
1819
1820         if (mask & ETH_VLAN_EXTEND_MASK) {
1821                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1822                         ixgbe_vlan_hw_extend_enable(dev);
1823                 else
1824                         ixgbe_vlan_hw_extend_disable(dev);
1825         }
1826 }
1827
1828 static void
1829 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1830 {
1831         struct ixgbe_hw *hw =
1832                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1833         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1834         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1835         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1836         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1837 }
1838
1839 static int
1840 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1841 {
1842         switch (nb_rx_q) {
1843         case 1:
1844         case 2:
1845                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1846                 break;
1847         case 4:
1848                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1849                 break;
1850         default:
1851                 return -EINVAL;
1852         }
1853
1854         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1855         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1856
1857         return 0;
1858 }
1859
1860 static int
1861 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1862 {
1863         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1864         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1865         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1866
1867         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1868                 /* check multi-queue mode */
1869                 switch (dev_conf->rxmode.mq_mode) {
1870                 case ETH_MQ_RX_VMDQ_DCB:
1871                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1872                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1873                         PMD_INIT_LOG(ERR, "SRIOV active,"
1874                                         " unsupported mq_mode rx %d.",
1875                                         dev_conf->rxmode.mq_mode);
1876                         return -EINVAL;
1877                 case ETH_MQ_RX_RSS:
1878                 case ETH_MQ_RX_VMDQ_RSS:
1879                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1880                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1881                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1882                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1883                                                 " invalid queue number"
1884                                                 " for VMDQ RSS, allowed"
1885                                                 " value are 1, 2 or 4.");
1886                                         return -EINVAL;
1887                                 }
1888                         break;
1889                 case ETH_MQ_RX_VMDQ_ONLY:
1890                 case ETH_MQ_RX_NONE:
1891                         /* if nothing mq mode configure, use default scheme */
1892                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1893                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1894                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1895                         break;
1896                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1897                         /* SRIOV only works in VMDq enable mode */
1898                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1899                                         " wrong mq_mode rx %d.",
1900                                         dev_conf->rxmode.mq_mode);
1901                         return -EINVAL;
1902                 }
1903
1904                 switch (dev_conf->txmode.mq_mode) {
1905                 case ETH_MQ_TX_VMDQ_DCB:
1906                         /* DCB VMDQ in SRIOV mode, not implement yet */
1907                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1908                                         " unsupported VMDQ mq_mode tx %d.",
1909                                         dev_conf->txmode.mq_mode);
1910                         return -EINVAL;
1911                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1912                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1913                         break;
1914                 }
1915
1916                 /* check valid queue number */
1917                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1918                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1919                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1920                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1921                                         " must be less than or equal to %d.",
1922                                         nb_rx_q, nb_tx_q,
1923                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1924                         return -EINVAL;
1925                 }
1926         } else {
1927                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1928                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1929                                           " not supported.");
1930                         return -EINVAL;
1931                 }
1932                 /* check configuration for vmdb+dcb mode */
1933                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1934                         const struct rte_eth_vmdq_dcb_conf *conf;
1935
1936                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1937                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1938                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1939                                 return -EINVAL;
1940                         }
1941                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1942                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1943                                conf->nb_queue_pools == ETH_32_POOLS)) {
1944                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1945                                                 " nb_queue_pools must be %d or %d.",
1946                                                 ETH_16_POOLS, ETH_32_POOLS);
1947                                 return -EINVAL;
1948                         }
1949                 }
1950                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1951                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1952
1953                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1954                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1955                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1956                                 return -EINVAL;
1957                         }
1958                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1959                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1960                                conf->nb_queue_pools == ETH_32_POOLS)) {
1961                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1962                                                 " nb_queue_pools != %d and"
1963                                                 " nb_queue_pools != %d.",
1964                                                 ETH_16_POOLS, ETH_32_POOLS);
1965                                 return -EINVAL;
1966                         }
1967                 }
1968
1969                 /* For DCB mode check our configuration before we go further */
1970                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1971                         const struct rte_eth_dcb_rx_conf *conf;
1972
1973                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1974                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1975                                                  IXGBE_DCB_NB_QUEUES);
1976                                 return -EINVAL;
1977                         }
1978                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1979                         if (!(conf->nb_tcs == ETH_4_TCS ||
1980                                conf->nb_tcs == ETH_8_TCS)) {
1981                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1982                                                 " and nb_tcs != %d.",
1983                                                 ETH_4_TCS, ETH_8_TCS);
1984                                 return -EINVAL;
1985                         }
1986                 }
1987
1988                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1989                         const struct rte_eth_dcb_tx_conf *conf;
1990
1991                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1992                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1993                                                  IXGBE_DCB_NB_QUEUES);
1994                                 return -EINVAL;
1995                         }
1996                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1997                         if (!(conf->nb_tcs == ETH_4_TCS ||
1998                                conf->nb_tcs == ETH_8_TCS)) {
1999                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2000                                                 " and nb_tcs != %d.",
2001                                                 ETH_4_TCS, ETH_8_TCS);
2002                                 return -EINVAL;
2003                         }
2004                 }
2005         }
2006         return 0;
2007 }
2008
2009 static int
2010 ixgbe_dev_configure(struct rte_eth_dev *dev)
2011 {
2012         struct ixgbe_interrupt *intr =
2013                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2014         struct ixgbe_adapter *adapter =
2015                 (struct ixgbe_adapter *)dev->data->dev_private;
2016         int ret;
2017
2018         PMD_INIT_FUNC_TRACE();
2019         /* multipe queue mode checking */
2020         ret  = ixgbe_check_mq_mode(dev);
2021         if (ret != 0) {
2022                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2023                             ret);
2024                 return ret;
2025         }
2026
2027         /* set flag to update link status after init */
2028         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2029
2030         /*
2031          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2032          * allocation or vector Rx preconditions we will reset it.
2033          */
2034         adapter->rx_bulk_alloc_allowed = true;
2035         adapter->rx_vec_allowed = true;
2036
2037         return 0;
2038 }
2039
2040 static void
2041 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2042 {
2043         struct ixgbe_hw *hw =
2044                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2045         struct ixgbe_interrupt *intr =
2046                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2047         uint32_t gpie;
2048
2049         /* only set up it on X550EM_X */
2050         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2051                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2052                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2053                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2054                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2055                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2056         }
2057 }
2058
2059 /*
2060  * Configure device link speed and setup link.
2061  * It returns 0 on success.
2062  */
2063 static int
2064 ixgbe_dev_start(struct rte_eth_dev *dev)
2065 {
2066         struct ixgbe_hw *hw =
2067                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2068         struct ixgbe_vf_info *vfinfo =
2069                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2070         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2071         uint32_t intr_vector = 0;
2072         int err, link_up = 0, negotiate = 0;
2073         uint32_t speed = 0;
2074         int mask = 0;
2075         int status;
2076         uint16_t vf, idx;
2077
2078         PMD_INIT_FUNC_TRACE();
2079
2080         /* IXGBE devices don't support half duplex */
2081         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
2082                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
2083                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
2084                              dev->data->dev_conf.link_duplex,
2085                              dev->data->port_id);
2086                 return -EINVAL;
2087         }
2088
2089         /* disable uio/vfio intr/eventfd mapping */
2090         rte_intr_disable(intr_handle);
2091
2092         /* stop adapter */
2093         hw->adapter_stopped = 0;
2094         ixgbe_stop_adapter(hw);
2095
2096         /* reinitialize adapter
2097          * this calls reset and start */
2098         status = ixgbe_pf_reset_hw(hw);
2099         if (status != 0)
2100                 return -1;
2101         hw->mac.ops.start_hw(hw);
2102         hw->mac.get_link_status = true;
2103
2104         /* configure PF module if SRIOV enabled */
2105         ixgbe_pf_host_configure(dev);
2106
2107         ixgbe_dev_phy_intr_setup(dev);
2108
2109         /* check and configure queue intr-vector mapping */
2110         if ((rte_intr_cap_multiple(intr_handle) ||
2111              !RTE_ETH_DEV_SRIOV(dev).active) &&
2112             dev->data->dev_conf.intr_conf.rxq != 0) {
2113                 intr_vector = dev->data->nb_rx_queues;
2114                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2115                         return -1;
2116         }
2117
2118         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2119                 intr_handle->intr_vec =
2120                         rte_zmalloc("intr_vec",
2121                                     dev->data->nb_rx_queues * sizeof(int), 0);
2122                 if (intr_handle->intr_vec == NULL) {
2123                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2124                                      " intr_vec\n", dev->data->nb_rx_queues);
2125                         return -ENOMEM;
2126                 }
2127         }
2128
2129         /* confiugre msix for sleep until rx interrupt */
2130         ixgbe_configure_msix(dev);
2131
2132         /* initialize transmission unit */
2133         ixgbe_dev_tx_init(dev);
2134
2135         /* This can fail when allocating mbufs for descriptor rings */
2136         err = ixgbe_dev_rx_init(dev);
2137         if (err) {
2138                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2139                 goto error;
2140         }
2141
2142         err = ixgbe_dev_rxtx_start(dev);
2143         if (err < 0) {
2144                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2145                 goto error;
2146         }
2147
2148         /* Skip link setup if loopback mode is enabled for 82599. */
2149         if (hw->mac.type == ixgbe_mac_82599EB &&
2150                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2151                 goto skip_link_setup;
2152
2153         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2154                 err = hw->mac.ops.setup_sfp(hw);
2155                 if (err)
2156                         goto error;
2157         }
2158
2159         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2160                 /* Turn on the copper */
2161                 ixgbe_set_phy_power(hw, true);
2162         } else {
2163                 /* Turn on the laser */
2164                 ixgbe_enable_tx_laser(hw);
2165         }
2166
2167         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2168         if (err)
2169                 goto error;
2170         dev->data->dev_link.link_status = link_up;
2171
2172         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2173         if (err)
2174                 goto error;
2175
2176         switch(dev->data->dev_conf.link_speed) {
2177         case ETH_LINK_SPEED_AUTONEG:
2178                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2179                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2180                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2181                 break;
2182         case ETH_LINK_SPEED_100:
2183                 /*
2184                  * Invalid for 82598 but error will be detected by
2185                  * ixgbe_setup_link()
2186                  */
2187                 speed = IXGBE_LINK_SPEED_100_FULL;
2188                 break;
2189         case ETH_LINK_SPEED_1000:
2190                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2191                 break;
2192         case ETH_LINK_SPEED_10000:
2193                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2194                 break;
2195         default:
2196                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2197                              dev->data->dev_conf.link_speed,
2198                              dev->data->port_id);
2199                 goto error;
2200         }
2201
2202         err = ixgbe_setup_link(hw, speed, link_up);
2203         if (err)
2204                 goto error;
2205
2206 skip_link_setup:
2207
2208         if (rte_intr_allow_others(intr_handle)) {
2209                 /* check if lsc interrupt is enabled */
2210                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2211                         ixgbe_dev_lsc_interrupt_setup(dev);
2212         } else {
2213                 rte_intr_callback_unregister(intr_handle,
2214                                              ixgbe_dev_interrupt_handler,
2215                                              (void *)dev);
2216                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2217                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2218                                      " no intr multiplex\n");
2219         }
2220
2221         /* check if rxq interrupt is enabled */
2222         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2223             rte_intr_dp_is_en(intr_handle))
2224                 ixgbe_dev_rxq_interrupt_setup(dev);
2225
2226         /* enable uio/vfio intr/eventfd mapping */
2227         rte_intr_enable(intr_handle);
2228
2229         /* resume enabled intr since hw reset */
2230         ixgbe_enable_intr(dev);
2231
2232         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2233                 ETH_VLAN_EXTEND_MASK;
2234         ixgbe_vlan_offload_set(dev, mask);
2235
2236         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2237                 /* Enable vlan filtering for VMDq */
2238                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2239         }
2240
2241         /* Configure DCB hw */
2242         ixgbe_configure_dcb(dev);
2243
2244         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2245                 err = ixgbe_fdir_configure(dev);
2246                 if (err)
2247                         goto error;
2248         }
2249
2250         /* Restore vf rate limit */
2251         if (vfinfo != NULL) {
2252                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2253                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2254                                 if (vfinfo[vf].tx_rate[idx] != 0)
2255                                         ixgbe_set_vf_rate_limit(dev, vf,
2256                                                 vfinfo[vf].tx_rate[idx],
2257                                                 1 << idx);
2258         }
2259
2260         ixgbe_restore_statistics_mapping(dev);
2261
2262         return 0;
2263
2264 error:
2265         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2266         ixgbe_dev_clear_queues(dev);
2267         return -EIO;
2268 }
2269
2270 /*
2271  * Stop device: disable rx and tx functions to allow for reconfiguring.
2272  */
2273 static void
2274 ixgbe_dev_stop(struct rte_eth_dev *dev)
2275 {
2276         struct rte_eth_link link;
2277         struct ixgbe_hw *hw =
2278                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2279         struct ixgbe_vf_info *vfinfo =
2280                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2281         struct ixgbe_filter_info *filter_info =
2282                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2283         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2284         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2285         int vf;
2286
2287         PMD_INIT_FUNC_TRACE();
2288
2289         /* disable interrupts */
2290         ixgbe_disable_intr(hw);
2291
2292         /* reset the NIC */
2293         ixgbe_pf_reset_hw(hw);
2294         hw->adapter_stopped = 0;
2295
2296         /* stop adapter */
2297         ixgbe_stop_adapter(hw);
2298
2299         for (vf = 0; vfinfo != NULL &&
2300                      vf < dev->pci_dev->max_vfs; vf++)
2301                 vfinfo[vf].clear_to_send = false;
2302
2303         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2304                 /* Turn off the copper */
2305                 ixgbe_set_phy_power(hw, false);
2306         } else {
2307                 /* Turn off the laser */
2308                 ixgbe_disable_tx_laser(hw);
2309         }
2310
2311         ixgbe_dev_clear_queues(dev);
2312
2313         /* Clear stored conf */
2314         dev->data->scattered_rx = 0;
2315         dev->data->lro = 0;
2316
2317         /* Clear recorded link status */
2318         memset(&link, 0, sizeof(link));
2319         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2320
2321         /* Remove all ntuple filters of the device */
2322         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2323              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2324                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2325                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2326                              p_5tuple, entries);
2327                 rte_free(p_5tuple);
2328         }
2329         memset(filter_info->fivetuple_mask, 0,
2330                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2331
2332         if (!rte_intr_allow_others(intr_handle))
2333                 /* resume to the default handler */
2334                 rte_intr_callback_register(intr_handle,
2335                                            ixgbe_dev_interrupt_handler,
2336                                            (void *)dev);
2337
2338         /* Clean datapath event and queue/vec mapping */
2339         rte_intr_efd_disable(intr_handle);
2340         if (intr_handle->intr_vec != NULL) {
2341                 rte_free(intr_handle->intr_vec);
2342                 intr_handle->intr_vec = NULL;
2343         }
2344 }
2345
2346 /*
2347  * Set device link up: enable tx.
2348  */
2349 static int
2350 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2351 {
2352         struct ixgbe_hw *hw =
2353                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2354         if (hw->mac.type == ixgbe_mac_82599EB) {
2355 #ifdef RTE_NIC_BYPASS
2356                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2357                         /* Not suported in bypass mode */
2358                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2359                                      "by device id 0x%x", hw->device_id);
2360                         return -ENOTSUP;
2361                 }
2362 #endif
2363         }
2364
2365         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2366                 /* Turn on the copper */
2367                 ixgbe_set_phy_power(hw, true);
2368         } else {
2369                 /* Turn on the laser */
2370                 ixgbe_enable_tx_laser(hw);
2371         }
2372
2373         return 0;
2374 }
2375
2376 /*
2377  * Set device link down: disable tx.
2378  */
2379 static int
2380 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2381 {
2382         struct ixgbe_hw *hw =
2383                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2384         if (hw->mac.type == ixgbe_mac_82599EB) {
2385 #ifdef RTE_NIC_BYPASS
2386                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2387                         /* Not suported in bypass mode */
2388                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2389                                      "by device id 0x%x", hw->device_id);
2390                         return -ENOTSUP;
2391                 }
2392 #endif
2393         }
2394
2395         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2396                 /* Turn off the copper */
2397                 ixgbe_set_phy_power(hw, false);
2398         } else {
2399                 /* Turn off the laser */
2400                 ixgbe_disable_tx_laser(hw);
2401         }
2402
2403         return 0;
2404 }
2405
2406 /*
2407  * Reest and stop device.
2408  */
2409 static void
2410 ixgbe_dev_close(struct rte_eth_dev *dev)
2411 {
2412         struct ixgbe_hw *hw =
2413                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2414
2415         PMD_INIT_FUNC_TRACE();
2416
2417         ixgbe_pf_reset_hw(hw);
2418
2419         ixgbe_dev_stop(dev);
2420         hw->adapter_stopped = 1;
2421
2422         ixgbe_dev_free_queues(dev);
2423
2424         ixgbe_disable_pcie_master(hw);
2425
2426         /* reprogram the RAR[0] in case user changed it. */
2427         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2428 }
2429
2430 static void
2431 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2432                            struct ixgbe_hw_stats *hw_stats,
2433                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2434                            uint64_t *total_qprc, uint64_t *total_qprdc)
2435 {
2436         uint32_t bprc, lxon, lxoff, total;
2437         uint32_t delta_gprc = 0;
2438         unsigned i;
2439         /* Workaround for RX byte count not including CRC bytes when CRC
2440 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2441          * is disabled.
2442 +        */
2443         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2444                         IXGBE_HLREG0_RXCRCSTRP);
2445
2446         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2447         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2448         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2449         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2450
2451         for (i = 0; i < 8; i++) {
2452                 uint32_t mp;
2453                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2454                 /* global total per queue */
2455                 hw_stats->mpc[i] += mp;
2456                 /* Running comprehensive total for stats display */
2457                 *total_missed_rx += hw_stats->mpc[i];
2458                 if (hw->mac.type == ixgbe_mac_82598EB) {
2459                         hw_stats->rnbc[i] +=
2460                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2461                         hw_stats->pxonrxc[i] +=
2462                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2463                         hw_stats->pxoffrxc[i] +=
2464                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2465                 } else {
2466                         hw_stats->pxonrxc[i] +=
2467                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2468                         hw_stats->pxoffrxc[i] +=
2469                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2470                         hw_stats->pxon2offc[i] +=
2471                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2472                 }
2473                 hw_stats->pxontxc[i] +=
2474                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2475                 hw_stats->pxofftxc[i] +=
2476                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2477         }
2478         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2479                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2480                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2481                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2482
2483                 delta_gprc += delta_qprc;
2484
2485                 hw_stats->qprc[i] += delta_qprc;
2486                 hw_stats->qptc[i] += delta_qptc;
2487
2488                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2489                 hw_stats->qbrc[i] +=
2490                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2491                 if (crc_strip == 0)
2492                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2493
2494                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2495                 hw_stats->qbtc[i] +=
2496                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2497
2498                 hw_stats->qprdc[i] += delta_qprdc;
2499                 *total_qprdc += hw_stats->qprdc[i];
2500
2501                 *total_qprc += hw_stats->qprc[i];
2502                 *total_qbrc += hw_stats->qbrc[i];
2503         }
2504         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2505         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2506         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2507
2508         /*
2509          * An errata states that gprc actually counts good + missed packets:
2510          * Workaround to set gprc to summated queue packet receives
2511          */
2512         hw_stats->gprc = *total_qprc;
2513
2514         if (hw->mac.type != ixgbe_mac_82598EB) {
2515                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2516                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2517                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2518                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2519                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2520                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2521                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2522                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2523         } else {
2524                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2525                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2526                 /* 82598 only has a counter in the high register */
2527                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2528                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2529                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2530         }
2531         uint64_t old_tpr = hw_stats->tpr;
2532
2533         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2534         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2535
2536         if (crc_strip == 0)
2537                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2538
2539         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2540         hw_stats->gptc += delta_gptc;
2541         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2542         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2543
2544         /*
2545          * Workaround: mprc hardware is incorrectly counting
2546          * broadcasts, so for now we subtract those.
2547          */
2548         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2549         hw_stats->bprc += bprc;
2550         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2551         if (hw->mac.type == ixgbe_mac_82598EB)
2552                 hw_stats->mprc -= bprc;
2553
2554         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2555         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2556         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2557         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2558         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2559         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2560
2561         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2562         hw_stats->lxontxc += lxon;
2563         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2564         hw_stats->lxofftxc += lxoff;
2565         total = lxon + lxoff;
2566
2567         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2568         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2569         hw_stats->gptc -= total;
2570         hw_stats->mptc -= total;
2571         hw_stats->ptc64 -= total;
2572         hw_stats->gotc -= total * ETHER_MIN_LEN;
2573
2574         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2575         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2576         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2577         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2578         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2579         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2580         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2581         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2582         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2583         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2584         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2585         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2586         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2587         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2588         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2589         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2590         /* Only read FCOE on 82599 */
2591         if (hw->mac.type != ixgbe_mac_82598EB) {
2592                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2593                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2594                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2595                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2596                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2597         }
2598
2599         /* Flow Director Stats registers */
2600         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2601         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2602 }
2603
2604 /*
2605  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2606  */
2607 static void
2608 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2609 {
2610         struct ixgbe_hw *hw =
2611                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2612         struct ixgbe_hw_stats *hw_stats =
2613                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2614         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2615         unsigned i;
2616
2617         total_missed_rx = 0;
2618         total_qbrc = 0;
2619         total_qprc = 0;
2620         total_qprdc = 0;
2621
2622         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2623                         &total_qprc, &total_qprdc);
2624
2625         if (stats == NULL)
2626                 return;
2627
2628         /* Fill out the rte_eth_stats statistics structure */
2629         stats->ipackets = total_qprc;
2630         stats->ibytes = total_qbrc;
2631         stats->opackets = hw_stats->gptc;
2632         stats->obytes = hw_stats->gotc;
2633
2634         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2635                 stats->q_ipackets[i] = hw_stats->qprc[i];
2636                 stats->q_opackets[i] = hw_stats->qptc[i];
2637                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2638                 stats->q_obytes[i] = hw_stats->qbtc[i];
2639                 stats->q_errors[i] = hw_stats->qprdc[i];
2640         }
2641
2642         /* Rx Errors */
2643         stats->imissed  = total_missed_rx;
2644         stats->ierrors  = hw_stats->crcerrs +
2645                           hw_stats->mspdc +
2646                           hw_stats->rlec +
2647                           hw_stats->ruc +
2648                           hw_stats->roc +
2649                           total_missed_rx +
2650                           hw_stats->illerrc +
2651                           hw_stats->errbc +
2652                           hw_stats->rfc +
2653                           hw_stats->fccrc +
2654                           hw_stats->fclast;
2655
2656         /* Tx Errors */
2657         stats->oerrors  = 0;
2658 }
2659
2660 static void
2661 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2662 {
2663         struct ixgbe_hw_stats *stats =
2664                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2665
2666         /* HW registers are cleared on read */
2667         ixgbe_dev_stats_get(dev, NULL);
2668
2669         /* Reset software totals */
2670         memset(stats, 0, sizeof(*stats));
2671 }
2672
2673 /* This function calculates the number of xstats based on the current config */
2674 static unsigned
2675 ixgbe_xstats_calc_num(void) {
2676         return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2677                 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2678 }
2679
2680 static int
2681 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2682                                          unsigned n)
2683 {
2684         struct ixgbe_hw *hw =
2685                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2686         struct ixgbe_hw_stats *hw_stats =
2687                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2688         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2689         unsigned i, stat, count = 0;
2690
2691         count = ixgbe_xstats_calc_num();
2692
2693         if (n < count)
2694                 return count;
2695
2696         total_missed_rx = 0;
2697         total_qbrc = 0;
2698         total_qprc = 0;
2699         total_qprdc = 0;
2700
2701         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2702                                    &total_qprc, &total_qprdc);
2703
2704         /* If this is a reset xstats is NULL, and we have cleared the
2705          * registers by reading them.
2706          */
2707         if (!xstats)
2708                 return 0;
2709
2710         /* Extended stats from ixgbe_hw_stats */
2711         count = 0;
2712         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2713                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2714                          rte_ixgbe_stats_strings[i].name);
2715                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2716                                 rte_ixgbe_stats_strings[i].offset);
2717                 count++;
2718         }
2719
2720         /* RX Priority Stats */
2721         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2722                 for (i = 0; i < 8; i++) {
2723                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2724                                  "rx_priority%u_%s", i,
2725                                  rte_ixgbe_rxq_strings[stat].name);
2726                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2727                                         rte_ixgbe_rxq_strings[stat].offset +
2728                                         (sizeof(uint64_t) * i));
2729                         count++;
2730                 }
2731         }
2732
2733         /* TX Priority Stats */
2734         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2735                 for (i = 0; i < 8; i++) {
2736                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2737                                  "tx_priority%u_%s", i,
2738                                  rte_ixgbe_txq_strings[stat].name);
2739                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2740                                         rte_ixgbe_txq_strings[stat].offset +
2741                                         (sizeof(uint64_t) * i));
2742                         count++;
2743                 }
2744         }
2745
2746         return count;
2747 }
2748
2749 static void
2750 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2751 {
2752         struct ixgbe_hw_stats *stats =
2753                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2754
2755         unsigned count = ixgbe_xstats_calc_num();
2756
2757         /* HW registers are cleared on read */
2758         ixgbe_dev_xstats_get(dev, NULL, count);
2759
2760         /* Reset software totals */
2761         memset(stats, 0, sizeof(*stats));
2762 }
2763
2764 static void
2765 ixgbevf_update_stats(struct rte_eth_dev *dev)
2766 {
2767         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2768         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2769                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2770
2771         /* Good Rx packet, include VF loopback */
2772         UPDATE_VF_STAT(IXGBE_VFGPRC,
2773             hw_stats->last_vfgprc, hw_stats->vfgprc);
2774
2775         /* Good Rx octets, include VF loopback */
2776         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2777             hw_stats->last_vfgorc, hw_stats->vfgorc);
2778
2779         /* Good Tx packet, include VF loopback */
2780         UPDATE_VF_STAT(IXGBE_VFGPTC,
2781             hw_stats->last_vfgptc, hw_stats->vfgptc);
2782
2783         /* Good Tx octets, include VF loopback */
2784         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2785             hw_stats->last_vfgotc, hw_stats->vfgotc);
2786
2787         /* Rx Multicst Packet */
2788         UPDATE_VF_STAT(IXGBE_VFMPRC,
2789             hw_stats->last_vfmprc, hw_stats->vfmprc);
2790 }
2791
2792 static int
2793 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2794                        unsigned n)
2795 {
2796         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2797                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2798         unsigned i;
2799
2800         if (n < IXGBEVF_NB_XSTATS)
2801                 return IXGBEVF_NB_XSTATS;
2802
2803         ixgbevf_update_stats(dev);
2804
2805         if (!xstats)
2806                 return 0;
2807
2808         /* Extended stats */
2809         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2810                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2811                          "%s", rte_ixgbevf_stats_strings[i].name);
2812                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2813                         rte_ixgbevf_stats_strings[i].offset);
2814         }
2815
2816         return IXGBEVF_NB_XSTATS;
2817 }
2818
2819 static void
2820 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2821 {
2822         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2823                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2824
2825         ixgbevf_update_stats(dev);
2826
2827         if (stats == NULL)
2828                 return;
2829
2830         stats->ipackets = hw_stats->vfgprc;
2831         stats->ibytes = hw_stats->vfgorc;
2832         stats->opackets = hw_stats->vfgptc;
2833         stats->obytes = hw_stats->vfgotc;
2834         stats->imcasts = hw_stats->vfmprc;
2835         /* stats->imcasts should be removed as imcasts is deprecated */
2836 }
2837
2838 static void
2839 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2840 {
2841         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2842                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2843
2844         /* Sync HW register to the last stats */
2845         ixgbevf_dev_stats_get(dev, NULL);
2846
2847         /* reset HW current stats*/
2848         hw_stats->vfgprc = 0;
2849         hw_stats->vfgorc = 0;
2850         hw_stats->vfgptc = 0;
2851         hw_stats->vfgotc = 0;
2852         hw_stats->vfmprc = 0;
2853
2854 }
2855
2856 static void
2857 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2858 {
2859         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2860
2861         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2862         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2863         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2864         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2865         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2866         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2867         dev_info->max_vfs = dev->pci_dev->max_vfs;
2868         if (hw->mac.type == ixgbe_mac_82598EB)
2869                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2870         else
2871                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2872         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2873         dev_info->rx_offload_capa =
2874                 DEV_RX_OFFLOAD_VLAN_STRIP |
2875                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2876                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2877                 DEV_RX_OFFLOAD_TCP_CKSUM;
2878
2879         /*
2880          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2881          * mode.
2882          */
2883         if ((hw->mac.type == ixgbe_mac_82599EB ||
2884              hw->mac.type == ixgbe_mac_X540) &&
2885             !RTE_ETH_DEV_SRIOV(dev).active)
2886                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2887
2888         if (hw->mac.type == ixgbe_mac_X550 ||
2889             hw->mac.type == ixgbe_mac_X550EM_x)
2890                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2891
2892         dev_info->tx_offload_capa =
2893                 DEV_TX_OFFLOAD_VLAN_INSERT |
2894                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2895                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2896                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2897                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2898                 DEV_TX_OFFLOAD_TCP_TSO;
2899
2900         if (hw->mac.type == ixgbe_mac_X550 ||
2901             hw->mac.type == ixgbe_mac_X550EM_x)
2902                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2903
2904         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2905                 .rx_thresh = {
2906                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2907                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2908                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2909                 },
2910                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2911                 .rx_drop_en = 0,
2912         };
2913
2914         dev_info->default_txconf = (struct rte_eth_txconf) {
2915                 .tx_thresh = {
2916                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2917                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2918                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2919                 },
2920                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2921                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2922                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2923                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2924         };
2925
2926         dev_info->rx_desc_lim = rx_desc_lim;
2927         dev_info->tx_desc_lim = tx_desc_lim;
2928
2929         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2930         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2931         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2932 }
2933
2934 static void
2935 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2936                      struct rte_eth_dev_info *dev_info)
2937 {
2938         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2939
2940         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2941         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2942         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2943         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2944         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2945         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2946         dev_info->max_vfs = dev->pci_dev->max_vfs;
2947         if (hw->mac.type == ixgbe_mac_82598EB)
2948                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2949         else
2950                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2951         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2952                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2953                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2954                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2955         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2956                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2957                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2958                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2959                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2960                                 DEV_TX_OFFLOAD_TCP_TSO;
2961
2962         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2963                 .rx_thresh = {
2964                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2965                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2966                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2967                 },
2968                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2969                 .rx_drop_en = 0,
2970         };
2971
2972         dev_info->default_txconf = (struct rte_eth_txconf) {
2973                 .tx_thresh = {
2974                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2975                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2976                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2977                 },
2978                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2979                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2980                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2981                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2982         };
2983
2984         dev_info->rx_desc_lim = rx_desc_lim;
2985         dev_info->tx_desc_lim = tx_desc_lim;
2986 }
2987
2988 /* return 0 means link status changed, -1 means not changed */
2989 static int
2990 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2991 {
2992         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2993         struct rte_eth_link link, old;
2994         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2995         int link_up;
2996         int diag;
2997
2998         link.link_status = 0;
2999         link.link_speed = 0;
3000         link.link_duplex = 0;
3001         memset(&old, 0, sizeof(old));
3002         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3003
3004         hw->mac.get_link_status = true;
3005
3006         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3007         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3008                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3009         else
3010                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3011
3012         if (diag != 0) {
3013                 link.link_speed = ETH_LINK_SPEED_100;
3014                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3015                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3016                 if (link.link_status == old.link_status)
3017                         return -1;
3018                 return 0;
3019         }
3020
3021         if (link_up == 0) {
3022                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3023                 if (link.link_status == old.link_status)
3024                         return -1;
3025                 return 0;
3026         }
3027         link.link_status = 1;
3028         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3029
3030         switch (link_speed) {
3031         default:
3032         case IXGBE_LINK_SPEED_UNKNOWN:
3033                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3034                 link.link_speed = ETH_LINK_SPEED_100;
3035                 break;
3036
3037         case IXGBE_LINK_SPEED_100_FULL:
3038                 link.link_speed = ETH_LINK_SPEED_100;
3039                 break;
3040
3041         case IXGBE_LINK_SPEED_1GB_FULL:
3042                 link.link_speed = ETH_LINK_SPEED_1000;
3043                 break;
3044
3045         case IXGBE_LINK_SPEED_10GB_FULL:
3046                 link.link_speed = ETH_LINK_SPEED_10000;
3047                 break;
3048         }
3049         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3050
3051         if (link.link_status == old.link_status)
3052                 return -1;
3053
3054         return 0;
3055 }
3056
3057 static void
3058 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3059 {
3060         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3061         uint32_t fctrl;
3062
3063         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3064         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3065         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3066 }
3067
3068 static void
3069 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3070 {
3071         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3072         uint32_t fctrl;
3073
3074         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3075         fctrl &= (~IXGBE_FCTRL_UPE);
3076         if (dev->data->all_multicast == 1)
3077                 fctrl |= IXGBE_FCTRL_MPE;
3078         else
3079                 fctrl &= (~IXGBE_FCTRL_MPE);
3080         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3081 }
3082
3083 static void
3084 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3085 {
3086         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3087         uint32_t fctrl;
3088
3089         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3090         fctrl |= IXGBE_FCTRL_MPE;
3091         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3092 }
3093
3094 static void
3095 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3096 {
3097         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3098         uint32_t fctrl;
3099
3100         if (dev->data->promiscuous == 1)
3101                 return; /* must remain in all_multicast mode */
3102
3103         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3104         fctrl &= (~IXGBE_FCTRL_MPE);
3105         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3106 }
3107
3108 /**
3109  * It clears the interrupt causes and enables the interrupt.
3110  * It will be called once only during nic initialized.
3111  *
3112  * @param dev
3113  *  Pointer to struct rte_eth_dev.
3114  *
3115  * @return
3116  *  - On success, zero.
3117  *  - On failure, a negative value.
3118  */
3119 static int
3120 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3121 {
3122         struct ixgbe_interrupt *intr =
3123                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3124
3125         ixgbe_dev_link_status_print(dev);
3126         intr->mask |= IXGBE_EICR_LSC;
3127
3128         return 0;
3129 }
3130
3131 /**
3132  * It clears the interrupt causes and enables the interrupt.
3133  * It will be called once only during nic initialized.
3134  *
3135  * @param dev
3136  *  Pointer to struct rte_eth_dev.
3137  *
3138  * @return
3139  *  - On success, zero.
3140  *  - On failure, a negative value.
3141  */
3142 static int
3143 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3144 {
3145         struct ixgbe_interrupt *intr =
3146                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3147
3148         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3149
3150         return 0;
3151 }
3152
3153 /*
3154  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3155  *
3156  * @param dev
3157  *  Pointer to struct rte_eth_dev.
3158  *
3159  * @return
3160  *  - On success, zero.
3161  *  - On failure, a negative value.
3162  */
3163 static int
3164 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3165 {
3166         uint32_t eicr;
3167         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3168         struct ixgbe_interrupt *intr =
3169                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3170
3171         /* clear all cause mask */
3172         ixgbe_disable_intr(hw);
3173
3174         /* read-on-clear nic registers here */
3175         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3176         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3177
3178         intr->flags = 0;
3179
3180         /* set flag for async link update */
3181         if (eicr & IXGBE_EICR_LSC)
3182                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3183
3184         if (eicr & IXGBE_EICR_MAILBOX)
3185                 intr->flags |= IXGBE_FLAG_MAILBOX;
3186
3187         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3188             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3189             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3190                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3191
3192         return 0;
3193 }
3194
3195 /**
3196  * It gets and then prints the link status.
3197  *
3198  * @param dev
3199  *  Pointer to struct rte_eth_dev.
3200  *
3201  * @return
3202  *  - On success, zero.
3203  *  - On failure, a negative value.
3204  */
3205 static void
3206 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3207 {
3208         struct rte_eth_link link;
3209
3210         memset(&link, 0, sizeof(link));
3211         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3212         if (link.link_status) {
3213                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3214                                         (int)(dev->data->port_id),
3215                                         (unsigned)link.link_speed,
3216                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3217                                         "full-duplex" : "half-duplex");
3218         } else {
3219                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3220                                 (int)(dev->data->port_id));
3221         }
3222         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3223                                 dev->pci_dev->addr.domain,
3224                                 dev->pci_dev->addr.bus,
3225                                 dev->pci_dev->addr.devid,
3226                                 dev->pci_dev->addr.function);
3227 }
3228
3229 /*
3230  * It executes link_update after knowing an interrupt occurred.
3231  *
3232  * @param dev
3233  *  Pointer to struct rte_eth_dev.
3234  *
3235  * @return
3236  *  - On success, zero.
3237  *  - On failure, a negative value.
3238  */
3239 static int
3240 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3241 {
3242         struct ixgbe_interrupt *intr =
3243                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3244         int64_t timeout;
3245         struct rte_eth_link link;
3246         int intr_enable_delay = false;
3247         struct ixgbe_hw *hw =
3248                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3249
3250         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3251
3252         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3253                 ixgbe_pf_mbx_process(dev);
3254                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3255         }
3256
3257         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3258                 ixgbe_handle_lasi(hw);
3259                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3260         }
3261
3262         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3263                 /* get the link status before link update, for predicting later */
3264                 memset(&link, 0, sizeof(link));
3265                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3266
3267                 ixgbe_dev_link_update(dev, 0);
3268
3269                 /* likely to up */
3270                 if (!link.link_status)
3271                         /* handle it 1 sec later, wait it being stable */
3272                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3273                 /* likely to down */
3274                 else
3275                         /* handle it 4 sec later, wait it being stable */
3276                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3277
3278                 ixgbe_dev_link_status_print(dev);
3279
3280                 intr_enable_delay = true;
3281         }
3282
3283         if (intr_enable_delay) {
3284                 if (rte_eal_alarm_set(timeout * 1000,
3285                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3286                         PMD_DRV_LOG(ERR, "Error setting alarm");
3287         } else {
3288                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3289                 ixgbe_enable_intr(dev);
3290                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3291         }
3292
3293
3294         return 0;
3295 }
3296
3297 /**
3298  * Interrupt handler which shall be registered for alarm callback for delayed
3299  * handling specific interrupt to wait for the stable nic state. As the
3300  * NIC interrupt state is not stable for ixgbe after link is just down,
3301  * it needs to wait 4 seconds to get the stable status.
3302  *
3303  * @param handle
3304  *  Pointer to interrupt handle.
3305  * @param param
3306  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3307  *
3308  * @return
3309  *  void
3310  */
3311 static void
3312 ixgbe_dev_interrupt_delayed_handler(void *param)
3313 {
3314         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3315         struct ixgbe_interrupt *intr =
3316                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3317         struct ixgbe_hw *hw =
3318                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3319         uint32_t eicr;
3320
3321         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3322         if (eicr & IXGBE_EICR_MAILBOX)
3323                 ixgbe_pf_mbx_process(dev);
3324
3325         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3326                 ixgbe_handle_lasi(hw);
3327                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3328         }
3329
3330         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3331                 ixgbe_dev_link_update(dev, 0);
3332                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3333                 ixgbe_dev_link_status_print(dev);
3334                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3335         }
3336
3337         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3338         ixgbe_enable_intr(dev);
3339         rte_intr_enable(&(dev->pci_dev->intr_handle));
3340 }
3341
3342 /**
3343  * Interrupt handler triggered by NIC  for handling
3344  * specific interrupt.
3345  *
3346  * @param handle
3347  *  Pointer to interrupt handle.
3348  * @param param
3349  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3350  *
3351  * @return
3352  *  void
3353  */
3354 static void
3355 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3356                             void *param)
3357 {
3358         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3359
3360         ixgbe_dev_interrupt_get_status(dev);
3361         ixgbe_dev_interrupt_action(dev);
3362 }
3363
3364 static int
3365 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3366 {
3367         struct ixgbe_hw *hw;
3368
3369         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3370         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3371 }
3372
3373 static int
3374 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3375 {
3376         struct ixgbe_hw *hw;
3377
3378         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3379         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3380 }
3381
3382 static int
3383 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3384 {
3385         struct ixgbe_hw *hw;
3386         uint32_t mflcn_reg;
3387         uint32_t fccfg_reg;
3388         int rx_pause;
3389         int tx_pause;
3390
3391         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3392
3393         fc_conf->pause_time = hw->fc.pause_time;
3394         fc_conf->high_water = hw->fc.high_water[0];
3395         fc_conf->low_water = hw->fc.low_water[0];
3396         fc_conf->send_xon = hw->fc.send_xon;
3397         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3398
3399         /*
3400          * Return rx_pause status according to actual setting of
3401          * MFLCN register.
3402          */
3403         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3404         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3405                 rx_pause = 1;
3406         else
3407                 rx_pause = 0;
3408
3409         /*
3410          * Return tx_pause status according to actual setting of
3411          * FCCFG register.
3412          */
3413         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3414         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3415                 tx_pause = 1;
3416         else
3417                 tx_pause = 0;
3418
3419         if (rx_pause && tx_pause)
3420                 fc_conf->mode = RTE_FC_FULL;
3421         else if (rx_pause)
3422                 fc_conf->mode = RTE_FC_RX_PAUSE;
3423         else if (tx_pause)
3424                 fc_conf->mode = RTE_FC_TX_PAUSE;
3425         else
3426                 fc_conf->mode = RTE_FC_NONE;
3427
3428         return 0;
3429 }
3430
3431 static int
3432 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3433 {
3434         struct ixgbe_hw *hw;
3435         int err;
3436         uint32_t rx_buf_size;
3437         uint32_t max_high_water;
3438         uint32_t mflcn;
3439         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3440                 ixgbe_fc_none,
3441                 ixgbe_fc_rx_pause,
3442                 ixgbe_fc_tx_pause,
3443                 ixgbe_fc_full
3444         };
3445
3446         PMD_INIT_FUNC_TRACE();
3447
3448         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3449         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3450         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3451
3452         /*
3453          * At least reserve one Ethernet frame for watermark
3454          * high_water/low_water in kilo bytes for ixgbe
3455          */
3456         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3457         if ((fc_conf->high_water > max_high_water) ||
3458                 (fc_conf->high_water < fc_conf->low_water)) {
3459                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3460                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3461                 return -EINVAL;
3462         }
3463
3464         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3465         hw->fc.pause_time     = fc_conf->pause_time;
3466         hw->fc.high_water[0]  = fc_conf->high_water;
3467         hw->fc.low_water[0]   = fc_conf->low_water;
3468         hw->fc.send_xon       = fc_conf->send_xon;
3469         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3470
3471         err = ixgbe_fc_enable(hw);
3472
3473         /* Not negotiated is not an error case */
3474         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3475
3476                 /* check if we want to forward MAC frames - driver doesn't have native
3477                  * capability to do that, so we'll write the registers ourselves */
3478
3479                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3480
3481                 /* set or clear MFLCN.PMCF bit depending on configuration */
3482                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3483                         mflcn |= IXGBE_MFLCN_PMCF;
3484                 else
3485                         mflcn &= ~IXGBE_MFLCN_PMCF;
3486
3487                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3488                 IXGBE_WRITE_FLUSH(hw);
3489
3490                 return 0;
3491         }
3492
3493         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3494         return -EIO;
3495 }
3496
3497 /**
3498  *  ixgbe_pfc_enable_generic - Enable flow control
3499  *  @hw: pointer to hardware structure
3500  *  @tc_num: traffic class number
3501  *  Enable flow control according to the current settings.
3502  */
3503 static int
3504 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3505 {
3506         int ret_val = 0;
3507         uint32_t mflcn_reg, fccfg_reg;
3508         uint32_t reg;
3509         uint32_t fcrtl, fcrth;
3510         uint8_t i;
3511         uint8_t nb_rx_en;
3512
3513         /* Validate the water mark configuration */
3514         if (!hw->fc.pause_time) {
3515                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3516                 goto out;
3517         }
3518
3519         /* Low water mark of zero causes XOFF floods */
3520         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3521                  /* High/Low water can not be 0 */
3522                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3523                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3524                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3525                         goto out;
3526                 }
3527
3528                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3529                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3530                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3531                         goto out;
3532                 }
3533         }
3534         /* Negotiate the fc mode to use */
3535         ixgbe_fc_autoneg(hw);
3536
3537         /* Disable any previous flow control settings */
3538         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3539         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3540
3541         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3542         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3543
3544         switch (hw->fc.current_mode) {
3545         case ixgbe_fc_none:
3546                 /*
3547                  * If the count of enabled RX Priority Flow control >1,
3548                  * and the TX pause can not be disabled
3549                  */
3550                 nb_rx_en = 0;
3551                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3552                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3553                         if (reg & IXGBE_FCRTH_FCEN)
3554                                 nb_rx_en++;
3555                 }
3556                 if (nb_rx_en > 1)
3557                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3558                 break;
3559         case ixgbe_fc_rx_pause:
3560                 /*
3561                  * Rx Flow control is enabled and Tx Flow control is
3562                  * disabled by software override. Since there really
3563                  * isn't a way to advertise that we are capable of RX
3564                  * Pause ONLY, we will advertise that we support both
3565                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3566                  * disable the adapter's ability to send PAUSE frames.
3567                  */
3568                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3569                 /*
3570                  * If the count of enabled RX Priority Flow control >1,
3571                  * and the TX pause can not be disabled
3572                  */
3573                 nb_rx_en = 0;
3574                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3575                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3576                         if (reg & IXGBE_FCRTH_FCEN)
3577                                 nb_rx_en++;
3578                 }
3579                 if (nb_rx_en > 1)
3580                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3581                 break;
3582         case ixgbe_fc_tx_pause:
3583                 /*
3584                  * Tx Flow control is enabled, and Rx Flow control is
3585                  * disabled by software override.
3586                  */
3587                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3588                 break;
3589         case ixgbe_fc_full:
3590                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3591                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3592                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3593                 break;
3594         default:
3595                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3596                 ret_val = IXGBE_ERR_CONFIG;
3597                 goto out;
3598                 break;
3599         }
3600
3601         /* Set 802.3x based flow control settings. */
3602         mflcn_reg |= IXGBE_MFLCN_DPF;
3603         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3604         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3605
3606         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3607         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3608                 hw->fc.high_water[tc_num]) {
3609                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3610                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3611                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3612         } else {
3613                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3614                 /*
3615                  * In order to prevent Tx hangs when the internal Tx
3616                  * switch is enabled we must set the high water mark
3617                  * to the maximum FCRTH value.  This allows the Tx
3618                  * switch to function even under heavy Rx workloads.
3619                  */
3620                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3621         }
3622         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3623
3624         /* Configure pause time (2 TCs per register) */
3625         reg = hw->fc.pause_time * 0x00010001;
3626         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3627                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3628
3629         /* Configure flow control refresh threshold value */
3630         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3631
3632 out:
3633         return ret_val;
3634 }
3635
3636 static int
3637 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3638 {
3639         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3640         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3641
3642         if (hw->mac.type != ixgbe_mac_82598EB) {
3643                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3644         }
3645         return ret_val;
3646 }
3647
3648 static int
3649 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3650 {
3651         int err;
3652         uint32_t rx_buf_size;
3653         uint32_t max_high_water;
3654         uint8_t tc_num;
3655         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3656         struct ixgbe_hw *hw =
3657                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3658         struct ixgbe_dcb_config *dcb_config =
3659                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3660
3661         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3662                 ixgbe_fc_none,
3663                 ixgbe_fc_rx_pause,
3664                 ixgbe_fc_tx_pause,
3665                 ixgbe_fc_full
3666         };
3667
3668         PMD_INIT_FUNC_TRACE();
3669
3670         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3671         tc_num = map[pfc_conf->priority];
3672         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3673         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3674         /*
3675          * At least reserve one Ethernet frame for watermark
3676          * high_water/low_water in kilo bytes for ixgbe
3677          */
3678         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3679         if ((pfc_conf->fc.high_water > max_high_water) ||
3680             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3681                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3682                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3683                 return -EINVAL;
3684         }
3685
3686         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3687         hw->fc.pause_time = pfc_conf->fc.pause_time;
3688         hw->fc.send_xon = pfc_conf->fc.send_xon;
3689         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3690         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3691
3692         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3693
3694         /* Not negotiated is not an error case */
3695         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3696                 return 0;
3697
3698         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3699         return -EIO;
3700 }
3701
3702 static int
3703 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3704                           struct rte_eth_rss_reta_entry64 *reta_conf,
3705                           uint16_t reta_size)
3706 {
3707         uint8_t i, j, mask;
3708         uint32_t reta, r;
3709         uint16_t idx, shift;
3710         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3711         uint16_t sp_reta_size;
3712         uint32_t reta_reg;
3713
3714         PMD_INIT_FUNC_TRACE();
3715
3716         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3717                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3718                         "NIC.");
3719                 return -ENOTSUP;
3720         }
3721
3722         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3723         if (reta_size != sp_reta_size) {
3724                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3725                         "(%d) doesn't match the number hardware can supported "
3726                         "(%d)\n", reta_size, sp_reta_size);
3727                 return -EINVAL;
3728         }
3729
3730         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3731                 idx = i / RTE_RETA_GROUP_SIZE;
3732                 shift = i % RTE_RETA_GROUP_SIZE;
3733                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3734                                                 IXGBE_4_BIT_MASK);
3735                 if (!mask)
3736                         continue;
3737                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3738                 if (mask == IXGBE_4_BIT_MASK)
3739                         r = 0;
3740                 else
3741                         r = IXGBE_READ_REG(hw, reta_reg);
3742                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3743                         if (mask & (0x1 << j))
3744                                 reta |= reta_conf[idx].reta[shift + j] <<
3745                                                         (CHAR_BIT * j);
3746                         else
3747                                 reta |= r & (IXGBE_8_BIT_MASK <<
3748                                                 (CHAR_BIT * j));
3749                 }
3750                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3751         }
3752
3753         return 0;
3754 }
3755
3756 static int
3757 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3758                          struct rte_eth_rss_reta_entry64 *reta_conf,
3759                          uint16_t reta_size)
3760 {
3761         uint8_t i, j, mask;
3762         uint32_t reta;
3763         uint16_t idx, shift;
3764         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3765         uint16_t sp_reta_size;
3766         uint32_t reta_reg;
3767
3768         PMD_INIT_FUNC_TRACE();
3769         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3770         if (reta_size != sp_reta_size) {
3771                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3772                         "(%d) doesn't match the number hardware can supported "
3773                         "(%d)\n", reta_size, sp_reta_size);
3774                 return -EINVAL;
3775         }
3776
3777         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3778                 idx = i / RTE_RETA_GROUP_SIZE;
3779                 shift = i % RTE_RETA_GROUP_SIZE;
3780                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3781                                                 IXGBE_4_BIT_MASK);
3782                 if (!mask)
3783                         continue;
3784
3785                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3786                 reta = IXGBE_READ_REG(hw, reta_reg);
3787                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3788                         if (mask & (0x1 << j))
3789                                 reta_conf[idx].reta[shift + j] =
3790                                         ((reta >> (CHAR_BIT * j)) &
3791                                                 IXGBE_8_BIT_MASK);
3792                 }
3793         }
3794
3795         return 0;
3796 }
3797
3798 static void
3799 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3800                                 uint32_t index, uint32_t pool)
3801 {
3802         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3803         uint32_t enable_addr = 1;
3804
3805         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3806 }
3807
3808 static void
3809 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3810 {
3811         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3812
3813         ixgbe_clear_rar(hw, index);
3814 }
3815
3816 static void
3817 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3818 {
3819         ixgbe_remove_rar(dev, 0);
3820
3821         ixgbe_add_rar(dev, addr, 0, 0);
3822 }
3823
3824 static int
3825 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3826 {
3827         uint32_t hlreg0;
3828         uint32_t maxfrs;
3829         struct ixgbe_hw *hw;
3830         struct rte_eth_dev_info dev_info;
3831         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3832
3833         ixgbe_dev_info_get(dev, &dev_info);
3834
3835         /* check that mtu is within the allowed range */
3836         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3837                 return -EINVAL;
3838
3839         /* refuse mtu that requires the support of scattered packets when this
3840          * feature has not been enabled before. */
3841         if (!dev->data->scattered_rx &&
3842             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3843              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3844                 return -EINVAL;
3845
3846         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3847         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3848
3849         /* switch to jumbo mode if needed */
3850         if (frame_size > ETHER_MAX_LEN) {
3851                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3852                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3853         } else {
3854                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3855                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3856         }
3857         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3858
3859         /* update max frame size */
3860         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3861
3862         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3863         maxfrs &= 0x0000FFFF;
3864         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3865         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3866
3867         return 0;
3868 }
3869
3870 /*
3871  * Virtual Function operations
3872  */
3873 static void
3874 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3875 {
3876         PMD_INIT_FUNC_TRACE();
3877
3878         /* Clear interrupt mask to stop from interrupts being generated */
3879         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3880
3881         IXGBE_WRITE_FLUSH(hw);
3882 }
3883
3884 static void
3885 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3886 {
3887         PMD_INIT_FUNC_TRACE();
3888
3889         /* VF enable interrupt autoclean */
3890         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3891         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3892         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3893
3894         IXGBE_WRITE_FLUSH(hw);
3895 }
3896
3897 static int
3898 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3899 {
3900         struct rte_eth_conf* conf = &dev->data->dev_conf;
3901         struct ixgbe_adapter *adapter =
3902                         (struct ixgbe_adapter *)dev->data->dev_private;
3903
3904         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3905                      dev->data->port_id);
3906
3907         /*
3908          * VF has no ability to enable/disable HW CRC
3909          * Keep the persistent behavior the same as Host PF
3910          */
3911 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3912         if (!conf->rxmode.hw_strip_crc) {
3913                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3914                 conf->rxmode.hw_strip_crc = 1;
3915         }
3916 #else
3917         if (conf->rxmode.hw_strip_crc) {
3918                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3919                 conf->rxmode.hw_strip_crc = 0;
3920         }
3921 #endif
3922
3923         /*
3924          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3925          * allocation or vector Rx preconditions we will reset it.
3926          */
3927         adapter->rx_bulk_alloc_allowed = true;
3928         adapter->rx_vec_allowed = true;
3929
3930         return 0;
3931 }
3932
3933 static int
3934 ixgbevf_dev_start(struct rte_eth_dev *dev)
3935 {
3936         struct ixgbe_hw *hw =
3937                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3938         uint32_t intr_vector = 0;
3939         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3940
3941         int err, mask = 0;
3942
3943         PMD_INIT_FUNC_TRACE();
3944
3945         hw->mac.ops.reset_hw(hw);
3946         hw->mac.get_link_status = true;
3947
3948         /* negotiate mailbox API version to use with the PF. */
3949         ixgbevf_negotiate_api(hw);
3950
3951         ixgbevf_dev_tx_init(dev);
3952
3953         /* This can fail when allocating mbufs for descriptor rings */
3954         err = ixgbevf_dev_rx_init(dev);
3955         if (err) {
3956                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3957                 ixgbe_dev_clear_queues(dev);
3958                 return err;
3959         }
3960
3961         /* Set vfta */
3962         ixgbevf_set_vfta_all(dev,1);
3963
3964         /* Set HW strip */
3965         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3966                 ETH_VLAN_EXTEND_MASK;
3967         ixgbevf_vlan_offload_set(dev, mask);
3968
3969         ixgbevf_dev_rxtx_start(dev);
3970
3971         /* check and configure queue intr-vector mapping */
3972         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3973                 intr_vector = dev->data->nb_rx_queues;
3974                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3975                         return -1;
3976         }
3977
3978         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3979                 intr_handle->intr_vec =
3980                         rte_zmalloc("intr_vec",
3981                                     dev->data->nb_rx_queues * sizeof(int), 0);
3982                 if (intr_handle->intr_vec == NULL) {
3983                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3984                                      " intr_vec\n", dev->data->nb_rx_queues);
3985                         return -ENOMEM;
3986                 }
3987         }
3988         ixgbevf_configure_msix(dev);
3989
3990         rte_intr_enable(intr_handle);
3991
3992         /* Re-enable interrupt for VF */
3993         ixgbevf_intr_enable(hw);
3994
3995         return 0;
3996 }
3997
3998 static void
3999 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4000 {
4001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4002         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4003
4004         PMD_INIT_FUNC_TRACE();
4005
4006         hw->adapter_stopped = 1;
4007         ixgbe_stop_adapter(hw);
4008
4009         /*
4010           * Clear what we set, but we still keep shadow_vfta to
4011           * restore after device starts
4012           */
4013         ixgbevf_set_vfta_all(dev,0);
4014
4015         /* Clear stored conf */
4016         dev->data->scattered_rx = 0;
4017
4018         ixgbe_dev_clear_queues(dev);
4019
4020         /* Clean datapath event and queue/vec mapping */
4021         rte_intr_efd_disable(intr_handle);
4022         if (intr_handle->intr_vec != NULL) {
4023                 rte_free(intr_handle->intr_vec);
4024                 intr_handle->intr_vec = NULL;
4025         }
4026 }
4027
4028 static void
4029 ixgbevf_dev_close(struct rte_eth_dev *dev)
4030 {
4031         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4032
4033         PMD_INIT_FUNC_TRACE();
4034
4035         ixgbe_reset_hw(hw);
4036
4037         ixgbevf_dev_stop(dev);
4038
4039         ixgbe_dev_free_queues(dev);
4040
4041         /**
4042          * Remove the VF MAC address ro ensure
4043          * that the VF traffic goes to the PF
4044          * after stop, close and detach of the VF
4045          **/
4046         ixgbevf_remove_mac_addr(dev, 0);
4047 }
4048
4049 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4050 {
4051         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4052         struct ixgbe_vfta * shadow_vfta =
4053                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4054         int i = 0, j = 0, vfta = 0, mask = 1;
4055
4056         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
4057                 vfta = shadow_vfta->vfta[i];
4058                 if (vfta) {
4059                         mask = 1;
4060                         for (j = 0; j < 32; j++){
4061                                 if (vfta & mask)
4062                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4063                                 mask<<=1;
4064                         }
4065                 }
4066         }
4067
4068 }
4069
4070 static int
4071 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4072 {
4073         struct ixgbe_hw *hw =
4074                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4075         struct ixgbe_vfta * shadow_vfta =
4076                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4077         uint32_t vid_idx = 0;
4078         uint32_t vid_bit = 0;
4079         int ret = 0;
4080
4081         PMD_INIT_FUNC_TRACE();
4082
4083         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4084         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4085         if (ret) {
4086                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4087                 return ret;
4088         }
4089         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4090         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4091
4092         /* Save what we set and retore it after device reset */
4093         if (on)
4094                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4095         else
4096                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4097
4098         return 0;
4099 }
4100
4101 static void
4102 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4103 {
4104         struct ixgbe_hw *hw =
4105                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4106         uint32_t ctrl;
4107
4108         PMD_INIT_FUNC_TRACE();
4109
4110         if (queue >= hw->mac.max_rx_queues)
4111                 return;
4112
4113         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4114         if (on)
4115                 ctrl |= IXGBE_RXDCTL_VME;
4116         else
4117                 ctrl &= ~IXGBE_RXDCTL_VME;
4118         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4119
4120         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4121 }
4122
4123 static void
4124 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4125 {
4126         struct ixgbe_hw *hw =
4127                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4128         uint16_t i;
4129         int on = 0;
4130
4131         /* VF function only support hw strip feature, others are not support */
4132         if (mask & ETH_VLAN_STRIP_MASK) {
4133                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4134
4135                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4136                         ixgbevf_vlan_strip_queue_set(dev,i,on);
4137         }
4138 }
4139
4140 static int
4141 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4142 {
4143         uint32_t reg_val;
4144
4145         /* we only need to do this if VMDq is enabled */
4146         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4147         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4148                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4149                 return -1;
4150         }
4151
4152         return 0;
4153 }
4154
4155 static uint32_t
4156 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4157 {
4158         uint32_t vector = 0;
4159         switch (hw->mac.mc_filter_type) {
4160         case 0:   /* use bits [47:36] of the address */
4161                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4162                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4163                 break;
4164         case 1:   /* use bits [46:35] of the address */
4165                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4166                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4167                 break;
4168         case 2:   /* use bits [45:34] of the address */
4169                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4170                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4171                 break;
4172         case 3:   /* use bits [43:32] of the address */
4173                 vector = ((uc_addr->addr_bytes[4]) |
4174                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4175                 break;
4176         default:  /* Invalid mc_filter_type */
4177                 break;
4178         }
4179
4180         /* vector can only be 12-bits or boundary will be exceeded */
4181         vector &= 0xFFF;
4182         return vector;
4183 }
4184
4185 static int
4186 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4187                                uint8_t on)
4188 {
4189         uint32_t vector;
4190         uint32_t uta_idx;
4191         uint32_t reg_val;
4192         uint32_t uta_shift;
4193         uint32_t rc;
4194         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4195         const uint32_t ixgbe_uta_bit_shift = 5;
4196         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4197         const uint32_t bit1 = 0x1;
4198
4199         struct ixgbe_hw *hw =
4200                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4201         struct ixgbe_uta_info *uta_info =
4202                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4203
4204         /* The UTA table only exists on 82599 hardware and newer */
4205         if (hw->mac.type < ixgbe_mac_82599EB)
4206                 return -ENOTSUP;
4207
4208         vector = ixgbe_uta_vector(hw,mac_addr);
4209         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4210         uta_shift = vector & ixgbe_uta_bit_mask;
4211
4212         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4213         if (rc == on)
4214                 return 0;
4215
4216         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4217         if (on) {
4218                 uta_info->uta_in_use++;
4219                 reg_val |= (bit1 << uta_shift);
4220                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4221         } else {
4222                 uta_info->uta_in_use--;
4223                 reg_val &= ~(bit1 << uta_shift);
4224                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4225         }
4226
4227         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4228
4229         if (uta_info->uta_in_use > 0)
4230                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4231                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4232         else
4233                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4234
4235         return 0;
4236 }
4237
4238 static int
4239 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4240 {
4241         int i;
4242         struct ixgbe_hw *hw =
4243                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4244         struct ixgbe_uta_info *uta_info =
4245                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4246
4247         /* The UTA table only exists on 82599 hardware and newer */
4248         if (hw->mac.type < ixgbe_mac_82599EB)
4249                 return -ENOTSUP;
4250
4251         if (on) {
4252                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4253                         uta_info->uta_shadow[i] = ~0;
4254                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4255                 }
4256         } else {
4257                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4258                         uta_info->uta_shadow[i] = 0;
4259                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4260                 }
4261         }
4262         return 0;
4263
4264 }
4265
4266 uint32_t
4267 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4268 {
4269         uint32_t new_val = orig_val;
4270
4271         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4272                 new_val |= IXGBE_VMOLR_AUPE;
4273         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4274                 new_val |= IXGBE_VMOLR_ROMPE;
4275         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4276                 new_val |= IXGBE_VMOLR_ROPE;
4277         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4278                 new_val |= IXGBE_VMOLR_BAM;
4279         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4280                 new_val |= IXGBE_VMOLR_MPE;
4281
4282         return new_val;
4283 }
4284
4285 static int
4286 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4287                                uint16_t rx_mask, uint8_t on)
4288 {
4289         int val = 0;
4290
4291         struct ixgbe_hw *hw =
4292                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4293         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4294
4295         if (hw->mac.type == ixgbe_mac_82598EB) {
4296                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4297                              " on 82599 hardware and newer");
4298                 return -ENOTSUP;
4299         }
4300         if (ixgbe_vmdq_mode_check(hw) < 0)
4301                 return -ENOTSUP;
4302
4303         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4304
4305         if (on)
4306                 vmolr |= val;
4307         else
4308                 vmolr &= ~val;
4309
4310         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4311
4312         return 0;
4313 }
4314
4315 static int
4316 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4317 {
4318         uint32_t reg,addr;
4319         uint32_t val;
4320         const uint8_t bit1 = 0x1;
4321
4322         struct ixgbe_hw *hw =
4323                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4324
4325         if (ixgbe_vmdq_mode_check(hw) < 0)
4326                 return -ENOTSUP;
4327
4328         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4329         reg = IXGBE_READ_REG(hw, addr);
4330         val = bit1 << pool;
4331
4332         if (on)
4333                 reg |= val;
4334         else
4335                 reg &= ~val;
4336
4337         IXGBE_WRITE_REG(hw, addr,reg);
4338
4339         return 0;
4340 }
4341
4342 static int
4343 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4344 {
4345         uint32_t reg,addr;
4346         uint32_t val;
4347         const uint8_t bit1 = 0x1;
4348
4349         struct ixgbe_hw *hw =
4350                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4351
4352         if (ixgbe_vmdq_mode_check(hw) < 0)
4353                 return -ENOTSUP;
4354
4355         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4356         reg = IXGBE_READ_REG(hw, addr);
4357         val = bit1 << pool;
4358
4359         if (on)
4360                 reg |= val;
4361         else
4362                 reg &= ~val;
4363
4364         IXGBE_WRITE_REG(hw, addr,reg);
4365
4366         return 0;
4367 }
4368
4369 static int
4370 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4371                         uint64_t pool_mask, uint8_t vlan_on)
4372 {
4373         int ret = 0;
4374         uint16_t pool_idx;
4375         struct ixgbe_hw *hw =
4376                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4377
4378         if (ixgbe_vmdq_mode_check(hw) < 0)
4379                 return -ENOTSUP;
4380         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4381                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4382                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4383                         if (ret < 0)
4384                                 return ret;
4385         }
4386
4387         return ret;
4388 }
4389
4390 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4391 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4392 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4393 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4394 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4395         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4396         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4397
4398 static int
4399 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4400                         struct rte_eth_mirror_conf *mirror_conf,
4401                         uint8_t rule_id, uint8_t on)
4402 {
4403         uint32_t mr_ctl,vlvf;
4404         uint32_t mp_lsb = 0;
4405         uint32_t mv_msb = 0;
4406         uint32_t mv_lsb = 0;
4407         uint32_t mp_msb = 0;
4408         uint8_t i = 0;
4409         int reg_index = 0;
4410         uint64_t vlan_mask = 0;
4411
4412         const uint8_t pool_mask_offset = 32;
4413         const uint8_t vlan_mask_offset = 32;
4414         const uint8_t dst_pool_offset = 8;
4415         const uint8_t rule_mr_offset  = 4;
4416         const uint8_t mirror_rule_mask= 0x0F;
4417
4418         struct ixgbe_mirror_info *mr_info =
4419                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4420         struct ixgbe_hw *hw =
4421                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4422         uint8_t mirror_type = 0;
4423
4424         if (ixgbe_vmdq_mode_check(hw) < 0)
4425                 return -ENOTSUP;
4426
4427         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4428                 return -EINVAL;
4429
4430         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4431                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4432                         mirror_conf->rule_type);
4433                 return -EINVAL;
4434         }
4435
4436         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4437                 mirror_type |= IXGBE_MRCTL_VLME;
4438                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4439                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4440                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4441                                 /* search vlan id related pool vlan filter index */
4442                                 reg_index = ixgbe_find_vlvf_slot(hw,
4443                                                 mirror_conf->vlan.vlan_id[i]);
4444                                 if (reg_index < 0)
4445                                         return -EINVAL;
4446                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4447                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4448                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4449                                       mirror_conf->vlan.vlan_id[i]))
4450                                         vlan_mask |= (1ULL << reg_index);
4451                                 else
4452                                         return -EINVAL;
4453                         }
4454                 }
4455
4456                 if (on) {
4457                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4458                         mv_msb = vlan_mask >> vlan_mask_offset;
4459
4460                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4461                                                 mirror_conf->vlan.vlan_mask;
4462                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4463                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4464                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4465                                                 mirror_conf->vlan.vlan_id[i];
4466                         }
4467                 } else {
4468                         mv_lsb = 0;
4469                         mv_msb = 0;
4470                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4471                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4472                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4473                 }
4474         }
4475
4476         /*
4477          * if enable pool mirror, write related pool mask register,if disable
4478          * pool mirror, clear PFMRVM register
4479          */
4480         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4481                 mirror_type |= IXGBE_MRCTL_VPME;
4482                 if (on) {
4483                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4484                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4485                         mr_info->mr_conf[rule_id].pool_mask =
4486                                         mirror_conf->pool_mask;
4487
4488                 } else {
4489                         mp_lsb = 0;
4490                         mp_msb = 0;
4491                         mr_info->mr_conf[rule_id].pool_mask = 0;
4492                 }
4493         }
4494         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4495                 mirror_type |= IXGBE_MRCTL_UPME;
4496         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4497                 mirror_type |= IXGBE_MRCTL_DPME;
4498
4499         /* read  mirror control register and recalculate it */
4500         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4501
4502         if (on) {
4503                 mr_ctl |= mirror_type;
4504                 mr_ctl &= mirror_rule_mask;
4505                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4506         } else
4507                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4508
4509         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4510         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4511
4512         /* write mirrror control  register */
4513         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4514
4515         /* write pool mirrror control  register */
4516         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4517                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4518                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4519                                 mp_msb);
4520         }
4521         /* write VLAN mirrror control  register */
4522         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4523                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4524                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4525                                 mv_msb);
4526         }
4527
4528         return 0;
4529 }
4530
4531 static int
4532 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4533 {
4534         int mr_ctl = 0;
4535         uint32_t lsb_val = 0;
4536         uint32_t msb_val = 0;
4537         const uint8_t rule_mr_offset = 4;
4538
4539         struct ixgbe_hw *hw =
4540                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4541         struct ixgbe_mirror_info *mr_info =
4542                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4543
4544         if (ixgbe_vmdq_mode_check(hw) < 0)
4545                 return -ENOTSUP;
4546
4547         memset(&mr_info->mr_conf[rule_id], 0,
4548                 sizeof(struct rte_eth_mirror_conf));
4549
4550         /* clear PFVMCTL register */
4551         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4552
4553         /* clear pool mask register */
4554         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4555         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4556
4557         /* clear vlan mask register */
4558         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4559         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4560
4561         return 0;
4562 }
4563
4564 static int
4565 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4566 {
4567         uint32_t mask;
4568         struct ixgbe_hw *hw =
4569                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4570
4571         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4572         mask |= (1 << IXGBE_MISC_VEC_ID);
4573         RTE_SET_USED(queue_id);
4574         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4575
4576         rte_intr_enable(&dev->pci_dev->intr_handle);
4577
4578         return 0;
4579 }
4580
4581 static int
4582 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4583 {
4584         uint32_t mask;
4585         struct ixgbe_hw *hw =
4586                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4587
4588         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4589         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4590         RTE_SET_USED(queue_id);
4591         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4592
4593         return 0;
4594 }
4595
4596 static int
4597 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4598 {
4599         uint32_t mask;
4600         struct ixgbe_hw *hw =
4601                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4602         struct ixgbe_interrupt *intr =
4603                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4604
4605         if (queue_id < 16) {
4606                 ixgbe_disable_intr(hw);
4607                 intr->mask |= (1 << queue_id);
4608                 ixgbe_enable_intr(dev);
4609         } else if (queue_id < 32) {
4610                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4611                 mask &= (1 << queue_id);
4612                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4613         } else if (queue_id < 64) {
4614                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4615                 mask &= (1 << (queue_id - 32));
4616                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4617         }
4618         rte_intr_enable(&dev->pci_dev->intr_handle);
4619
4620         return 0;
4621 }
4622
4623 static int
4624 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4625 {
4626         uint32_t mask;
4627         struct ixgbe_hw *hw =
4628                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4629         struct ixgbe_interrupt *intr =
4630                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4631
4632         if (queue_id < 16) {
4633                 ixgbe_disable_intr(hw);
4634                 intr->mask &= ~(1 << queue_id);
4635                 ixgbe_enable_intr(dev);
4636         } else if (queue_id < 32) {
4637                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4638                 mask &= ~(1 << queue_id);
4639                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4640         } else if (queue_id < 64) {
4641                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4642                 mask &= ~(1 << (queue_id - 32));
4643                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4644         }
4645
4646         return 0;
4647 }
4648
4649 static void
4650 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4651                      uint8_t queue, uint8_t msix_vector)
4652 {
4653         uint32_t tmp, idx;
4654
4655         if (direction == -1) {
4656                 /* other causes */
4657                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4658                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4659                 tmp &= ~0xFF;
4660                 tmp |= msix_vector;
4661                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4662         } else {
4663                 /* rx or tx cause */
4664                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4665                 idx = ((16 * (queue & 1)) + (8 * direction));
4666                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4667                 tmp &= ~(0xFF << idx);
4668                 tmp |= (msix_vector << idx);
4669                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4670         }
4671 }
4672
4673 /**
4674  * set the IVAR registers, mapping interrupt causes to vectors
4675  * @param hw
4676  *  pointer to ixgbe_hw struct
4677  * @direction
4678  *  0 for Rx, 1 for Tx, -1 for other causes
4679  * @queue
4680  *  queue to map the corresponding interrupt to
4681  * @msix_vector
4682  *  the vector to map to the corresponding queue
4683  */
4684 static void
4685 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4686                    uint8_t queue, uint8_t msix_vector)
4687 {
4688         uint32_t tmp, idx;
4689
4690         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4691         if (hw->mac.type == ixgbe_mac_82598EB) {
4692                 if (direction == -1)
4693                         direction = 0;
4694                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4695                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4696                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4697                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4698                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4699         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4700                         (hw->mac.type == ixgbe_mac_X540)) {
4701                 if (direction == -1) {
4702                         /* other causes */
4703                         idx = ((queue & 1) * 8);
4704                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4705                         tmp &= ~(0xFF << idx);
4706                         tmp |= (msix_vector << idx);
4707                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4708                 } else {
4709                         /* rx or tx causes */
4710                         idx = ((16 * (queue & 1)) + (8 * direction));
4711                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4712                         tmp &= ~(0xFF << idx);
4713                         tmp |= (msix_vector << idx);
4714                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4715                 }
4716         }
4717 }
4718
4719 static void
4720 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4721 {
4722         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4723         struct ixgbe_hw *hw =
4724                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4725         uint32_t q_idx;
4726         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4727
4728         /* won't configure msix register if no mapping is done
4729          * between intr vector and event fd.
4730          */
4731         if (!rte_intr_dp_is_en(intr_handle))
4732                 return;
4733
4734         /* Configure all RX queues of VF */
4735         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4736                 /* Force all queue use vector 0,
4737                  * as IXGBE_VF_MAXMSIVECOTR = 1
4738                  */
4739                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4740                 intr_handle->intr_vec[q_idx] = vector_idx;
4741         }
4742
4743         /* Configure VF other cause ivar */
4744         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4745 }
4746
4747 /**
4748  * Sets up the hardware to properly generate MSI-X interrupts
4749  * @hw
4750  *  board private structure
4751  */
4752 static void
4753 ixgbe_configure_msix(struct rte_eth_dev *dev)
4754 {
4755         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4756         struct ixgbe_hw *hw =
4757                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4758         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4759         uint32_t vec = IXGBE_MISC_VEC_ID;
4760         uint32_t mask;
4761         uint32_t gpie;
4762
4763         /* won't configure msix register if no mapping is done
4764          * between intr vector and event fd
4765          */
4766         if (!rte_intr_dp_is_en(intr_handle))
4767                 return;
4768
4769         if (rte_intr_allow_others(intr_handle))
4770                 vec = base = IXGBE_RX_VEC_START;
4771
4772         /* setup GPIE for MSI-x mode */
4773         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4774         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4775                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4776         /* auto clearing and auto setting corresponding bits in EIMS
4777          * when MSI-X interrupt is triggered
4778          */
4779         if (hw->mac.type == ixgbe_mac_82598EB) {
4780                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4781         } else {
4782                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4783                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4784         }
4785         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4786
4787         /* Populate the IVAR table and set the ITR values to the
4788          * corresponding register.
4789          */
4790         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4791              queue_id++) {
4792                 /* by default, 1:1 mapping */
4793                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4794                 intr_handle->intr_vec[queue_id] = vec;
4795                 if (vec < base + intr_handle->nb_efd - 1)
4796                         vec++;
4797         }
4798
4799         switch (hw->mac.type) {
4800         case ixgbe_mac_82598EB:
4801                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4802                                    IXGBE_MISC_VEC_ID);
4803                 break;
4804         case ixgbe_mac_82599EB:
4805         case ixgbe_mac_X540:
4806                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4807                 break;
4808         default:
4809                 break;
4810         }
4811         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4812                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4813
4814         /* set up to autoclear timer, and the vectors */
4815         mask = IXGBE_EIMS_ENABLE_MASK;
4816         mask &= ~(IXGBE_EIMS_OTHER |
4817                   IXGBE_EIMS_MAILBOX |
4818                   IXGBE_EIMS_LSC);
4819
4820         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4821 }
4822
4823 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4824         uint16_t queue_idx, uint16_t tx_rate)
4825 {
4826         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4827         uint32_t rf_dec, rf_int;
4828         uint32_t bcnrc_val;
4829         uint16_t link_speed = dev->data->dev_link.link_speed;
4830
4831         if (queue_idx >= hw->mac.max_tx_queues)
4832                 return -EINVAL;
4833
4834         if (tx_rate != 0) {
4835                 /* Calculate the rate factor values to set */
4836                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4837                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4838                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4839
4840                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4841                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4842                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4843                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4844         } else {
4845                 bcnrc_val = 0;
4846         }
4847
4848         /*
4849          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4850          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4851          * set as 0x4.
4852          */
4853         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4854                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4855                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4856                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4857                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4858         else
4859                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4860                         IXGBE_MMW_SIZE_DEFAULT);
4861
4862         /* Set RTTBCNRC of queue X */
4863         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4864         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4865         IXGBE_WRITE_FLUSH(hw);
4866
4867         return 0;
4868 }
4869
4870 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4871         uint16_t tx_rate, uint64_t q_msk)
4872 {
4873         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4874         struct ixgbe_vf_info *vfinfo =
4875                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4876         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4877         uint32_t queue_stride =
4878                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4879         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4880         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4881         uint16_t total_rate = 0;
4882
4883         if (queue_end >= hw->mac.max_tx_queues)
4884                 return -EINVAL;
4885
4886         if (vfinfo != NULL) {
4887                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4888                         if (vf_idx == vf)
4889                                 continue;
4890                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4891                                 idx++)
4892                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4893                 }
4894         } else
4895                 return -EINVAL;
4896
4897         /* Store tx_rate for this vf. */
4898         for (idx = 0; idx < nb_q_per_pool; idx++) {
4899                 if (((uint64_t)0x1 << idx) & q_msk) {
4900                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4901                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4902                         total_rate += tx_rate;
4903                 }
4904         }
4905
4906         if (total_rate > dev->data->dev_link.link_speed) {
4907                 /*
4908                  * Reset stored TX rate of the VF if it causes exceed
4909                  * link speed.
4910                  */
4911                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4912                 return -EINVAL;
4913         }
4914
4915         /* Set RTTBCNRC of each queue/pool for vf X  */
4916         for (; queue_idx <= queue_end; queue_idx++) {
4917                 if (0x1 & q_msk)
4918                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4919                 q_msk = q_msk >> 1;
4920         }
4921
4922         return 0;
4923 }
4924
4925 static void
4926 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4927                      __attribute__((unused)) uint32_t index,
4928                      __attribute__((unused)) uint32_t pool)
4929 {
4930         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4931         int diag;
4932
4933         /*
4934          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4935          * operation. Trap this case to avoid exhausting the [very limited]
4936          * set of PF resources used to store VF MAC addresses.
4937          */
4938         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4939                 return;
4940         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4941         if (diag == 0)
4942                 return;
4943         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4944 }
4945
4946 static void
4947 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4948 {
4949         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4950         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4951         struct ether_addr *mac_addr;
4952         uint32_t i;
4953         int diag;
4954
4955         /*
4956          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4957          * not support the deletion of a given MAC address.
4958          * Instead, it imposes to delete all MAC addresses, then to add again
4959          * all MAC addresses with the exception of the one to be deleted.
4960          */
4961         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4962
4963         /*
4964          * Add again all MAC addresses, with the exception of the deleted one
4965          * and of the permanent MAC address.
4966          */
4967         for (i = 0, mac_addr = dev->data->mac_addrs;
4968              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4969                 /* Skip the deleted MAC address */
4970                 if (i == index)
4971                         continue;
4972                 /* Skip NULL MAC addresses */
4973                 if (is_zero_ether_addr(mac_addr))
4974                         continue;
4975                 /* Skip the permanent MAC address */
4976                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4977                         continue;
4978                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4979                 if (diag != 0)
4980                         PMD_DRV_LOG(ERR,
4981                                     "Adding again MAC address "
4982                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4983                                     "diag=%d",
4984                                     mac_addr->addr_bytes[0],
4985                                     mac_addr->addr_bytes[1],
4986                                     mac_addr->addr_bytes[2],
4987                                     mac_addr->addr_bytes[3],
4988                                     mac_addr->addr_bytes[4],
4989                                     mac_addr->addr_bytes[5],
4990                                     diag);
4991         }
4992 }
4993
4994 static void
4995 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4996 {
4997         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4998
4999         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5000 }
5001
5002 #define MAC_TYPE_FILTER_SUP(type)    do {\
5003         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5004                 (type) != ixgbe_mac_X550)\
5005                 return -ENOTSUP;\
5006 } while (0)
5007
5008 static int
5009 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5010                         struct rte_eth_syn_filter *filter,
5011                         bool add)
5012 {
5013         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5014         uint32_t synqf;
5015
5016         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5017                 return -EINVAL;
5018
5019         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5020
5021         if (add) {
5022                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5023                         return -EINVAL;
5024                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5025                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5026
5027                 if (filter->hig_pri)
5028                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5029                 else
5030                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5031         } else {
5032                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5033                         return -ENOENT;
5034                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5035         }
5036         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5037         IXGBE_WRITE_FLUSH(hw);
5038         return 0;
5039 }
5040
5041 static int
5042 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5043                         struct rte_eth_syn_filter *filter)
5044 {
5045         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5046         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5047
5048         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5049                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5050                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5051                 return 0;
5052         }
5053         return -ENOENT;
5054 }
5055
5056 static int
5057 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5058                         enum rte_filter_op filter_op,
5059                         void *arg)
5060 {
5061         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5062         int ret;
5063
5064         MAC_TYPE_FILTER_SUP(hw->mac.type);
5065
5066         if (filter_op == RTE_ETH_FILTER_NOP)
5067                 return 0;
5068
5069         if (arg == NULL) {
5070                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5071                             filter_op);
5072                 return -EINVAL;
5073         }
5074
5075         switch (filter_op) {
5076         case RTE_ETH_FILTER_ADD:
5077                 ret = ixgbe_syn_filter_set(dev,
5078                                 (struct rte_eth_syn_filter *)arg,
5079                                 TRUE);
5080                 break;
5081         case RTE_ETH_FILTER_DELETE:
5082                 ret = ixgbe_syn_filter_set(dev,
5083                                 (struct rte_eth_syn_filter *)arg,
5084                                 FALSE);
5085                 break;
5086         case RTE_ETH_FILTER_GET:
5087                 ret = ixgbe_syn_filter_get(dev,
5088                                 (struct rte_eth_syn_filter *)arg);
5089                 break;
5090         default:
5091                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5092                 ret = -EINVAL;
5093                 break;
5094         }
5095
5096         return ret;
5097 }
5098
5099
5100 static inline enum ixgbe_5tuple_protocol
5101 convert_protocol_type(uint8_t protocol_value)
5102 {
5103         if (protocol_value == IPPROTO_TCP)
5104                 return IXGBE_FILTER_PROTOCOL_TCP;
5105         else if (protocol_value == IPPROTO_UDP)
5106                 return IXGBE_FILTER_PROTOCOL_UDP;
5107         else if (protocol_value == IPPROTO_SCTP)
5108                 return IXGBE_FILTER_PROTOCOL_SCTP;
5109         else
5110                 return IXGBE_FILTER_PROTOCOL_NONE;
5111 }
5112
5113 /*
5114  * add a 5tuple filter
5115  *
5116  * @param
5117  * dev: Pointer to struct rte_eth_dev.
5118  * index: the index the filter allocates.
5119  * filter: ponter to the filter that will be added.
5120  * rx_queue: the queue id the filter assigned to.
5121  *
5122  * @return
5123  *    - On success, zero.
5124  *    - On failure, a negative value.
5125  */
5126 static int
5127 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5128                         struct ixgbe_5tuple_filter *filter)
5129 {
5130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5131         struct ixgbe_filter_info *filter_info =
5132                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5133         int i, idx, shift;
5134         uint32_t ftqf, sdpqf;
5135         uint32_t l34timir = 0;
5136         uint8_t mask = 0xff;
5137
5138         /*
5139          * look for an unused 5tuple filter index,
5140          * and insert the filter to list.
5141          */
5142         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5143                 idx = i / (sizeof(uint32_t) * NBBY);
5144                 shift = i % (sizeof(uint32_t) * NBBY);
5145                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5146                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5147                         filter->index = i;
5148                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5149                                           filter,
5150                                           entries);
5151                         break;
5152                 }
5153         }
5154         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5155                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5156                 return -ENOSYS;
5157         }
5158
5159         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5160                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5161         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5162
5163         ftqf = (uint32_t)(filter->filter_info.proto &
5164                 IXGBE_FTQF_PROTOCOL_MASK);
5165         ftqf |= (uint32_t)((filter->filter_info.priority &
5166                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5167         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5168                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5169         if (filter->filter_info.dst_ip_mask == 0)
5170                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5171         if (filter->filter_info.src_port_mask == 0)
5172                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5173         if (filter->filter_info.dst_port_mask == 0)
5174                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5175         if (filter->filter_info.proto_mask == 0)
5176                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5177         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5178         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5179         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5180
5181         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5182         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5183         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5184         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5185
5186         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5187         l34timir |= (uint32_t)(filter->queue <<
5188                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5189         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5190         return 0;
5191 }
5192
5193 /*
5194  * remove a 5tuple filter
5195  *
5196  * @param
5197  * dev: Pointer to struct rte_eth_dev.
5198  * filter: the pointer of the filter will be removed.
5199  */
5200 static void
5201 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5202                         struct ixgbe_5tuple_filter *filter)
5203 {
5204         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5205         struct ixgbe_filter_info *filter_info =
5206                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5207         uint16_t index = filter->index;
5208
5209         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5210                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5211         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5212         rte_free(filter);
5213
5214         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5215         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5216         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5217         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5218         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5219 }
5220
5221 static int
5222 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5223 {
5224         struct ixgbe_hw *hw;
5225         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5226
5227         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5228
5229         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5230                 return -EINVAL;
5231
5232         /* refuse mtu that requires the support of scattered packets when this
5233          * feature has not been enabled before. */
5234         if (!dev->data->scattered_rx &&
5235             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5236              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5237                 return -EINVAL;
5238
5239         /*
5240          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5241          * request of the version 2.0 of the mailbox API.
5242          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5243          * of the mailbox API.
5244          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5245          * prior to 3.11.33 which contains the following change:
5246          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5247          */
5248         ixgbevf_rlpml_set_vf(hw, max_frame);
5249
5250         /* update max frame size */
5251         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5252         return 0;
5253 }
5254
5255 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5256         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5257                 return -ENOTSUP;\
5258 } while (0)
5259
5260 static inline struct ixgbe_5tuple_filter *
5261 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5262                         struct ixgbe_5tuple_filter_info *key)
5263 {
5264         struct ixgbe_5tuple_filter *it;
5265
5266         TAILQ_FOREACH(it, filter_list, entries) {
5267                 if (memcmp(key, &it->filter_info,
5268                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5269                         return it;
5270                 }
5271         }
5272         return NULL;
5273 }
5274
5275 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5276 static inline int
5277 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5278                         struct ixgbe_5tuple_filter_info *filter_info)
5279 {
5280         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5281                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5282                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5283                 return -EINVAL;
5284
5285         switch (filter->dst_ip_mask) {
5286         case UINT32_MAX:
5287                 filter_info->dst_ip_mask = 0;
5288                 filter_info->dst_ip = filter->dst_ip;
5289                 break;
5290         case 0:
5291                 filter_info->dst_ip_mask = 1;
5292                 break;
5293         default:
5294                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5295                 return -EINVAL;
5296         }
5297
5298         switch (filter->src_ip_mask) {
5299         case UINT32_MAX:
5300                 filter_info->src_ip_mask = 0;
5301                 filter_info->src_ip = filter->src_ip;
5302                 break;
5303         case 0:
5304                 filter_info->src_ip_mask = 1;
5305                 break;
5306         default:
5307                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5308                 return -EINVAL;
5309         }
5310
5311         switch (filter->dst_port_mask) {
5312         case UINT16_MAX:
5313                 filter_info->dst_port_mask = 0;
5314                 filter_info->dst_port = filter->dst_port;
5315                 break;
5316         case 0:
5317                 filter_info->dst_port_mask = 1;
5318                 break;
5319         default:
5320                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5321                 return -EINVAL;
5322         }
5323
5324         switch (filter->src_port_mask) {
5325         case UINT16_MAX:
5326                 filter_info->src_port_mask = 0;
5327                 filter_info->src_port = filter->src_port;
5328                 break;
5329         case 0:
5330                 filter_info->src_port_mask = 1;
5331                 break;
5332         default:
5333                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5334                 return -EINVAL;
5335         }
5336
5337         switch (filter->proto_mask) {
5338         case UINT8_MAX:
5339                 filter_info->proto_mask = 0;
5340                 filter_info->proto =
5341                         convert_protocol_type(filter->proto);
5342                 break;
5343         case 0:
5344                 filter_info->proto_mask = 1;
5345                 break;
5346         default:
5347                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5348                 return -EINVAL;
5349         }
5350
5351         filter_info->priority = (uint8_t)filter->priority;
5352         return 0;
5353 }
5354
5355 /*
5356  * add or delete a ntuple filter
5357  *
5358  * @param
5359  * dev: Pointer to struct rte_eth_dev.
5360  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5361  * add: if true, add filter, if false, remove filter
5362  *
5363  * @return
5364  *    - On success, zero.
5365  *    - On failure, a negative value.
5366  */
5367 static int
5368 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5369                         struct rte_eth_ntuple_filter *ntuple_filter,
5370                         bool add)
5371 {
5372         struct ixgbe_filter_info *filter_info =
5373                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5374         struct ixgbe_5tuple_filter_info filter_5tuple;
5375         struct ixgbe_5tuple_filter *filter;
5376         int ret;
5377
5378         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5379                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5380                 return -EINVAL;
5381         }
5382
5383         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5384         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5385         if (ret < 0)
5386                 return ret;
5387
5388         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5389                                          &filter_5tuple);
5390         if (filter != NULL && add) {
5391                 PMD_DRV_LOG(ERR, "filter exists.");
5392                 return -EEXIST;
5393         }
5394         if (filter == NULL && !add) {
5395                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5396                 return -ENOENT;
5397         }
5398
5399         if (add) {
5400                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5401                                 sizeof(struct ixgbe_5tuple_filter), 0);
5402                 if (filter == NULL)
5403                         return -ENOMEM;
5404                 (void)rte_memcpy(&filter->filter_info,
5405                                  &filter_5tuple,
5406                                  sizeof(struct ixgbe_5tuple_filter_info));
5407                 filter->queue = ntuple_filter->queue;
5408                 ret = ixgbe_add_5tuple_filter(dev, filter);
5409                 if (ret < 0) {
5410                         rte_free(filter);
5411                         return ret;
5412                 }
5413         } else
5414                 ixgbe_remove_5tuple_filter(dev, filter);
5415
5416         return 0;
5417 }
5418
5419 /*
5420  * get a ntuple filter
5421  *
5422  * @param
5423  * dev: Pointer to struct rte_eth_dev.
5424  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5425  *
5426  * @return
5427  *    - On success, zero.
5428  *    - On failure, a negative value.
5429  */
5430 static int
5431 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5432                         struct rte_eth_ntuple_filter *ntuple_filter)
5433 {
5434         struct ixgbe_filter_info *filter_info =
5435                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5436         struct ixgbe_5tuple_filter_info filter_5tuple;
5437         struct ixgbe_5tuple_filter *filter;
5438         int ret;
5439
5440         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5441                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5442                 return -EINVAL;
5443         }
5444
5445         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5446         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5447         if (ret < 0)
5448                 return ret;
5449
5450         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5451                                          &filter_5tuple);
5452         if (filter == NULL) {
5453                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5454                 return -ENOENT;
5455         }
5456         ntuple_filter->queue = filter->queue;
5457         return 0;
5458 }
5459
5460 /*
5461  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5462  * @dev: pointer to rte_eth_dev structure
5463  * @filter_op:operation will be taken.
5464  * @arg: a pointer to specific structure corresponding to the filter_op
5465  *
5466  * @return
5467  *    - On success, zero.
5468  *    - On failure, a negative value.
5469  */
5470 static int
5471 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5472                                 enum rte_filter_op filter_op,
5473                                 void *arg)
5474 {
5475         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5476         int ret;
5477
5478         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5479
5480         if (filter_op == RTE_ETH_FILTER_NOP)
5481                 return 0;
5482
5483         if (arg == NULL) {
5484                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5485                             filter_op);
5486                 return -EINVAL;
5487         }
5488
5489         switch (filter_op) {
5490         case RTE_ETH_FILTER_ADD:
5491                 ret = ixgbe_add_del_ntuple_filter(dev,
5492                         (struct rte_eth_ntuple_filter *)arg,
5493                         TRUE);
5494                 break;
5495         case RTE_ETH_FILTER_DELETE:
5496                 ret = ixgbe_add_del_ntuple_filter(dev,
5497                         (struct rte_eth_ntuple_filter *)arg,
5498                         FALSE);
5499                 break;
5500         case RTE_ETH_FILTER_GET:
5501                 ret = ixgbe_get_ntuple_filter(dev,
5502                         (struct rte_eth_ntuple_filter *)arg);
5503                 break;
5504         default:
5505                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5506                 ret = -EINVAL;
5507                 break;
5508         }
5509         return ret;
5510 }
5511
5512 static inline int
5513 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5514                         uint16_t ethertype)
5515 {
5516         int i;
5517
5518         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5519                 if (filter_info->ethertype_filters[i] == ethertype &&
5520                     (filter_info->ethertype_mask & (1 << i)))
5521                         return i;
5522         }
5523         return -1;
5524 }
5525
5526 static inline int
5527 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5528                         uint16_t ethertype)
5529 {
5530         int i;
5531
5532         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5533                 if (!(filter_info->ethertype_mask & (1 << i))) {
5534                         filter_info->ethertype_mask |= 1 << i;
5535                         filter_info->ethertype_filters[i] = ethertype;
5536                         return i;
5537                 }
5538         }
5539         return -1;
5540 }
5541
5542 static inline int
5543 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5544                         uint8_t idx)
5545 {
5546         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5547                 return -1;
5548         filter_info->ethertype_mask &= ~(1 << idx);
5549         filter_info->ethertype_filters[idx] = 0;
5550         return idx;
5551 }
5552
5553 static int
5554 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5555                         struct rte_eth_ethertype_filter *filter,
5556                         bool add)
5557 {
5558         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5559         struct ixgbe_filter_info *filter_info =
5560                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5561         uint32_t etqf = 0;
5562         uint32_t etqs = 0;
5563         int ret;
5564
5565         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5566                 return -EINVAL;
5567
5568         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5569                 filter->ether_type == ETHER_TYPE_IPv6) {
5570                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5571                         " ethertype filter.", filter->ether_type);
5572                 return -EINVAL;
5573         }
5574
5575         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5576                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5577                 return -EINVAL;
5578         }
5579         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5580                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5581                 return -EINVAL;
5582         }
5583
5584         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5585         if (ret >= 0 && add) {
5586                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5587                             filter->ether_type);
5588                 return -EEXIST;
5589         }
5590         if (ret < 0 && !add) {
5591                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5592                             filter->ether_type);
5593                 return -ENOENT;
5594         }
5595
5596         if (add) {
5597                 ret = ixgbe_ethertype_filter_insert(filter_info,
5598                         filter->ether_type);
5599                 if (ret < 0) {
5600                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5601                         return -ENOSYS;
5602                 }
5603                 etqf = IXGBE_ETQF_FILTER_EN;
5604                 etqf |= (uint32_t)filter->ether_type;
5605                 etqs |= (uint32_t)((filter->queue <<
5606                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5607                                     IXGBE_ETQS_RX_QUEUE);
5608                 etqs |= IXGBE_ETQS_QUEUE_EN;
5609         } else {
5610                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5611                 if (ret < 0)
5612                         return -ENOSYS;
5613         }
5614         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5615         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5616         IXGBE_WRITE_FLUSH(hw);
5617
5618         return 0;
5619 }
5620
5621 static int
5622 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5623                         struct rte_eth_ethertype_filter *filter)
5624 {
5625         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5626         struct ixgbe_filter_info *filter_info =
5627                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5628         uint32_t etqf, etqs;
5629         int ret;
5630
5631         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5632         if (ret < 0) {
5633                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5634                             filter->ether_type);
5635                 return -ENOENT;
5636         }
5637
5638         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5639         if (etqf & IXGBE_ETQF_FILTER_EN) {
5640                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5641                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5642                 filter->flags = 0;
5643                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5644                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5645                 return 0;
5646         }
5647         return -ENOENT;
5648 }
5649
5650 /*
5651  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5652  * @dev: pointer to rte_eth_dev structure
5653  * @filter_op:operation will be taken.
5654  * @arg: a pointer to specific structure corresponding to the filter_op
5655  */
5656 static int
5657 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5658                                 enum rte_filter_op filter_op,
5659                                 void *arg)
5660 {
5661         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5662         int ret;
5663
5664         MAC_TYPE_FILTER_SUP(hw->mac.type);
5665
5666         if (filter_op == RTE_ETH_FILTER_NOP)
5667                 return 0;
5668
5669         if (arg == NULL) {
5670                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5671                             filter_op);
5672                 return -EINVAL;
5673         }
5674
5675         switch (filter_op) {
5676         case RTE_ETH_FILTER_ADD:
5677                 ret = ixgbe_add_del_ethertype_filter(dev,
5678                         (struct rte_eth_ethertype_filter *)arg,
5679                         TRUE);
5680                 break;
5681         case RTE_ETH_FILTER_DELETE:
5682                 ret = ixgbe_add_del_ethertype_filter(dev,
5683                         (struct rte_eth_ethertype_filter *)arg,
5684                         FALSE);
5685                 break;
5686         case RTE_ETH_FILTER_GET:
5687                 ret = ixgbe_get_ethertype_filter(dev,
5688                         (struct rte_eth_ethertype_filter *)arg);
5689                 break;
5690         default:
5691                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5692                 ret = -EINVAL;
5693                 break;
5694         }
5695         return ret;
5696 }
5697
5698 static int
5699 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5700                      enum rte_filter_type filter_type,
5701                      enum rte_filter_op filter_op,
5702                      void *arg)
5703 {
5704         int ret = -EINVAL;
5705
5706         switch (filter_type) {
5707         case RTE_ETH_FILTER_NTUPLE:
5708                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5709                 break;
5710         case RTE_ETH_FILTER_ETHERTYPE:
5711                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5712                 break;
5713         case RTE_ETH_FILTER_SYN:
5714                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5715                 break;
5716         case RTE_ETH_FILTER_FDIR:
5717                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5718                 break;
5719         case RTE_ETH_FILTER_L2_TUNNEL:
5720                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5721                 break;
5722         default:
5723                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5724                                                         filter_type);
5725                 break;
5726         }
5727
5728         return ret;
5729 }
5730
5731 static u8 *
5732 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5733                         u8 **mc_addr_ptr, u32 *vmdq)
5734 {
5735         u8 *mc_addr;
5736
5737         *vmdq = 0;
5738         mc_addr = *mc_addr_ptr;
5739         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5740         return mc_addr;
5741 }
5742
5743 static int
5744 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5745                           struct ether_addr *mc_addr_set,
5746                           uint32_t nb_mc_addr)
5747 {
5748         struct ixgbe_hw *hw;
5749         u8 *mc_addr_list;
5750
5751         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5752         mc_addr_list = (u8 *)mc_addr_set;
5753         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5754                                          ixgbe_dev_addr_list_itr, TRUE);
5755 }
5756
5757 static uint64_t
5758 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5759 {
5760         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5761         uint64_t systime_cycles;
5762
5763         switch (hw->mac.type) {
5764         case ixgbe_mac_X550:
5765                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5766                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5767                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5768                                 * NSEC_PER_SEC;
5769                 break;
5770         default:
5771                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5772                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5773                                 << 32;
5774         }
5775
5776         return systime_cycles;
5777 }
5778
5779 static uint64_t
5780 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5781 {
5782         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5783         uint64_t rx_tstamp_cycles;
5784
5785         switch (hw->mac.type) {
5786         case ixgbe_mac_X550:
5787                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5788                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5789                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5790                                 * NSEC_PER_SEC;
5791                 break;
5792         default:
5793                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5794                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5795                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5796                                 << 32;
5797         }
5798
5799         return rx_tstamp_cycles;
5800 }
5801
5802 static uint64_t
5803 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5804 {
5805         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5806         uint64_t tx_tstamp_cycles;
5807
5808         switch (hw->mac.type) {
5809         case ixgbe_mac_X550:
5810                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5811                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5812                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5813                                 * NSEC_PER_SEC;
5814                 break;
5815         default:
5816                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5817                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5818                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5819                                 << 32;
5820         }
5821
5822         return tx_tstamp_cycles;
5823 }
5824
5825 static void
5826 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5827 {
5828         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5829         struct ixgbe_adapter *adapter =
5830                 (struct ixgbe_adapter *)dev->data->dev_private;
5831         struct rte_eth_link link;
5832         uint32_t incval = 0;
5833         uint32_t shift = 0;
5834
5835         /* Get current link speed. */
5836         memset(&link, 0, sizeof(link));
5837         ixgbe_dev_link_update(dev, 1);
5838         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5839
5840         switch (link.link_speed) {
5841         case ETH_LINK_SPEED_100:
5842                 incval = IXGBE_INCVAL_100;
5843                 shift = IXGBE_INCVAL_SHIFT_100;
5844                 break;
5845         case ETH_LINK_SPEED_1000:
5846                 incval = IXGBE_INCVAL_1GB;
5847                 shift = IXGBE_INCVAL_SHIFT_1GB;
5848                 break;
5849         case ETH_LINK_SPEED_10000:
5850         default:
5851                 incval = IXGBE_INCVAL_10GB;
5852                 shift = IXGBE_INCVAL_SHIFT_10GB;
5853                 break;
5854         }
5855
5856         switch (hw->mac.type) {
5857         case ixgbe_mac_X550:
5858                 /* Independent of link speed. */
5859                 incval = 1;
5860                 /* Cycles read will be interpreted as ns. */
5861                 shift = 0;
5862                 /* Fall-through */
5863         case ixgbe_mac_X540:
5864                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5865                 break;
5866         case ixgbe_mac_82599EB:
5867                 incval >>= IXGBE_INCVAL_SHIFT_82599;
5868                 shift -= IXGBE_INCVAL_SHIFT_82599;
5869                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5870                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5871                 break;
5872         default:
5873                 /* Not supported. */
5874                 return;
5875         }
5876
5877         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5878         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5879         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5880
5881         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5882         adapter->systime_tc.cc_shift = shift;
5883         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5884
5885         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5886         adapter->rx_tstamp_tc.cc_shift = shift;
5887         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5888
5889         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5890         adapter->tx_tstamp_tc.cc_shift = shift;
5891         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5892 }
5893
5894 static int
5895 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5896 {
5897         struct ixgbe_adapter *adapter =
5898                         (struct ixgbe_adapter *)dev->data->dev_private;
5899
5900         adapter->systime_tc.nsec += delta;
5901         adapter->rx_tstamp_tc.nsec += delta;
5902         adapter->tx_tstamp_tc.nsec += delta;
5903
5904         return 0;
5905 }
5906
5907 static int
5908 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5909 {
5910         uint64_t ns;
5911         struct ixgbe_adapter *adapter =
5912                         (struct ixgbe_adapter *)dev->data->dev_private;
5913
5914         ns = rte_timespec_to_ns(ts);
5915         /* Set the timecounters to a new value. */
5916         adapter->systime_tc.nsec = ns;
5917         adapter->rx_tstamp_tc.nsec = ns;
5918         adapter->tx_tstamp_tc.nsec = ns;
5919
5920         return 0;
5921 }
5922
5923 static int
5924 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5925 {
5926         uint64_t ns, systime_cycles;
5927         struct ixgbe_adapter *adapter =
5928                         (struct ixgbe_adapter *)dev->data->dev_private;
5929
5930         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
5931         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5932         *ts = rte_ns_to_timespec(ns);
5933
5934         return 0;
5935 }
5936
5937 static int
5938 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5939 {
5940         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5941         uint32_t tsync_ctl;
5942         uint32_t tsauxc;
5943
5944         /* Stop the timesync system time. */
5945         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
5946         /* Reset the timesync system time value. */
5947         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
5948         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
5949
5950         /* Enable system time for platforms where it isn't on by default. */
5951         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5952         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5953         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5954
5955         ixgbe_start_timecounters(dev);
5956
5957         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5958         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5959                         (ETHER_TYPE_1588 |
5960                          IXGBE_ETQF_FILTER_EN |
5961                          IXGBE_ETQF_1588));
5962
5963         /* Enable timestamping of received PTP packets. */
5964         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5965         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5966         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5967
5968         /* Enable timestamping of transmitted PTP packets. */
5969         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5970         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5971         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5972
5973         IXGBE_WRITE_FLUSH(hw);
5974
5975         return 0;
5976 }
5977
5978 static int
5979 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5980 {
5981         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5982         uint32_t tsync_ctl;
5983
5984         /* Disable timestamping of transmitted PTP packets. */
5985         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5986         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5987         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5988
5989         /* Disable timestamping of received PTP packets. */
5990         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5991         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5992         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5993
5994         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5995         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5996
5997         /* Stop incrementating the System Time registers. */
5998         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5999
6000         return 0;
6001 }
6002
6003 static int
6004 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6005                                  struct timespec *timestamp,
6006                                  uint32_t flags __rte_unused)
6007 {
6008         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6009         struct ixgbe_adapter *adapter =
6010                 (struct ixgbe_adapter *)dev->data->dev_private;
6011         uint32_t tsync_rxctl;
6012         uint64_t rx_tstamp_cycles;
6013         uint64_t ns;
6014
6015         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6016         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6017                 return -EINVAL;
6018
6019         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6020         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6021         *timestamp = rte_ns_to_timespec(ns);
6022
6023         return  0;
6024 }
6025
6026 static int
6027 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6028                                  struct timespec *timestamp)
6029 {
6030         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6031         struct ixgbe_adapter *adapter =
6032                 (struct ixgbe_adapter *)dev->data->dev_private;
6033         uint32_t tsync_txctl;
6034         uint64_t tx_tstamp_cycles;
6035         uint64_t ns;
6036
6037         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6038         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6039                 return -EINVAL;
6040
6041         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6042         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6043         *timestamp = rte_ns_to_timespec(ns);
6044
6045         return 0;
6046 }
6047
6048 static int
6049 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6050 {
6051         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6052         int count = 0;
6053         int g_ind = 0;
6054         const struct reg_info *reg_group;
6055         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6056                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6057
6058         while ((reg_group = reg_set[g_ind++]))
6059                 count += ixgbe_regs_group_count(reg_group);
6060
6061         return count;
6062 }
6063
6064 static int
6065 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6066 {
6067         int count = 0;
6068         int g_ind = 0;
6069         const struct reg_info *reg_group;
6070
6071         while ((reg_group = ixgbevf_regs[g_ind++]))
6072                 count += ixgbe_regs_group_count(reg_group);
6073
6074         return count;
6075 }
6076
6077 static int
6078 ixgbe_get_regs(struct rte_eth_dev *dev,
6079               struct rte_dev_reg_info *regs)
6080 {
6081         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6082         uint32_t *data = regs->data;
6083         int g_ind = 0;
6084         int count = 0;
6085         const struct reg_info *reg_group;
6086         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6087                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6088
6089         /* Support only full register dump */
6090         if ((regs->length == 0) ||
6091             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6092                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6093                         hw->device_id;
6094                 while ((reg_group = reg_set[g_ind++]))
6095                         count += ixgbe_read_regs_group(dev, &data[count],
6096                                 reg_group);
6097                 return 0;
6098         }
6099
6100         return -ENOTSUP;
6101 }
6102
6103 static int
6104 ixgbevf_get_regs(struct rte_eth_dev *dev,
6105                 struct rte_dev_reg_info *regs)
6106 {
6107         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6108         uint32_t *data = regs->data;
6109         int g_ind = 0;
6110         int count = 0;
6111         const struct reg_info *reg_group;
6112
6113         /* Support only full register dump */
6114         if ((regs->length == 0) ||
6115             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6116                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6117                         hw->device_id;
6118                 while ((reg_group = ixgbevf_regs[g_ind++]))
6119                         count += ixgbe_read_regs_group(dev, &data[count],
6120                                                       reg_group);
6121                 return 0;
6122         }
6123
6124         return -ENOTSUP;
6125 }
6126
6127 static int
6128 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6129 {
6130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6131
6132         /* Return unit is byte count */
6133         return hw->eeprom.word_size * 2;
6134 }
6135
6136 static int
6137 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6138                 struct rte_dev_eeprom_info *in_eeprom)
6139 {
6140         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6141         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6142         uint16_t *data = in_eeprom->data;
6143         int first, length;
6144
6145         first = in_eeprom->offset >> 1;
6146         length = in_eeprom->length >> 1;
6147         if ((first > hw->eeprom.word_size) ||
6148             ((first + length) > hw->eeprom.word_size))
6149                 return -EINVAL;
6150
6151         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6152
6153         return eeprom->ops.read_buffer(hw, first, length, data);
6154 }
6155
6156 static int
6157 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6158                 struct rte_dev_eeprom_info *in_eeprom)
6159 {
6160         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6161         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6162         uint16_t *data = in_eeprom->data;
6163         int first, length;
6164
6165         first = in_eeprom->offset >> 1;
6166         length = in_eeprom->length >> 1;
6167         if ((first > hw->eeprom.word_size) ||
6168             ((first + length) > hw->eeprom.word_size))
6169                 return -EINVAL;
6170
6171         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6172
6173         return eeprom->ops.write_buffer(hw,  first, length, data);
6174 }
6175
6176 uint16_t
6177 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6178         switch (mac_type) {
6179         case ixgbe_mac_X550:
6180         case ixgbe_mac_X550EM_x:
6181         case ixgbe_mac_X550EM_a:
6182                 return ETH_RSS_RETA_SIZE_512;
6183         case ixgbe_mac_X550_vf:
6184         case ixgbe_mac_X550EM_x_vf:
6185         case ixgbe_mac_X550EM_a_vf:
6186                 return ETH_RSS_RETA_SIZE_64;
6187         default:
6188                 return ETH_RSS_RETA_SIZE_128;
6189         }
6190 }
6191
6192 uint32_t
6193 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6194         switch (mac_type) {
6195         case ixgbe_mac_X550:
6196         case ixgbe_mac_X550EM_x:
6197         case ixgbe_mac_X550EM_a:
6198                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6199                         return IXGBE_RETA(reta_idx >> 2);
6200                 else
6201                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6202         case ixgbe_mac_X550_vf:
6203         case ixgbe_mac_X550EM_x_vf:
6204         case ixgbe_mac_X550EM_a_vf:
6205                 return IXGBE_VFRETA(reta_idx >> 2);
6206         default:
6207                 return IXGBE_RETA(reta_idx >> 2);
6208         }
6209 }
6210
6211 uint32_t
6212 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6213         switch (mac_type) {
6214         case ixgbe_mac_X550_vf:
6215         case ixgbe_mac_X550EM_x_vf:
6216         case ixgbe_mac_X550EM_a_vf:
6217                 return IXGBE_VFMRQC;
6218         default:
6219                 return IXGBE_MRQC;
6220         }
6221 }
6222
6223 uint32_t
6224 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6225         switch (mac_type) {
6226         case ixgbe_mac_X550_vf:
6227         case ixgbe_mac_X550EM_x_vf:
6228         case ixgbe_mac_X550EM_a_vf:
6229                 return IXGBE_VFRSSRK(i);
6230         default:
6231                 return IXGBE_RSSRK(i);
6232         }
6233 }
6234
6235 bool
6236 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6237         switch (mac_type) {
6238         case ixgbe_mac_82599_vf:
6239         case ixgbe_mac_X540_vf:
6240                 return 0;
6241         default:
6242                 return 1;
6243         }
6244 }
6245
6246 static int
6247 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6248                         struct rte_eth_dcb_info *dcb_info)
6249 {
6250         struct ixgbe_dcb_config *dcb_config =
6251                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6252         struct ixgbe_dcb_tc_config *tc;
6253         uint8_t i, j;
6254
6255         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6256                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6257         else
6258                 dcb_info->nb_tcs = 1;
6259
6260         if (dcb_config->vt_mode) { /* vt is enabled*/
6261                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6262                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6263                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6264                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6265                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6266                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6267                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6268                                                 i * dcb_info->nb_tcs + j;
6269                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6270                                 dcb_info->tc_queue.tc_txq[i][j].base =
6271                                                 i * dcb_info->nb_tcs + j;
6272                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6273                         }
6274                 }
6275         } else { /* vt is disabled*/
6276                 struct rte_eth_dcb_rx_conf *rx_conf =
6277                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6278                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6279                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6280                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6281                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6282                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6283                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6284                         }
6285                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6286                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6287                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6288                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6289                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6290                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6291                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6292                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6293                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6294                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6295                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6296                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6297                         }
6298                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6299                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6300                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6301                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6302                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6303                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6304                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6305                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6306                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6307                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6308                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6309                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6310                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6311                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6312                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6313                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6314                 }
6315         }
6316         for (i = 0; i < dcb_info->nb_tcs; i++) {
6317                 tc = &dcb_config->tc_config[i];
6318                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6319         }
6320         return 0;
6321 }
6322
6323 /* Update e-tag ether type */
6324 static int
6325 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6326                             uint16_t ether_type)
6327 {
6328         uint32_t etag_etype;
6329
6330         if (hw->mac.type != ixgbe_mac_X550 &&
6331             hw->mac.type != ixgbe_mac_X550EM_x) {
6332                 return -ENOTSUP;
6333         }
6334
6335         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6336         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6337         etag_etype |= ether_type;
6338         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6339         IXGBE_WRITE_FLUSH(hw);
6340
6341         return 0;
6342 }
6343
6344 /* Config l2 tunnel ether type */
6345 static int
6346 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6347                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6348 {
6349         int ret = 0;
6350         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6351
6352         if (l2_tunnel == NULL)
6353                 return -EINVAL;
6354
6355         switch (l2_tunnel->l2_tunnel_type) {
6356         case RTE_L2_TUNNEL_TYPE_E_TAG:
6357                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6358                 break;
6359         default:
6360                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6361                 ret = -EINVAL;
6362                 break;
6363         }
6364
6365         return ret;
6366 }
6367
6368 /* Enable e-tag tunnel */
6369 static int
6370 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6371 {
6372         uint32_t etag_etype;
6373
6374         if (hw->mac.type != ixgbe_mac_X550 &&
6375             hw->mac.type != ixgbe_mac_X550EM_x) {
6376                 return -ENOTSUP;
6377         }
6378
6379         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6380         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6381         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6382         IXGBE_WRITE_FLUSH(hw);
6383
6384         return 0;
6385 }
6386
6387 /* Enable l2 tunnel */
6388 static int
6389 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6390                            enum rte_eth_tunnel_type l2_tunnel_type)
6391 {
6392         int ret = 0;
6393         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6394
6395         switch (l2_tunnel_type) {
6396         case RTE_L2_TUNNEL_TYPE_E_TAG:
6397                 ret = ixgbe_e_tag_enable(hw);
6398                 break;
6399         default:
6400                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6401                 ret = -EINVAL;
6402                 break;
6403         }
6404
6405         return ret;
6406 }
6407
6408 /* Disable e-tag tunnel */
6409 static int
6410 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6411 {
6412         uint32_t etag_etype;
6413
6414         if (hw->mac.type != ixgbe_mac_X550 &&
6415             hw->mac.type != ixgbe_mac_X550EM_x) {
6416                 return -ENOTSUP;
6417         }
6418
6419         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6420         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6421         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6422         IXGBE_WRITE_FLUSH(hw);
6423
6424         return 0;
6425 }
6426
6427 /* Disable l2 tunnel */
6428 static int
6429 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6430                             enum rte_eth_tunnel_type l2_tunnel_type)
6431 {
6432         int ret = 0;
6433         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6434
6435         switch (l2_tunnel_type) {
6436         case RTE_L2_TUNNEL_TYPE_E_TAG:
6437                 ret = ixgbe_e_tag_disable(hw);
6438                 break;
6439         default:
6440                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6441                 ret = -EINVAL;
6442                 break;
6443         }
6444
6445         return ret;
6446 }
6447
6448 static int
6449 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6450                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6451 {
6452         int ret = 0;
6453         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6454         uint32_t i, rar_entries;
6455         uint32_t rar_low, rar_high;
6456
6457         if (hw->mac.type != ixgbe_mac_X550 &&
6458             hw->mac.type != ixgbe_mac_X550EM_x) {
6459                 return -ENOTSUP;
6460         }
6461
6462         rar_entries = ixgbe_get_num_rx_addrs(hw);
6463
6464         for (i = 1; i < rar_entries; i++) {
6465                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6466                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6467                 if ((rar_high & IXGBE_RAH_AV) &&
6468                     (rar_high & IXGBE_RAH_ADTYPE) &&
6469                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6470                      l2_tunnel->tunnel_id)) {
6471                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6472                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6473
6474                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6475
6476                         return ret;
6477                 }
6478         }
6479
6480         return ret;
6481 }
6482
6483 static int
6484 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6485                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6486 {
6487         int ret = 0;
6488         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6489         uint32_t i, rar_entries;
6490         uint32_t rar_low, rar_high;
6491
6492         if (hw->mac.type != ixgbe_mac_X550 &&
6493             hw->mac.type != ixgbe_mac_X550EM_x) {
6494                 return -ENOTSUP;
6495         }
6496
6497         /* One entry for one tunnel. Try to remove potential existing entry. */
6498         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6499
6500         rar_entries = ixgbe_get_num_rx_addrs(hw);
6501
6502         for (i = 1; i < rar_entries; i++) {
6503                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6504                 if (rar_high & IXGBE_RAH_AV) {
6505                         continue;
6506                 } else {
6507                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6508                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6509                         rar_low = l2_tunnel->tunnel_id;
6510
6511                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6512                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6513
6514                         return ret;
6515                 }
6516         }
6517
6518         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6519                      " Please remove a rule before adding a new one.");
6520         return -EINVAL;
6521 }
6522
6523 /* Add l2 tunnel filter */
6524 static int
6525 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6526                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6527 {
6528         int ret = 0;
6529
6530         switch (l2_tunnel->l2_tunnel_type) {
6531         case RTE_L2_TUNNEL_TYPE_E_TAG:
6532                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6533                 break;
6534         default:
6535                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6536                 ret = -EINVAL;
6537                 break;
6538         }
6539
6540         return ret;
6541 }
6542
6543 /* Delete l2 tunnel filter */
6544 static int
6545 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6546                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6547 {
6548         int ret = 0;
6549
6550         switch (l2_tunnel->l2_tunnel_type) {
6551         case RTE_L2_TUNNEL_TYPE_E_TAG:
6552                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6553                 break;
6554         default:
6555                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6556                 ret = -EINVAL;
6557                 break;
6558         }
6559
6560         return ret;
6561 }
6562
6563 /**
6564  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6565  * @dev: pointer to rte_eth_dev structure
6566  * @filter_op:operation will be taken.
6567  * @arg: a pointer to specific structure corresponding to the filter_op
6568  */
6569 static int
6570 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6571                                   enum rte_filter_op filter_op,
6572                                   void *arg)
6573 {
6574         int ret = 0;
6575
6576         if (filter_op == RTE_ETH_FILTER_NOP)
6577                 return 0;
6578
6579         if (arg == NULL) {
6580                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6581                             filter_op);
6582                 return -EINVAL;
6583         }
6584
6585         switch (filter_op) {
6586         case RTE_ETH_FILTER_ADD:
6587                 ret = ixgbe_dev_l2_tunnel_filter_add
6588                         (dev,
6589                          (struct rte_eth_l2_tunnel_conf *)arg);
6590                 break;
6591         case RTE_ETH_FILTER_DELETE:
6592                 ret = ixgbe_dev_l2_tunnel_filter_del
6593                         (dev,
6594                          (struct rte_eth_l2_tunnel_conf *)arg);
6595                 break;
6596         default:
6597                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6598                 ret = -EINVAL;
6599                 break;
6600         }
6601         return ret;
6602 }
6603
6604 static int
6605 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6606 {
6607         int ret = 0;
6608         uint32_t ctrl;
6609         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6610
6611         if (hw->mac.type != ixgbe_mac_X550 &&
6612             hw->mac.type != ixgbe_mac_X550EM_x) {
6613                 return -ENOTSUP;
6614         }
6615
6616         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6617         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6618         if (en)
6619                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6620         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6621
6622         return ret;
6623 }
6624
6625 /* Enable l2 tunnel forwarding */
6626 static int
6627 ixgbe_dev_l2_tunnel_forwarding_enable
6628         (struct rte_eth_dev *dev,
6629          enum rte_eth_tunnel_type l2_tunnel_type)
6630 {
6631         int ret = 0;
6632
6633         switch (l2_tunnel_type) {
6634         case RTE_L2_TUNNEL_TYPE_E_TAG:
6635                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6636                 break;
6637         default:
6638                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6639                 ret = -EINVAL;
6640                 break;
6641         }
6642
6643         return ret;
6644 }
6645
6646 /* Disable l2 tunnel forwarding */
6647 static int
6648 ixgbe_dev_l2_tunnel_forwarding_disable
6649         (struct rte_eth_dev *dev,
6650          enum rte_eth_tunnel_type l2_tunnel_type)
6651 {
6652         int ret = 0;
6653
6654         switch (l2_tunnel_type) {
6655         case RTE_L2_TUNNEL_TYPE_E_TAG:
6656                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6657                 break;
6658         default:
6659                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6660                 ret = -EINVAL;
6661                 break;
6662         }
6663
6664         return ret;
6665 }
6666
6667 static int
6668 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6669                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6670                              bool en)
6671 {
6672         int ret = 0;
6673         uint32_t vmtir, vmvir;
6674         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6675
6676         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6677                 PMD_DRV_LOG(ERR,
6678                             "VF id %u should be less than %u",
6679                             l2_tunnel->vf_id,
6680                             dev->pci_dev->max_vfs);
6681                 return -EINVAL;
6682         }
6683
6684         if (hw->mac.type != ixgbe_mac_X550 &&
6685             hw->mac.type != ixgbe_mac_X550EM_x) {
6686                 return -ENOTSUP;
6687         }
6688
6689         if (en)
6690                 vmtir = l2_tunnel->tunnel_id;
6691         else
6692                 vmtir = 0;
6693
6694         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6695
6696         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6697         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6698         if (en)
6699                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6700         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6701
6702         return ret;
6703 }
6704
6705 /* Enable l2 tunnel tag insertion */
6706 static int
6707 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6708                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6709 {
6710         int ret = 0;
6711
6712         switch (l2_tunnel->l2_tunnel_type) {
6713         case RTE_L2_TUNNEL_TYPE_E_TAG:
6714                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6715                 break;
6716         default:
6717                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6718                 ret = -EINVAL;
6719                 break;
6720         }
6721
6722         return ret;
6723 }
6724
6725 /* Disable l2 tunnel tag insertion */
6726 static int
6727 ixgbe_dev_l2_tunnel_insertion_disable
6728         (struct rte_eth_dev *dev,
6729          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6730 {
6731         int ret = 0;
6732
6733         switch (l2_tunnel->l2_tunnel_type) {
6734         case RTE_L2_TUNNEL_TYPE_E_TAG:
6735                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6736                 break;
6737         default:
6738                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6739                 ret = -EINVAL;
6740                 break;
6741         }
6742
6743         return ret;
6744 }
6745
6746 static int
6747 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6748                              bool en)
6749 {
6750         int ret = 0;
6751         uint32_t qde;
6752         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6753
6754         if (hw->mac.type != ixgbe_mac_X550 &&
6755             hw->mac.type != ixgbe_mac_X550EM_x) {
6756                 return -ENOTSUP;
6757         }
6758
6759         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6760         if (en)
6761                 qde |= IXGBE_QDE_STRIP_TAG;
6762         else
6763                 qde &= ~IXGBE_QDE_STRIP_TAG;
6764         qde &= ~IXGBE_QDE_READ;
6765         qde |= IXGBE_QDE_WRITE;
6766         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6767
6768         return ret;
6769 }
6770
6771 /* Enable l2 tunnel tag stripping */
6772 static int
6773 ixgbe_dev_l2_tunnel_stripping_enable
6774         (struct rte_eth_dev *dev,
6775          enum rte_eth_tunnel_type l2_tunnel_type)
6776 {
6777         int ret = 0;
6778
6779         switch (l2_tunnel_type) {
6780         case RTE_L2_TUNNEL_TYPE_E_TAG:
6781                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6782                 break;
6783         default:
6784                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6785                 ret = -EINVAL;
6786                 break;
6787         }
6788
6789         return ret;
6790 }
6791
6792 /* Disable l2 tunnel tag stripping */
6793 static int
6794 ixgbe_dev_l2_tunnel_stripping_disable
6795         (struct rte_eth_dev *dev,
6796          enum rte_eth_tunnel_type l2_tunnel_type)
6797 {
6798         int ret = 0;
6799
6800         switch (l2_tunnel_type) {
6801         case RTE_L2_TUNNEL_TYPE_E_TAG:
6802                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6803                 break;
6804         default:
6805                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6806                 ret = -EINVAL;
6807                 break;
6808         }
6809
6810         return ret;
6811 }
6812
6813 /* Enable/disable l2 tunnel offload functions */
6814 static int
6815 ixgbe_dev_l2_tunnel_offload_set
6816         (struct rte_eth_dev *dev,
6817          struct rte_eth_l2_tunnel_conf *l2_tunnel,
6818          uint32_t mask,
6819          uint8_t en)
6820 {
6821         int ret = 0;
6822
6823         if (l2_tunnel == NULL)
6824                 return -EINVAL;
6825
6826         ret = -EINVAL;
6827         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6828                 if (en)
6829                         ret = ixgbe_dev_l2_tunnel_enable(
6830                                 dev,
6831                                 l2_tunnel->l2_tunnel_type);
6832                 else
6833                         ret = ixgbe_dev_l2_tunnel_disable(
6834                                 dev,
6835                                 l2_tunnel->l2_tunnel_type);
6836         }
6837
6838         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6839                 if (en)
6840                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
6841                                 dev,
6842                                 l2_tunnel);
6843                 else
6844                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
6845                                 dev,
6846                                 l2_tunnel);
6847         }
6848
6849         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6850                 if (en)
6851                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
6852                                 dev,
6853                                 l2_tunnel->l2_tunnel_type);
6854                 else
6855                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
6856                                 dev,
6857                                 l2_tunnel->l2_tunnel_type);
6858         }
6859
6860         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6861                 if (en)
6862                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6863                                 dev,
6864                                 l2_tunnel->l2_tunnel_type);
6865                 else
6866                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6867                                 dev,
6868                                 l2_tunnel->l2_tunnel_type);
6869         }
6870
6871         return ret;
6872 }
6873
6874 static int
6875 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6876                         uint16_t port)
6877 {
6878         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6879         IXGBE_WRITE_FLUSH(hw);
6880
6881         return 0;
6882 }
6883
6884 /* There's only one register for VxLAN UDP port.
6885  * So, we cannot add several ports. Will update it.
6886  */
6887 static int
6888 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
6889                      uint16_t port)
6890 {
6891         if (port == 0) {
6892                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
6893                 return -EINVAL;
6894         }
6895
6896         return ixgbe_update_vxlan_port(hw, port);
6897 }
6898
6899 /* We cannot delete the VxLAN port. For there's a register for VxLAN
6900  * UDP port, it must have a value.
6901  * So, will reset it to the original value 0.
6902  */
6903 static int
6904 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
6905                      uint16_t port)
6906 {
6907         uint16_t cur_port;
6908
6909         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
6910
6911         if (cur_port != port) {
6912                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
6913                 return -EINVAL;
6914         }
6915
6916         return ixgbe_update_vxlan_port(hw, 0);
6917 }
6918
6919 /* Add UDP tunneling port */
6920 static int
6921 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6922                               struct rte_eth_udp_tunnel *udp_tunnel)
6923 {
6924         int ret = 0;
6925         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6926
6927         if (hw->mac.type != ixgbe_mac_X550 &&
6928             hw->mac.type != ixgbe_mac_X550EM_x) {
6929                 return -ENOTSUP;
6930         }
6931
6932         if (udp_tunnel == NULL)
6933                 return -EINVAL;
6934
6935         switch (udp_tunnel->prot_type) {
6936         case RTE_TUNNEL_TYPE_VXLAN:
6937                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
6938                 break;
6939
6940         case RTE_TUNNEL_TYPE_GENEVE:
6941         case RTE_TUNNEL_TYPE_TEREDO:
6942                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6943                 ret = -EINVAL;
6944                 break;
6945
6946         default:
6947                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6948                 ret = -EINVAL;
6949                 break;
6950         }
6951
6952         return ret;
6953 }
6954
6955 /* Remove UDP tunneling port */
6956 static int
6957 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6958                               struct rte_eth_udp_tunnel *udp_tunnel)
6959 {
6960         int ret = 0;
6961         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6962
6963         if (hw->mac.type != ixgbe_mac_X550 &&
6964             hw->mac.type != ixgbe_mac_X550EM_x) {
6965                 return -ENOTSUP;
6966         }
6967
6968         if (udp_tunnel == NULL)
6969                 return -EINVAL;
6970
6971         switch (udp_tunnel->prot_type) {
6972         case RTE_TUNNEL_TYPE_VXLAN:
6973                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
6974                 break;
6975         case RTE_TUNNEL_TYPE_GENEVE:
6976         case RTE_TUNNEL_TYPE_TEREDO:
6977                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6978                 ret = -EINVAL;
6979                 break;
6980         default:
6981                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6982                 ret = -EINVAL;
6983                 break;
6984         }
6985
6986         return ret;
6987 }
6988
6989 /* ixgbevf_update_xcast_mode - Update Multicast mode
6990  * @hw: pointer to the HW structure
6991  * @netdev: pointer to net device structure
6992  * @xcast_mode: new multicast mode
6993  *
6994  * Updates the Multicast Mode of VF.
6995  */
6996 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
6997                                      int xcast_mode)
6998 {
6999         struct ixgbe_mbx_info *mbx = &hw->mbx;
7000         u32 msgbuf[2];
7001         s32 err;
7002
7003         switch (hw->api_version) {
7004         case ixgbe_mbox_api_12:
7005                 break;
7006         default:
7007                 return -EOPNOTSUPP;
7008         }
7009
7010         msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7011         msgbuf[1] = xcast_mode;
7012
7013         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7014         if (err)
7015                 return err;
7016
7017         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7018         if (err)
7019                 return err;
7020
7021         msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7022         if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7023                 return -EPERM;
7024
7025         return 0;
7026 }
7027
7028 static void
7029 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7030 {
7031         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7032
7033         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7034 }
7035
7036 static void
7037 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7038 {
7039         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7040
7041         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7042 }
7043
7044 static struct rte_driver rte_ixgbe_driver = {
7045         .type = PMD_PDEV,
7046         .init = rte_ixgbe_pmd_init,
7047 };
7048
7049 static struct rte_driver rte_ixgbevf_driver = {
7050         .type = PMD_PDEV,
7051         .init = rte_ixgbevf_pmd_init,
7052 };
7053
7054 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7055 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);