drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153
 154 enum ixgbevf_xcast_modes {
 155         IXGBEVF_XCAST_MODE_NONE = 0,
 156         IXGBEVF_XCAST_MODE_MULTI,
 157         IXGBEVF_XCAST_MODE_ALLMULTI,
 158 };
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 163 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 164 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 165 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 166 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 167 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 172 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 173                                 int wait_to_complete);
 174 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 175                                 struct rte_eth_stats *stats);
 176 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 177                                 struct rte_eth_xstats *xstats, unsigned n);
 178 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 179                                   struct rte_eth_xstats *xstats, unsigned n);
 180 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 181 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 182 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 183                                              uint16_t queue_id,
 184                                              uint8_t stat_idx,
 185                                              uint8_t is_rx);
 186 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 187                                struct rte_eth_dev_info *dev_info);
 188 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 189 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 190                                  struct rte_eth_dev_info *dev_info);
 191 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 192
 193 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 194                 uint16_t vlan_id, int on);
 195 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 196                                enum rte_vlan_type vlan_type,
 197                                uint16_t tpid_id);
 198 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 199                 uint16_t queue, bool on);
 200 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 201                 int on);
 202 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 203 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 204 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 205 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 206 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 207
 208 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 209 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 210 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 211                                struct rte_eth_fc_conf *fc_conf);
 212 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 215                 struct rte_eth_pfc_conf *pfc_conf);
 216 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 217                         struct rte_eth_rss_reta_entry64 *reta_conf,
 218                         uint16_t reta_size);
 219 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 220                         struct rte_eth_rss_reta_entry64 *reta_conf,
 221                         uint16_t reta_size);
 222 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 224 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 226 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 227 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 228                 void *param);
 229 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 230 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 231                 uint32_t index, uint32_t pool);
 232 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 233 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 234                                            struct ether_addr *mac_addr);
 235 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 236
 237 /* For Virtual Function support */
 238 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 239 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 240 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 241 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 243 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 244 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 245 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 246 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 247                 struct rte_eth_stats *stats);
 248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 250                 uint16_t vlan_id, int on);
 251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 252                 uint16_t queue, int on);
 253 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 254 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 255 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 256                                             uint16_t queue_id);
 257 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 258                                              uint16_t queue_id);
 259 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 260                                  uint8_t queue, uint8_t msix_vector);
 261 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 264
 265 /* For Eth VMDQ APIs support */
 266 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 267                 ether_addr * mac_addr, uint8_t on);
 268 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 269 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 270                 uint16_t rx_mask, uint8_t on);
 271 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 272 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 273 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 274                 uint64_t pool_mask, uint8_t vlan_on);
 275 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 276                 struct rte_eth_mirror_conf *mirror_conf,
 277                 uint8_t rule_id, uint8_t on);
 278 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 279                 uint8_t rule_id);
 280 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 281                                           uint16_t queue_id);
 282 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 283                                            uint16_t queue_id);
 284 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 285                                uint8_t queue, uint8_t msix_vector);
 286 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 287
 288 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 289                 uint16_t queue_idx, uint16_t tx_rate);
 290 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 291                 uint16_t tx_rate, uint64_t q_msk);
 292
 293 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 294                                  struct ether_addr *mac_addr,
 295                                  uint32_t index, uint32_t pool);
 296 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 297 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 298                                              struct ether_addr *mac_addr);
 299 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 300                         struct rte_eth_syn_filter *filter,
 301                         bool add);
 302 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 303                         struct rte_eth_syn_filter *filter);
 304 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 305                         enum rte_filter_op filter_op,
 306                         void *arg);
 307 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 308                         struct ixgbe_5tuple_filter *filter);
 309 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 310                         struct ixgbe_5tuple_filter *filter);
 311 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 312                         struct rte_eth_ntuple_filter *filter,
 313                         bool add);
 314 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 315                                 enum rte_filter_op filter_op,
 316                                 void *arg);
 317 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 318                         struct rte_eth_ntuple_filter *filter);
 319 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 320                         struct rte_eth_ethertype_filter *filter,
 321                         bool add);
 322 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 323                                 enum rte_filter_op filter_op,
 324                                 void *arg);
 325 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 326                         struct rte_eth_ethertype_filter *filter);
 327 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 328                      enum rte_filter_type filter_type,
 329                      enum rte_filter_op filter_op,
 330                      void *arg);
 331 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 332
 333 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 334                                       struct ether_addr *mc_addr_set,
 335                                       uint32_t nb_mc_addr);
 336 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 337                                    struct rte_eth_dcb_info *dcb_info);
 338
 339 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 340 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 341                             struct rte_dev_reg_info *regs);
 342 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 343 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 344                                 struct rte_dev_eeprom_info *eeprom);
 345 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 346                                 struct rte_dev_eeprom_info *eeprom);
 347
 348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 350                                 struct rte_dev_reg_info *regs);
 351
 352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 355                                             struct timespec *timestamp,
 356                                             uint32_t flags);
 357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 358                                             struct timespec *timestamp);
 359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 361                                    struct timespec *timestamp);
 362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 363                                    const struct timespec *timestamp);
 364
 365 static int ixgbe_dev_l2_tunnel_eth_type_conf
 366         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 367 static int ixgbe_dev_l2_tunnel_offload_set
 368         (struct rte_eth_dev *dev,
 369          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 370          uint32_t mask,
 371          uint8_t en);
 372 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 373                                              enum rte_filter_op filter_op,
 374                                              void *arg);
 375
 376 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 377                                          struct rte_eth_udp_tunnel *udp_tunnel);
 378 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 379                                          struct rte_eth_udp_tunnel *udp_tunnel);
 380
 381 /*
 382  * Define VF Stats MACRO for Non "cleared on read" register
 383  */
 384 #define UPDATE_VF_STAT(reg, last, cur)                          \
 385 {                                                               \
 386         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 387         cur += (latest - last) & UINT_MAX;                      \
 388         last = latest;                                          \
 389 }
 390
 391 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 392 {                                                                \
 393         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 394         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 395         u64 latest = ((new_msb << 32) | new_lsb);                \
 396         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 397         last = latest;                                           \
 398 }
 399
 400 #define IXGBE_SET_HWSTRIP(h, q) do {\
 401                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 402                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 403                 (h)->bitmap[idx] |= 1 << bit;\
 404         } while (0)
 405
 406 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 407                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 408                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 409                 (h)->bitmap[idx] &= ~(1 << bit);\
 410         } while (0)
 411
 412 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 413                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 414                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 415                 (r) = (h)->bitmap[idx] >> bit & 1;\
 416         } while (0)
 417
 418 /*
 419  * The set of PCI devices this driver supports
 420  */
 421 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 422
 423 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 424 #include "rte_pci_dev_ids.h"
 425
 426 { .vendor_id = 0, /* sentinel */ },
 427 };
 428
 429
 430 /*
 431  * The set of PCI devices this driver supports (for 82599 VF)
 432  */
 433 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 434
 435 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 436 #include "rte_pci_dev_ids.h"
 437 { .vendor_id = 0, /* sentinel */ },
 438
 439 };
 440
 441 static const struct rte_eth_desc_lim rx_desc_lim = {
 442         .nb_max = IXGBE_MAX_RING_DESC,
 443         .nb_min = IXGBE_MIN_RING_DESC,
 444         .nb_align = IXGBE_RXD_ALIGN,
 445 };
 446
 447 static const struct rte_eth_desc_lim tx_desc_lim = {
 448         .nb_max = IXGBE_MAX_RING_DESC,
 449         .nb_min = IXGBE_MIN_RING_DESC,
 450         .nb_align = IXGBE_TXD_ALIGN,
 451 };
 452
 453 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 454         .dev_configure        = ixgbe_dev_configure,
 455         .dev_start            = ixgbe_dev_start,
 456         .dev_stop             = ixgbe_dev_stop,
 457         .dev_set_link_up    = ixgbe_dev_set_link_up,
 458         .dev_set_link_down  = ixgbe_dev_set_link_down,
 459         .dev_close            = ixgbe_dev_close,
 460         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 461         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 462         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 463         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 464         .link_update          = ixgbe_dev_link_update,
 465         .stats_get            = ixgbe_dev_stats_get,
 466         .xstats_get           = ixgbe_dev_xstats_get,
 467         .stats_reset          = ixgbe_dev_stats_reset,
 468         .xstats_reset         = ixgbe_dev_xstats_reset,
 469         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 470         .dev_infos_get        = ixgbe_dev_info_get,
 471         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 472         .mtu_set              = ixgbe_dev_mtu_set,
 473         .vlan_filter_set      = ixgbe_vlan_filter_set,
 474         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 475         .vlan_offload_set     = ixgbe_vlan_offload_set,
 476         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 477         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 478         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 479         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 480         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 481         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 482         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 483         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 484         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 485         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 486         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 487         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 488         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 489         .dev_led_on           = ixgbe_dev_led_on,
 490         .dev_led_off          = ixgbe_dev_led_off,
 491         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 492         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 493         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 494         .mac_addr_add         = ixgbe_add_rar,
 495         .mac_addr_remove      = ixgbe_remove_rar,
 496         .mac_addr_set         = ixgbe_set_default_mac_addr,
 497         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 498         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 499         .mirror_rule_set      = ixgbe_mirror_rule_set,
 500         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 501         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 502         .set_vf_rx            = ixgbe_set_pool_rx,
 503         .set_vf_tx            = ixgbe_set_pool_tx,
 504         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 505         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 506         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 507         .reta_update          = ixgbe_dev_rss_reta_update,
 508         .reta_query           = ixgbe_dev_rss_reta_query,
 509 #ifdef RTE_NIC_BYPASS
 510         .bypass_init          = ixgbe_bypass_init,
 511         .bypass_state_set     = ixgbe_bypass_state_store,
 512         .bypass_state_show    = ixgbe_bypass_state_show,
 513         .bypass_event_set     = ixgbe_bypass_event_store,
 514         .bypass_event_show    = ixgbe_bypass_event_show,
 515         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 516         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 517         .bypass_ver_show      = ixgbe_bypass_ver_show,
 518         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 519 #endif /* RTE_NIC_BYPASS */
 520         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 521         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 522         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 523         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 524         .rxq_info_get         = ixgbe_rxq_info_get,
 525         .txq_info_get         = ixgbe_txq_info_get,
 526         .timesync_enable      = ixgbe_timesync_enable,
 527         .timesync_disable     = ixgbe_timesync_disable,
 528         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 529         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 530         .get_reg_length       = ixgbe_get_reg_length,
 531         .get_reg              = ixgbe_get_regs,
 532         .get_eeprom_length    = ixgbe_get_eeprom_length,
 533         .get_eeprom           = ixgbe_get_eeprom,
 534         .set_eeprom           = ixgbe_set_eeprom,
 535         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 536         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 537         .timesync_read_time   = ixgbe_timesync_read_time,
 538         .timesync_write_time  = ixgbe_timesync_write_time,
 539         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 540         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 541         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 542         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 543 };
 544
 545 /*
 546  * dev_ops for virtual function, bare necessities for basic vf
 547  * operation have been implemented
 548  */
 549 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 550         .dev_configure        = ixgbevf_dev_configure,
 551         .dev_start            = ixgbevf_dev_start,
 552         .dev_stop             = ixgbevf_dev_stop,
 553         .link_update          = ixgbe_dev_link_update,
 554         .stats_get            = ixgbevf_dev_stats_get,
 555         .xstats_get           = ixgbevf_dev_xstats_get,
 556         .stats_reset          = ixgbevf_dev_stats_reset,
 557         .xstats_reset         = ixgbevf_dev_stats_reset,
 558         .dev_close            = ixgbevf_dev_close,
 559         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 560         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 561         .dev_infos_get        = ixgbevf_dev_info_get,
 562         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 563         .mtu_set              = ixgbevf_dev_set_mtu,
 564         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 565         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 566         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 567         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 568         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 569         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 570         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 571         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 572         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 573         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 574         .mac_addr_add         = ixgbevf_add_mac_addr,
 575         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 576         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 577         .rxq_info_get         = ixgbe_rxq_info_get,
 578         .txq_info_get         = ixgbe_txq_info_get,
 579         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 580         .get_reg_length       = ixgbevf_get_reg_length,
 581         .get_reg              = ixgbevf_get_regs,
 582         .reta_update          = ixgbe_dev_rss_reta_update,
 583         .reta_query           = ixgbe_dev_rss_reta_query,
 584         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 585         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 586 };
 587
 588 /* store statistics names and its offset in stats structure */
 589 struct rte_ixgbe_xstats_name_off {
 590         char name[RTE_ETH_XSTATS_NAME_SIZE];
 591         unsigned offset;
 592 };
 593
 594 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 595         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 596         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 597         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 598         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 599         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 600         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 601         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 602         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 603         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 604         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 605         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 606         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 607         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 608         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 609         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 610                 prc1023)},
 611         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 612                 prc1522)},
 613         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 614         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 615         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 616         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 617         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 618         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 619         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 620         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 621         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 622         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 623         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 624         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 625         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 626         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 627         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 628         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 629         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 630                 ptc1023)},
 631         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 632                 ptc1522)},
 633         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 634         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 635         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 636         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 637
 638         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 639                 fdirustat_add)},
 640         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 641                 fdirustat_remove)},
 642         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 643                 fdirfstat_fadd)},
 644         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 645                 fdirfstat_fremove)},
 646         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 647                 fdirmatch)},
 648         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 649                 fdirmiss)},
 650
 651         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 652         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 653         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 654                 fclast)},
 655         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 656         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 657         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 658         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 659         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 660                 fcoe_noddp)},
 661         {"rx_fcoe_no_direct_data_placement_ext_buff",
 662                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 663
 664         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 665                 lxontxc)},
 666         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 667                 lxonrxc)},
 668         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 669                 lxofftxc)},
 670         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 671                 lxoffrxc)},
 672         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 673 };
 674
 675 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 676                            sizeof(rte_ixgbe_stats_strings[0]))
 677
 678 /* Per-queue statistics */
 679 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 680         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 681         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 682         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 683         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 684 };
 685
 686 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 687                            sizeof(rte_ixgbe_rxq_strings[0]))
 688
 689 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 690         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 691         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 692         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 693                 pxon2offc)},
 694 };
 695
 696 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 697                            sizeof(rte_ixgbe_txq_strings[0]))
 698
 699 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 700         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 701 };
 702
 703 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 704                 sizeof(rte_ixgbevf_stats_strings[0]))
 705
 706 /**
 707  * Atomically reads the link status information from global
 708  * structure rte_eth_dev.
 709  *
 710  * @param dev
 711  *   - Pointer to the structure rte_eth_dev to read from.
 712  *   - Pointer to the buffer to be saved with the link status.
 713  *
 714  * @return
 715  *   - On success, zero.
 716  *   - On failure, negative value.
 717  */
 718 static inline int
 719 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 720                                 struct rte_eth_link *link)
 721 {
 722         struct rte_eth_link *dst = link;
 723         struct rte_eth_link *src = &(dev->data->dev_link);
 724
 725         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 726                                         *(uint64_t *)src) == 0)
 727                 return -1;
 728
 729         return 0;
 730 }
 731
 732 /**
 733  * Atomically writes the link status information into global
 734  * structure rte_eth_dev.
 735  *
 736  * @param dev
 737  *   - Pointer to the structure rte_eth_dev to read from.
 738  *   - Pointer to the buffer to be saved with the link status.
 739  *
 740  * @return
 741  *   - On success, zero.
 742  *   - On failure, negative value.
 743  */
 744 static inline int
 745 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 746                                 struct rte_eth_link *link)
 747 {
 748         struct rte_eth_link *dst = &(dev->data->dev_link);
 749         struct rte_eth_link *src = link;
 750
 751         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 752                                         *(uint64_t *)src) == 0)
 753                 return -1;
 754
 755         return 0;
 756 }
 757
 758 /*
 759  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 760  */
 761 static inline int
 762 ixgbe_is_sfp(struct ixgbe_hw *hw)
 763 {
 764         switch (hw->phy.type) {
 765         case ixgbe_phy_sfp_avago:
 766         case ixgbe_phy_sfp_ftl:
 767         case ixgbe_phy_sfp_intel:
 768         case ixgbe_phy_sfp_unknown:
 769         case ixgbe_phy_sfp_passive_tyco:
 770         case ixgbe_phy_sfp_passive_unknown:
 771                 return 1;
 772         default:
 773                 return 0;
 774         }
 775 }
 776
 777 static inline int32_t
 778 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 779 {
 780         uint32_t ctrl_ext;
 781         int32_t status;
 782
 783         status = ixgbe_reset_hw(hw);
 784
 785         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 786         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 787         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 788         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 789         IXGBE_WRITE_FLUSH(hw);
 790
 791         return status;
 792 }
 793
 794 static inline void
 795 ixgbe_enable_intr(struct rte_eth_dev *dev)
 796 {
 797         struct ixgbe_interrupt *intr =
 798                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 799         struct ixgbe_hw *hw =
 800                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 801
 802         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 803         IXGBE_WRITE_FLUSH(hw);
 804 }
 805
 806 /*
 807  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 808  */
 809 static void
 810 ixgbe_disable_intr(struct ixgbe_hw *hw)
 811 {
 812         PMD_INIT_FUNC_TRACE();
 813
 814         if (hw->mac.type == ixgbe_mac_82598EB) {
 815                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 816         } else {
 817                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 818                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 819                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 820         }
 821         IXGBE_WRITE_FLUSH(hw);
 822 }
 823
 824 /*
 825  * This function resets queue statistics mapping registers.
 826  * From Niantic datasheet, Initialization of Statistics section:
 827  * "...if software requires the queue counters, the RQSMR and TQSM registers
 828  * must be re-programmed following a device reset.
 829  */
 830 static void
 831 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 832 {
 833         uint32_t i;
 834
 835         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 836                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 837                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 838         }
 839 }
 840
 841
 842 static int
 843 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 844                                   uint16_t queue_id,
 845                                   uint8_t stat_idx,
 846                                   uint8_t is_rx)
 847 {
 848 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 849 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 850 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 851
 852         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 853         struct ixgbe_stat_mapping_registers *stat_mappings =
 854                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 855         uint32_t qsmr_mask = 0;
 856         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 857         uint32_t q_map;
 858         uint8_t n, offset;
 859
 860         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 861                 (hw->mac.type != ixgbe_mac_X540) &&
 862                 (hw->mac.type != ixgbe_mac_X550) &&
 863                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 864                 (hw->mac.type != ixgbe_mac_X550EM_a))
 865                 return -ENOSYS;
 866
 867         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 868                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 869                      queue_id, stat_idx);
 870
 871         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 872         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 873                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 874                 return -EIO;
 875         }
 876         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 877
 878         /* Now clear any previous stat_idx set */
 879         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 880         if (!is_rx)
 881                 stat_mappings->tqsm[n] &= ~clearing_mask;
 882         else
 883                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 884
 885         q_map = (uint32_t)stat_idx;
 886         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 887         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 888         if (!is_rx)
 889                 stat_mappings->tqsm[n] |= qsmr_mask;
 890         else
 891                 stat_mappings->rqsmr[n] |= qsmr_mask;
 892
 893         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 894                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 895                      queue_id, stat_idx);
 896         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 897                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 898
 899         /* Now write the mapping in the appropriate register */
 900         if (is_rx) {
 901                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 902                              stat_mappings->rqsmr[n], n);
 903                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 904         } else {
 905                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 906                              stat_mappings->tqsm[n], n);
 907                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 908         }
 909         return 0;
 910 }
 911
 912 static void
 913 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 914 {
 915         struct ixgbe_stat_mapping_registers *stat_mappings =
 916                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 917         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 918         int i;
 919
 920         /* write whatever was in stat mapping table to the NIC */
 921         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 922                 /* rx */
 923                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 924
 925                 /* tx */
 926                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 927         }
 928 }
 929
 930 static void
 931 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 932 {
 933         uint8_t i;
 934         struct ixgbe_dcb_tc_config *tc;
 935         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 936
 937         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 938         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 939         for (i = 0; i < dcb_max_tc; i++) {
 940                 tc = &dcb_config->tc_config[i];
 941                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 942                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 943                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 944                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 945                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 946                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 947                 tc->pfc = ixgbe_dcb_pfc_disabled;
 948         }
 949
 950         /* Initialize default user to priority mapping, UPx->TC0 */
 951         tc = &dcb_config->tc_config[0];
 952         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 953         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 954         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 955                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 956                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 957         }
 958         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 959         dcb_config->pfc_mode_enable = false;
 960         dcb_config->vt_mode = true;
 961         dcb_config->round_robin_enable = false;
 962         /* support all DCB capabilities in 82599 */
 963         dcb_config->support.capabilities = 0xFF;
 964
 965         /*we only support 4 Tcs for X540, X550 */
 966         if (hw->mac.type == ixgbe_mac_X540 ||
 967                 hw->mac.type == ixgbe_mac_X550 ||
 968                 hw->mac.type == ixgbe_mac_X550EM_x ||
 969                 hw->mac.type == ixgbe_mac_X550EM_a) {
 970                 dcb_config->num_tcs.pg_tcs = 4;
 971                 dcb_config->num_tcs.pfc_tcs = 4;
 972         }
 973 }
 974
 975 /*
 976  * Ensure that all locks are released before first NVM or PHY access
 977  */
 978 static void
 979 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 980 {
 981         uint16_t mask;
 982
 983         /*
 984          * Phy lock should not fail in this early stage. If this is the case,
 985          * it is due to an improper exit of the application.
 986          * So force the release of the faulty lock. Release of common lock
 987          * is done automatically by swfw_sync function.
 988          */
 989         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 990         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 991                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 992         }
 993         ixgbe_release_swfw_semaphore(hw, mask);
 994
 995         /*
 996          * These ones are more tricky since they are common to all ports; but
 997          * swfw_sync retries last long enough (1s) to be almost sure that if
 998          * lock can not be taken it is due to an improper lock of the
 999          * semaphore.
1000          */
1001         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1002         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1003                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1004         }
1005         ixgbe_release_swfw_semaphore(hw, mask);
1006 }
1007
1008 /*
1009  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1010  * It returns 0 on success.
1011  */
1012 static int
1013 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1014 {
1015         struct rte_pci_device *pci_dev;
1016         struct ixgbe_hw *hw =
1017                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1018         struct ixgbe_vfta *shadow_vfta =
1019                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1020         struct ixgbe_hwstrip *hwstrip =
1021                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1022         struct ixgbe_dcb_config *dcb_config =
1023                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1024         struct ixgbe_filter_info *filter_info =
1025                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1026         uint32_t ctrl_ext;
1027         uint16_t csum;
1028         int diag, i;
1029
1030         PMD_INIT_FUNC_TRACE();
1031
1032         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1033         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1034         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1035
1036         /*
1037          * For secondary processes, we don't initialise any further as primary
1038          * has already done this work. Only check we don't need a different
1039          * RX and TX function.
1040          */
1041         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1042                 struct ixgbe_tx_queue *txq;
1043                 /* TX queue function in primary, set by last queue initialized
1044                  * Tx queue may not initialized by primary process
1045                  */
1046                 if (eth_dev->data->tx_queues) {
1047                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1048                         ixgbe_set_tx_function(eth_dev, txq);
1049                 } else {
1050                         /* Use default TX function if we get here */
1051                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1052                                      "Using default TX function.");
1053                 }
1054
1055                 ixgbe_set_rx_function(eth_dev);
1056
1057                 return 0;
1058         }
1059         pci_dev = eth_dev->pci_dev;
1060
1061         rte_eth_copy_pci_info(eth_dev, pci_dev);
1062
1063         /* Vendor and Device ID need to be set before init of shared code */
1064         hw->device_id = pci_dev->id.device_id;
1065         hw->vendor_id = pci_dev->id.vendor_id;
1066         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1067         hw->allow_unsupported_sfp = 1;
1068
1069         /* Initialize the shared code (base driver) */
1070 #ifdef RTE_NIC_BYPASS
1071         diag = ixgbe_bypass_init_shared_code(hw);
1072 #else
1073         diag = ixgbe_init_shared_code(hw);
1074 #endif /* RTE_NIC_BYPASS */
1075
1076         if (diag != IXGBE_SUCCESS) {
1077                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1078                 return -EIO;
1079         }
1080
1081         /* pick up the PCI bus settings for reporting later */
1082         ixgbe_get_bus_info(hw);
1083
1084         /* Unlock any pending hardware semaphore */
1085         ixgbe_swfw_lock_reset(hw);
1086
1087         /* Initialize DCB configuration*/
1088         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1089         ixgbe_dcb_init(hw, dcb_config);
1090         /* Get Hardware Flow Control setting */
1091         hw->fc.requested_mode = ixgbe_fc_full;
1092         hw->fc.current_mode = ixgbe_fc_full;
1093         hw->fc.pause_time = IXGBE_FC_PAUSE;
1094         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1095                 hw->fc.low_water[i] = IXGBE_FC_LO;
1096                 hw->fc.high_water[i] = IXGBE_FC_HI;
1097         }
1098         hw->fc.send_xon = 1;
1099
1100         /* Make sure we have a good EEPROM before we read from it */
1101         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1102         if (diag != IXGBE_SUCCESS) {
1103                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1104                 return -EIO;
1105         }
1106
1107 #ifdef RTE_NIC_BYPASS
1108         diag = ixgbe_bypass_init_hw(hw);
1109 #else
1110         diag = ixgbe_init_hw(hw);
1111 #endif /* RTE_NIC_BYPASS */
1112
1113         /*
1114          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1115          * is called too soon after the kernel driver unbinding/binding occurs.
1116          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1117          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1118          * also called. See ixgbe_identify_phy_82599(). The reason for the
1119          * failure is not known, and only occuts when virtualisation features
1120          * are disabled in the bios. A delay of 100ms  was found to be enough by
1121          * trial-and-error, and is doubled to be safe.
1122          */
1123         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1124                 rte_delay_ms(200);
1125                 diag = ixgbe_init_hw(hw);
1126         }
1127
1128         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1129                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1130                              "LOM.  Please be aware there may be issues associated "
1131                              "with your hardware.");
1132                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1133                              "please contact your Intel or hardware representative "
1134                              "who provided you with this hardware.");
1135         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1136                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1137         if (diag) {
1138                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1139                 return -EIO;
1140         }
1141
1142         /* Reset the hw statistics */
1143         ixgbe_dev_stats_reset(eth_dev);
1144
1145         /* disable interrupt */
1146         ixgbe_disable_intr(hw);
1147
1148         /* reset mappings for queue statistics hw counters*/
1149         ixgbe_reset_qstat_mappings(hw);
1150
1151         /* Allocate memory for storing MAC addresses */
1152         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1153                                                hw->mac.num_rar_entries, 0);
1154         if (eth_dev->data->mac_addrs == NULL) {
1155                 PMD_INIT_LOG(ERR,
1156                              "Failed to allocate %u bytes needed to store "
1157                              "MAC addresses",
1158                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1159                 return -ENOMEM;
1160         }
1161         /* Copy the permanent MAC address */
1162         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1163                         &eth_dev->data->mac_addrs[0]);
1164
1165         /* Allocate memory for storing hash filter MAC addresses */
1166         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1167                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1168         if (eth_dev->data->hash_mac_addrs == NULL) {
1169                 PMD_INIT_LOG(ERR,
1170                              "Failed to allocate %d bytes needed to store MAC addresses",
1171                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1172                 return -ENOMEM;
1173         }
1174
1175         /* initialize the vfta */
1176         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1177
1178         /* initialize the hw strip bitmap*/
1179         memset(hwstrip, 0, sizeof(*hwstrip));
1180
1181         /* initialize PF if max_vfs not zero */
1182         ixgbe_pf_host_init(eth_dev);
1183
1184         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1185         /* let hardware know driver is loaded */
1186         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1187         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1188         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1189         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1190         IXGBE_WRITE_FLUSH(hw);
1191
1192         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1193                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1194                              (int) hw->mac.type, (int) hw->phy.type,
1195                              (int) hw->phy.sfp_type);
1196         else
1197                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1198                              (int) hw->mac.type, (int) hw->phy.type);
1199
1200         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1201                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1202                      pci_dev->id.device_id);
1203
1204         rte_intr_callback_register(&pci_dev->intr_handle,
1205                                    ixgbe_dev_interrupt_handler,
1206                                    (void *)eth_dev);
1207
1208         /* enable uio/vfio intr/eventfd mapping */
1209         rte_intr_enable(&pci_dev->intr_handle);
1210
1211         /* enable support intr */
1212         ixgbe_enable_intr(eth_dev);
1213
1214         /* initialize 5tuple filter list */
1215         TAILQ_INIT(&filter_info->fivetuple_list);
1216         memset(filter_info->fivetuple_mask, 0,
1217                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1218
1219         return 0;
1220 }
1221
1222 static int
1223 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1224 {
1225         struct rte_pci_device *pci_dev;
1226         struct ixgbe_hw *hw;
1227
1228         PMD_INIT_FUNC_TRACE();
1229
1230         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1231                 return -EPERM;
1232
1233         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1234         pci_dev = eth_dev->pci_dev;
1235
1236         if (hw->adapter_stopped == 0)
1237                 ixgbe_dev_close(eth_dev);
1238
1239         eth_dev->dev_ops = NULL;
1240         eth_dev->rx_pkt_burst = NULL;
1241         eth_dev->tx_pkt_burst = NULL;
1242
1243         /* Unlock any pending hardware semaphore */
1244         ixgbe_swfw_lock_reset(hw);
1245
1246         /* disable uio intr before callback unregister */
1247         rte_intr_disable(&(pci_dev->intr_handle));
1248         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1249                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1250
1251         /* uninitialize PF if max_vfs not zero */
1252         ixgbe_pf_host_uninit(eth_dev);
1253
1254         rte_free(eth_dev->data->mac_addrs);
1255         eth_dev->data->mac_addrs = NULL;
1256
1257         rte_free(eth_dev->data->hash_mac_addrs);
1258         eth_dev->data->hash_mac_addrs = NULL;
1259
1260         return 0;
1261 }
1262
1263 /*
1264  * Negotiate mailbox API version with the PF.
1265  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1266  * Then we try to negotiate starting with the most recent one.
1267  * If all negotiation attempts fail, then we will proceed with
1268  * the default one (ixgbe_mbox_api_10).
1269  */
1270 static void
1271 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1272 {
1273         int32_t i;
1274
1275         /* start with highest supported, proceed down */
1276         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1277                 ixgbe_mbox_api_12,
1278                 ixgbe_mbox_api_11,
1279                 ixgbe_mbox_api_10,
1280         };
1281
1282         for (i = 0;
1283                         i != RTE_DIM(sup_ver) &&
1284                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1285                         i++)
1286                 ;
1287 }
1288
1289 static void
1290 generate_random_mac_addr(struct ether_addr *mac_addr)
1291 {
1292         uint64_t random;
1293
1294         /* Set Organizationally Unique Identifier (OUI) prefix. */
1295         mac_addr->addr_bytes[0] = 0x00;
1296         mac_addr->addr_bytes[1] = 0x09;
1297         mac_addr->addr_bytes[2] = 0xC0;
1298         /* Force indication of locally assigned MAC address. */
1299         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1300         /* Generate the last 3 bytes of the MAC address with a random number. */
1301         random = rte_rand();
1302         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1303 }
1304
1305 /*
1306  * Virtual Function device init
1307  */
1308 static int
1309 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1310 {
1311         int diag;
1312         uint32_t tc, tcs;
1313         struct rte_pci_device *pci_dev;
1314         struct ixgbe_hw *hw =
1315                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1316         struct ixgbe_vfta *shadow_vfta =
1317                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1318         struct ixgbe_hwstrip *hwstrip =
1319                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1320         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1321
1322         PMD_INIT_FUNC_TRACE();
1323
1324         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1325         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1326         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1327
1328         /* for secondary processes, we don't initialise any further as primary
1329          * has already done this work. Only check we don't need a different
1330          * RX function
1331          */
1332         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1333                 struct ixgbe_tx_queue *txq;
1334                 /* TX queue function in primary, set by last queue initialized
1335                  * Tx queue may not initialized by primary process
1336                  */
1337                 if (eth_dev->data->tx_queues) {
1338                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1339                         ixgbe_set_tx_function(eth_dev, txq);
1340                 } else {
1341                         /* Use default TX function if we get here */
1342                         PMD_INIT_LOG(NOTICE,
1343                                      "No TX queues configured yet. Using default TX function.");
1344                 }
1345
1346                 ixgbe_set_rx_function(eth_dev);
1347
1348                 return 0;
1349         }
1350
1351         pci_dev = eth_dev->pci_dev;
1352
1353         rte_eth_copy_pci_info(eth_dev, pci_dev);
1354
1355         hw->device_id = pci_dev->id.device_id;
1356         hw->vendor_id = pci_dev->id.vendor_id;
1357         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1358
1359         /* initialize the vfta */
1360         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1361
1362         /* initialize the hw strip bitmap*/
1363         memset(hwstrip, 0, sizeof(*hwstrip));
1364
1365         /* Initialize the shared code (base driver) */
1366         diag = ixgbe_init_shared_code(hw);
1367         if (diag != IXGBE_SUCCESS) {
1368                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1369                 return -EIO;
1370         }
1371
1372         /* init_mailbox_params */
1373         hw->mbx.ops.init_params(hw);
1374
1375         /* Reset the hw statistics */
1376         ixgbevf_dev_stats_reset(eth_dev);
1377
1378         /* Disable the interrupts for VF */
1379         ixgbevf_intr_disable(hw);
1380
1381         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1382         diag = hw->mac.ops.reset_hw(hw);
1383
1384         /*
1385          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1386          * the underlying PF driver has not assigned a MAC address to the VF.
1387          * In this case, assign a random MAC address.
1388          */
1389         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1390                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1391                 return diag;
1392         }
1393
1394         /* negotiate mailbox API version to use with the PF. */
1395         ixgbevf_negotiate_api(hw);
1396
1397         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1398         ixgbevf_get_queues(hw, &tcs, &tc);
1399
1400         /* Allocate memory for storing MAC addresses */
1401         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1402                                                hw->mac.num_rar_entries, 0);
1403         if (eth_dev->data->mac_addrs == NULL) {
1404                 PMD_INIT_LOG(ERR,
1405                              "Failed to allocate %u bytes needed to store "
1406                              "MAC addresses",
1407                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1408                 return -ENOMEM;
1409         }
1410
1411         /* Generate a random MAC address, if none was assigned by PF. */
1412         if (is_zero_ether_addr(perm_addr)) {
1413                 generate_random_mac_addr(perm_addr);
1414                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1415                 if (diag) {
1416                         rte_free(eth_dev->data->mac_addrs);
1417                         eth_dev->data->mac_addrs = NULL;
1418                         return diag;
1419                 }
1420                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1421                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1422                              "%02x:%02x:%02x:%02x:%02x:%02x",
1423                              perm_addr->addr_bytes[0],
1424                              perm_addr->addr_bytes[1],
1425                              perm_addr->addr_bytes[2],
1426                              perm_addr->addr_bytes[3],
1427                              perm_addr->addr_bytes[4],
1428                              perm_addr->addr_bytes[5]);
1429         }
1430
1431         /* Copy the permanent MAC address */
1432         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1433
1434         /* reset the hardware with the new settings */
1435         diag = hw->mac.ops.start_hw(hw);
1436         switch (diag) {
1437         case  0:
1438                 break;
1439
1440         default:
1441                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1442                 return -EIO;
1443         }
1444
1445         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1446                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1447                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1448
1449         return 0;
1450 }
1451
1452 /* Virtual Function device uninit */
1453
1454 static int
1455 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1456 {
1457         struct ixgbe_hw *hw;
1458
1459         PMD_INIT_FUNC_TRACE();
1460
1461         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1462                 return -EPERM;
1463
1464         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1465
1466         if (hw->adapter_stopped == 0)
1467                 ixgbevf_dev_close(eth_dev);
1468
1469         eth_dev->dev_ops = NULL;
1470         eth_dev->rx_pkt_burst = NULL;
1471         eth_dev->tx_pkt_burst = NULL;
1472
1473         /* Disable the interrupts for VF */
1474         ixgbevf_intr_disable(hw);
1475
1476         rte_free(eth_dev->data->mac_addrs);
1477         eth_dev->data->mac_addrs = NULL;
1478
1479         return 0;
1480 }
1481
1482 static struct eth_driver rte_ixgbe_pmd = {
1483         .pci_drv = {
1484                 .name = "rte_ixgbe_pmd",
1485                 .id_table = pci_id_ixgbe_map,
1486                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1487                         RTE_PCI_DRV_DETACHABLE,
1488         },
1489         .eth_dev_init = eth_ixgbe_dev_init,
1490         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1491         .dev_private_size = sizeof(struct ixgbe_adapter),
1492 };
1493
1494 /*
1495  * virtual function driver struct
1496  */
1497 static struct eth_driver rte_ixgbevf_pmd = {
1498         .pci_drv = {
1499                 .name = "rte_ixgbevf_pmd",
1500                 .id_table = pci_id_ixgbevf_map,
1501                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1502         },
1503         .eth_dev_init = eth_ixgbevf_dev_init,
1504         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1505         .dev_private_size = sizeof(struct ixgbe_adapter),
1506 };
1507
1508 /*
1509  * Driver initialization routine.
1510  * Invoked once at EAL init time.
1511  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1512  */
1513 static int
1514 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1515 {
1516         PMD_INIT_FUNC_TRACE();
1517
1518         rte_eth_driver_register(&rte_ixgbe_pmd);
1519         return 0;
1520 }
1521
1522 /*
1523  * VF Driver initialization routine.
1524  * Invoked one at EAL init time.
1525  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1526  */
1527 static int
1528 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1529 {
1530         PMD_INIT_FUNC_TRACE();
1531
1532         rte_eth_driver_register(&rte_ixgbevf_pmd);
1533         return 0;
1534 }
1535
1536 static int
1537 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1538 {
1539         struct ixgbe_hw *hw =
1540                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1541         struct ixgbe_vfta *shadow_vfta =
1542                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1543         uint32_t vfta;
1544         uint32_t vid_idx;
1545         uint32_t vid_bit;
1546
1547         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1548         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1549         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1550         if (on)
1551                 vfta |= vid_bit;
1552         else
1553                 vfta &= ~vid_bit;
1554         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1555
1556         /* update local VFTA copy */
1557         shadow_vfta->vfta[vid_idx] = vfta;
1558
1559         return 0;
1560 }
1561
1562 static void
1563 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1564 {
1565         if (on)
1566                 ixgbe_vlan_hw_strip_enable(dev, queue);
1567         else
1568                 ixgbe_vlan_hw_strip_disable(dev, queue);
1569 }
1570
1571 static int
1572 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1573                     enum rte_vlan_type vlan_type,
1574                     uint16_t tpid)
1575 {
1576         struct ixgbe_hw *hw =
1577                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1578         int ret = 0;
1579
1580         switch (vlan_type) {
1581         case ETH_VLAN_TYPE_INNER:
1582                 /* Only the high 16-bits is valid */
1583                 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1584                 break;
1585         default:
1586                 ret = -EINVAL;
1587                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1588                 break;
1589         }
1590
1591         return ret;
1592 }
1593
1594 void
1595 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1596 {
1597         struct ixgbe_hw *hw =
1598                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1599         uint32_t vlnctrl;
1600
1601         PMD_INIT_FUNC_TRACE();
1602
1603         /* Filter Table Disable */
1604         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1605         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1606
1607         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1608 }
1609
1610 void
1611 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1612 {
1613         struct ixgbe_hw *hw =
1614                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1615         struct ixgbe_vfta *shadow_vfta =
1616                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1617         uint32_t vlnctrl;
1618         uint16_t i;
1619
1620         PMD_INIT_FUNC_TRACE();
1621
1622         /* Filter Table Enable */
1623         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1624         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1625         vlnctrl |= IXGBE_VLNCTRL_VFE;
1626
1627         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1628
1629         /* write whatever is in local vfta copy */
1630         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1631                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1632 }
1633
1634 static void
1635 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1636 {
1637         struct ixgbe_hwstrip *hwstrip =
1638                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1639         struct ixgbe_rx_queue *rxq;
1640
1641         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1642                 return;
1643
1644         if (on)
1645                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1646         else
1647                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1648
1649         if (queue >= dev->data->nb_rx_queues)
1650                 return;
1651
1652         rxq = dev->data->rx_queues[queue];
1653
1654         if (on)
1655                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1656         else
1657                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1658 }
1659
1660 static void
1661 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1662 {
1663         struct ixgbe_hw *hw =
1664                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1665         uint32_t ctrl;
1666
1667         PMD_INIT_FUNC_TRACE();
1668
1669         if (hw->mac.type == ixgbe_mac_82598EB) {
1670                 /* No queue level support */
1671                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1672                 return;
1673         }
1674
1675         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1676         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1677         ctrl &= ~IXGBE_RXDCTL_VME;
1678         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1679
1680         /* record those setting for HW strip per queue */
1681         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1682 }
1683
1684 static void
1685 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1686 {
1687         struct ixgbe_hw *hw =
1688                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1689         uint32_t ctrl;
1690
1691         PMD_INIT_FUNC_TRACE();
1692
1693         if (hw->mac.type == ixgbe_mac_82598EB) {
1694                 /* No queue level supported */
1695                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1696                 return;
1697         }
1698
1699         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1700         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1701         ctrl |= IXGBE_RXDCTL_VME;
1702         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1703
1704         /* record those setting for HW strip per queue */
1705         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1706 }
1707
1708 void
1709 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1710 {
1711         struct ixgbe_hw *hw =
1712                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1713         uint32_t ctrl;
1714         uint16_t i;
1715
1716         PMD_INIT_FUNC_TRACE();
1717
1718         if (hw->mac.type == ixgbe_mac_82598EB) {
1719                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1720                 ctrl &= ~IXGBE_VLNCTRL_VME;
1721                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1722         } else {
1723                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1724                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1725                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1726                         ctrl &= ~IXGBE_RXDCTL_VME;
1727                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1728
1729                         /* record those setting for HW strip per queue */
1730                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1731                 }
1732         }
1733 }
1734
1735 void
1736 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1737 {
1738         struct ixgbe_hw *hw =
1739                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1740         uint32_t ctrl;
1741         uint16_t i;
1742
1743         PMD_INIT_FUNC_TRACE();
1744
1745         if (hw->mac.type == ixgbe_mac_82598EB) {
1746                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1747                 ctrl |= IXGBE_VLNCTRL_VME;
1748                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1749         } else {
1750                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1751                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1752                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1753                         ctrl |= IXGBE_RXDCTL_VME;
1754                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1755
1756                         /* record those setting for HW strip per queue */
1757                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1758                 }
1759         }
1760 }
1761
1762 static void
1763 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1764 {
1765         struct ixgbe_hw *hw =
1766                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1767         uint32_t ctrl;
1768
1769         PMD_INIT_FUNC_TRACE();
1770
1771         /* DMATXCTRL: Geric Double VLAN Disable */
1772         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1773         ctrl &= ~IXGBE_DMATXCTL_GDV;
1774         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1775
1776         /* CTRL_EXT: Global Double VLAN Disable */
1777         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1778         ctrl &= ~IXGBE_EXTENDED_VLAN;
1779         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1780
1781 }
1782
1783 static void
1784 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1785 {
1786         struct ixgbe_hw *hw =
1787                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1788         uint32_t ctrl;
1789
1790         PMD_INIT_FUNC_TRACE();
1791
1792         /* DMATXCTRL: Geric Double VLAN Enable */
1793         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1794         ctrl |= IXGBE_DMATXCTL_GDV;
1795         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1796
1797         /* CTRL_EXT: Global Double VLAN Enable */
1798         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1799         ctrl |= IXGBE_EXTENDED_VLAN;
1800         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1801
1802         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1803         if (hw->mac.type == ixgbe_mac_X550 ||
1804             hw->mac.type == ixgbe_mac_X550EM_x ||
1805             hw->mac.type == ixgbe_mac_X550EM_a) {
1806                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1807                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1808                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1809         }
1810
1811         /*
1812          * VET EXT field in the EXVET register = 0x8100 by default
1813          * So no need to change. Same to VT field of DMATXCTL register
1814          */
1815 }
1816
1817 static void
1818 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1819 {
1820         if (mask & ETH_VLAN_STRIP_MASK) {
1821                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1822                         ixgbe_vlan_hw_strip_enable_all(dev);
1823                 else
1824                         ixgbe_vlan_hw_strip_disable_all(dev);
1825         }
1826
1827         if (mask & ETH_VLAN_FILTER_MASK) {
1828                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1829                         ixgbe_vlan_hw_filter_enable(dev);
1830                 else
1831                         ixgbe_vlan_hw_filter_disable(dev);
1832         }
1833
1834         if (mask & ETH_VLAN_EXTEND_MASK) {
1835                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1836                         ixgbe_vlan_hw_extend_enable(dev);
1837                 else
1838                         ixgbe_vlan_hw_extend_disable(dev);
1839         }
1840 }
1841
1842 static void
1843 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1844 {
1845         struct ixgbe_hw *hw =
1846                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1847         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1848         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1849
1850         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1851         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1852 }
1853
1854 static int
1855 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1856 {
1857         switch (nb_rx_q) {
1858         case 1:
1859         case 2:
1860                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1861                 break;
1862         case 4:
1863                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1864                 break;
1865         default:
1866                 return -EINVAL;
1867         }
1868
1869         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1870         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1871
1872         return 0;
1873 }
1874
1875 static int
1876 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1877 {
1878         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1879         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1880         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1881         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1882
1883         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1884                 /* check multi-queue mode */
1885                 switch (dev_conf->rxmode.mq_mode) {
1886                 case ETH_MQ_RX_VMDQ_DCB:
1887                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1888                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1889                         PMD_INIT_LOG(ERR, "SRIOV active,"
1890                                         " unsupported mq_mode rx %d.",
1891                                         dev_conf->rxmode.mq_mode);
1892                         return -EINVAL;
1893                 case ETH_MQ_RX_RSS:
1894                 case ETH_MQ_RX_VMDQ_RSS:
1895                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1896                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1897                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1898                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1899                                                 " invalid queue number"
1900                                                 " for VMDQ RSS, allowed"
1901                                                 " value are 1, 2 or 4.");
1902                                         return -EINVAL;
1903                                 }
1904                         break;
1905                 case ETH_MQ_RX_VMDQ_ONLY:
1906                 case ETH_MQ_RX_NONE:
1907                         /* if nothing mq mode configure, use default scheme */
1908                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1909                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1910                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1911                         break;
1912                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1913                         /* SRIOV only works in VMDq enable mode */
1914                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1915                                         " wrong mq_mode rx %d.",
1916                                         dev_conf->rxmode.mq_mode);
1917                         return -EINVAL;
1918                 }
1919
1920                 switch (dev_conf->txmode.mq_mode) {
1921                 case ETH_MQ_TX_VMDQ_DCB:
1922                         /* DCB VMDQ in SRIOV mode, not implement yet */
1923                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1924                                         " unsupported VMDQ mq_mode tx %d.",
1925                                         dev_conf->txmode.mq_mode);
1926                         return -EINVAL;
1927                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1928                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1929                         break;
1930                 }
1931
1932                 /* check valid queue number */
1933                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1934                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1935                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1936                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1937                                         " must be less than or equal to %d.",
1938                                         nb_rx_q, nb_tx_q,
1939                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1940                         return -EINVAL;
1941                 }
1942         } else {
1943                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1944                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1945                                           " not supported.");
1946                         return -EINVAL;
1947                 }
1948                 /* check configuration for vmdb+dcb mode */
1949                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1950                         const struct rte_eth_vmdq_dcb_conf *conf;
1951
1952                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1953                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1954                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1955                                 return -EINVAL;
1956                         }
1957                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1958                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1959                                conf->nb_queue_pools == ETH_32_POOLS)) {
1960                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1961                                                 " nb_queue_pools must be %d or %d.",
1962                                                 ETH_16_POOLS, ETH_32_POOLS);
1963                                 return -EINVAL;
1964                         }
1965                 }
1966                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1967                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1968
1969                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1970                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1971                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1972                                 return -EINVAL;
1973                         }
1974                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1975                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1976                                conf->nb_queue_pools == ETH_32_POOLS)) {
1977                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1978                                                 " nb_queue_pools != %d and"
1979                                                 " nb_queue_pools != %d.",
1980                                                 ETH_16_POOLS, ETH_32_POOLS);
1981                                 return -EINVAL;
1982                         }
1983                 }
1984
1985                 /* For DCB mode check our configuration before we go further */
1986                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1987                         const struct rte_eth_dcb_rx_conf *conf;
1988
1989                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1990                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1991                                                  IXGBE_DCB_NB_QUEUES);
1992                                 return -EINVAL;
1993                         }
1994                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1995                         if (!(conf->nb_tcs == ETH_4_TCS ||
1996                                conf->nb_tcs == ETH_8_TCS)) {
1997                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1998                                                 " and nb_tcs != %d.",
1999                                                 ETH_4_TCS, ETH_8_TCS);
2000                                 return -EINVAL;
2001                         }
2002                 }
2003
2004                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2005                         const struct rte_eth_dcb_tx_conf *conf;
2006
2007                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2008                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2009                                                  IXGBE_DCB_NB_QUEUES);
2010                                 return -EINVAL;
2011                         }
2012                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2013                         if (!(conf->nb_tcs == ETH_4_TCS ||
2014                                conf->nb_tcs == ETH_8_TCS)) {
2015                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2016                                                 " and nb_tcs != %d.",
2017                                                 ETH_4_TCS, ETH_8_TCS);
2018                                 return -EINVAL;
2019                         }
2020                 }
2021
2022                 /*
2023                  * When DCB/VT is off, maximum number of queues changes,
2024                  * except for 82598EB, which remains constant.
2025                  */
2026                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2027                                 hw->mac.type != ixgbe_mac_82598EB) {
2028                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2029                                 PMD_INIT_LOG(ERR,
2030                                              "Neither VT nor DCB are enabled, "
2031                                              "nb_tx_q > %d.",
2032                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2033                                 return -EINVAL;
2034                         }
2035                 }
2036         }
2037         return 0;
2038 }
2039
2040 static int
2041 ixgbe_dev_configure(struct rte_eth_dev *dev)
2042 {
2043         struct ixgbe_interrupt *intr =
2044                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2045         struct ixgbe_adapter *adapter =
2046                 (struct ixgbe_adapter *)dev->data->dev_private;
2047         int ret;
2048
2049         PMD_INIT_FUNC_TRACE();
2050         /* multipe queue mode checking */
2051         ret  = ixgbe_check_mq_mode(dev);
2052         if (ret != 0) {
2053                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2054                             ret);
2055                 return ret;
2056         }
2057
2058         /* set flag to update link status after init */
2059         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2060
2061         /*
2062          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2063          * allocation or vector Rx preconditions we will reset it.
2064          */
2065         adapter->rx_bulk_alloc_allowed = true;
2066         adapter->rx_vec_allowed = true;
2067
2068         return 0;
2069 }
2070
2071 static void
2072 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2073 {
2074         struct ixgbe_hw *hw =
2075                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2076         struct ixgbe_interrupt *intr =
2077                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2078         uint32_t gpie;
2079
2080         /* only set up it on X550EM_X */
2081         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2082                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2083                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2084                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2085                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2086                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2087         }
2088 }
2089
2090 /*
2091  * Configure device link speed and setup link.
2092  * It returns 0 on success.
2093  */
2094 static int
2095 ixgbe_dev_start(struct rte_eth_dev *dev)
2096 {
2097         struct ixgbe_hw *hw =
2098                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099         struct ixgbe_vf_info *vfinfo =
2100                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2101         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2102         uint32_t intr_vector = 0;
2103         int err, link_up = 0, negotiate = 0;
2104         uint32_t speed = 0;
2105         int mask = 0;
2106         int status;
2107         uint16_t vf, idx;
2108         uint32_t *link_speeds;
2109
2110         PMD_INIT_FUNC_TRACE();
2111
2112         /* IXGBE devices don't support:
2113         *    - half duplex (checked afterwards for valid speeds)
2114         *    - fixed speed: TODO implement
2115         */
2116         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2117                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2118                              dev->data->port_id);
2119                 return -EINVAL;
2120         }
2121
2122         /* disable uio/vfio intr/eventfd mapping */
2123         rte_intr_disable(intr_handle);
2124
2125         /* stop adapter */
2126         hw->adapter_stopped = 0;
2127         ixgbe_stop_adapter(hw);
2128
2129         /* reinitialize adapter
2130          * this calls reset and start
2131          */
2132         status = ixgbe_pf_reset_hw(hw);
2133         if (status != 0)
2134                 return -1;
2135         hw->mac.ops.start_hw(hw);
2136         hw->mac.get_link_status = true;
2137
2138         /* configure PF module if SRIOV enabled */
2139         ixgbe_pf_host_configure(dev);
2140
2141         ixgbe_dev_phy_intr_setup(dev);
2142
2143         /* check and configure queue intr-vector mapping */
2144         if ((rte_intr_cap_multiple(intr_handle) ||
2145              !RTE_ETH_DEV_SRIOV(dev).active) &&
2146             dev->data->dev_conf.intr_conf.rxq != 0) {
2147                 intr_vector = dev->data->nb_rx_queues;
2148                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2149                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2150                                         IXGBE_MAX_INTR_QUEUE_NUM);
2151                         return -ENOTSUP;
2152                 }
2153                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2154                         return -1;
2155         }
2156
2157         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2158                 intr_handle->intr_vec =
2159                         rte_zmalloc("intr_vec",
2160                                     dev->data->nb_rx_queues * sizeof(int), 0);
2161                 if (intr_handle->intr_vec == NULL) {
2162                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2163                                      " intr_vec\n", dev->data->nb_rx_queues);
2164                         return -ENOMEM;
2165                 }
2166         }
2167
2168         /* confiugre msix for sleep until rx interrupt */
2169         ixgbe_configure_msix(dev);
2170
2171         /* initialize transmission unit */
2172         ixgbe_dev_tx_init(dev);
2173
2174         /* This can fail when allocating mbufs for descriptor rings */
2175         err = ixgbe_dev_rx_init(dev);
2176         if (err) {
2177                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2178                 goto error;
2179         }
2180
2181         err = ixgbe_dev_rxtx_start(dev);
2182         if (err < 0) {
2183                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2184                 goto error;
2185         }
2186
2187         /* Skip link setup if loopback mode is enabled for 82599. */
2188         if (hw->mac.type == ixgbe_mac_82599EB &&
2189                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2190                 goto skip_link_setup;
2191
2192         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2193                 err = hw->mac.ops.setup_sfp(hw);
2194                 if (err)
2195                         goto error;
2196         }
2197
2198         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2199                 /* Turn on the copper */
2200                 ixgbe_set_phy_power(hw, true);
2201         } else {
2202                 /* Turn on the laser */
2203                 ixgbe_enable_tx_laser(hw);
2204         }
2205
2206         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2207         if (err)
2208                 goto error;
2209         dev->data->dev_link.link_status = link_up;
2210
2211         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2212         if (err)
2213                 goto error;
2214
2215         link_speeds = &dev->data->dev_conf.link_speeds;
2216         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2217                         ETH_LINK_SPEED_10G)) {
2218                 PMD_INIT_LOG(ERR, "Invalid link setting");
2219                 goto error;
2220         }
2221
2222         speed = 0x0;
2223         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2224                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2225                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2226                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2227         } else {
2228                 if (*link_speeds & ETH_LINK_SPEED_10G)
2229                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2230                 if (*link_speeds & ETH_LINK_SPEED_1G)
2231                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2232                 if (*link_speeds & ETH_LINK_SPEED_100M)
2233                         speed |= IXGBE_LINK_SPEED_100_FULL;
2234         }
2235
2236         err = ixgbe_setup_link(hw, speed, link_up);
2237         if (err)
2238                 goto error;
2239
2240 skip_link_setup:
2241
2242         if (rte_intr_allow_others(intr_handle)) {
2243                 /* check if lsc interrupt is enabled */
2244                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2245                         ixgbe_dev_lsc_interrupt_setup(dev);
2246         } else {
2247                 rte_intr_callback_unregister(intr_handle,
2248                                              ixgbe_dev_interrupt_handler,
2249                                              (void *)dev);
2250                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2251                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2252                                      " no intr multiplex\n");
2253         }
2254
2255         /* check if rxq interrupt is enabled */
2256         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2257             rte_intr_dp_is_en(intr_handle))
2258                 ixgbe_dev_rxq_interrupt_setup(dev);
2259
2260         /* enable uio/vfio intr/eventfd mapping */
2261         rte_intr_enable(intr_handle);
2262
2263         /* resume enabled intr since hw reset */
2264         ixgbe_enable_intr(dev);
2265
2266         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2267                 ETH_VLAN_EXTEND_MASK;
2268         ixgbe_vlan_offload_set(dev, mask);
2269
2270         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2271                 /* Enable vlan filtering for VMDq */
2272                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2273         }
2274
2275         /* Configure DCB hw */
2276         ixgbe_configure_dcb(dev);
2277
2278         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2279                 err = ixgbe_fdir_configure(dev);
2280                 if (err)
2281                         goto error;
2282         }
2283
2284         /* Restore vf rate limit */
2285         if (vfinfo != NULL) {
2286                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2287                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2288                                 if (vfinfo[vf].tx_rate[idx] != 0)
2289                                         ixgbe_set_vf_rate_limit(dev, vf,
2290                                                 vfinfo[vf].tx_rate[idx],
2291                                                 1 << idx);
2292         }
2293
2294         ixgbe_restore_statistics_mapping(dev);
2295
2296         return 0;
2297
2298 error:
2299         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2300         ixgbe_dev_clear_queues(dev);
2301         return -EIO;
2302 }
2303
2304 /*
2305  * Stop device: disable rx and tx functions to allow for reconfiguring.
2306  */
2307 static void
2308 ixgbe_dev_stop(struct rte_eth_dev *dev)
2309 {
2310         struct rte_eth_link link;
2311         struct ixgbe_hw *hw =
2312                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2313         struct ixgbe_vf_info *vfinfo =
2314                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2315         struct ixgbe_filter_info *filter_info =
2316                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2317         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2318         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2319         int vf;
2320
2321         PMD_INIT_FUNC_TRACE();
2322
2323         /* disable interrupts */
2324         ixgbe_disable_intr(hw);
2325
2326         /* reset the NIC */
2327         ixgbe_pf_reset_hw(hw);
2328         hw->adapter_stopped = 0;
2329
2330         /* stop adapter */
2331         ixgbe_stop_adapter(hw);
2332
2333         for (vf = 0; vfinfo != NULL &&
2334                      vf < dev->pci_dev->max_vfs; vf++)
2335                 vfinfo[vf].clear_to_send = false;
2336
2337         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2338                 /* Turn off the copper */
2339                 ixgbe_set_phy_power(hw, false);
2340         } else {
2341                 /* Turn off the laser */
2342                 ixgbe_disable_tx_laser(hw);
2343         }
2344
2345         ixgbe_dev_clear_queues(dev);
2346
2347         /* Clear stored conf */
2348         dev->data->scattered_rx = 0;
2349         dev->data->lro = 0;
2350
2351         /* Clear recorded link status */
2352         memset(&link, 0, sizeof(link));
2353         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2354
2355         /* Remove all ntuple filters of the device */
2356         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2357              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2358                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2359                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2360                              p_5tuple, entries);
2361                 rte_free(p_5tuple);
2362         }
2363         memset(filter_info->fivetuple_mask, 0,
2364                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2365
2366         if (!rte_intr_allow_others(intr_handle))
2367                 /* resume to the default handler */
2368                 rte_intr_callback_register(intr_handle,
2369                                            ixgbe_dev_interrupt_handler,
2370                                            (void *)dev);
2371
2372         /* Clean datapath event and queue/vec mapping */
2373         rte_intr_efd_disable(intr_handle);
2374         if (intr_handle->intr_vec != NULL) {
2375                 rte_free(intr_handle->intr_vec);
2376                 intr_handle->intr_vec = NULL;
2377         }
2378 }
2379
2380 /*
2381  * Set device link up: enable tx.
2382  */
2383 static int
2384 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2385 {
2386         struct ixgbe_hw *hw =
2387                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2388         if (hw->mac.type == ixgbe_mac_82599EB) {
2389 #ifdef RTE_NIC_BYPASS
2390                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2391                         /* Not suported in bypass mode */
2392                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2393                                      "by device id 0x%x", hw->device_id);
2394                         return -ENOTSUP;
2395                 }
2396 #endif
2397         }
2398
2399         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2400                 /* Turn on the copper */
2401                 ixgbe_set_phy_power(hw, true);
2402         } else {
2403                 /* Turn on the laser */
2404                 ixgbe_enable_tx_laser(hw);
2405         }
2406
2407         return 0;
2408 }
2409
2410 /*
2411  * Set device link down: disable tx.
2412  */
2413 static int
2414 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2415 {
2416         struct ixgbe_hw *hw =
2417                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2418         if (hw->mac.type == ixgbe_mac_82599EB) {
2419 #ifdef RTE_NIC_BYPASS
2420                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2421                         /* Not suported in bypass mode */
2422                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2423                                      "by device id 0x%x", hw->device_id);
2424                         return -ENOTSUP;
2425                 }
2426 #endif
2427         }
2428
2429         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2430                 /* Turn off the copper */
2431                 ixgbe_set_phy_power(hw, false);
2432         } else {
2433                 /* Turn off the laser */
2434                 ixgbe_disable_tx_laser(hw);
2435         }
2436
2437         return 0;
2438 }
2439
2440 /*
2441  * Reest and stop device.
2442  */
2443 static void
2444 ixgbe_dev_close(struct rte_eth_dev *dev)
2445 {
2446         struct ixgbe_hw *hw =
2447                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2448
2449         PMD_INIT_FUNC_TRACE();
2450
2451         ixgbe_pf_reset_hw(hw);
2452
2453         ixgbe_dev_stop(dev);
2454         hw->adapter_stopped = 1;
2455
2456         ixgbe_dev_free_queues(dev);
2457
2458         ixgbe_disable_pcie_master(hw);
2459
2460         /* reprogram the RAR[0] in case user changed it. */
2461         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2462 }
2463
2464 static void
2465 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2466                            struct ixgbe_hw_stats *hw_stats,
2467                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2468                            uint64_t *total_qprc, uint64_t *total_qprdc)
2469 {
2470         uint32_t bprc, lxon, lxoff, total;
2471         uint32_t delta_gprc = 0;
2472         unsigned i;
2473         /* Workaround for RX byte count not including CRC bytes when CRC
2474 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2475          * is disabled.
2476 +        */
2477         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2478                         IXGBE_HLREG0_RXCRCSTRP);
2479
2480         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2481         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2482         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2483         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2484
2485         for (i = 0; i < 8; i++) {
2486                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2487
2488                 /* global total per queue */
2489                 hw_stats->mpc[i] += mp;
2490                 /* Running comprehensive total for stats display */
2491                 *total_missed_rx += hw_stats->mpc[i];
2492                 if (hw->mac.type == ixgbe_mac_82598EB) {
2493                         hw_stats->rnbc[i] +=
2494                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2495                         hw_stats->pxonrxc[i] +=
2496                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2497                         hw_stats->pxoffrxc[i] +=
2498                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2499                 } else {
2500                         hw_stats->pxonrxc[i] +=
2501                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2502                         hw_stats->pxoffrxc[i] +=
2503                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2504                         hw_stats->pxon2offc[i] +=
2505                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2506                 }
2507                 hw_stats->pxontxc[i] +=
2508                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2509                 hw_stats->pxofftxc[i] +=
2510                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2511         }
2512         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2513                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2514                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2515                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2516
2517                 delta_gprc += delta_qprc;
2518
2519                 hw_stats->qprc[i] += delta_qprc;
2520                 hw_stats->qptc[i] += delta_qptc;
2521
2522                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2523                 hw_stats->qbrc[i] +=
2524                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2525                 if (crc_strip == 0)
2526                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2527
2528                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2529                 hw_stats->qbtc[i] +=
2530                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2531
2532                 hw_stats->qprdc[i] += delta_qprdc;
2533                 *total_qprdc += hw_stats->qprdc[i];
2534
2535                 *total_qprc += hw_stats->qprc[i];
2536                 *total_qbrc += hw_stats->qbrc[i];
2537         }
2538         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2539         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2540         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2541
2542         /*
2543          * An errata states that gprc actually counts good + missed packets:
2544          * Workaround to set gprc to summated queue packet receives
2545          */
2546         hw_stats->gprc = *total_qprc;
2547
2548         if (hw->mac.type != ixgbe_mac_82598EB) {
2549                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2550                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2551                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2552                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2553                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2554                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2555                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2556                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2557         } else {
2558                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2559                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2560                 /* 82598 only has a counter in the high register */
2561                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2562                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2563                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2564         }
2565         uint64_t old_tpr = hw_stats->tpr;
2566
2567         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2568         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2569
2570         if (crc_strip == 0)
2571                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2572
2573         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2574         hw_stats->gptc += delta_gptc;
2575         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2576         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2577
2578         /*
2579          * Workaround: mprc hardware is incorrectly counting
2580          * broadcasts, so for now we subtract those.
2581          */
2582         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2583         hw_stats->bprc += bprc;
2584         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2585         if (hw->mac.type == ixgbe_mac_82598EB)
2586                 hw_stats->mprc -= bprc;
2587
2588         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2589         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2590         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2591         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2592         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2593         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2594
2595         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2596         hw_stats->lxontxc += lxon;
2597         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2598         hw_stats->lxofftxc += lxoff;
2599         total = lxon + lxoff;
2600
2601         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2602         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2603         hw_stats->gptc -= total;
2604         hw_stats->mptc -= total;
2605         hw_stats->ptc64 -= total;
2606         hw_stats->gotc -= total * ETHER_MIN_LEN;
2607
2608         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2609         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2610         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2611         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2612         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2613         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2614         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2615         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2616         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2617         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2618         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2619         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2620         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2621         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2622         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2623         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2624         /* Only read FCOE on 82599 */
2625         if (hw->mac.type != ixgbe_mac_82598EB) {
2626                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2627                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2628                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2629                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2630                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2631         }
2632
2633         /* Flow Director Stats registers */
2634         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2635         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2636 }
2637
2638 /*
2639  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2640  */
2641 static void
2642 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2643 {
2644         struct ixgbe_hw *hw =
2645                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2646         struct ixgbe_hw_stats *hw_stats =
2647                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2648         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2649         unsigned i;
2650
2651         total_missed_rx = 0;
2652         total_qbrc = 0;
2653         total_qprc = 0;
2654         total_qprdc = 0;
2655
2656         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2657                         &total_qprc, &total_qprdc);
2658
2659         if (stats == NULL)
2660                 return;
2661
2662         /* Fill out the rte_eth_stats statistics structure */
2663         stats->ipackets = total_qprc;
2664         stats->ibytes = total_qbrc;
2665         stats->opackets = hw_stats->gptc;
2666         stats->obytes = hw_stats->gotc;
2667
2668         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2669                 stats->q_ipackets[i] = hw_stats->qprc[i];
2670                 stats->q_opackets[i] = hw_stats->qptc[i];
2671                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2672                 stats->q_obytes[i] = hw_stats->qbtc[i];
2673                 stats->q_errors[i] = hw_stats->qprdc[i];
2674         }
2675
2676         /* Rx Errors */
2677         stats->imissed  = total_missed_rx;
2678         stats->ierrors  = hw_stats->crcerrs +
2679                           hw_stats->mspdc +
2680                           hw_stats->rlec +
2681                           hw_stats->ruc +
2682                           hw_stats->roc +
2683                           hw_stats->illerrc +
2684                           hw_stats->errbc +
2685                           hw_stats->rfc +
2686                           hw_stats->fccrc +
2687                           hw_stats->fclast;
2688
2689         /* Tx Errors */
2690         stats->oerrors  = 0;
2691 }
2692
2693 static void
2694 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2695 {
2696         struct ixgbe_hw_stats *stats =
2697                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2698
2699         /* HW registers are cleared on read */
2700         ixgbe_dev_stats_get(dev, NULL);
2701
2702         /* Reset software totals */
2703         memset(stats, 0, sizeof(*stats));
2704 }
2705
2706 /* This function calculates the number of xstats based on the current config */
2707 static unsigned
2708 ixgbe_xstats_calc_num(void) {
2709         return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2710                 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2711 }
2712
2713 static int
2714 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2715                                          unsigned n)
2716 {
2717         struct ixgbe_hw *hw =
2718                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2719         struct ixgbe_hw_stats *hw_stats =
2720                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2721         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2722         unsigned i, stat, count = 0;
2723
2724         count = ixgbe_xstats_calc_num();
2725
2726         if (n < count)
2727                 return count;
2728
2729         total_missed_rx = 0;
2730         total_qbrc = 0;
2731         total_qprc = 0;
2732         total_qprdc = 0;
2733
2734         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2735                                    &total_qprc, &total_qprdc);
2736
2737         /* If this is a reset xstats is NULL, and we have cleared the
2738          * registers by reading them.
2739          */
2740         if (!xstats)
2741                 return 0;
2742
2743         /* Extended stats from ixgbe_hw_stats */
2744         count = 0;
2745         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2746                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2747                          rte_ixgbe_stats_strings[i].name);
2748                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2749                                 rte_ixgbe_stats_strings[i].offset);
2750                 count++;
2751         }
2752
2753         /* RX Priority Stats */
2754         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2755                 for (i = 0; i < 8; i++) {
2756                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2757                                  "rx_priority%u_%s", i,
2758                                  rte_ixgbe_rxq_strings[stat].name);
2759                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2760                                         rte_ixgbe_rxq_strings[stat].offset +
2761                                         (sizeof(uint64_t) * i));
2762                         count++;
2763                 }
2764         }
2765
2766         /* TX Priority Stats */
2767         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2768                 for (i = 0; i < 8; i++) {
2769                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2770                                  "tx_priority%u_%s", i,
2771                                  rte_ixgbe_txq_strings[stat].name);
2772                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2773                                         rte_ixgbe_txq_strings[stat].offset +
2774                                         (sizeof(uint64_t) * i));
2775                         count++;
2776                 }
2777         }
2778
2779         return count;
2780 }
2781
2782 static void
2783 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2784 {
2785         struct ixgbe_hw_stats *stats =
2786                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2787
2788         unsigned count = ixgbe_xstats_calc_num();
2789
2790         /* HW registers are cleared on read */
2791         ixgbe_dev_xstats_get(dev, NULL, count);
2792
2793         /* Reset software totals */
2794         memset(stats, 0, sizeof(*stats));
2795 }
2796
2797 static void
2798 ixgbevf_update_stats(struct rte_eth_dev *dev)
2799 {
2800         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2801         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2802                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2803
2804         /* Good Rx packet, include VF loopback */
2805         UPDATE_VF_STAT(IXGBE_VFGPRC,
2806             hw_stats->last_vfgprc, hw_stats->vfgprc);
2807
2808         /* Good Rx octets, include VF loopback */
2809         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2810             hw_stats->last_vfgorc, hw_stats->vfgorc);
2811
2812         /* Good Tx packet, include VF loopback */
2813         UPDATE_VF_STAT(IXGBE_VFGPTC,
2814             hw_stats->last_vfgptc, hw_stats->vfgptc);
2815
2816         /* Good Tx octets, include VF loopback */
2817         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2818             hw_stats->last_vfgotc, hw_stats->vfgotc);
2819
2820         /* Rx Multicst Packet */
2821         UPDATE_VF_STAT(IXGBE_VFMPRC,
2822             hw_stats->last_vfmprc, hw_stats->vfmprc);
2823 }
2824
2825 static int
2826 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2827                        unsigned n)
2828 {
2829         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2830                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2831         unsigned i;
2832
2833         if (n < IXGBEVF_NB_XSTATS)
2834                 return IXGBEVF_NB_XSTATS;
2835
2836         ixgbevf_update_stats(dev);
2837
2838         if (!xstats)
2839                 return 0;
2840
2841         /* Extended stats */
2842         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2843                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2844                          "%s", rte_ixgbevf_stats_strings[i].name);
2845                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2846                         rte_ixgbevf_stats_strings[i].offset);
2847         }
2848
2849         return IXGBEVF_NB_XSTATS;
2850 }
2851
2852 static void
2853 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2854 {
2855         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2856                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2857
2858         ixgbevf_update_stats(dev);
2859
2860         if (stats == NULL)
2861                 return;
2862
2863         stats->ipackets = hw_stats->vfgprc;
2864         stats->ibytes = hw_stats->vfgorc;
2865         stats->opackets = hw_stats->vfgptc;
2866         stats->obytes = hw_stats->vfgotc;
2867 }
2868
2869 static void
2870 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2871 {
2872         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2873                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2874
2875         /* Sync HW register to the last stats */
2876         ixgbevf_dev_stats_get(dev, NULL);
2877
2878         /* reset HW current stats*/
2879         hw_stats->vfgprc = 0;
2880         hw_stats->vfgorc = 0;
2881         hw_stats->vfgptc = 0;
2882         hw_stats->vfgotc = 0;
2883 }
2884
2885 static void
2886 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2887 {
2888         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2889         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2890
2891         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2892         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2893         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
2894                 /*
2895                  * When DCB/VT is off, maximum number of queues changes,
2896                  * except for 82598EB, which remains constant.
2897                  */
2898                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2899                                 hw->mac.type != ixgbe_mac_82598EB)
2900                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
2901         }
2902         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2903         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2904         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2905         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2906         dev_info->max_vfs = dev->pci_dev->max_vfs;
2907         if (hw->mac.type == ixgbe_mac_82598EB)
2908                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2909         else
2910                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2911         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2912         dev_info->rx_offload_capa =
2913                 DEV_RX_OFFLOAD_VLAN_STRIP |
2914                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2915                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2916                 DEV_RX_OFFLOAD_TCP_CKSUM;
2917
2918         /*
2919          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2920          * mode.
2921          */
2922         if ((hw->mac.type == ixgbe_mac_82599EB ||
2923              hw->mac.type == ixgbe_mac_X540) &&
2924             !RTE_ETH_DEV_SRIOV(dev).active)
2925                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2926
2927         if (hw->mac.type == ixgbe_mac_X550 ||
2928             hw->mac.type == ixgbe_mac_X550EM_x ||
2929             hw->mac.type == ixgbe_mac_X550EM_a)
2930                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2931
2932         dev_info->tx_offload_capa =
2933                 DEV_TX_OFFLOAD_VLAN_INSERT |
2934                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2935                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2936                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2937                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2938                 DEV_TX_OFFLOAD_TCP_TSO;
2939
2940         if (hw->mac.type == ixgbe_mac_X550 ||
2941             hw->mac.type == ixgbe_mac_X550EM_x ||
2942             hw->mac.type == ixgbe_mac_X550EM_a)
2943                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2944
2945         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2946                 .rx_thresh = {
2947                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2948                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2949                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2950                 },
2951                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2952                 .rx_drop_en = 0,
2953         };
2954
2955         dev_info->default_txconf = (struct rte_eth_txconf) {
2956                 .tx_thresh = {
2957                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2958                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2959                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2960                 },
2961                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2962                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2963                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2964                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2965         };
2966
2967         dev_info->rx_desc_lim = rx_desc_lim;
2968         dev_info->tx_desc_lim = tx_desc_lim;
2969
2970         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2971         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2972         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2973
2974         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2975         if (hw->mac.type == ixgbe_mac_X540 ||
2976             hw->mac.type == ixgbe_mac_X540_vf ||
2977             hw->mac.type == ixgbe_mac_X550 ||
2978             hw->mac.type == ixgbe_mac_X550_vf) {
2979                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2980         }
2981 }
2982
2983 static const uint32_t *
2984 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2985 {
2986         static const uint32_t ptypes[] = {
2987                 /* For non-vec functions,
2988                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
2989                  * for vec functions,
2990                  * refers to _recv_raw_pkts_vec().
2991                  */
2992                 RTE_PTYPE_L2_ETHER,
2993                 RTE_PTYPE_L3_IPV4,
2994                 RTE_PTYPE_L3_IPV4_EXT,
2995                 RTE_PTYPE_L3_IPV6,
2996                 RTE_PTYPE_L3_IPV6_EXT,
2997                 RTE_PTYPE_L4_SCTP,
2998                 RTE_PTYPE_L4_TCP,
2999                 RTE_PTYPE_L4_UDP,
3000                 RTE_PTYPE_TUNNEL_IP,
3001                 RTE_PTYPE_INNER_L3_IPV6,
3002                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3003                 RTE_PTYPE_INNER_L4_TCP,
3004                 RTE_PTYPE_INNER_L4_UDP,
3005                 RTE_PTYPE_UNKNOWN
3006         };
3007
3008         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3009             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3010             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3011             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3012                 return ptypes;
3013         return NULL;
3014 }
3015
3016 static void
3017 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3018                      struct rte_eth_dev_info *dev_info)
3019 {
3020         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3021
3022         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3023         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3024         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3025         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3026         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3027         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3028         dev_info->max_vfs = dev->pci_dev->max_vfs;
3029         if (hw->mac.type == ixgbe_mac_82598EB)
3030                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3031         else
3032                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3033         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3034                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3035                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3036                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3037         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3038                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3039                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3040                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3041                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3042                                 DEV_TX_OFFLOAD_TCP_TSO;
3043
3044         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3045                 .rx_thresh = {
3046                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3047                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3048                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3049                 },
3050                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3051                 .rx_drop_en = 0,
3052         };
3053
3054         dev_info->default_txconf = (struct rte_eth_txconf) {
3055                 .tx_thresh = {
3056                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3057                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3058                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3059                 },
3060                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3061                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3062                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3063                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3064         };
3065
3066         dev_info->rx_desc_lim = rx_desc_lim;
3067         dev_info->tx_desc_lim = tx_desc_lim;
3068 }
3069
3070 /* return 0 means link status changed, -1 means not changed */
3071 static int
3072 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3073 {
3074         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3075         struct rte_eth_link link, old;
3076         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3077         int link_up;
3078         int diag;
3079
3080         link.link_status = ETH_LINK_DOWN;
3081         link.link_speed = 0;
3082         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3083         memset(&old, 0, sizeof(old));
3084         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3085
3086         hw->mac.get_link_status = true;
3087
3088         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3089         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3090                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3091         else
3092                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3093
3094         if (diag != 0) {
3095                 link.link_speed = ETH_SPEED_NUM_100M;
3096                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3097                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3098                 if (link.link_status == old.link_status)
3099                         return -1;
3100                 return 0;
3101         }
3102
3103         if (link_up == 0) {
3104                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3105                 if (link.link_status == old.link_status)
3106                         return -1;
3107                 return 0;
3108         }
3109         link.link_status = ETH_LINK_UP;
3110         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3111
3112         switch (link_speed) {
3113         default:
3114         case IXGBE_LINK_SPEED_UNKNOWN:
3115                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3116                 link.link_speed = ETH_SPEED_NUM_100M;
3117                 break;
3118
3119         case IXGBE_LINK_SPEED_100_FULL:
3120                 link.link_speed = ETH_SPEED_NUM_100M;
3121                 break;
3122
3123         case IXGBE_LINK_SPEED_1GB_FULL:
3124                 link.link_speed = ETH_SPEED_NUM_1G;
3125                 break;
3126
3127         case IXGBE_LINK_SPEED_10GB_FULL:
3128                 link.link_speed = ETH_SPEED_NUM_10G;
3129                 break;
3130         }
3131         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3132
3133         if (link.link_status == old.link_status)
3134                 return -1;
3135
3136         return 0;
3137 }
3138
3139 static void
3140 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3141 {
3142         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3143         uint32_t fctrl;
3144
3145         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3146         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3147         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3148 }
3149
3150 static void
3151 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3152 {
3153         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3154         uint32_t fctrl;
3155
3156         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3157         fctrl &= (~IXGBE_FCTRL_UPE);
3158         if (dev->data->all_multicast == 1)
3159                 fctrl |= IXGBE_FCTRL_MPE;
3160         else
3161                 fctrl &= (~IXGBE_FCTRL_MPE);
3162         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3163 }
3164
3165 static void
3166 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3167 {
3168         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3169         uint32_t fctrl;
3170
3171         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3172         fctrl |= IXGBE_FCTRL_MPE;
3173         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3174 }
3175
3176 static void
3177 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3178 {
3179         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3180         uint32_t fctrl;
3181
3182         if (dev->data->promiscuous == 1)
3183                 return; /* must remain in all_multicast mode */
3184
3185         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3186         fctrl &= (~IXGBE_FCTRL_MPE);
3187         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3188 }
3189
3190 /**
3191  * It clears the interrupt causes and enables the interrupt.
3192  * It will be called once only during nic initialized.
3193  *
3194  * @param dev
3195  *  Pointer to struct rte_eth_dev.
3196  *
3197  * @return
3198  *  - On success, zero.
3199  *  - On failure, a negative value.
3200  */
3201 static int
3202 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3203 {
3204         struct ixgbe_interrupt *intr =
3205                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3206
3207         ixgbe_dev_link_status_print(dev);
3208         intr->mask |= IXGBE_EICR_LSC;
3209
3210         return 0;
3211 }
3212
3213 /**
3214  * It clears the interrupt causes and enables the interrupt.
3215  * It will be called once only during nic initialized.
3216  *
3217  * @param dev
3218  *  Pointer to struct rte_eth_dev.
3219  *
3220  * @return
3221  *  - On success, zero.
3222  *  - On failure, a negative value.
3223  */
3224 static int
3225 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3226 {
3227         struct ixgbe_interrupt *intr =
3228                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3229
3230         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3231
3232         return 0;
3233 }
3234
3235 /*
3236  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3237  *
3238  * @param dev
3239  *  Pointer to struct rte_eth_dev.
3240  *
3241  * @return
3242  *  - On success, zero.
3243  *  - On failure, a negative value.
3244  */
3245 static int
3246 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3247 {
3248         uint32_t eicr;
3249         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3250         struct ixgbe_interrupt *intr =
3251                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3252
3253         /* clear all cause mask */
3254         ixgbe_disable_intr(hw);
3255
3256         /* read-on-clear nic registers here */
3257         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3258         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3259
3260         intr->flags = 0;
3261
3262         /* set flag for async link update */
3263         if (eicr & IXGBE_EICR_LSC)
3264                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3265
3266         if (eicr & IXGBE_EICR_MAILBOX)
3267                 intr->flags |= IXGBE_FLAG_MAILBOX;
3268
3269         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3270             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3271             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3272                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3273
3274         return 0;
3275 }
3276
3277 /**
3278  * It gets and then prints the link status.
3279  *
3280  * @param dev
3281  *  Pointer to struct rte_eth_dev.
3282  *
3283  * @return
3284  *  - On success, zero.
3285  *  - On failure, a negative value.
3286  */
3287 static void
3288 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3289 {
3290         struct rte_eth_link link;
3291
3292         memset(&link, 0, sizeof(link));
3293         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3294         if (link.link_status) {
3295                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3296                                         (int)(dev->data->port_id),
3297                                         (unsigned)link.link_speed,
3298                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3299                                         "full-duplex" : "half-duplex");
3300         } else {
3301                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3302                                 (int)(dev->data->port_id));
3303         }
3304         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3305                                 dev->pci_dev->addr.domain,
3306                                 dev->pci_dev->addr.bus,
3307                                 dev->pci_dev->addr.devid,
3308                                 dev->pci_dev->addr.function);
3309 }
3310
3311 /*
3312  * It executes link_update after knowing an interrupt occurred.
3313  *
3314  * @param dev
3315  *  Pointer to struct rte_eth_dev.
3316  *
3317  * @return
3318  *  - On success, zero.
3319  *  - On failure, a negative value.
3320  */
3321 static int
3322 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3323 {
3324         struct ixgbe_interrupt *intr =
3325                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3326         int64_t timeout;
3327         struct rte_eth_link link;
3328         int intr_enable_delay = false;
3329         struct ixgbe_hw *hw =
3330                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3331
3332         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3333
3334         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3335                 ixgbe_pf_mbx_process(dev);
3336                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3337         }
3338
3339         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3340                 ixgbe_handle_lasi(hw);
3341                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3342         }
3343
3344         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3345                 /* get the link status before link update, for predicting later */
3346                 memset(&link, 0, sizeof(link));
3347                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3348
3349                 ixgbe_dev_link_update(dev, 0);
3350
3351                 /* likely to up */
3352                 if (!link.link_status)
3353                         /* handle it 1 sec later, wait it being stable */
3354                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3355                 /* likely to down */
3356                 else
3357                         /* handle it 4 sec later, wait it being stable */
3358                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3359
3360                 ixgbe_dev_link_status_print(dev);
3361
3362                 intr_enable_delay = true;
3363         }
3364
3365         if (intr_enable_delay) {
3366                 if (rte_eal_alarm_set(timeout * 1000,
3367                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3368                         PMD_DRV_LOG(ERR, "Error setting alarm");
3369         } else {
3370                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3371                 ixgbe_enable_intr(dev);
3372                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3373         }
3374
3375
3376         return 0;
3377 }
3378
3379 /**
3380  * Interrupt handler which shall be registered for alarm callback for delayed
3381  * handling specific interrupt to wait for the stable nic state. As the
3382  * NIC interrupt state is not stable for ixgbe after link is just down,
3383  * it needs to wait 4 seconds to get the stable status.
3384  *
3385  * @param handle
3386  *  Pointer to interrupt handle.
3387  * @param param
3388  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3389  *
3390  * @return
3391  *  void
3392  */
3393 static void
3394 ixgbe_dev_interrupt_delayed_handler(void *param)
3395 {
3396         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3397         struct ixgbe_interrupt *intr =
3398                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3399         struct ixgbe_hw *hw =
3400                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3401         uint32_t eicr;
3402
3403         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3404         if (eicr & IXGBE_EICR_MAILBOX)
3405                 ixgbe_pf_mbx_process(dev);
3406
3407         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3408                 ixgbe_handle_lasi(hw);
3409                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3410         }
3411
3412         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3413                 ixgbe_dev_link_update(dev, 0);
3414                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3415                 ixgbe_dev_link_status_print(dev);
3416                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3417         }
3418
3419         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3420         ixgbe_enable_intr(dev);
3421         rte_intr_enable(&(dev->pci_dev->intr_handle));
3422 }
3423
3424 /**
3425  * Interrupt handler triggered by NIC  for handling
3426  * specific interrupt.
3427  *
3428  * @param handle
3429  *  Pointer to interrupt handle.
3430  * @param param
3431  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3432  *
3433  * @return
3434  *  void
3435  */
3436 static void
3437 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3438                             void *param)
3439 {
3440         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3441
3442         ixgbe_dev_interrupt_get_status(dev);
3443         ixgbe_dev_interrupt_action(dev);
3444 }
3445
3446 static int
3447 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3448 {
3449         struct ixgbe_hw *hw;
3450
3451         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3452         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3453 }
3454
3455 static int
3456 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3457 {
3458         struct ixgbe_hw *hw;
3459
3460         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3461         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3462 }
3463
3464 static int
3465 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3466 {
3467         struct ixgbe_hw *hw;
3468         uint32_t mflcn_reg;
3469         uint32_t fccfg_reg;
3470         int rx_pause;
3471         int tx_pause;
3472
3473         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3474
3475         fc_conf->pause_time = hw->fc.pause_time;
3476         fc_conf->high_water = hw->fc.high_water[0];
3477         fc_conf->low_water = hw->fc.low_water[0];
3478         fc_conf->send_xon = hw->fc.send_xon;
3479         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3480
3481         /*
3482          * Return rx_pause status according to actual setting of
3483          * MFLCN register.
3484          */
3485         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3486         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3487                 rx_pause = 1;
3488         else
3489                 rx_pause = 0;
3490
3491         /*
3492          * Return tx_pause status according to actual setting of
3493          * FCCFG register.
3494          */
3495         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3496         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3497                 tx_pause = 1;
3498         else
3499                 tx_pause = 0;
3500
3501         if (rx_pause && tx_pause)
3502                 fc_conf->mode = RTE_FC_FULL;
3503         else if (rx_pause)
3504                 fc_conf->mode = RTE_FC_RX_PAUSE;
3505         else if (tx_pause)
3506                 fc_conf->mode = RTE_FC_TX_PAUSE;
3507         else
3508                 fc_conf->mode = RTE_FC_NONE;
3509
3510         return 0;
3511 }
3512
3513 static int
3514 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3515 {
3516         struct ixgbe_hw *hw;
3517         int err;
3518         uint32_t rx_buf_size;
3519         uint32_t max_high_water;
3520         uint32_t mflcn;
3521         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3522                 ixgbe_fc_none,
3523                 ixgbe_fc_rx_pause,
3524                 ixgbe_fc_tx_pause,
3525                 ixgbe_fc_full
3526         };
3527
3528         PMD_INIT_FUNC_TRACE();
3529
3530         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3531         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3532         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3533
3534         /*
3535          * At least reserve one Ethernet frame for watermark
3536          * high_water/low_water in kilo bytes for ixgbe
3537          */
3538         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3539         if ((fc_conf->high_water > max_high_water) ||
3540                 (fc_conf->high_water < fc_conf->low_water)) {
3541                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3542                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3543                 return -EINVAL;
3544         }
3545
3546         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3547         hw->fc.pause_time     = fc_conf->pause_time;
3548         hw->fc.high_water[0]  = fc_conf->high_water;
3549         hw->fc.low_water[0]   = fc_conf->low_water;
3550         hw->fc.send_xon       = fc_conf->send_xon;
3551         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3552
3553         err = ixgbe_fc_enable(hw);
3554
3555         /* Not negotiated is not an error case */
3556         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3557
3558                 /* check if we want to forward MAC frames - driver doesn't have native
3559                  * capability to do that, so we'll write the registers ourselves */
3560
3561                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3562
3563                 /* set or clear MFLCN.PMCF bit depending on configuration */
3564                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3565                         mflcn |= IXGBE_MFLCN_PMCF;
3566                 else
3567                         mflcn &= ~IXGBE_MFLCN_PMCF;
3568
3569                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3570                 IXGBE_WRITE_FLUSH(hw);
3571
3572                 return 0;
3573         }
3574
3575         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3576         return -EIO;
3577 }
3578
3579 /**
3580  *  ixgbe_pfc_enable_generic - Enable flow control
3581  *  @hw: pointer to hardware structure
3582  *  @tc_num: traffic class number
3583  *  Enable flow control according to the current settings.
3584  */
3585 static int
3586 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3587 {
3588         int ret_val = 0;
3589         uint32_t mflcn_reg, fccfg_reg;
3590         uint32_t reg;
3591         uint32_t fcrtl, fcrth;
3592         uint8_t i;
3593         uint8_t nb_rx_en;
3594
3595         /* Validate the water mark configuration */
3596         if (!hw->fc.pause_time) {
3597                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3598                 goto out;
3599         }
3600
3601         /* Low water mark of zero causes XOFF floods */
3602         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3603                  /* High/Low water can not be 0 */
3604                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3605                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3606                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3607                         goto out;
3608                 }
3609
3610                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3611                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3612                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3613                         goto out;
3614                 }
3615         }
3616         /* Negotiate the fc mode to use */
3617         ixgbe_fc_autoneg(hw);
3618
3619         /* Disable any previous flow control settings */
3620         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3621         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3622
3623         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3624         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3625
3626         switch (hw->fc.current_mode) {
3627         case ixgbe_fc_none:
3628                 /*
3629                  * If the count of enabled RX Priority Flow control >1,
3630                  * and the TX pause can not be disabled
3631                  */
3632                 nb_rx_en = 0;
3633                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3634                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3635                         if (reg & IXGBE_FCRTH_FCEN)
3636                                 nb_rx_en++;
3637                 }
3638                 if (nb_rx_en > 1)
3639                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3640                 break;
3641         case ixgbe_fc_rx_pause:
3642                 /*
3643                  * Rx Flow control is enabled and Tx Flow control is
3644                  * disabled by software override. Since there really
3645                  * isn't a way to advertise that we are capable of RX
3646                  * Pause ONLY, we will advertise that we support both
3647                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3648                  * disable the adapter's ability to send PAUSE frames.
3649                  */
3650                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3651                 /*
3652                  * If the count of enabled RX Priority Flow control >1,
3653                  * and the TX pause can not be disabled
3654                  */
3655                 nb_rx_en = 0;
3656                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3657                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3658                         if (reg & IXGBE_FCRTH_FCEN)
3659                                 nb_rx_en++;
3660                 }
3661                 if (nb_rx_en > 1)
3662                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3663                 break;
3664         case ixgbe_fc_tx_pause:
3665                 /*
3666                  * Tx Flow control is enabled, and Rx Flow control is
3667                  * disabled by software override.
3668                  */
3669                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3670                 break;
3671         case ixgbe_fc_full:
3672                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3673                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3674                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3675                 break;
3676         default:
3677                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3678                 ret_val = IXGBE_ERR_CONFIG;
3679                 goto out;
3680         }
3681
3682         /* Set 802.3x based flow control settings. */
3683         mflcn_reg |= IXGBE_MFLCN_DPF;
3684         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3685         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3686
3687         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3688         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3689                 hw->fc.high_water[tc_num]) {
3690                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3691                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3692                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3693         } else {
3694                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3695                 /*
3696                  * In order to prevent Tx hangs when the internal Tx
3697                  * switch is enabled we must set the high water mark
3698                  * to the maximum FCRTH value.  This allows the Tx
3699                  * switch to function even under heavy Rx workloads.
3700                  */
3701                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3702         }
3703         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3704
3705         /* Configure pause time (2 TCs per register) */
3706         reg = hw->fc.pause_time * 0x00010001;
3707         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3708                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3709
3710         /* Configure flow control refresh threshold value */
3711         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3712
3713 out:
3714         return ret_val;
3715 }
3716
3717 static int
3718 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3719 {
3720         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3721         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3722
3723         if (hw->mac.type != ixgbe_mac_82598EB) {
3724                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
3725         }
3726         return ret_val;
3727 }
3728
3729 static int
3730 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3731 {
3732         int err;
3733         uint32_t rx_buf_size;
3734         uint32_t max_high_water;
3735         uint8_t tc_num;
3736         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3737         struct ixgbe_hw *hw =
3738                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3739         struct ixgbe_dcb_config *dcb_config =
3740                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3741
3742         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3743                 ixgbe_fc_none,
3744                 ixgbe_fc_rx_pause,
3745                 ixgbe_fc_tx_pause,
3746                 ixgbe_fc_full
3747         };
3748
3749         PMD_INIT_FUNC_TRACE();
3750
3751         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3752         tc_num = map[pfc_conf->priority];
3753         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3754         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3755         /*
3756          * At least reserve one Ethernet frame for watermark
3757          * high_water/low_water in kilo bytes for ixgbe
3758          */
3759         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3760         if ((pfc_conf->fc.high_water > max_high_water) ||
3761             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3762                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3763                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3764                 return -EINVAL;
3765         }
3766
3767         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3768         hw->fc.pause_time = pfc_conf->fc.pause_time;
3769         hw->fc.send_xon = pfc_conf->fc.send_xon;
3770         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3771         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3772
3773         err = ixgbe_dcb_pfc_enable(dev, tc_num);
3774
3775         /* Not negotiated is not an error case */
3776         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3777                 return 0;
3778
3779         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3780         return -EIO;
3781 }
3782
3783 static int
3784 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3785                           struct rte_eth_rss_reta_entry64 *reta_conf,
3786                           uint16_t reta_size)
3787 {
3788         uint16_t i, sp_reta_size;
3789         uint8_t j, mask;
3790         uint32_t reta, r;
3791         uint16_t idx, shift;
3792         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3793         uint32_t reta_reg;
3794
3795         PMD_INIT_FUNC_TRACE();
3796
3797         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3798                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3799                         "NIC.");
3800                 return -ENOTSUP;
3801         }
3802
3803         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3804         if (reta_size != sp_reta_size) {
3805                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3806                         "(%d) doesn't match the number hardware can supported "
3807                         "(%d)\n", reta_size, sp_reta_size);
3808                 return -EINVAL;
3809         }
3810
3811         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3812                 idx = i / RTE_RETA_GROUP_SIZE;
3813                 shift = i % RTE_RETA_GROUP_SIZE;
3814                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3815                                                 IXGBE_4_BIT_MASK);
3816                 if (!mask)
3817                         continue;
3818                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3819                 if (mask == IXGBE_4_BIT_MASK)
3820                         r = 0;
3821                 else
3822                         r = IXGBE_READ_REG(hw, reta_reg);
3823                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3824                         if (mask & (0x1 << j))
3825                                 reta |= reta_conf[idx].reta[shift + j] <<
3826                                                         (CHAR_BIT * j);
3827                         else
3828                                 reta |= r & (IXGBE_8_BIT_MASK <<
3829                                                 (CHAR_BIT * j));
3830                 }
3831                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3832         }
3833
3834         return 0;
3835 }
3836
3837 static int
3838 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3839                          struct rte_eth_rss_reta_entry64 *reta_conf,
3840                          uint16_t reta_size)
3841 {
3842         uint16_t i, sp_reta_size;
3843         uint8_t j, mask;
3844         uint32_t reta;
3845         uint16_t idx, shift;
3846         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3847         uint32_t reta_reg;
3848
3849         PMD_INIT_FUNC_TRACE();
3850         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3851         if (reta_size != sp_reta_size) {
3852                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3853                         "(%d) doesn't match the number hardware can supported "
3854                         "(%d)\n", reta_size, sp_reta_size);
3855                 return -EINVAL;
3856         }
3857
3858         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3859                 idx = i / RTE_RETA_GROUP_SIZE;
3860                 shift = i % RTE_RETA_GROUP_SIZE;
3861                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3862                                                 IXGBE_4_BIT_MASK);
3863                 if (!mask)
3864                         continue;
3865
3866                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3867                 reta = IXGBE_READ_REG(hw, reta_reg);
3868                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3869                         if (mask & (0x1 << j))
3870                                 reta_conf[idx].reta[shift + j] =
3871                                         ((reta >> (CHAR_BIT * j)) &
3872                                                 IXGBE_8_BIT_MASK);
3873                 }
3874         }
3875
3876         return 0;
3877 }
3878
3879 static void
3880 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3881                                 uint32_t index, uint32_t pool)
3882 {
3883         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3884         uint32_t enable_addr = 1;
3885
3886         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3887 }
3888
3889 static void
3890 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3891 {
3892         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3893
3894         ixgbe_clear_rar(hw, index);
3895 }
3896
3897 static void
3898 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3899 {
3900         ixgbe_remove_rar(dev, 0);
3901
3902         ixgbe_add_rar(dev, addr, 0, 0);
3903 }
3904
3905 static int
3906 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3907 {
3908         uint32_t hlreg0;
3909         uint32_t maxfrs;
3910         struct ixgbe_hw *hw;
3911         struct rte_eth_dev_info dev_info;
3912         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3913
3914         ixgbe_dev_info_get(dev, &dev_info);
3915
3916         /* check that mtu is within the allowed range */
3917         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3918                 return -EINVAL;
3919
3920         /* refuse mtu that requires the support of scattered packets when this
3921          * feature has not been enabled before.
3922          */
3923         if (!dev->data->scattered_rx &&
3924             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3925              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3926                 return -EINVAL;
3927
3928         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3929         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3930
3931         /* switch to jumbo mode if needed */
3932         if (frame_size > ETHER_MAX_LEN) {
3933                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3934                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3935         } else {
3936                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3937                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3938         }
3939         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3940
3941         /* update max frame size */
3942         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3943
3944         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3945         maxfrs &= 0x0000FFFF;
3946         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3947         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3948
3949         return 0;
3950 }
3951
3952 /*
3953  * Virtual Function operations
3954  */
3955 static void
3956 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3957 {
3958         PMD_INIT_FUNC_TRACE();
3959
3960         /* Clear interrupt mask to stop from interrupts being generated */
3961         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3962
3963         IXGBE_WRITE_FLUSH(hw);
3964 }
3965
3966 static void
3967 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3968 {
3969         PMD_INIT_FUNC_TRACE();
3970
3971         /* VF enable interrupt autoclean */
3972         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3973         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3974         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3975
3976         IXGBE_WRITE_FLUSH(hw);
3977 }
3978
3979 static int
3980 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3981 {
3982         struct rte_eth_conf *conf = &dev->data->dev_conf;
3983         struct ixgbe_adapter *adapter =
3984                         (struct ixgbe_adapter *)dev->data->dev_private;
3985
3986         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3987                      dev->data->port_id);
3988
3989         /*
3990          * VF has no ability to enable/disable HW CRC
3991          * Keep the persistent behavior the same as Host PF
3992          */
3993 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3994         if (!conf->rxmode.hw_strip_crc) {
3995                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3996                 conf->rxmode.hw_strip_crc = 1;
3997         }
3998 #else
3999         if (conf->rxmode.hw_strip_crc) {
4000                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4001                 conf->rxmode.hw_strip_crc = 0;
4002         }
4003 #endif
4004
4005         /*
4006          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4007          * allocation or vector Rx preconditions we will reset it.
4008          */
4009         adapter->rx_bulk_alloc_allowed = true;
4010         adapter->rx_vec_allowed = true;
4011
4012         return 0;
4013 }
4014
4015 static int
4016 ixgbevf_dev_start(struct rte_eth_dev *dev)
4017 {
4018         struct ixgbe_hw *hw =
4019                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4020         uint32_t intr_vector = 0;
4021         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4022
4023         int err, mask = 0;
4024
4025         PMD_INIT_FUNC_TRACE();
4026
4027         hw->mac.ops.reset_hw(hw);
4028         hw->mac.get_link_status = true;
4029
4030         /* negotiate mailbox API version to use with the PF. */
4031         ixgbevf_negotiate_api(hw);
4032
4033         ixgbevf_dev_tx_init(dev);
4034
4035         /* This can fail when allocating mbufs for descriptor rings */
4036         err = ixgbevf_dev_rx_init(dev);
4037         if (err) {
4038                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4039                 ixgbe_dev_clear_queues(dev);
4040                 return err;
4041         }
4042
4043         /* Set vfta */
4044         ixgbevf_set_vfta_all(dev, 1);
4045
4046         /* Set HW strip */
4047         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4048                 ETH_VLAN_EXTEND_MASK;
4049         ixgbevf_vlan_offload_set(dev, mask);
4050
4051         ixgbevf_dev_rxtx_start(dev);
4052
4053         /* check and configure queue intr-vector mapping */
4054         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4055                 intr_vector = dev->data->nb_rx_queues;
4056                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4057                         return -1;
4058         }
4059
4060         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4061                 intr_handle->intr_vec =
4062                         rte_zmalloc("intr_vec",
4063                                     dev->data->nb_rx_queues * sizeof(int), 0);
4064                 if (intr_handle->intr_vec == NULL) {
4065                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4066                                      " intr_vec\n", dev->data->nb_rx_queues);
4067                         return -ENOMEM;
4068                 }
4069         }
4070         ixgbevf_configure_msix(dev);
4071
4072         rte_intr_enable(intr_handle);
4073
4074         /* Re-enable interrupt for VF */
4075         ixgbevf_intr_enable(hw);
4076
4077         return 0;
4078 }
4079
4080 static void
4081 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4082 {
4083         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4084         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4085
4086         PMD_INIT_FUNC_TRACE();
4087
4088         hw->adapter_stopped = 1;
4089         ixgbe_stop_adapter(hw);
4090
4091         /*
4092           * Clear what we set, but we still keep shadow_vfta to
4093           * restore after device starts
4094           */
4095         ixgbevf_set_vfta_all(dev, 0);
4096
4097         /* Clear stored conf */
4098         dev->data->scattered_rx = 0;
4099
4100         ixgbe_dev_clear_queues(dev);
4101
4102         /* Clean datapath event and queue/vec mapping */
4103         rte_intr_efd_disable(intr_handle);
4104         if (intr_handle->intr_vec != NULL) {
4105                 rte_free(intr_handle->intr_vec);
4106                 intr_handle->intr_vec = NULL;
4107         }
4108 }
4109
4110 static void
4111 ixgbevf_dev_close(struct rte_eth_dev *dev)
4112 {
4113         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4114
4115         PMD_INIT_FUNC_TRACE();
4116
4117         ixgbe_reset_hw(hw);
4118
4119         ixgbevf_dev_stop(dev);
4120
4121         ixgbe_dev_free_queues(dev);
4122
4123         /**
4124          * Remove the VF MAC address ro ensure
4125          * that the VF traffic goes to the PF
4126          * after stop, close and detach of the VF
4127          **/
4128         ixgbevf_remove_mac_addr(dev, 0);
4129 }
4130
4131 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4132 {
4133         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4134         struct ixgbe_vfta *shadow_vfta =
4135                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4136         int i = 0, j = 0, vfta = 0, mask = 1;
4137
4138         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4139                 vfta = shadow_vfta->vfta[i];
4140                 if (vfta) {
4141                         mask = 1;
4142                         for (j = 0; j < 32; j++) {
4143                                 if (vfta & mask)
4144                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4145                                 mask <<= 1;
4146                         }
4147                 }
4148         }
4149
4150 }
4151
4152 static int
4153 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4154 {
4155         struct ixgbe_hw *hw =
4156                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4157         struct ixgbe_vfta *shadow_vfta =
4158                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4159         uint32_t vid_idx = 0;
4160         uint32_t vid_bit = 0;
4161         int ret = 0;
4162
4163         PMD_INIT_FUNC_TRACE();
4164
4165         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4166         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4167         if (ret) {
4168                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4169                 return ret;
4170         }
4171         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4172         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4173
4174         /* Save what we set and retore it after device reset */
4175         if (on)
4176                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4177         else
4178                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4179
4180         return 0;
4181 }
4182
4183 static void
4184 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4185 {
4186         struct ixgbe_hw *hw =
4187                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4188         uint32_t ctrl;
4189
4190         PMD_INIT_FUNC_TRACE();
4191
4192         if (queue >= hw->mac.max_rx_queues)
4193                 return;
4194
4195         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4196         if (on)
4197                 ctrl |= IXGBE_RXDCTL_VME;
4198         else
4199                 ctrl &= ~IXGBE_RXDCTL_VME;
4200         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4201
4202         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4203 }
4204
4205 static void
4206 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4207 {
4208         struct ixgbe_hw *hw =
4209                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4210         uint16_t i;
4211         int on = 0;
4212
4213         /* VF function only support hw strip feature, others are not support */
4214         if (mask & ETH_VLAN_STRIP_MASK) {
4215                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4216
4217                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4218                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4219         }
4220 }
4221
4222 static int
4223 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4224 {
4225         uint32_t reg_val;
4226
4227         /* we only need to do this if VMDq is enabled */
4228         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4229         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4230                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4231                 return -1;
4232         }
4233
4234         return 0;
4235 }
4236
4237 static uint32_t
4238 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4239 {
4240         uint32_t vector = 0;
4241
4242         switch (hw->mac.mc_filter_type) {
4243         case 0:   /* use bits [47:36] of the address */
4244                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4245                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4246                 break;
4247         case 1:   /* use bits [46:35] of the address */
4248                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4249                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4250                 break;
4251         case 2:   /* use bits [45:34] of the address */
4252                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4253                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4254                 break;
4255         case 3:   /* use bits [43:32] of the address */
4256                 vector = ((uc_addr->addr_bytes[4]) |
4257                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4258                 break;
4259         default:  /* Invalid mc_filter_type */
4260                 break;
4261         }
4262
4263         /* vector can only be 12-bits or boundary will be exceeded */
4264         vector &= 0xFFF;
4265         return vector;
4266 }
4267
4268 static int
4269 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4270                         uint8_t on)
4271 {
4272         uint32_t vector;
4273         uint32_t uta_idx;
4274         uint32_t reg_val;
4275         uint32_t uta_shift;
4276         uint32_t rc;
4277         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4278         const uint32_t ixgbe_uta_bit_shift = 5;
4279         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4280         const uint32_t bit1 = 0x1;
4281
4282         struct ixgbe_hw *hw =
4283                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4284         struct ixgbe_uta_info *uta_info =
4285                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4286
4287         /* The UTA table only exists on 82599 hardware and newer */
4288         if (hw->mac.type < ixgbe_mac_82599EB)
4289                 return -ENOTSUP;
4290
4291         vector = ixgbe_uta_vector(hw, mac_addr);
4292         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4293         uta_shift = vector & ixgbe_uta_bit_mask;
4294
4295         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4296         if (rc == on)
4297                 return 0;
4298
4299         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4300         if (on) {
4301                 uta_info->uta_in_use++;
4302                 reg_val |= (bit1 << uta_shift);
4303                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4304         } else {
4305                 uta_info->uta_in_use--;
4306                 reg_val &= ~(bit1 << uta_shift);
4307                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4308         }
4309
4310         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4311
4312         if (uta_info->uta_in_use > 0)
4313                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4314                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4315         else
4316                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4317
4318         return 0;
4319 }
4320
4321 static int
4322 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4323 {
4324         int i;
4325         struct ixgbe_hw *hw =
4326                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4327         struct ixgbe_uta_info *uta_info =
4328                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4329
4330         /* The UTA table only exists on 82599 hardware and newer */
4331         if (hw->mac.type < ixgbe_mac_82599EB)
4332                 return -ENOTSUP;
4333
4334         if (on) {
4335                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4336                         uta_info->uta_shadow[i] = ~0;
4337                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4338                 }
4339         } else {
4340                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4341                         uta_info->uta_shadow[i] = 0;
4342                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4343                 }
4344         }
4345         return 0;
4346
4347 }
4348
4349 uint32_t
4350 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4351 {
4352         uint32_t new_val = orig_val;
4353
4354         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4355                 new_val |= IXGBE_VMOLR_AUPE;
4356         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4357                 new_val |= IXGBE_VMOLR_ROMPE;
4358         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4359                 new_val |= IXGBE_VMOLR_ROPE;
4360         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4361                 new_val |= IXGBE_VMOLR_BAM;
4362         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4363                 new_val |= IXGBE_VMOLR_MPE;
4364
4365         return new_val;
4366 }
4367
4368 static int
4369 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4370                                uint16_t rx_mask, uint8_t on)
4371 {
4372         int val = 0;
4373
4374         struct ixgbe_hw *hw =
4375                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4376         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4377
4378         if (hw->mac.type == ixgbe_mac_82598EB) {
4379                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4380                              " on 82599 hardware and newer");
4381                 return -ENOTSUP;
4382         }
4383         if (ixgbe_vmdq_mode_check(hw) < 0)
4384                 return -ENOTSUP;
4385
4386         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4387
4388         if (on)
4389                 vmolr |= val;
4390         else
4391                 vmolr &= ~val;
4392
4393         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4394
4395         return 0;
4396 }
4397
4398 static int
4399 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4400 {
4401         uint32_t reg, addr;
4402         uint32_t val;
4403         const uint8_t bit1 = 0x1;
4404
4405         struct ixgbe_hw *hw =
4406                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4407
4408         if (ixgbe_vmdq_mode_check(hw) < 0)
4409                 return -ENOTSUP;
4410
4411         if (pool >= ETH_64_POOLS)
4412                 return -EINVAL;
4413
4414         /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4415         if (pool >= 32) {
4416                 addr = IXGBE_VFRE(1);
4417                 val = bit1 << (pool - 32);
4418         } else {
4419                 addr = IXGBE_VFRE(0);
4420                 val = bit1 << pool;
4421         }
4422
4423         reg = IXGBE_READ_REG(hw, addr);
4424
4425         if (on)
4426                 reg |= val;
4427         else
4428                 reg &= ~val;
4429
4430         IXGBE_WRITE_REG(hw, addr, reg);
4431
4432         return 0;
4433 }
4434
4435 static int
4436 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4437 {
4438         uint32_t reg, addr;
4439         uint32_t val;
4440         const uint8_t bit1 = 0x1;
4441
4442         struct ixgbe_hw *hw =
4443                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4444
4445         if (ixgbe_vmdq_mode_check(hw) < 0)
4446                 return -ENOTSUP;
4447
4448         if (pool >= ETH_64_POOLS)
4449                 return -EINVAL;
4450
4451         /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4452         if (pool >= 32) {
4453                 addr = IXGBE_VFTE(1);
4454                 val = bit1 << (pool - 32);
4455         } else {
4456                 addr = IXGBE_VFTE(0);
4457                 val = bit1 << pool;
4458         }
4459
4460         reg = IXGBE_READ_REG(hw, addr);
4461
4462         if (on)
4463                 reg |= val;
4464         else
4465                 reg &= ~val;
4466
4467         IXGBE_WRITE_REG(hw, addr, reg);
4468
4469         return 0;
4470 }
4471
4472 static int
4473 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4474                         uint64_t pool_mask, uint8_t vlan_on)
4475 {
4476         int ret = 0;
4477         uint16_t pool_idx;
4478         struct ixgbe_hw *hw =
4479                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4480
4481         if (ixgbe_vmdq_mode_check(hw) < 0)
4482                 return -ENOTSUP;
4483         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4484                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4485                         ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx, vlan_on);
4486                         if (ret < 0)
4487                                 return ret;
4488                 }
4489         }
4490
4491         return ret;
4492 }
4493
4494 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4495 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4496 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4497 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4498 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4499         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4500         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4501
4502 static int
4503 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4504                         struct rte_eth_mirror_conf *mirror_conf,
4505                         uint8_t rule_id, uint8_t on)
4506 {
4507         uint32_t mr_ctl, vlvf;
4508         uint32_t mp_lsb = 0;
4509         uint32_t mv_msb = 0;
4510         uint32_t mv_lsb = 0;
4511         uint32_t mp_msb = 0;
4512         uint8_t i = 0;
4513         int reg_index = 0;
4514         uint64_t vlan_mask = 0;
4515
4516         const uint8_t pool_mask_offset = 32;
4517         const uint8_t vlan_mask_offset = 32;
4518         const uint8_t dst_pool_offset = 8;
4519         const uint8_t rule_mr_offset  = 4;
4520         const uint8_t mirror_rule_mask = 0x0F;
4521
4522         struct ixgbe_mirror_info *mr_info =
4523                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4524         struct ixgbe_hw *hw =
4525                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4526         uint8_t mirror_type = 0;
4527
4528         if (ixgbe_vmdq_mode_check(hw) < 0)
4529                 return -ENOTSUP;
4530
4531         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4532                 return -EINVAL;
4533
4534         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4535                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4536                         mirror_conf->rule_type);
4537                 return -EINVAL;
4538         }
4539
4540         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4541                 mirror_type |= IXGBE_MRCTL_VLME;
4542                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4543                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
4544                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4545                                 /* search vlan id related pool vlan filter index */
4546                                 reg_index = ixgbe_find_vlvf_slot(hw,
4547                                                 mirror_conf->vlan.vlan_id[i]);
4548                                 if (reg_index < 0)
4549                                         return -EINVAL;
4550                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4551                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4552                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4553                                       mirror_conf->vlan.vlan_id[i]))
4554                                         vlan_mask |= (1ULL << reg_index);
4555                                 else
4556                                         return -EINVAL;
4557                         }
4558                 }
4559
4560                 if (on) {
4561                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4562                         mv_msb = vlan_mask >> vlan_mask_offset;
4563
4564                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4565                                                 mirror_conf->vlan.vlan_mask;
4566                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4567                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4568                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4569                                                 mirror_conf->vlan.vlan_id[i];
4570                         }
4571                 } else {
4572                         mv_lsb = 0;
4573                         mv_msb = 0;
4574                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4575                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4576                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4577                 }
4578         }
4579
4580         /*
4581          * if enable pool mirror, write related pool mask register,if disable
4582          * pool mirror, clear PFMRVM register
4583          */
4584         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4585                 mirror_type |= IXGBE_MRCTL_VPME;
4586                 if (on) {
4587                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4588                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4589                         mr_info->mr_conf[rule_id].pool_mask =
4590                                         mirror_conf->pool_mask;
4591
4592                 } else {
4593                         mp_lsb = 0;
4594                         mp_msb = 0;
4595                         mr_info->mr_conf[rule_id].pool_mask = 0;
4596                 }
4597         }
4598         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4599                 mirror_type |= IXGBE_MRCTL_UPME;
4600         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4601                 mirror_type |= IXGBE_MRCTL_DPME;
4602
4603         /* read  mirror control register and recalculate it */
4604         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4605
4606         if (on) {
4607                 mr_ctl |= mirror_type;
4608                 mr_ctl &= mirror_rule_mask;
4609                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4610         } else
4611                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4612
4613         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4614         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4615
4616         /* write mirrror control  register */
4617         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4618
4619         /* write pool mirrror control  register */
4620         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4621                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4622                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4623                                 mp_msb);
4624         }
4625         /* write VLAN mirrror control  register */
4626         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4627                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4628                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4629                                 mv_msb);
4630         }
4631
4632         return 0;
4633 }
4634
4635 static int
4636 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4637 {
4638         int mr_ctl = 0;
4639         uint32_t lsb_val = 0;
4640         uint32_t msb_val = 0;
4641         const uint8_t rule_mr_offset = 4;
4642
4643         struct ixgbe_hw *hw =
4644                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4645         struct ixgbe_mirror_info *mr_info =
4646                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4647
4648         if (ixgbe_vmdq_mode_check(hw) < 0)
4649                 return -ENOTSUP;
4650
4651         memset(&mr_info->mr_conf[rule_id], 0,
4652                 sizeof(struct rte_eth_mirror_conf));
4653
4654         /* clear PFVMCTL register */
4655         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4656
4657         /* clear pool mask register */
4658         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4659         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4660
4661         /* clear vlan mask register */
4662         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4663         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4664
4665         return 0;
4666 }
4667
4668 static int
4669 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4670 {
4671         uint32_t mask;
4672         struct ixgbe_hw *hw =
4673                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4674
4675         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4676         mask |= (1 << IXGBE_MISC_VEC_ID);
4677         RTE_SET_USED(queue_id);
4678         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4679
4680         rte_intr_enable(&dev->pci_dev->intr_handle);
4681
4682         return 0;
4683 }
4684
4685 static int
4686 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4687 {
4688         uint32_t mask;
4689         struct ixgbe_hw *hw =
4690                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4691
4692         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4693         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4694         RTE_SET_USED(queue_id);
4695         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4696
4697         return 0;
4698 }
4699
4700 static int
4701 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4702 {
4703         uint32_t mask;
4704         struct ixgbe_hw *hw =
4705                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4706         struct ixgbe_interrupt *intr =
4707                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4708
4709         if (queue_id < 16) {
4710                 ixgbe_disable_intr(hw);
4711                 intr->mask |= (1 << queue_id);
4712                 ixgbe_enable_intr(dev);
4713         } else if (queue_id < 32) {
4714                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4715                 mask &= (1 << queue_id);
4716                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4717         } else if (queue_id < 64) {
4718                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4719                 mask &= (1 << (queue_id - 32));
4720                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4721         }
4722         rte_intr_enable(&dev->pci_dev->intr_handle);
4723
4724         return 0;
4725 }
4726
4727 static int
4728 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4729 {
4730         uint32_t mask;
4731         struct ixgbe_hw *hw =
4732                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4733         struct ixgbe_interrupt *intr =
4734                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4735
4736         if (queue_id < 16) {
4737                 ixgbe_disable_intr(hw);
4738                 intr->mask &= ~(1 << queue_id);
4739                 ixgbe_enable_intr(dev);
4740         } else if (queue_id < 32) {
4741                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4742                 mask &= ~(1 << queue_id);
4743                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4744         } else if (queue_id < 64) {
4745                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4746                 mask &= ~(1 << (queue_id - 32));
4747                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4748         }
4749
4750         return 0;
4751 }
4752
4753 static void
4754 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4755                      uint8_t queue, uint8_t msix_vector)
4756 {
4757         uint32_t tmp, idx;
4758
4759         if (direction == -1) {
4760                 /* other causes */
4761                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4762                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4763                 tmp &= ~0xFF;
4764                 tmp |= msix_vector;
4765                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4766         } else {
4767                 /* rx or tx cause */
4768                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4769                 idx = ((16 * (queue & 1)) + (8 * direction));
4770                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4771                 tmp &= ~(0xFF << idx);
4772                 tmp |= (msix_vector << idx);
4773                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4774         }
4775 }
4776
4777 /**
4778  * set the IVAR registers, mapping interrupt causes to vectors
4779  * @param hw
4780  *  pointer to ixgbe_hw struct
4781  * @direction
4782  *  0 for Rx, 1 for Tx, -1 for other causes
4783  * @queue
4784  *  queue to map the corresponding interrupt to
4785  * @msix_vector
4786  *  the vector to map to the corresponding queue
4787  */
4788 static void
4789 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4790                    uint8_t queue, uint8_t msix_vector)
4791 {
4792         uint32_t tmp, idx;
4793
4794         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4795         if (hw->mac.type == ixgbe_mac_82598EB) {
4796                 if (direction == -1)
4797                         direction = 0;
4798                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4799                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4800                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4801                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4802                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4803         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4804                         (hw->mac.type == ixgbe_mac_X540)) {
4805                 if (direction == -1) {
4806                         /* other causes */
4807                         idx = ((queue & 1) * 8);
4808                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4809                         tmp &= ~(0xFF << idx);
4810                         tmp |= (msix_vector << idx);
4811                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4812                 } else {
4813                         /* rx or tx causes */
4814                         idx = ((16 * (queue & 1)) + (8 * direction));
4815                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4816                         tmp &= ~(0xFF << idx);
4817                         tmp |= (msix_vector << idx);
4818                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4819                 }
4820         }
4821 }
4822
4823 static void
4824 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4825 {
4826         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4827         struct ixgbe_hw *hw =
4828                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4829         uint32_t q_idx;
4830         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4831
4832         /* won't configure msix register if no mapping is done
4833          * between intr vector and event fd.
4834          */
4835         if (!rte_intr_dp_is_en(intr_handle))
4836                 return;
4837
4838         /* Configure all RX queues of VF */
4839         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4840                 /* Force all queue use vector 0,
4841                  * as IXGBE_VF_MAXMSIVECOTR = 1
4842                  */
4843                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4844                 intr_handle->intr_vec[q_idx] = vector_idx;
4845         }
4846
4847         /* Configure VF other cause ivar */
4848         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4849 }
4850
4851 /**
4852  * Sets up the hardware to properly generate MSI-X interrupts
4853  * @hw
4854  *  board private structure
4855  */
4856 static void
4857 ixgbe_configure_msix(struct rte_eth_dev *dev)
4858 {
4859         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4860         struct ixgbe_hw *hw =
4861                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4862         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4863         uint32_t vec = IXGBE_MISC_VEC_ID;
4864         uint32_t mask;
4865         uint32_t gpie;
4866
4867         /* won't configure msix register if no mapping is done
4868          * between intr vector and event fd
4869          */
4870         if (!rte_intr_dp_is_en(intr_handle))
4871                 return;
4872
4873         if (rte_intr_allow_others(intr_handle))
4874                 vec = base = IXGBE_RX_VEC_START;
4875
4876         /* setup GPIE for MSI-x mode */
4877         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4878         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4879                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4880         /* auto clearing and auto setting corresponding bits in EIMS
4881          * when MSI-X interrupt is triggered
4882          */
4883         if (hw->mac.type == ixgbe_mac_82598EB) {
4884                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4885         } else {
4886                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4887                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4888         }
4889         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4890
4891         /* Populate the IVAR table and set the ITR values to the
4892          * corresponding register.
4893          */
4894         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4895              queue_id++) {
4896                 /* by default, 1:1 mapping */
4897                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4898                 intr_handle->intr_vec[queue_id] = vec;
4899                 if (vec < base + intr_handle->nb_efd - 1)
4900                         vec++;
4901         }
4902
4903         switch (hw->mac.type) {
4904         case ixgbe_mac_82598EB:
4905                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4906                                    IXGBE_MISC_VEC_ID);
4907                 break;
4908         case ixgbe_mac_82599EB:
4909         case ixgbe_mac_X540:
4910                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4911                 break;
4912         default:
4913                 break;
4914         }
4915         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4916                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4917
4918         /* set up to autoclear timer, and the vectors */
4919         mask = IXGBE_EIMS_ENABLE_MASK;
4920         mask &= ~(IXGBE_EIMS_OTHER |
4921                   IXGBE_EIMS_MAILBOX |
4922                   IXGBE_EIMS_LSC);
4923
4924         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4925 }
4926
4927 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4928         uint16_t queue_idx, uint16_t tx_rate)
4929 {
4930         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4931         uint32_t rf_dec, rf_int;
4932         uint32_t bcnrc_val;
4933         uint16_t link_speed = dev->data->dev_link.link_speed;
4934
4935         if (queue_idx >= hw->mac.max_tx_queues)
4936                 return -EINVAL;
4937
4938         if (tx_rate != 0) {
4939                 /* Calculate the rate factor values to set */
4940                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4941                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4942                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4943
4944                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4945                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4946                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4947                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4948         } else {
4949                 bcnrc_val = 0;
4950         }
4951
4952         /*
4953          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4954          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4955          * set as 0x4.
4956          */
4957         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4958                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4959                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4960                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4961                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4962         else
4963                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4964                         IXGBE_MMW_SIZE_DEFAULT);
4965
4966         /* Set RTTBCNRC of queue X */
4967         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4968         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4969         IXGBE_WRITE_FLUSH(hw);
4970
4971         return 0;
4972 }
4973
4974 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4975         uint16_t tx_rate, uint64_t q_msk)
4976 {
4977         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4978         struct ixgbe_vf_info *vfinfo =
4979                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4980         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4981         uint32_t queue_stride =
4982                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4983         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4984         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4985         uint16_t total_rate = 0;
4986
4987         if (queue_end >= hw->mac.max_tx_queues)
4988                 return -EINVAL;
4989
4990         if (vfinfo != NULL) {
4991                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4992                         if (vf_idx == vf)
4993                                 continue;
4994                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4995                                 idx++)
4996                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4997                 }
4998         } else
4999                 return -EINVAL;
5000
5001         /* Store tx_rate for this vf. */
5002         for (idx = 0; idx < nb_q_per_pool; idx++) {
5003                 if (((uint64_t)0x1 << idx) & q_msk) {
5004                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5005                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5006                         total_rate += tx_rate;
5007                 }
5008         }
5009
5010         if (total_rate > dev->data->dev_link.link_speed) {
5011                 /*
5012                  * Reset stored TX rate of the VF if it causes exceed
5013                  * link speed.
5014                  */
5015                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5016                 return -EINVAL;
5017         }
5018
5019         /* Set RTTBCNRC of each queue/pool for vf X  */
5020         for (; queue_idx <= queue_end; queue_idx++) {
5021                 if (0x1 & q_msk)
5022                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5023                 q_msk = q_msk >> 1;
5024         }
5025
5026         return 0;
5027 }
5028
5029 static void
5030 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5031                      __attribute__((unused)) uint32_t index,
5032                      __attribute__((unused)) uint32_t pool)
5033 {
5034         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5035         int diag;
5036
5037         /*
5038          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5039          * operation. Trap this case to avoid exhausting the [very limited]
5040          * set of PF resources used to store VF MAC addresses.
5041          */
5042         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5043                 return;
5044         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5045         if (diag == 0)
5046                 return;
5047         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5048 }
5049
5050 static void
5051 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5052 {
5053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5054         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5055         struct ether_addr *mac_addr;
5056         uint32_t i;
5057         int diag;
5058
5059         /*
5060          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5061          * not support the deletion of a given MAC address.
5062          * Instead, it imposes to delete all MAC addresses, then to add again
5063          * all MAC addresses with the exception of the one to be deleted.
5064          */
5065         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5066
5067         /*
5068          * Add again all MAC addresses, with the exception of the deleted one
5069          * and of the permanent MAC address.
5070          */
5071         for (i = 0, mac_addr = dev->data->mac_addrs;
5072              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5073                 /* Skip the deleted MAC address */
5074                 if (i == index)
5075                         continue;
5076                 /* Skip NULL MAC addresses */
5077                 if (is_zero_ether_addr(mac_addr))
5078                         continue;
5079                 /* Skip the permanent MAC address */
5080                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5081                         continue;
5082                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5083                 if (diag != 0)
5084                         PMD_DRV_LOG(ERR,
5085                                     "Adding again MAC address "
5086                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5087                                     "diag=%d",
5088                                     mac_addr->addr_bytes[0],
5089                                     mac_addr->addr_bytes[1],
5090                                     mac_addr->addr_bytes[2],
5091                                     mac_addr->addr_bytes[3],
5092                                     mac_addr->addr_bytes[4],
5093                                     mac_addr->addr_bytes[5],
5094                                     diag);
5095         }
5096 }
5097
5098 static void
5099 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5100 {
5101         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5102
5103         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5104 }
5105
5106 #define MAC_TYPE_FILTER_SUP(type)    do {\
5107         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5108                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5109                 (type) != ixgbe_mac_X550EM_a)\
5110                 return -ENOTSUP;\
5111 } while (0)
5112
5113 static int
5114 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5115                         struct rte_eth_syn_filter *filter,
5116                         bool add)
5117 {
5118         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5119         uint32_t synqf;
5120
5121         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5122                 return -EINVAL;
5123
5124         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5125
5126         if (add) {
5127                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5128                         return -EINVAL;
5129                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5130                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5131
5132                 if (filter->hig_pri)
5133                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5134                 else
5135                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5136         } else {
5137                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5138                         return -ENOENT;
5139                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5140         }
5141         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5142         IXGBE_WRITE_FLUSH(hw);
5143         return 0;
5144 }
5145
5146 static int
5147 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5148                         struct rte_eth_syn_filter *filter)
5149 {
5150         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5151         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5152
5153         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5154                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5155                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5156                 return 0;
5157         }
5158         return -ENOENT;
5159 }
5160
5161 static int
5162 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5163                         enum rte_filter_op filter_op,
5164                         void *arg)
5165 {
5166         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5167         int ret;
5168
5169         MAC_TYPE_FILTER_SUP(hw->mac.type);
5170
5171         if (filter_op == RTE_ETH_FILTER_NOP)
5172                 return 0;
5173
5174         if (arg == NULL) {
5175                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5176                             filter_op);
5177                 return -EINVAL;
5178         }
5179
5180         switch (filter_op) {
5181         case RTE_ETH_FILTER_ADD:
5182                 ret = ixgbe_syn_filter_set(dev,
5183                                 (struct rte_eth_syn_filter *)arg,
5184                                 TRUE);
5185                 break;
5186         case RTE_ETH_FILTER_DELETE:
5187                 ret = ixgbe_syn_filter_set(dev,
5188                                 (struct rte_eth_syn_filter *)arg,
5189                                 FALSE);
5190                 break;
5191         case RTE_ETH_FILTER_GET:
5192                 ret = ixgbe_syn_filter_get(dev,
5193                                 (struct rte_eth_syn_filter *)arg);
5194                 break;
5195         default:
5196                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5197                 ret = -EINVAL;
5198                 break;
5199         }
5200
5201         return ret;
5202 }
5203
5204
5205 static inline enum ixgbe_5tuple_protocol
5206 convert_protocol_type(uint8_t protocol_value)
5207 {
5208         if (protocol_value == IPPROTO_TCP)
5209                 return IXGBE_FILTER_PROTOCOL_TCP;
5210         else if (protocol_value == IPPROTO_UDP)
5211                 return IXGBE_FILTER_PROTOCOL_UDP;
5212         else if (protocol_value == IPPROTO_SCTP)
5213                 return IXGBE_FILTER_PROTOCOL_SCTP;
5214         else
5215                 return IXGBE_FILTER_PROTOCOL_NONE;
5216 }
5217
5218 /*
5219  * add a 5tuple filter
5220  *
5221  * @param
5222  * dev: Pointer to struct rte_eth_dev.
5223  * index: the index the filter allocates.
5224  * filter: ponter to the filter that will be added.
5225  * rx_queue: the queue id the filter assigned to.
5226  *
5227  * @return
5228  *    - On success, zero.
5229  *    - On failure, a negative value.
5230  */
5231 static int
5232 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5233                         struct ixgbe_5tuple_filter *filter)
5234 {
5235         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5236         struct ixgbe_filter_info *filter_info =
5237                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5238         int i, idx, shift;
5239         uint32_t ftqf, sdpqf;
5240         uint32_t l34timir = 0;
5241         uint8_t mask = 0xff;
5242
5243         /*
5244          * look for an unused 5tuple filter index,
5245          * and insert the filter to list.
5246          */
5247         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5248                 idx = i / (sizeof(uint32_t) * NBBY);
5249                 shift = i % (sizeof(uint32_t) * NBBY);
5250                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5251                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5252                         filter->index = i;
5253                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5254                                           filter,
5255                                           entries);
5256                         break;
5257                 }
5258         }
5259         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5260                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5261                 return -ENOSYS;
5262         }
5263
5264         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5265                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5266         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5267
5268         ftqf = (uint32_t)(filter->filter_info.proto &
5269                 IXGBE_FTQF_PROTOCOL_MASK);
5270         ftqf |= (uint32_t)((filter->filter_info.priority &
5271                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5272         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5273                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5274         if (filter->filter_info.dst_ip_mask == 0)
5275                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5276         if (filter->filter_info.src_port_mask == 0)
5277                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5278         if (filter->filter_info.dst_port_mask == 0)
5279                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5280         if (filter->filter_info.proto_mask == 0)
5281                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5282         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5283         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5284         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5285
5286         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5287         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5288         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5289         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5290
5291         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5292         l34timir |= (uint32_t)(filter->queue <<
5293                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5294         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5295         return 0;
5296 }
5297
5298 /*
5299  * remove a 5tuple filter
5300  *
5301  * @param
5302  * dev: Pointer to struct rte_eth_dev.
5303  * filter: the pointer of the filter will be removed.
5304  */
5305 static void
5306 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5307                         struct ixgbe_5tuple_filter *filter)
5308 {
5309         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5310         struct ixgbe_filter_info *filter_info =
5311                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5312         uint16_t index = filter->index;
5313
5314         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5315                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5316         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5317         rte_free(filter);
5318
5319         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5320         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5321         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5322         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5323         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5324 }
5325
5326 static int
5327 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5328 {
5329         struct ixgbe_hw *hw;
5330         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5331
5332         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5333
5334         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5335                 return -EINVAL;
5336
5337         /* refuse mtu that requires the support of scattered packets when this
5338          * feature has not been enabled before.
5339          */
5340         if (!dev->data->scattered_rx &&
5341             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5342              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5343                 return -EINVAL;
5344
5345         /*
5346          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5347          * request of the version 2.0 of the mailbox API.
5348          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5349          * of the mailbox API.
5350          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5351          * prior to 3.11.33 which contains the following change:
5352          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5353          */
5354         ixgbevf_rlpml_set_vf(hw, max_frame);
5355
5356         /* update max frame size */
5357         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5358         return 0;
5359 }
5360
5361 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5362         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5363                 return -ENOTSUP;\
5364 } while (0)
5365
5366 static inline struct ixgbe_5tuple_filter *
5367 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5368                         struct ixgbe_5tuple_filter_info *key)
5369 {
5370         struct ixgbe_5tuple_filter *it;
5371
5372         TAILQ_FOREACH(it, filter_list, entries) {
5373                 if (memcmp(key, &it->filter_info,
5374                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5375                         return it;
5376                 }
5377         }
5378         return NULL;
5379 }
5380
5381 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5382 static inline int
5383 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5384                         struct ixgbe_5tuple_filter_info *filter_info)
5385 {
5386         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5387                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5388                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5389                 return -EINVAL;
5390
5391         switch (filter->dst_ip_mask) {
5392         case UINT32_MAX:
5393                 filter_info->dst_ip_mask = 0;
5394                 filter_info->dst_ip = filter->dst_ip;
5395                 break;
5396         case 0:
5397                 filter_info->dst_ip_mask = 1;
5398                 break;
5399         default:
5400                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5401                 return -EINVAL;
5402         }
5403
5404         switch (filter->src_ip_mask) {
5405         case UINT32_MAX:
5406                 filter_info->src_ip_mask = 0;
5407                 filter_info->src_ip = filter->src_ip;
5408                 break;
5409         case 0:
5410                 filter_info->src_ip_mask = 1;
5411                 break;
5412         default:
5413                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5414                 return -EINVAL;
5415         }
5416
5417         switch (filter->dst_port_mask) {
5418         case UINT16_MAX:
5419                 filter_info->dst_port_mask = 0;
5420                 filter_info->dst_port = filter->dst_port;
5421                 break;
5422         case 0:
5423                 filter_info->dst_port_mask = 1;
5424                 break;
5425         default:
5426                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5427                 return -EINVAL;
5428         }
5429
5430         switch (filter->src_port_mask) {
5431         case UINT16_MAX:
5432                 filter_info->src_port_mask = 0;
5433                 filter_info->src_port = filter->src_port;
5434                 break;
5435         case 0:
5436                 filter_info->src_port_mask = 1;
5437                 break;
5438         default:
5439                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5440                 return -EINVAL;
5441         }
5442
5443         switch (filter->proto_mask) {
5444         case UINT8_MAX:
5445                 filter_info->proto_mask = 0;
5446                 filter_info->proto =
5447                         convert_protocol_type(filter->proto);
5448                 break;
5449         case 0:
5450                 filter_info->proto_mask = 1;
5451                 break;
5452         default:
5453                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5454                 return -EINVAL;
5455         }
5456
5457         filter_info->priority = (uint8_t)filter->priority;
5458         return 0;
5459 }
5460
5461 /*
5462  * add or delete a ntuple filter
5463  *
5464  * @param
5465  * dev: Pointer to struct rte_eth_dev.
5466  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5467  * add: if true, add filter, if false, remove filter
5468  *
5469  * @return
5470  *    - On success, zero.
5471  *    - On failure, a negative value.
5472  */
5473 static int
5474 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5475                         struct rte_eth_ntuple_filter *ntuple_filter,
5476                         bool add)
5477 {
5478         struct ixgbe_filter_info *filter_info =
5479                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5480         struct ixgbe_5tuple_filter_info filter_5tuple;
5481         struct ixgbe_5tuple_filter *filter;
5482         int ret;
5483
5484         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5485                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5486                 return -EINVAL;
5487         }
5488
5489         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5490         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5491         if (ret < 0)
5492                 return ret;
5493
5494         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5495                                          &filter_5tuple);
5496         if (filter != NULL && add) {
5497                 PMD_DRV_LOG(ERR, "filter exists.");
5498                 return -EEXIST;
5499         }
5500         if (filter == NULL && !add) {
5501                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5502                 return -ENOENT;
5503         }
5504
5505         if (add) {
5506                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5507                                 sizeof(struct ixgbe_5tuple_filter), 0);
5508                 if (filter == NULL)
5509                         return -ENOMEM;
5510                 (void)rte_memcpy(&filter->filter_info,
5511                                  &filter_5tuple,
5512                                  sizeof(struct ixgbe_5tuple_filter_info));
5513                 filter->queue = ntuple_filter->queue;
5514                 ret = ixgbe_add_5tuple_filter(dev, filter);
5515                 if (ret < 0) {
5516                         rte_free(filter);
5517                         return ret;
5518                 }
5519         } else
5520                 ixgbe_remove_5tuple_filter(dev, filter);
5521
5522         return 0;
5523 }
5524
5525 /*
5526  * get a ntuple filter
5527  *
5528  * @param
5529  * dev: Pointer to struct rte_eth_dev.
5530  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5531  *
5532  * @return
5533  *    - On success, zero.
5534  *    - On failure, a negative value.
5535  */
5536 static int
5537 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5538                         struct rte_eth_ntuple_filter *ntuple_filter)
5539 {
5540         struct ixgbe_filter_info *filter_info =
5541                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5542         struct ixgbe_5tuple_filter_info filter_5tuple;
5543         struct ixgbe_5tuple_filter *filter;
5544         int ret;
5545
5546         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5547                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5548                 return -EINVAL;
5549         }
5550
5551         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5552         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5553         if (ret < 0)
5554                 return ret;
5555
5556         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5557                                          &filter_5tuple);
5558         if (filter == NULL) {
5559                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5560                 return -ENOENT;
5561         }
5562         ntuple_filter->queue = filter->queue;
5563         return 0;
5564 }
5565
5566 /*
5567  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5568  * @dev: pointer to rte_eth_dev structure
5569  * @filter_op:operation will be taken.
5570  * @arg: a pointer to specific structure corresponding to the filter_op
5571  *
5572  * @return
5573  *    - On success, zero.
5574  *    - On failure, a negative value.
5575  */
5576 static int
5577 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5578                                 enum rte_filter_op filter_op,
5579                                 void *arg)
5580 {
5581         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5582         int ret;
5583
5584         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5585
5586         if (filter_op == RTE_ETH_FILTER_NOP)
5587                 return 0;
5588
5589         if (arg == NULL) {
5590                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5591                             filter_op);
5592                 return -EINVAL;
5593         }
5594
5595         switch (filter_op) {
5596         case RTE_ETH_FILTER_ADD:
5597                 ret = ixgbe_add_del_ntuple_filter(dev,
5598                         (struct rte_eth_ntuple_filter *)arg,
5599                         TRUE);
5600                 break;
5601         case RTE_ETH_FILTER_DELETE:
5602                 ret = ixgbe_add_del_ntuple_filter(dev,
5603                         (struct rte_eth_ntuple_filter *)arg,
5604                         FALSE);
5605                 break;
5606         case RTE_ETH_FILTER_GET:
5607                 ret = ixgbe_get_ntuple_filter(dev,
5608                         (struct rte_eth_ntuple_filter *)arg);
5609                 break;
5610         default:
5611                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5612                 ret = -EINVAL;
5613                 break;
5614         }
5615         return ret;
5616 }
5617
5618 static inline int
5619 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5620                         uint16_t ethertype)
5621 {
5622         int i;
5623
5624         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5625                 if (filter_info->ethertype_filters[i] == ethertype &&
5626                     (filter_info->ethertype_mask & (1 << i)))
5627                         return i;
5628         }
5629         return -1;
5630 }
5631
5632 static inline int
5633 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5634                         uint16_t ethertype)
5635 {
5636         int i;
5637
5638         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5639                 if (!(filter_info->ethertype_mask & (1 << i))) {
5640                         filter_info->ethertype_mask |= 1 << i;
5641                         filter_info->ethertype_filters[i] = ethertype;
5642                         return i;
5643                 }
5644         }
5645         return -1;
5646 }
5647
5648 static inline int
5649 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5650                         uint8_t idx)
5651 {
5652         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5653                 return -1;
5654         filter_info->ethertype_mask &= ~(1 << idx);
5655         filter_info->ethertype_filters[idx] = 0;
5656         return idx;
5657 }
5658
5659 static int
5660 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5661                         struct rte_eth_ethertype_filter *filter,
5662                         bool add)
5663 {
5664         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5665         struct ixgbe_filter_info *filter_info =
5666                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5667         uint32_t etqf = 0;
5668         uint32_t etqs = 0;
5669         int ret;
5670
5671         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5672                 return -EINVAL;
5673
5674         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5675                 filter->ether_type == ETHER_TYPE_IPv6) {
5676                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5677                         " ethertype filter.", filter->ether_type);
5678                 return -EINVAL;
5679         }
5680
5681         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5682                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5683                 return -EINVAL;
5684         }
5685         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5686                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5687                 return -EINVAL;
5688         }
5689
5690         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5691         if (ret >= 0 && add) {
5692                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5693                             filter->ether_type);
5694                 return -EEXIST;
5695         }
5696         if (ret < 0 && !add) {
5697                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5698                             filter->ether_type);
5699                 return -ENOENT;
5700         }
5701
5702         if (add) {
5703                 ret = ixgbe_ethertype_filter_insert(filter_info,
5704                         filter->ether_type);
5705                 if (ret < 0) {
5706                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5707                         return -ENOSYS;
5708                 }
5709                 etqf = IXGBE_ETQF_FILTER_EN;
5710                 etqf |= (uint32_t)filter->ether_type;
5711                 etqs |= (uint32_t)((filter->queue <<
5712                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5713                                     IXGBE_ETQS_RX_QUEUE);
5714                 etqs |= IXGBE_ETQS_QUEUE_EN;
5715         } else {
5716                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5717                 if (ret < 0)
5718                         return -ENOSYS;
5719         }
5720         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5721         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5722         IXGBE_WRITE_FLUSH(hw);
5723
5724         return 0;
5725 }
5726
5727 static int
5728 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5729                         struct rte_eth_ethertype_filter *filter)
5730 {
5731         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5732         struct ixgbe_filter_info *filter_info =
5733                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5734         uint32_t etqf, etqs;
5735         int ret;
5736
5737         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5738         if (ret < 0) {
5739                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5740                             filter->ether_type);
5741                 return -ENOENT;
5742         }
5743
5744         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5745         if (etqf & IXGBE_ETQF_FILTER_EN) {
5746                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5747                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5748                 filter->flags = 0;
5749                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5750                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5751                 return 0;
5752         }
5753         return -ENOENT;
5754 }
5755
5756 /*
5757  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5758  * @dev: pointer to rte_eth_dev structure
5759  * @filter_op:operation will be taken.
5760  * @arg: a pointer to specific structure corresponding to the filter_op
5761  */
5762 static int
5763 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5764                                 enum rte_filter_op filter_op,
5765                                 void *arg)
5766 {
5767         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5768         int ret;
5769
5770         MAC_TYPE_FILTER_SUP(hw->mac.type);
5771
5772         if (filter_op == RTE_ETH_FILTER_NOP)
5773                 return 0;
5774
5775         if (arg == NULL) {
5776                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5777                             filter_op);
5778                 return -EINVAL;
5779         }
5780
5781         switch (filter_op) {
5782         case RTE_ETH_FILTER_ADD:
5783                 ret = ixgbe_add_del_ethertype_filter(dev,
5784                         (struct rte_eth_ethertype_filter *)arg,
5785                         TRUE);
5786                 break;
5787         case RTE_ETH_FILTER_DELETE:
5788                 ret = ixgbe_add_del_ethertype_filter(dev,
5789                         (struct rte_eth_ethertype_filter *)arg,
5790                         FALSE);
5791                 break;
5792         case RTE_ETH_FILTER_GET:
5793                 ret = ixgbe_get_ethertype_filter(dev,
5794                         (struct rte_eth_ethertype_filter *)arg);
5795                 break;
5796         default:
5797                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5798                 ret = -EINVAL;
5799                 break;
5800         }
5801         return ret;
5802 }
5803
5804 static int
5805 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5806                      enum rte_filter_type filter_type,
5807                      enum rte_filter_op filter_op,
5808                      void *arg)
5809 {
5810         int ret = -EINVAL;
5811
5812         switch (filter_type) {
5813         case RTE_ETH_FILTER_NTUPLE:
5814                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5815                 break;
5816         case RTE_ETH_FILTER_ETHERTYPE:
5817                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5818                 break;
5819         case RTE_ETH_FILTER_SYN:
5820                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5821                 break;
5822         case RTE_ETH_FILTER_FDIR:
5823                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5824                 break;
5825         case RTE_ETH_FILTER_L2_TUNNEL:
5826                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5827                 break;
5828         default:
5829                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5830                                                         filter_type);
5831                 break;
5832         }
5833
5834         return ret;
5835 }
5836
5837 static u8 *
5838 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5839                         u8 **mc_addr_ptr, u32 *vmdq)
5840 {
5841         u8 *mc_addr;
5842
5843         *vmdq = 0;
5844         mc_addr = *mc_addr_ptr;
5845         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5846         return mc_addr;
5847 }
5848
5849 static int
5850 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5851                           struct ether_addr *mc_addr_set,
5852                           uint32_t nb_mc_addr)
5853 {
5854         struct ixgbe_hw *hw;
5855         u8 *mc_addr_list;
5856
5857         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5858         mc_addr_list = (u8 *)mc_addr_set;
5859         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5860                                          ixgbe_dev_addr_list_itr, TRUE);
5861 }
5862
5863 static uint64_t
5864 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5865 {
5866         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5867         uint64_t systime_cycles;
5868
5869         switch (hw->mac.type) {
5870         case ixgbe_mac_X550:
5871         case ixgbe_mac_X550EM_x:
5872         case ixgbe_mac_X550EM_a:
5873                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5874                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5875                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5876                                 * NSEC_PER_SEC;
5877                 break;
5878         default:
5879                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5880                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5881                                 << 32;
5882         }
5883
5884         return systime_cycles;
5885 }
5886
5887 static uint64_t
5888 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5889 {
5890         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5891         uint64_t rx_tstamp_cycles;
5892
5893         switch (hw->mac.type) {
5894         case ixgbe_mac_X550:
5895         case ixgbe_mac_X550EM_x:
5896         case ixgbe_mac_X550EM_a:
5897                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5898                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5899                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5900                                 * NSEC_PER_SEC;
5901                 break;
5902         default:
5903                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5904                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5905                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5906                                 << 32;
5907         }
5908
5909         return rx_tstamp_cycles;
5910 }
5911
5912 static uint64_t
5913 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5914 {
5915         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5916         uint64_t tx_tstamp_cycles;
5917
5918         switch (hw->mac.type) {
5919         case ixgbe_mac_X550:
5920         case ixgbe_mac_X550EM_x:
5921         case ixgbe_mac_X550EM_a:
5922                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5923                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5924                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5925                                 * NSEC_PER_SEC;
5926                 break;
5927         default:
5928                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5929                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5930                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5931                                 << 32;
5932         }
5933
5934         return tx_tstamp_cycles;
5935 }
5936
5937 static void
5938 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5939 {
5940         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5941         struct ixgbe_adapter *adapter =
5942                 (struct ixgbe_adapter *)dev->data->dev_private;
5943         struct rte_eth_link link;
5944         uint32_t incval = 0;
5945         uint32_t shift = 0;
5946
5947         /* Get current link speed. */
5948         memset(&link, 0, sizeof(link));
5949         ixgbe_dev_link_update(dev, 1);
5950         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5951
5952         switch (link.link_speed) {
5953         case ETH_SPEED_NUM_100M:
5954                 incval = IXGBE_INCVAL_100;
5955                 shift = IXGBE_INCVAL_SHIFT_100;
5956                 break;
5957         case ETH_SPEED_NUM_1G:
5958                 incval = IXGBE_INCVAL_1GB;
5959                 shift = IXGBE_INCVAL_SHIFT_1GB;
5960                 break;
5961         case ETH_SPEED_NUM_10G:
5962         default:
5963                 incval = IXGBE_INCVAL_10GB;
5964                 shift = IXGBE_INCVAL_SHIFT_10GB;
5965                 break;
5966         }
5967
5968         switch (hw->mac.type) {
5969         case ixgbe_mac_X550:
5970         case ixgbe_mac_X550EM_x:
5971         case ixgbe_mac_X550EM_a:
5972                 /* Independent of link speed. */
5973                 incval = 1;
5974                 /* Cycles read will be interpreted as ns. */
5975                 shift = 0;
5976                 /* Fall-through */
5977         case ixgbe_mac_X540:
5978                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5979                 break;
5980         case ixgbe_mac_82599EB:
5981                 incval >>= IXGBE_INCVAL_SHIFT_82599;
5982                 shift -= IXGBE_INCVAL_SHIFT_82599;
5983                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5984                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5985                 break;
5986         default:
5987                 /* Not supported. */
5988                 return;
5989         }
5990
5991         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5992         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5993         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5994
5995         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5996         adapter->systime_tc.cc_shift = shift;
5997         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5998
5999         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6000         adapter->rx_tstamp_tc.cc_shift = shift;
6001         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6002
6003         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6004         adapter->tx_tstamp_tc.cc_shift = shift;
6005         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6006 }
6007
6008 static int
6009 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6010 {
6011         struct ixgbe_adapter *adapter =
6012                         (struct ixgbe_adapter *)dev->data->dev_private;
6013
6014         adapter->systime_tc.nsec += delta;
6015         adapter->rx_tstamp_tc.nsec += delta;
6016         adapter->tx_tstamp_tc.nsec += delta;
6017
6018         return 0;
6019 }
6020
6021 static int
6022 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6023 {
6024         uint64_t ns;
6025         struct ixgbe_adapter *adapter =
6026                         (struct ixgbe_adapter *)dev->data->dev_private;
6027
6028         ns = rte_timespec_to_ns(ts);
6029         /* Set the timecounters to a new value. */
6030         adapter->systime_tc.nsec = ns;
6031         adapter->rx_tstamp_tc.nsec = ns;
6032         adapter->tx_tstamp_tc.nsec = ns;
6033
6034         return 0;
6035 }
6036
6037 static int
6038 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6039 {
6040         uint64_t ns, systime_cycles;
6041         struct ixgbe_adapter *adapter =
6042                         (struct ixgbe_adapter *)dev->data->dev_private;
6043
6044         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6045         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6046         *ts = rte_ns_to_timespec(ns);
6047
6048         return 0;
6049 }
6050
6051 static int
6052 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6053 {
6054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6055         uint32_t tsync_ctl;
6056         uint32_t tsauxc;
6057
6058         /* Stop the timesync system time. */
6059         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6060         /* Reset the timesync system time value. */
6061         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6062         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6063
6064         /* Enable system time for platforms where it isn't on by default. */
6065         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6066         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6067         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6068
6069         ixgbe_start_timecounters(dev);
6070
6071         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6072         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6073                         (ETHER_TYPE_1588 |
6074                          IXGBE_ETQF_FILTER_EN |
6075                          IXGBE_ETQF_1588));
6076
6077         /* Enable timestamping of received PTP packets. */
6078         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6079         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6080         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6081
6082         /* Enable timestamping of transmitted PTP packets. */
6083         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6084         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6085         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6086
6087         IXGBE_WRITE_FLUSH(hw);
6088
6089         return 0;
6090 }
6091
6092 static int
6093 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6094 {
6095         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6096         uint32_t tsync_ctl;
6097
6098         /* Disable timestamping of transmitted PTP packets. */
6099         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6100         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6101         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6102
6103         /* Disable timestamping of received PTP packets. */
6104         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6105         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6106         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6107
6108         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6109         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6110
6111         /* Stop incrementating the System Time registers. */
6112         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6113
6114         return 0;
6115 }
6116
6117 static int
6118 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6119                                  struct timespec *timestamp,
6120                                  uint32_t flags __rte_unused)
6121 {
6122         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6123         struct ixgbe_adapter *adapter =
6124                 (struct ixgbe_adapter *)dev->data->dev_private;
6125         uint32_t tsync_rxctl;
6126         uint64_t rx_tstamp_cycles;
6127         uint64_t ns;
6128
6129         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6130         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6131                 return -EINVAL;
6132
6133         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6134         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6135         *timestamp = rte_ns_to_timespec(ns);
6136
6137         return  0;
6138 }
6139
6140 static int
6141 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6142                                  struct timespec *timestamp)
6143 {
6144         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6145         struct ixgbe_adapter *adapter =
6146                 (struct ixgbe_adapter *)dev->data->dev_private;
6147         uint32_t tsync_txctl;
6148         uint64_t tx_tstamp_cycles;
6149         uint64_t ns;
6150
6151         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6152         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6153                 return -EINVAL;
6154
6155         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6156         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6157         *timestamp = rte_ns_to_timespec(ns);
6158
6159         return 0;
6160 }
6161
6162 static int
6163 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6164 {
6165         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6166         int count = 0;
6167         int g_ind = 0;
6168         const struct reg_info *reg_group;
6169         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6170                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6171
6172         while ((reg_group = reg_set[g_ind++]))
6173                 count += ixgbe_regs_group_count(reg_group);
6174
6175         return count;
6176 }
6177
6178 static int
6179 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6180 {
6181         int count = 0;
6182         int g_ind = 0;
6183         const struct reg_info *reg_group;
6184
6185         while ((reg_group = ixgbevf_regs[g_ind++]))
6186                 count += ixgbe_regs_group_count(reg_group);
6187
6188         return count;
6189 }
6190
6191 static int
6192 ixgbe_get_regs(struct rte_eth_dev *dev,
6193               struct rte_dev_reg_info *regs)
6194 {
6195         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6196         uint32_t *data = regs->data;
6197         int g_ind = 0;
6198         int count = 0;
6199         const struct reg_info *reg_group;
6200         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6201                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6202
6203         /* Support only full register dump */
6204         if ((regs->length == 0) ||
6205             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6206                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6207                         hw->device_id;
6208                 while ((reg_group = reg_set[g_ind++]))
6209                         count += ixgbe_read_regs_group(dev, &data[count],
6210                                 reg_group);
6211                 return 0;
6212         }
6213
6214         return -ENOTSUP;
6215 }
6216
6217 static int
6218 ixgbevf_get_regs(struct rte_eth_dev *dev,
6219                 struct rte_dev_reg_info *regs)
6220 {
6221         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6222         uint32_t *data = regs->data;
6223         int g_ind = 0;
6224         int count = 0;
6225         const struct reg_info *reg_group;
6226
6227         /* Support only full register dump */
6228         if ((regs->length == 0) ||
6229             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6230                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6231                         hw->device_id;
6232                 while ((reg_group = ixgbevf_regs[g_ind++]))
6233                         count += ixgbe_read_regs_group(dev, &data[count],
6234                                                       reg_group);
6235                 return 0;
6236         }
6237
6238         return -ENOTSUP;
6239 }
6240
6241 static int
6242 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6243 {
6244         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6245
6246         /* Return unit is byte count */
6247         return hw->eeprom.word_size * 2;
6248 }
6249
6250 static int
6251 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6252                 struct rte_dev_eeprom_info *in_eeprom)
6253 {
6254         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6255         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6256         uint16_t *data = in_eeprom->data;
6257         int first, length;
6258
6259         first = in_eeprom->offset >> 1;
6260         length = in_eeprom->length >> 1;
6261         if ((first > hw->eeprom.word_size) ||
6262             ((first + length) > hw->eeprom.word_size))
6263                 return -EINVAL;
6264
6265         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6266
6267         return eeprom->ops.read_buffer(hw, first, length, data);
6268 }
6269
6270 static int
6271 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6272                 struct rte_dev_eeprom_info *in_eeprom)
6273 {
6274         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6275         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6276         uint16_t *data = in_eeprom->data;
6277         int first, length;
6278
6279         first = in_eeprom->offset >> 1;
6280         length = in_eeprom->length >> 1;
6281         if ((first > hw->eeprom.word_size) ||
6282             ((first + length) > hw->eeprom.word_size))
6283                 return -EINVAL;
6284
6285         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6286
6287         return eeprom->ops.write_buffer(hw,  first, length, data);
6288 }
6289
6290 uint16_t
6291 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6292         switch (mac_type) {
6293         case ixgbe_mac_X550:
6294         case ixgbe_mac_X550EM_x:
6295         case ixgbe_mac_X550EM_a:
6296                 return ETH_RSS_RETA_SIZE_512;
6297         case ixgbe_mac_X550_vf:
6298         case ixgbe_mac_X550EM_x_vf:
6299         case ixgbe_mac_X550EM_a_vf:
6300                 return ETH_RSS_RETA_SIZE_64;
6301         default:
6302                 return ETH_RSS_RETA_SIZE_128;
6303         }
6304 }
6305
6306 uint32_t
6307 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6308         switch (mac_type) {
6309         case ixgbe_mac_X550:
6310         case ixgbe_mac_X550EM_x:
6311         case ixgbe_mac_X550EM_a:
6312                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6313                         return IXGBE_RETA(reta_idx >> 2);
6314                 else
6315                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6316         case ixgbe_mac_X550_vf:
6317         case ixgbe_mac_X550EM_x_vf:
6318         case ixgbe_mac_X550EM_a_vf:
6319                 return IXGBE_VFRETA(reta_idx >> 2);
6320         default:
6321                 return IXGBE_RETA(reta_idx >> 2);
6322         }
6323 }
6324
6325 uint32_t
6326 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6327         switch (mac_type) {
6328         case ixgbe_mac_X550_vf:
6329         case ixgbe_mac_X550EM_x_vf:
6330         case ixgbe_mac_X550EM_a_vf:
6331                 return IXGBE_VFMRQC;
6332         default:
6333                 return IXGBE_MRQC;
6334         }
6335 }
6336
6337 uint32_t
6338 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6339         switch (mac_type) {
6340         case ixgbe_mac_X550_vf:
6341         case ixgbe_mac_X550EM_x_vf:
6342         case ixgbe_mac_X550EM_a_vf:
6343                 return IXGBE_VFRSSRK(i);
6344         default:
6345                 return IXGBE_RSSRK(i);
6346         }
6347 }
6348
6349 bool
6350 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6351         switch (mac_type) {
6352         case ixgbe_mac_82599_vf:
6353         case ixgbe_mac_X540_vf:
6354                 return 0;
6355         default:
6356                 return 1;
6357         }
6358 }
6359
6360 static int
6361 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6362                         struct rte_eth_dcb_info *dcb_info)
6363 {
6364         struct ixgbe_dcb_config *dcb_config =
6365                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6366         struct ixgbe_dcb_tc_config *tc;
6367         uint8_t i, j;
6368
6369         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6370                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6371         else
6372                 dcb_info->nb_tcs = 1;
6373
6374         if (dcb_config->vt_mode) { /* vt is enabled*/
6375                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6376                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6377                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6378                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6379                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6380                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6381                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6382                                                 i * dcb_info->nb_tcs + j;
6383                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6384                                 dcb_info->tc_queue.tc_txq[i][j].base =
6385                                                 i * dcb_info->nb_tcs + j;
6386                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6387                         }
6388                 }
6389         } else { /* vt is disabled*/
6390                 struct rte_eth_dcb_rx_conf *rx_conf =
6391                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6392                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6393                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6394                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6395                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6396                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6397                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6398                         }
6399                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6400                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6401                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6402                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6403                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6404                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6405                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6406                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6407                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6408                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6409                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6410                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6411                         }
6412                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6413                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6414                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6415                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6416                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6417                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6418                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6419                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6420                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6421                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6422                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6423                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6424                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6425                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6426                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6427                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6428                 }
6429         }
6430         for (i = 0; i < dcb_info->nb_tcs; i++) {
6431                 tc = &dcb_config->tc_config[i];
6432                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6433         }
6434         return 0;
6435 }
6436
6437 /* Update e-tag ether type */
6438 static int
6439 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6440                             uint16_t ether_type)
6441 {
6442         uint32_t etag_etype;
6443
6444         if (hw->mac.type != ixgbe_mac_X550 &&
6445             hw->mac.type != ixgbe_mac_X550EM_x &&
6446             hw->mac.type != ixgbe_mac_X550EM_a) {
6447                 return -ENOTSUP;
6448         }
6449
6450         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6451         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6452         etag_etype |= ether_type;
6453         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6454         IXGBE_WRITE_FLUSH(hw);
6455
6456         return 0;
6457 }
6458
6459 /* Config l2 tunnel ether type */
6460 static int
6461 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6462                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6463 {
6464         int ret = 0;
6465         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6466
6467         if (l2_tunnel == NULL)
6468                 return -EINVAL;
6469
6470         switch (l2_tunnel->l2_tunnel_type) {
6471         case RTE_L2_TUNNEL_TYPE_E_TAG:
6472                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6473                 break;
6474         default:
6475                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6476                 ret = -EINVAL;
6477                 break;
6478         }
6479
6480         return ret;
6481 }
6482
6483 /* Enable e-tag tunnel */
6484 static int
6485 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6486 {
6487         uint32_t etag_etype;
6488
6489         if (hw->mac.type != ixgbe_mac_X550 &&
6490             hw->mac.type != ixgbe_mac_X550EM_x &&
6491             hw->mac.type != ixgbe_mac_X550EM_a) {
6492                 return -ENOTSUP;
6493         }
6494
6495         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6496         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6497         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6498         IXGBE_WRITE_FLUSH(hw);
6499
6500         return 0;
6501 }
6502
6503 /* Enable l2 tunnel */
6504 static int
6505 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6506                            enum rte_eth_tunnel_type l2_tunnel_type)
6507 {
6508         int ret = 0;
6509         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6510
6511         switch (l2_tunnel_type) {
6512         case RTE_L2_TUNNEL_TYPE_E_TAG:
6513                 ret = ixgbe_e_tag_enable(hw);
6514                 break;
6515         default:
6516                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6517                 ret = -EINVAL;
6518                 break;
6519         }
6520
6521         return ret;
6522 }
6523
6524 /* Disable e-tag tunnel */
6525 static int
6526 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6527 {
6528         uint32_t etag_etype;
6529
6530         if (hw->mac.type != ixgbe_mac_X550 &&
6531             hw->mac.type != ixgbe_mac_X550EM_x &&
6532             hw->mac.type != ixgbe_mac_X550EM_a) {
6533                 return -ENOTSUP;
6534         }
6535
6536         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6537         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6538         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6539         IXGBE_WRITE_FLUSH(hw);
6540
6541         return 0;
6542 }
6543
6544 /* Disable l2 tunnel */
6545 static int
6546 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6547                             enum rte_eth_tunnel_type l2_tunnel_type)
6548 {
6549         int ret = 0;
6550         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6551
6552         switch (l2_tunnel_type) {
6553         case RTE_L2_TUNNEL_TYPE_E_TAG:
6554                 ret = ixgbe_e_tag_disable(hw);
6555                 break;
6556         default:
6557                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6558                 ret = -EINVAL;
6559                 break;
6560         }
6561
6562         return ret;
6563 }
6564
6565 static int
6566 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6567                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6568 {
6569         int ret = 0;
6570         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6571         uint32_t i, rar_entries;
6572         uint32_t rar_low, rar_high;
6573
6574         if (hw->mac.type != ixgbe_mac_X550 &&
6575             hw->mac.type != ixgbe_mac_X550EM_x &&
6576             hw->mac.type != ixgbe_mac_X550EM_a) {
6577                 return -ENOTSUP;
6578         }
6579
6580         rar_entries = ixgbe_get_num_rx_addrs(hw);
6581
6582         for (i = 1; i < rar_entries; i++) {
6583                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6584                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6585                 if ((rar_high & IXGBE_RAH_AV) &&
6586                     (rar_high & IXGBE_RAH_ADTYPE) &&
6587                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6588                      l2_tunnel->tunnel_id)) {
6589                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6590                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6591
6592                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6593
6594                         return ret;
6595                 }
6596         }
6597
6598         return ret;
6599 }
6600
6601 static int
6602 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6603                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6604 {
6605         int ret = 0;
6606         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6607         uint32_t i, rar_entries;
6608         uint32_t rar_low, rar_high;
6609
6610         if (hw->mac.type != ixgbe_mac_X550 &&
6611             hw->mac.type != ixgbe_mac_X550EM_x &&
6612             hw->mac.type != ixgbe_mac_X550EM_a) {
6613                 return -ENOTSUP;
6614         }
6615
6616         /* One entry for one tunnel. Try to remove potential existing entry. */
6617         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6618
6619         rar_entries = ixgbe_get_num_rx_addrs(hw);
6620
6621         for (i = 1; i < rar_entries; i++) {
6622                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6623                 if (rar_high & IXGBE_RAH_AV) {
6624                         continue;
6625                 } else {
6626                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6627                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6628                         rar_low = l2_tunnel->tunnel_id;
6629
6630                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6631                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6632
6633                         return ret;
6634                 }
6635         }
6636
6637         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6638                      " Please remove a rule before adding a new one.");
6639         return -EINVAL;
6640 }
6641
6642 /* Add l2 tunnel filter */
6643 static int
6644 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6645                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6646 {
6647         int ret = 0;
6648
6649         switch (l2_tunnel->l2_tunnel_type) {
6650         case RTE_L2_TUNNEL_TYPE_E_TAG:
6651                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6652                 break;
6653         default:
6654                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6655                 ret = -EINVAL;
6656                 break;
6657         }
6658
6659         return ret;
6660 }
6661
6662 /* Delete l2 tunnel filter */
6663 static int
6664 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6665                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6666 {
6667         int ret = 0;
6668
6669         switch (l2_tunnel->l2_tunnel_type) {
6670         case RTE_L2_TUNNEL_TYPE_E_TAG:
6671                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6672                 break;
6673         default:
6674                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6675                 ret = -EINVAL;
6676                 break;
6677         }
6678
6679         return ret;
6680 }
6681
6682 /**
6683  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6684  * @dev: pointer to rte_eth_dev structure
6685  * @filter_op:operation will be taken.
6686  * @arg: a pointer to specific structure corresponding to the filter_op
6687  */
6688 static int
6689 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6690                                   enum rte_filter_op filter_op,
6691                                   void *arg)
6692 {
6693         int ret = 0;
6694
6695         if (filter_op == RTE_ETH_FILTER_NOP)
6696                 return 0;
6697
6698         if (arg == NULL) {
6699                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6700                             filter_op);
6701                 return -EINVAL;
6702         }
6703
6704         switch (filter_op) {
6705         case RTE_ETH_FILTER_ADD:
6706                 ret = ixgbe_dev_l2_tunnel_filter_add
6707                         (dev,
6708                          (struct rte_eth_l2_tunnel_conf *)arg);
6709                 break;
6710         case RTE_ETH_FILTER_DELETE:
6711                 ret = ixgbe_dev_l2_tunnel_filter_del
6712                         (dev,
6713                          (struct rte_eth_l2_tunnel_conf *)arg);
6714                 break;
6715         default:
6716                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6717                 ret = -EINVAL;
6718                 break;
6719         }
6720         return ret;
6721 }
6722
6723 static int
6724 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6725 {
6726         int ret = 0;
6727         uint32_t ctrl;
6728         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6729
6730         if (hw->mac.type != ixgbe_mac_X550 &&
6731             hw->mac.type != ixgbe_mac_X550EM_x &&
6732             hw->mac.type != ixgbe_mac_X550EM_a) {
6733                 return -ENOTSUP;
6734         }
6735
6736         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6737         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6738         if (en)
6739                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6740         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6741
6742         return ret;
6743 }
6744
6745 /* Enable l2 tunnel forwarding */
6746 static int
6747 ixgbe_dev_l2_tunnel_forwarding_enable
6748         (struct rte_eth_dev *dev,
6749          enum rte_eth_tunnel_type l2_tunnel_type)
6750 {
6751         int ret = 0;
6752
6753         switch (l2_tunnel_type) {
6754         case RTE_L2_TUNNEL_TYPE_E_TAG:
6755                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6756                 break;
6757         default:
6758                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6759                 ret = -EINVAL;
6760                 break;
6761         }
6762
6763         return ret;
6764 }
6765
6766 /* Disable l2 tunnel forwarding */
6767 static int
6768 ixgbe_dev_l2_tunnel_forwarding_disable
6769         (struct rte_eth_dev *dev,
6770          enum rte_eth_tunnel_type l2_tunnel_type)
6771 {
6772         int ret = 0;
6773
6774         switch (l2_tunnel_type) {
6775         case RTE_L2_TUNNEL_TYPE_E_TAG:
6776                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6777                 break;
6778         default:
6779                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6780                 ret = -EINVAL;
6781                 break;
6782         }
6783
6784         return ret;
6785 }
6786
6787 static int
6788 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6789                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6790                              bool en)
6791 {
6792         int ret = 0;
6793         uint32_t vmtir, vmvir;
6794         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6795
6796         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6797                 PMD_DRV_LOG(ERR,
6798                             "VF id %u should be less than %u",
6799                             l2_tunnel->vf_id,
6800                             dev->pci_dev->max_vfs);
6801                 return -EINVAL;
6802         }
6803
6804         if (hw->mac.type != ixgbe_mac_X550 &&
6805             hw->mac.type != ixgbe_mac_X550EM_x &&
6806             hw->mac.type != ixgbe_mac_X550EM_a) {
6807                 return -ENOTSUP;
6808         }
6809
6810         if (en)
6811                 vmtir = l2_tunnel->tunnel_id;
6812         else
6813                 vmtir = 0;
6814
6815         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6816
6817         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6818         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6819         if (en)
6820                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6821         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6822
6823         return ret;
6824 }
6825
6826 /* Enable l2 tunnel tag insertion */
6827 static int
6828 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6829                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6830 {
6831         int ret = 0;
6832
6833         switch (l2_tunnel->l2_tunnel_type) {
6834         case RTE_L2_TUNNEL_TYPE_E_TAG:
6835                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6836                 break;
6837         default:
6838                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6839                 ret = -EINVAL;
6840                 break;
6841         }
6842
6843         return ret;
6844 }
6845
6846 /* Disable l2 tunnel tag insertion */
6847 static int
6848 ixgbe_dev_l2_tunnel_insertion_disable
6849         (struct rte_eth_dev *dev,
6850          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6851 {
6852         int ret = 0;
6853
6854         switch (l2_tunnel->l2_tunnel_type) {
6855         case RTE_L2_TUNNEL_TYPE_E_TAG:
6856                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6857                 break;
6858         default:
6859                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6860                 ret = -EINVAL;
6861                 break;
6862         }
6863
6864         return ret;
6865 }
6866
6867 static int
6868 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6869                              bool en)
6870 {
6871         int ret = 0;
6872         uint32_t qde;
6873         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6874
6875         if (hw->mac.type != ixgbe_mac_X550 &&
6876             hw->mac.type != ixgbe_mac_X550EM_x &&
6877             hw->mac.type != ixgbe_mac_X550EM_a) {
6878                 return -ENOTSUP;
6879         }
6880
6881         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6882         if (en)
6883                 qde |= IXGBE_QDE_STRIP_TAG;
6884         else
6885                 qde &= ~IXGBE_QDE_STRIP_TAG;
6886         qde &= ~IXGBE_QDE_READ;
6887         qde |= IXGBE_QDE_WRITE;
6888         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6889
6890         return ret;
6891 }
6892
6893 /* Enable l2 tunnel tag stripping */
6894 static int
6895 ixgbe_dev_l2_tunnel_stripping_enable
6896         (struct rte_eth_dev *dev,
6897          enum rte_eth_tunnel_type l2_tunnel_type)
6898 {
6899         int ret = 0;
6900
6901         switch (l2_tunnel_type) {
6902         case RTE_L2_TUNNEL_TYPE_E_TAG:
6903                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6904                 break;
6905         default:
6906                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6907                 ret = -EINVAL;
6908                 break;
6909         }
6910
6911         return ret;
6912 }
6913
6914 /* Disable l2 tunnel tag stripping */
6915 static int
6916 ixgbe_dev_l2_tunnel_stripping_disable
6917         (struct rte_eth_dev *dev,
6918          enum rte_eth_tunnel_type l2_tunnel_type)
6919 {
6920         int ret = 0;
6921
6922         switch (l2_tunnel_type) {
6923         case RTE_L2_TUNNEL_TYPE_E_TAG:
6924                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6925                 break;
6926         default:
6927                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6928                 ret = -EINVAL;
6929                 break;
6930         }
6931
6932         return ret;
6933 }
6934
6935 /* Enable/disable l2 tunnel offload functions */
6936 static int
6937 ixgbe_dev_l2_tunnel_offload_set
6938         (struct rte_eth_dev *dev,
6939          struct rte_eth_l2_tunnel_conf *l2_tunnel,
6940          uint32_t mask,
6941          uint8_t en)
6942 {
6943         int ret = 0;
6944
6945         if (l2_tunnel == NULL)
6946                 return -EINVAL;
6947
6948         ret = -EINVAL;
6949         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6950                 if (en)
6951                         ret = ixgbe_dev_l2_tunnel_enable(
6952                                 dev,
6953                                 l2_tunnel->l2_tunnel_type);
6954                 else
6955                         ret = ixgbe_dev_l2_tunnel_disable(
6956                                 dev,
6957                                 l2_tunnel->l2_tunnel_type);
6958         }
6959
6960         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6961                 if (en)
6962                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
6963                                 dev,
6964                                 l2_tunnel);
6965                 else
6966                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
6967                                 dev,
6968                                 l2_tunnel);
6969         }
6970
6971         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6972                 if (en)
6973                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
6974                                 dev,
6975                                 l2_tunnel->l2_tunnel_type);
6976                 else
6977                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
6978                                 dev,
6979                                 l2_tunnel->l2_tunnel_type);
6980         }
6981
6982         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6983                 if (en)
6984                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6985                                 dev,
6986                                 l2_tunnel->l2_tunnel_type);
6987                 else
6988                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6989                                 dev,
6990                                 l2_tunnel->l2_tunnel_type);
6991         }
6992
6993         return ret;
6994 }
6995
6996 static int
6997 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6998                         uint16_t port)
6999 {
7000         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7001         IXGBE_WRITE_FLUSH(hw);
7002
7003         return 0;
7004 }
7005
7006 /* There's only one register for VxLAN UDP port.
7007  * So, we cannot add several ports. Will update it.
7008  */
7009 static int
7010 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7011                      uint16_t port)
7012 {
7013         if (port == 0) {
7014                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7015                 return -EINVAL;
7016         }
7017
7018         return ixgbe_update_vxlan_port(hw, port);
7019 }
7020
7021 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7022  * UDP port, it must have a value.
7023  * So, will reset it to the original value 0.
7024  */
7025 static int
7026 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7027                      uint16_t port)
7028 {
7029         uint16_t cur_port;
7030
7031         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7032
7033         if (cur_port != port) {
7034                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7035                 return -EINVAL;
7036         }
7037
7038         return ixgbe_update_vxlan_port(hw, 0);
7039 }
7040
7041 /* Add UDP tunneling port */
7042 static int
7043 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7044                               struct rte_eth_udp_tunnel *udp_tunnel)
7045 {
7046         int ret = 0;
7047         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7048
7049         if (hw->mac.type != ixgbe_mac_X550 &&
7050             hw->mac.type != ixgbe_mac_X550EM_x &&
7051             hw->mac.type != ixgbe_mac_X550EM_a) {
7052                 return -ENOTSUP;
7053         }
7054
7055         if (udp_tunnel == NULL)
7056                 return -EINVAL;
7057
7058         switch (udp_tunnel->prot_type) {
7059         case RTE_TUNNEL_TYPE_VXLAN:
7060                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7061                 break;
7062
7063         case RTE_TUNNEL_TYPE_GENEVE:
7064         case RTE_TUNNEL_TYPE_TEREDO:
7065                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7066                 ret = -EINVAL;
7067                 break;
7068
7069         default:
7070                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7071                 ret = -EINVAL;
7072                 break;
7073         }
7074
7075         return ret;
7076 }
7077
7078 /* Remove UDP tunneling port */
7079 static int
7080 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7081                               struct rte_eth_udp_tunnel *udp_tunnel)
7082 {
7083         int ret = 0;
7084         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7085
7086         if (hw->mac.type != ixgbe_mac_X550 &&
7087             hw->mac.type != ixgbe_mac_X550EM_x &&
7088             hw->mac.type != ixgbe_mac_X550EM_a) {
7089                 return -ENOTSUP;
7090         }
7091
7092         if (udp_tunnel == NULL)
7093                 return -EINVAL;
7094
7095         switch (udp_tunnel->prot_type) {
7096         case RTE_TUNNEL_TYPE_VXLAN:
7097                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7098                 break;
7099         case RTE_TUNNEL_TYPE_GENEVE:
7100         case RTE_TUNNEL_TYPE_TEREDO:
7101                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7102                 ret = -EINVAL;
7103                 break;
7104         default:
7105                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7106                 ret = -EINVAL;
7107                 break;
7108         }
7109
7110         return ret;
7111 }
7112
7113 /* ixgbevf_update_xcast_mode - Update Multicast mode
7114  * @hw: pointer to the HW structure
7115  * @netdev: pointer to net device structure
7116  * @xcast_mode: new multicast mode
7117  *
7118  * Updates the Multicast Mode of VF.
7119  */
7120 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
7121                                      int xcast_mode)
7122 {
7123         struct ixgbe_mbx_info *mbx = &hw->mbx;
7124         u32 msgbuf[2];
7125         s32 err;
7126
7127         switch (hw->api_version) {
7128         case ixgbe_mbox_api_12:
7129                 break;
7130         default:
7131                 return -EOPNOTSUPP;
7132         }
7133
7134         msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7135         msgbuf[1] = xcast_mode;
7136
7137         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7138         if (err)
7139                 return err;
7140
7141         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7142         if (err)
7143                 return err;
7144
7145         msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7146         if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7147                 return -EPERM;
7148
7149         return 0;
7150 }
7151
7152 static void
7153 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7154 {
7155         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7156
7157         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7158 }
7159
7160 static void
7161 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7162 {
7163         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7164
7165         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7166 }
7167
7168 static struct rte_driver rte_ixgbe_driver = {
7169         .type = PMD_PDEV,
7170         .init = rte_ixgbe_pmd_init,
7171 };
7172
7173 static struct rte_driver rte_ixgbevf_driver = {
7174         .type = PMD_PDEV,
7175         .init = rte_ixgbevf_pmd_init,
7176 };
7177
7178 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7179 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);